34 lines
2.0 KiB
Plaintext
34 lines
2.0 KiB
Plaintext
// File: STM32F100.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F100xx Reference manual (RM0041)
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// STM32F100xx datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <i> Reserved bits must be kept at reset value
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// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.24> DBG_TIM17_STOP <i> TIM17 counter stopped when core is halted
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// <o.23> DBG_TIM16_STOP <i> TIM16 counter stopped when core is halted
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// <o.22> DBG_TIM15_STOP <i> TIM15 counter stopped when core is halted
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// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
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// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// <o.0> DBG_SLEEP <i> Debug sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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