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IAPV1.1/Driver/ENC28J602/enc28j60.c
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IAPV1.1/Driver/ENC28J602/enc28j60.c
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#include "spi.h"
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//#include "delay.h"
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//#include "timerx.h"
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#include <stdio.h>
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#include "enc28j60.h"
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//////////////////////////////////////////////////////////////////////////////////
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//ALIENTEKս<4B><D5BD>STM32<33><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//ENC28J60<36><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
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//<2F><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>:2012/9/28
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//<2F>汾<EFBFBD><E6B1BE>V1.0
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//////////////////////////////////////////////////////////////////////////////////
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static u8 ENC28J60BANK;
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static u32 NextPacketPtr;
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//<2F><>λENC28J60
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//<2F><><EFBFBD><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC>/IO<49><4F>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
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static void ENC28J60_SPI2_Init(void)
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{
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// SPI_InitTypeDef SPI_InitStructure;
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// GPIO_InitTypeDef GPIO_InitStructure;
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// RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );//SPI2ʱ<32><CAB1>ʹ<EFBFBD><CAB9>
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// RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOG, ENABLE );//PORTB,D,Gʱ<47><CAB1>ʹ<EFBFBD><CAB9>
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; // <20>˿<EFBFBD><CBBF><EFBFBD><EFBFBD><EFBFBD>
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //IO<49><4F><EFBFBD>ٶ<EFBFBD>Ϊ50MHz
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// GPIO_Init(GPIOD, &GPIO_InitStructure); //<2F><><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>GPIOD.2
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// GPIO_SetBits(GPIOD,GPIO_Pin_2); //PD.2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//
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// //<2F><><EFBFBD><EFBFBD>PG7<47><37>PB12<31><32><EFBFBD><EFBFBD>,<2C><>Ϊ<EFBFBD>˷<EFBFBD>ֹNRF24L01<30><31>SPI FLASHӰ<48><D3B0>.
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// //<2F><>Ϊ<EFBFBD><CEAA><EFBFBD>ǹ<EFBFBD><C7B9><EFBFBD>һ<EFBFBD><D2BB>SPI<50><49>.
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; // PB12 <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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// GPIO_Init(GPIOB, &GPIO_InitStructure); //<2F><><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>GPIOB.12
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// GPIO_SetBits(GPIOB,GPIO_Pin_12); //PB.12<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7|GPIO_Pin_8;//PG6/7/8 <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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// GPIO_Init(GPIOG, &GPIO_InitStructure); //<2F><><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>//PG6/7/8
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// GPIO_SetBits(GPIOG,GPIO_Pin_6|GPIO_Pin_7|GPIO_Pin_8);//PG6/7/8<><38><EFBFBD><EFBFBD>
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //PB13/14/15<31><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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// GPIO_Init(GPIOB, &GPIO_InitStructure);//<2F><>ʼ<EFBFBD><CABC>GPIOB
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// GPIO_SetBits(GPIOB,GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15); //PB13/14/15<31><35><EFBFBD><EFBFBD>
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// SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; //<2F><><EFBFBD><EFBFBD>SPI<50><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˫<EFBFBD><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ:SPI<50><49><EFBFBD><EFBFBD>Ϊ˫<CEAA><CBAB>˫<EFBFBD><CBAB>ȫ˫<C8AB><CBAB>
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// SPI_InitStructure.SPI_Mode = SPI_Mode_Master; //<2F><><EFBFBD><EFBFBD>SPI<50><49><EFBFBD><EFBFBD>ģʽ:<3A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>SPI
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// SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; //<2F><><EFBFBD><EFBFBD>SPI<50><49><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С:SPI<50><49><EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD>8λ֡<CEBB>ṹ
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// SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; //<2F><><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ʱ<EFBFBD>ӵĿ<D3B5><C4BF><EFBFBD>״̬Ϊ<CCAC>͵<EFBFBD>ƽ
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// SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; //<2F><><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ʱ<EFBFBD>ӵĵ<D3B5>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD><D8A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>
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// SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; //NSS<53>ź<EFBFBD><C5BA><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>NSS<53>ܽţ<DCBD><C5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>SSIλ<49><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A>ڲ<EFBFBD>NSS<53>ź<EFBFBD><C5BA><EFBFBD>SSIλ<49><CEBB><EFBFBD><EFBFBD>
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// SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; //<2F><><EFBFBD>岨<EFBFBD><E5B2A8><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4>Ƶ<EFBFBD><C6B5>ֵ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4>ƵֵΪ256
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// SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; //ָ<><D6B8><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD>MSBλ<42><CEBB><EFBFBD><EFBFBD>LSBλ<42><CEBB>ʼ:<3A><><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD>MSBλ<42><CEBB>ʼ
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// SPI_InitStructure.SPI_CRCPolynomial = 7; //CRCֵ<43><D6B5><EFBFBD><EFBFBD><EFBFBD>Ķ<EFBFBD><C4B6><EFBFBD>ʽ
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// SPI_Init(SPI2, &SPI_InitStructure); //<2F><><EFBFBD><EFBFBD>SPI_InitStruct<63><74>ָ<EFBFBD><D6B8><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPIx<49>Ĵ<EFBFBD><C4B4><EFBFBD>
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//
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// SPI_Cmd(SPI2, ENABLE); //ʹ<><CAB9>SPI<50><49><EFBFBD><EFBFBD>
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//
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// SPI2_ReadWriteByte(0xff);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}
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void ENC28J60_Reset(void)
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{
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// ENC28J60_SPI2_Init();//SPI2<49><32>ʼ<EFBFBD><CABC>
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// SPI2_SetSpeed(SPI_BaudRatePrescaler_4); //SPI2 SCKƵ<4B><C6B5>Ϊ36M/4=9Mhz
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// TIM6_Int_Init(1000,719);//100Khz<68><7A><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1000Ϊ10ms
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// ENC28J60_RST=0; //<2F><>λENC28J60
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// delay_ms(10);
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// ENC28J60_RST=1; //<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>
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// delay_ms(10);
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}
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//<2F><>ȡENC28J60<36>Ĵ<EFBFBD><C4B4><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//op<6F><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//addr:<3A>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ/<2F><><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ֵ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u8 ENC28J60_Read_Op(u8 op,u8 addr)
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{
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u8 dat=0;
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ENC28J60_CSL ;
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dat=op|(addr&ADDR_MASK);
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SPI1_ReadWrite(dat);
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dat=SPI1_ReadWrite(0xFF);
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//<2F><><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD>ȡMAC/MII<49>Ĵ<EFBFBD><C4B4><EFBFBD>,<2C><><EFBFBD>ڶ<EFBFBD><DAB6>ζ<EFBFBD><CEB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7>,<2C><><EFBFBD>ֲ<EFBFBD>29ҳ
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if(addr&0x80)dat=SPI1_ReadWrite(0xFF);
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ENC28J60_CSH;
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return dat;
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}
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//<2F><>ȡENC28J60<36>Ĵ<EFBFBD><C4B4><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//op<6F><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//addr:<3A>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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//data:<3A><><EFBFBD><EFBFBD>
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void ENC28J60_Write_Op(u8 op,u8 addr,u8 data)
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{
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u8 dat = 0;
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ENC28J60_CSL;
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dat=op|(addr&ADDR_MASK);
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SPI1_ReadWrite(dat);
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SPI1_ReadWrite(data);
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ENC28J60_CSH;
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}
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//<2F><>ȡENC28J60<36><30><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//len:Ҫ<><D2AA>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
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//data:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>(ĩβ<C4A9>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD>ӽ<EFBFBD><D3BD><EFBFBD><EFBFBD><EFBFBD>)
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void ENC28J60_Read_Buf(u32 len,u8* data)
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{
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ENC28J60_CSL;
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SPI1_ReadWrite(ENC28J60_READ_BUF_MEM);
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while(len)
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{
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len--;
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*data=(u8)SPI1_ReadWrite(0);
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data++;
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}
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*data='\0';
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ENC28J60_CSL;
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}
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//<2F><>ENC28J60д<30><D0B4><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//len:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
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//data:<3A><><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>
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void ENC28J60_Write_Buf(u32 len,u8* data)
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{
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ENC28J60_CSL;
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SPI1_ReadWrite(ENC28J60_WRITE_BUF_MEM);
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while(len)
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{
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len--;
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SPI1_ReadWrite(*data);
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data++;
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}
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ENC28J60_CSH;
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}
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//<2F><><EFBFBD><EFBFBD>ENC28J60<36>Ĵ<EFBFBD><C4B4><EFBFBD>Bank
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//ban:Ҫ<><D2AA><EFBFBD>õ<EFBFBD>bank
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void ENC28J60_Set_Bank(u8 bank)
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{
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if((bank&BANK_MASK)!=ENC28J60BANK)//<2F>͵<EFBFBD>ǰbank<6E><6B>һ<EFBFBD>µ<EFBFBD>ʱ<EFBFBD><CAB1>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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{
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ENC28J60_Write_Op(ENC28J60_BIT_FIELD_CLR,ECON1,(ECON1_BSEL1|ECON1_BSEL0));
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ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,ECON1,(bank&BANK_MASK)>>5);
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ENC28J60BANK=(bank&BANK_MASK);
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}
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}
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//<2F><>ȡENC28J60ָ<30><D6B8><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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//addr:<3A>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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//<2F><><EFBFBD><EFBFBD>ֵ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u8 ENC28J60_Read(u8 addr)
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{
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ENC28J60_Set_Bank(addr);//<2F><><EFBFBD><EFBFBD>BANK
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return ENC28J60_Read_Op(ENC28J60_READ_CTRL_REG,addr);
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}
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//<2F><>ENC28J60ָ<30><D6B8><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
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//addr:<3A>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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//data:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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void ENC28J60_Write(u8 addr,u8 data)
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{
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ENC28J60_Set_Bank(addr);
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ENC28J60_Write_Op(ENC28J60_WRITE_CTRL_REG,addr,data);
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}
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//<2F><>ENC28J60<36><30>PHY<48>Ĵ<EFBFBD><C4B4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//addr:<3A>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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//data:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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void ENC28J60_PHY_Write(u8 addr,u32 data)
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{
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u16 retry=0;
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ENC28J60_Write(MIREGADR,addr); //<2F><><EFBFBD><EFBFBD>PHY<48>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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ENC28J60_Write(MIWRL,data); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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ENC28J60_Write(MIWRH,data>>8);
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while((ENC28J60_Read(MISTAT)&MISTAT_BUSY)&&retry<0XFFF)retry++;//<2F>ȴ<EFBFBD>д<EFBFBD><D0B4>PHY<48><59><EFBFBD><EFBFBD>
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}
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//<2F><>ʼ<EFBFBD><CABC>ENC28J60
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//macaddr:MAC<41><43>ַ
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//<2F><><EFBFBD><EFBFBD>ֵ:0,<2C><>ʼ<EFBFBD><CABC><EFBFBD>ɹ<EFBFBD>;
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// 1,<2C><>ʼ<EFBFBD><CABC>ʧ<EFBFBD><CAA7>;
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u8 ENC28J60_Init(u8* macaddr)
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{
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u16 retry=0;
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ENC28J60_Reset();
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ENC28J60_Write_Op(ENC28J60_SOFT_RESET,0,ENC28J60_SOFT_RESET);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
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while(!(ENC28J60_Read(ESTAT)&ESTAT_CLKRDY)&&retry<500)//<2F>ȴ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ȶ<EFBFBD>
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{
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retry++;
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// delay_ms(1);
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};
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if(retry>=500)return 1;//ENC28J60<36><30>ʼ<EFBFBD><CABC>ʧ<EFBFBD><CAA7>
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// do bank 0 stuff
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// initialize receive buffer
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// 16-bit transfers,must write low byte first
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// set receive buffer start address <20><><EFBFBD>ý<EFBFBD><C3BD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ 8K<38>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
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NextPacketPtr=RXSTART_INIT;
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// Rx start
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//<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD>FIFO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɡ<EFBFBD>
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//<2F>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ERXSTH:ERXSTL <20><>ERXNDH:ERXNDL <20><>
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//Ϊָ<CEAA>룬<EFBFBD><EBA3AC><EFBFBD>建<EFBFBD><E5BBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ洢<DAB4><E6B4A2><EFBFBD>е<EFBFBD>λ<EFBFBD>á<EFBFBD>
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//ERXST<53><54>ERXNDָ<44><D6B8><EFBFBD><EFBFBD><EFBFBD>ֽھ<D6BD><DABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڡ<EFBFBD>
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||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̫<EFBFBD><CCAB><EFBFBD>ӿڽ<D3BF><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Щ<EFBFBD>ֽڱ<D6BD>˳<EFBFBD><CBB3>д<EFBFBD><D0B4>
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||||
//<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ǵ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ERXND ָ<><D6B8><EFBFBD>Ĵ洢<C4B4><E6B4A2>Ԫ
|
||||
//<2F><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>һ<EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ERXST ָ<><D6B8>
|
||||
//<2F>Ĵ洢<C4B4><E6B4A2>Ԫ<EFBFBD><D4AA> <20><><EFBFBD>˽<EFBFBD><CBBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>FIFO <20><><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>
|
||||
//Ԫ<><D4AA>
|
||||
//<2F><><EFBFBD>ý<EFBFBD><C3BD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ֽ<EFBFBD>
|
||||
ENC28J60_Write(ERXSTL,RXSTART_INIT&0xFF);
|
||||
ENC28J60_Write(ERXSTH,RXSTART_INIT>>8);
|
||||
//ERXWRPTH:ERXWRPTL <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>FIFO <20><>
|
||||
//<2F><><EFBFBD>ĸ<EFBFBD>λ<EFBFBD><CEBB>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ֽڡ<D6BD> ָ<><D6B8><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ģ<EFBFBD><C4A3>ڳ<EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD>롣 ָ<><D6B8><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>FIFO <20><>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD><D5BC>Ĵ<EFBFBD>С 8K-1500<30><30>
|
||||
//<2F><><EFBFBD>ý<EFBFBD><C3BD>ն<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ֽ<EFBFBD>
|
||||
ENC28J60_Write(ERXRDPTL,RXSTART_INIT&0xFF);
|
||||
ENC28J60_Write(ERXRDPTH,RXSTART_INIT>>8);
|
||||
//<2F><><EFBFBD>ý<EFBFBD><C3BD>ս<EFBFBD><D5BD><EFBFBD><EFBFBD>ֽ<EFBFBD>
|
||||
ENC28J60_Write(ERXNDL,RXSTOP_INIT&0xFF);
|
||||
ENC28J60_Write(ERXNDH,RXSTOP_INIT>>8);
|
||||
//<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ֽ<EFBFBD>
|
||||
ENC28J60_Write(ETXSTL,TXSTART_INIT&0xFF);
|
||||
ENC28J60_Write(ETXSTH,TXSTART_INIT>>8);
|
||||
//<2F><><EFBFBD>÷<EFBFBD><C3B7>ͽ<EFBFBD><CDBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
|
||||
ENC28J60_Write(ETXNDL,TXSTOP_INIT&0xFF);
|
||||
ENC28J60_Write(ETXNDH,TXSTOP_INIT>>8);
|
||||
// do bank 1 stuff,packet filter:
|
||||
// For broadcast packets we allow only ARP packtets
|
||||
// All other packets should be unicast only for our mac (MAADR)
|
||||
//
|
||||
// The pattern to match on is therefore
|
||||
// Type ETH.DST
|
||||
// ARP BROADCAST
|
||||
// 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
|
||||
// in binary these poitions are:11 0000 0011 1111
|
||||
// This is hex 303F->EPMM0=0x3f,EPMM1=0x30
|
||||
//<2F><><EFBFBD>չ<EFBFBD><D5B9><EFBFBD><EFBFBD><EFBFBD>
|
||||
//UCEN<45><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//<2F><>ANDOR = 1 ʱ<><CAB1>
|
||||
//1 = Ŀ<><C4BF><EFBFBD><EFBFBD>ַ<EFBFBD>뱾<EFBFBD><EBB1BE>MAC <20><>ַ<EFBFBD><D6B7>ƥ<EFBFBD><C6A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><>ANDOR = 0 ʱ<><CAB1>
|
||||
//1 = Ŀ<><C4BF><EFBFBD><EFBFBD>ַ<EFBFBD>뱾<EFBFBD><EBB1BE>MAC <20><>ַƥ<D6B7><C6A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0>ᱻ<EFBFBD><E1B1BB><EFBFBD><EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//CRCEN<45><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRC У<><D0A3>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD>CRC <20><>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRC <20>Ƿ<EFBFBD><C7B7><EFBFBD>Ч
|
||||
//PMEN<45><4E><EFBFBD><EFBFBD>ʽƥ<CABD><C6A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//<2F><>ANDOR = 1 ʱ<><CAB1>
|
||||
//1 = <20><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϸ<EFBFBD>ʽƥ<CABD><C6A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><F2BDABB1><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><>ANDOR = 0 ʱ<><CAB1>
|
||||
//1 = <20><><EFBFBD>ϸ<EFBFBD>ʽƥ<CABD><C6A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_Write(ERXFCON,ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
|
||||
ENC28J60_Write(EPMM0,0x3f);
|
||||
ENC28J60_Write(EPMM1,0x30);
|
||||
ENC28J60_Write(EPMCSL,0xf9);
|
||||
ENC28J60_Write(EPMCSH,0xf7);
|
||||
// do bank 2 stuff
|
||||
// enable MAC receive
|
||||
//bit 0 MARXEN<45><4E>MAC <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD>MAC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
|
||||
//bit 3 TXPAUS<55><53><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD>MAC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ˫<C8AB><CBAB>ģʽ<C4A3>µ<EFBFBD><C2B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƣ<EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9>ͣ֡<CDA3><D6A1><EFBFBD><EFBFBD>
|
||||
//bit 2 RXPAUS<55><53><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>֡ʱ<D6A1><CAB1><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><><EFBFBD>Խ<EFBFBD><D4BD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>֡
|
||||
ENC28J60_Write(MACON1,MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
|
||||
// bring MAC out of reset
|
||||
//<2F><>MACON2 <20>е<EFBFBD>MARST λ<><CEBB><EFBFBD>㣬ʹMAC <20>˳<EFBFBD><CBB3><EFBFBD>λ״̬<D7B4><CCAC>
|
||||
ENC28J60_Write(MACON2,0x00);
|
||||
// enable automatic padding to 60bytes and CRC operations
|
||||
//bit 7-5 PADCFG2:PACDFG0<47><30><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRC <20><><EFBFBD><EFBFBD>λ
|
||||
//111 = <20><>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>֡<EFBFBD><D6A1>64 <20>ֽڳ<D6BD><DAB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><D7B7>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC
|
||||
//110 = <20><><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡
|
||||
//101 = MAC <20>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8100h <20><><EFBFBD><EFBFBD><EFBFBD>ֶε<D6B6>VLAN Э<><D0AD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD>䵽64 <20>ֽڳ<D6BD><DAB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><>VLAN ֡<><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>60 <20>ֽڳ<D6BD><DAB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<D2AA><D7B7>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC
|
||||
//100 = <20><><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡
|
||||
//011 = <20><>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>֡<EFBFBD><D6A1>64 <20>ֽڳ<D6BD><DAB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><D7B7>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC
|
||||
//010 = <20><><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡
|
||||
//001 = <20><>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>֡<EFBFBD><D6A1>60 <20>ֽڳ<D6BD><DAB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><D7B7>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC
|
||||
//000 = <20><><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡
|
||||
//bit 4 TXCRCEN<45><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRC ʹ<><CAB9>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD>PADCFG<46><47><EFBFBD>Σ<EFBFBD>MAC<41><43><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD>֡<EFBFBD><D6A1>ĩβ<CEB2><D7B7>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC<52><43> <20><><EFBFBD><EFBFBD>PADCFG<46>涨Ҫ
|
||||
//<><D7B7><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC<52><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뽫TXCRCEN <20><>1<EFBFBD><31>
|
||||
//0 = MAC<41><43><EFBFBD><EFBFBD><EFBFBD><D7B7>CRC<52><43> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4 <20><><EFBFBD>ֽڣ<D6BD><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CRC <20><EFBFBD><F2B1A8B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//bit 0 FULDPX<50><58>MAC ȫ˫<C8AB><CBAB>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = MAC<41><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ˫<C8AB><CBAB>ģʽ<C4A3>¡<EFBFBD> PHCON1.PDPXMD λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>
|
||||
//0 = MAC<41><43><EFBFBD><EFBFBD><EFBFBD>ڰ<EFBFBD>˫<EFBFBD><CBAB>ģʽ<C4A3>¡<EFBFBD> PHCON1.PDPXMD λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㡣
|
||||
ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,MACON3,MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN|MACON3_FULDPX);
|
||||
// set inter-frame gap (non-back-to-back)
|
||||
//<2F><><EFBFBD>÷DZ<C3B7><C7B1>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ĵ<EFBFBD><C4B5>ֽ<EFBFBD>
|
||||
//MAIPGL<47><4C> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ʹ<EFBFBD><CAB9>12h <20><><EFBFBD≯üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD>ð<EFBFBD>˫<EFBFBD><CBAB>ģʽ<C4A3><CABD>Ӧ<EFBFBD><D3A6><EFBFBD>̷DZ<CCB7><C7B1>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8>ֽ<EFBFBD>MAIPGH<47><48> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ʹ<EFBFBD><CAB9>0Ch
|
||||
//<2F><><EFBFBD≯üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_Write(MAIPGL,0x12);
|
||||
ENC28J60_Write(MAIPGH,0x0C);
|
||||
// set inter-frame gap (back-to-back)
|
||||
//<2F><><EFBFBD>ñ<EFBFBD><C3B1>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>MABBIPG<50><47><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||||
//ȫ˫<C8AB><CBAB>ģʽʱ<CABD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ʹ<EFBFBD><CAB9>15h <20><><EFBFBD≯üĴ<C3BC>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ð<EFBFBD>˫<EFBFBD><CBAB>ģʽʱ<CABD><CAB1>ʹ<EFBFBD><CAB9>12h <20><><EFBFBD>б<EFBFBD><D0B1>̡<EFBFBD>
|
||||
ENC28J60_Write(MABBIPG,0x15);
|
||||
// Set the maximum packet size which the controller will accept
|
||||
// Do not send packets longer than MAX_FRAMELEN:
|
||||
// <20><><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD> 1500
|
||||
ENC28J60_Write(MAMXFLL,MAX_FRAMELEN&0xFF);
|
||||
ENC28J60_Write(MAMXFLH,MAX_FRAMELEN>>8);
|
||||
// do bank 3 stuff
|
||||
// write MAC address
|
||||
// NOTE: MAC address in ENC28J60 is byte-backward
|
||||
//<2F><><EFBFBD><EFBFBD>MAC<41><43>ַ
|
||||
ENC28J60_Write(MAADR5,macaddr[0]);
|
||||
ENC28J60_Write(MAADR4,macaddr[1]);
|
||||
ENC28J60_Write(MAADR3,macaddr[2]);
|
||||
ENC28J60_Write(MAADR2,macaddr[3]);
|
||||
ENC28J60_Write(MAADR1,macaddr[4]);
|
||||
ENC28J60_Write(MAADR0,macaddr[5]);
|
||||
//<2F><><EFBFBD><EFBFBD>PHYΪȫ˫<C8AB><CBAB> LEDBΪ<42><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_PHY_Write(PHCON1,PHCON1_PDPXMD);
|
||||
// no loopback of transmitted frames <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
|
||||
//HDLDIS<49><53>PHY <20><>˫<EFBFBD><CBAB><EFBFBD><EFBFBD><EFBFBD>ؽ<EFBFBD>ֹλ
|
||||
//<2F><>PHCON1.PDPXMD = 1 <20><>PHCON1.PLOOPBK = 1 ʱ<><CAB1>
|
||||
//<2F><>λ<EFBFBD>ɱ<EFBFBD><C9B1><EFBFBD><EFBFBD>ԡ<EFBFBD>
|
||||
//<2F><>PHCON1.PDPXMD = 0 <20><>PHCON1.PLOOPBK = 0 ʱ<><CAB1>
|
||||
//1 = Ҫ<><D2AA><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD>ݽ<EFBFBD>ͨ<EFBFBD><CDA8>˫<EFBFBD><CBAB><EFBFBD>߽ӿڷ<D3BF><DAB7><EFBFBD>
|
||||
//0 = Ҫ<><D2AA><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD>ݻỷ<DDBB>ص<EFBFBD>MAC <20><>ͨ<EFBFBD><CDA8>˫<EFBFBD><CBAB><EFBFBD>߽ӿڷ<D3BF><DAB7><EFBFBD>
|
||||
ENC28J60_PHY_Write(PHCON2,PHCON2_HDLDIS);
|
||||
// switch to bank 0
|
||||
//ECON1 <20>Ĵ<EFBFBD><C4B4><EFBFBD>
|
||||
//<2F>Ĵ<EFBFBD><C4B4><EFBFBD>3-1 <20><>ʾΪECON1 <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD>
|
||||
//ENC28J60 <20><><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>ܡ<EFBFBD> ECON1 <20>а<EFBFBD><D0B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ܡ<EFBFBD><DCA1><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA <20><><EFBFBD>ƺʹ洢<CDB4><E6B4A2>ѡ<EFBFBD><D1A1>λ<EFBFBD><CEBB>
|
||||
ENC28J60_Set_Bank(ECON1);
|
||||
// enable interrutps
|
||||
//EIE<49><45> <20><>̫<EFBFBD><CCAB><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
|
||||
//bit 7 INTIE<49><45> ȫ<><C8AB>INT <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD>INT <20><><EFBFBD><EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>INT <20><><EFBFBD>ŵĻ<C4BB><EEB6AF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ձ<EFBFBD><D5B1><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD><C6BD>
|
||||
//bit 6 PKTIE<49><45> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>λ
|
||||
//1 = <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
//0 = <20><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,EIE,EIE_INTIE|EIE_PKTIE);
|
||||
// enable packet reception
|
||||
//bit 2 RXEN<45><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>λ
|
||||
//1 = ͨ<><CDA8><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>
|
||||
//0 = <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>н<EFBFBD><D0BD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ݰ<EFBFBD>
|
||||
ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,ECON1,ECON1_RXEN);
|
||||
if(ENC28J60_Read(MAADR5)== macaddr[0])return 0;//<2F><>ʼ<EFBFBD><CABC><EFBFBD>ɹ<EFBFBD>
|
||||
else return 1;
|
||||
|
||||
}
|
||||
//<2F><>ȡEREVID
|
||||
u8 ENC28J60_Get_EREVID(void)
|
||||
{
|
||||
//<2F><>EREVID <20><>Ҳ<EFBFBD>洢<EFBFBD>˰汾<CBB0><E6B1BE>Ϣ<EFBFBD><CFA2> EREVID <20><>һ<EFBFBD><D2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD>
|
||||
//<2F>ƼĴ<C6BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>5 λ<><CEBB>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>Ƭ
|
||||
//<2F>İ汾<C4B0><E6B1BE>
|
||||
return ENC28J60_Read(EREVID);
|
||||
}
|
||||
//#include "uip.h"
|
||||
//ͨ<><CDA8>ENC28J60<36><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//len:<3A><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD>С
|
||||
//packet:<3A><><EFBFBD>ݰ<EFBFBD>
|
||||
void ENC28J60_Packet_Send(u32 len,u8* packet)
|
||||
{
|
||||
//<2F><><EFBFBD>÷<EFBFBD><C3B7>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַдָ<D0B4><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_Write(EWRPTL,TXSTART_INIT&0xFF);
|
||||
ENC28J60_Write(EWRPTH,TXSTART_INIT>>8);
|
||||
//<2F><><EFBFBD><EFBFBD>TXNDָ<44>룬<EFBFBD>Զ<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD>С
|
||||
ENC28J60_Write(ETXNDL,(TXSTART_INIT+len)&0xFF);
|
||||
ENC28J60_Write(ETXNDH,(TXSTART_INIT+len)>>8);
|
||||
//дÿ<D0B4><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽڣ<D6BD>0x00<30><30>ʾʹ<CABE><CAB9>macon3<6E><33><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD>
|
||||
ENC28J60_Write_Op(ENC28J60_WRITE_BUF_MEM,0,0x00);
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>
|
||||
//printf("len:%d\r\n",len); //<2F><><EFBFBD>ӷ<EFBFBD><D3B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||||
ENC28J60_Write_Buf(len,packet);
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,ECON1,ECON1_TXRTS);
|
||||
//<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⡣<EFBFBD>μ<EFBFBD>Rev. B4 Silicon Errata point 12.
|
||||
if((ENC28J60_Read(EIR)&EIR_TXERIF))ENC28J60_Write_Op(ENC28J60_BIT_FIELD_CLR,ECON1,ECON1_TXRTS);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡһ<C8A1><D2BB><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>
|
||||
//maxlen:<3A><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD><D5B3><EFBFBD>
|
||||
//packet:<3A><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>ֵ:<3A>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>(<28>ֽ<EFBFBD>)
|
||||
u32 ENC28J60_Packet_Receive(u32 maxlen,u8* packet)
|
||||
{
|
||||
u32 rxstat;
|
||||
u32 len;
|
||||
if(ENC28J60_Read(EPKTCNT)==0)return 0; //<2F>Ƿ<EFBFBD><C7B7>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ݰ<EFBFBD>?
|
||||
//<2F><><EFBFBD>ý<EFBFBD><C3BD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
|
||||
ENC28J60_Write(ERDPTL,(NextPacketPtr));
|
||||
ENC28J60_Write(ERDPTH,(NextPacketPtr)>>8);
|
||||
// <20><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
|
||||
NextPacketPtr=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0);
|
||||
NextPacketPtr|=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0)<<8;
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3><EFBFBD>
|
||||
len=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0);
|
||||
len|=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0)<<8;
|
||||
len-=4; //ȥ<><C8A5>CRC<52><43><EFBFBD><EFBFBD>
|
||||
//<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>״̬
|
||||
rxstat=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0);
|
||||
rxstat|=ENC28J60_Read_Op(ENC28J60_READ_BUF_MEM,0)<<8;
|
||||
//<2F><><EFBFBD>ƽ<EFBFBD><C6BD>ճ<EFBFBD><D5B3><EFBFBD>
|
||||
if (len>maxlen-1)len=maxlen-1;
|
||||
//<2F><><EFBFBD><EFBFBD>CRC<52>ͷ<EFBFBD><CDB7>Ŵ<EFBFBD><C5B4><EFBFBD>
|
||||
// ERXFCON.CRCENΪĬ<CEAA><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,һ<><D2BB><EFBFBD><EFBFBD><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>.
|
||||
if((rxstat&0x80)==0)len=0;//<2F><>Ч
|
||||
else ENC28J60_Read_Buf(len,packet);//<2F>ӽ<EFBFBD><D3BD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>и<EFBFBD><D0B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>
|
||||
//RX<52><58>ָ<EFBFBD><D6B8><EFBFBD>ƶ<EFBFBD><C6B6><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0>Ŀ<EFBFBD>ʼλ<CABC><CEBB>
|
||||
//<2F><><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD>ǸղŶ<D5B2><C5B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>
|
||||
ENC28J60_Write(ERXRDPTL,(NextPacketPtr));
|
||||
ENC28J60_Write(ERXRDPTH,(NextPacketPtr)>>8);
|
||||
//<2F>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
ENC28J60_Write_Op(ENC28J60_BIT_FIELD_SET,ECON2,ECON2_PKTDEC);
|
||||
return(len);
|
||||
}
|
||||
|
||||
|
||||
|
||||
300
IAPV1.1/Driver/ENC28J602/enc28j60.h
Normal file
300
IAPV1.1/Driver/ENC28J602/enc28j60.h
Normal file
@ -0,0 +1,300 @@
|
||||
//#include "sys.h"
|
||||
#include "stm32l1xx.h"
|
||||
#ifndef __ENC28J60_H
|
||||
#define __ENC28J60_H
|
||||
|
||||
#include "stm32l1xx.h"
|
||||
#include "General_type.h"
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//ALIENTEKս<4B><D5BD>STM32<33><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//ENC28J60<36><30><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
|
||||
//<2F><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>:2012/9/28
|
||||
//<2F>汾<EFBFBD><E6B1BE>V1.0
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// ENC28J60 Control Registers
|
||||
// Control register definitions are a combination of address,
|
||||
// bank number, and Ethernet/MAC/PHY indicator bits.
|
||||
// - Register address (bits 0-4)
|
||||
// - Bank number (bits 5-6)
|
||||
// - MAC/PHY indicator (bit 7)
|
||||
#define ADDR_MASK 0x1F
|
||||
#define BANK_MASK 0x60
|
||||
#define SPRD_MASK 0x80
|
||||
// All-bank registers
|
||||
#define EIE 0x1B
|
||||
#define EIR 0x1C
|
||||
#define ESTAT 0x1D
|
||||
#define ECON2 0x1E
|
||||
#define ECON1 0x1F
|
||||
// Bank 0 registers
|
||||
#define ERDPTL (0x00|0x00)
|
||||
#define ERDPTH (0x01|0x00)
|
||||
#define EWRPTL (0x02|0x00)
|
||||
#define EWRPTH (0x03|0x00)
|
||||
#define ETXSTL (0x04|0x00)
|
||||
#define ETXSTH (0x05|0x00)
|
||||
#define ETXNDL (0x06|0x00)
|
||||
#define ETXNDH (0x07|0x00)
|
||||
#define ERXSTL (0x08|0x00)
|
||||
#define ERXSTH (0x09|0x00)
|
||||
#define ERXNDL (0x0A|0x00)
|
||||
#define ERXNDH (0x0B|0x00)
|
||||
//ERXWRPTH:ERXWRPTL <20>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>FIFO <20><>
|
||||
//<2F><><EFBFBD>ĸ<EFBFBD>λ<EFBFBD><CEBB>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ֽڡ<D6BD> ָ<><D6B8><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ģ<EFBFBD><C4A3>ڳ<EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD>롣 ָ<><D6B8><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>FIFO <20><>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD><D5BC>Ĵ<EFBFBD>С<EFBFBD><D0A1>
|
||||
#define ERXRDPTL (0x0C|0x00)
|
||||
#define ERXRDPTH (0x0D|0x00)
|
||||
#define ERXWRPTL (0x0E|0x00)
|
||||
#define ERXWRPTH (0x0F|0x00)
|
||||
#define EDMASTL (0x10|0x00)
|
||||
#define EDMASTH (0x11|0x00)
|
||||
#define EDMANDL (0x12|0x00)
|
||||
#define EDMANDH (0x13|0x00)
|
||||
#define EDMADSTL (0x14|0x00)
|
||||
#define EDMADSTH (0x15|0x00)
|
||||
#define EDMACSL (0x16|0x00)
|
||||
#define EDMACSH (0x17|0x00)
|
||||
// Bank 1 registers
|
||||
#define EHT0 (0x00|0x20)
|
||||
#define EHT1 (0x01|0x20)
|
||||
#define EHT2 (0x02|0x20)
|
||||
#define EHT3 (0x03|0x20)
|
||||
#define EHT4 (0x04|0x20)
|
||||
#define EHT5 (0x05|0x20)
|
||||
#define EHT6 (0x06|0x20)
|
||||
#define EHT7 (0x07|0x20)
|
||||
#define EPMM0 (0x08|0x20)
|
||||
#define EPMM1 (0x09|0x20)
|
||||
#define EPMM2 (0x0A|0x20)
|
||||
#define EPMM3 (0x0B|0x20)
|
||||
#define EPMM4 (0x0C|0x20)
|
||||
#define EPMM5 (0x0D|0x20)
|
||||
#define EPMM6 (0x0E|0x20)
|
||||
#define EPMM7 (0x0F|0x20)
|
||||
#define EPMCSL (0x10|0x20)
|
||||
#define EPMCSH (0x11|0x20)
|
||||
#define EPMOL (0x14|0x20)
|
||||
#define EPMOH (0x15|0x20)
|
||||
#define EWOLIE (0x16|0x20)
|
||||
#define EWOLIR (0x17|0x20)
|
||||
#define ERXFCON (0x18|0x20)
|
||||
#define EPKTCNT (0x19|0x20)
|
||||
// Bank 2 registers
|
||||
#define MACON1 (0x00|0x40|0x80)
|
||||
#define MACON2 (0x01|0x40|0x80)
|
||||
#define MACON3 (0x02|0x40|0x80)
|
||||
#define MACON4 (0x03|0x40|0x80)
|
||||
#define MABBIPG (0x04|0x40|0x80)
|
||||
#define MAIPGL (0x06|0x40|0x80)
|
||||
#define MAIPGH (0x07|0x40|0x80)
|
||||
#define MACLCON1 (0x08|0x40|0x80)
|
||||
#define MACLCON2 (0x09|0x40|0x80)
|
||||
#define MAMXFLL (0x0A|0x40|0x80)
|
||||
#define MAMXFLH (0x0B|0x40|0x80)
|
||||
#define MAPHSUP (0x0D|0x40|0x80)
|
||||
#define MICON (0x11|0x40|0x80)
|
||||
#define MICMD (0x12|0x40|0x80)
|
||||
#define MIREGADR (0x14|0x40|0x80)
|
||||
#define MIWRL (0x16|0x40|0x80)
|
||||
#define MIWRH (0x17|0x40|0x80)
|
||||
#define MIRDL (0x18|0x40|0x80)
|
||||
#define MIRDH (0x19|0x40|0x80)
|
||||
// Bank 3 registers
|
||||
#define MAADR1 (0x00|0x60|0x80)
|
||||
#define MAADR0 (0x01|0x60|0x80)
|
||||
#define MAADR3 (0x02|0x60|0x80)
|
||||
#define MAADR2 (0x03|0x60|0x80)
|
||||
#define MAADR5 (0x04|0x60|0x80)
|
||||
#define MAADR4 (0x05|0x60|0x80)
|
||||
#define EBSTSD (0x06|0x60)
|
||||
#define EBSTCON (0x07|0x60)
|
||||
#define EBSTCSL (0x08|0x60)
|
||||
#define EBSTCSH (0x09|0x60)
|
||||
#define MISTAT (0x0A|0x60|0x80)
|
||||
#define EREVID (0x12|0x60)
|
||||
#define ECOCON (0x15|0x60)
|
||||
#define EFLOCON (0x17|0x60)
|
||||
#define EPAUSL (0x18|0x60)
|
||||
#define EPAUSH (0x19|0x60)
|
||||
// PHY registers
|
||||
#define PHCON1 0x00
|
||||
#define PHSTAT1 0x01
|
||||
#define PHHID1 0x02
|
||||
#define PHHID2 0x03
|
||||
#define PHCON2 0x10
|
||||
#define PHSTAT2 0x11
|
||||
#define PHIE 0x12
|
||||
#define PHIR 0x13
|
||||
#define PHLCON 0x14
|
||||
// ENC28J60 ERXFCON Register Bit Definitions
|
||||
#define ERXFCON_UCEN 0x80
|
||||
#define ERXFCON_ANDOR 0x40
|
||||
#define ERXFCON_CRCEN 0x20
|
||||
#define ERXFCON_PMEN 0x10
|
||||
#define ERXFCON_MPEN 0x08
|
||||
#define ERXFCON_HTEN 0x04
|
||||
#define ERXFCON_MCEN 0x02
|
||||
#define ERXFCON_BCEN 0x01
|
||||
// ENC28J60 EIE Register Bit Definitions
|
||||
#define EIE_INTIE 0x80
|
||||
#define EIE_PKTIE 0x40
|
||||
#define EIE_DMAIE 0x20
|
||||
#define EIE_LINKIE 0x10
|
||||
#define EIE_TXIE 0x08
|
||||
#define EIE_WOLIE 0x04
|
||||
#define EIE_TXERIE 0x02
|
||||
#define EIE_RXERIE 0x01
|
||||
// ENC28J60 EIR Register Bit Definitions
|
||||
#define EIR_PKTIF 0x40
|
||||
#define EIR_DMAIF 0x20
|
||||
#define EIR_LINKIF 0x10
|
||||
#define EIR_TXIF 0x08
|
||||
#define EIR_WOLIF 0x04
|
||||
#define EIR_TXERIF 0x02
|
||||
#define EIR_RXERIF 0x01
|
||||
// ENC28J60 ESTAT Register Bit Definitions
|
||||
#define ESTAT_INT 0x80
|
||||
#define ESTAT_LATECOL 0x10
|
||||
#define ESTAT_RXBUSY 0x04
|
||||
#define ESTAT_TXABRT 0x02
|
||||
#define ESTAT_CLKRDY 0x01
|
||||
// ENC28J60 ECON2 Register Bit Definitions
|
||||
#define ECON2_AUTOINC 0x80
|
||||
#define ECON2_PKTDEC 0x40
|
||||
#define ECON2_PWRSV 0x20
|
||||
#define ECON2_VRPS 0x08
|
||||
// ENC28J60 ECON1 Register Bit Definitions
|
||||
#define ECON1_TXRST 0x80
|
||||
#define ECON1_RXRST 0x40
|
||||
#define ECON1_DMAST 0x20
|
||||
#define ECON1_CSUMEN 0x10
|
||||
#define ECON1_TXRTS 0x08
|
||||
#define ECON1_RXEN 0x04
|
||||
#define ECON1_BSEL1 0x02
|
||||
#define ECON1_BSEL0 0x01
|
||||
// ENC28J60 MACON1 Register Bit Definitions
|
||||
#define MACON1_LOOPBK 0x10
|
||||
#define MACON1_TXPAUS 0x08
|
||||
#define MACON1_RXPAUS 0x04
|
||||
#define MACON1_PASSALL 0x02
|
||||
#define MACON1_MARXEN 0x01
|
||||
// ENC28J60 MACON2 Register Bit Definitions
|
||||
#define MACON2_MARST 0x80
|
||||
#define MACON2_RNDRST 0x40
|
||||
#define MACON2_MARXRST 0x08
|
||||
#define MACON2_RFUNRST 0x04
|
||||
#define MACON2_MATXRST 0x02
|
||||
#define MACON2_TFUNRST 0x01
|
||||
// ENC28J60 MACON3 Register Bit Definitions
|
||||
#define MACON3_PADCFG2 0x80
|
||||
#define MACON3_PADCFG1 0x40
|
||||
#define MACON3_PADCFG0 0x20
|
||||
#define MACON3_TXCRCEN 0x10
|
||||
#define MACON3_PHDRLEN 0x08
|
||||
#define MACON3_HFRMLEN 0x04
|
||||
#define MACON3_FRMLNEN 0x02
|
||||
#define MACON3_FULDPX 0x01
|
||||
// ENC28J60 MICMD Register Bit Definitions
|
||||
#define MICMD_MIISCAN 0x02
|
||||
#define MICMD_MIIRD 0x01
|
||||
// ENC28J60 MISTAT Register Bit Definitions
|
||||
#define MISTAT_NVALID 0x04
|
||||
#define MISTAT_SCAN 0x02
|
||||
#define MISTAT_BUSY 0x01
|
||||
// ENC28J60 PHY PHCON1 Register Bit Definitions
|
||||
#define PHCON1_PRST 0x8000
|
||||
#define PHCON1_PLOOPBK 0x4000
|
||||
#define PHCON1_PPWRSV 0x0800
|
||||
#define PHCON1_PDPXMD 0x0100
|
||||
// ENC28J60 PHY PHSTAT1 Register Bit Definitions
|
||||
#define PHSTAT1_PFDPX 0x1000
|
||||
#define PHSTAT1_PHDPX 0x0800
|
||||
#define PHSTAT1_LLSTAT 0x0004
|
||||
#define PHSTAT1_JBSTAT 0x0002
|
||||
// ENC28J60 PHY PHCON2 Register Bit Definitions
|
||||
#define PHCON2_FRCLINK 0x4000
|
||||
#define PHCON2_TXDIS 0x2000
|
||||
#define PHCON2_JABBER 0x0400
|
||||
#define PHCON2_HDLDIS 0x0100
|
||||
|
||||
// ENC28J60 Packet Control Byte Bit Definitions
|
||||
#define PKTCTRL_PHUGEEN 0x08
|
||||
#define PKTCTRL_PPADEN 0x04
|
||||
#define PKTCTRL_PCRCEN 0x02
|
||||
#define PKTCTRL_POVERRIDE 0x01
|
||||
|
||||
// SPI operation codes
|
||||
#define ENC28J60_READ_CTRL_REG 0x00
|
||||
#define ENC28J60_READ_BUF_MEM 0x3A
|
||||
#define ENC28J60_WRITE_CTRL_REG 0x40
|
||||
#define ENC28J60_WRITE_BUF_MEM 0x7A
|
||||
#define ENC28J60_BIT_FIELD_SET 0x80
|
||||
#define ENC28J60_BIT_FIELD_CLR 0xA0
|
||||
#define ENC28J60_SOFT_RESET 0xFF
|
||||
|
||||
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
|
||||
// buffer boundaries applied to internal 8K ram
|
||||
// the entire available packet buffer space is allocated
|
||||
//
|
||||
// start with recbuf at 0/
|
||||
#define RXSTART_INIT 0x0
|
||||
// receive buffer end
|
||||
#define RXSTOP_INIT (0x1FFF-1518-1)
|
||||
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (0~1518 bytes)
|
||||
#define TXSTART_INIT (0x1FFF-1518)
|
||||
// stp TX buffer at end of mem
|
||||
#define TXSTOP_INIT 0x1FFF
|
||||
// max frame length which the conroller will accept:
|
||||
#define MAX_FRAMELEN 1518 // (note: maximum ethernet frame length would be 1518)
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//GPIOA->ODR |= (unsigned int)(1<<ENC28J60_CS);
|
||||
//#define ENC28J60_CS PGout(8) //ENC28J60Ƭѡ<C6AC>ź<EFBFBD>
|
||||
//#define ENC28J60_RST PGout(6) //ENC28J60<36><30>λ<EFBFBD>ź<EFBFBD>
|
||||
#define ENC28J60_CSH (GPIOA->ODR |= (unsigned int)(1<<4))
|
||||
#define ENC28J60_CSL (GPIOA->ODR &= ~((unsigned int)(1<<4)))
|
||||
//SPI1<49><31>ʼ<EFBFBD><CABC>
|
||||
void ENC28J60_Reset(void);
|
||||
u8 ENC28J60_Read_Op(u8 op,u8 addr);
|
||||
void ENC28J60_Write_Op(u8 op,u8 addr,u8 data);
|
||||
void ENC28J60_Read_Buf(u32 len,u8* data);
|
||||
void ENC28J60_Write_Buf(u32 len,u8* data);
|
||||
void ENC28J60_Set_Bank(u8 bank);
|
||||
u8 ENC28J60_Read(u8 addr);
|
||||
void ENC28J60_Write(u8 addr,u8 data);
|
||||
void ENC28J60_PHY_Write(u8 addr,u32 data);
|
||||
u8 ENC28J60_Init(u8* macaddr);
|
||||
u8 ENC28J60_Get_EREVID(void);
|
||||
void ENC28J60_Packet_Send(u32 len,u8* packet);
|
||||
u32 ENC28J60_Packet_Receive(u32 maxlen,u8* packet);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user