20260324
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91
IAPV1.1/Driver/system/sys/sys.h
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91
IAPV1.1/Driver/system/sys/sys.h
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#ifndef __SYS_H
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#define __SYS_H
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#include "misc.h"
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#include "stm32l1xx.h"
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#include "general_type.h"
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//#define NVIC_VectTab_RAM ((u32)0x20000000)
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//#define NVIC_VectTab_FLASH ((u32)0x08000000)
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//JTAGģʽ<C4A3><CABD><EFBFBD>ö<EFBFBD><C3B6><EFBFBD>
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#define JTAG_SWD_DISABLE 0X02
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#define SWD_ENABLE 0X01
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#define JTAG_SWD_ENABLE 0X00
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/////////////////////////////////////////////////////////////////
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void Sys_Soft_Reset(void); //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>λ
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void Sys_Standby(void); //<2F><><EFBFBD><EFBFBD>ģʽ
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void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);//<2F><><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
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void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group);//<2F><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD>
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void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM);//<2F>ⲿ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>(ֻ<><D6BB>GPIOA~G)
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void JTAG_Set(u8 mode);
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//////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ຯ<EFBFBD><E0BAAF>
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void WFI_SET(void); //ִ<><D6B4>WFIָ<49><D6B8>
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void INTX_DISABLE(void);//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void INTX_ENABLE(void); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void MSR_MSP(u32 addr); //<2F><><EFBFBD>ö<EFBFBD>ջ<EFBFBD><D5BB>ַ
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//λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,ʵ<><CAB5>51<35><31><EFBFBD>Ƶ<EFBFBD>GPIO<49><4F><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>˼<EFBFBD><CBBC>,<2C>ο<EFBFBD><<CM3Ȩ<33><C8A8>ָ<EFBFBD><D6B8>>><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(87ҳ~92ҳ).
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8>
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#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
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#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
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#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
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//IO<49>ڵ<EFBFBD>ַӳ<D6B7><D3B3>
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#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
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#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
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#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
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#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
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#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
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#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
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#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
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#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
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#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
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#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
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#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
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#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
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#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
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#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD>,ֻ<>Ե<EFBFBD>һ<EFBFBD><D2BB>IO<49><4F>!
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//ȷ<><C8B7>n<EFBFBD><6E>ֵС<D6B5><D0A1>16!
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#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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#endif
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