20260324
This commit is contained in:
178
RTX5_20220316/Driver/system/sys/sys.c
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178
RTX5_20220316/Driver/system/sys/sys.c
Normal file
@ -0,0 +1,178 @@
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#include "sys.h"
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void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
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{
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SCB->VTOR = NVIC_VectTab|(Offset & (u32)0x1FFFFF80);//<2F><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
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//<2F><><EFBFBD>ڱ<EFBFBD>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<44><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D>
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}
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//<2F><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD>
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//NVIC_Group:NVIC<49><43><EFBFBD><EFBFBD> 0~4 <20>ܹ<EFBFBD>5<EFBFBD><35>
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void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group)
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{
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u32 temp,temp1;
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temp1=(~NVIC_Group)&0x07;//ȡ<><C8A1><EFBFBD><EFBFBD>λ
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temp1<<=8;
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temp=SCB->AIRCR; //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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temp&=0X0000F8FF; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>
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temp|=0X05FA0000; //д<><D0B4>Կ<EFBFBD><D4BF>
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temp|=temp1;
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SCB->AIRCR=temp; //<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>
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}
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//<2F><><EFBFBD><EFBFBD>NVIC
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//NVIC_PreemptionPriority:<3A><>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>
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//NVIC_SubPriority :<3A><>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//NVIC_Channel :<3A>жϱ<D0B6><CFB1><EFBFBD>
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//NVIC_Group :<3A>жϷ<D0B6><CFB7><EFBFBD> 0~4
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//ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD>ܳ<EFBFBD><DCB3><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Χ!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>벻<EFBFBD><EBB2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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//<2F>黮<EFBFBD><E9BBAE>:
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//<2F><>0:0λ<30><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,4λ<34><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//<2F><>1:1λ<31><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,3λ<33><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//<2F><>2:2λ<32><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,2λ<32><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//<2F><>3:3λ<33><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,1λ<31><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//<2F><>4:4λ<34><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,0λ<30><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
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//NVIC_SubPriority<74><79>NVIC_PreemptionPriority<74><79>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD>,<2C><>ֵԽС,Խ<><D4BD><EFBFBD><EFBFBD>
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void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
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{
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u32 temp;
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u8 IPRADDR=NVIC_Channel/4; //ÿ<><C3BF>ֻ<EFBFBD>ܴ<EFBFBD>4<EFBFBD><34>,<2C>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>ַ
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u8 IPROFFSET=NVIC_Channel%4;//<2F><><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD>ƫ<EFBFBD><C6AB>
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IPROFFSET=IPROFFSET*8+4; //<2F>õ<EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ȷ<EFBFBD><C8B7>λ<EFBFBD><CEBB>
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MY_NVIC_PriorityGroupConfig(NVIC_Group);//<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>
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temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
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temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
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temp&=0xf;//ȡ<><C8A1><EFBFBD><EFBFBD>λ
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if(NVIC_Channel<32)NVIC->ISER[0]|=1<<NVIC_Channel;//ʹ<><CAB9><EFBFBD>ж<EFBFBD>λ(Ҫ<><D2AA><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD>,<2C>෴<EFBFBD><E0B7B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>OK)
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else NVIC->ISER[1]|=1<<(NVIC_Channel-32);
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NVIC->IP[IPRADDR]|=temp<<IPROFFSET;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD> IPR
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}
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//<2F>ⲿ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
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//ֻ<><D6BB><EFBFBD><EFBFBD>GPIOA~G;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PVD,RTC<54><43>USB<53><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD>:
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//GPIOx:0~6,<2C><><EFBFBD><EFBFBD>GPIOA~G
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//BITx:<3A><>Ҫʹ<D2AA>ܵ<EFBFBD>λ;
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//TRIM:<3A><><EFBFBD><EFBFBD>ģʽ,1,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>;2,<2C>Ͻ<EFBFBD><CFBD><EFBFBD>;3<><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD>
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//<2F>ú<EFBFBD><C3BA><EFBFBD>һ<EFBFBD><D2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>IO<49><4F>,<2C><><EFBFBD><EFBFBD>IO<49><4F>,<2C><><EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD><CEB5><EFBFBD>
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//<2F>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ж<EFBFBD>,<2C>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
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{
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u8 EXTADDR;
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u8 EXTOFFSET;
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EXTADDR=BITx/4;//<2F>õ<EFBFBD><C3B5>жϼĴ<CFBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD><C4B1><EFBFBD>
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EXTOFFSET=(BITx%4)*4;
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RCC->APB2ENR|=0x01;//ʹ<><CAB9>io<69><6F><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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SYSCFG->EXTICR[EXTADDR]&=~(0x000F<<EXTOFFSET);//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>
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SYSCFG->EXTICR[EXTADDR]|=GPIOx<<EXTOFFSET;//EXTI.BITxӳ<78>䵽GPIOx.BITx
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//<2F>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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EXTI->IMR|=1<<BITx;// <20><><EFBFBD><EFBFBD>line BITx<54>ϵ<EFBFBD><CFB5>ж<EFBFBD>
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//EXTI->EMR|=1<<BITx;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>line BITx<54>ϵ<EFBFBD><CFB5>¼<EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF>Ե<EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>!)
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if(TRIM&0x01)EXTI->FTSR|=1<<BITx;//line BITx<54><78><EFBFBD>¼<EFBFBD><C2BC>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
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if(TRIM&0x02)EXTI->RTSR|=1<<BITx;//line BITx<54><78><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>踴λ!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<F0B4AEBF><DAB2><EFBFBD><EFBFBD><EFBFBD>.
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӼĴ<D3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>λ
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void MYRCC_DeInit(void)
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{
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RCC->APB1RSTR = 0x00000000;//<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>
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RCC->APB2RSTR = 0x00000000;
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RCC->AHBENR = 0x00000014; //˯<><CBAF>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SRAMʱ<4D><CAB1>ʹ<EFBFBD><CAB9>.<2E><><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>.
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RCC->APB2ENR = 0x00000000; //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD>ӹر<D3B9>.
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RCC->APB1ENR = 0x00000000;
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RCC->CR |= 0x00000001; //ʹ<><CAB9><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>HSION
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RCC->CFGR &= 0xF8FF0000; //<2F><>λSW[1:0],HPRE[3:0],PPRE1[2:0],PPRE2[2:0],ADCPRE[1:0],MCO[2:0]
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RCC->CR &= 0xFEF6FFFF; //<2F><>λHSEON,CSSON,PLLON
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RCC->CR &= 0xFFFBFFFF; //<2F><>λHSEBYP
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RCC->CFGR &= 0xFF80FFFF; //<2F><>λPLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE
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RCC->CIR = 0x00000000; //<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#ifdef VECT_TAB_RAM
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MY_NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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#else
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MY_NVIC_SetVectorTable(NVIC_VectTab_FLASH,0x0);
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#endif
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}
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//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
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__asm void WFI_SET(void)
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{
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WFI;
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}
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//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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__asm void INTX_DISABLE(void)
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{
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CPSID I;
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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__asm void INTX_ENABLE(void)
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{
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CPSIE I;
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}
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//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
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//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
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__asm void MSR_MSP(u32 addr)
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{
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MSR MSP, r0 //set Main Stack value
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BX r14
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
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void Sys_Standby(void)
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{
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SCB->SCR|=1<<2;//ʹ<><CAB9>SLEEPDEEPλ (SYS->CTRL)
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RCC->APB1ENR|=1<<28; //ʹ<>ܵ<EFBFBD>Դʱ<D4B4><CAB1>
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PWR->CSR|=1<<8; //<2F><><EFBFBD><EFBFBD>WKUP<55><50><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD>
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PWR->CR|=1<<2; //<2F><><EFBFBD><EFBFBD>Wake-up <20><>־
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PWR->CR|=1<<1; //PDDS<44><53>λ
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WFI_SET(); //ִ<><D6B4>WFIָ<49><D6B8>
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}
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//ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>λ
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void Sys_Soft_Reset(void)
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{
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SCB->AIRCR =0X05FA0000|(u32)0x04;
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}
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//JTAGģʽ<C4A3><CABD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>JTAG<41><47>ģʽ
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//mode:jtag,swdģʽ<C4A3><CABD><EFBFBD><EFBFBD>;00,ȫʹ<C8AB><CAB9>;01,ʹ<><CAB9>SWD;10,ȫ<>ر<EFBFBD>;
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//#define JTAG_SWD_DISABLE 0X02
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//#define SWD_ENABLE 0X01
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//#define JTAG_SWD_ENABLE 0X00
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void JTAG_Set(u8 mode)
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{
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u32 temp;
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temp=mode;
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temp<<=25;
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RCC->APB2ENR|=1<<0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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// AFIO->MAPR&=0XF8FFFFFF; //<2F><><EFBFBD><EFBFBD>MAPR<50><52>[26:24]
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// AFIO->MAPR|=temp; //<2F><><EFBFBD><EFBFBD>jtagģʽ
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}
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91
RTX5_20220316/Driver/system/sys/sys.h
Normal file
91
RTX5_20220316/Driver/system/sys/sys.h
Normal file
@ -0,0 +1,91 @@
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#ifndef __SYS_H
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#define __SYS_H
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#include "misc.h"
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#include "stm32l1xx.h"
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#include "general_type.h"
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//#define NVIC_VectTab_RAM ((u32)0x20000000)
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//#define NVIC_VectTab_FLASH ((u32)0x08000000)
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//JTAGģʽ<C4A3><CABD><EFBFBD>ö<EFBFBD><C3B6><EFBFBD>
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#define JTAG_SWD_DISABLE 0X02
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#define SWD_ENABLE 0X01
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#define JTAG_SWD_ENABLE 0X00
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/////////////////////////////////////////////////////////////////
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void Sys_Soft_Reset(void); //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>λ
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void Sys_Standby(void); //<2F><><EFBFBD><EFBFBD>ģʽ
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void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);//<2F><><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
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void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group);//<2F><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD>
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void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM);//<2F>ⲿ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>(ֻ<><D6BB>GPIOA~G)
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void JTAG_Set(u8 mode);
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//////////////////////////////////////////////////////////////////////////////
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//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ຯ<EFBFBD><E0BAAF>
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void WFI_SET(void); //ִ<><D6B4>WFIָ<49><D6B8>
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void INTX_DISABLE(void);//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void INTX_ENABLE(void); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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void MSR_MSP(u32 addr); //<2F><><EFBFBD>ö<EFBFBD>ջ<EFBFBD><D5BB>ַ
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||||
|
||||
|
||||
//λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,ʵ<><CAB5>51<35><31><EFBFBD>Ƶ<EFBFBD>GPIO<49><4F><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD>
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||||
//<2F><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>˼<EFBFBD><CBBC>,<2C>ο<EFBFBD><<CM3Ȩ<33><C8A8>ָ<EFBFBD><D6B8>>><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(87ҳ~92ҳ).
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||||
//IO<49>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8>
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#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
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||||
#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
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#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
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||||
//IO<49>ڵ<EFBFBD>ַӳ<D6B7><D3B3>
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||||
#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
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||||
#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
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||||
#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
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||||
#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
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||||
#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
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||||
#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
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||||
#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
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||||
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||||
#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
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||||
#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
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#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
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#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
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#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
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||||
#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
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#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
|
||||
|
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//IO<49>ڲ<EFBFBD><DAB2><EFBFBD>,ֻ<>Ե<EFBFBD>һ<EFBFBD><D2BB>IO<49><4F>!
|
||||
//ȷ<><C8B7>n<EFBFBD><6E>ֵС<D6B5><D0A1>16!
|
||||
#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
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||||
#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //<2F><><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user