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chenxin
2026-04-23 10:50:18 +08:00
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RTX5_20220316/Project/%APPDATA%/Microsoft/Windows/IETldCache/index.dat Normal file
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#include "SPI_SD_driver.h"
#include "diskio.h"
//#include "flash.h"
#include "spi.h"
//#include "malloc.h"
//////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
//ALIENTEKս<4B><D5BD>STM32<33><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//FATFS disio.c <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
//<2F>޸<EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>:2012/9/18
//<2F>汾<EFBFBD><E6B1BE>V1.0
//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾ 2009-2019
//All rights reserved
//////////////////////////////////////////////////////////////////////////////////
#define SD_CARD 0 //SD<53><44>,<2C><><EFBFBD><EFBFBD>Ϊ0
#define EX_FLASH 1 //<2F>ⲿflash,<2C><><EFBFBD><EFBFBD>Ϊ1
#define FLASH_SECTOR_SIZE 512
//<2F><><EFBFBD><EFBFBD>W25Q64
//ǰ6M<36>ֽڸ<D6BD>fatfs<66><73>,6M<36>ֽں<D6BD>~6M+500K<30><4B><EFBFBD>û<EFBFBD><C3BB><EFBFBD>,6M+500K<30>Ժ<EFBFBD>,<2C><><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD>ֿ<EFBFBD>,<2C>ֿ<EFBFBD>ռ<EFBFBD><D5BC>1.5M.
u16 FLASH_SECTOR_COUNT=2048*6;//6M<36>ֽ<EFBFBD>,Ĭ<><C4AC>ΪW25Q64
#define FLASH_BLOCK_SIZE 8 //ÿ<><C3BF>BLOCK<43><4B>8<EFBFBD><38><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DSTATUS disk_initialize (
BYTE drv /* Physical drive nmuber (0..) */
)
{
u8 res=0;
switch(drv)
{
case SD_CARD://SD<53><44>
res = SD_Initialize();//SD_Initialize()
if(res)//STM32 SPI<50><49>bug,<2C><>sd<73><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD>ܵ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD>SPI<50><49>д<EFBFBD>쳣
{
SD_SPI_SpeedLow();
SD_SPI_ReadWriteByte(0xff);//<2F>ṩ<EFBFBD><E1B9A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8<EFBFBD><38>ʱ<EFBFBD><CAB1>
SD_SPI_SpeedHigh();
}
break;
case EX_FLASH://<2F>ⲿflash
//SPI_Flash_Init();
// if(SPI_FLASH_TYPE==W25Q64)FLASH_SECTOR_COUNT=2048*6;//W25Q64
// else FLASH_SECTOR_COUNT=2048*2; //<2F><><EFBFBD><EFBFBD>
break;
default:
res=1;
}
if(res)return STA_NOINIT;
else return 0; //<2F><>ʼ<EFBFBD><CABC><EFBFBD>ɹ<EFBFBD>
}
//<2F><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>״̬
DSTATUS disk_status (
BYTE drv /* Physical drive nmuber (0..) */
)
{
return 0;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//drv:<3A><><EFBFBD>̱<EFBFBD><CCB1><EFBFBD>0~9
//*buff:<3A><><EFBFBD>ݽ<EFBFBD><DDBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>׵<EFBFBD>ַ
//sector:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
//count:<3A><>Ҫ<EFBFBD><D2AA>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DRESULT disk_read (
BYTE drv, /* Physical drive nmuber (0..) */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Sector address (LBA) */
BYTE count /* Number of sectors to read (1..255) */
)
{
u8 res=0;
if (!count)return RES_PARERR;//count<6E><74><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD>򷵻ز<F2B7B5BB><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
switch(drv)
{
case SD_CARD://SD<53><44>
res=SD_ReadDisk(buff,sector,count);
if(res)//STM32 SPI<50><49>bug,<2C><>sd<73><64><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD>ܵ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD>SPI<50><49>д<EFBFBD>쳣
{
SD_SPI_SpeedLow();
SD_SPI_ReadWriteByte(0xff);//<2F>ṩ<EFBFBD><E1B9A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8<EFBFBD><38>ʱ<EFBFBD><CAB1>
SD_SPI_SpeedHigh();
}
break;
case EX_FLASH://<2F>ⲿflash
for(;count>0;count--)
{
//SPI_Flash_Read(buff,sector*FLASH_SECTOR_SIZE,FLASH_SECTOR_SIZE);
sector++;
buff+=FLASH_SECTOR_SIZE;
}
res=0;
break;
default:
res=1;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>SPI_SD_driver.c<>ķ<EFBFBD><C4B7><EFBFBD>ֵת<D6B5><D7AA>ff.c<>ķ<EFBFBD><C4B7><EFBFBD>ֵ
if(res==0x00)return RES_OK;
else return RES_ERROR;
}
//д<><D0B4><EFBFBD><EFBFBD>
//drv:<3A><><EFBFBD>̱<EFBFBD><CCB1><EFBFBD>0~9
//*buff:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ
//sector:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
//count:<3A><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#if _READONLY == 0
DRESULT disk_write (
BYTE drv, /* Physical drive nmuber (0..) */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Sector address (LBA) */
BYTE count /* Number of sectors to write (1..255) */
)
{
u8 res=0;
if (!count)return RES_PARERR;//count<6E><74><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD>򷵻ز<F2B7B5BB><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
switch(drv)
{
case SD_CARD://SD<53><44>
res=SD_WriteDisk((u8*)buff,sector,count);
break;
case EX_FLASH://<2F>ⲿflash
for(;count>0;count--)
{
//SPI_Flash_Write((u8*)buff,sector*FLASH_SECTOR_SIZE,FLASH_SECTOR_SIZE);
sector++;
buff+=FLASH_SECTOR_SIZE;
}
res=0;
break;
default:
res=1;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>SPI_SD_driver.c<>ķ<EFBFBD><C4B7><EFBFBD>ֵת<D6B5><D7AA>ff.c<>ķ<EFBFBD><C4B7><EFBFBD>ֵ
if(res == 0x00)return RES_OK;
else return RES_ERROR;
}
#endif /* _READONLY */
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD>
//drv:<3A><><EFBFBD>̱<EFBFBD><CCB1><EFBFBD>0~9
//ctrl:<3A><><EFBFBD>ƴ<EFBFBD><C6B4><EFBFBD>
//*buff:<3A><><EFBFBD><EFBFBD>/<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
DRESULT disk_ioctl (
BYTE drv, /* Physical drive nmuber (0..) */
BYTE ctrl, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
DRESULT res;
if(drv==SD_CARD)//SD<53><44>
{
switch(ctrl)
{
case CTRL_SYNC:
SD_CS_ENABLE();
if(SD_WaitReady()==0)res = RES_OK;
else res = RES_ERROR;
SD_CS_DISABLE();
break;
case GET_SECTOR_SIZE:
*(WORD*)buff = 512;
res = RES_OK;
break;
case GET_BLOCK_SIZE:
*(WORD*)buff = 8;
res = RES_OK;
break;
case GET_SECTOR_COUNT:
*(DWORD*)buff = SD_GetSectorCount();
res = RES_OK;
break;
default:
res = RES_PARERR;
break;
}
}else if(drv==EX_FLASH) //<2F>ⲿFLASH
{
switch(ctrl)
{
case CTRL_SYNC:
res = RES_OK;
break;
case GET_SECTOR_SIZE:
*(WORD*)buff = FLASH_SECTOR_SIZE;
res = RES_OK;
break;
case GET_BLOCK_SIZE:
*(WORD*)buff = FLASH_BLOCK_SIZE;
res = RES_OK;
break;
case GET_SECTOR_COUNT:
*(DWORD*)buff = FLASH_SECTOR_COUNT;
res = RES_OK;
break;
default:
res = RES_PARERR;
break;
}
}else res=RES_ERROR;//<2F><><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD>֧<EFBFBD><D6A7>
return res;
}
//<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
//User defined function to give a current time to fatfs module */
//31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
//15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
DWORD get_fattime (void)
{
RTC_TimeTypeDef time;
RTC_DateTypeDef date;
RTC_GetTime(RTC_Format_BIN,&time);
RTC_GetDate(RTC_Format_BIN,&date);
return ((date.RTC_Year+2000-1980)<<25|
date.RTC_Month<<21|
date.RTC_Date<<16|
time.RTC_Hours<<11|
time.RTC_Minutes<<5|
time.RTC_Seconds>>1
);
}
//<2F><>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>
//void *ff_memalloc (UINT size)
//{
// return (void*)mymalloc(SRAMIN,size);
//}
////<2F>ͷ<EFBFBD><CDB7>ڴ<EFBFBD>
//void ff_memfree (void* mf)
//{
// myfree(SRAMIN,mf);
//}

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// File: STM32L100_151_152_162.dbgconf
// Version: 1.0.0
// Note: refer to STM32L100xx STM32L151xx STM32L152xx STM32L162xx Reference manual (RM0038)
// refer to STM32L100xx datasheet
// refer to STM32L151xx STM32L152xx datasheets
// refer to STM32L162xx datasheet
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.2> DBG_STANDBY <i> Debug Standby mode
// <o.1> DBG_STOP <i> Debug Stop mode
// <o.0> DBG_SLEEP <i> Debug Sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> Debug RTC stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.4> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.3> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.2> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> Flash Download Options
// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
// </h>
DoOptionByteLoading = 0x00000000;
// <<< end of configuration section >>>

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// File: STM32L100_151_152_162.dbgconf
// Version: 1.0.0
// Note: refer to STM32L100xx STM32L151xx STM32L152xx STM32L162xx Reference manual (RM0038)
// refer to STM32L100xx datasheet
// refer to STM32L151xx STM32L152xx datasheets
// refer to STM32L162xx datasheet
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.2> DBG_STANDBY <i> Debug Standby mode
// <o.1> DBG_STOP <i> Debug Stop mode
// <o.0> DBG_SLEEP <i> Debug Sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> Debug RTC stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.4> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.3> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.2> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> Flash Download Options
// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
// </h>
DoOptionByteLoading = 0x00000000;
// <<< end of configuration section >>>

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// File: STM32L100_151_152_162.dbgconf
// Version: 1.0.0
// Note: refer to STM32L100xx STM32L151xx STM32L152xx STM32L162xx Reference manual (RM0038)
// refer to STM32L100xx datasheet
// refer to STM32L151xx STM32L152xx datasheets
// refer to STM32L162xx datasheet
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.2> DBG_STANDBY <i> Debug Standby mode
// <o.1> DBG_STOP <i> Debug Stop mode
// <o.0> DBG_SLEEP <i> Debug Sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> Debug RTC stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.4> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.3> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.2> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> Flash Download Options
// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
// </h>
DoOptionByteLoading = 0x00000000;
// <<< end of configuration section >>>

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// File: STM32L100_151_152_162.dbgconf
// Version: 1.0.0
// Note: refer to STM32L100xx STM32L151xx STM32L152xx STM32L162xx Reference manual (RM0038)
// refer to STM32L100xx datasheet
// refer to STM32L151xx STM32L152xx datasheets
// refer to STM32L162xx datasheet
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.2> DBG_STANDBY <i> Debug Standby mode
// <o.1> DBG_STOP <i> Debug Stop mode
// <o.0> DBG_SLEEP <i> Debug Sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> Debug RTC stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.4> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.3> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.2> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> Flash Download Options
// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
// </h>
DoOptionByteLoading = 0x00000000;
// <<< end of configuration section >>>

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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

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[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
}

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/*
* Copyright (c) 2013-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.5.1
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 23552
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 512
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 1024
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <h>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x01U
#endif
// <h>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x01U
#endif
// <h>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x05U
#endif
// <h>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x01U
#endif
// <h>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x01U
#endif
// <h>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x01U
#endif
// <h>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x01U
#endif
// <h>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x01U
#endif
// <h>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
#endif
// <h>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x01U
#endif
// <h>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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/*------------------------------------------------------------------------------
* MDK - Component ::Event Recorder
* Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: EventRecorderConf.h
* Purpose: Event Recorder Configuration
* Rev.: V1.1.0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Event Recorder
// <o>Number of Records
// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
// <65536=>65536
// <i>Configures size of Event Record Buffer (each record is 16 bytes)
// <i>Must be 2^n (min=8, max=65536)
#define EVENT_RECORD_COUNT 64U
// <o>Time Stamp Source
// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer
// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset)
// <i>Selects source for 32-bit time stamp
#define EVENT_TIMESTAMP_SOURCE 0
// <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
// <i>Defines initial time stamp clock frequency (0 when not used)
#define EVENT_TIMESTAMP_FREQ 0U
// </h>
//------------- <<< end of configuration section >>> ---------------------------

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/**
******************************************************************************
* @file system_stm32l1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l1xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l1xx_system
* @{
*/
/** @addtogroup STM32L1xx_System_Private_Includes
* @{
*/
#include "stm32l1xx.h"
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM32L152D_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 2097000U;
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range.
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
break;
case 0x04: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
}
else
{
/* HSE selected as PLL clock entry */
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in SystemInit() function before jump to main.
* This function configures the external SRAM mounted on STM32L152D_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg = 0;
/* Flash 1 wait state */
FLASH->ACR |= FLASH_ACR_LATENCY;
/* Power enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
/* Select the Voltage Range 1 (1.8 V) */
PWR->CR = PWR_CR_VOS_0;
/* Wait Until the Voltage Regulator is ready */
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
{
}
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
| PD15 <-> FSMC_D1 |--------------------+
+-------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHBENR = 0x000080D8;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CC00CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A0A;
/* Configure PDx pins speed to 40 MHz */
GPIOD->OSPEEDR = 0xFFFF0F0F;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 40 MHz */
GPIOE->OSPEEDR = 0xFFFFC00F;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 40 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x00000C00;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00200AAA;
/* Configure PGx pins speed to 40 MHz */
GPIOG->OSPEEDR = 0x00300FFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHBENR = 0x400080D8;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
(void)(tmpreg);
/* Configure and enable Bank1_SRAM3 */
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000300;
FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
/*
Bank1_SRAM3 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 3;
p.FSMC_BusTurnAroundDuration = 0;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
*/
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32l151xd.s
;* Author : MCD Application Team
;* Description : STM32L151XD Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD DAC_IRQHandler ; DAC
DCD COMP_IRQHandler ; COMP through EXTI Line
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT TIM11_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT COMP_ACQ_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
TIM11_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USB_FS_WKUP_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
COMP_ACQ_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/**
******************************************************************************
* @file system_stm32l1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l1xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l1xx_system
* @{
*/
/** @addtogroup STM32L1xx_System_Private_Includes
* @{
*/
#include "stm32l1xx.h"
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM32L152D_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 2097000U;
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range.
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
break;
case 0x04: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
}
else
{
/* HSE selected as PLL clock entry */
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in SystemInit() function before jump to main.
* This function configures the external SRAM mounted on STM32L152D_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg = 0;
/* Flash 1 wait state */
FLASH->ACR |= FLASH_ACR_LATENCY;
/* Power enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
/* Select the Voltage Range 1 (1.8 V) */
PWR->CR = PWR_CR_VOS_0;
/* Wait Until the Voltage Regulator is ready */
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
{
}
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
| PD15 <-> FSMC_D1 |--------------------+
+-------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHBENR = 0x000080D8;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CC00CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A0A;
/* Configure PDx pins speed to 40 MHz */
GPIOD->OSPEEDR = 0xFFFF0F0F;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 40 MHz */
GPIOE->OSPEEDR = 0xFFFFC00F;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 40 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x00000C00;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00200AAA;
/* Configure PGx pins speed to 40 MHz */
GPIOG->OSPEEDR = 0x00300FFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHBENR = 0x400080D8;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
(void)(tmpreg);
/* Configure and enable Bank1_SRAM3 */
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000300;
FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
/*
Bank1_SRAM3 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 3;
p.FSMC_BusTurnAroundDuration = 0;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
*/
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'STM32L1_Project'
* Target: 'Data_Acq'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l1xx.h"
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'STM32L1_Project'
* Target: 'Data_Acq'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l1xx.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.2 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'STM32L1_Project'
* Target: 'UART'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l1xx.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.2 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Data_Acq</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>STM32L151RD</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L1xx_DFP.1.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x08000000,0x00060000) IRAM(0x20000000,0x0000C000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L1xx_384 -FS08000000 -FL060000 -FP0($$Device:STM32L151RD$Flash/STM32L1xx_384.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32L151RD$Device/Include/stm32l1xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32L151RD$SVD/STM32L1xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>..\Output\</OutputDirectory>
<OutputName>APP</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin -o "$L@L.bin" "#L"</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0xc000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x60000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8010000</StartAddress>
<Size>0x50000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0xc000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>1</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\Driver;..\main;..\STM32L1xx_StdPeriph_Driver\inc;..\STM32L1xx_StdPeriph_Driver\src;..\Driver\spi;..\Driver\adc;..\Driver\temp;..\Driver\system\delay;..\Driver\system\sys;..\System;..\Driver\usart;..\Driver\bsp;..\Driver\pwr_ctrl;..\Driver\FATFS;..\Driver\FATFS\source;..\Driver\BC25;..\Driver\esp8266;..\Driver\eeprom;..\Driver\RTC;D:\Keil_v5\ARM\Pack\ARM\CMSIS\5.7.0\CMSIS\Include;..\Driver\process;..\Driver\sdi12;..\Driver\L76X;..\Driver\dwt;..\Driver\DS3231;..\Driver\IIC;.\RTE;.\RTE\_UART;D:\Keil_v5\ARM\Pack\Keil\STM32L1xx_DFP\1.3.0\Drivers\CMSIS\Device\ST\STM32L1xx\Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>startup</GroupName>
<Files>
<File>
<FileName>startup_stm32l1xx_hd.s</FileName>
<FileType>2</FileType>
<FilePath>.\startup_stm32l1xx_hd.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>stm32l_lib</GroupName>
<Files>
<File>
<FileName>misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\misc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_adc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_aes.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_aes.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_aes_util.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_aes_util.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_comp.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_comp.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_crc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_dac.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dac.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_dbgmcu.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dbgmcu.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_exti.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_fsmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_fsmc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_iwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_iwdg.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_lcd.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_lcd.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_opamp.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_opamp.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rtc.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_sdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_sdio.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_syscfg.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_tim.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_wwdg.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>main</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\main\main.c</FilePath>
</File>
<File>
<FileName>system_stm32l1xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\main\system_stm32l1xx.c</FilePath>
</File>
<File>
<FileName>stm32l1xx_it.c</FileName>
<FileType>1</FileType>
<FilePath>..\main\stm32l1xx_it.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>sys</GroupName>
<Files>
<File>
<FileName>delay.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\system\delay\delay.c</FilePath>
</File>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\system\sys\sys.c</FilePath>
</File>
<File>
<FileName>bsp_dwt.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\dwt\bsp_dwt.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>bsp</GroupName>
<Files>
<File>
<FileName>usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart.c</FilePath>
</File>
<File>
<FileName>bsp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\bsp\bsp.c</FilePath>
</File>
<File>
<FileName>adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\adc\adc.c</FilePath>
</File>
<File>
<FileName>pwr_ctrl.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\pwr_ctrl\pwr_ctrl.c</FilePath>
</File>
<File>
<FileName>spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\spi\spi.c</FilePath>
</File>
<File>
<FileName>SPI_SD_driver.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\spi\SPI_SD_driver.c</FilePath>
</File>
<File>
<FileName>usart3.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart3.c</FilePath>
</File>
<File>
<FileName>eeprom.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\eeprom\eeprom.c</FilePath>
</File>
<File>
<FileName>usart2.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart2.c</FilePath>
</File>
<File>
<FileName>rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\RTC\rtc.c</FilePath>
</File>
<File>
<FileName>usart1_sdi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart1_sdi.c</FilePath>
</File>
<File>
<FileName>usart4.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart4.c</FilePath>
</File>
<File>
<FileName>usart5.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\usart\usart5.c</FilePath>
</File>
<File>
<FileName>myiic.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\IIC\myiic.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>fatfs</GroupName>
<Files>
<File>
<FileName>data_handle.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\FATFS\data_handle.c</FilePath>
</File>
<File>
<FileName>ffsystem.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\FATFS\source\ffsystem.c</FilePath>
</File>
<File>
<FileName>ffunicode.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\FATFS\source\ffunicode.c</FilePath>
</File>
<File>
<FileName>diskio.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\FATFS\source\diskio.c</FilePath>
</File>
<File>
<FileName>ff.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\FATFS\source\ff.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>bc25</GroupName>
<Files>
<File>
<FileName>BC25.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\BC25\BC25.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>esp8266</GroupName>
<Files>
<File>
<FileName>esp8266.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\esp8266\esp8266.c</FilePath>
</File>
<File>
<FileName>tcp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\esp8266\tcp.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>L76C</GroupName>
<Files>
<File>
<FileName>L76X.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\L76X\L76X.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>sdi12</GroupName>
<Files>
<File>
<FileName>sdi12.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\sdi12\sdi12.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DS3231</GroupName>
<Files>
<File>
<FileName>DS3231.c</FileName>
<FileType>1</FileType>
<FilePath>..\Driver\DS3231\DS3231.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>0</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<packages>
<filter>
<targetInfos/>
</filter>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0">
<targetInfos>
<targetInfo name="Data_Acq" versionMatchMode="fixed"/>
</targetInfos>
</package>
<package name="STM32L1xx_DFP" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0">
<targetInfos>
<targetInfo name="Data_Acq" versionMatchMode="fixed"/>
</targetInfos>
</package>
</packages>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="Data_Acq"/>
</targetInfos>
</api>
</apis>
<components>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="Data_Acq"/>
</targetInfos>
</component>
<component Cbundle="Standalone" Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32L1 CMSIS">
<package name="STM32L1xx_DFP" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
<targetInfos>
<targetInfo excluded="1" name="Data_Acq" versionMatchMode=""/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="Data_Acq"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.1">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
<targetInfos>
<targetInfo name="Data_Acq"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.3"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="STM32L151xD ARMCC" name="Drivers\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l151xd.s" version="1.0.0">
<instance index="0" removed="1">RTE\Device\STM32L151RDTx\startup_stm32l151xd.s</instance>
<component Cbundle="Standalone" Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32L1 CMSIS"/>
<package name="STM32L1xx_DFP" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Drivers\CMSIS\Device\ST\STM32L1xx\Source\Templates\system_stm32l1xx.c" version="1.0.0">
<instance index="0" removed="1">RTE\Device\STM32L151RDTx\system_stm32l1xx.c</instance>
<component Cbundle="Standalone" Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32L1 CMSIS"/>
<package name="STM32L1xx_DFP" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Drivers\CMSIS\Device\ST\STM32L1xx\Source\Templates\system_stm32l1xx.c" version="1.0.0">
<instance index="0">RTE\Device\STM32L151RD\system_stm32l1xx.c</instance>
<component Cbundle="Standalone" Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32L1 CMSIS"/>
<package name="STM32L1xx_DFP" schemaVersion="1.6.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
<targetInfos>
<targetInfo excluded="1" name="Data_Acq"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>

64
RTX5_20220316/Project/UART.BAT Normal file
View File

@ -0,0 +1,64 @@
SET PATH=C:\Keil_v5\ARM\ARMCC\Bin;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\WINDOWS\System32\OpenSSH\;C:\Program Files (x86)\STMicroelectronics\STM32 ST-LINK Utility\ST-LINK Utility;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files\TortoiseSVN\bin;C:\Cadence\Cadence_SPB_16.6\openaccess\bin\win32\opt;C:\Cadence\Cadence_SPB_16.6\tools\capture;C:\Cadence\Cadence_SPB_16.6\tools\pspice;C:\Cadence\Cadence_SPB_16.6\tools\specctra\bin;C:\Cadence\Cadence_SPB_16.6\tools\fet\bin;C:\Cadence\Cadence_SPB_16.6\tools\libutil\bin;C:\Cadence\Cadence_SPB_16.6\tools\bin;C:\Cadence\Cadence_SPB_16.6\tools\pcb\bin;C:\Users\86139\AppData\Local\Microsoft\WindowsApps
SET CPU_TYPE=STM32L151RDTx
SET CPU_VENDOR=STMicroelectronics
SET UV2_TARGET=UART
SET CPU_CLOCK=0x007A1200
"C:\Keil_v5\ARM\ARMCC\Bin\ArmAsm" --Via "..\output\startup_stm32l1xx_hd._ia"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\misc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_adc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_aes.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_aes_util.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_comp.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_crc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_dac.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_dbgmcu.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_dma.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_exti.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_flash.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_fsmc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_gpio.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_i2c.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_iwdg.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_lcd.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_opamp.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_pwr.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_rcc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_rtc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_sdio.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_spi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_syscfg.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_tim.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_usart.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_wwdg.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\main.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\system_stm32l1xx.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\stm32l1xx_it.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\delay.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\sys.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\bsp_dwt.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\bsp.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\adc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\pwr_ctrl.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\spi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\spi_sd_driver.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart3.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\eeprom.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart2.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\rtc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart1_sdi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart4.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\usart5.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\data_handle.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\ff.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\diskio.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\bc25.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\esp8266.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\tcp.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\l76x.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\process.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\sdi12.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\rtx_lib.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "..\output\rtx_config.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmLink" --Via "..\Output\STM32L1_Project.lnp"
"C:\Keil_v5\ARM\ARMCC\Bin\fromelf.exe" "..\Output\STM32L1_Project.axf" --i32combined --output "..\Output\STM32L1_Project.hex"

449
RTX5_20220316/Project/irq_cm3.lst Normal file
View File

@ -0,0 +1,449 @@
ARM Macro Assembler Page 1
1 00000000 ;/*
2 00000000 ; * Copyright (c) 2013-2018 Arm Limited. All rights rese
rved.
3 00000000 ; *
4 00000000 ; * SPDX-License-Identifier: Apache-2.0
5 00000000 ; *
6 00000000 ; * Licensed under the Apache License, Version 2.0 (the
License); you may
7 00000000 ; * not use this file except in compliance with the Lice
nse.
8 00000000 ; * You may obtain a copy of the License at
9 00000000 ; *
10 00000000 ; * www.apache.org/licenses/LICENSE-2.0
11 00000000 ; *
12 00000000 ; * Unless required by applicable law or agreed to in wr
iting, software
13 00000000 ; * distributed under the License is distributed on an A
S IS BASIS, WITHOUT
14 00000000 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express
or implied.
15 00000000 ; * See the License for the specific language governing
permissions and
16 00000000 ; * limitations under the License.
17 00000000 ; *
18 00000000 ; * ----------------------------------------------------
-------------------------
19 00000000 ; *
20 00000000 ; * Project: CMSIS-RTOS RTX
21 00000000 ; * Title: Cortex-M3 Exception handlers
22 00000000 ; *
23 00000000 ; * ----------------------------------------------------
-------------------------
24 00000000 ; */
25 00000000
26 00000000
27 00000000 00000014
I_T_RUN_OFS
EQU 20 ; osRtxInfo.thread.
run offset
28 00000000 00000038
TCB_SP_OFS
EQU 56 ; TCB.SP offset
29 00000000
30 00000000
31 00000000 PRESERVE8
32 00000000 THUMB
33 00000000
34 00000000
35 00000000 AREA |.constdata|, DATA, READONLY
36 00000000 EXPORT irqRtxLib
37 00000000 00 irqRtxLib
DCB 0 ; Non weak library
reference
38 00000001
39 00000001
40 00000001 AREA |.text|, CODE, READONLY
41 00000000
42 00000000
43 00000000 SVC_Handler
ARM Macro Assembler Page 2
PROC
44 00000000 EXPORT SVC_Handler
45 00000000 IMPORT osRtxUserSVC
46 00000000 IMPORT osRtxInfo
47 00000000 IF :DEF:MPU_LOAD
49 ENDIF
50 00000000
51 00000000 F01E 0F04 TST LR,#0x04 ; Determine return
stack from EXC_RETU
RN bit 2
52 00000004 BF0C ITE EQ
53 00000006 F3EF 8008 MRSEQ R0,MSP ; Get MSP if return
stack is MSP
54 0000000A F3EF 8009 MRSNE R0,PSP ; Get PSP if return
stack is PSP
55 0000000E
56 0000000E 6981 LDR R1,[R0,#24] ; Load saved PC fro
m stack
57 00000010 F811 1C02 LDRB R1,[R1,#-2] ; Load SVC number
58 00000014 B9D9 CBNZ R1,SVC_User ; Branch if not SVC
0
59 00000016
60 00000016 B501 PUSH {R0,LR} ; Save SP and EXC_R
ETURN
61 00000018 E890 100F LDM R0,{R0-R3,R12} ; Load function
parameters and addr
ess from stack
62 0000001C 47E0 BLX R12 ; Call service func
tion
63 0000001E E8BD 5000 POP {R12,LR} ; Restore SP and EX
C_RETURN
64 00000022 E88C 0003 STM R12,{R0-R1} ; Store function re
turn values
65 00000026
66 00000026 SVC_Context
67 00000026 4B19 LDR R3,=osRtxInfo+I_T_RUN_OFS ; Loa
d address of osRtxI
nfo.run
68 00000028 E893 0006 LDM R3,{R1,R2} ; Load osRtxInfo.th
read.run: curr & ne
xt
69 0000002C 4291 CMP R1,R2 ; Check if thread s
witch is required
70 0000002E BF08 IT EQ
71 00000030 4770 BXEQ LR ; Exit when threads
are the same
72 00000032
73 00000032 B119 CBZ R1,SVC_ContextSwitch ; Branch i
f running thread is
deleted
74 00000034
75 00000034 SVC_ContextSave
76 00000034 E92C 0FF0 STMDB R12!,{R4-R11} ; Save R4..R11
77 00000038 F8C1 C038 STR R12,[R1,#TCB_SP_OFS] ; Store SP
78 0000003C
79 0000003C SVC_ContextSwitch
80 0000003C 601A STR R2,[R3] ; osRtxInfo.thread.
run: curr = next
ARM Macro Assembler Page 3
81 0000003E
82 0000003E IF :DEF:MPU_LOAD
87 ENDIF
88 0000003E
89 0000003E SVC_ContextRestore
90 0000003E 6B90 LDR R0,[R2,#TCB_SP_OFS] ; Load SP
91 00000040 E8B0 0FF0 LDMIA R0!,{R4-R11} ; Restore R4..R11
92 00000044 F380 8809 MSR PSP,R0 ; Set PSP
93 00000048
94 00000048 F06F 0E02 MVN LR,#~0xFFFFFFFD ; Set EXC_RETUR
N value
95 0000004C
96 0000004C SVC_Exit
97 0000004C 4770 BX LR ; Exit from handler
98 0000004E
99 0000004E SVC_User
100 0000004E 4A10 LDR R2,=osRtxUserSVC ; Load address
of SVC table
101 00000050 6813 LDR R3,[R2] ; Load SVC maximum
number
102 00000052 4299 CMP R1,R3 ; Check SVC number
range
103 00000054 D8FA BHI SVC_Exit ; Branch if out of
range
104 00000056
105 00000056 B501 PUSH {R0,LR} ; Save SP and EXC_R
ETURN
106 00000058 F852 C021 LDR R12,[R2,R1,LSL #2] ; Load addre
ss of SVC function
107 0000005C C80F LDM R0,{R0-R3} ; Load function par
ameters from stack
108 0000005E 47E0 BLX R12 ; Call service func
tion
109 00000060 E8BD 5000 POP {R12,LR} ; Restore SP and EX
C_RETURN
110 00000064 F8CC 0000 STR R0,[R12] ; Store function re
turn value
111 00000068
112 00000068 4770 BX LR ; Return from handl
er
113 0000006A
114 0000006A 00 00 ALIGN
115 0000006C ENDP
116 0000006C
117 0000006C
118 0000006C PendSV_Handler
PROC
119 0000006C EXPORT PendSV_Handler
120 0000006C IMPORT osRtxPendSV_Handler
121 0000006C
122 0000006C B501 PUSH {R0,LR} ; Save EXC_RETURN
123 0000006E F7FF FFFE BL osRtxPendSV_Handler ; Call osRt
xPendSV_Handler
124 00000072 E8BD 4001 POP {R0,LR} ; Restore EXC_RETUR
N
125 00000076 F3EF 8C09 MRS R12,PSP
126 0000007A E7D4 B SVC_Context
127 0000007C
ARM Macro Assembler Page 4
128 0000007C ALIGN
129 0000007C ENDP
130 0000007C
131 0000007C
132 0000007C SysTick_Handler
PROC
133 0000007C EXPORT SysTick_Handler
134 0000007C IMPORT osRtxTick_Handler
135 0000007C
136 0000007C B501 PUSH {R0,LR} ; Save EXC_RETURN
137 0000007E F7FF FFFE BL osRtxTick_Handler ; Call osRtxT
ick_Handler
138 00000082 E8BD 4001 POP {R0,LR} ; Restore EXC_RETUR
N
139 00000086 F3EF 8C09 MRS R12,PSP
140 0000008A E7CC B SVC_Context
141 0000008C
142 0000008C ALIGN
143 0000008C ENDP
144 0000008C
145 0000008C
146 0000008C END
00000014
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=..\output\irq_cm3.d -o..\output\irq_cm3.o -ID:\26<32><36><EFBFBD>ݲɼ<DDB2><C9BC><EFBFBD><EFBFBD><EFBFBD>\soft
ware\<5C><><EFBFBD>ӱ<EFBFBD>־λ<D6BE>ж<EFBFBD>\RTX5_20220316\Project\RTE -ID:\26<32><36><EFBFBD>ݲɼ<DDB2><C9BC><EFBFBD><EFBFBD><EFBFBD>\software\<5C><><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD>־λ<EFBFBD>ж<EFBFBD>\RTX5_20220316\Project\RTE\CMSIS -ID:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.
0\CMSIS\RTOS2\Include -ID:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\Inc
lude -ID:\Keil_v5\ARM\PACK\Keil\STM32L1xx_DFP\1.3.0 -ID:\Keil_v5\ARM\CMSIS\Incl
ude --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 514" --
predefine="_RTE_ SETA 1" --predefine="STM32L151xD SETA 1" --list=.\irq_cm3.lst
D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\Source\ARM\irq_cm3.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.constdata 00000000
Symbol: .constdata
Definitions
At line 35 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
None
Comment: .constdata unused
irqRtxLib 00000000
Symbol: irqRtxLib
Definitions
At line 37 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 36 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: irqRtxLib used once
2 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 40 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
None
Comment: .text unused
PendSV_Handler 0000006C
Symbol: PendSV_Handler
Definitions
At line 118 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Uses
At line 119 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: PendSV_Handler used once
SVC_Context 00000026
Symbol: SVC_Context
Definitions
At line 66 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 126 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
At line 140 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
SVC_ContextRestore 0000003E
Symbol: SVC_ContextRestore
Definitions
At line 89 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
None
Comment: SVC_ContextRestore unused
SVC_ContextSave 00000034
Symbol: SVC_ContextSave
Definitions
At line 75 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
None
Comment: SVC_ContextSave unused
SVC_ContextSwitch 0000003C
Symbol: SVC_ContextSwitch
Definitions
At line 79 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 73 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: SVC_ContextSwitch used once
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
SVC_Exit 0000004C
Symbol: SVC_Exit
Definitions
At line 96 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 103 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: SVC_Exit used once
SVC_Handler 00000000
Symbol: SVC_Handler
Definitions
At line 43 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 44 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: SVC_Handler used once
SVC_User 0000004E
Symbol: SVC_User
Definitions
At line 99 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 58 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: SVC_User used once
SysTick_Handler 0000007C
Symbol: SysTick_Handler
Definitions
At line 132 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Uses
At line 133 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: SysTick_Handler used once
10 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
I_T_RUN_OFS 00000014
Symbol: I_T_RUN_OFS
Definitions
At line 27 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 67 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: I_T_RUN_OFS used once
TCB_SP_OFS 00000038
Symbol: TCB_SP_OFS
Definitions
At line 28 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 77 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
At line 90 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
2 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
osRtxInfo 00000000
Symbol: osRtxInfo
Definitions
At line 46 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 67 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Comment: osRtxInfo used once
osRtxPendSV_Handler 00000000
Symbol: osRtxPendSV_Handler
Definitions
At line 120 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Uses
At line 123 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: osRtxPendSV_Handler used once
osRtxTick_Handler 00000000
Symbol: osRtxTick_Handler
Definitions
At line 134 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Uses
At line 137 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: osRtxTick_Handler used once
osRtxUserSVC 00000000
Symbol: osRtxUserSVC
Definitions
At line 45 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\So
urce\ARM\irq_cm3.s
Uses
At line 100 in file D:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\CMSIS\RTOS2\RTX\S
ource\ARM\irq_cm3.s
Comment: osRtxUserSVC used once
4 symbols
358 symbols in table

27
RTX5_20220316/Project/keilkilll.bat Normal file
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@ -0,0 +1,27 @@
del *.bak /s
del *.ddk /s
del *.edk /s
del *.lst /s
del *.lnp /s
del *.mpf /s
del *.mpj /s
del *.obj /s
del *.omf /s
::del *.opt /s ::<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɾ<EFBFBD><C9BE>JLINK<4E><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
del *.plg /s
del *.rpt /s
del *.tmp /s
del *.__i /s
del *.crf /s
del *.o /s
del *.d /s
del *.axf /s
del *.tra /s
del *.dep /s
del JLinkLog.txt /s
del *.iex /s
del *.htm /s
del *.sct /s
del *.map /s
exit

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;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32l1xx_hd.s
;* Author : MCD Application Team
;* Version : V1.3.3
;* Date : 20-April-2015
;* Description : STM32L1xx Ultra Low Power High-density Devices vector
;* table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00003000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD DAC_IRQHandler ; DAC
DCD COMP_IRQHandler ; COMP through EXTI Line
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD LCD_IRQHandler ; LCD
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD AES_IRQHandler ; AES
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT TIM11_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT COMP_ACQ_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
LCD_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
TIM11_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USB_FS_WKUP_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
AES_IRQHandler
COMP_ACQ_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32l1xx_md.s
;* Author : MCD Application Team
;* Version : V1.1.1
;* Date : 09-March-2012
;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector
;* table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD DAC_IRQHandler ; DAC
DCD COMP_IRQHandler ; COMP through EXTI Line
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD LCD_IRQHandler ; LCD
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT TIM11_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
LCD_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
TIM11_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USB_FS_WKUP_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****