// File: STM32L100_151_152_162.dbgconf // Version: 1.0.0 // Note: refer to STM32L100xx STM32L151xx STM32L152xx STM32L162xx Reference manual (RM0038) // refer to STM32L100xx datasheet // refer to STM32L151xx STM32L152xx datasheets // refer to STM32L162xx datasheet // <<< Use Configuration Wizard in Context Menu >>> // Debug MCU configuration register (DBGMCU_CR) // Reserved bits must be kept at reset value // DBG_STANDBY Debug Standby mode // DBG_STOP Debug Stop mode // DBG_SLEEP Debug Sleep mode // DbgMCU_CR = 0x00000007; // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) // Reserved bits must be kept at reset value // DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted // DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted // DBG_WWDG_STOP Debug window watchdog stopped when core is halted // DBG_RTC_STOP Debug RTC stopped when core is halted // DBG_TIM7_STOP TIM7 counter stopped when core is halted // DBG_TIM6_STOP TIM6 counter stopped when core is halted // DBG_TIM4_STOP TIM4 counter stopped when core is halted // DBG_TIM3_STOP TIM3 counter stopped when core is halted // DBG_TIM2_STOP TIM2 counter stopped when core is halted // DbgMCU_APB1_Fz = 0x00000000; // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) // Reserved bits must be kept at reset value // DBG_TIM11_STOP TIM11 counter stopped when core is halted // DBG_TIM10_STOP TIM10 counter stopped when core is halted // DBG_TIM9_STOP TIM9 counter stopped when core is halted // DbgMCU_APB2_Fz = 0x00000000; // Flash Download Options // Option Byte Loading Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset) // DoOptionByteLoading = 0x00000000; // <<< end of configuration section >>>