STM32L1xx Standard Peripherals Firmware Library: STM32L1xx Standard Peripherals Library

STM32L1xx Standard Peripherals Firmware Library
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STM32L1xx Standard Peripherals Library

STM32L1xx Standard Peripherals Library

Copyright 2012 STMicroelectronics

The STM32L1xx Standard Peripherals Library is a complete package, consisting of device drivers for all of the standard device peripherals, for STM32L Ultra Low Power High-, Medium-Density and Medium-Density Plus Devices 32-bit Flash microcontrollers.

This library is a firmware package which contains a collection of routines, data structures and macros covering the features of STM32L peripherals. It includes a description of the device drivers plus a set of examples for each peripheral. The firmware library allows any device to be used in the user application without the need for in-depth study of each peripheral’s specifications.

Using the Standard Peripherals Library has two advantages: it saves significant time that would otherwise be spent in coding, while simultaneously reducing application development and integration costs.

The STM32L1xx Standard Peripherals Library is full CMSIS compliant.

The manual is structured as follows:

Standard Peripherals Library

Overview

MISRA-C 2004 Compliance

Run-time Checking

Coding rules and conventions

Acronyms

Naming conventions

Coding rules

Bit-Banding

Description of Peripheral's driver and CMSIS files

Architecture

STM32L1xx Standard Peripheral's Drivers

STM32L1xx CMSIS files

Supported devices and toolchains

STM32 device peripherals overview

Supported STM32 devices

Supported toolchains

How to use the Library

How to use the Standard Peripherals Library

Peripheral initialization and configuration

Manual tab sheets description:

Modules: Lists the different modules that compose this Library.

Data Structures: Lists the variables, defines, structures, ...

Files: Lists all the files and global.

Directories: List of directories.

Release Notes for STM32L1xx Standard Peripherals Library

Limitations: STM32L1xx Standard Peripherals Library Limitations.

License

The use of this STM32 Firmware is governed by the terms and conditions of the License Agreement available in the root of this package.

STM32L1xx Standard Peripherals Library: Footer

For complete documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx Standard Peripheral's Drivers

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STM32L1xx Standard Peripheral's Drivers

src

  • misc.c
  • stm32l1xx_adc.c
  • stm32l1xx_aes.c
  • stm32l1xx_aes_util.c
  • stm32l1xx_comp.c
  • stm32l1xx_crc.c
  • stm32l1xx_dac.c
  • stm32l1xx_dbgmcu.c
  • stm32l1xx_dma.c
  • stm32l1xx_exti.c
  • stm32l1xx_flash.c
  • stm32l1xx_flash_ramfunc.c
  • stm32l1xx_fsmc.c
  • stm32l1xx_gpio.c
  • stm32l1xx_i2c.c
  • stm32l1xx_iwdg.c
  • stm32l1xx_lcd.c
  • stm32l1xx_opamp.c
  • stm32l1xx_pwr.c
  • stm32l1xx_rcc.c
  • stm32l1xx_rtc.c
  • stm32l1xx_sdio.c
  • stm32l1xx_spi.c
  • stm32l1xx_syscfg.c
  • stm32l1xx_tim.c
  • stm32l1xx_usart.c
  • stm32l1xx_wwdg.c

inc

  • misc.h
  • stm32l1xx_adc.h
  • stm32l1xx_aes.h
  • stm32l1xx_comp.h
  • stm32l1xx_crc.h
  • stm32l1xx_dac.h
  • stm32l1xx_dbgmcu.h
  • stm32l1xx_dma.h
  • stm32l1xx_exti.h
  • stm32l1xx_flash.h
  • stm32l1xx_fsmc.h
  • stm32l1xx_gpio.h
  • stm32l1xx_i2c.h
  • stm32l1xx_iwdg.h
  • stm32l1xx_lcd.h
  • stm32l1xx_opamp.h
  • stm32l1xx_pwr.h
  • stm32l1xx_rcc.h
  • stm32l1xx_rtc.h
  • stm32l1xx_sdio.h
  • stm32l1xx_spi.h
  • stm32l1xx_syscfg.h
  • stm32l1xx_tim.h
  • stm32l1xx_usart.h
  • stm32l1xx_wwdg.h


STM32L1xx Standard Peripherals Firmware Library: Library_configuration_section

  • Directories
Defines

Library_configuration_section

Stm32l1xx

Defines

#define | __STM32L1XX_STDPERIPH_VERSION
#define | __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01)
STM32L1xx Standard Peripheral Library version number V1.1.0.
#define | __STM32L1XX_STDPERIPH_VERSION_RC (0x00)
#define | __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01)
#define | __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00)
#define | HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.
#define | HSE_VALUE ((uint32_t)8000000)
Comment the line below if you will not use the peripherals drivers.
#define | HSI_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value.
#define | HSI_VALUE ((uint32_t)16000000)
#define | LSE_VALUE ((uint32_t)32768)
#define | LSI_VALUE ((uint32_t)37000)
#define | STM32L1XX_HD

Define Documentation

#define __STM32L1XX_STDPERIPH_VERSION
Value:
( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
                                             |(__STM32L1XX_STDPERIPH_VERSION_RC))

Definition at line 145 of file stm32l1xx.h.

#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01)

STM32L1xx Standard Peripheral Library version number V1.1.0.

[31:24] main version

Definition at line 141 of file stm32l1xx.h.

#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 144 of file stm32l1xx.h.

#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01)

[23:16] sub1 version

Definition at line 142 of file stm32l1xx.h.

#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00)

[15:8] sub2 version

Definition at line 143 of file stm32l1xx.h.

#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)

In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.

Time out for HSE start up

Definition at line 111 of file stm32l1xx.h.

Referenced by RCC_WaitForHSEStartUp(), and SetSysClock().

#define HSE_VALUE ((uint32_t)8000000)

Comment the line below if you will not use the peripherals drivers.

In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers In the following line adjust the value of External High Speed oscillator (HSE) used in your application

Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. Value of the External oscillator in Hz

Definition at line 103 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500)

In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value.

Time out for HSI start up

Definition at line 119 of file stm32l1xx.h.

#define HSI_VALUE ((uint32_t)16000000)

Value of the Internal High Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature.

Definition at line 123 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define LSE_VALUE ((uint32_t)32768)

Value of the External Low Speed oscillator in Hz

Definition at line 135 of file stm32l1xx.h.

#define LSI_VALUE ((uint32_t)37000)

Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.

Definition at line 129 of file stm32l1xx.h.

#define STM32L1XX_HD

< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices

< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices STM32L1XX_HD: STM32L Ultra Low Power High-density devices

Definition at line 69 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: Configuration_section_for_CMSIS

Defines | Typedefs | Enumerations

Configuration_section_for_CMSIS

Stm32l1xx

Defines

#define | __CM3_REV 0x200
STM32L1xx Interrupt Number Definition, according to the selected device in Library_configuration_section.
#define | __MPU_PRESENT 1
#define | __NVIC_PRIO_BITS 4
#define | __Vendor_SysTickConfig 0

Typedefs

typedef enum IRQn | IRQn_Type

Enumerations

enum IRQn {
NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
SVC_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3,
FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,
EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,
DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,
DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_IRQn = 18, USB_HP_IRQn = 19,
USB_LP_IRQn = 20, DAC_IRQn = 21, COMP_IRQn = 22, EXTI9_5_IRQn = 23,
LCD_IRQn = 24, TIM9_IRQn = 25, TIM10_IRQn = 26, TIM11_IRQn = 27,
TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35,
SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39,
EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, USB_FS_WKUP_IRQn = 42, TIM6_IRQn = 43,
TIM7_IRQn = 44, SDIO_IRQn = 45, TIM5_IRQn = 46, SPI3_IRQn = 47,
UART4_IRQn = 48, UART5_IRQn = 49, DMA2_Channel1_IRQn = 50, DMA2_Channel2_IRQn = 51,
DMA2_Channel3_IRQn = 52, DMA2_Channel4_IRQn = 53, DMA2_Channel5_IRQn = 54, AES_IRQn = 55,
COMP_ACQ_IRQn = 56
}

Define Documentation

#define __CM3_REV 0x200

STM32L1xx Interrupt Number Definition, according to the selected device in Library_configuration_section.

Cortex-M3 Revision r2p0

Definition at line 162 of file stm32l1xx.h.

#define __MPU_PRESENT 1

STM32L provides MPU

Definition at line 163 of file stm32l1xx.h.

#define __NVIC_PRIO_BITS 4

STM32 uses 4 Bits for the Priority Levels

Definition at line 164 of file stm32l1xx.h.

#define __Vendor_SysTickConfig 0

Set to 1 if different SysTick Config is used Interrupt Number Definition

Definition at line 165 of file stm32l1xx.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

Enumeration Type Documentation

enum IRQn
Enumerator:
NonMaskableInt_IRQn

2 Non Maskable Interrupt

MemoryManagement_IRQn

4 Cortex-M3 Memory Management Interrupt

BusFault_IRQn

5 Cortex-M3 Bus Fault Interrupt

UsageFault_IRQn

6 Cortex-M3 Usage Fault Interrupt

SVC_IRQn

11 Cortex-M3 SV Call Interrupt

DebugMonitor_IRQn

12 Cortex-M3 Debug Monitor Interrupt

PendSV_IRQn

14 Cortex-M3 Pend SV Interrupt

SysTick_IRQn

15 Cortex-M3 System Tick Interrupt

WWDG_IRQn

Window WatchDog Interrupt

PVD_IRQn

PVD through EXTI Line detection Interrupt

TAMPER_STAMP_IRQn

Tamper and Time Stamp through EXTI Line Interrupts

RTC_WKUP_IRQn

RTC Wakeup Timer through EXTI Line Interrupt

FLASH_IRQn

FLASH global Interrupt

RCC_IRQn

RCC global Interrupt

EXTI0_IRQn

EXTI Line0 Interrupt

EXTI1_IRQn

EXTI Line1 Interrupt

EXTI2_IRQn

EXTI Line2 Interrupt

EXTI3_IRQn

EXTI Line3 Interrupt

EXTI4_IRQn

EXTI Line4 Interrupt

DMA1_Channel1_IRQn

DMA1 Channel 1 global Interrupt

DMA1_Channel2_IRQn

DMA1 Channel 2 global Interrupt

DMA1_Channel3_IRQn

DMA1 Channel 3 global Interrupt

DMA1_Channel4_IRQn

DMA1 Channel 4 global Interrupt

DMA1_Channel5_IRQn

DMA1 Channel 5 global Interrupt

DMA1_Channel6_IRQn

DMA1 Channel 6 global Interrupt

DMA1_Channel7_IRQn

DMA1 Channel 7 global Interrupt

ADC1_IRQn

ADC1 global Interrupt

USB_HP_IRQn

USB High Priority Interrupt

USB_LP_IRQn

USB Low Priority Interrupt

DAC_IRQn

DAC Interrupt

COMP_IRQn

Comparator through EXTI Line Interrupt

EXTI9_5_IRQn

External Line[9:5] Interrupts

LCD_IRQn

LCD Interrupt

TIM9_IRQn

TIM9 global Interrupt

TIM10_IRQn

TIM10 global Interrupt

TIM11_IRQn

TIM11 global Interrupt

TIM2_IRQn

TIM2 global Interrupt

TIM3_IRQn

TIM3 global Interrupt

TIM4_IRQn

TIM4 global Interrupt

I2C1_EV_IRQn

I2C1 Event Interrupt

I2C1_ER_IRQn

I2C1 Error Interrupt

I2C2_EV_IRQn

I2C2 Event Interrupt

I2C2_ER_IRQn

I2C2 Error Interrupt

SPI1_IRQn

SPI1 global Interrupt

SPI2_IRQn

SPI2 global Interrupt

USART1_IRQn

USART1 global Interrupt

USART2_IRQn

USART2 global Interrupt

USART3_IRQn

USART3 global Interrupt

EXTI15_10_IRQn

External Line[15:10] Interrupts

RTC_Alarm_IRQn

RTC Alarm through EXTI Line Interrupt

USB_FS_WKUP_IRQn

USB FS WakeUp from suspend through EXTI Line Interrupt

TIM6_IRQn

TIM6 global Interrupt

TIM7_IRQn

TIM7 global Interrupt

SDIO_IRQn

SDIO global Interrupt

TIM5_IRQn

TIM5 global Interrupt

SPI3_IRQn

SPI3 global Interrupt

UART4_IRQn

UART4 global Interrupt

UART5_IRQn

UART5 global Interrupt

DMA2_Channel1_IRQn

DMA2 Channel 1 global Interrupt

DMA2_Channel2_IRQn

DMA2 Channel 2 global Interrupt

DMA2_Channel3_IRQn

DMA2 Channel 3 global Interrupt

DMA2_Channel4_IRQn

DMA2 Channel 4 global Interrupt

DMA2_Channel5_IRQn

DMA2 Channel 5 global Interrupt

AES_IRQn

AES global Interrupt

COMP_ACQ_IRQn

Comparator Channel Acquisition global Interrupt

Definition at line 168 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: Exported_types

Defines | Typedefs | Enumerations

Exported_types

Stm32l1xx

Defines

#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Typedefs

typedef enum FlagStatus | ITStatus

Enumerations

enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Define Documentation

#define IS_FUNCTIONAL_STATE ( STATE ) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Definition at line 274 of file stm32l1xx.h.

Referenced by ADC_AutoInjectedConvCmd(), ADC_Cmd(), ADC_ContinuousModeCmd(), ADC_DiscModeCmd(), ADC_DMACmd(), ADC_DMARequestAfterLastTransferCmd(), ADC_EOCOnEachRegularChannelCmd(), ADC_Init(), ADC_InjectedDiscModeCmd(), ADC_ITConfig(), ADC_PowerDownCmd(), ADC_TempSensorVrefintCmd(), AES_Cmd(), AES_ITConfig(), COMP_Cmd(), COMP_SW1SwitchConfig(), COMP_VrefintOutputCmd(), COMP_WindowCmd(), DAC_Cmd(), DAC_DMACmd(), DAC_DualSoftwareTriggerCmd(), DAC_ITConfig(), DAC_SoftwareTriggerCmd(), DAC_WaveGenerationCmd(), DATA_EEPROM_FixedTimeProgramCmd(), DBGMCU_APB1PeriphConfig(), DBGMCU_APB2PeriphConfig(), DBGMCU_Config(), DMA_Cmd(), DMA_ITConfig(), EXTI_Init(), FLASH_ITConfig(), FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), FLASH_OB_WRPConfig(), FLASH_PrefetchBufferCmd(), FLASH_ReadAccess64Cmd(), FLASH_SLEEPPowerDownCmd(), FSMC_NORSRAMCmd(), I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_Cmd(), I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_DualAddressCmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_ITConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), I2C_TransmitPEC(), I2S_Cmd(), LCD_Cmd(), LCD_HighDriveCmd(), LCD_ITConfig(), LCD_MuxSegmentCmd(), NVIC_Init(), NVIC_SystemLPConfig(), OPAMP_Cmd(), OPAMP_LowPowerCmd(), OPAMP_SwitchCmd(), PWR_EnterLowPowerRunMode(), PWR_FastWakeUpCmd(), PWR_PVDCmd(), PWR_RTCAccessCmd(), PWR_UltraLowPowerCmd(), PWR_WakeUpPinCmd(), RCC_AHBPeriphClockCmd(), RCC_AHBPeriphClockLPModeCmd(), RCC_AHBPeriphResetCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphClockLPModeCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphClockLPModeCmd(), RCC_APB2PeriphResetCmd(), RCC_ClockSecuritySystemCmd(), RCC_HSICmd(), RCC_ITConfig(), RCC_LSEClockSecuritySystemCmd(), RCC_LSICmd(), RCC_MSICmd(), RCC_PLLCmd(), RCC_RTCCLKCmd(), RCC_RTCResetCmd(), RTC_AlarmCmd(), RTC_BypassShadowCmd(), RTC_CalibOutputCmd(), RTC_CoarseCalibCmd(), RTC_ITConfig(), RTC_RefClockCmd(), RTC_TamperCmd(), RTC_TamperPullUpCmd(), RTC_TimeStampCmd(), RTC_TimeStampOnTamperDetectionCmd(), RTC_WakeUpCmd(), RTC_WriteProtectionCmd(), SDIO_CEATAITCmd(), SDIO_ClockCmd(), SDIO_CommandCompletionCmd(), SDIO_DMACmd(), SDIO_ITConfig(), SDIO_SendCEATACmd(), SDIO_SendSDIOSuspendCmd(), SDIO_SetSDIOOperation(), SDIO_StartSDIOReadWait(), SDIO_StopSDIOReadWait(), SPI_CalculateCRC(), SPI_Cmd(), SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_SSOutputCmd(), SYSCFG_RIHysteresisConfig(), SYSCFG_RIResistorConfig(), SYSCFG_RISwitchControlModeCmd(), SYSCFG_USBPuCmd(), TIM_ARRPreloadConfig(), TIM_Cmd(), TIM_DMACmd(), TIM_ITConfig(), TIM_SelectCCDMA(), TIM_SelectHallSensor(), TIM_UpdateDisableConfig(), USART_Cmd(), USART_DMACmd(), USART_HalfDuplexCmd(), USART_IrDACmd(), USART_ITConfig(), USART_LINCmd(), USART_OneBitMethodCmd(), USART_OverSampling8Cmd(), USART_ReceiverWakeUpCmd(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

Typedef Documentation

typedef enum FlagStatus ITStatus

Enumeration Type Documentation

enum ErrorStatus
Enumerator:
ERROR
SUCCESS

Definition at line 276 of file stm32l1xx.h.

enum FlagStatus
Enumerator:
RESET
SET

Definition at line 271 of file stm32l1xx.h.

enum FunctionalState
Enumerator:
DISABLE
ENABLE

Definition at line 273 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: ADC_Common_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_Common_TypeDef Struct Reference
Peripheral_registers_structures

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CCR
__IO uint32_t | CSR

Detailed Description

Definition at line 358 of file stm32l1xx.h.

Field Documentation

__IO uint32_t ADC_Common_TypeDef::CCR

ADC common control register, Address offset: ADC1 base address + 0x304

Definition at line 361 of file stm32l1xx.h.

__IO uint32_t ADC_Common_TypeDef::CSR

ADC common status register, Address offset: ADC1 base address + 0x300

Definition at line 360 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: ADC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_TypeDef Struct Reference
Peripheral_registers_structures

Analog to Digital Converter. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CR1
__IO uint32_t | CR2
__IO uint32_t | DR
__IO uint32_t | HTR
__IO uint32_t | JDR1
__IO uint32_t | JDR2
__IO uint32_t | JDR3
__IO uint32_t | JDR4
__IO uint32_t | JOFR1
__IO uint32_t | JOFR2
__IO uint32_t | JOFR3
__IO uint32_t | JOFR4
__IO uint32_t | JSQR
__IO uint32_t | LTR
__IO uint32_t | SMPR0
__IO uint32_t | SMPR1
__IO uint32_t | SMPR2
__IO uint32_t | SMPR3
__IO uint32_t | SQR1
__IO uint32_t | SQR2
__IO uint32_t | SQR3
__IO uint32_t | SQR4
__IO uint32_t | SQR5
__IO uint32_t | SR

Detailed Description

Analog to Digital Converter.

Definition at line 330 of file stm32l1xx.h.

Field Documentation

__IO uint32_t ADC_TypeDef::CR1

ADC control register 1, Address offset: 0x04

Definition at line 333 of file stm32l1xx.h.

Referenced by ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AutoInjectedConvCmd(), ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_GetITStatus(), ADC_Init(), ADC_InjectedDiscModeCmd(), ADC_ITConfig(), and ADC_PowerDownCmd().

__IO uint32_t ADC_TypeDef::CR2

ADC control register 2, Address offset: 0x08

Definition at line 334 of file stm32l1xx.h.

Referenced by ADC_BankSelection(), ADC_Cmd(), ADC_ContinuousModeCmd(), ADC_DelaySelectionConfig(), ADC_DMACmd(), ADC_DMARequestAfterLastTransferCmd(), ADC_EOCOnEachRegularChannelCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_ExternalTrigInjectedConvEdgeConfig(), ADC_GetSoftwareStartConvStatus(), ADC_GetSoftwareStartInjectedConvCmdStatus(), ADC_Init(), ADC_SoftwareStartConv(), and ADC_SoftwareStartInjectedConv().

__IO uint32_t ADC_TypeDef::DR

ADC regular data register, Address offset: 0x58

Definition at line 354 of file stm32l1xx.h.

Referenced by ADC_GetConversionValue().

__IO uint32_t ADC_TypeDef::HTR

ADC watchdog higher threshold register, Address offset: 0x28

Definition at line 342 of file stm32l1xx.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().

__IO uint32_t ADC_TypeDef::JDR1

ADC injected data register 1, Address offset: 0x48

Definition at line 350 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JDR2

ADC injected data register 2, Address offset: 0x4C

Definition at line 351 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JDR3

ADC injected data register 3, Address offset: 0x50

Definition at line 352 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JDR4

ADC injected data register 4, Address offset: 0x54

Definition at line 353 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JOFR1

ADC injected channel data offset register 1, Address offset: 0x18

Definition at line 338 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JOFR2

ADC injected channel data offset register 2, Address offset: 0x1C

Definition at line 339 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JOFR3

ADC injected channel data offset register 3, Address offset: 0x20

Definition at line 340 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JOFR4

ADC injected channel data offset register 4, Address offset: 0x24

Definition at line 341 of file stm32l1xx.h.

__IO uint32_t ADC_TypeDef::JSQR

ADC injected sequence register, Address offset: 0x44

Definition at line 349 of file stm32l1xx.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_InjectedSequencerLengthConfig().

__IO uint32_t ADC_TypeDef::LTR

ADC watchdog lower threshold register, Address offset: 0x2C

Definition at line 343 of file stm32l1xx.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().

__IO uint32_t ADC_TypeDef::SMPR0

ADC sample time register 0, Address offset: 0x5C

Definition at line 355 of file stm32l1xx.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SMPR1

ADC sample time register 1, Address offset: 0x0C

Definition at line 335 of file stm32l1xx.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SMPR2

ADC sample time register 2, Address offset: 0x10

Definition at line 336 of file stm32l1xx.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SMPR3

ADC sample time register 3, Address offset: 0x14

Definition at line 337 of file stm32l1xx.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR1

ADC regular sequence register 1, Address offset: 0x30

Definition at line 344 of file stm32l1xx.h.

Referenced by ADC_Init(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR2

ADC regular sequence register 2, Address offset: 0x34

Definition at line 345 of file stm32l1xx.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR3

ADC regular sequence register 3, Address offset: 0x38

Definition at line 346 of file stm32l1xx.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR4

ADC regular sequence register 4, Address offset: 0x3C

Definition at line 347 of file stm32l1xx.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR5

ADC regular sequence register 5, Address offset: 0x40

Definition at line 348 of file stm32l1xx.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SR

ADC status register, Address offset: 0x00

Definition at line 332 of file stm32l1xx.h.

Referenced by ADC_ClearFlag(), ADC_ClearITPendingBit(), ADC_GetFlagStatus(), and ADC_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: AES_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AES_TypeDef Struct Reference
Peripheral_registers_structures

AES hardware accelerator. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | DINR
__IO uint32_t | DOUTR
__IO uint32_t | IVR0
__IO uint32_t | IVR1
__IO uint32_t | IVR2
__IO uint32_t | IVR3
__IO uint32_t | KEYR0
__IO uint32_t | KEYR1
__IO uint32_t | KEYR2
__IO uint32_t | KEYR3
__IO uint32_t | SR

Detailed Description

AES hardware accelerator.

Definition at line 369 of file stm32l1xx.h.

Field Documentation

__IO uint32_t AES_TypeDef::CR

AES control register, Address offset: 0x00

Definition at line 371 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::DINR

AES data input register, Address offset: 0x08

Definition at line 373 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::DOUTR

AES data output register, Address offset: 0x0C

Definition at line 374 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::IVR0

AES initialization vector register 0, Address offset: 0x20

Definition at line 379 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::IVR1

AES initialization vector register 1, Address offset: 0x24

Definition at line 380 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::IVR2

AES initialization vector register 2, Address offset: 0x28

Definition at line 381 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::IVR3

AES initialization vector register 3, Address offset: 0x2C

Definition at line 382 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::KEYR0

AES key register 0, Address offset: 0x10

Definition at line 375 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::KEYR1

AES key register 1, Address offset: 0x14

Definition at line 376 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::KEYR2

AES key register 2, Address offset: 0x18

Definition at line 377 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::KEYR3

AES key register 3, Address offset: 0x1C

Definition at line 378 of file stm32l1xx.h.

__IO uint32_t AES_TypeDef::SR

AES status register, Address offset: 0x04

Definition at line 372 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: COMP_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

COMP_TypeDef Struct Reference
Peripheral_registers_structures

Comparator. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t CSR

Detailed Description

Comparator.

Definition at line 389 of file stm32l1xx.h.

Field Documentation

__IO uint32_t COMP_TypeDef::CSR

COMP comparator control and status register, Address offset: 0x00

Definition at line 391 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: CRC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CRC_TypeDef Struct Reference
Peripheral_registers_structures

CRC calculation unit. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | DR
__IO uint8_t | IDR
uint8_t | RESERVED0
uint16_t | RESERVED1

Detailed Description

CRC calculation unit.

Definition at line 398 of file stm32l1xx.h.

Field Documentation

__IO uint32_t CRC_TypeDef::CR

CRC Control register, Address offset: 0x08

Definition at line 404 of file stm32l1xx.h.

__IO uint32_t CRC_TypeDef::DR

CRC Data register, Address offset: 0x00

Definition at line 400 of file stm32l1xx.h.

__IO uint8_t CRC_TypeDef::IDR

CRC Independent data register, Address offset: 0x04

Definition at line 401 of file stm32l1xx.h.

uint8_t CRC_TypeDef::RESERVED0

Reserved, 0x05

Definition at line 402 of file stm32l1xx.h.

uint16_t CRC_TypeDef::RESERVED1

Reserved, 0x06

Definition at line 403 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: DAC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DAC_TypeDef Struct Reference
Peripheral_registers_structures

Digital to Analog Converter. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | DHR12L1
__IO uint32_t | DHR12L2
__IO uint32_t | DHR12LD
__IO uint32_t | DHR12R1
__IO uint32_t | DHR12R2
__IO uint32_t | DHR12RD
__IO uint32_t | DHR8R1
__IO uint32_t | DHR8R2
__IO uint32_t | DHR8RD
__IO uint32_t | DOR1
__IO uint32_t | DOR2
__IO uint32_t | SR
__IO uint32_t | SWTRIGR

Detailed Description

Digital to Analog Converter.

Definition at line 411 of file stm32l1xx.h.

Field Documentation

__IO uint32_t DAC_TypeDef::CR

DAC control register, Address offset: 0x00

Definition at line 413 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12L1

DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C

Definition at line 416 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12L2

DAC channel2 12-bit left aligned data holding register, Address offset: 0x18

Definition at line 419 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12LD

DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24

Definition at line 422 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12R1

DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08

Definition at line 415 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12R2

DAC channel2 12-bit right aligned data holding register, Address offset: 0x14

Definition at line 418 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR12RD

Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20

Definition at line 421 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR8R1

DAC channel1 8-bit right aligned data holding register, Address offset: 0x10

Definition at line 417 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR8R2

DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C

Definition at line 420 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DHR8RD

DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28

Definition at line 423 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DOR1

DAC channel1 data output register, Address offset: 0x2C

Definition at line 424 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::DOR2

DAC channel2 data output register, Address offset: 0x30

Definition at line 425 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::SR

DAC status register, Address offset: 0x34

Definition at line 426 of file stm32l1xx.h.

__IO uint32_t DAC_TypeDef::SWTRIGR

DAC software trigger register, Address offset: 0x04

Definition at line 414 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: DBGMCU_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DBGMCU_TypeDef Struct Reference
Peripheral_registers_structures

Debug MCU. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | APB1FZ
__IO uint32_t | APB2FZ
__IO uint32_t | CR
__IO uint32_t | IDCODE

Detailed Description

Debug MCU.

Definition at line 433 of file stm32l1xx.h.

Field Documentation

__IO uint32_t DBGMCU_TypeDef::APB1FZ

Debug MCU APB1 freeze register, Address offset: 0x08

Definition at line 437 of file stm32l1xx.h.

__IO uint32_t DBGMCU_TypeDef::APB2FZ

Debug MCU APB2 freeze register, Address offset: 0x0C

Definition at line 438 of file stm32l1xx.h.

__IO uint32_t DBGMCU_TypeDef::CR

Debug MCU configuration register, Address offset: 0x04

Definition at line 436 of file stm32l1xx.h.

__IO uint32_t DBGMCU_TypeDef::IDCODE

MCU device ID code, Address offset: 0x00

Definition at line 435 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: DMA_Channel_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_Channel_TypeDef Struct Reference
Peripheral_registers_structures

DMA Controller. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CCR
__IO uint32_t | CMAR
__IO uint32_t | CNDTR
__IO uint32_t | CPAR

Detailed Description

DMA Controller.

Definition at line 445 of file stm32l1xx.h.

Field Documentation

__IO uint32_t DMA_Channel_TypeDef::CCR

DMA channel x configuration register

Definition at line 447 of file stm32l1xx.h.

Referenced by DMA_Cmd(), DMA_DeInit(), DMA_Init(), and DMA_ITConfig().

__IO uint32_t DMA_Channel_TypeDef::CMAR

DMA channel x memory address register

Definition at line 450 of file stm32l1xx.h.

Referenced by DMA_DeInit(), and DMA_Init().

__IO uint32_t DMA_Channel_TypeDef::CNDTR

DMA channel x number of data register

Definition at line 448 of file stm32l1xx.h.

Referenced by DMA_DeInit(), DMA_GetCurrDataCounter(), DMA_Init(), and DMA_SetCurrDataCounter().

__IO uint32_t DMA_Channel_TypeDef::CPAR

DMA channel x peripheral address register

Definition at line 449 of file stm32l1xx.h.

Referenced by DMA_DeInit(), and DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: DMA_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_TypeDef Struct Reference
Peripheral_registers_structures

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | IFCR
__IO uint32_t | ISR

Detailed Description

Definition at line 453 of file stm32l1xx.h.

Field Documentation

__IO uint32_t DMA_TypeDef::IFCR

DMA interrupt flag clear register, Address offset: 0x04

Definition at line 456 of file stm32l1xx.h.

__IO uint32_t DMA_TypeDef::ISR

DMA interrupt status register, Address offset: 0x00

Definition at line 455 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: EXTI_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

EXTI_TypeDef Struct Reference
Peripheral_registers_structures

External Interrupt/Event Controller. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | EMR
__IO uint32_t | FTSR
__IO uint32_t | IMR
__IO uint32_t | PR
__IO uint32_t | RTSR
__IO uint32_t | SWIER

Detailed Description

External Interrupt/Event Controller.

Definition at line 463 of file stm32l1xx.h.

Field Documentation

__IO uint32_t EXTI_TypeDef::EMR

EXTI event mask register, Address offset: 0x04

Definition at line 466 of file stm32l1xx.h.

__IO uint32_t EXTI_TypeDef::FTSR

EXTI Falling edge trigger selection register, Address offset: 0x0C

Definition at line 468 of file stm32l1xx.h.

__IO uint32_t EXTI_TypeDef::IMR

EXTI interrupt mask register, Address offset: 0x00

Definition at line 465 of file stm32l1xx.h.

__IO uint32_t EXTI_TypeDef::PR

EXTI pending register, Address offset: 0x14

Definition at line 470 of file stm32l1xx.h.

__IO uint32_t EXTI_TypeDef::RTSR

EXTI rising edge trigger selection register, Address offset: 0x08

Definition at line 467 of file stm32l1xx.h.

__IO uint32_t EXTI_TypeDef::SWIER

EXTI software interrupt event register, Address offset: 0x10

Definition at line 469 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: FLASH_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FLASH_TypeDef Struct Reference
Peripheral_registers_structures

FLASH Registers. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | ACR
__IO uint32_t | OBR
__IO uint32_t | OPTKEYR
__IO uint32_t | PDKEYR
__IO uint32_t | PECR
__IO uint32_t | PEKEYR
__IO uint32_t | PRGKEYR
uint32_t | RESERVED [23]
__IO uint32_t | SR
__IO uint32_t | WRPR
__IO uint32_t | WRPR1
__IO uint32_t | WRPR2

Detailed Description

FLASH Registers.

Definition at line 477 of file stm32l1xx.h.

Field Documentation

__IO uint32_t FLASH_TypeDef::ACR

Access control register, Address offset: 0x00

Definition at line 479 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::OBR

Option byte register, Address offset: 0x1c

Definition at line 486 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::OPTKEYR

Option byte key register, Address offset: 0x14

Definition at line 484 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::PDKEYR

Power down key register, Address offset: 0x08

Definition at line 481 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::PECR

Program/erase control register, Address offset: 0x04

Definition at line 480 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::PEKEYR

Program/erase key register, Address offset: 0x0c

Definition at line 482 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::PRGKEYR

Program memory key register, Address offset: 0x10

Definition at line 483 of file stm32l1xx.h.

uint32_t FLASH_TypeDef::RESERVED[23]

Reserved, 0x24

Definition at line 488 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::SR

Status register, Address offset: 0x18

Definition at line 485 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::WRPR

Write protection register, Address offset: 0x20

Definition at line 487 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::WRPR1

Write protection register 1, Address offset: 0x28

Definition at line 489 of file stm32l1xx.h.

__IO uint32_t FLASH_TypeDef::WRPR2

Write protection register 2, Address offset: 0x2C

Definition at line 490 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: FSMC_Bank1_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank1_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t BTCR [8]

Detailed Description

Flexible Static Memory Controller.

Definition at line 524 of file stm32l1xx.h.

Field Documentation

__IO uint32_t FSMC_Bank1_TypeDef::BTCR[8]

NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C

Definition at line 526 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: FSMC_Bank1E_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank1E_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller Bank1E. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t BWTR [7]

Detailed Description

Flexible Static Memory Controller Bank1E.

Definition at line 533 of file stm32l1xx.h.

Field Documentation

__IO uint32_t FSMC_Bank1E_TypeDef::BWTR[7]

NOR/PSRAM write timing registers, Address offset: 0x104-0x11C

Definition at line 535 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: GPIO_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

GPIO_TypeDef Struct Reference
Peripheral_registers_structures

General Purpose IO. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | AFR [2]
__IO uint16_t | BRR
__IO uint16_t | BSRRH
__IO uint16_t | BSRRL
__IO uint16_t | IDR
__IO uint32_t | LCKR
__IO uint32_t | MODER
__IO uint16_t | ODR
__IO uint32_t | OSPEEDR
__IO uint16_t | OTYPER
__IO uint32_t | PUPDR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3

Detailed Description

General Purpose IO.

Definition at line 542 of file stm32l1xx.h.

Field Documentation

__IO uint32_t GPIO_TypeDef::AFR[2]

GPIO alternate function low register, Address offset: 0x20-0x24

Definition at line 556 of file stm32l1xx.h.

Referenced by GPIO_PinAFConfig().

__IO uint16_t GPIO_TypeDef::BRR

GPIO bit reset register, Address offset: 0x28

Definition at line 557 of file stm32l1xx.h.

__IO uint16_t GPIO_TypeDef::BSRRH

GPIO port bit set/reset high registerBSRR, Address offset: 0x1A

Definition at line 554 of file stm32l1xx.h.

Referenced by GPIO_ResetBits(), and GPIO_WriteBit().

__IO uint16_t GPIO_TypeDef::BSRRL

GPIO port bit set/reset low registerBSRR, Address offset: 0x18

Definition at line 553 of file stm32l1xx.h.

Referenced by GPIO_SetBits(), and GPIO_WriteBit().

__IO uint16_t GPIO_TypeDef::IDR

GPIO port input data register, Address offset: 0x10

Definition at line 549 of file stm32l1xx.h.

Referenced by GPIO_ReadInputData(), and GPIO_ReadInputDataBit().

__IO uint32_t GPIO_TypeDef::LCKR

GPIO port configuration lock register, Address offset: 0x1C

Definition at line 555 of file stm32l1xx.h.

Referenced by GPIO_PinLockConfig().

__IO uint32_t GPIO_TypeDef::MODER

GPIO port mode register, Address offset: 0x00

Definition at line 544 of file stm32l1xx.h.

Referenced by GPIO_Init().

__IO uint16_t GPIO_TypeDef::ODR

GPIO port output data register, Address offset: 0x14

Definition at line 551 of file stm32l1xx.h.

Referenced by GPIO_ReadOutputData(), GPIO_ReadOutputDataBit(), GPIO_ToggleBits(), and GPIO_Write().

__IO uint32_t GPIO_TypeDef::OSPEEDR

GPIO port output speed register, Address offset: 0x08

Definition at line 547 of file stm32l1xx.h.

Referenced by GPIO_Init().

__IO uint16_t GPIO_TypeDef::OTYPER

GPIO port output type register, Address offset: 0x04

Definition at line 545 of file stm32l1xx.h.

Referenced by GPIO_Init().

__IO uint32_t GPIO_TypeDef::PUPDR

GPIO port pull-up/pull-down register, Address offset: 0x0C

Definition at line 548 of file stm32l1xx.h.

Referenced by GPIO_Init().

uint16_t GPIO_TypeDef::RESERVED0

Reserved, 0x06

Definition at line 546 of file stm32l1xx.h.

uint16_t GPIO_TypeDef::RESERVED1

Reserved, 0x12

Definition at line 550 of file stm32l1xx.h.

uint16_t GPIO_TypeDef::RESERVED2

Reserved, 0x16

Definition at line 552 of file stm32l1xx.h.

uint16_t GPIO_TypeDef::RESERVED3

Reserved, 0x2A

Definition at line 558 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: I2C_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2C_TypeDef Struct Reference
Peripheral_registers_structures

Inter-integrated Circuit Interface. More...

#include <stm32l1xx.h>

Data Fields

__IO uint16_t | CCR
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | DR
__IO uint16_t | OAR1
__IO uint16_t | OAR2
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
__IO uint16_t | SR1
__IO uint16_t | SR2
__IO uint16_t | TRISE

Detailed Description

Inter-integrated Circuit Interface.

Definition at line 576 of file stm32l1xx.h.

Field Documentation

__IO uint16_t I2C_TypeDef::CCR

I2C Clock control register, Address offset: 0x1C

Definition at line 592 of file stm32l1xx.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

__IO uint16_t I2C_TypeDef::CR1

I2C Control register 1, Address offset: 0x00

Definition at line 578 of file stm32l1xx.h.

Referenced by I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_Cmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_Init(), I2C_NACKPositionConfig(), I2C_PECPositionConfig(), I2C_SMBusAlertConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), and I2C_TransmitPEC().

__IO uint16_t I2C_TypeDef::CR2

I2C Control register 2, Address offset: 0x04

Definition at line 580 of file stm32l1xx.h.

Referenced by I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_GetITStatus(), I2C_Init(), and I2C_ITConfig().

__IO uint16_t I2C_TypeDef::DR

I2C Data register, Address offset: 0x10

Definition at line 586 of file stm32l1xx.h.

Referenced by I2C_ReceiveData(), I2C_Send7bitAddress(), and I2C_SendData().

__IO uint16_t I2C_TypeDef::OAR1

I2C Own address register 1, Address offset: 0x08

Definition at line 582 of file stm32l1xx.h.

Referenced by I2C_Init().

__IO uint16_t I2C_TypeDef::OAR2

I2C Own address register 2, Address offset: 0x0C

Definition at line 584 of file stm32l1xx.h.

Referenced by I2C_DualAddressCmd(), and I2C_OwnAddress2Config().

uint16_t I2C_TypeDef::RESERVED0

Reserved, 0x02

Definition at line 579 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED1

Reserved, 0x06

Definition at line 581 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED2

Reserved, 0x0A

Definition at line 583 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED3

Reserved, 0x0E

Definition at line 585 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED4

Reserved, 0x12

Definition at line 587 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED5

Reserved, 0x16

Definition at line 589 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED6

Reserved, 0x1A

Definition at line 591 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED7

Reserved, 0x1E

Definition at line 593 of file stm32l1xx.h.

uint16_t I2C_TypeDef::RESERVED8

Reserved, 0x22

Definition at line 595 of file stm32l1xx.h.

__IO uint16_t I2C_TypeDef::SR1

I2C Status register 1, Address offset: 0x14

Definition at line 588 of file stm32l1xx.h.

Referenced by I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_GetITStatus(), and I2C_GetLastEvent().

__IO uint16_t I2C_TypeDef::SR2

I2C Status register 2, Address offset: 0x18

Definition at line 590 of file stm32l1xx.h.

Referenced by I2C_CheckEvent(), I2C_GetLastEvent(), and I2C_GetPEC().

__IO uint16_t I2C_TypeDef::TRISE

I2C TRISE register, Address offset: 0x20

Definition at line 594 of file stm32l1xx.h.

Referenced by I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: IWDG_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

IWDG_TypeDef Struct Reference
Peripheral_registers_structures

Independent WATCHDOG. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | KR
__IO uint32_t | PR
__IO uint32_t | RLR
__IO uint32_t | SR

Detailed Description

Independent WATCHDOG.

Definition at line 602 of file stm32l1xx.h.

Field Documentation

__IO uint32_t IWDG_TypeDef::KR

Key register, Address offset: 0x00

Definition at line 604 of file stm32l1xx.h.

__IO uint32_t IWDG_TypeDef::PR

Prescaler register, Address offset: 0x04

Definition at line 605 of file stm32l1xx.h.

__IO uint32_t IWDG_TypeDef::RLR

Reload register, Address offset: 0x08

Definition at line 606 of file stm32l1xx.h.

__IO uint32_t IWDG_TypeDef::SR

Status register, Address offset: 0x0C

Definition at line 607 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: LCD_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

LCD_TypeDef Struct Reference
Peripheral_registers_structures

LCD. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CLR
__IO uint32_t | CR
__IO uint32_t | FCR
__IO uint32_t | RAM [16]
uint32_t | RESERVED
__IO uint32_t | SR

Detailed Description

LCD.

Definition at line 615 of file stm32l1xx.h.

Field Documentation

__IO uint32_t LCD_TypeDef::CLR

LCD clear register, Address offset: 0x0C

Definition at line 620 of file stm32l1xx.h.

__IO uint32_t LCD_TypeDef::CR

LCD control register, Address offset: 0x00

Definition at line 617 of file stm32l1xx.h.

__IO uint32_t LCD_TypeDef::FCR

LCD frame control register, Address offset: 0x04

Definition at line 618 of file stm32l1xx.h.

__IO uint32_t LCD_TypeDef::RAM[16]

LCD display memory, Address offset: 0x14-0x50

Definition at line 622 of file stm32l1xx.h.

uint32_t LCD_TypeDef::RESERVED

Reserved, Address offset: 0x10

Definition at line 621 of file stm32l1xx.h.

__IO uint32_t LCD_TypeDef::SR

LCD status register, Address offset: 0x08

Definition at line 619 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: OB_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OB_TypeDef Struct Reference
Peripheral_registers_structures

Option Bytes Registers. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | RDP
__IO uint32_t | USER
__IO uint32_t | WRP01
__IO uint32_t | WRP1011
__IO uint32_t | WRP23
__IO uint32_t | WRP45
__IO uint32_t | WRP67
__IO uint32_t | WRP89

Detailed Description

Option Bytes Registers.

Definition at line 497 of file stm32l1xx.h.

Field Documentation

__IO uint32_t OB_TypeDef::RDP

Read protection register, Address offset: 0x00

Definition at line 499 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::USER

user register, Address offset: 0x04

Definition at line 500 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP01

write protection register 0 1, Address offset: 0x08

Definition at line 501 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP1011

write protection register 10 11, Address offset: 0x1C

Definition at line 506 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP23

write protection register 2 3, Address offset: 0x0C

Definition at line 502 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP45

write protection register 4 5, Address offset: 0x10

Definition at line 503 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP67

write protection register 6 7, Address offset: 0x14

Definition at line 504 of file stm32l1xx.h.

__IO uint32_t OB_TypeDef::WRP89

write protection register 8 9, Address offset: 0x18

Definition at line 505 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: OPAMP_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OPAMP_TypeDef Struct Reference
Peripheral_registers_structures

Operational Amplifier (OPAMP) More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CSR
__IO uint32_t | LPOTR
__IO uint32_t | OTR

Detailed Description

Operational Amplifier (OPAMP)

Definition at line 513 of file stm32l1xx.h.

Field Documentation

__IO uint32_t OPAMP_TypeDef::CSR

OPAMP control/status register, Address offset: 0x00

Definition at line 515 of file stm32l1xx.h.

__IO uint32_t OPAMP_TypeDef::LPOTR

OPAMP offset trimming register for low power mode, Address offset: 0x08

Definition at line 517 of file stm32l1xx.h.

__IO uint32_t OPAMP_TypeDef::OTR

OPAMP offset trimming register for normal mode, Address offset: 0x04

Definition at line 516 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: PWR_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

PWR_TypeDef Struct Reference
Peripheral_registers_structures

Power Control. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | CSR

Detailed Description

Power Control.

Definition at line 629 of file stm32l1xx.h.

Field Documentation

__IO uint32_t PWR_TypeDef::CR

PWR power control register, Address offset: 0x00

Definition at line 631 of file stm32l1xx.h.

__IO uint32_t PWR_TypeDef::CSR

PWR power control/status register, Address offset: 0x04

Definition at line 632 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: RCC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RCC_TypeDef Struct Reference
Peripheral_registers_structures

Reset and Clock Control. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | AHBENR
__IO uint32_t | AHBLPENR
__IO uint32_t | AHBRSTR
__IO uint32_t | APB1ENR
__IO uint32_t | APB1LPENR
__IO uint32_t | APB1RSTR
__IO uint32_t | APB2ENR
__IO uint32_t | APB2LPENR
__IO uint32_t | APB2RSTR
__IO uint32_t | CFGR
__IO uint32_t | CIR
__IO uint32_t | CR
__IO uint32_t | CSR
__IO uint32_t | ICSCR

Detailed Description

Reset and Clock Control.

Definition at line 639 of file stm32l1xx.h.

Field Documentation

__IO uint32_t RCC_TypeDef::AHBENR

RCC AHB peripheral clock enable register, Address offset: 0x1C

Definition at line 648 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::AHBLPENR

RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28

Definition at line 651 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::AHBRSTR

RCC AHB peripheral reset register, Address offset: 0x10

Definition at line 645 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB1ENR

RCC APB1 peripheral clock enable register, Address offset: 0x24

Definition at line 650 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB1LPENR

RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30

Definition at line 653 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB1RSTR

RCC APB1 peripheral reset register, Address offset: 0x18

Definition at line 647 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB2ENR

RCC APB2 peripheral clock enable register, Address offset: 0x20

Definition at line 649 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB2LPENR

RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C

Definition at line 652 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x14

Definition at line 646 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::CFGR

RCC Clock configuration register, Address offset: 0x08

Definition at line 643 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::CIR

RCC Clock interrupt register, Address offset: 0x0C

Definition at line 644 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::CR

RCC clock control register, Address offset: 0x00

Definition at line 641 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::CSR

RCC Control/status register, Address offset: 0x34

Definition at line 654 of file stm32l1xx.h.

__IO uint32_t RCC_TypeDef::ICSCR

RCC Internal clock sources calibration register, Address offset: 0x04

Definition at line 642 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: RI_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RI_TypeDef Struct Reference
Peripheral_registers_structures

Routing Interface. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | ASCR1
__IO uint32_t | ASCR2
__IO uint32_t | HYSCR1
__IO uint32_t | HYSCR2
__IO uint32_t | HYSCR3
__IO uint32_t | HYSCR4
__IO uint32_t | ICR

Detailed Description

Routing Interface.

Definition at line 661 of file stm32l1xx.h.

Field Documentation

__IO uint32_t RI_TypeDef::ASCR1

RI analog switches control register, Address offset: 0x04

Definition at line 664 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::ASCR2

RI analog switch control register 2, Address offset: 0x08

Definition at line 665 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::HYSCR1

RI hysteresis control register, Address offset: 0x0C

Definition at line 666 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::HYSCR2

RI Hysteresis control register, Address offset: 0x10

Definition at line 667 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::HYSCR3

RI Hysteresis control register, Address offset: 0x14

Definition at line 668 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::HYSCR4

RI Hysteresis control register, Address offset: 0x18

Definition at line 669 of file stm32l1xx.h.

__IO uint32_t RI_TypeDef::ICR

RI input capture register, Address offset: 0x00

Definition at line 663 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: RTC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_TypeDef Struct Reference
Peripheral_registers_structures

Real-Time Clock. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | ALRMAR
__IO uint32_t | ALRMASSR
__IO uint32_t | ALRMBR
__IO uint32_t | ALRMBSSR
__IO uint32_t | BKP0R
__IO uint32_t | BKP10R
__IO uint32_t | BKP11R
__IO uint32_t | BKP12R
__IO uint32_t | BKP13R
__IO uint32_t | BKP14R
__IO uint32_t | BKP15R
__IO uint32_t | BKP16R
__IO uint32_t | BKP17R
__IO uint32_t | BKP18R
__IO uint32_t | BKP19R
__IO uint32_t | BKP1R
__IO uint32_t | BKP20R
__IO uint32_t | BKP21R
__IO uint32_t | BKP22R
__IO uint32_t | BKP23R
__IO uint32_t | BKP24R
__IO uint32_t | BKP25R
__IO uint32_t | BKP26R
__IO uint32_t | BKP27R
__IO uint32_t | BKP28R
__IO uint32_t | BKP29R
__IO uint32_t | BKP2R
__IO uint32_t | BKP30R
__IO uint32_t | BKP31R
__IO uint32_t | BKP3R
__IO uint32_t | BKP4R
__IO uint32_t | BKP5R
__IO uint32_t | BKP6R
__IO uint32_t | BKP7R
__IO uint32_t | BKP8R
__IO uint32_t | BKP9R
__IO uint32_t | CALIBR
__IO uint32_t | CALR
__IO uint32_t | CR
__IO uint32_t | DR
__IO uint32_t | ISR
__IO uint32_t | PRER
uint32_t | RESERVED7
__IO uint32_t | SHIFTR
__IO uint32_t | SSR
__IO uint32_t | TAFCR
__IO uint32_t | TR
__IO uint32_t | TSDR
__IO uint32_t | TSSSR
__IO uint32_t | TSTR
__IO uint32_t | WPR
__IO uint32_t | WUTR

Detailed Description

Real-Time Clock.

Definition at line 676 of file stm32l1xx.h.

Field Documentation

__IO uint32_t RTC_TypeDef::ALRMAR

RTC alarm A register, Address offset: 0x1C

Definition at line 685 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::ALRMASSR

RTC alarm A sub second register, Address offset: 0x44

Definition at line 695 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::ALRMBR

RTC alarm B register, Address offset: 0x20

Definition at line 686 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::ALRMBSSR

RTC alarm B sub second register, Address offset: 0x48

Definition at line 696 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP0R

RTC backup register 0, Address offset: 0x50

Definition at line 698 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP10R

RTC backup register 10, Address offset: 0x78

Definition at line 708 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP11R

RTC backup register 11, Address offset: 0x7C

Definition at line 709 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP12R

RTC backup register 12, Address offset: 0x80

Definition at line 710 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP13R

RTC backup register 13, Address offset: 0x84

Definition at line 711 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP14R

RTC backup register 14, Address offset: 0x88

Definition at line 712 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP15R

RTC backup register 15, Address offset: 0x8C

Definition at line 713 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP16R

RTC backup register 16, Address offset: 0x90

Definition at line 714 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP17R

RTC backup register 17, Address offset: 0x94

Definition at line 715 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP18R

RTC backup register 18, Address offset: 0x98

Definition at line 716 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP19R

RTC backup register 19, Address offset: 0x9C

Definition at line 717 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP1R

RTC backup register 1, Address offset: 0x54

Definition at line 699 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP20R

RTC backup register 20, Address offset: 0xA0

Definition at line 718 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP21R

RTC backup register 21, Address offset: 0xA4

Definition at line 719 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP22R

RTC backup register 22, Address offset: 0xA8

Definition at line 720 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP23R

RTC backup register 23, Address offset: 0xAC

Definition at line 721 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP24R

RTC backup register 24, Address offset: 0xB0

Definition at line 722 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP25R

RTC backup register 25, Address offset: 0xB4

Definition at line 723 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP26R

RTC backup register 26, Address offset: 0xB8

Definition at line 724 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP27R

RTC backup register 27, Address offset: 0xBC

Definition at line 725 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP28R

RTC backup register 28, Address offset: 0xC0

Definition at line 726 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP29R

RTC backup register 29, Address offset: 0xC4

Definition at line 727 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP2R

RTC backup register 2, Address offset: 0x58

Definition at line 700 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP30R

RTC backup register 30, Address offset: 0xC8

Definition at line 728 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP31R

RTC backup register 31, Address offset: 0xCC

Definition at line 729 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP3R

RTC backup register 3, Address offset: 0x5C

Definition at line 701 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP4R

RTC backup register 4, Address offset: 0x60

Definition at line 702 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP5R

RTC backup register 5, Address offset: 0x64

Definition at line 703 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP6R

RTC backup register 6, Address offset: 0x68

Definition at line 704 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP7R

RTC backup register 7, Address offset: 0x6C

Definition at line 705 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP8R

RTC backup register 8, Address offset: 0x70

Definition at line 706 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::BKP9R

RTC backup register 9, Address offset: 0x74

Definition at line 707 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::CALIBR

RTC calibration register, Address offset: 0x18

Definition at line 684 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::CALR

RRTC calibration register, Address offset: 0x3C

Definition at line 693 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::CR

RTC control register, Address offset: 0x08

Definition at line 680 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::DR

RTC date register, Address offset: 0x04

Definition at line 679 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::ISR

RTC initialization and status register, Address offset: 0x0C

Definition at line 681 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::PRER

RTC prescaler register, Address offset: 0x10

Definition at line 682 of file stm32l1xx.h.

uint32_t RTC_TypeDef::RESERVED7

Reserved, 0x4C

Definition at line 697 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::SHIFTR

RTC shift control register, Address offset: 0x2C

Definition at line 689 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::SSR

RTC sub second register, Address offset: 0x28

Definition at line 688 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::TAFCR

RTC tamper and alternate function configuration register, Address offset: 0x40

Definition at line 694 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::TR

RTC time register, Address offset: 0x00

Definition at line 678 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::TSDR

RTC time stamp date register, Address offset: 0x34

Definition at line 691 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::TSSSR

RTC time-stamp sub second register, Address offset: 0x38

Definition at line 692 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::TSTR

RTC time stamp time register, Address offset: 0x30

Definition at line 690 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::WPR

RTC write protection register, Address offset: 0x24

Definition at line 687 of file stm32l1xx.h.

__IO uint32_t RTC_TypeDef::WUTR

RTC wakeup timer register, Address offset: 0x14

Definition at line 683 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: SDIO_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_TypeDef Struct Reference
Peripheral_registers_structures

SD host Interface. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | ARG
__IO uint32_t | CLKCR
__IO uint32_t | CMD
__I uint32_t | DCOUNT
__IO uint32_t | DCTRL
__IO uint32_t | DLEN
__IO uint32_t | DTIMER
__IO uint32_t | FIFO
__I uint32_t | FIFOCNT
__IO uint32_t | ICR
__IO uint32_t | MASK
__IO uint32_t | POWER
uint32_t | RESERVED0 [2]
uint32_t | RESERVED1 [13]
__I uint32_t | RESP1
__I uint32_t | RESP2
__I uint32_t | RESP3
__I uint32_t | RESP4
__I uint32_t | RESPCMD
__I uint32_t | STA

Detailed Description

SD host Interface.

Definition at line 736 of file stm32l1xx.h.

Field Documentation

__IO uint32_t SDIO_TypeDef::ARG

SDIO argument register, Address offset: 0x08

Definition at line 740 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::CLKCR

SDI clock control register, Address offset: 0x04

Definition at line 739 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::CMD

SDIO command register, Address offset: 0x0C

Definition at line 741 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::DCOUNT

SDIO data counter register, Address offset: 0x30

Definition at line 750 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::DCTRL

SDIO data control register, Address offset: 0x2C

Definition at line 749 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::DLEN

SDIO data length register, Address offset: 0x28

Definition at line 748 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::DTIMER

SDIO data timer register, Address offset: 0x24

Definition at line 747 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::FIFO

SDIO data FIFO register, Address offset: 0x80

Definition at line 757 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::FIFOCNT

SDIO FIFO counter register, Address offset: 0x48

Definition at line 755 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::ICR

SDIO interrupt clear register, Address offset: 0x38

Definition at line 752 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::MASK

SDIO mask register, Address offset: 0x3C

Definition at line 753 of file stm32l1xx.h.

__IO uint32_t SDIO_TypeDef::POWER

SDIO power control register, Address offset: 0x00

Definition at line 738 of file stm32l1xx.h.

uint32_t SDIO_TypeDef::RESERVED0[2]

Reserved, 0x40-0x44

Definition at line 754 of file stm32l1xx.h.

uint32_t SDIO_TypeDef::RESERVED1[13]

Reserved, 0x4C-0x7C

Definition at line 756 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::RESP1

SDIO response 1 register, Address offset: 0x14

Definition at line 743 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::RESP2

SDIO response 2 register, Address offset: 0x18

Definition at line 744 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::RESP3

SDIO response 3 register, Address offset: 0x1C

Definition at line 745 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::RESP4

SDIO response 4 register, Address offset: 0x20

Definition at line 746 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::RESPCMD

SDIO command response register, Address offset: 0x10

Definition at line 742 of file stm32l1xx.h.

__I uint32_t SDIO_TypeDef::STA

SDIO status register, Address offset: 0x34

Definition at line 751 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: SPI_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SPI_TypeDef Struct Reference
Peripheral_registers_structures

Serial Peripheral Interface. More...

#include <stm32l1xx.h>

Data Fields

__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | CRCPR
__IO uint16_t | DR
__IO uint16_t | I2SCFGR
__IO uint16_t | I2SPR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
__IO uint16_t | RXCRCR
__IO uint16_t | SR
__IO uint16_t | TXCRCR

Detailed Description

Serial Peripheral Interface.

Definition at line 764 of file stm32l1xx.h.

Field Documentation

__IO uint16_t SPI_TypeDef::CR1

SPI control register 1 (not used in I2S mode), Address offset: 0x00

Definition at line 766 of file stm32l1xx.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRC(), SPI_Cmd(), SPI_DataSizeConfig(), SPI_Init(), SPI_NSSInternalSoftwareConfig(), and SPI_TransmitCRC().

__IO uint16_t SPI_TypeDef::CR2

SPI control register 2, Address offset: 0x04

Definition at line 768 of file stm32l1xx.h.

Referenced by SPI_I2S_DMACmd(), SPI_I2S_GetITStatus(), SPI_I2S_ITConfig(), and SPI_SSOutputCmd().

__IO uint16_t SPI_TypeDef::CRCPR

SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10

Definition at line 774 of file stm32l1xx.h.

Referenced by SPI_GetCRCPolynomial(), and SPI_Init().

__IO uint16_t SPI_TypeDef::DR

SPI data register, Address offset: 0x0C

Definition at line 772 of file stm32l1xx.h.

Referenced by SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

__IO uint16_t SPI_TypeDef::I2SCFGR

SPI_I2S configuration register, Address offset: 0x1C

Definition at line 780 of file stm32l1xx.h.

Referenced by I2S_Cmd(), I2S_Init(), and SPI_Init().

__IO uint16_t SPI_TypeDef::I2SPR

SPI_I2S prescaler register, Address offset: 0x20

Definition at line 782 of file stm32l1xx.h.

Referenced by I2S_Init().

uint16_t SPI_TypeDef::RESERVED0

Reserved, 0x02

Definition at line 767 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED1

Reserved, 0x06

Definition at line 769 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED2

Reserved, 0x0A

Definition at line 771 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED3

Reserved, 0x0E

Definition at line 773 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED4

Reserved, 0x12

Definition at line 775 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED5

Reserved, 0x16

Definition at line 777 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED6

Reserved, 0x1A

Definition at line 779 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED7

Reserved, 0x1E

Definition at line 781 of file stm32l1xx.h.

uint16_t SPI_TypeDef::RESERVED8

Reserved, 0x22

Definition at line 783 of file stm32l1xx.h.

__IO uint16_t SPI_TypeDef::RXCRCR

SPI RX CRC register (not used in I2S mode), Address offset: 0x14

Definition at line 776 of file stm32l1xx.h.

Referenced by SPI_GetCRC().

__IO uint16_t SPI_TypeDef::SR

SPI status register, Address offset: 0x08

Definition at line 770 of file stm32l1xx.h.

Referenced by SPI_I2S_ClearFlag(), SPI_I2S_ClearITPendingBit(), SPI_I2S_GetFlagStatus(), and SPI_I2S_GetITStatus().

__IO uint16_t SPI_TypeDef::TXCRCR

SPI TX CRC register (not used in I2S mode), Address offset: 0x18

Definition at line 778 of file stm32l1xx.h.

Referenced by SPI_GetCRC().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: SYSCFG_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SYSCFG_TypeDef Struct Reference
Peripheral_registers_structures

SysTem Configuration. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | EXTICR [4]
__IO uint32_t | MEMRMP
__IO uint32_t | PMC

Detailed Description

SysTem Configuration.

Definition at line 565 of file stm32l1xx.h.

Field Documentation

__IO uint32_t SYSCFG_TypeDef::EXTICR[4]

SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14

Definition at line 569 of file stm32l1xx.h.

__IO uint32_t SYSCFG_TypeDef::MEMRMP

SYSCFG memory remap register, Address offset: 0x00

Definition at line 567 of file stm32l1xx.h.

__IO uint32_t SYSCFG_TypeDef::PMC

SYSCFG peripheral mode configuration register, Address offset: 0x04

Definition at line 568 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: TIM_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_TypeDef Struct Reference
Peripheral_registers_structures

TIM. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | ARR
__IO uint16_t | CCER
__IO uint16_t | CCMR1
__IO uint16_t | CCMR2
__IO uint32_t | CCR1
__IO uint32_t | CCR2
__IO uint32_t | CCR3
__IO uint32_t | CCR4
__IO uint32_t | CNT
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | DCR
__IO uint16_t | DIER
__IO uint16_t | DMAR
__IO uint16_t | EGR
__IO uint16_t | OR
__IO uint16_t | PSC
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED10
uint32_t | RESERVED12
uint32_t | RESERVED17
uint16_t | RESERVED18
uint16_t | RESERVED19
uint16_t | RESERVED2
uint16_t | RESERVED20
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
__IO uint16_t | SMCR
__IO uint16_t | SR

Detailed Description

TIM.

Definition at line 790 of file stm32l1xx.h.

Field Documentation

__IO uint32_t TIM_TypeDef::ARR

TIM auto-reload register, Address offset: 0x2C

Definition at line 813 of file stm32l1xx.h.

Referenced by TIM_SetAutoreload(), and TIM_TimeBaseInit().

__IO uint16_t TIM_TypeDef::CCER

TIM capture/compare enable register, Address offset: 0x20

Definition at line 808 of file stm32l1xx.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM_CCxCmd(), TIM_EncoderInterfaceConfig(), TIM_OC1Init(), TIM_OC1PolarityConfig(), TIM_OC2Init(), TIM_OC2PolarityConfig(), TIM_OC3Init(), TIM_OC3PolarityConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), and TIM_SelectOCxM().

__IO uint16_t TIM_TypeDef::CCMR1

TIM capture/compare mode register 1, Address offset: 0x18

Definition at line 804 of file stm32l1xx.h.

Referenced by TI1_Config(), TI2_Config(), TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_EncoderInterfaceConfig(), TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

__IO uint16_t TIM_TypeDef::CCMR2

TIM capture/compare mode register 2, Address offset: 0x1C

Definition at line 806 of file stm32l1xx.h.

Referenced by TI3_Config(), TI4_Config(), TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

__IO uint32_t TIM_TypeDef::CCR1

TIM capture/compare register 1, Address offset: 0x34

Definition at line 815 of file stm32l1xx.h.

Referenced by TIM_GetCapture1(), TIM_OC1Init(), and TIM_SetCompare1().

__IO uint32_t TIM_TypeDef::CCR2

TIM capture/compare register 2, Address offset: 0x38

Definition at line 816 of file stm32l1xx.h.

Referenced by TIM_GetCapture2(), TIM_OC2Init(), and TIM_SetCompare2().

__IO uint32_t TIM_TypeDef::CCR3

TIM capture/compare register 3, Address offset: 0x3C

Definition at line 817 of file stm32l1xx.h.

Referenced by TIM_GetCapture3(), TIM_OC3Init(), and TIM_SetCompare3().

__IO uint32_t TIM_TypeDef::CCR4

TIM capture/compare register 4, Address offset: 0x40

Definition at line 818 of file stm32l1xx.h.

Referenced by TIM_GetCapture4(), TIM_OC4Init(), and TIM_SetCompare4().

__IO uint32_t TIM_TypeDef::CNT

TIM counter register, Address offset: 0x24

Definition at line 810 of file stm32l1xx.h.

Referenced by TIM_GetCounter(), and TIM_SetCounter().

__IO uint16_t TIM_TypeDef::CR1

TIM control register 1, Address offset: 0x00

Definition at line 792 of file stm32l1xx.h.

Referenced by TIM_ARRPreloadConfig(), TIM_Cmd(), TIM_CounterModeConfig(), TIM_SelectOnePulseMode(), TIM_SetClockDivision(), TIM_TimeBaseInit(), TIM_UpdateDisableConfig(), and TIM_UpdateRequestConfig().

__IO uint16_t TIM_TypeDef::CR2

TIM control register 2, Address offset: 0x04

Definition at line 794 of file stm32l1xx.h.

Referenced by TIM_SelectCCDMA(), TIM_SelectHallSensor(), and TIM_SelectOutputTrigger().

__IO uint16_t TIM_TypeDef::DCR

TIM DMA control register, Address offset: 0x48

Definition at line 820 of file stm32l1xx.h.

Referenced by TIM_DMAConfig().

__IO uint16_t TIM_TypeDef::DIER

TIM DMA/interrupt enable register, Address offset: 0x0C

Definition at line 798 of file stm32l1xx.h.

Referenced by TIM_DMACmd(), TIM_GetITStatus(), and TIM_ITConfig().

__IO uint16_t TIM_TypeDef::DMAR

TIM DMA address for full transfer, Address offset: 0x4C

Definition at line 822 of file stm32l1xx.h.

__IO uint16_t TIM_TypeDef::EGR

TIM event generation register, Address offset: 0x14

Definition at line 802 of file stm32l1xx.h.

Referenced by TIM_GenerateEvent(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().

__IO uint16_t TIM_TypeDef::OR

TIM option register, Address offset: 0x50

Definition at line 824 of file stm32l1xx.h.

Referenced by TIM_RemapConfig().

__IO uint16_t TIM_TypeDef::PSC

TIM prescaler, Address offset: 0x28

Definition at line 811 of file stm32l1xx.h.

Referenced by TIM_GetPrescaler(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().

uint16_t TIM_TypeDef::RESERVED0

Reserved, 0x02

Definition at line 793 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED1

Reserved, 0x06

Definition at line 795 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED10

Reserved, 0x2A

Definition at line 812 of file stm32l1xx.h.

uint32_t TIM_TypeDef::RESERVED12

Reserved, 0x30

Definition at line 814 of file stm32l1xx.h.

uint32_t TIM_TypeDef::RESERVED17

Reserved, 0x44

Definition at line 819 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED18

Reserved, 0x4A

Definition at line 821 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED19

Reserved, 0x4E

Definition at line 823 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED2

Reserved, 0x0A

Definition at line 797 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED20

Reserved, 0x52

Definition at line 825 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED3

Reserved, 0x0E

Definition at line 799 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED4

Reserved, 0x12

Definition at line 801 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED5

Reserved, 0x16

Definition at line 803 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED6

Reserved, 0x1A

Definition at line 805 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED7

Reserved, 0x1E

Definition at line 807 of file stm32l1xx.h.

uint16_t TIM_TypeDef::RESERVED8

Reserved, 0x22

Definition at line 809 of file stm32l1xx.h.

__IO uint16_t TIM_TypeDef::SMCR

TIM slave mode control register, Address offset: 0x08

Definition at line 796 of file stm32l1xx.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_InternalClockConfig(), TIM_ITRxExternalClockConfig(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOCREFClear(), TIM_SelectSlaveMode(), and TIM_TIxExternalClockConfig().

__IO uint16_t TIM_TypeDef::SR

TIM status register, Address offset: 0x10

Definition at line 800 of file stm32l1xx.h.

Referenced by TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_GetFlagStatus(), and TIM_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: USART_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_TypeDef Struct Reference
Peripheral_registers_structures

Universal Synchronous Asynchronous Receiver Transmitter. More...

#include <stm32l1xx.h>

Data Fields

__IO uint16_t | BRR
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | CR3
__IO uint16_t | DR
__IO uint16_t | GTPR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
__IO uint16_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter.

Definition at line 832 of file stm32l1xx.h.

Field Documentation

__IO uint16_t USART_TypeDef::BRR

USART Baud rate register, Address offset: 0x08

Definition at line 838 of file stm32l1xx.h.

Referenced by USART_Init().

__IO uint16_t USART_TypeDef::CR1

USART Control register 1, Address offset: 0x0C

Definition at line 840 of file stm32l1xx.h.

Referenced by USART_Cmd(), USART_GetITStatus(), USART_Init(), USART_OverSampling8Cmd(), USART_ReceiverWakeUpCmd(), USART_SendBreak(), and USART_WakeUpConfig().

__IO uint16_t USART_TypeDef::CR2

USART Control register 2, Address offset: 0x10

Definition at line 842 of file stm32l1xx.h.

Referenced by USART_ClockInit(), USART_GetITStatus(), USART_Init(), USART_LINBreakDetectLengthConfig(), USART_LINCmd(), and USART_SetAddress().

__IO uint16_t USART_TypeDef::CR3

USART Control register 3, Address offset: 0x14

Definition at line 844 of file stm32l1xx.h.

Referenced by USART_DMACmd(), USART_GetITStatus(), USART_HalfDuplexCmd(), USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_OneBitMethodCmd(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

__IO uint16_t USART_TypeDef::DR

USART Data register, Address offset: 0x04

Definition at line 836 of file stm32l1xx.h.

Referenced by USART_ReceiveData(), and USART_SendData().

__IO uint16_t USART_TypeDef::GTPR

USART Guard time and prescaler register, Address offset: 0x18

Definition at line 846 of file stm32l1xx.h.

Referenced by USART_SetGuardTime(), and USART_SetPrescaler().

uint16_t USART_TypeDef::RESERVED0

Reserved, 0x02

Definition at line 835 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED1

Reserved, 0x06

Definition at line 837 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED2

Reserved, 0x0A

Definition at line 839 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED3

Reserved, 0x0E

Definition at line 841 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED4

Reserved, 0x12

Definition at line 843 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED5

Reserved, 0x16

Definition at line 845 of file stm32l1xx.h.

uint16_t USART_TypeDef::RESERVED6

Reserved, 0x1A

Definition at line 847 of file stm32l1xx.h.

__IO uint16_t USART_TypeDef::SR

USART Status register, Address offset: 0x00

Definition at line 834 of file stm32l1xx.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_GetFlagStatus(), and USART_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: WWDG_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

WWDG_TypeDef Struct Reference
Peripheral_registers_structures

Window WATCHDOG. More...

#include <stm32l1xx.h>

Data Fields

__IO uint32_t | CFR
__IO uint32_t | CR
__IO uint32_t | SR

Detailed Description

Window WATCHDOG.

Definition at line 854 of file stm32l1xx.h.

Field Documentation

__IO uint32_t WWDG_TypeDef::CFR

WWDG Configuration register, Address offset: 0x04

Definition at line 857 of file stm32l1xx.h.

__IO uint32_t WWDG_TypeDef::CR

WWDG Control register, Address offset: 0x00

Definition at line 856 of file stm32l1xx.h.

__IO uint32_t WWDG_TypeDef::SR

WWDG Status register, Address offset: 0x08

Definition at line 858 of file stm32l1xx.h.

The documentation for this struct was generated from the following file:
  • stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Peripheral_memory_map

Defines

Peripheral_memory_map

Stm32l1xx

Defines

#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define | ADC_BASE (APB2PERIPH_BASE + 0x2700)
#define | AES_BASE ((uint32_t)0x50060000)
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define | APB1PERIPH_BASE PERIPH_BASE
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define | COMP_BASE (APB1PERIPH_BASE + 0x7C00)
#define | CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define | DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define | DBGMCU_BASE ((uint32_t)0xE0042000)
#define | DMA1_BASE (AHBPERIPH_BASE + 0x6000)
#define | DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
#define | DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
#define | DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
#define | DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
#define | DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
#define | DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
#define | DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
#define | DMA2_BASE (AHBPERIPH_BASE + 0x6400)
#define | DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
#define | DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
#define | DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
#define | DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
#define | DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define | FLASH_BASE ((uint32_t)0x08000000)
#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00)
#define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define | FSMC_R_BASE ((uint32_t)0xA0000000)
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
#define | GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
#define | GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define | LCD_BASE (APB1PERIPH_BASE + 0x2400)
#define | OB_BASE ((uint32_t)0x1FF80000)
#define | OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | PERIPH_BB_BASE ((uint32_t)0x42000000)
#define | PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define | RCC_BASE (AHBPERIPH_BASE + 0x3800)
#define | RI_BASE (APB1PERIPH_BASE + 0x7C04)
#define | RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | SRAM_BB_BASE ((uint32_t)0x22000000)
#define | SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
#define | TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
#define | TIM11_BASE (APB2PERIPH_BASE + 0x1000)
#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define | TIM9_BASE (APB2PERIPH_BASE + 0x0800)
#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define | UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define | USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define | USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define | USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00)

Define Documentation

#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)

Definition at line 912 of file stm32l1xx.h.

#define ADC_BASE (APB2PERIPH_BASE + 0x2700)

Definition at line 913 of file stm32l1xx.h.

#define AES_BASE ((uint32_t)0x50060000)

Definition at line 949 of file stm32l1xx.h.

#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)

Definition at line 881 of file stm32l1xx.h.

#define APB1PERIPH_BASE PERIPH_BASE

Definition at line 879 of file stm32l1xx.h.

#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)

Definition at line 880 of file stm32l1xx.h.

#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)

Definition at line 903 of file stm32l1xx.h.

#define CRC_BASE (AHBPERIPH_BASE + 0x3000)

Definition at line 926 of file stm32l1xx.h.

#define DAC_BASE (APB1PERIPH_BASE + 0x7400)

Definition at line 902 of file stm32l1xx.h.

Referenced by DAC_GetDataOutputValue(), DAC_SetChannel1Data(), DAC_SetChannel2Data(), and DAC_SetDualChannelData().

#define DBGMCU_BASE ((uint32_t)0xE0042000)

Debug MCU registers base address

Definition at line 954 of file stm32l1xx.h.

#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)

Definition at line 933 of file stm32l1xx.h.

#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)

Definition at line 934 of file stm32l1xx.h.

#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)

Definition at line 935 of file stm32l1xx.h.

#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)

Definition at line 936 of file stm32l1xx.h.

#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)

Definition at line 937 of file stm32l1xx.h.

#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)

Definition at line 938 of file stm32l1xx.h.

#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)

Definition at line 939 of file stm32l1xx.h.

#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)

Definition at line 940 of file stm32l1xx.h.

#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)

Definition at line 942 of file stm32l1xx.h.

#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)

Definition at line 943 of file stm32l1xx.h.

#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)

Definition at line 944 of file stm32l1xx.h.

#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)

Definition at line 945 of file stm32l1xx.h.

#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)

Definition at line 946 of file stm32l1xx.h.

#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)

Definition at line 947 of file stm32l1xx.h.

#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)

Definition at line 908 of file stm32l1xx.h.

Referenced by EXTI_Init().

#define FLASH_BASE ((uint32_t)0x08000000)

FLASH base address in the alias region

Definition at line 869 of file stm32l1xx.h.

Referenced by SystemInit().

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00)

FLASH registers base address

Definition at line 930 of file stm32l1xx.h.

Referenced by OPAMP_DeInit().

#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)

FSMC Bank1 registers base address

Definition at line 951 of file stm32l1xx.h.

#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)

FSMC Bank1E registers base address

Definition at line 952 of file stm32l1xx.h.

#define FSMC_R_BASE ((uint32_t)0xA0000000)

FSMC registers base address Peripheral memory map

Definition at line 876 of file stm32l1xx.h.

#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)

Definition at line 918 of file stm32l1xx.h.

#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)

Definition at line 919 of file stm32l1xx.h.

#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)

Definition at line 920 of file stm32l1xx.h.

#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)

Definition at line 921 of file stm32l1xx.h.

#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)

Definition at line 922 of file stm32l1xx.h.

#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)

Definition at line 924 of file stm32l1xx.h.

#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)

Definition at line 925 of file stm32l1xx.h.

#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)

Definition at line 923 of file stm32l1xx.h.

#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)

Definition at line 899 of file stm32l1xx.h.

#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)

Definition at line 900 of file stm32l1xx.h.

#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)

Definition at line 892 of file stm32l1xx.h.

#define LCD_BASE (APB1PERIPH_BASE + 0x2400)

Definition at line 889 of file stm32l1xx.h.

#define OB_BASE ((uint32_t)0x1FF80000)

FLASH Option Bytes base address

Definition at line 931 of file stm32l1xx.h.

#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)

Definition at line 905 of file stm32l1xx.h.

#define PERIPH_BASE ((uint32_t)0x40000000)

Peripheral base address in the alias region

Definition at line 871 of file stm32l1xx.h.

#define PERIPH_BB_BASE ((uint32_t)0x42000000)

Peripheral base address in the bit-band region

Definition at line 874 of file stm32l1xx.h.

#define PWR_BASE (APB1PERIPH_BASE + 0x7000)

Definition at line 901 of file stm32l1xx.h.

#define RCC_BASE (AHBPERIPH_BASE + 0x3800)

Definition at line 927 of file stm32l1xx.h.

#define RI_BASE (APB1PERIPH_BASE + 0x7C04)

Definition at line 904 of file stm32l1xx.h.

#define RTC_BASE (APB1PERIPH_BASE + 0x2800)

Definition at line 890 of file stm32l1xx.h.

Referenced by RTC_ReadBackupRegister(), and RTC_WriteBackupRegister().

#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)

Definition at line 914 of file stm32l1xx.h.

#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)

Definition at line 915 of file stm32l1xx.h.

#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)

Definition at line 893 of file stm32l1xx.h.

#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)

Definition at line 894 of file stm32l1xx.h.

#define SRAM_BASE ((uint32_t)0x20000000)

SRAM base address in the alias region

Definition at line 870 of file stm32l1xx.h.

Referenced by SystemInit().

#define SRAM_BB_BASE ((uint32_t)0x22000000)

SRAM base address in the bit-band region

Definition at line 873 of file stm32l1xx.h.

#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)

Definition at line 907 of file stm32l1xx.h.

#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)

Definition at line 910 of file stm32l1xx.h.

#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)

Definition at line 911 of file stm32l1xx.h.

#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)

Definition at line 883 of file stm32l1xx.h.

#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)

Definition at line 884 of file stm32l1xx.h.

#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)

Definition at line 885 of file stm32l1xx.h.

#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)

Definition at line 886 of file stm32l1xx.h.

#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)

Definition at line 887 of file stm32l1xx.h.

#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)

Definition at line 888 of file stm32l1xx.h.

#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)

Definition at line 909 of file stm32l1xx.h.

#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)

Definition at line 897 of file stm32l1xx.h.

#define UART5_BASE (APB1PERIPH_BASE + 0x5000)

Definition at line 898 of file stm32l1xx.h.

#define USART1_BASE (APB2PERIPH_BASE + 0x3800)

Definition at line 916 of file stm32l1xx.h.

#define USART2_BASE (APB1PERIPH_BASE + 0x4400)

Definition at line 895 of file stm32l1xx.h.

#define USART3_BASE (APB1PERIPH_BASE + 0x4800)

Definition at line 896 of file stm32l1xx.h.

#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)

Definition at line 891 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: Peripheral_declaration

Defines

Peripheral_declaration

Stm32l1xx

Defines

#define | ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define | ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define | AES ((AES_TypeDef *) AES_BASE)
#define | COMP ((COMP_TypeDef *) COMP_BASE)
#define | CRC ((CRC_TypeDef *) CRC_BASE)
#define | DAC ((DAC_TypeDef *) DAC_BASE)
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define | GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define | IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | OB ((OB_TypeDef *) OB_BASE)
#define | OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define | PWR ((PWR_TypeDef *) PWR_BASE)
#define | RCC ((RCC_TypeDef *) RCC_BASE)
#define | RI ((RI_TypeDef *) RI_BASE)
#define | RTC ((RTC_TypeDef *) RTC_BASE)
#define | SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define | SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define | TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define | TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define | TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define | UART4 ((USART_TypeDef *) UART4_BASE)
#define | UART5 ((USART_TypeDef *) UART5_BASE)
#define | USART1 ((USART_TypeDef *) USART1_BASE)
#define | USART2 ((USART_TypeDef *) USART2_BASE)
#define | USART3 ((USART_TypeDef *) USART3_BASE)
#define | WWDG ((WWDG_TypeDef *) WWDG_BASE)

Define Documentation

#define ADC ((ADC_Common_TypeDef *) ADC_BASE)

Definition at line 991 of file stm32l1xx.h.

Referenced by ADC_CommonInit(), and ADC_TempSensorVrefintCmd().

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)

Definition at line 990 of file stm32l1xx.h.

Referenced by ADC_DeInit().

#define AES ((AES_TypeDef *) AES_BASE)

Definition at line 1029 of file stm32l1xx.h.

Referenced by AES_ClearFlag(), AES_ClearITPendingBit(), AES_Cmd(), AES_DMAConfig(), AES_GetFlagStatus(), AES_GetITStatus(), AES_Init(), AES_ITConfig(), AES_IVInit(), AES_KeyInit(), AES_ReadIV(), AES_ReadKey(), AES_ReadSubData(), and AES_WriteSubData().

#define COMP ((COMP_TypeDef *) COMP_BASE)

Definition at line 984 of file stm32l1xx.h.

Referenced by COMP_Cmd(), COMP_DeInit(), COMP_GetOutputLevel(), COMP_Init(), COMP_SW1SwitchConfig(), COMP_VrefintOutputCmd(), COMP_WindowCmd(), SYSCFG_RIChannelSpeedConfig(), and SYSCFG_RIResistorConfig().

#define CRC ((CRC_TypeDef *) CRC_BASE)

Definition at line 1015 of file stm32l1xx.h.

Referenced by CRC_CalcBlockCRC(), CRC_CalcCRC(), CRC_GetCRC(), CRC_GetIDRegister(), CRC_ResetDR(), and CRC_SetIDRegister().

#define DAC ((DAC_TypeDef *) DAC_BASE)

Definition at line 983 of file stm32l1xx.h.

Referenced by DAC_ClearFlag(), DAC_ClearITPendingBit(), DAC_Cmd(), DAC_DMACmd(), DAC_DualSoftwareTriggerCmd(), DAC_GetFlagStatus(), DAC_GetITStatus(), DAC_Init(), DAC_ITConfig(), DAC_SoftwareTriggerCmd(), and DAC_WaveGenerationCmd().

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

Definition at line 1034 of file stm32l1xx.h.

Referenced by DBGMCU_APB1PeriphConfig(), DBGMCU_APB2PeriphConfig(), DBGMCU_Config(), DBGMCU_GetDEVID(), and DBGMCU_GetREVID().

#define DMA1 ((DMA_TypeDef *) DMA1_BASE)

Definition at line 998 of file stm32l1xx.h.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_DeInit(), DMA_GetFlagStatus(), and DMA_GetITStatus().

#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

Definition at line 999 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

Definition at line 1000 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

Definition at line 1001 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

Definition at line 1002 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

Definition at line 1003 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

Definition at line 1004 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

Definition at line 1005 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA2 ((DMA_TypeDef *) DMA2_BASE)

Definition at line 1007 of file stm32l1xx.h.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_DeInit(), DMA_GetFlagStatus(), and DMA_GetITStatus().

#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

Definition at line 1008 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

Definition at line 1009 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

Definition at line 1010 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

Definition at line 1011 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

Definition at line 1012 of file stm32l1xx.h.

Referenced by DMA_DeInit().

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

Definition at line 988 of file stm32l1xx.h.

Referenced by EXTI_ClearFlag(), EXTI_ClearITPendingBit(), EXTI_DeInit(), EXTI_GenerateSWInterrupt(), EXTI_GetFlagStatus(), EXTI_GetITStatus(), and EXTI_Init().

#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

Definition at line 1026 of file stm32l1xx.h.

Referenced by DATA_EEPROM_EraseDoubleWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), DATA_EEPROM_FixedTimeProgramCmd(), DATA_EEPROM_Lock(), DATA_EEPROM_ProgramDoubleWord(), DATA_EEPROM_Unlock(), FLASH_ClearFlag(), FLASH_ErasePage(), FLASH_EraseParallelPage(), FLASH_GetFlagStatus(), FLASH_GetStatus(), FLASH_ITConfig(), FLASH_Lock(), FLASH_OB_BootConfig(), FLASH_OB_BORConfig(), FLASH_OB_GetBOR(), FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), FLASH_OB_GetWRP1(), FLASH_OB_GetWRP2(), FLASH_OB_Launch(), FLASH_OB_Lock(), FLASH_OB_Unlock(), FLASH_OB_UserConfig(), FLASH_PrefetchBufferCmd(), FLASH_ProgramHalfPage(), FLASH_ProgramParallelHalfPage(), FLASH_ReadAccess64Cmd(), FLASH_RUNPowerDownCmd(), FLASH_SetLatency(), FLASH_SLEEPPowerDownCmd(), FLASH_Unlock(), GetStatus(), and SetSysClock().

#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)

Definition at line 1031 of file stm32l1xx.h.

Referenced by FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().

#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)

Definition at line 1032 of file stm32l1xx.h.

Referenced by FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

Definition at line 1017 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

Definition at line 1018 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

Definition at line 1019 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

Definition at line 1020 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

Definition at line 1021 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

Definition at line 1023 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

Definition at line 1024 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

Definition at line 1022 of file stm32l1xx.h.

Referenced by GPIO_DeInit().

#define I2C1 ((I2C_TypeDef *) I2C1_BASE)

Definition at line 980 of file stm32l1xx.h.

Referenced by I2C_DeInit().

#define I2C2 ((I2C_TypeDef *) I2C2_BASE)

Definition at line 981 of file stm32l1xx.h.

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

Definition at line 973 of file stm32l1xx.h.

Referenced by IWDG_Enable(), IWDG_GetFlagStatus(), IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), and IWDG_WriteAccessCmd().

#define LCD ((LCD_TypeDef *) LCD_BASE)

Definition at line 970 of file stm32l1xx.h.

Referenced by LCD_BlinkConfig(), LCD_ClearFlag(), LCD_ClearITPendingBit(), LCD_ContrastConfig(), LCD_DeadTimeConfig(), LCD_GetFlagStatus(), LCD_GetITStatus(), LCD_Init(), LCD_ITConfig(), LCD_PulseOnDurationConfig(), LCD_WaitForSynchro(), and LCD_Write().

#define OB ((OB_TypeDef *) OB_BASE)

Definition at line 1027 of file stm32l1xx.h.

Referenced by FLASH_OB_BootConfig(), FLASH_OB_BORConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), and FLASH_OB_WRPConfig().

#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

Definition at line 986 of file stm32l1xx.h.

Referenced by OPAMP_Cmd(), OPAMP_DeInit(), OPAMP_GetFlagStatus(), OPAMP_LowPowerCmd(), OPAMP_OffsetTrimConfig(), OPAMP_OffsetTrimLowPowerConfig(), OPAMP_OffsetTrimmingModeSelect(), OPAMP_PowerRangeSelect(), and OPAMP_SwitchCmd().

#define PWR ((PWR_TypeDef *) PWR_BASE)

Definition at line 982 of file stm32l1xx.h.

Referenced by PWR_ClearFlag(), PWR_EnterLowPowerRunMode(), PWR_EnterSleepMode(), PWR_EnterSTANDBYMode(), PWR_EnterSTOPMode(), PWR_GetFlagStatus(), PWR_PVDLevelConfig(), PWR_VoltageScalingConfig(), and SetSysClock().

#define RCC ((RCC_TypeDef *) RCC_BASE)

Definition at line 1014 of file stm32l1xx.h.

Referenced by RCC_AdjustHSICalibrationValue(), RCC_AHBPeriphClockCmd(), RCC_AHBPeriphClockLPModeCmd(), RCC_AHBPeriphResetCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphClockLPModeCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphClockLPModeCmd(), RCC_APB2PeriphResetCmd(), RCC_ClearFlag(), RCC_DeInit(), RCC_GetClocksFreq(), RCC_GetFlagStatus(), RCC_GetITStatus(), RCC_GetSYSCLKSource(), RCC_HCLKConfig(), RCC_MSIRangeConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_RTCCLKConfig(), RCC_SYSCLKConfig(), SetSysClock(), SystemCoreClockUpdate(), and SystemInit().

#define RI ((RI_TypeDef *) RI_BASE)

Definition at line 985 of file stm32l1xx.h.

Referenced by SYSCFG_RIDeInit(), SYSCFG_RIHysteresisConfig(), SYSCFG_RIIOSwitchConfig(), SYSCFG_RISwitchControlModeCmd(), SYSCFG_RITIMInputCaptureConfig(), and SYSCFG_RITIMSelect().

#define RTC ((RTC_TypeDef *) RTC_BASE)

Definition at line 971 of file stm32l1xx.h.

Referenced by RTC_AlarmCmd(), RTC_AlarmSubSecondConfig(), RTC_BypassShadowCmd(), RTC_CalibOutputCmd(), RTC_CalibOutputConfig(), RTC_ClearFlag(), RTC_ClearITPendingBit(), RTC_CoarseCalibCmd(), RTC_CoarseCalibConfig(), RTC_DayLightSavingConfig(), RTC_DeInit(), RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_GetAlarm(), RTC_GetAlarmSubSecond(), RTC_GetDate(), RTC_GetFlagStatus(), RTC_GetITStatus(), RTC_GetStoreOperation(), RTC_GetSubSecond(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_GetTimeStampSubSecond(), RTC_GetWakeUpCounter(), RTC_Init(), RTC_ITConfig(), RTC_OutputConfig(), RTC_OutputTypeConfig(), RTC_RefClockCmd(), RTC_SetAlarm(), RTC_SetDate(), RTC_SetTime(), RTC_SetWakeUpCounter(), RTC_SmoothCalibConfig(), RTC_SynchroShiftConfig(), RTC_TamperCmd(), RTC_TamperFilterConfig(), RTC_TamperPinsPrechargeDuration(), RTC_TamperPullUpCmd(), RTC_TamperSamplingFreqConfig(), RTC_TamperTriggerConfig(), RTC_TimeStampCmd(), RTC_TimeStampOnTamperDetectionCmd(), RTC_WaitForSynchro(), RTC_WakeUpClockConfig(), RTC_WakeUpCmd(), and RTC_WriteProtectionCmd().

#define SDIO ((SDIO_TypeDef *) SDIO_BASE)

Definition at line 992 of file stm32l1xx.h.

Referenced by SDIO_ClearFlag(), SDIO_ClearITPendingBit(), SDIO_DataConfig(), SDIO_GetCommandResponse(), SDIO_GetDataCounter(), SDIO_GetFIFOCount(), SDIO_GetFlagStatus(), SDIO_GetITStatus(), SDIO_GetPowerState(), SDIO_Init(), SDIO_ITConfig(), SDIO_ReadData(), SDIO_SendCommand(), SDIO_SetPowerState(), and SDIO_WriteData().

#define SPI1 ((SPI_TypeDef *) SPI1_BASE)

Definition at line 996 of file stm32l1xx.h.

Referenced by SPI_I2S_DeInit().

#define SPI2 ((SPI_TypeDef *) SPI2_BASE)

Definition at line 974 of file stm32l1xx.h.

Referenced by SPI_I2S_DeInit().

#define SPI3 ((SPI_TypeDef *) SPI3_BASE)

Definition at line 975 of file stm32l1xx.h.

Referenced by SPI_I2S_DeInit().

#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

Definition at line 987 of file stm32l1xx.h.

Referenced by SYSCFG_EXTILineConfig(), SYSCFG_GetBootMode(), SYSCFG_MemoryRemapConfig(), and SYSCFG_USBPuCmd().

#define TIM10 ((TIM_TypeDef *) TIM10_BASE)

Definition at line 994 of file stm32l1xx.h.

Referenced by TIM_DeInit().

#define TIM11 ((TIM_TypeDef *) TIM11_BASE)

Definition at line 995 of file stm32l1xx.h.

Referenced by TIM_DeInit().

#define TIM2 ((TIM_TypeDef *) TIM2_BASE)

Definition at line 964 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

Definition at line 965 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM4 ((TIM_TypeDef *) TIM4_BASE)

Definition at line 966 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

Definition at line 967 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

Definition at line 968 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM7 ((TIM_TypeDef *) TIM7_BASE)

Definition at line 969 of file stm32l1xx.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

Definition at line 993 of file stm32l1xx.h.

Referenced by TIM_DeInit().

#define UART4 ((USART_TypeDef *) UART4_BASE)

Definition at line 978 of file stm32l1xx.h.

Referenced by USART_DeInit().

#define UART5 ((USART_TypeDef *) UART5_BASE)

Definition at line 979 of file stm32l1xx.h.

Referenced by USART_DeInit().

#define USART1 ((USART_TypeDef *) USART1_BASE)

Definition at line 997 of file stm32l1xx.h.

Referenced by USART_DeInit(), and USART_Init().

#define USART2 ((USART_TypeDef *) USART2_BASE)

Definition at line 976 of file stm32l1xx.h.

Referenced by USART_DeInit().

#define USART3 ((USART_TypeDef *) USART3_BASE)

Definition at line 977 of file stm32l1xx.h.

Referenced by USART_DeInit().

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

Definition at line 972 of file stm32l1xx.h.

Referenced by WWDG_ClearFlag(), WWDG_Enable(), WWDG_GetFlagStatus(), WWDG_SetCounter(), WWDG_SetPrescaler(), and WWDG_SetWindowValue().


STM32L1xx Standard Peripherals Firmware Library: Peripheral_Registers_Bits_Definition

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Defines

Peripheral_Registers_Bits_Definition

Exported_constants

Defines

#define

ADC_CCR_ADCPRE ((uint32_t)0x00030000)

#define

ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)

#define

ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)

#define

ADC_CCR_TSVREFE ((uint32_t)0x00800000)

#define

ADC_CR1_AWDCH ((uint32_t)0x0000001F)

#define

ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)

#define

ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)

#define

ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)

#define

ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)

#define

ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)

#define

ADC_CR1_AWDEN ((uint32_t)0x00800000)

#define

ADC_CR1_AWDIE ((uint32_t)0x00000040)

#define

ADC_CR1_AWDSGL ((uint32_t)0x00000200)

#define

ADC_CR1_DISCEN ((uint32_t)0x00000800)

#define

ADC_CR1_DISCNUM ((uint32_t)0x0000E000)

#define

ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)

#define

ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)

#define

ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)

#define

ADC_CR1_EOCIE ((uint32_t)0x00000020)

#define

ADC_CR1_JAUTO ((uint32_t)0x00000400)

#define

ADC_CR1_JAWDEN ((uint32_t)0x00400000)

#define

ADC_CR1_JDISCEN ((uint32_t)0x00001000)

#define

ADC_CR1_JEOCIE ((uint32_t)0x00000080)

#define

ADC_CR1_OVRIE ((uint32_t)0x04000000)

#define

ADC_CR1_PDD ((uint32_t)0x00010000)

#define

ADC_CR1_PDI ((uint32_t)0x00020000)

#define

ADC_CR1_RES ((uint32_t)0x03000000)

#define

ADC_CR1_RES_0 ((uint32_t)0x01000000)

#define

ADC_CR1_RES_1 ((uint32_t)0x02000000)

#define

ADC_CR1_SCAN ((uint32_t)0x00000100)

#define

ADC_CR2_ADON ((uint32_t)0x00000001)

#define

ADC_CR2_ALIGN ((uint32_t)0x00000800)

#define

ADC_CR2_CFG ((uint32_t)0x00000004)

#define

ADC_CR2_CONT ((uint32_t)0x00000002)

#define

ADC_CR2_DDS ((uint32_t)0x00000200)

#define

ADC_CR2_DELS ((uint32_t)0x00000070)

#define

ADC_CR2_DELS_0 ((uint32_t)0x00000010)

#define

ADC_CR2_DELS_1 ((uint32_t)0x00000020)

#define

ADC_CR2_DELS_2 ((uint32_t)0x00000040)

#define

ADC_CR2_DMA ((uint32_t)0x00000100)

#define

ADC_CR2_EOCS ((uint32_t)0x00000400)

#define

ADC_CR2_EXTEN ((uint32_t)0x30000000)

#define

ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)

#define

ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)

#define

ADC_CR2_EXTSEL ((uint32_t)0x0F000000)

#define

ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)

#define

ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)

#define

ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)

#define

ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)

#define

ADC_CR2_JEXTEN ((uint32_t)0x00300000)

#define

ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)

#define

ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)

#define

ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)

#define

ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)

#define

ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)

#define

ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)

#define

ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)

#define

ADC_CR2_JSWSTART ((uint32_t)0x00400000)

#define

ADC_CR2_SWSTART ((uint32_t)0x40000000)

#define

ADC_CSR_ADONS1 ((uint32_t)0x00000040)

#define

ADC_CSR_AWD1 ((uint32_t)0x00000001)

#define

ADC_CSR_EOC1 ((uint32_t)0x00000002)

#define

ADC_CSR_JEOC1 ((uint32_t)0x00000004)

#define

ADC_CSR_JSTRT1 ((uint32_t)0x00000008)

#define

ADC_CSR_OVR1 ((uint32_t)0x00000020)

#define

ADC_CSR_STRT1 ((uint32_t)0x00000010)

#define

ADC_DR_DATA ((uint32_t)0x0000FFFF)

#define

ADC_HTR_HT ((uint32_t)0x00000FFF)

#define

ADC_JDR1_JDATA ((uint32_t)0x0000FFFF)

#define

ADC_JDR2_JDATA ((uint32_t)0x0000FFFF)

#define

ADC_JDR3_JDATA ((uint32_t)0x0000FFFF)

#define

ADC_JDR4_JDATA ((uint32_t)0x0000FFFF)

#define

ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF)

#define

ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF)

#define

ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF)

#define

ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF)

#define

ADC_JSQR_JL ((uint32_t)0x00300000)

#define

ADC_JSQR_JL_0 ((uint32_t)0x00100000)

#define

ADC_JSQR_JL_1 ((uint32_t)0x00200000)

#define

ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)

#define

ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)

#define

ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)

#define

ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)

#define

ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)

#define

ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)

#define

ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)

#define

ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)

#define

ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)

#define

ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)

#define

ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)

#define

ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)

#define

ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)

#define

ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)

#define

ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)

#define

ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)

#define

ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)

#define

ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)

#define

ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)

#define

ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)

#define

ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)

#define

ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)

#define

ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)

#define

ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)

#define

ADC_LTR_LT ((uint32_t)0x00000FFF)

#define

ADC_SMPR1_SMP20 ((uint32_t)0x00000007)

#define

ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001)

#define

ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002)

#define

ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004)

#define

ADC_SMPR1_SMP21 ((uint32_t)0x00000038)

#define

ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008)

#define

ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010)

#define

ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020)

#define

ADC_SMPR1_SMP22 ((uint32_t)0x000001C0)

#define

ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040)

#define

ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080)

#define

ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100)

#define

ADC_SMPR1_SMP23 ((uint32_t)0x00000E00)

#define

ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200)

#define

ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400)

#define

ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800)

#define

ADC_SMPR1_SMP24 ((uint32_t)0x00007000)

#define

ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000)

#define

ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000)

#define

ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000)

#define

ADC_SMPR1_SMP25 ((uint32_t)0x00038000)

#define

ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000)

#define

ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000)

#define

ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000)

#define

ADC_SMPR1_SMP26 ((uint32_t)0x001C0000)

#define

ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000)

#define

ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000)

#define

ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000)

#define

ADC_SMPR1_SMP27 ((uint32_t)0x00E00000)

#define

ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000)

#define

ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000)

#define

ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000)

#define

ADC_SMPR1_SMP28 ((uint32_t)0x07000000)

#define

ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000)

#define

ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000)

#define

ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000)

#define

ADC_SMPR1_SMP29 ((uint32_t)0x38000000)

#define

ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000)

#define

ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000)

#define

ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000)

#define

ADC_SMPR2_SMP10 ((uint32_t)0x00000007)

#define

ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001)

#define

ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002)

#define

ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004)

#define

ADC_SMPR2_SMP11 ((uint32_t)0x00000038)

#define

ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008)

#define

ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010)

#define

ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020)

#define

ADC_SMPR2_SMP12 ((uint32_t)0x000001C0)

#define

ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040)

#define

ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080)

#define

ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100)

#define

ADC_SMPR2_SMP13 ((uint32_t)0x00000E00)

#define

ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200)

#define

ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400)

#define

ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800)

#define

ADC_SMPR2_SMP14 ((uint32_t)0x00007000)

#define

ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000)

#define

ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000)

#define

ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000)

#define

ADC_SMPR2_SMP15 ((uint32_t)0x00038000)

#define

ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000)

#define

ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000)

#define

ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000)

#define

ADC_SMPR2_SMP16 ((uint32_t)0x001C0000)

#define

ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000)

#define

ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000)

#define

ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000)

#define

ADC_SMPR2_SMP17 ((uint32_t)0x00E00000)

#define

ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000)

#define

ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000)

#define

ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000)

#define

ADC_SMPR2_SMP18 ((uint32_t)0x07000000)

#define

ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000)

#define

ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000)

#define

ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000)

#define

ADC_SMPR2_SMP19 ((uint32_t)0x38000000)

#define

ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000)

#define

ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000)

#define

ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000)

#define

ADC_SMPR3_SMP0 ((uint32_t)0x00000007)

#define

ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001)

#define

ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002)

#define

ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004)

#define

ADC_SMPR3_SMP1 ((uint32_t)0x00000038)

#define

ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008)

#define

ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010)

#define

ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020)

#define

ADC_SMPR3_SMP2 ((uint32_t)0x000001C0)

#define

ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040)

#define

ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080)

#define

ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100)

#define

ADC_SMPR3_SMP3 ((uint32_t)0x00000E00)

#define

ADC_SMPR3_SMP30 ((uint32_t)0x00000007)

#define

ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001)

#define

ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002)

#define

ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004)

#define

ADC_SMPR3_SMP31 ((uint32_t)0x00000038)

#define

ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008)

#define

ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010)

#define

ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020)

#define

ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200)

#define

ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400)

#define

ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800)

#define

ADC_SMPR3_SMP4 ((uint32_t)0x00007000)

#define

ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000)

#define

ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000)

#define

ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000)

#define

ADC_SMPR3_SMP5 ((uint32_t)0x00038000)

#define

ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000)

#define

ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000)

#define

ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000)

#define

ADC_SMPR3_SMP6 ((uint32_t)0x001C0000)

#define

ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000)

#define

ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000)

#define

ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000)

#define

ADC_SMPR3_SMP7 ((uint32_t)0x00E00000)

#define

ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000)

#define

ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000)

#define

ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000)

#define

ADC_SMPR3_SMP8 ((uint32_t)0x07000000)

#define

ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000)

#define

ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000)

#define

ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000)

#define

ADC_SMPR3_SMP9 ((uint32_t)0x38000000)

#define

ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000)

#define

ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000)

#define

ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000)

#define

ADC_SQR1_L ((uint32_t)0x00F00000)

#define

ADC_SQR1_L_0 ((uint32_t)0x00100000)

#define

ADC_SQR1_L_1 ((uint32_t)0x00200000)

#define

ADC_SQR1_L_2 ((uint32_t)0x00400000)

#define

ADC_SQR1_L_3 ((uint32_t)0x00800000)

#define

ADC_SQR1_SQ25 ((uint32_t)0x0000001F)

#define

ADC_SQR1_SQ25_0 ((uint32_t)0x00000001)

#define

ADC_SQR1_SQ25_1 ((uint32_t)0x00000002)

#define

ADC_SQR1_SQ25_2 ((uint32_t)0x00000004)

#define

ADC_SQR1_SQ25_3 ((uint32_t)0x00000008)

#define

ADC_SQR1_SQ25_4 ((uint32_t)0x00000010)

#define

ADC_SQR1_SQ26 ((uint32_t)0x000003E0)

#define

ADC_SQR1_SQ26_0 ((uint32_t)0x00000020)

#define

ADC_SQR1_SQ26_1 ((uint32_t)0x00000040)

#define

ADC_SQR1_SQ26_2 ((uint32_t)0x00000080)

#define

ADC_SQR1_SQ26_3 ((uint32_t)0x00000100)

#define

ADC_SQR1_SQ26_4 ((uint32_t)0x00000200)

#define

ADC_SQR1_SQ27 ((uint32_t)0x00007C00)

#define

ADC_SQR1_SQ27_0 ((uint32_t)0x00000400)

#define

ADC_SQR1_SQ27_1 ((uint32_t)0x00000800)

#define

ADC_SQR1_SQ27_2 ((uint32_t)0x00001000)

#define

ADC_SQR1_SQ27_3 ((uint32_t)0x00002000)

#define

ADC_SQR1_SQ27_4 ((uint32_t)0x00004000)

#define

ADC_SQR1_SQ28 ((uint32_t)0x000F8000)

#define

ADC_SQR1_SQ28_0 ((uint32_t)0x00008000)

#define

ADC_SQR1_SQ28_1 ((uint32_t)0x00010000)

#define

ADC_SQR1_SQ28_2 ((uint32_t)0x00020000)

#define

ADC_SQR1_SQ28_3 ((uint32_t)0x00040000)

#define

ADC_SQR1_SQ28_4 ((uint32_t)0x00080000)

#define

ADC_SQR2_SQ19 ((uint32_t)0x0000001F)

#define

ADC_SQR2_SQ19_0 ((uint32_t)0x00000001)

#define

ADC_SQR2_SQ19_1 ((uint32_t)0x00000002)

#define

ADC_SQR2_SQ19_2 ((uint32_t)0x00000004)

#define

ADC_SQR2_SQ19_3 ((uint32_t)0x00000008)

#define

ADC_SQR2_SQ19_4 ((uint32_t)0x00000010)

#define

ADC_SQR2_SQ20 ((uint32_t)0x000003E0)

#define

ADC_SQR2_SQ20_0 ((uint32_t)0x00000020)

#define

ADC_SQR2_SQ20_1 ((uint32_t)0x00000040)

#define

ADC_SQR2_SQ20_2 ((uint32_t)0x00000080)

#define

ADC_SQR2_SQ20_3 ((uint32_t)0x00000100)

#define

ADC_SQR2_SQ20_4 ((uint32_t)0x00000200)

#define

ADC_SQR2_SQ21 ((uint32_t)0x00007C00)

#define

ADC_SQR2_SQ21_0 ((uint32_t)0x00000400)

#define

ADC_SQR2_SQ21_1 ((uint32_t)0x00000800)

#define

ADC_SQR2_SQ21_2 ((uint32_t)0x00001000)

#define

ADC_SQR2_SQ21_3 ((uint32_t)0x00002000)

#define

ADC_SQR2_SQ21_4 ((uint32_t)0x00004000)

#define

ADC_SQR2_SQ22 ((uint32_t)0x000F8000)

#define

ADC_SQR2_SQ22_0 ((uint32_t)0x00008000)

#define

ADC_SQR2_SQ22_1 ((uint32_t)0x00010000)

#define

ADC_SQR2_SQ22_2 ((uint32_t)0x00020000)

#define

ADC_SQR2_SQ22_3 ((uint32_t)0x00040000)

#define

ADC_SQR2_SQ22_4 ((uint32_t)0x00080000)

#define

ADC_SQR2_SQ23 ((uint32_t)0x01F00000)

#define

ADC_SQR2_SQ23_0 ((uint32_t)0x00100000)

#define

ADC_SQR2_SQ23_1 ((uint32_t)0x00200000)

#define

ADC_SQR2_SQ23_2 ((uint32_t)0x00400000)

#define

ADC_SQR2_SQ23_3 ((uint32_t)0x00800000)

#define

ADC_SQR2_SQ23_4 ((uint32_t)0x01000000)

#define

ADC_SQR2_SQ24 ((uint32_t)0x3E000000)

#define

ADC_SQR2_SQ24_0 ((uint32_t)0x02000000)

#define

ADC_SQR2_SQ24_1 ((uint32_t)0x04000000)

#define

ADC_SQR2_SQ24_2 ((uint32_t)0x08000000)

#define

ADC_SQR2_SQ24_3 ((uint32_t)0x10000000)

#define

ADC_SQR2_SQ24_4 ((uint32_t)0x20000000)

#define

ADC_SQR3_SQ13 ((uint32_t)0x0000001F)

#define

ADC_SQR3_SQ13_0 ((uint32_t)0x00000001)

#define

ADC_SQR3_SQ13_1 ((uint32_t)0x00000002)

#define

ADC_SQR3_SQ13_2 ((uint32_t)0x00000004)

#define

ADC_SQR3_SQ13_3 ((uint32_t)0x00000008)

#define

ADC_SQR3_SQ13_4 ((uint32_t)0x00000010)

#define

ADC_SQR3_SQ14 ((uint32_t)0x000003E0)

#define

ADC_SQR3_SQ14_0 ((uint32_t)0x00000020)

#define

ADC_SQR3_SQ14_1 ((uint32_t)0x00000040)

#define

ADC_SQR3_SQ14_2 ((uint32_t)0x00000080)

#define

ADC_SQR3_SQ14_3 ((uint32_t)0x00000100)

#define

ADC_SQR3_SQ14_4 ((uint32_t)0x00000200)

#define

ADC_SQR3_SQ15 ((uint32_t)0x00007C00)

#define

ADC_SQR3_SQ15_0 ((uint32_t)0x00000400)

#define

ADC_SQR3_SQ15_1 ((uint32_t)0x00000800)

#define

ADC_SQR3_SQ15_2 ((uint32_t)0x00001000)

#define

ADC_SQR3_SQ15_3 ((uint32_t)0x00002000)

#define

ADC_SQR3_SQ15_4 ((uint32_t)0x00004000)

#define

ADC_SQR3_SQ16 ((uint32_t)0x000F8000)

#define

ADC_SQR3_SQ16_0 ((uint32_t)0x00008000)

#define

ADC_SQR3_SQ16_1 ((uint32_t)0x00010000)

#define

ADC_SQR3_SQ16_2 ((uint32_t)0x00020000)

#define

ADC_SQR3_SQ16_3 ((uint32_t)0x00040000)

#define

ADC_SQR3_SQ16_4 ((uint32_t)0x00080000)

#define

ADC_SQR3_SQ17 ((uint32_t)0x01F00000)

#define

ADC_SQR3_SQ17_0 ((uint32_t)0x00100000)

#define

ADC_SQR3_SQ17_1 ((uint32_t)0x00200000)

#define

ADC_SQR3_SQ17_2 ((uint32_t)0x00400000)

#define

ADC_SQR3_SQ17_3 ((uint32_t)0x00800000)

#define

ADC_SQR3_SQ17_4 ((uint32_t)0x01000000)

#define

ADC_SQR3_SQ18 ((uint32_t)0x3E000000)

#define

ADC_SQR3_SQ18_0 ((uint32_t)0x02000000)

#define

ADC_SQR3_SQ18_1 ((uint32_t)0x04000000)

#define

ADC_SQR3_SQ18_2 ((uint32_t)0x08000000)

#define

ADC_SQR3_SQ18_3 ((uint32_t)0x10000000)

#define

ADC_SQR3_SQ18_4 ((uint32_t)0x20000000)

#define

ADC_SQR4_SQ10 ((uint32_t)0x000F8000)

#define

ADC_SQR4_SQ10_0 ((uint32_t)0x00008000)

#define

ADC_SQR4_SQ10_1 ((uint32_t)0x00010000)

#define

ADC_SQR4_SQ10_2 ((uint32_t)0x00020000)

#define

ADC_SQR4_SQ10_3 ((uint32_t)0x00040000)

#define

ADC_SQR4_SQ10_4 ((uint32_t)0x00080000)

#define

ADC_SQR4_SQ11 ((uint32_t)0x01F00000)

#define

ADC_SQR4_SQ11_0 ((uint32_t)0x00100000)

#define

ADC_SQR4_SQ11_1 ((uint32_t)0x00200000)

#define

ADC_SQR4_SQ11_2 ((uint32_t)0x00400000)

#define

ADC_SQR4_SQ11_3 ((uint32_t)0x00800000)

#define

ADC_SQR4_SQ11_4 ((uint32_t)0x01000000)

#define

ADC_SQR4_SQ12 ((uint32_t)0x3E000000)

#define

ADC_SQR4_SQ12_0 ((uint32_t)0x02000000)

#define

ADC_SQR4_SQ12_1 ((uint32_t)0x04000000)

#define

ADC_SQR4_SQ12_2 ((uint32_t)0x08000000)

#define

ADC_SQR4_SQ12_3 ((uint32_t)0x10000000)

#define

ADC_SQR4_SQ12_4 ((uint32_t)0x20000000)

#define

ADC_SQR4_SQ7 ((uint32_t)0x0000001F)

#define

ADC_SQR4_SQ7_0 ((uint32_t)0x00000001)

#define

ADC_SQR4_SQ7_1 ((uint32_t)0x00000002)

#define

ADC_SQR4_SQ7_2 ((uint32_t)0x00000004)

#define

ADC_SQR4_SQ7_3 ((uint32_t)0x00000008)

#define

ADC_SQR4_SQ7_4 ((uint32_t)0x00000010)

#define

ADC_SQR4_SQ8 ((uint32_t)0x000003E0)

#define

ADC_SQR4_SQ8_0 ((uint32_t)0x00000020)

#define

ADC_SQR4_SQ8_1 ((uint32_t)0x00000040)

#define

ADC_SQR4_SQ8_2 ((uint32_t)0x00000080)

#define

ADC_SQR4_SQ8_3 ((uint32_t)0x00000100)

#define

ADC_SQR4_SQ8_4 ((uint32_t)0x00000200)

#define

ADC_SQR4_SQ9 ((uint32_t)0x00007C00)

#define

ADC_SQR4_SQ9_0 ((uint32_t)0x00000400)

#define

ADC_SQR4_SQ9_1 ((uint32_t)0x00000800)

#define

ADC_SQR4_SQ9_2 ((uint32_t)0x00001000)

#define

ADC_SQR4_SQ9_3 ((uint32_t)0x00002000)

#define

ADC_SQR4_SQ9_4 ((uint32_t)0x00004000)

#define

ADC_SQR5_SQ1 ((uint32_t)0x0000001F)

#define

ADC_SQR5_SQ1_0 ((uint32_t)0x00000001)

#define

ADC_SQR5_SQ1_1 ((uint32_t)0x00000002)

#define

ADC_SQR5_SQ1_2 ((uint32_t)0x00000004)

#define

ADC_SQR5_SQ1_3 ((uint32_t)0x00000008)

#define

ADC_SQR5_SQ1_4 ((uint32_t)0x00000010)

#define

ADC_SQR5_SQ2 ((uint32_t)0x000003E0)

#define

ADC_SQR5_SQ2_0 ((uint32_t)0x00000020)

#define

ADC_SQR5_SQ2_1 ((uint32_t)0x00000040)

#define

ADC_SQR5_SQ2_2 ((uint32_t)0x00000080)

#define

ADC_SQR5_SQ2_3 ((uint32_t)0x00000100)

#define

ADC_SQR5_SQ2_4 ((uint32_t)0x00000200)

#define

ADC_SQR5_SQ3 ((uint32_t)0x00007C00)

#define

ADC_SQR5_SQ3_0 ((uint32_t)0x00000400)

#define

ADC_SQR5_SQ3_1 ((uint32_t)0x00000800)

#define

ADC_SQR5_SQ3_2 ((uint32_t)0x00001000)

#define

ADC_SQR5_SQ3_3 ((uint32_t)0x00002000)

#define

ADC_SQR5_SQ3_4 ((uint32_t)0x00004000)

#define

ADC_SQR5_SQ4 ((uint32_t)0x000F8000)

#define

ADC_SQR5_SQ4_0 ((uint32_t)0x00008000)

#define

ADC_SQR5_SQ4_1 ((uint32_t)0x00010000)

#define

ADC_SQR5_SQ4_2 ((uint32_t)0x00020000)

#define

ADC_SQR5_SQ4_3 ((uint32_t)0x00040000)

#define

ADC_SQR5_SQ4_4 ((uint32_t)0x00080000)

#define

ADC_SQR5_SQ5 ((uint32_t)0x01F00000)

#define

ADC_SQR5_SQ5_0 ((uint32_t)0x00100000)

#define

ADC_SQR5_SQ5_1 ((uint32_t)0x00200000)

#define

ADC_SQR5_SQ5_2 ((uint32_t)0x00400000)

#define

ADC_SQR5_SQ5_3 ((uint32_t)0x00800000)

#define

ADC_SQR5_SQ5_4 ((uint32_t)0x01000000)

#define

ADC_SQR5_SQ6 ((uint32_t)0x3E000000)

#define

ADC_SQR5_SQ6_0 ((uint32_t)0x02000000)

#define

ADC_SQR5_SQ6_1 ((uint32_t)0x04000000)

#define

ADC_SQR5_SQ6_2 ((uint32_t)0x08000000)

#define

ADC_SQR5_SQ6_3 ((uint32_t)0x10000000)

#define

ADC_SQR5_SQ6_4 ((uint32_t)0x20000000)

#define

ADC_SR_ADONS ((uint32_t)0x00000040)

#define

ADC_SR_AWD ((uint32_t)0x00000001)

#define

ADC_SR_EOC ((uint32_t)0x00000002)

#define

ADC_SR_JCNR ((uint32_t)0x00000200)

#define

ADC_SR_JEOC ((uint32_t)0x00000004)

#define

ADC_SR_JSTRT ((uint32_t)0x00000008)

#define

ADC_SR_OVR ((uint32_t)0x00000020)

#define

ADC_SR_RCNR ((uint32_t)0x00000100)

#define

ADC_SR_STRT ((uint32_t)0x00000010)

#define

AES_CR_CCFC ((uint32_t)0x00000080)

#define

AES_CR_CCIE ((uint32_t)0x00000200)

#define

AES_CR_CHMOD ((uint32_t)0x00000060)

#define

AES_CR_CHMOD_0 ((uint32_t)0x00000020)

#define

AES_CR_CHMOD_1 ((uint32_t)0x00000040)

#define

AES_CR_DATATYPE ((uint32_t)0x00000006)

#define

AES_CR_DATATYPE_0 ((uint32_t)0x00000002)

#define

AES_CR_DATATYPE_1 ((uint32_t)0x00000004)

#define

AES_CR_DMAINEN ((uint32_t)0x00000800)

#define

AES_CR_DMAOUTEN ((uint32_t)0x00001000)

#define

AES_CR_EN ((uint32_t)0x00000001)

#define

AES_CR_ERRC ((uint32_t)0x00000100)

#define

AES_CR_ERRIE ((uint32_t)0x00000400)

#define

AES_CR_MODE ((uint32_t)0x00000018)

#define

AES_CR_MODE_0 ((uint32_t)0x00000008)

#define

AES_CR_MODE_1 ((uint32_t)0x00000010)

#define

AES_DINR ((uint32_t)0x0000FFFF)

#define

AES_DOUTR ((uint32_t)0x0000FFFF)

#define

AES_IVR0 ((uint32_t)0x0000FFFF)

#define

AES_IVR1 ((uint32_t)0x0000FFFF)

#define

AES_IVR2 ((uint32_t)0x0000FFFF)

#define

AES_IVR3 ((uint32_t)0x0000FFFF)

#define

AES_KEYR0 ((uint32_t)0x0000FFFF)

#define

AES_KEYR1 ((uint32_t)0x0000FFFF)

#define

AES_KEYR2 ((uint32_t)0x0000FFFF)

#define

AES_KEYR3 ((uint32_t)0x0000FFFF)

#define

AES_SR_CCF ((uint32_t)0x00000001)

#define

AES_SR_RDERR ((uint32_t)0x00000002)

#define

AES_SR_WRERR ((uint32_t)0x00000004)

#define

COMP_CSR_10KPD ((uint32_t)0x00000004)

#define

COMP_CSR_10KPU ((uint32_t)0x00000001)

#define

COMP_CSR_400KPD ((uint32_t)0x00000008)

#define

COMP_CSR_400KPU ((uint32_t)0x00000002)

#define

COMP_CSR_CAIE ((uint32_t)0x20000000)

#define

COMP_CSR_CAIF ((uint32_t)0x40000000)

#define

COMP_CSR_CMP1EN ((uint32_t)0x00000010)

#define

COMP_CSR_CMP1OUT ((uint32_t)0x00000080)

#define

COMP_CSR_CMP2OUT ((uint32_t)0x00002000)

#define

COMP_CSR_FCH3 ((uint32_t)0x04000000)

#define

COMP_CSR_FCH8 ((uint32_t)0x08000000)

#define

COMP_CSR_INSEL ((uint32_t)0x001C0000)

#define

COMP_CSR_INSEL_0 ((uint32_t)0x00040000)

#define

COMP_CSR_INSEL_1 ((uint32_t)0x00080000)

#define

COMP_CSR_INSEL_2 ((uint32_t)0x00100000)

#define

COMP_CSR_OUTSEL ((uint32_t)0x00E00000)

#define

COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000)

#define

COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000)

#define

COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000)

#define

COMP_CSR_RCH13 ((uint32_t)0x10000000)

#define

COMP_CSR_SPEED ((uint32_t)0x00001000)

#define

COMP_CSR_SW1 ((uint32_t)0x00000020)

#define

COMP_CSR_TSUSP ((uint32_t)0x80000000)

#define

COMP_CSR_VREFOUTEN ((uint32_t)0x00010000)

#define

COMP_CSR_WNDWE ((uint32_t)0x00020000)

#define

CRC_CR_RESET ((uint32_t)0x00000001)

#define

CRC_DR_DR ((uint32_t)0xFFFFFFFF)

#define

CRC_IDR_IDR ((uint8_t)0xFF)

#define

DAC_CR_BOFF1 ((uint32_t)0x00000002)

#define

DAC_CR_BOFF2 ((uint32_t)0x00020000)

#define

DAC_CR_DMAEN1 ((uint32_t)0x00001000)

#define

DAC_CR_DMAEN2 ((uint32_t)0x10000000)

#define

DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000)

#define

DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000)

#define

DAC_CR_EN1 ((uint32_t)0x00000001)

#define

DAC_CR_EN2 ((uint32_t)0x00010000)

#define

DAC_CR_MAMP1 ((uint32_t)0x00000F00)

#define

DAC_CR_MAMP1_0 ((uint32_t)0x00000100)

#define

DAC_CR_MAMP1_1 ((uint32_t)0x00000200)

#define

DAC_CR_MAMP1_2 ((uint32_t)0x00000400)

#define

DAC_CR_MAMP1_3 ((uint32_t)0x00000800)

#define

DAC_CR_MAMP2 ((uint32_t)0x0F000000)

#define

DAC_CR_MAMP2_0 ((uint32_t)0x01000000)

#define

DAC_CR_MAMP2_1 ((uint32_t)0x02000000)

#define

DAC_CR_MAMP2_2 ((uint32_t)0x04000000)

#define

DAC_CR_MAMP2_3 ((uint32_t)0x08000000)

#define

DAC_CR_TEN1 ((uint32_t)0x00000004)

#define

DAC_CR_TEN2 ((uint32_t)0x00040000)

#define

DAC_CR_TSEL1 ((uint32_t)0x00000038)

#define

DAC_CR_TSEL1_0 ((uint32_t)0x00000008)

#define

DAC_CR_TSEL1_1 ((uint32_t)0x00000010)

#define

DAC_CR_TSEL1_2 ((uint32_t)0x00000020)

#define

DAC_CR_TSEL2 ((uint32_t)0x00380000)

#define

DAC_CR_TSEL2_0 ((uint32_t)0x00080000)

#define

DAC_CR_TSEL2_1 ((uint32_t)0x00100000)

#define

DAC_CR_TSEL2_2 ((uint32_t)0x00200000)

#define

DAC_CR_WAVE1 ((uint32_t)0x000000C0)

#define

DAC_CR_WAVE1_0 ((uint32_t)0x00000040)

#define

DAC_CR_WAVE1_1 ((uint32_t)0x00000080)

#define

DAC_CR_WAVE2 ((uint32_t)0x00C00000)

#define

DAC_CR_WAVE2_0 ((uint32_t)0x00400000)

#define

DAC_CR_WAVE2_1 ((uint32_t)0x00800000)

#define

DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)

#define

DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)

#define

DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)

#define

DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)

#define

DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)

#define

DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)

#define

DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)

#define

DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)

#define

DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)

#define

DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)

#define

DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)

#define

DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)

#define

DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)

#define

DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)

#define

DAC_SR_DMAUDR1 ((uint32_t)0x00002000)

#define

DAC_SR_DMAUDR2 ((uint32_t)0x20000000)

#define

DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)

#define

DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)

#define

DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)

#define

DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)

#define

DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)

#define

DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)

#define

DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)

#define

DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)

#define

DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)

#define

DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)

#define

DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)

#define

DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)

#define

DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)

#define

DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008)

#define

DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010)

#define

DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004)

#define

DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)

#define

DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)

#define

DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)

#define

DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)

#define

DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)

#define

DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)

#define

DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)

#define

DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)

#define

DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)

#define

DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)

#define

DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)

#define

DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)

#define

DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)

#define

DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)

#define

DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)

#define

DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)

#define

DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)

#define

DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)

#define

DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)

#define

DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)

#define

DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)

#define

DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)

#define

DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)

#define

DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)

#define

DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)

#define

DMA_CCR1_CIRC ((uint16_t)0x0020)

#define

DMA_CCR1_DIR ((uint16_t)0x0010)

#define

DMA_CCR1_EN ((uint16_t)0x0001)

#define

DMA_CCR1_HTIE ((uint16_t)0x0004)

#define

DMA_CCR1_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR1_MINC ((uint16_t)0x0080)

#define

DMA_CCR1_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR1_PINC ((uint16_t)0x0040)

#define

DMA_CCR1_PL ((uint16_t)0x3000)

#define

DMA_CCR1_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR1_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR1_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR1_TCIE ((uint16_t)0x0002)

#define

DMA_CCR1_TEIE ((uint16_t)0x0008)

#define

DMA_CCR2_CIRC ((uint16_t)0x0020)

#define

DMA_CCR2_DIR ((uint16_t)0x0010)

#define

DMA_CCR2_EN ((uint16_t)0x0001)

#define

DMA_CCR2_HTIE ((uint16_t)0x0004)

#define

DMA_CCR2_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR2_MINC ((uint16_t)0x0080)

#define

DMA_CCR2_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR2_PINC ((uint16_t)0x0040)

#define

DMA_CCR2_PL ((uint16_t)0x3000)

#define

DMA_CCR2_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR2_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR2_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR2_TCIE ((uint16_t)0x0002)

#define

DMA_CCR2_TEIE ((uint16_t)0x0008)

#define

DMA_CCR3_CIRC ((uint16_t)0x0020)

#define

DMA_CCR3_DIR ((uint16_t)0x0010)

#define

DMA_CCR3_EN ((uint16_t)0x0001)

#define

DMA_CCR3_HTIE ((uint16_t)0x0004)

#define

DMA_CCR3_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR3_MINC ((uint16_t)0x0080)

#define

DMA_CCR3_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR3_PINC ((uint16_t)0x0040)

#define

DMA_CCR3_PL ((uint16_t)0x3000)

#define

DMA_CCR3_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR3_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR3_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR3_TCIE ((uint16_t)0x0002)

#define

DMA_CCR3_TEIE ((uint16_t)0x0008)

#define

DMA_CCR4_CIRC ((uint16_t)0x0020)

#define

DMA_CCR4_DIR ((uint16_t)0x0010)

#define

DMA_CCR4_EN ((uint16_t)0x0001)

#define

DMA_CCR4_HTIE ((uint16_t)0x0004)

#define

DMA_CCR4_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR4_MINC ((uint16_t)0x0080)

#define

DMA_CCR4_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR4_PINC ((uint16_t)0x0040)

#define

DMA_CCR4_PL ((uint16_t)0x3000)

#define

DMA_CCR4_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR4_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR4_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR4_TCIE ((uint16_t)0x0002)

#define

DMA_CCR4_TEIE ((uint16_t)0x0008)

#define

DMA_CCR5_CIRC ((uint16_t)0x0020)

#define

DMA_CCR5_DIR ((uint16_t)0x0010)

#define

DMA_CCR5_EN ((uint16_t)0x0001)

#define

DMA_CCR5_HTIE ((uint16_t)0x0004)

#define

DMA_CCR5_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR5_MINC ((uint16_t)0x0080)

#define

DMA_CCR5_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR5_PINC ((uint16_t)0x0040)

#define

DMA_CCR5_PL ((uint16_t)0x3000)

#define

DMA_CCR5_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR5_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR5_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR5_TCIE ((uint16_t)0x0002)

#define

DMA_CCR5_TEIE ((uint16_t)0x0008)

#define

DMA_CCR6_CIRC ((uint16_t)0x0020)

#define

DMA_CCR6_DIR ((uint16_t)0x0010)

#define

DMA_CCR6_EN ((uint16_t)0x0001)

#define

DMA_CCR6_HTIE ((uint16_t)0x0004)

#define

DMA_CCR6_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR6_MINC ((uint16_t)0x0080)

#define

DMA_CCR6_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR6_PINC ((uint16_t)0x0040)

#define

DMA_CCR6_PL ((uint16_t)0x3000)

#define

DMA_CCR6_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR6_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR6_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR6_TCIE ((uint16_t)0x0002)

#define

DMA_CCR6_TEIE ((uint16_t)0x0008)

#define

DMA_CCR7_CIRC ((uint16_t)0x0020)

#define

DMA_CCR7_DIR ((uint16_t)0x0010)

#define

DMA_CCR7_EN ((uint16_t)0x0001)

#define

DMA_CCR7_HTIE ((uint16_t)0x0004)

#define

DMA_CCR7_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR7_MINC ((uint16_t)0x0080)

#define

DMA_CCR7_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR7_PINC ((uint16_t)0x0040)

#define

DMA_CCR7_PL ((uint16_t)0x3000)

#define

DMA_CCR7_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR7_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR7_PSIZE , ((uint16_t)0x0300)

#define

DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR7_TCIE ((uint16_t)0x0002)

#define

DMA_CCR7_TEIE ((uint16_t)0x0008)

#define

DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CNDTR1_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR2_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR3_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR4_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR5_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR6_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR7_NDT ((uint16_t)0xFFFF)

#define

DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_IFCR_CGIF1 ((uint32_t)0x00000001)

#define

DMA_IFCR_CGIF2 ((uint32_t)0x00000010)

#define

DMA_IFCR_CGIF3 ((uint32_t)0x00000100)

#define

DMA_IFCR_CGIF4 ((uint32_t)0x00001000)

#define

DMA_IFCR_CGIF5 ((uint32_t)0x00010000)

#define

DMA_IFCR_CGIF6 ((uint32_t)0x00100000)

#define

DMA_IFCR_CGIF7 ((uint32_t)0x01000000)

#define

DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)

#define

DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)

#define

DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)

#define

DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)

#define

DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)

#define

DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)

#define

DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)

#define

DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)

#define

DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)

#define

DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)

#define

DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)

#define

DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)

#define

DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)

#define

DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)

#define

DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)

#define

DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)

#define

DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)

#define

DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)

#define

DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)

#define

DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)

#define

DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)

#define

DMA_ISR_GIF1 ((uint32_t)0x00000001)

#define

DMA_ISR_GIF2 ((uint32_t)0x00000010)

#define

DMA_ISR_GIF3 ((uint32_t)0x00000100)

#define

DMA_ISR_GIF4 ((uint32_t)0x00001000)

#define

DMA_ISR_GIF5 ((uint32_t)0x00010000)

#define

DMA_ISR_GIF6 ((uint32_t)0x00100000)

#define

DMA_ISR_GIF7 ((uint32_t)0x01000000)

#define

DMA_ISR_HTIF1 ((uint32_t)0x00000004)

#define

DMA_ISR_HTIF2 ((uint32_t)0x00000040)

#define

DMA_ISR_HTIF3 ((uint32_t)0x00000400)

#define

DMA_ISR_HTIF4 ((uint32_t)0x00004000)

#define

DMA_ISR_HTIF5 ((uint32_t)0x00040000)

#define

DMA_ISR_HTIF6 ((uint32_t)0x00400000)

#define

DMA_ISR_HTIF7 ((uint32_t)0x04000000)

#define

DMA_ISR_TCIF1 ((uint32_t)0x00000002)

#define

DMA_ISR_TCIF2 ((uint32_t)0x00000020)

#define

DMA_ISR_TCIF3 ((uint32_t)0x00000200)

#define

DMA_ISR_TCIF4 ((uint32_t)0x00002000)

#define

DMA_ISR_TCIF5 ((uint32_t)0x00020000)

#define

DMA_ISR_TCIF6 ((uint32_t)0x00200000)

#define

DMA_ISR_TCIF7 ((uint32_t)0x02000000)

#define

DMA_ISR_TEIF1 ((uint32_t)0x00000008)

#define

DMA_ISR_TEIF2 ((uint32_t)0x00000080)

#define

DMA_ISR_TEIF3 ((uint32_t)0x00000800)

#define

DMA_ISR_TEIF4 ((uint32_t)0x00008000)

#define

DMA_ISR_TEIF5 ((uint32_t)0x00080000)

#define

DMA_ISR_TEIF6 ((uint32_t)0x00800000)

#define

DMA_ISR_TEIF7 ((uint32_t)0x08000000)

#define

EXTI_EMR_MR0 ((uint32_t)0x00000001)

#define

EXTI_EMR_MR1 ((uint32_t)0x00000002)

#define

EXTI_EMR_MR10 ((uint32_t)0x00000400)

#define

EXTI_EMR_MR11 ((uint32_t)0x00000800)

#define

EXTI_EMR_MR12 ((uint32_t)0x00001000)

#define

EXTI_EMR_MR13 ((uint32_t)0x00002000)

#define

EXTI_EMR_MR14 ((uint32_t)0x00004000)

#define

EXTI_EMR_MR15 ((uint32_t)0x00008000)

#define

EXTI_EMR_MR16 ((uint32_t)0x00010000)

#define

EXTI_EMR_MR17 ((uint32_t)0x00020000)

#define

EXTI_EMR_MR18 ((uint32_t)0x00040000)

#define

EXTI_EMR_MR19 ((uint32_t)0x00080000)

#define

EXTI_EMR_MR2 ((uint32_t)0x00000004)

#define

EXTI_EMR_MR20 ((uint32_t)0x00100000)

#define

EXTI_EMR_MR21 ((uint32_t)0x00200000)

#define

EXTI_EMR_MR22 ((uint32_t)0x00400000)

#define

EXTI_EMR_MR23 ((uint32_t)0x00800000)

#define

EXTI_EMR_MR3 ((uint32_t)0x00000008)

#define

EXTI_EMR_MR4 ((uint32_t)0x00000010)

#define

EXTI_EMR_MR5 ((uint32_t)0x00000020)

#define

EXTI_EMR_MR6 ((uint32_t)0x00000040)

#define

EXTI_EMR_MR7 ((uint32_t)0x00000080)

#define

EXTI_EMR_MR8 ((uint32_t)0x00000100)

#define

EXTI_EMR_MR9 ((uint32_t)0x00000200)

#define

EXTI_FTSR_TR0 ((uint32_t)0x00000001)

#define

EXTI_FTSR_TR1 ((uint32_t)0x00000002)

#define

EXTI_FTSR_TR10 ((uint32_t)0x00000400)

#define

EXTI_FTSR_TR11 ((uint32_t)0x00000800)

#define

EXTI_FTSR_TR12 ((uint32_t)0x00001000)

#define

EXTI_FTSR_TR13 ((uint32_t)0x00002000)

#define

EXTI_FTSR_TR14 ((uint32_t)0x00004000)

#define

EXTI_FTSR_TR15 ((uint32_t)0x00008000)

#define

EXTI_FTSR_TR16 ((uint32_t)0x00010000)

#define

EXTI_FTSR_TR17 ((uint32_t)0x00020000)

#define

EXTI_FTSR_TR18 ((uint32_t)0x00040000)

#define

EXTI_FTSR_TR19 ((uint32_t)0x00080000)

#define

EXTI_FTSR_TR2 ((uint32_t)0x00000004)

#define

EXTI_FTSR_TR20 ((uint32_t)0x00100000)

#define

EXTI_FTSR_TR21 ((uint32_t)0x00200000)

#define

EXTI_FTSR_TR22 ((uint32_t)0x00400000)

#define

EXTI_FTSR_TR23 ((uint32_t)0x00800000)

#define

EXTI_FTSR_TR3 ((uint32_t)0x00000008)

#define

EXTI_FTSR_TR4 ((uint32_t)0x00000010)

#define

EXTI_FTSR_TR5 ((uint32_t)0x00000020)

#define

EXTI_FTSR_TR6 ((uint32_t)0x00000040)

#define

EXTI_FTSR_TR7 ((uint32_t)0x00000080)

#define

EXTI_FTSR_TR8 ((uint32_t)0x00000100)

#define

EXTI_FTSR_TR9 ((uint32_t)0x00000200)

#define

EXTI_IMR_MR0 ((uint32_t)0x00000001)

#define

EXTI_IMR_MR1 ((uint32_t)0x00000002)

#define

EXTI_IMR_MR10 ((uint32_t)0x00000400)

#define

EXTI_IMR_MR11 ((uint32_t)0x00000800)

#define

EXTI_IMR_MR12 ((uint32_t)0x00001000)

#define

EXTI_IMR_MR13 ((uint32_t)0x00002000)

#define

EXTI_IMR_MR14 ((uint32_t)0x00004000)

#define

EXTI_IMR_MR15 ((uint32_t)0x00008000)

#define

EXTI_IMR_MR16 ((uint32_t)0x00010000)

#define

EXTI_IMR_MR17 ((uint32_t)0x00020000)

#define

EXTI_IMR_MR18 ((uint32_t)0x00040000)

#define

EXTI_IMR_MR19 ((uint32_t)0x00080000)

#define

EXTI_IMR_MR2 ((uint32_t)0x00000004)

#define

EXTI_IMR_MR20 ((uint32_t)0x00100000)

#define

EXTI_IMR_MR21 ((uint32_t)0x00200000)

#define

EXTI_IMR_MR22 ((uint32_t)0x00400000)

#define

EXTI_IMR_MR23 ((uint32_t)0x00800000)

#define

EXTI_IMR_MR3 ((uint32_t)0x00000008)

#define

EXTI_IMR_MR4 ((uint32_t)0x00000010)

#define

EXTI_IMR_MR5 ((uint32_t)0x00000020)

#define

EXTI_IMR_MR6 ((uint32_t)0x00000040)

#define

EXTI_IMR_MR7 ((uint32_t)0x00000080)

#define

EXTI_IMR_MR8 ((uint32_t)0x00000100)

#define

EXTI_IMR_MR9 ((uint32_t)0x00000200)

#define

EXTI_PR_PR0 ((uint32_t)0x00000001)

#define

EXTI_PR_PR1 ((uint32_t)0x00000002)

#define

EXTI_PR_PR10 ((uint32_t)0x00000400)

#define

EXTI_PR_PR11 ((uint32_t)0x00000800)

#define

EXTI_PR_PR12 ((uint32_t)0x00001000)

#define

EXTI_PR_PR13 ((uint32_t)0x00002000)

#define

EXTI_PR_PR14 ((uint32_t)0x00004000)

#define

EXTI_PR_PR15 ((uint32_t)0x00008000)

#define

EXTI_PR_PR16 ((uint32_t)0x00010000)

#define

EXTI_PR_PR17 ((uint32_t)0x00020000)

#define

EXTI_PR_PR18 ((uint32_t)0x00040000)

#define

EXTI_PR_PR19 ((uint32_t)0x00080000)

#define

EXTI_PR_PR2 ((uint32_t)0x00000004)

#define

EXTI_PR_PR20 ((uint32_t)0x00100000)

#define

EXTI_PR_PR21 ((uint32_t)0x00200000)

#define

EXTI_PR_PR22 ((uint32_t)0x00400000)

#define

EXTI_PR_PR23 ((uint32_t)0x00800000)

#define

EXTI_PR_PR3 ((uint32_t)0x00000008)

#define

EXTI_PR_PR4 ((uint32_t)0x00000010)

#define

EXTI_PR_PR5 ((uint32_t)0x00000020)

#define

EXTI_PR_PR6 ((uint32_t)0x00000040)

#define

EXTI_PR_PR7 ((uint32_t)0x00000080)

#define

EXTI_PR_PR8 ((uint32_t)0x00000100)

#define

EXTI_PR_PR9 ((uint32_t)0x00000200)

#define

EXTI_RTSR_TR0 ((uint32_t)0x00000001)

#define

EXTI_RTSR_TR1 ((uint32_t)0x00000002)

#define

EXTI_RTSR_TR10 ((uint32_t)0x00000400)

#define

EXTI_RTSR_TR11 ((uint32_t)0x00000800)

#define

EXTI_RTSR_TR12 ((uint32_t)0x00001000)

#define

EXTI_RTSR_TR13 ((uint32_t)0x00002000)

#define

EXTI_RTSR_TR14 ((uint32_t)0x00004000)

#define

EXTI_RTSR_TR15 ((uint32_t)0x00008000)

#define

EXTI_RTSR_TR16 ((uint32_t)0x00010000)

#define

EXTI_RTSR_TR17 ((uint32_t)0x00020000)

#define

EXTI_RTSR_TR18 ((uint32_t)0x00040000)

#define

EXTI_RTSR_TR19 ((uint32_t)0x00080000)

#define

EXTI_RTSR_TR2 ((uint32_t)0x00000004)

#define

EXTI_RTSR_TR20 ((uint32_t)0x00100000)

#define

EXTI_RTSR_TR21 ((uint32_t)0x00200000)

#define

EXTI_RTSR_TR22 ((uint32_t)0x00400000)

#define

EXTI_RTSR_TR23 ((uint32_t)0x00800000)

#define

EXTI_RTSR_TR3 ((uint32_t)0x00000008)

#define

EXTI_RTSR_TR4 ((uint32_t)0x00000010)

#define

EXTI_RTSR_TR5 ((uint32_t)0x00000020)

#define

EXTI_RTSR_TR6 ((uint32_t)0x00000040)

#define

EXTI_RTSR_TR7 ((uint32_t)0x00000080)

#define

EXTI_RTSR_TR8 ((uint32_t)0x00000100)

#define

EXTI_RTSR_TR9 ((uint32_t)0x00000200)

#define

EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)

#define

EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)

#define

EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)

#define

EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)

#define

EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)

#define

EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)

#define

EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)

#define

EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)

#define

EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)

#define

EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)

#define

EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)

#define

EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)

#define

EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)

#define

EXTI_SWIER_SWIER20 ((uint32_t)0x00100000)

#define

EXTI_SWIER_SWIER21 ((uint32_t)0x00200000)

#define

EXTI_SWIER_SWIER22 ((uint32_t)0x00400000)

#define

EXTI_SWIER_SWIER23 ((uint32_t)0x00800000)

#define

EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)

#define

EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)

#define

EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)

#define

EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)

#define

EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)

#define

EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)

#define

EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)

#define

FLASH_ACR_ACC64 ((uint32_t)0x00000004)

#define

FLASH_ACR_LATENCY ((uint32_t)0x00000001)

#define

FLASH_ACR_PRFTEN ((uint32_t)0x00000002)

#define

FLASH_ACR_RUN_PD ((uint32_t)0x00000010)

#define

FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008)

#define

FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000)

#define

FLASH_OBR_IWDG_SW ((uint32_t)0x00100000)

#define

FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000)

#define

FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000)

#define

FLASH_OBR_nRST_STOP ((uint32_t)0x00200000)

#define

FLASH_OBR_RDPRT ((uint16_t)0x000000AA)

#define

FLASH_OBR_USER ((uint32_t)0x00700000)

#define

FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_PECR_DATA ((uint32_t)0x00000010)

#define

FLASH_PECR_EOPIE ((uint32_t)0x00010000)

#define

FLASH_PECR_ERASE ((uint32_t)0x00000200)

#define

FLASH_PECR_ERRIE ((uint32_t)0x00020000)

#define

FLASH_PECR_FPRG ((uint32_t)0x00000400)

#define

FLASH_PECR_FTDW ((uint32_t)0x00000100)

#define

FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000)

#define

FLASH_PECR_OPTLOCK ((uint32_t)0x00000004)

#define

FLASH_PECR_PARALLBANK ((uint32_t)0x00008000)

#define

FLASH_PECR_PELOCK ((uint32_t)0x00000001)

#define

FLASH_PECR_PRGLOCK ((uint32_t)0x00000002)

#define

FLASH_PECR_PROG ((uint32_t)0x00000008)

#define

FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_SR_BSY ((uint32_t)0x00000001)

#define

FLASH_SR_ENHV ((uint32_t)0x00000004)

#define

FLASH_SR_EOP ((uint32_t)0x00000002)

#define

FLASH_SR_OPTVERR ((uint32_t)0x00000800)

#define

FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000)

#define

FLASH_SR_PGAERR ((uint32_t)0x00000200)

#define

FLASH_SR_READY ((uint32_t)0x00000008)

#define

FLASH_SR_SIZERR ((uint32_t)0x00000400)

#define

FLASH_SR_WRPERR ((uint32_t)0x00000100)

#define

FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF)

#define

FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF)

#define

FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)

#define

FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR1_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR1_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR1_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR1_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR1_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR1_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR1_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR2_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR2_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR2_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR2_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR2_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR2_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR2_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR3_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR3_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR3_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR3_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR3_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR3_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR3_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR4_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR4_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR4_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR4_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR4_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR4_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR4_WREN ((uint32_t)0x00001000)

#define

FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)

#define

GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)

#define

GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)

#define

GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)

#define

GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)

#define

GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)

#define

GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)

#define

GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)

#define

GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)

#define

GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)

#define

GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)

#define

GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)

#define

GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)

#define

GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)

#define

GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)

#define

GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)

#define

GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)

#define

GPIO_BSRR_BR_0 ((uint32_t)0x00010000)

#define

GPIO_BSRR_BR_1 ((uint32_t)0x00020000)

#define

GPIO_BSRR_BR_10 ((uint32_t)0x04000000)

#define

GPIO_BSRR_BR_11 ((uint32_t)0x08000000)

#define

GPIO_BSRR_BR_12 ((uint32_t)0x10000000)

#define

GPIO_BSRR_BR_13 ((uint32_t)0x20000000)

#define

GPIO_BSRR_BR_14 ((uint32_t)0x40000000)

#define

GPIO_BSRR_BR_15 ((uint32_t)0x80000000)

#define

GPIO_BSRR_BR_2 ((uint32_t)0x00040000)

#define

GPIO_BSRR_BR_3 ((uint32_t)0x00080000)

#define

GPIO_BSRR_BR_4 ((uint32_t)0x00100000)

#define

GPIO_BSRR_BR_5 ((uint32_t)0x00200000)

#define

GPIO_BSRR_BR_6 ((uint32_t)0x00400000)

#define

GPIO_BSRR_BR_7 ((uint32_t)0x00800000)

#define

GPIO_BSRR_BR_8 ((uint32_t)0x01000000)

#define

GPIO_BSRR_BR_9 ((uint32_t)0x02000000)

#define

GPIO_BSRR_BS_0 ((uint32_t)0x00000001)

#define

GPIO_BSRR_BS_1 ((uint32_t)0x00000002)

#define

GPIO_BSRR_BS_10 ((uint32_t)0x00000400)

#define

GPIO_BSRR_BS_11 ((uint32_t)0x00000800)

#define

GPIO_BSRR_BS_12 ((uint32_t)0x00001000)

#define

GPIO_BSRR_BS_13 ((uint32_t)0x00002000)

#define

GPIO_BSRR_BS_14 ((uint32_t)0x00004000)

#define

GPIO_BSRR_BS_15 ((uint32_t)0x00008000)

#define

GPIO_BSRR_BS_2 ((uint32_t)0x00000004)

#define

GPIO_BSRR_BS_3 ((uint32_t)0x00000008)

#define

GPIO_BSRR_BS_4 ((uint32_t)0x00000010)

#define

GPIO_BSRR_BS_5 ((uint32_t)0x00000020)

#define

GPIO_BSRR_BS_6 ((uint32_t)0x00000040)

#define

GPIO_BSRR_BS_7 ((uint32_t)0x00000080)

#define

GPIO_BSRR_BS_8 ((uint32_t)0x00000100)

#define

GPIO_BSRR_BS_9 ((uint32_t)0x00000200)

#define

GPIO_IDR_IDR_0 ((uint32_t)0x00000001)

#define

GPIO_IDR_IDR_1 ((uint32_t)0x00000002)

#define

GPIO_IDR_IDR_10 ((uint32_t)0x00000400)

#define

GPIO_IDR_IDR_11 ((uint32_t)0x00000800)

#define

GPIO_IDR_IDR_12 ((uint32_t)0x00001000)

#define

GPIO_IDR_IDR_13 ((uint32_t)0x00002000)

#define

GPIO_IDR_IDR_14 ((uint32_t)0x00004000)

#define

GPIO_IDR_IDR_15 ((uint32_t)0x00008000)

#define

GPIO_IDR_IDR_2 ((uint32_t)0x00000004)

#define

GPIO_IDR_IDR_3 ((uint32_t)0x00000008)

#define

GPIO_IDR_IDR_4 ((uint32_t)0x00000010)

#define

GPIO_IDR_IDR_5 ((uint32_t)0x00000020)

#define

GPIO_IDR_IDR_6 ((uint32_t)0x00000040)

#define

GPIO_IDR_IDR_7 ((uint32_t)0x00000080)

#define

GPIO_IDR_IDR_8 ((uint32_t)0x00000100)

#define

GPIO_IDR_IDR_9 ((uint32_t)0x00000200)

#define

GPIO_LCKR_LCK0 ((uint32_t)0x00000001)

#define

GPIO_LCKR_LCK1 ((uint32_t)0x00000002)

#define

GPIO_LCKR_LCK10 ((uint32_t)0x00000400)

#define

GPIO_LCKR_LCK11 ((uint32_t)0x00000800)

#define

GPIO_LCKR_LCK12 ((uint32_t)0x00001000)

#define

GPIO_LCKR_LCK13 ((uint32_t)0x00002000)

#define

GPIO_LCKR_LCK14 ((uint32_t)0x00004000)

#define

GPIO_LCKR_LCK15 ((uint32_t)0x00008000)

#define

GPIO_LCKR_LCK2 ((uint32_t)0x00000004)

#define

GPIO_LCKR_LCK3 ((uint32_t)0x00000008)

#define

GPIO_LCKR_LCK4 ((uint32_t)0x00000010)

#define

GPIO_LCKR_LCK5 ((uint32_t)0x00000020)

#define

GPIO_LCKR_LCK6 ((uint32_t)0x00000040)

#define

GPIO_LCKR_LCK7 ((uint32_t)0x00000080)

#define

GPIO_LCKR_LCK8 ((uint32_t)0x00000100)

#define

GPIO_LCKR_LCK9 ((uint32_t)0x00000200)

#define

GPIO_LCKR_LCKK ((uint32_t)0x00010000)

#define

GPIO_MODER_MODER0 ((uint32_t)0x00000003)

#define

GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)

#define

GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)

#define

GPIO_MODER_MODER1 ((uint32_t)0x0000000C)

#define

GPIO_MODER_MODER10 ((uint32_t)0x00300000)

#define

GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)

#define

GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)

#define

GPIO_MODER_MODER11 ((uint32_t)0x00C00000)

#define

GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)

#define

GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)

#define

GPIO_MODER_MODER12 ((uint32_t)0x03000000)

#define

GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)

#define

GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)

#define

GPIO_MODER_MODER13 ((uint32_t)0x0C000000)

#define

GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)

#define

GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)

#define

GPIO_MODER_MODER14 ((uint32_t)0x30000000)

#define

GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)

#define

GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)

#define

GPIO_MODER_MODER15 ((uint32_t)0xC0000000)

#define

GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)

#define

GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)

#define

GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)

#define

GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)

#define

GPIO_MODER_MODER2 ((uint32_t)0x00000030)

#define

GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)

#define

GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)

#define

GPIO_MODER_MODER3 ((uint32_t)0x000000C0)

#define

GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)

#define

GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)

#define

GPIO_MODER_MODER4 ((uint32_t)0x00000300)

#define

GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)

#define

GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)

#define

GPIO_MODER_MODER5 ((uint32_t)0x00000C00)

#define

GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)

#define

GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)

#define

GPIO_MODER_MODER6 ((uint32_t)0x00003000)

#define

GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)

#define

GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)

#define

GPIO_MODER_MODER7 ((uint32_t)0x0000C000)

#define

GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)

#define

GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)

#define

GPIO_MODER_MODER8 ((uint32_t)0x00030000)

#define

GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)

#define

GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)

#define

GPIO_MODER_MODER9 ((uint32_t)0x000C0000)

#define

GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)

#define

GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)

#define

GPIO_ODR_ODR_0 ((uint32_t)0x00000001)

#define

GPIO_ODR_ODR_1 ((uint32_t)0x00000002)

#define

GPIO_ODR_ODR_10 ((uint32_t)0x00000400)

#define

GPIO_ODR_ODR_11 ((uint32_t)0x00000800)

#define

GPIO_ODR_ODR_12 ((uint32_t)0x00001000)

#define

GPIO_ODR_ODR_13 ((uint32_t)0x00002000)

#define

GPIO_ODR_ODR_14 ((uint32_t)0x00004000)

#define

GPIO_ODR_ODR_15 ((uint32_t)0x00008000)

#define

GPIO_ODR_ODR_2 ((uint32_t)0x00000004)

#define

GPIO_ODR_ODR_3 ((uint32_t)0x00000008)

#define

GPIO_ODR_ODR_4 ((uint32_t)0x00000010)

#define

GPIO_ODR_ODR_5 ((uint32_t)0x00000020)

#define

GPIO_ODR_ODR_6 ((uint32_t)0x00000040)

#define

GPIO_ODR_ODR_7 ((uint32_t)0x00000080)

#define

GPIO_ODR_ODR_8 ((uint32_t)0x00000100)

#define

GPIO_ODR_ODR_9 ((uint32_t)0x00000200)

#define

GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)

#define

GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)

#define

GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)

#define

GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)

#define

GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)

#define

GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)

#define

GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)

#define

GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)

#define

GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)

#define

GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)

#define

GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)

#define

GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)

#define

GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)

#define

GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)

#define

GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)

#define

GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)

#define

GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)

#define

GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)

#define

GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)

#define

GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)

#define

GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)

#define

GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)

#define

GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)

#define

GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)

#define

GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)

#define

GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)

#define

GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)

#define

GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)

#define

GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)

#define

GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)

#define

GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)

#define

GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)

#define

GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)

#define

GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)

#define

GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)

#define

GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)

#define

GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)

#define

GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)

#define

GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)

#define

GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)

#define

GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)

#define

GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)

#define

GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)

#define

GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)

#define

GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)

#define

GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)

#define

GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)

#define

GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)

#define

GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0

#define

GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1

#define

GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10

#define

GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11

#define

GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12

#define

GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13

#define

GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14

#define

GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15

#define

GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2

#define

GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3

#define

GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4

#define

GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5

#define

GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6

#define

GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7

#define

GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8

#define

GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9

#define

GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0

#define

GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1

#define

GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10

#define

GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11

#define

GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12

#define

GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13

#define

GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14

#define

GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15

#define

GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2

#define

GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3

#define

GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4

#define

GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5

#define

GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6

#define

GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7

#define

GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8

#define

GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9

#define

GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)

#define

GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)

#define

GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)

#define

GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)

#define

GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)

#define

GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)

#define

GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)

#define

GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)

#define

GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)

#define

GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)

#define

GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)

#define

GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)

#define

GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)

#define

GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)

#define

GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)

#define

GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)

#define

GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)

#define

GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)

#define

GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)

#define

GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)

#define

GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)

#define

GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)

#define

GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)

#define

GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)

#define

GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)

#define

GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)

#define

GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)

#define

GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)

#define

GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)

#define

GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)

#define

GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)

#define

GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)

#define

GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)

#define

GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)

#define

GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)

#define

GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)

#define

GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)

#define

GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)

#define

GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)

#define

GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)

#define

GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)

#define

GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)

#define

GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)

#define

GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)

#define

GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)

#define

GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)

#define

GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)

#define

GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)

#define

GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)

#define

GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)

#define

GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)

#define

GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)

#define

GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)

#define

GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)

#define

GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)

#define

GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)

#define

GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)

#define

GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)

#define

GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)

#define

GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)

#define

GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)

#define

GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)

#define

GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)

#define

GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)

#define

I2C_CCR_CCR ((uint16_t)0x0FFF)

#define

I2C_CCR_DUTY ((uint16_t)0x4000)

#define

I2C_CCR_FS ((uint16_t)0x8000)

#define

I2C_CR1_ACK ((uint16_t)0x0400)

#define

I2C_CR1_ALERT ((uint16_t)0x2000)

#define

I2C_CR1_ENARP ((uint16_t)0x0010)

#define

I2C_CR1_ENGC ((uint16_t)0x0040)

#define

I2C_CR1_ENPEC ((uint16_t)0x0020)

#define

I2C_CR1_NOSTRETCH ((uint16_t)0x0080)

#define

I2C_CR1_PE ((uint16_t)0x0001)

#define

I2C_CR1_PEC ((uint16_t)0x1000)

#define

I2C_CR1_POS ((uint16_t)0x0800)

#define

I2C_CR1_SMBTYPE ((uint16_t)0x0008)

#define

I2C_CR1_SMBUS ((uint16_t)0x0002)

#define

I2C_CR1_START ((uint16_t)0x0100)

#define

I2C_CR1_STOP ((uint16_t)0x0200)

#define

I2C_CR1_SWRST ((uint16_t)0x8000)

#define

I2C_CR2_DMAEN ((uint16_t)0x0800)

#define

I2C_CR2_FREQ ((uint16_t)0x003F)

#define

I2C_CR2_FREQ_0 ((uint16_t)0x0001)

#define

I2C_CR2_FREQ_1 ((uint16_t)0x0002)

#define

I2C_CR2_FREQ_2 ((uint16_t)0x0004)

#define

I2C_CR2_FREQ_3 ((uint16_t)0x0008)

#define

I2C_CR2_FREQ_4 ((uint16_t)0x0010)

#define

I2C_CR2_FREQ_5 ((uint16_t)0x0020)

#define

I2C_CR2_ITBUFEN ((uint16_t)0x0400)

#define

I2C_CR2_ITERREN ((uint16_t)0x0100)

#define

I2C_CR2_ITEVTEN ((uint16_t)0x0200)

#define

I2C_CR2_LAST ((uint16_t)0x1000)

#define

I2C_DR_DR ((uint8_t)0xFF)

#define

I2C_OAR1_ADD0 ((uint16_t)0x0001)

#define

I2C_OAR1_ADD1 ((uint16_t)0x0002)

#define

I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)

#define

I2C_OAR1_ADD2 ((uint16_t)0x0004)

#define

I2C_OAR1_ADD3 ((uint16_t)0x0008)

#define

I2C_OAR1_ADD4 ((uint16_t)0x0010)

#define

I2C_OAR1_ADD5 ((uint16_t)0x0020)

#define

I2C_OAR1_ADD6 ((uint16_t)0x0040)

#define

I2C_OAR1_ADD7 ((uint16_t)0x0080)

#define

I2C_OAR1_ADD8 ((uint16_t)0x0100)

#define

I2C_OAR1_ADD8_9 ((uint16_t)0x0300)

#define

I2C_OAR1_ADD9 ((uint16_t)0x0200)

#define

I2C_OAR1_ADDMODE ((uint16_t)0x8000)

#define

I2C_OAR2_ADD2 ((uint8_t)0xFE)

#define

I2C_OAR2_ENDUAL ((uint8_t)0x01)

#define

I2C_SR1_ADD10 ((uint16_t)0x0008)

#define

I2C_SR1_ADDR ((uint16_t)0x0002)

#define

I2C_SR1_AF ((uint16_t)0x0400)

#define

I2C_SR1_ARLO ((uint16_t)0x0200)

#define

I2C_SR1_BERR ((uint16_t)0x0100)

#define

I2C_SR1_BTF ((uint16_t)0x0004)

#define

I2C_SR1_OVR ((uint16_t)0x0800)

#define

I2C_SR1_PECERR ((uint16_t)0x1000)

#define

I2C_SR1_RXNE ((uint16_t)0x0040)

#define

I2C_SR1_SB ((uint16_t)0x0001)

#define

I2C_SR1_SMBALERT ((uint16_t)0x8000)

#define

I2C_SR1_STOPF ((uint16_t)0x0010)

#define

I2C_SR1_TIMEOUT ((uint16_t)0x4000)

#define

I2C_SR1_TXE ((uint16_t)0x0080)

#define

I2C_SR2_BUSY ((uint16_t)0x0002)

#define

I2C_SR2_DUALF ((uint16_t)0x0080)

#define

I2C_SR2_GENCALL ((uint16_t)0x0010)

#define

I2C_SR2_MSL ((uint16_t)0x0001)

#define

I2C_SR2_PEC ((uint16_t)0xFF00)

#define

I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)

#define

I2C_SR2_SMBHOST ((uint16_t)0x0040)

#define

I2C_SR2_TRA ((uint16_t)0x0004)

#define

I2C_TRISE_TRISE ((uint8_t)0x3F)

#define

IWDG_KR_KEY ((uint16_t)0xFFFF)

#define

IWDG_PR_PR ((uint8_t)0x07)

#define

IWDG_PR_PR_0 ((uint8_t)0x01)

#define

IWDG_PR_PR_1 ((uint8_t)0x02)

#define

IWDG_PR_PR_2 ((uint8_t)0x04)

#define

IWDG_RLR_RL ((uint16_t)0x0FFF)

#define

IWDG_SR_PVU ((uint8_t)0x01)

#define

IWDG_SR_RVU ((uint8_t)0x02)

#define

LCD_CLR_SOFC ((uint32_t)0x00000002)

#define

LCD_CLR_UDDC ((uint32_t)0x00000008)

#define

LCD_CR_BIAS ((uint32_t)0x00000060)

#define

LCD_CR_BIAS_0 ((uint32_t)0x00000020)

#define

LCD_CR_BIAS_1 ((uint32_t)0x00000040)

#define

LCD_CR_DUTY ((uint32_t)0x0000001C)

#define

LCD_CR_DUTY_0 ((uint32_t)0x00000004)

#define

LCD_CR_DUTY_1 ((uint32_t)0x00000008)

#define

LCD_CR_DUTY_2 ((uint32_t)0x00000010)

#define

LCD_CR_LCDEN ((uint32_t)0x00000001)

#define

LCD_CR_MUX_SEG ((uint32_t)0x00000080)

#define

LCD_CR_VSEL ((uint32_t)0x00000002)

#define

LCD_FCR_BLINK ((uint32_t)0x00030000)

#define

LCD_FCR_BLINK_0 ((uint32_t)0x00010000)

#define

LCD_FCR_BLINK_1 ((uint32_t)0x00020000)

#define

LCD_FCR_BLINKF ((uint32_t)0x0000E000)

#define

LCD_FCR_BLINKF_0 ((uint32_t)0x00002000)

#define

LCD_FCR_BLINKF_1 ((uint32_t)0x00004000)

#define

LCD_FCR_BLINKF_2 ((uint32_t)0x00008000)

#define

LCD_FCR_CC ((uint32_t)0x00001C00)

#define

LCD_FCR_CC_0 ((uint32_t)0x00000400)

#define

LCD_FCR_CC_1 ((uint32_t)0x00000800)

#define

LCD_FCR_CC_2 ((uint32_t)0x00001000)

#define

LCD_FCR_DEAD ((uint32_t)0x00000380)

#define

LCD_FCR_DEAD_0 ((uint32_t)0x00000080)

#define

LCD_FCR_DEAD_1 ((uint32_t)0x00000100)

#define

LCD_FCR_DEAD_2 ((uint32_t)0x00000200)

#define

LCD_FCR_DIV ((uint32_t)0x003C0000)

#define

LCD_FCR_HD ((uint32_t)0x00000001)

#define

LCD_FCR_PON ((uint32_t)0x00000070)

#define

LCD_FCR_PON_0 ((uint32_t)0x00000010)

#define

LCD_FCR_PON_1 ((uint32_t)0x00000020)

#define

LCD_FCR_PON_2 ((uint32_t)0x00000040)

#define

LCD_FCR_PS ((uint32_t)0x03C00000)

#define

LCD_FCR_SOFIE ((uint32_t)0x00000002)

#define

LCD_FCR_UDDIE ((uint32_t)0x00000008)

#define

LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF)

#define

LCD_SR_ENS ((uint32_t)0x00000001)

#define

LCD_SR_FCRSR ((uint32_t)0x00000020)

#define

LCD_SR_RDY ((uint32_t)0x00000010)

#define

LCD_SR_SOF ((uint32_t)0x00000002)

#define

LCD_SR_UDD ((uint32_t)0x00000008)

#define

LCD_SR_UDR ((uint32_t)0x00000004)

#define

NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)

#define

NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)

#define

NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)

#define

NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)

#define

NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)

#define

NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)

#define

NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)

#define

NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)

#define

NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)

#define

NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)

#define

NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)

#define

NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)

#define

NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)

#define

NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)

#define

NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)

#define

NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)

#define

NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)

#define

NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)

#define

NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)

#define

NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)

#define

NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)

#define

NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)

#define

NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)

#define

NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)

#define

NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)

#define

NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)

#define

NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)

#define

NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)

#define

NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)

#define

NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)

#define

NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)

#define

NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)

#define

NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)

#define

NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)

#define

NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)

#define

NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)

#define

NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)

#define

NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)

#define

NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)

#define

NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)

#define

NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)

#define

NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)

#define

NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)

#define

NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)

#define

NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)

#define

NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)

#define

NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)

#define

NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)

#define

NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)

#define

NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)

#define

NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)

#define

NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)

#define

NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)

#define

NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)

#define

NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)

#define

NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)

#define

NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)

#define

NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)

#define

NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)

#define

NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)

#define

NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)

#define

NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)

#define

NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)

#define

NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)

#define

NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)

#define

NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)

#define

NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)

#define

NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)

#define

NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)

#define

NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)

#define

NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)

#define

NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)

#define

NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)

#define

NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)

#define

NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)

#define

NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)

#define

NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)

#define

NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)

#define

NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)

#define

NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)

#define

NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)

#define

NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)

#define

NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)

#define

NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)

#define

NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)

#define

NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)

#define

NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)

#define

NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)

#define

NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)

#define

NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)

#define

NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)

#define

NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)

#define

NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)

#define

NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)

#define

NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)

#define

NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)

#define

NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)

#define

NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)

#define

NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)

#define

NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)

#define

NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)

#define

NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)

#define

NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)

#define

NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)

#define

NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)

#define

NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)

#define

NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)

#define

NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)

#define

NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)

#define

NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)

#define

NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)

#define

NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)

#define

NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)

#define

NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)

#define

NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)

#define

NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)

#define

NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)

#define

NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)

#define

NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)

#define

NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)

#define

NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)

#define

NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)

#define

NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)

#define

NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)

#define

NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)

#define

NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)

#define

NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)

#define

NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)

#define

NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)

#define

NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)

#define

NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)

#define

NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)

#define

NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)

#define

NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)

#define

NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)

#define

NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)

#define

NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)

#define

NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)

#define

NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)

#define

NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)

#define

NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)

#define

NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)

#define

NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)

#define

NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)

#define

NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)

#define

NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)

#define

NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)

#define

NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)

#define

NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)

#define

NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)

#define

NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)

#define

NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)

#define

NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)

#define

NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)

#define

NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)

#define

NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)

#define

NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)

#define

NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)

#define

NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)

#define

NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)

#define

NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)

#define

NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)

#define

NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)

#define

NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)

#define

NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)

#define

NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)

#define

NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)

#define

NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)

#define

NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)

#define

NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)

#define

NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)

#define

NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)

#define

NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)

#define

NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)

#define

NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)

#define

NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)

#define

NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)

#define

NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)

#define

NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)

#define

NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)

#define

NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)

#define

NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)

#define

NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)

#define

NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)

#define

NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)

#define

NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)

#define

NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)

#define

NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)

#define

NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)

#define

NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)

#define

NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)

#define

NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)

#define

NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)

#define

NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)

#define

NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)

#define

NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)

#define

NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)

#define

OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000)

#define

OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000)

#define

OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000)

#define

OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000)

#define

OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040)

#define

OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020)

#define

OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000)

#define

OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080)

#define

OPAMP_CSR_OPA1PD ((uint32_t)0x00000001)

#define

OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000)

#define

OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000)

#define

OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000)

#define

OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000)

#define

OPAMP_CSR_OPA2PD ((uint32_t)0x00000100)

#define

OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000)

#define

OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000)

#define

OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000)

#define

OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000)

#define

OPAMP_CSR_OPA3PD ((uint32_t)0x00010000)

#define

OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002)

#define

OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200)

#define

OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000)

#define

OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004)

#define

OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400)

#define

OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000)

#define

OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008)

#define

OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800)

#define

OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000)

#define

OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010)

#define

OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000)

#define

OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000)

#define

OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000)

#define

OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF)

#define

OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00)

#define

OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000)

#define

OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF)

#define

OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00)

#define

OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000)

#define

OPAMP_OTR_OT_USER ((uint32_t)0x80000000)

#define

PWR_CR_CSBF ((uint16_t)0x0008)

#define

PWR_CR_CWUF ((uint16_t)0x0004)

#define

PWR_CR_DBP ((uint16_t)0x0100)

#define

PWR_CR_FWU ((uint16_t)0x0400)

#define

PWR_CR_LPRUN ((uint16_t)0x4000)

#define

PWR_CR_LPSDSR ((uint16_t)0x0001)

#define

PWR_CR_PDDS ((uint16_t)0x0002)

#define

PWR_CR_PLS ((uint16_t)0x00E0)

#define

PWR_CR_PLS_0 ((uint16_t)0x0020)

#define

PWR_CR_PLS_1 ((uint16_t)0x0040)

#define

PWR_CR_PLS_2 ((uint16_t)0x0080)

#define

PWR_CR_PLS_LEV0 ((uint16_t)0x0000)

#define

PWR_CR_PLS_LEV1 ((uint16_t)0x0020)

#define

PWR_CR_PLS_LEV2 ((uint16_t)0x0040)

#define

PWR_CR_PLS_LEV3 ((uint16_t)0x0060)

#define

PWR_CR_PLS_LEV4 ((uint16_t)0x0080)

#define

PWR_CR_PLS_LEV5 ((uint16_t)0x00A0)

#define

PWR_CR_PLS_LEV6 ((uint16_t)0x00C0)

#define

PWR_CR_PLS_LEV7 ((uint16_t)0x00E0)

#define

PWR_CR_PVDE ((uint16_t)0x0010)

#define

PWR_CR_ULP ((uint16_t)0x0200)

#define

PWR_CR_VOS ((uint16_t)0x1800)

#define

PWR_CR_VOS_0 ((uint16_t)0x0800)

#define

PWR_CR_VOS_1 ((uint16_t)0x1000)

#define

PWR_CSR_EWUP1 ((uint16_t)0x0100)

#define

PWR_CSR_EWUP2 ((uint16_t)0x0200)

#define

PWR_CSR_EWUP3 ((uint16_t)0x0400)

#define

PWR_CSR_PVDO ((uint16_t)0x0004)

#define

PWR_CSR_REGLPF ((uint16_t)0x0020)

#define

PWR_CSR_SBF ((uint16_t)0x0002)

#define

PWR_CSR_VOSF ((uint16_t)0x0010)

#define

PWR_CSR_VREFINTRDYF ((uint16_t)0x0008)

#define

PWR_CSR_WUF ((uint16_t)0x0001)

#define

RCC_AHBENR_AESEN ((uint32_t)0x08000000)

#define

RCC_AHBENR_CRCEN ((uint32_t)0x00001000)

#define

RCC_AHBENR_DMA1EN ((uint32_t)0x01000000)

#define

RCC_AHBENR_DMA2EN ((uint32_t)0x02000000)

#define

RCC_AHBENR_FLITFEN ((uint32_t)0x00008000)

#define

RCC_AHBENR_FSMCEN ((uint32_t)0x40000000)

#define

RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001)

#define

RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002)

#define

RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004)

#define

RCC_AHBENR_GPIODEN ((uint32_t)0x00000008)

#define

RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010)

#define

RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040)

#define

RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080)

#define

RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020)

#define

RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000)

#define

RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000)

#define

RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000)

#define

RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000)

#define

RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000)

#define

RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000)

#define

RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001)

#define

RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002)

#define

RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004)

#define

RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008)

#define

RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010)

#define

RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040)

#define

RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080)

#define

RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020)

#define

RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000)

#define

RCC_AHBRSTR_AESRST ((uint32_t)0x08000000)

#define

RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000)

#define

RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000)

#define

RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000)

#define

RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000)

#define

RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000)

#define

RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001)

#define

RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002)

#define

RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004)

#define

RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008)

#define

RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010)

#define

RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040)

#define

RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080)

#define

RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020)

#define

RCC_APB1ENR_COMPEN ((uint32_t)0x80000000)

#define

RCC_APB1ENR_DACEN ((uint32_t)0x20000000)

#define

RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)

#define

RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)

#define

RCC_APB1ENR_LCDEN ((uint32_t)0x00000200)

#define

RCC_APB1ENR_PWREN ((uint32_t)0x10000000)

#define

RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)

#define

RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)

#define

RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)

#define

RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)

#define

RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)

#define

RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)

#define

RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)

#define

RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)

#define

RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)

#define

RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)

#define

RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)

#define

RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)

#define

RCC_APB1ENR_USBEN ((uint32_t)0x00800000)

#define

RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)

#define

RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000)

#define

RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)

#define

RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)

#define

RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)

#define

RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200)

#define

RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)

#define

RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)

#define

RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)

#define

RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)

#define

RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)

#define

RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)

#define

RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)

#define

RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)

#define

RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)

#define

RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)

#define

RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)

#define

RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)

#define

RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)

#define

RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000)

#define

RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)

#define

RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000)

#define

RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)

#define

RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)

#define

RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)

#define

RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200)

#define

RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)

#define

RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)

#define

RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)

#define

RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)

#define

RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)

#define

RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)

#define

RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)

#define

RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)

#define

RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)

#define

RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)

#define

RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)

#define

RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)

#define

RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)

#define

RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)

#define

RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)

#define

RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)

#define

RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)

#define

RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)

#define

RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001)

#define

RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008)

#define

RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010)

#define

RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004)

#define

RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)

#define

RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200)

#define

RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)

#define

RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)

#define

RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001)

#define

RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008)

#define

RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010)

#define

RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004)

#define

RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000)

#define

RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)

#define

RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)

#define

RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)

#define

RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001)

#define

RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008)

#define

RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010)

#define

RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004)

#define

RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)

#define

RCC_CFGR_HPRE ((uint32_t)0x000000F0)

#define

RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)

#define

RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)

#define

RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)

#define

RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)

#define

RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)

#define

RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)

#define

RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)

#define

RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)

#define

RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)

#define

RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)

#define

RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)

#define

RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)

#define

RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000)

#define

RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000)

#define

RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000)

#define

RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000)

#define

RCC_CFGR_MCO_HSE ((uint32_t)0x04000000)

#define

RCC_CFGR_MCO_HSI ((uint32_t)0x02000000)

#define

RCC_CFGR_MCO_LSE ((uint32_t)0x07000000)

#define

RCC_CFGR_MCO_LSI ((uint32_t)0x06000000)

#define

RCC_CFGR_MCO_MSI ((uint32_t)0x03000000)

#define

RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)

#define

RCC_CFGR_MCO_PLL ((uint32_t)0x05000000)

#define

RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000)

#define

RCC_CFGR_MCOPRE ((uint32_t)0x70000000)

#define

RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000)

#define

RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000)

#define

RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000)

#define

RCC_CFGR_MCOSEL ((uint32_t)0x07000000)

#define

RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000)

#define

RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000)

#define

RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000)

#define

RCC_CFGR_PLLDIV ((uint32_t)0x00C00000)

#define

RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000)

#define

RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000)

#define

RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000)

#define

RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000)

#define

RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000)

#define

RCC_CFGR_PLLMUL ((uint32_t)0x003C0000)

#define

RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000)

#define

RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000)

#define

RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000)

#define

RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000)

#define

RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000)

#define

RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000)

#define

RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000)

#define

RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000)

#define

RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000)

#define

RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000)

#define

RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000)

#define

RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000)

#define

RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000)

#define

RCC_CFGR_PLLSRC ((uint32_t)0x00010000)

#define

RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)

#define

RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000)

#define

RCC_CFGR_PPRE1 ((uint32_t)0x00000700)

#define

RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)

#define

RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)

#define

RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)

#define

RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)

#define

RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)

#define

RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)

#define

RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)

#define

RCC_CFGR_PPRE2 ((uint32_t)0x00003800)

#define

RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)

#define

RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)

#define

RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)

#define

RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)

#define

RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)

#define

RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)

#define

RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)

#define

RCC_CFGR_SW ((uint32_t)0x00000003)

#define

RCC_CFGR_SW_0 ((uint32_t)0x00000001)

#define

RCC_CFGR_SW_1 ((uint32_t)0x00000002)

#define

RCC_CFGR_SW_HSE ((uint32_t)0x00000002)

#define

RCC_CFGR_SW_HSI ((uint32_t)0x00000001)

#define

RCC_CFGR_SW_MSI ((uint32_t)0x00000000)

#define

RCC_CFGR_SW_PLL ((uint32_t)0x00000003)

#define

RCC_CFGR_SWS ((uint32_t)0x0000000C)

#define

RCC_CFGR_SWS_0 ((uint32_t)0x00000004)

#define

RCC_CFGR_SWS_1 ((uint32_t)0x00000008)

#define

RCC_CFGR_SWS_HSE ((uint32_t)0x00000008)

#define

RCC_CFGR_SWS_HSI ((uint32_t)0x00000004)

#define

RCC_CFGR_SWS_MSI ((uint32_t)0x00000000)

#define

RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C)

#define

RCC_CIR_CSSC ((uint32_t)0x00800000)

#define

RCC_CIR_CSSF ((uint32_t)0x00000080)

#define

RCC_CIR_HSERDYC ((uint32_t)0x00080000)

#define

RCC_CIR_HSERDYF ((uint32_t)0x00000008)

#define

RCC_CIR_HSERDYIE ((uint32_t)0x00000800)

#define

RCC_CIR_HSIRDYC ((uint32_t)0x00040000)

#define

RCC_CIR_HSIRDYF ((uint32_t)0x00000004)

#define

RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)

#define

RCC_CIR_LSECSS ((uint32_t)0x00000040)

#define

RCC_CIR_LSECSSC ((uint32_t)0x00400000)

#define

RCC_CIR_LSECSSIE ((uint32_t)0x00004000)

#define

RCC_CIR_LSERDYC ((uint32_t)0x00020000)

#define

RCC_CIR_LSERDYF ((uint32_t)0x00000002)

#define

RCC_CIR_LSERDYIE ((uint32_t)0x00000200)

#define

RCC_CIR_LSIRDYC ((uint32_t)0x00010000)

#define

RCC_CIR_LSIRDYF ((uint32_t)0x00000001)

#define

RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)

#define

RCC_CIR_MSIRDYC ((uint32_t)0x00200000)

#define

RCC_CIR_MSIRDYF ((uint32_t)0x00000020)

#define

RCC_CIR_MSIRDYIE ((uint32_t)0x00002000)

#define

RCC_CIR_PLLRDYC ((uint32_t)0x00100000)

#define

RCC_CIR_PLLRDYF ((uint32_t)0x00000010)

#define

RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)

#define

RCC_CR_CSSON ((uint32_t)0x10000000)

#define

RCC_CR_HSEBYP ((uint32_t)0x00040000)

#define

RCC_CR_HSEON ((uint32_t)0x00010000)

#define

RCC_CR_HSERDY ((uint32_t)0x00020000)

#define

RCC_CR_HSION ((uint32_t)0x00000001)

#define

RCC_CR_HSIRDY ((uint32_t)0x00000002)

#define

RCC_CR_MSION ((uint32_t)0x00000100)

#define

RCC_CR_MSIRDY ((uint32_t)0x00000200)

#define

RCC_CR_PLLON ((uint32_t)0x01000000)

#define

RCC_CR_PLLRDY ((uint32_t)0x02000000)

#define

RCC_CR_RTCPRE ((uint32_t)0x60000000)

#define

RCC_CR_RTCPRE_0 ((uint32_t)0x20000000)

#define

RCC_CR_RTCPRE_1 ((uint32_t)0x40000000)

#define

RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)

#define

RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

#define

RCC_CSR_LSEBYP ((uint32_t)0x00000400)

#define

RCC_CSR_LSECSSD ((uint32_t)0x00001000)

#define

RCC_CSR_LSECSSON ((uint32_t)0x00000800)

#define

RCC_CSR_LSEON ((uint32_t)0x00000100)

#define

RCC_CSR_LSERDY ((uint32_t)0x00000200)

#define

RCC_CSR_LSION ((uint32_t)0x00000001)

#define

RCC_CSR_LSIRDY ((uint32_t)0x00000002)

#define

RCC_CSR_OBLRSTF ((uint32_t)0x02000000)

#define

RCC_CSR_PINRSTF ((uint32_t)0x04000000)

#define

RCC_CSR_PORRSTF ((uint32_t)0x08000000)

#define

RCC_CSR_RMVF ((uint32_t)0x01000000)

#define

RCC_CSR_RTCEN ((uint32_t)0x00400000)

#define

RCC_CSR_RTCRST ((uint32_t)0x00800000)

#define

RCC_CSR_RTCSEL ((uint32_t)0x00030000)

#define

RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000)

#define

RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000)

#define

RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000)

#define

RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000)

#define

RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000)

#define

RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)

#define

RCC_CSR_SFTRSTF ((uint32_t)0x10000000)

#define

RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)

#define

RCC_ICSCR_HSICAL ((uint32_t)0x000000FF)

#define

RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00)

#define

RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000)

#define

RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000)

#define

RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000)

#define

RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000)

#define

RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000)

#define

RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000)

#define

RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000)

#define

RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000)

#define

RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000)

#define

RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000)

#define

RI_ASCR1_CH ((uint32_t)0x03FCFFFF)

#define

RI_ASCR1_CH_0 ((uint32_t)0x00000001)

#define

RI_ASCR1_CH_1 ((uint32_t)0x00000002)

#define

RI_ASCR1_CH_10 ((uint32_t)0x00000400)

#define

RI_ASCR1_CH_11 ((uint32_t)0x00000800)

#define

RI_ASCR1_CH_12 ((uint32_t)0x00001000)

#define

RI_ASCR1_CH_13 ((uint32_t)0x00002000)

#define

RI_ASCR1_CH_14 ((uint32_t)0x00004000)

#define

RI_ASCR1_CH_15 ((uint32_t)0x00008000)

#define

RI_ASCR1_CH_18 ((uint32_t)0x00040000)

#define

RI_ASCR1_CH_19 ((uint32_t)0x00080000)

#define

RI_ASCR1_CH_2 ((uint32_t)0x00000004)

#define

RI_ASCR1_CH_20 ((uint32_t)0x00100000)

#define

RI_ASCR1_CH_21 ((uint32_t)0x00200000)

#define

RI_ASCR1_CH_22 ((uint32_t)0x00400000)

#define

RI_ASCR1_CH_23 ((uint32_t)0x00800000)

#define

RI_ASCR1_CH_24 ((uint32_t)0x01000000)

#define

RI_ASCR1_CH_25 ((uint32_t)0x02000000)

#define

RI_ASCR1_CH_27 ((uint32_t)0x00400000)

#define

RI_ASCR1_CH_28 ((uint32_t)0x00800000)

#define

RI_ASCR1_CH_29 ((uint32_t)0x01000000)

#define

RI_ASCR1_CH_3 ((uint32_t)0x00000008)

#define

RI_ASCR1_CH_30 ((uint32_t)0x02000000)

#define

RI_ASCR1_CH_31 ((uint32_t)0x00010000)

#define

RI_ASCR1_CH_4 ((uint32_t)0x00000010)

#define

RI_ASCR1_CH_5 ((uint32_t)0x00000020)

#define

RI_ASCR1_CH_6 ((uint32_t)0x00000040)

#define

RI_ASCR1_CH_7 ((uint32_t)0x00000080)

#define

RI_ASCR1_CH_8 ((uint32_t)0x00000100)

#define

RI_ASCR1_CH_9 ((uint32_t)0x00000200)

#define

RI_ASCR1_SCM ((uint32_t)0x80000000)

#define

RI_ASCR1_VCOMP ((uint32_t)0x04000000)

#define

RI_ASCR2_CH0b ((uint32_t)0x00010000)

#define

RI_ASCR2_CH10b ((uint32_t)0x01000000)

#define

RI_ASCR2_CH11b ((uint32_t)0x02000000)

#define

RI_ASCR2_CH12b ((uint32_t)0x04000000)

#define

RI_ASCR2_CH1b ((uint32_t)0x00020000)

#define

RI_ASCR2_CH2b ((uint32_t)0x00040000)

#define

RI_ASCR2_CH3b ((uint32_t)0x00080000)

#define

RI_ASCR2_CH6b ((uint32_t)0x00100000)

#define

RI_ASCR2_CH7b ((uint32_t)0x00200000)

#define

RI_ASCR2_CH8b ((uint32_t)0x00400000)

#define

RI_ASCR2_CH9b ((uint32_t)0x00800000)

#define

RI_ASCR2_GR10_1 ((uint32_t)0x00000001)

#define

RI_ASCR2_GR10_2 ((uint32_t)0x00000002)

#define

RI_ASCR2_GR10_3 ((uint32_t)0x00000004)

#define

RI_ASCR2_GR10_4 ((uint32_t)0x00000008)

#define

RI_ASCR2_GR4_1 ((uint32_t)0x00000200)

#define

RI_ASCR2_GR4_2 ((uint32_t)0x00000400)

#define

RI_ASCR2_GR4_3 ((uint32_t)0x00000800)

#define

RI_ASCR2_GR4_4 ((uint32_t)0x00008000)

#define

RI_ASCR2_GR5_1 ((uint32_t)0x00000040)

#define

RI_ASCR2_GR5_2 ((uint32_t)0x00000080)

#define

RI_ASCR2_GR5_3 ((uint32_t)0x00000100)

#define

RI_ASCR2_GR5_4 ((uint32_t)0x20000000)

#define

RI_ASCR2_GR6_1 ((uint32_t)0x00000010)

#define

RI_ASCR2_GR6_2 ((uint32_t)0x00000020)

#define

RI_ASCR2_GR6_3 ((uint32_t)0x08000000)

#define

RI_ASCR2_GR6_4 ((uint32_t)0x10000000)

#define

RI_HYSCR1_PA ((uint32_t)0x0000FFFF)

#define

RI_HYSCR1_PA_0 ((uint32_t)0x00000001)

#define

RI_HYSCR1_PA_1 ((uint32_t)0x00000002)

#define

RI_HYSCR1_PA_10 ((uint32_t)0x00000400)

#define

RI_HYSCR1_PA_11 ((uint32_t)0x00000800)

#define

RI_HYSCR1_PA_12 ((uint32_t)0x00001000)

#define

RI_HYSCR1_PA_13 ((uint32_t)0x00002000)

#define

RI_HYSCR1_PA_14 ((uint32_t)0x00004000)

#define

RI_HYSCR1_PA_15 ((uint32_t)0x00008000)

#define

RI_HYSCR1_PA_2 ((uint32_t)0x00000004)

#define

RI_HYSCR1_PA_3 ((uint32_t)0x00000008)

#define

RI_HYSCR1_PA_4 ((uint32_t)0x00000010)

#define

RI_HYSCR1_PA_5 ((uint32_t)0x00000020)

#define

RI_HYSCR1_PA_6 ((uint32_t)0x00000040)

#define

RI_HYSCR1_PA_7 ((uint32_t)0x00000080)

#define

RI_HYSCR1_PA_8 ((uint32_t)0x00000100)

#define

RI_HYSCR1_PA_9 ((uint32_t)0x00000200)

#define

RI_HYSCR1_PB ((uint32_t)0xFFFF0000)

#define

RI_HYSCR1_PB_0 ((uint32_t)0x00010000)

#define

RI_HYSCR1_PB_1 ((uint32_t)0x00020000)

#define

RI_HYSCR1_PB_10 ((uint32_t)0x04000000)

#define

RI_HYSCR1_PB_11 ((uint32_t)0x08000000)

#define

RI_HYSCR1_PB_12 ((uint32_t)0x10000000)

#define

RI_HYSCR1_PB_13 ((uint32_t)0x20000000)

#define

RI_HYSCR1_PB_14 ((uint32_t)0x40000000)

#define

RI_HYSCR1_PB_15 ((uint32_t)0x80000000)

#define

RI_HYSCR1_PB_2 ((uint32_t)0x00040000)

#define

RI_HYSCR1_PB_3 ((uint32_t)0x00080000)

#define

RI_HYSCR1_PB_4 ((uint32_t)0x00100000)

#define

RI_HYSCR1_PB_5 ((uint32_t)0x00200000)

#define

RI_HYSCR1_PB_6 ((uint32_t)0x00400000)

#define

RI_HYSCR1_PB_7 ((uint32_t)0x00800000)

#define

RI_HYSCR1_PB_8 ((uint32_t)0x01000000)

#define

RI_HYSCR1_PB_9 ((uint32_t)0x02000000)

#define

RI_HYSCR2_PC ((uint32_t)0x0000FFFF)

#define

RI_HYSCR2_PC_0 ((uint32_t)0x00000001)

#define

RI_HYSCR2_PC_1 ((uint32_t)0x00000002)

#define

RI_HYSCR2_PC_10 ((uint32_t)0x00000400)

#define

RI_HYSCR2_PC_11 ((uint32_t)0x00000800)

#define

RI_HYSCR2_PC_12 ((uint32_t)0x00001000)

#define

RI_HYSCR2_PC_13 ((uint32_t)0x00002000)

#define

RI_HYSCR2_PC_14 ((uint32_t)0x00004000)

#define

RI_HYSCR2_PC_15 ((uint32_t)0x00008000)

#define

RI_HYSCR2_PC_2 ((uint32_t)0x00000004)

#define

RI_HYSCR2_PC_3 ((uint32_t)0x00000008)

#define

RI_HYSCR2_PC_4 ((uint32_t)0x00000010)

#define

RI_HYSCR2_PC_5 ((uint32_t)0x00000020)

#define

RI_HYSCR2_PC_6 ((uint32_t)0x00000040)

#define

RI_HYSCR2_PC_7 ((uint32_t)0x00000080)

#define

RI_HYSCR2_PC_8 ((uint32_t)0x00000100)

#define

RI_HYSCR2_PC_9 ((uint32_t)0x00000200)

#define

RI_HYSCR2_PD ((uint32_t)0xFFFF0000)

#define

RI_HYSCR2_PD_0 ((uint32_t)0x00010000)

#define

RI_HYSCR2_PD_1 ((uint32_t)0x00020000)

#define

RI_HYSCR2_PD_10 ((uint32_t)0x04000000)

#define

RI_HYSCR2_PD_11 ((uint32_t)0x08000000)

#define

RI_HYSCR2_PD_12 ((uint32_t)0x10000000)

#define

RI_HYSCR2_PD_13 ((uint32_t)0x20000000)

#define

RI_HYSCR2_PD_14 ((uint32_t)0x40000000)

#define

RI_HYSCR2_PD_15 ((uint32_t)0x80000000)

#define

RI_HYSCR2_PD_2 ((uint32_t)0x00040000)

#define

RI_HYSCR2_PD_3 ((uint32_t)0x00080000)

#define

RI_HYSCR2_PD_4 ((uint32_t)0x00100000)

#define

RI_HYSCR2_PD_5 ((uint32_t)0x00200000)

#define

RI_HYSCR2_PD_6 ((uint32_t)0x00400000)

#define

RI_HYSCR2_PD_7 ((uint32_t)0x00800000)

#define

RI_HYSCR2_PD_8 ((uint32_t)0x01000000)

#define

RI_HYSCR2_PD_9 ((uint32_t)0x02000000)

#define

RI_HYSCR2_PE ((uint32_t)0x0000FFFF)

#define

RI_HYSCR2_PE_0 ((uint32_t)0x00000001)

#define

RI_HYSCR2_PE_1 ((uint32_t)0x00000002)

#define

RI_HYSCR2_PE_10 ((uint32_t)0x00000400)

#define

RI_HYSCR2_PE_11 ((uint32_t)0x00000800)

#define

RI_HYSCR2_PE_12 ((uint32_t)0x00001000)

#define

RI_HYSCR2_PE_13 ((uint32_t)0x00002000)

#define

RI_HYSCR2_PE_14 ((uint32_t)0x00004000)

#define

RI_HYSCR2_PE_15 ((uint32_t)0x00008000)

#define

RI_HYSCR2_PE_2 ((uint32_t)0x00000004)

#define

RI_HYSCR2_PE_3 ((uint32_t)0x00000008)

#define

RI_HYSCR2_PE_4 ((uint32_t)0x00000010)

#define

RI_HYSCR2_PE_5 ((uint32_t)0x00000020)

#define

RI_HYSCR2_PE_6 ((uint32_t)0x00000040)

#define

RI_HYSCR2_PE_7 ((uint32_t)0x00000080)

#define

RI_HYSCR2_PE_8 ((uint32_t)0x00000100)

#define

RI_HYSCR2_PE_9 ((uint32_t)0x00000200)

#define

RI_HYSCR3_PF ((uint32_t)0xFFFF0000)

#define

RI_HYSCR3_PF_0 ((uint32_t)0x00010000)

#define

RI_HYSCR3_PF_1 ((uint32_t)0x00020000)

#define

RI_HYSCR3_PF_10 ((uint32_t)0x04000000)

#define

RI_HYSCR3_PF_11 ((uint32_t)0x08000000)

#define

RI_HYSCR3_PF_12 ((uint32_t)0x10000000)

#define

RI_HYSCR3_PF_13 ((uint32_t)0x20000000)

#define

RI_HYSCR3_PF_14 ((uint32_t)0x40000000)

#define

RI_HYSCR3_PF_15 ((uint32_t)0x80000000)

#define

RI_HYSCR3_PF_2 ((uint32_t)0x00040000)

#define

RI_HYSCR3_PF_3 ((uint32_t)0x00080000)

#define

RI_HYSCR3_PF_4 ((uint32_t)0x00100000)

#define

RI_HYSCR3_PF_5 ((uint32_t)0x00200000)

#define

RI_HYSCR3_PF_6 ((uint32_t)0x00400000)

#define

RI_HYSCR3_PF_7 ((uint32_t)0x00800000)

#define

RI_HYSCR3_PF_8 ((uint32_t)0x01000000)

#define

RI_HYSCR3_PF_9 ((uint32_t)0x02000000)

#define

RI_HYSCR4_PG ((uint32_t)0x0000FFFF)

#define

RI_HYSCR4_PG_0 ((uint32_t)0x00000001)

#define

RI_HYSCR4_PG_1 ((uint32_t)0x00000002)

#define

RI_HYSCR4_PG_10 ((uint32_t)0x00000400)

#define

RI_HYSCR4_PG_11 ((uint32_t)0x00000800)

#define

RI_HYSCR4_PG_12 ((uint32_t)0x00001000)

#define

RI_HYSCR4_PG_13 ((uint32_t)0x00002000)

#define

RI_HYSCR4_PG_14 ((uint32_t)0x00004000)

#define

RI_HYSCR4_PG_15 ((uint32_t)0x00008000)

#define

RI_HYSCR4_PG_2 ((uint32_t)0x00000004)

#define

RI_HYSCR4_PG_3 ((uint32_t)0x00000008)

#define

RI_HYSCR4_PG_4 ((uint32_t)0x00000010)

#define

RI_HYSCR4_PG_5 ((uint32_t)0x00000020)

#define

RI_HYSCR4_PG_6 ((uint32_t)0x00000040)

#define

RI_HYSCR4_PG_7 ((uint32_t)0x00000080)

#define

RI_HYSCR4_PG_8 ((uint32_t)0x00000100)

#define

RI_HYSCR4_PG_9 ((uint32_t)0x00000200)

#define

RI_ICR_IC1 ((uint32_t)0x00040000)

#define

RI_ICR_IC1Z ((uint32_t)0x0000000F)

#define

RI_ICR_IC1Z_0 ((uint32_t)0x00000001)

#define

RI_ICR_IC1Z_1 ((uint32_t)0x00000002)

#define

RI_ICR_IC1Z_2 ((uint32_t)0x00000004)

#define

RI_ICR_IC1Z_3 ((uint32_t)0x00000008)

#define

RI_ICR_IC2 ((uint32_t)0x00080000)

#define

RI_ICR_IC2Z ((uint32_t)0x000000F0)

#define

RI_ICR_IC2Z_0 ((uint32_t)0x00000010)

#define

RI_ICR_IC2Z_1 ((uint32_t)0x00000020)

#define

RI_ICR_IC2Z_2 ((uint32_t)0x00000040)

#define

RI_ICR_IC2Z_3 ((uint32_t)0x00000080)

#define

RI_ICR_IC3 ((uint32_t)0x00100000)

#define

RI_ICR_IC3Z ((uint32_t)0x00000F00)

#define

RI_ICR_IC3Z_0 ((uint32_t)0x00000100)

#define

RI_ICR_IC3Z_1 ((uint32_t)0x00000200)

#define

RI_ICR_IC3Z_2 ((uint32_t)0x00000400)

#define

RI_ICR_IC3Z_3 ((uint32_t)0x00000800)

#define

RI_ICR_IC4 ((uint32_t)0x00200000)

#define

RI_ICR_IC4Z ((uint32_t)0x0000F000)

#define

RI_ICR_IC4Z_0 ((uint32_t)0x00001000)

#define

RI_ICR_IC4Z_1 ((uint32_t)0x00002000)

#define

RI_ICR_IC4Z_2 ((uint32_t)0x00004000)

#define

RI_ICR_IC4Z_3 ((uint32_t)0x00008000)

#define

RI_ICR_TIM ((uint32_t)0x00030000)

#define

RI_ICR_TIM_0 ((uint32_t)0x00010000)

#define

RI_ICR_TIM_1 ((uint32_t)0x00020000)

#define

RTC_ALRMAR_DT ((uint32_t)0x30000000)

#define

RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)

#define

RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)

#define

RTC_ALRMAR_DU ((uint32_t)0x0F000000)

#define

RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)

#define

RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)

#define

RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)

#define

RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)

#define

RTC_ALRMAR_HT ((uint32_t)0x00300000)

#define

RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)

#define

RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)

#define

RTC_ALRMAR_HU ((uint32_t)0x000F0000)

#define

RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)

#define

RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)

#define

RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)

#define

RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)

#define

RTC_ALRMAR_MNT ((uint32_t)0x00007000)

#define

RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)

#define

RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)

#define

RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)

#define

RTC_ALRMAR_MNU ((uint32_t)0x00000F00)

#define

RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)

#define

RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)

#define

RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)

#define

RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)

#define

RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)

#define

RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)

#define

RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)

#define

RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)

#define

RTC_ALRMAR_PM ((uint32_t)0x00400000)

#define

RTC_ALRMAR_ST ((uint32_t)0x00000070)

#define

RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)

#define

RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)

#define

RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)

#define

RTC_ALRMAR_SU ((uint32_t)0x0000000F)

#define

RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)

#define

RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)

#define

RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)

#define

RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)

#define

RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)

#define

RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)

#define

RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)

#define

RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)

#define

RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)

#define

RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)

#define

RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)

#define

RTC_ALRMBR_DT ((uint32_t)0x30000000)

#define

RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)

#define

RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)

#define

RTC_ALRMBR_DU ((uint32_t)0x0F000000)

#define

RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)

#define

RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)

#define

RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)

#define

RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)

#define

RTC_ALRMBR_HT ((uint32_t)0x00300000)

#define

RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)

#define

RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)

#define

RTC_ALRMBR_HU ((uint32_t)0x000F0000)

#define

RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)

#define

RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)

#define

RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)

#define

RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)

#define

RTC_ALRMBR_MNT ((uint32_t)0x00007000)

#define

RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)

#define

RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)

#define

RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)

#define

RTC_ALRMBR_MNU ((uint32_t)0x00000F00)

#define

RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)

#define

RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)

#define

RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)

#define

RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)

#define

RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)

#define

RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)

#define

RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)

#define

RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)

#define

RTC_ALRMBR_PM ((uint32_t)0x00400000)

#define

RTC_ALRMBR_ST ((uint32_t)0x00000070)

#define

RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)

#define

RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)

#define

RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)

#define

RTC_ALRMBR_SU ((uint32_t)0x0000000F)

#define

RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)

#define

RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)

#define

RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)

#define

RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)

#define

RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)

#define

RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)

#define

RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)

#define

RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)

#define

RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)

#define

RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)

#define

RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)

#define

RTC_BKP0R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP10R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP11R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP12R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP13R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP14R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP15R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP16R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP17R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP18R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP19R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP1R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP20R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP21R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP22R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP23R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP24R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP25R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP26R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP27R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP28R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP29R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP2R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP30R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP31R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP3R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP4R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP5R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP6R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP7R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP8R ((uint32_t)0xFFFFFFFF)

#define

RTC_BKP9R ((uint32_t)0xFFFFFFFF)

#define

RTC_CALIBR_DC ((uint32_t)0x0000001F)

#define

RTC_CALIBR_DCS ((uint32_t)0x00000080)

#define

RTC_CALR_CALM ((uint32_t)0x000001FF)

#define

RTC_CALR_CALM_0 ((uint32_t)0x00000001)

#define

RTC_CALR_CALM_1 ((uint32_t)0x00000002)

#define

RTC_CALR_CALM_2 ((uint32_t)0x00000004)

#define

RTC_CALR_CALM_3 ((uint32_t)0x00000008)

#define

RTC_CALR_CALM_4 ((uint32_t)0x00000010)

#define

RTC_CALR_CALM_5 ((uint32_t)0x00000020)

#define

RTC_CALR_CALM_6 ((uint32_t)0x00000040)

#define

RTC_CALR_CALM_7 ((uint32_t)0x00000080)

#define

RTC_CALR_CALM_8 ((uint32_t)0x00000100)

#define

RTC_CALR_CALP ((uint32_t)0x00008000)

#define

RTC_CALR_CALW16 ((uint32_t)0x00002000)

#define

RTC_CALR_CALW8 ((uint32_t)0x00004000)

#define

RTC_CR_ADD1H ((uint32_t)0x00010000)

#define

RTC_CR_ALRAE ((uint32_t)0x00000100)

#define

RTC_CR_ALRAIE ((uint32_t)0x00001000)

#define

RTC_CR_ALRBE ((uint32_t)0x00000200)

#define

RTC_CR_ALRBIE ((uint32_t)0x00002000)

#define

RTC_CR_BCK ((uint32_t)0x00040000)

#define

RTC_CR_BYPSHAD ((uint32_t)0x00000020)

#define

RTC_CR_COE ((uint32_t)0x00800000)

#define

RTC_CR_COSEL ((uint32_t)0x00080000)

#define

RTC_CR_DCE ((uint32_t)0x00000080)

#define

RTC_CR_FMT ((uint32_t)0x00000040)

#define

RTC_CR_OSEL ((uint32_t)0x00600000)

#define

RTC_CR_OSEL_0 ((uint32_t)0x00200000)

#define

RTC_CR_OSEL_1 ((uint32_t)0x00400000)

#define

RTC_CR_POL ((uint32_t)0x00100000)

#define

RTC_CR_REFCKON ((uint32_t)0x00000010)

#define

RTC_CR_SUB1H ((uint32_t)0x00020000)

#define

RTC_CR_TSE ((uint32_t)0x00000800)

#define

RTC_CR_TSEDGE ((uint32_t)0x00000008)

#define

RTC_CR_TSIE ((uint32_t)0x00008000)

#define

RTC_CR_WUCKSEL ((uint32_t)0x00000007)

#define

RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)

#define

RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)

#define

RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)

#define

RTC_CR_WUTE ((uint32_t)0x00000400)

#define

RTC_CR_WUTIE ((uint32_t)0x00004000)

#define

RTC_DR_DT ((uint32_t)0x00000030)

#define

RTC_DR_DT_0 ((uint32_t)0x00000010)

#define

RTC_DR_DT_1 ((uint32_t)0x00000020)

#define

RTC_DR_DU ((uint32_t)0x0000000F)

#define

RTC_DR_DU_0 ((uint32_t)0x00000001)

#define

RTC_DR_DU_1 ((uint32_t)0x00000002)

#define

RTC_DR_DU_2 ((uint32_t)0x00000004)

#define

RTC_DR_DU_3 ((uint32_t)0x00000008)

#define

RTC_DR_MT ((uint32_t)0x00001000)

#define

RTC_DR_MU ((uint32_t)0x00000F00)

#define

RTC_DR_MU_0 ((uint32_t)0x00000100)

#define

RTC_DR_MU_1 ((uint32_t)0x00000200)

#define

RTC_DR_MU_2 ((uint32_t)0x00000400)

#define

RTC_DR_MU_3 ((uint32_t)0x00000800)

#define

RTC_DR_WDU ((uint32_t)0x0000E000)

#define

RTC_DR_WDU_0 ((uint32_t)0x00002000)

#define

RTC_DR_WDU_1 ((uint32_t)0x00004000)

#define

RTC_DR_WDU_2 ((uint32_t)0x00008000)

#define

RTC_DR_YT ((uint32_t)0x00F00000)

#define

RTC_DR_YT_0 ((uint32_t)0x00100000)

#define

RTC_DR_YT_1 ((uint32_t)0x00200000)

#define

RTC_DR_YT_2 ((uint32_t)0x00400000)

#define

RTC_DR_YT_3 ((uint32_t)0x00800000)

#define

RTC_DR_YU ((uint32_t)0x000F0000)

#define

RTC_DR_YU_0 ((uint32_t)0x00010000)

#define

RTC_DR_YU_1 ((uint32_t)0x00020000)

#define

RTC_DR_YU_2 ((uint32_t)0x00040000)

#define

RTC_DR_YU_3 ((uint32_t)0x00080000)

#define

RTC_ISR_ALRAF ((uint32_t)0x00000100)

#define

RTC_ISR_ALRAWF ((uint32_t)0x00000001)

#define

RTC_ISR_ALRBF ((uint32_t)0x00000200)

#define

RTC_ISR_ALRBWF ((uint32_t)0x00000002)

#define

RTC_ISR_INIT ((uint32_t)0x00000080)

#define

RTC_ISR_INITF ((uint32_t)0x00000040)

#define

RTC_ISR_INITS ((uint32_t)0x00000010)

#define

RTC_ISR_RECALPF ((uint32_t)0x00010000)

#define

RTC_ISR_RSF ((uint32_t)0x00000020)

#define

RTC_ISR_SHPF ((uint32_t)0x00000008)

#define

RTC_ISR_TAMP1F ((uint32_t)0x00002000)

#define

RTC_ISR_TAMP2F ((uint32_t)0x00004000)

#define

RTC_ISR_TAMP3F ((uint32_t)0x00008000)

#define

RTC_ISR_TSF ((uint32_t)0x00000800)

#define

RTC_ISR_TSOVF ((uint32_t)0x00001000)

#define

RTC_ISR_WUTF ((uint32_t)0x00000400)

#define

RTC_ISR_WUTWF ((uint32_t)0x00000004)

#define

RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)

#define

RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)

#define

RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)

#define

RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)

#define

RTC_SSR_SS ((uint32_t)0x0000FFFF)

#define

RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)

#define

RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)

#define

RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)

#define

RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)

#define

RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)

#define

RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)

#define

RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)

#define

RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)

#define

RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)

#define

RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)

#define

RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)

#define

RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)

#define

RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)

#define

RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)

#define

RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)

#define

RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)

#define

RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)

#define

RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)

#define

RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)

#define

RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)

#define

RTC_TR_HT ((uint32_t)0x00300000)

#define

RTC_TR_HT_0 ((uint32_t)0x00100000)

#define

RTC_TR_HT_1 ((uint32_t)0x00200000)

#define

RTC_TR_HU ((uint32_t)0x000F0000)

#define

RTC_TR_HU_0 ((uint32_t)0x00010000)

#define

RTC_TR_HU_1 ((uint32_t)0x00020000)

#define

RTC_TR_HU_2 ((uint32_t)0x00040000)

#define

RTC_TR_HU_3 ((uint32_t)0x00080000)

#define

RTC_TR_MNT ((uint32_t)0x00007000)

#define

RTC_TR_MNT_0 ((uint32_t)0x00001000)

#define

RTC_TR_MNT_1 ((uint32_t)0x00002000)

#define

RTC_TR_MNT_2 ((uint32_t)0x00004000)

#define

RTC_TR_MNU ((uint32_t)0x00000F00)

#define

RTC_TR_MNU_0 ((uint32_t)0x00000100)

#define

RTC_TR_MNU_1 ((uint32_t)0x00000200)

#define

RTC_TR_MNU_2 ((uint32_t)0x00000400)

#define

RTC_TR_MNU_3 ((uint32_t)0x00000800)

#define

RTC_TR_PM ((uint32_t)0x00400000)

#define

RTC_TR_ST ((uint32_t)0x00000070)

#define

RTC_TR_ST_0 ((uint32_t)0x00000010)

#define

RTC_TR_ST_1 ((uint32_t)0x00000020)

#define

RTC_TR_ST_2 ((uint32_t)0x00000040)

#define

RTC_TR_SU ((uint32_t)0x0000000F)

#define

RTC_TR_SU_0 ((uint32_t)0x00000001)

#define

RTC_TR_SU_1 ((uint32_t)0x00000002)

#define

RTC_TR_SU_2 ((uint32_t)0x00000004)

#define

RTC_TR_SU_3 ((uint32_t)0x00000008)

#define

RTC_TSDR_DT ((uint32_t)0x00000030)

#define

RTC_TSDR_DT_0 ((uint32_t)0x00000010)

#define

RTC_TSDR_DT_1 ((uint32_t)0x00000020)

#define

RTC_TSDR_DU ((uint32_t)0x0000000F)

#define

RTC_TSDR_DU_0 ((uint32_t)0x00000001)

#define

RTC_TSDR_DU_1 ((uint32_t)0x00000002)

#define

RTC_TSDR_DU_2 ((uint32_t)0x00000004)

#define

RTC_TSDR_DU_3 ((uint32_t)0x00000008)

#define

RTC_TSDR_MT ((uint32_t)0x00001000)

#define

RTC_TSDR_MU ((uint32_t)0x00000F00)

#define

RTC_TSDR_MU_0 ((uint32_t)0x00000100)

#define

RTC_TSDR_MU_1 ((uint32_t)0x00000200)

#define

RTC_TSDR_MU_2 ((uint32_t)0x00000400)

#define

RTC_TSDR_MU_3 ((uint32_t)0x00000800)

#define

RTC_TSDR_WDU ((uint32_t)0x0000E000)

#define

RTC_TSDR_WDU_0 ((uint32_t)0x00002000)

#define

RTC_TSDR_WDU_1 ((uint32_t)0x00004000)

#define

RTC_TSDR_WDU_2 ((uint32_t)0x00008000)

#define

RTC_TSSSR_SS ((uint32_t)0x0000FFFF)

#define

RTC_TSTR_HT ((uint32_t)0x00300000)

#define

RTC_TSTR_HT_0 ((uint32_t)0x00100000)

#define

RTC_TSTR_HT_1 ((uint32_t)0x00200000)

#define

RTC_TSTR_HU ((uint32_t)0x000F0000)

#define

RTC_TSTR_HU_0 ((uint32_t)0x00010000)

#define

RTC_TSTR_HU_1 ((uint32_t)0x00020000)

#define

RTC_TSTR_HU_2 ((uint32_t)0x00040000)

#define

RTC_TSTR_HU_3 ((uint32_t)0x00080000)

#define

RTC_TSTR_MNT ((uint32_t)0x00007000)

#define

RTC_TSTR_MNT_0 ((uint32_t)0x00001000)

#define

RTC_TSTR_MNT_1 ((uint32_t)0x00002000)

#define

RTC_TSTR_MNT_2 ((uint32_t)0x00004000)

#define

RTC_TSTR_MNU ((uint32_t)0x00000F00)

#define

RTC_TSTR_MNU_0 ((uint32_t)0x00000100)

#define

RTC_TSTR_MNU_1 ((uint32_t)0x00000200)

#define

RTC_TSTR_MNU_2 ((uint32_t)0x00000400)

#define

RTC_TSTR_MNU_3 ((uint32_t)0x00000800)

#define

RTC_TSTR_PM ((uint32_t)0x00400000)

#define

RTC_TSTR_ST ((uint32_t)0x00000070)

#define

RTC_TSTR_ST_0 ((uint32_t)0x00000010)

#define

RTC_TSTR_ST_1 ((uint32_t)0x00000020)

#define

RTC_TSTR_ST_2 ((uint32_t)0x00000040)

#define

RTC_TSTR_SU ((uint32_t)0x0000000F)

#define

RTC_TSTR_SU_0 ((uint32_t)0x00000001)

#define

RTC_TSTR_SU_1 ((uint32_t)0x00000002)

#define

RTC_TSTR_SU_2 ((uint32_t)0x00000004)

#define

RTC_TSTR_SU_3 ((uint32_t)0x00000008)

#define

RTC_WPR_KEY ((uint32_t)0x000000FF)

#define

RTC_WUTR_WUT ((uint32_t)0x0000FFFF)

#define

SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)

#define

SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)

#define

SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)

#define

SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)

#define

SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)

#define

SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)

#define

SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)

#define

SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)

#define

SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)

#define

SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)

#define

SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)

#define

SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)

#define

SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)

#define

SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)

#define

SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)

#define

SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)

#define

SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)

#define

SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)

#define

SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

#define

SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)

#define

SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)

#define

SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)

#define

SCB_CCR_STKALIGN ((uint16_t)0x0200)

#define

SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)

#define

SCB_CCR_USERSETMPEND ((uint16_t)0x0002)

#define

SCB_CFSR_BFARVALID ((uint32_t)0x00008000)

#define

SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)

#define

SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)

#define

SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)

#define

SCB_CFSR_IBUSERR ((uint32_t)0x00000100)

#define

SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)

#define

SCB_CFSR_INVPC ((uint32_t)0x00040000)

#define

SCB_CFSR_INVSTATE ((uint32_t)0x00020000)

#define

SCB_CFSR_MMARVALID ((uint32_t)0x00000080)

#define

SCB_CFSR_MSTKERR ((uint32_t)0x00000010)

#define

SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)

#define

SCB_CFSR_NOCP ((uint32_t)0x00080000)

#define

SCB_CFSR_PRECISERR ((uint32_t)0x00000200)

#define

SCB_CFSR_STKERR ((uint32_t)0x00001000)

#define

SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)

#define

SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)

#define

SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)

#define

SCB_CPUID_Constant ((uint32_t)0x000F0000)

#define

SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)

#define

SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)

#define

SCB_CPUID_REVISION ((uint32_t)0x0000000F)

#define

SCB_CPUID_VARIANT ((uint32_t)0x00F00000)

#define

SCB_DFSR_BKPT ((uint8_t)0x02)

#define

SCB_DFSR_DWTTRAP ((uint8_t)0x04)

#define

SCB_DFSR_EXTERNAL ((uint8_t)0x10)

#define

SCB_DFSR_HALTED ((uint8_t)0x01)

#define

SCB_DFSR_VCATCH ((uint8_t)0x08)

#define

SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)

#define

SCB_HFSR_FORCED ((uint32_t)0x40000000)

#define

SCB_HFSR_VECTTBL ((uint32_t)0x00000002)

#define

SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)

#define

SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)

#define

SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)

#define

SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)

#define

SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)

#define

SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)

#define

SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)

#define

SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)

#define

SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)

#define

SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)

#define

SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

#define

SCB_SCR_SEVONPEND ((uint8_t)0x10)

#define

SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

#define

SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

#define

SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)

#define

SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)

#define

SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)

#define

SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)

#define

SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)

#define

SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)

#define

SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)

#define

SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)

#define

SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)

#define

SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)

#define

SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)

#define

SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)

#define

SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)

#define

SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)

#define

SCB_SHPR_PRI_N ((uint32_t)0x000000FF)

#define

SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)

#define

SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)

#define

SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)

#define

SCB_VTOR_TBLBASE ((uint32_t)0x20000000)

#define

SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)

#define

SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)

#define

SDIO_CLKCR_BYPASS ((uint16_t)0x0400)

#define

SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)

#define

SDIO_CLKCR_CLKEN ((uint16_t)0x0100)

#define

SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)

#define

SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)

#define

SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)

#define

SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)

#define

SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)

#define

SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)

#define

SDIO_CMD_CEATACMD ((uint16_t)0x4000)

#define

SDIO_CMD_CMDINDEX ((uint16_t)0x003F)

#define

SDIO_CMD_CPSMEN ((uint16_t)0x0400)

#define

SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)

#define

SDIO_CMD_NIEN ((uint16_t)0x2000)

#define

SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)

#define

SDIO_CMD_WAITINT ((uint16_t)0x0100)

#define

SDIO_CMD_WAITPEND ((uint16_t)0x0200)

#define

SDIO_CMD_WAITRESP ((uint16_t)0x00C0)

#define

SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)

#define

SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)

#define

SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)

#define

SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)

#define

SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)

#define

SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)

#define

SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)

#define

SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)

#define

SDIO_DCTRL_DMAEN ((uint16_t)0x0008)

#define

SDIO_DCTRL_DTDIR ((uint16_t)0x0002)

#define

SDIO_DCTRL_DTEN ((uint16_t)0x0001)

#define

SDIO_DCTRL_DTMODE ((uint16_t)0x0004)

#define

SDIO_DCTRL_RWMOD ((uint16_t)0x0400)

#define

SDIO_DCTRL_RWSTART ((uint16_t)0x0100)

#define

SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)

#define

SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)

#define

SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)

#define

SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)

#define

SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)

#define

SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)

#define

SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)

#define

SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)

#define

SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)

#define

SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)

#define

SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)

#define

SDIO_ICR_DATAENDC ((uint32_t)0x00000100)

#define

SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)

#define

SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)

#define

SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)

#define

SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)

#define

SDIO_ICR_SDIOITC ((uint32_t)0x00400000)

#define

SDIO_ICR_STBITERRC ((uint32_t)0x00000200)

#define

SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)

#define

SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)

#define

SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)

#define

SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)

#define

SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)

#define

SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)

#define

SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)

#define

SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)

#define

SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)

#define

SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)

#define

SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)

#define

SDIO_MASK_RXACTIE ((uint32_t)0x00002000)

#define

SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)

#define

SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)

#define

SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)

#define

SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)

#define

SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)

#define

SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)

#define

SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)

#define

SDIO_MASK_TXACTIE ((uint32_t)0x00001000)

#define

SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)

#define

SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)

#define

SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)

#define

SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)

#define

SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)

#define

SDIO_POWER_PWRCTRL ((uint8_t)0x03)

#define

SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)

#define

SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)

#define

SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)

#define

SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)

#define

SDIO_STA_CEATAEND ((uint32_t)0x00800000)

#define

SDIO_STA_CMDACT ((uint32_t)0x00000800)

#define

SDIO_STA_CMDREND ((uint32_t)0x00000040)

#define

SDIO_STA_CMDSENT ((uint32_t)0x00000080)

#define

SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)

#define

SDIO_STA_DATAEND ((uint32_t)0x00000100)

#define

SDIO_STA_DBCKEND ((uint32_t)0x00000400)

#define

SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)

#define

SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)

#define

SDIO_STA_RXACT ((uint32_t)0x00002000)

#define

SDIO_STA_RXDAVL ((uint32_t)0x00200000)

#define

SDIO_STA_RXFIFOE ((uint32_t)0x00080000)

#define

SDIO_STA_RXFIFOF ((uint32_t)0x00020000)

#define

SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)

#define

SDIO_STA_RXOVERR ((uint32_t)0x00000020)

#define

SDIO_STA_SDIOIT ((uint32_t)0x00400000)

#define

SDIO_STA_STBITERR ((uint32_t)0x00000200)

#define

SDIO_STA_TXACT ((uint32_t)0x00001000)

#define

SDIO_STA_TXDAVL ((uint32_t)0x00100000)

#define

SDIO_STA_TXFIFOE ((uint32_t)0x00040000)

#define

SDIO_STA_TXFIFOF ((uint32_t)0x00010000)

#define

SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)

#define

SDIO_STA_TXUNDERR ((uint32_t)0x00000010)

#define

SPI_CR1_BIDIMODE ((uint16_t)0x8000)

#define

SPI_CR1_BIDIOE ((uint16_t)0x4000)

#define

SPI_CR1_BR ((uint16_t)0x0038)

#define

SPI_CR1_BR_0 ((uint16_t)0x0008)

#define

SPI_CR1_BR_1 ((uint16_t)0x0010)

#define

SPI_CR1_BR_2 ((uint16_t)0x0020)

#define

SPI_CR1_CPHA ((uint16_t)0x0001)

#define

SPI_CR1_CPOL ((uint16_t)0x0002)

#define

SPI_CR1_CRCEN ((uint16_t)0x2000)

#define

SPI_CR1_CRCNEXT ((uint16_t)0x1000)

#define

SPI_CR1_DFF ((uint16_t)0x0800)

#define

SPI_CR1_LSBFIRST ((uint16_t)0x0080)

#define

SPI_CR1_MSTR ((uint16_t)0x0004)

#define

SPI_CR1_RXONLY ((uint16_t)0x0400)

#define

SPI_CR1_SPE ((uint16_t)0x0040)

#define

SPI_CR1_SSI ((uint16_t)0x0100)

#define

SPI_CR1_SSM ((uint16_t)0x0200)

#define

SPI_CR2_ERRIE ((uint8_t)0x20)

#define

SPI_CR2_FRF ((uint8_t)0x08)

#define

SPI_CR2_RXDMAEN ((uint8_t)0x01)

#define

SPI_CR2_RXNEIE ((uint8_t)0x40)

#define

SPI_CR2_SSOE ((uint8_t)0x04)

#define

SPI_CR2_TXDMAEN ((uint8_t)0x02)

#define

SPI_CR2_TXEIE ((uint8_t)0x80)

#define

SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)

#define

SPI_DR_DR ((uint16_t)0xFFFF)

#define

SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)

#define

SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)

#define

SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)

#define

SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)

#define

SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)

#define

SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)

#define

SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)

#define

SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)

#define

SPI_I2SCFGR_I2SE ((uint16_t)0x0400)

#define

SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)

#define

SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)

#define

SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)

#define

SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)

#define

SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)

#define

SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)

#define

SPI_I2SPR_MCKOE ((uint16_t)0x0200)

#define

SPI_I2SPR_ODD ((uint16_t)0x0100)

#define

SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)

#define

SPI_SR_BSY ((uint8_t)0x80)

#define

SPI_SR_CHSIDE ((uint8_t)0x04)

#define

SPI_SR_CRCERR ((uint8_t)0x10)

#define

SPI_SR_MODF ((uint8_t)0x20)

#define

SPI_SR_OVR ((uint8_t)0x40)

#define

SPI_SR_RXNE ((uint8_t)0x01)

#define

SPI_SR_TXE ((uint8_t)0x02)

#define

SPI_SR_UDR ((uint8_t)0x08)

#define

SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)

#define

SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F)

#define

SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000)

EXTI0 configuration.

#define

SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001)

#define

SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002)

#define

SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003)

#define

SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004)

#define

SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006)

#define

SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007)

#define

SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005)

#define

SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0)

#define

SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000)

EXTI1 configuration.

#define

SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010)

#define

SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020)

#define

SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030)

#define

SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040)

#define

SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060)

#define

SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070)

#define

SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050)

#define

SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00)

#define

SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)

EXTI2 configuration.

#define

SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100)

#define

SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200)

#define

SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300)

#define

SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400)

#define

SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600)

#define

SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700)

#define

SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500)

#define

SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000)

#define

SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000)

EXTI3 configuration.

#define

SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000)

#define

SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000)

#define

SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000)

#define

SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000)

#define

SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000)

#define

SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000)

#define

SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F)

#define

SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000)

EXTI4 configuration.

#define

SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001)

#define

SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002)

#define

SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003)

#define

SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004)

#define

SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006)

#define

SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007)

#define

SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0)

#define

SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000)

EXTI5 configuration.

#define

SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010)

#define

SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020)

#define

SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030)

#define

SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040)

#define

SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060)

#define

SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070)

#define

SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00)

#define

SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000)

EXTI6 configuration.

#define

SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100)

#define

SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200)

#define

SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300)

#define

SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400)

#define

SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600)

#define

SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700)

#define

SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000)

#define

SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000)

EXTI7 configuration.

#define

SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000)

#define

SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000)

#define

SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000)

#define

SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000)

#define

SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000)

#define

SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000)

#define

SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00)

#define

SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000)

EXTI10 configuration.

#define

SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100)

#define

SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200)

#define

SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300)

#define

SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400)

#define

SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600)

#define

SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700)

#define

SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000)

#define

SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000)

EXTI11 configuration.

#define

SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000)

#define

SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000)

#define

SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000)

#define

SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000)

#define

SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000)

#define

SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000)

#define

SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F)

#define

SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000)

EXTI8 configuration.

#define

SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001)

#define

SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002)

#define

SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003)

#define

SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004)

#define

SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006)

#define

SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007)

#define

SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0)

#define

SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000)

EXTI9 configuration.

#define

SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010)

#define

SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020)

#define

SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030)

#define

SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040)

#define

SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060)

#define

SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070)

#define

SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F)

#define

SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000)

EXTI12 configuration.

#define

SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001)

#define

SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002)

#define

SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003)

#define

SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004)

#define

SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006)

#define

SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007)

#define

SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0)

#define

SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000)

EXTI13 configuration.

#define

SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010)

#define

SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020)

#define

SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030)

#define

SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040)

#define

SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060)

#define

SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070)

#define

SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00)

#define

SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000)

EXTI14 configuration.

#define

SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100)

#define

SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200)

#define

SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300)

#define

SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400)

#define

SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600)

#define

SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700)

#define

SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)

#define

SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000)

EXTI15 configuration.

#define

SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000)

#define

SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000)

#define

SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000)

#define

SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000)

#define

SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000)

#define

SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000)

#define

SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300)

#define

SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100)

#define

SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200)

#define

SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003)

#define

SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)

#define

SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)

#define

SYSCFG_PMC_USB_PU ((uint32_t)0x00000001)

#define

SysTick_CALIB_NOREF ((uint32_t)0x80000000)

#define

SysTick_CALIB_SKEW ((uint32_t)0x40000000)

#define

SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)

#define

SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)

#define

SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)

#define

SysTick_CTRL_ENABLE ((uint32_t)0x00000001)

#define

SysTick_CTRL_TICKINT ((uint32_t)0x00000002)

#define

SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)

#define

SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)

#define

TIM_ARR_ARR ((uint16_t)0xFFFF)

#define

TIM_CCER_CC1E ((uint16_t)0x0001)

#define

TIM_CCER_CC1NP ((uint16_t)0x0008)

#define

TIM_CCER_CC1P ((uint16_t)0x0002)

#define

TIM_CCER_CC2E ((uint16_t)0x0010)

#define

TIM_CCER_CC2NP ((uint16_t)0x0080)

#define

TIM_CCER_CC2P ((uint16_t)0x0020)

#define

TIM_CCER_CC3E ((uint16_t)0x0100)

#define

TIM_CCER_CC3NP ((uint16_t)0x0800)

#define

TIM_CCER_CC3P ((uint16_t)0x0200)

#define

TIM_CCER_CC4E ((uint16_t)0x1000)

#define

TIM_CCER_CC4NP ((uint16_t)0x8000)

#define

TIM_CCER_CC4P ((uint16_t)0x2000)

#define

TIM_CCMR1_CC1S ((uint16_t)0x0003)

#define

TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)

#define

TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)

#define

TIM_CCMR1_CC2S ((uint16_t)0x0300)

#define

TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)

#define

TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)

#define

TIM_CCMR1_IC1F ((uint16_t)0x00F0)

#define

TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)

#define

TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)

#define

TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)

#define

TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)

#define

TIM_CCMR1_IC1PSC ((uint16_t)0x000C)

#define

TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)

#define

TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)

#define

TIM_CCMR1_IC2F ((uint16_t)0xF000)

#define

TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)

#define

TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)

#define

TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)

#define

TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)

#define

TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)

#define

TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)

#define

TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)

#define

TIM_CCMR1_OC1CE ((uint16_t)0x0080)

#define

TIM_CCMR1_OC1FE ((uint16_t)0x0004)

#define

TIM_CCMR1_OC1M ((uint16_t)0x0070)

#define

TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)

#define

TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)

#define

TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)

#define

TIM_CCMR1_OC1PE ((uint16_t)0x0008)

#define

TIM_CCMR1_OC2CE ((uint16_t)0x8000)

#define

TIM_CCMR1_OC2FE ((uint16_t)0x0400)

#define

TIM_CCMR1_OC2M ((uint16_t)0x7000)

#define

TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)

#define

TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)

#define

TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)

#define

TIM_CCMR1_OC2PE ((uint16_t)0x0800)

#define

TIM_CCMR2_CC3S ((uint16_t)0x0003)

#define

TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)

#define

TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)

#define

TIM_CCMR2_CC4S ((uint16_t)0x0300)

#define

TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)

#define

TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)

#define

TIM_CCMR2_IC3F ((uint16_t)0x00F0)

#define

TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)

#define

TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)

#define

TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)

#define

TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)

#define

TIM_CCMR2_IC3PSC ((uint16_t)0x000C)

#define

TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)

#define

TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)

#define

TIM_CCMR2_IC4F ((uint16_t)0xF000)

#define

TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)

#define

TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)

#define

TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)

#define

TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)

#define

TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)

#define

TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)

#define

TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)

#define

TIM_CCMR2_OC3CE ((uint16_t)0x0080)

#define

TIM_CCMR2_OC3FE ((uint16_t)0x0004)

#define

TIM_CCMR2_OC3M ((uint16_t)0x0070)

#define

TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)

#define

TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)

#define

TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)

#define

TIM_CCMR2_OC3PE ((uint16_t)0x0008)

#define

TIM_CCMR2_OC4CE ((uint16_t)0x8000)

#define

TIM_CCMR2_OC4FE ((uint16_t)0x0400)

#define

TIM_CCMR2_OC4M ((uint16_t)0x7000)

#define

TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)

#define

TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)

#define

TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)

#define

TIM_CCMR2_OC4PE ((uint16_t)0x0800)

#define

TIM_CCR1_CCR1 ((uint16_t)0xFFFF)

#define

TIM_CCR2_CCR2 ((uint16_t)0xFFFF)

#define

TIM_CCR3_CCR3 ((uint16_t)0xFFFF)

#define

TIM_CCR4_CCR4 ((uint16_t)0xFFFF)

#define

TIM_CNT_CNT ((uint16_t)0xFFFF)

#define

TIM_CR1_ARPE ((uint16_t)0x0080)

#define

TIM_CR1_CEN ((uint16_t)0x0001)

#define

TIM_CR1_CKD ((uint16_t)0x0300)

#define

TIM_CR1_CKD_0 ((uint16_t)0x0100)

#define

TIM_CR1_CKD_1 ((uint16_t)0x0200)

#define

TIM_CR1_CMS ((uint16_t)0x0060)

#define

TIM_CR1_CMS_0 ((uint16_t)0x0020)

#define

TIM_CR1_CMS_1 ((uint16_t)0x0040)

#define

TIM_CR1_DIR ((uint16_t)0x0010)

#define

TIM_CR1_OPM ((uint16_t)0x0008)

#define

TIM_CR1_UDIS ((uint16_t)0x0002)

#define

TIM_CR1_URS ((uint16_t)0x0004)

#define

TIM_CR2_CCDS ((uint16_t)0x0008)

#define

TIM_CR2_MMS ((uint16_t)0x0070)

#define

TIM_CR2_MMS_0 ((uint16_t)0x0010)

#define

TIM_CR2_MMS_1 ((uint16_t)0x0020)

#define

TIM_CR2_MMS_2 ((uint16_t)0x0040)

#define

TIM_CR2_TI1S ((uint16_t)0x0080)

#define

TIM_DCR_DBA ((uint16_t)0x001F)

#define

TIM_DCR_DBA_0 ((uint16_t)0x0001)

#define

TIM_DCR_DBA_1 ((uint16_t)0x0002)

#define

TIM_DCR_DBA_2 ((uint16_t)0x0004)

#define

TIM_DCR_DBA_3 ((uint16_t)0x0008)

#define

TIM_DCR_DBA_4 ((uint16_t)0x0010)

#define

TIM_DCR_DBL ((uint16_t)0x1F00)

#define

TIM_DCR_DBL_0 ((uint16_t)0x0100)

#define

TIM_DCR_DBL_1 ((uint16_t)0x0200)

#define

TIM_DCR_DBL_2 ((uint16_t)0x0400)

#define

TIM_DCR_DBL_3 ((uint16_t)0x0800)

#define

TIM_DCR_DBL_4 ((uint16_t)0x1000)

#define

TIM_DIER_CC1DE ((uint16_t)0x0200)

#define

TIM_DIER_CC1IE ((uint16_t)0x0002)

#define

TIM_DIER_CC2DE ((uint16_t)0x0400)

#define

TIM_DIER_CC2IE ((uint16_t)0x0004)

#define

TIM_DIER_CC3DE ((uint16_t)0x0800)

#define

TIM_DIER_CC3IE ((uint16_t)0x0008)

#define

TIM_DIER_CC4DE ((uint16_t)0x1000)

#define

TIM_DIER_CC4IE ((uint16_t)0x0010)

#define

TIM_DIER_TDE ((uint16_t)0x4000)

#define

TIM_DIER_TIE ((uint16_t)0x0040)

#define

TIM_DIER_UDE ((uint16_t)0x0100)

#define

TIM_DIER_UIE ((uint16_t)0x0001)

#define

TIM_DMAR_DMAB ((uint16_t)0xFFFF)

#define

TIM_EGR_CC1G ((uint8_t)0x02)

#define

TIM_EGR_CC2G ((uint8_t)0x04)

#define

TIM_EGR_CC3G ((uint8_t)0x08)

#define

TIM_EGR_CC4G ((uint8_t)0x10)

#define

TIM_EGR_TG ((uint8_t)0x40)

#define

TIM_EGR_UG ((uint8_t)0x01)

#define

TIM_OR_TI1RMP ((uint16_t)0x0003)

#define

TIM_OR_TI1RMP_0 ((uint16_t)0x0001)

#define

TIM_OR_TI1RMP_1 ((uint16_t)0x0002)

#define

TIM_PSC_PSC ((uint16_t)0xFFFF)

#define

TIM_SMCR_ECE ((uint16_t)0x4000)

#define

TIM_SMCR_ETF ((uint16_t)0x0F00)

#define

TIM_SMCR_ETF_0 ((uint16_t)0x0100)

#define

TIM_SMCR_ETF_1 ((uint16_t)0x0200)

#define

TIM_SMCR_ETF_2 ((uint16_t)0x0400)

#define

TIM_SMCR_ETF_3 ((uint16_t)0x0800)

#define

TIM_SMCR_ETP ((uint16_t)0x8000)

#define

TIM_SMCR_ETPS ((uint16_t)0x3000)

#define

TIM_SMCR_ETPS_0 ((uint16_t)0x1000)

#define

TIM_SMCR_ETPS_1 ((uint16_t)0x2000)

#define

TIM_SMCR_MSM ((uint16_t)0x0080)

#define

TIM_SMCR_OCCS ((uint16_t)0x0008)

#define

TIM_SMCR_SMS ((uint16_t)0x0007)

#define

TIM_SMCR_SMS_0 ((uint16_t)0x0001)

#define

TIM_SMCR_SMS_1 ((uint16_t)0x0002)

#define

TIM_SMCR_SMS_2 ((uint16_t)0x0004)

#define

TIM_SMCR_TS ((uint16_t)0x0070)

#define

TIM_SMCR_TS_0 ((uint16_t)0x0010)

#define

TIM_SMCR_TS_1 ((uint16_t)0x0020)

#define

TIM_SMCR_TS_2 ((uint16_t)0x0040)

#define

TIM_SR_CC1IF ((uint16_t)0x0002)

#define

TIM_SR_CC1OF ((uint16_t)0x0200)

#define

TIM_SR_CC2IF ((uint16_t)0x0004)

#define

TIM_SR_CC2OF ((uint16_t)0x0400)

#define

TIM_SR_CC3IF ((uint16_t)0x0008)

#define

TIM_SR_CC3OF ((uint16_t)0x0800)

#define

TIM_SR_CC4IF ((uint16_t)0x0010)

#define

TIM_SR_CC4OF ((uint16_t)0x1000)

#define

TIM_SR_TIF ((uint16_t)0x0040)

#define

TIM_SR_UIF ((uint16_t)0x0001)

#define

USART_BRR_DIV_FRACTION ((uint16_t)0x000F)

#define

USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0)

#define

USART_CR1_IDLEIE ((uint16_t)0x0010)

#define

USART_CR1_M ((uint16_t)0x1000)

#define

USART_CR1_OVER8 ((uint16_t)0x8000)

#define

USART_CR1_PCE ((uint16_t)0x0400)

#define

USART_CR1_PEIE ((uint16_t)0x0100)

#define

USART_CR1_PS ((uint16_t)0x0200)

#define

USART_CR1_RE ((uint16_t)0x0004)

#define

USART_CR1_RWU ((uint16_t)0x0002)

#define

USART_CR1_RXNEIE ((uint16_t)0x0020)

#define

USART_CR1_SBK ((uint16_t)0x0001)

#define

USART_CR1_TCIE ((uint16_t)0x0040)

#define

USART_CR1_TE ((uint16_t)0x0008)

#define

USART_CR1_TXEIE ((uint16_t)0x0080)

#define

USART_CR1_UE ((uint16_t)0x2000)

#define

USART_CR1_WAKE ((uint16_t)0x0800)

#define

USART_CR2_ADD ((uint16_t)0x000F)

#define

USART_CR2_CLKEN ((uint16_t)0x0800)

#define

USART_CR2_CPHA ((uint16_t)0x0200)

#define

USART_CR2_CPOL ((uint16_t)0x0400)

#define

USART_CR2_LBCL ((uint16_t)0x0100)

#define

USART_CR2_LBDIE ((uint16_t)0x0040)

#define

USART_CR2_LBDL ((uint16_t)0x0020)

#define

USART_CR2_LINEN ((uint16_t)0x4000)

#define

USART_CR2_STOP ((uint16_t)0x3000)

#define

USART_CR2_STOP_0 ((uint16_t)0x1000)

#define

USART_CR2_STOP_1 ((uint16_t)0x2000)

#define

USART_CR3_CTSE ((uint16_t)0x0200)

#define

USART_CR3_CTSIE ((uint16_t)0x0400)

#define

USART_CR3_DMAR ((uint16_t)0x0040)

#define

USART_CR3_DMAT ((uint16_t)0x0080)

#define

USART_CR3_EIE ((uint16_t)0x0001)

#define

USART_CR3_HDSEL ((uint16_t)0x0008)

#define

USART_CR3_IREN ((uint16_t)0x0002)

#define

USART_CR3_IRLP ((uint16_t)0x0004)

#define

USART_CR3_NACK ((uint16_t)0x0010)

#define

USART_CR3_ONEBIT ((uint16_t)0x0800)

#define

USART_CR3_RTSE ((uint16_t)0x0100)

#define

USART_CR3_SCEN ((uint16_t)0x0020)

#define

USART_DR_DR ((uint16_t)0x01FF)

#define

USART_GTPR_GT ((uint16_t)0xFF00)

#define

USART_GTPR_PSC ((uint16_t)0x00FF)

#define

USART_GTPR_PSC_0 ((uint16_t)0x0001)

#define

USART_GTPR_PSC_1 ((uint16_t)0x0002)

#define

USART_GTPR_PSC_2 ((uint16_t)0x0004)

#define

USART_GTPR_PSC_3 ((uint16_t)0x0008)

#define

USART_GTPR_PSC_4 ((uint16_t)0x0010)

#define

USART_GTPR_PSC_5 ((uint16_t)0x0020)

#define

USART_GTPR_PSC_6 ((uint16_t)0x0040)

#define

USART_GTPR_PSC_7 ((uint16_t)0x0080)

#define

USART_SR_CTS ((uint16_t)0x0200)

#define

USART_SR_FE ((uint16_t)0x0002)

#define

USART_SR_IDLE ((uint16_t)0x0010)

#define

USART_SR_LBD ((uint16_t)0x0100)

#define

USART_SR_NE ((uint16_t)0x0004)

#define

USART_SR_ORE ((uint16_t)0x0008)

#define

USART_SR_PE ((uint16_t)0x0001)

#define

USART_SR_RXNE ((uint16_t)0x0020)

#define

USART_SR_TC ((uint16_t)0x0040)

#define

USART_SR_TXE ((uint16_t)0x0080)

#define

USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)

#define

USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)

#define

USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)

#define

USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)

#define

USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)

#define

USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)

#define

USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)

#define

USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)

#define

USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)

#define

USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)

#define

USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)

#define

USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)

#define

USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)

#define

USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)

#define

USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)

#define

USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)

#define

USB_BTABLE_BTABLE ((uint16_t)0xFFF8)

#define

USB_CNTR_CTRM ((uint16_t)0x8000)

#define

USB_CNTR_ERRM ((uint16_t)0x2000)

#define

USB_CNTR_ESOFM ((uint16_t)0x0100)

#define

USB_CNTR_FRES ((uint16_t)0x0001)

#define

USB_CNTR_FSUSP ((uint16_t)0x0008)

#define

USB_CNTR_LP_MODE ((uint16_t)0x0004)

#define

USB_CNTR_PDWN ((uint16_t)0x0002)

#define

USB_CNTR_PMAOVRM ((uint16_t)0x4000)

#define

USB_CNTR_RESETM ((uint16_t)0x0400)

#define

USB_CNTR_RESUME ((uint16_t)0x0010)

#define

USB_CNTR_SOFM ((uint16_t)0x0200)

#define

USB_CNTR_SUSPM ((uint16_t)0x0800)

#define

USB_CNTR_WKUPM ((uint16_t)0x1000)

#define

USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)

#define

USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)

#define

USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)

#define

USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)

#define

USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)

#define

USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)

#define

USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)

#define

USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)

#define

USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)

#define

USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)

#define

USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)

#define

USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)

#define

USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)

#define

USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)

#define

USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)

#define

USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)

#define

USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)

#define

USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)

#define

USB_DADDR_ADD ((uint8_t)0x7F)

#define

USB_DADDR_ADD0 ((uint8_t)0x01)

#define

USB_DADDR_ADD1 ((uint8_t)0x02)

#define

USB_DADDR_ADD2 ((uint8_t)0x04)

#define

USB_DADDR_ADD3 ((uint8_t)0x08)

#define

USB_DADDR_ADD4 ((uint8_t)0x10)

#define

USB_DADDR_ADD5 ((uint8_t)0x20)

#define

USB_DADDR_ADD6 ((uint8_t)0x40)

#define

USB_DADDR_EF ((uint8_t)0x80)

#define

USB_EP0R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP0R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP0R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP0R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP0R_EA ((uint16_t)0x000F)

#define

USB_EP0R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP0R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP0R_SETUP ((uint16_t)0x0800)

#define

USB_EP0R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP0R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP1R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP1R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP1R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP1R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP1R_EA ((uint16_t)0x000F)

#define

USB_EP1R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP1R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP1R_SETUP ((uint16_t)0x0800)

#define

USB_EP1R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP1R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP2R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP2R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP2R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP2R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP2R_EA ((uint16_t)0x000F)

#define

USB_EP2R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP2R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP2R_SETUP ((uint16_t)0x0800)

#define

USB_EP2R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP2R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP3R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP3R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP3R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP3R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP3R_EA ((uint16_t)0x000F)

#define

USB_EP3R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP3R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP3R_SETUP ((uint16_t)0x0800)

#define

USB_EP3R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP3R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP4R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP4R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP4R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP4R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP4R_EA ((uint16_t)0x000F)

#define

USB_EP4R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP4R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP4R_SETUP ((uint16_t)0x0800)

#define

USB_EP4R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP4R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP5R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP5R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP5R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP5R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP5R_EA ((uint16_t)0x000F)

#define

USB_EP5R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP5R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP5R_SETUP ((uint16_t)0x0800)

#define

USB_EP5R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP5R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP6R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP6R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP6R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP6R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP6R_EA ((uint16_t)0x000F)

#define

USB_EP6R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP6R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP6R_SETUP ((uint16_t)0x0800)

#define

USB_EP6R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP6R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP7R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP7R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP7R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP7R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP7R_EA ((uint16_t)0x000F)

#define

USB_EP7R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP7R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP7R_SETUP ((uint16_t)0x0800)

#define

USB_EP7R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP7R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_FNR_FN ((uint16_t)0x07FF)

#define

USB_FNR_LCK ((uint16_t)0x2000)

#define

USB_FNR_LSOF ((uint16_t)0x1800)

#define

USB_FNR_RXDM ((uint16_t)0x4000)

#define

USB_FNR_RXDP ((uint16_t)0x8000)

#define

USB_ISTR_CTR ((uint16_t)0x8000)

#define

USB_ISTR_DIR ((uint16_t)0x0010)

#define

USB_ISTR_EP_ID ((uint16_t)0x000F)

#define

USB_ISTR_ERR ((uint16_t)0x2000)

#define

USB_ISTR_ESOF ((uint16_t)0x0100)

#define

USB_ISTR_PMAOVR ((uint16_t)0x4000)

#define

USB_ISTR_RESET ((uint16_t)0x0400)

#define

USB_ISTR_SOF ((uint16_t)0x0200)

#define

USB_ISTR_SUSP ((uint16_t)0x0800)

#define

USB_ISTR_WKUP ((uint16_t)0x1000)

#define

WWDG_CFR_EWI ((uint16_t)0x0200)

#define

WWDG_CFR_W ((uint16_t)0x007F)

#define

WWDG_CFR_W0 ((uint16_t)0x0001)

#define

WWDG_CFR_W1 ((uint16_t)0x0002)

#define

WWDG_CFR_W2 ((uint16_t)0x0004)

#define

WWDG_CFR_W3 ((uint16_t)0x0008)

#define

WWDG_CFR_W4 ((uint16_t)0x0010)

#define

WWDG_CFR_W5 ((uint16_t)0x0020)

#define

WWDG_CFR_W6 ((uint16_t)0x0040)

#define

WWDG_CFR_WDGTB ((uint16_t)0x0180)

#define

WWDG_CFR_WDGTB0 ((uint16_t)0x0080)

#define

WWDG_CFR_WDGTB1 ((uint16_t)0x0100)

#define

WWDG_CR_T ((uint8_t)0x7F)

#define

WWDG_CR_T0 ((uint8_t)0x01)

#define

WWDG_CR_T1 ((uint8_t)0x02)

#define

WWDG_CR_T2 ((uint8_t)0x04)

#define

WWDG_CR_T3 ((uint8_t)0x08)

#define

WWDG_CR_T4 ((uint8_t)0x10)

#define

WWDG_CR_T5 ((uint8_t)0x20)

#define

WWDG_CR_T6 ((uint8_t)0x40)

#define

WWDG_CR_WDGA ((uint8_t)0x80)

#define

WWDG_SR_EWIF ((uint8_t)0x01)

Define Documentation

#define ADC_CCR_ADCPRE ((uint32_t)0x00030000)

ADC prescaler

Definition at line 1589 of file stm32l1xx.h.

#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 1590 of file stm32l1xx.h.

#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 1591 of file stm32l1xx.h.

#define ADC_CCR_TSVREFE ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

Definition at line 1592 of file stm32l1xx.h.

Referenced by ADC_TempSensorVrefintCmd().

#define ADC_CR1_AWDCH ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

Definition at line 1069 of file stm32l1xx.h.

#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1070 of file stm32l1xx.h.

#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1071 of file stm32l1xx.h.

#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1072 of file stm32l1xx.h.

#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1073 of file stm32l1xx.h.

#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1074 of file stm32l1xx.h.

#define ADC_CR1_AWDEN ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

Definition at line 1094 of file stm32l1xx.h.

#define ADC_CR1_AWDIE ((uint32_t)0x00000040)

Analog Watchdog interrupt enable

Definition at line 1077 of file stm32l1xx.h.

#define ADC_CR1_AWDSGL ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

Definition at line 1080 of file stm32l1xx.h.

#define ADC_CR1_DISCEN ((uint32_t)0x00000800)

Discontinuous mode on regular channels

Definition at line 1082 of file stm32l1xx.h.

Referenced by ADC_DiscModeCmd().

#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

Definition at line 1085 of file stm32l1xx.h.

#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 1086 of file stm32l1xx.h.

#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 1087 of file stm32l1xx.h.

#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 1088 of file stm32l1xx.h.

#define ADC_CR1_EOCIE ((uint32_t)0x00000020)

Interrupt enable for EOC

Definition at line 1076 of file stm32l1xx.h.

#define ADC_CR1_JAUTO ((uint32_t)0x00000400)

Automatic injected group conversion

Definition at line 1081 of file stm32l1xx.h.

Referenced by ADC_AutoInjectedConvCmd().

#define ADC_CR1_JAWDEN ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

Definition at line 1093 of file stm32l1xx.h.

#define ADC_CR1_JDISCEN ((uint32_t)0x00001000)

Discontinuous mode on injected channels

Definition at line 1083 of file stm32l1xx.h.

Referenced by ADC_InjectedDiscModeCmd().

#define ADC_CR1_JEOCIE ((uint32_t)0x00000080)

Interrupt enable for injected channels

Definition at line 1078 of file stm32l1xx.h.

#define ADC_CR1_OVRIE ((uint32_t)0x04000000)

Overrun interrupt enable

Definition at line 1100 of file stm32l1xx.h.

#define ADC_CR1_PDD ((uint32_t)0x00010000)

Power Down during Delay phase

Definition at line 1090 of file stm32l1xx.h.

#define ADC_CR1_PDI ((uint32_t)0x00020000)

Power Down during Idle phase

Definition at line 1091 of file stm32l1xx.h.

#define ADC_CR1_RES ((uint32_t)0x03000000)

RES[1:0] bits (Resolution)

Definition at line 1096 of file stm32l1xx.h.

#define ADC_CR1_RES_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1097 of file stm32l1xx.h.

#define ADC_CR1_RES_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1098 of file stm32l1xx.h.

#define ADC_CR1_SCAN ((uint32_t)0x00000100)

Scan mode

Definition at line 1079 of file stm32l1xx.h.

#define ADC_CR2_ADON ((uint32_t)0x00000001)

A/D Converter ON / OFF

Definition at line 1103 of file stm32l1xx.h.

Referenced by ADC_Cmd().

#define ADC_CR2_ALIGN ((uint32_t)0x00000800)

Data Alignment

Definition at line 1115 of file stm32l1xx.h.

#define ADC_CR2_CFG ((uint32_t)0x00000004)

ADC Configuration

Definition at line 1105 of file stm32l1xx.h.

Referenced by ADC_BankSelection().

#define ADC_CR2_CONT ((uint32_t)0x00000002)

Continuous Conversion

Definition at line 1104 of file stm32l1xx.h.

Referenced by ADC_ContinuousModeCmd().

#define ADC_CR2_DDS ((uint32_t)0x00000200)

DMA disable selection (Single ADC)

Definition at line 1113 of file stm32l1xx.h.

Referenced by ADC_DMARequestAfterLastTransferCmd().

#define ADC_CR2_DELS ((uint32_t)0x00000070)

DELS[2:0] bits (Delay selection)

Definition at line 1107 of file stm32l1xx.h.

#define ADC_CR2_DELS_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 1108 of file stm32l1xx.h.

#define ADC_CR2_DELS_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 1109 of file stm32l1xx.h.

#define ADC_CR2_DELS_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 1110 of file stm32l1xx.h.

#define ADC_CR2_DMA ((uint32_t)0x00000100)

Direct Memory access mode

Definition at line 1112 of file stm32l1xx.h.

Referenced by ADC_DMACmd().

#define ADC_CR2_EOCS ((uint32_t)0x00000400)

End of conversion selection

Definition at line 1114 of file stm32l1xx.h.

Referenced by ADC_EOCOnEachRegularChannelCmd().

#define ADC_CR2_EXTEN ((uint32_t)0x30000000)

EXTEN[1:0] bits (External Trigger Conversion mode for regular channels)

Definition at line 1135 of file stm32l1xx.h.

#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 1136 of file stm32l1xx.h.

#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 1137 of file stm32l1xx.h.

#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000)

EXTSEL[3:0] bits (External Event Select for regular group)

Definition at line 1129 of file stm32l1xx.h.

#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1130 of file stm32l1xx.h.

#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1131 of file stm32l1xx.h.

#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1132 of file stm32l1xx.h.

#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 1133 of file stm32l1xx.h.

#define ADC_CR2_JEXTEN ((uint32_t)0x00300000)

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels)

Definition at line 1123 of file stm32l1xx.h.

#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1124 of file stm32l1xx.h.

#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1125 of file stm32l1xx.h.

#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)

JEXTSEL[3:0] bits (External event select for injected group)

Definition at line 1117 of file stm32l1xx.h.

#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 1118 of file stm32l1xx.h.

#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 1119 of file stm32l1xx.h.

#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 1120 of file stm32l1xx.h.

#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 1121 of file stm32l1xx.h.

#define ADC_CR2_JSWSTART ((uint32_t)0x00400000)

Start Conversion of injected channels

Definition at line 1127 of file stm32l1xx.h.

Referenced by ADC_GetSoftwareStartInjectedConvCmdStatus(), and ADC_SoftwareStartInjectedConv().

#define ADC_CR2_SWSTART ((uint32_t)0x40000000)

Start Conversion of regular channels

Definition at line 1139 of file stm32l1xx.h.

Referenced by ADC_GetSoftwareStartConvStatus(), and ADC_SoftwareStartConv().

#define ADC_CSR_ADONS1 ((uint32_t)0x00000040)

ADON status of ADC1

Definition at line 1586 of file stm32l1xx.h.

#define ADC_CSR_AWD1 ((uint32_t)0x00000001)

ADC1 Analog watchdog flag

Definition at line 1580 of file stm32l1xx.h.

#define ADC_CSR_EOC1 ((uint32_t)0x00000002)

ADC1 End of conversion

Definition at line 1581 of file stm32l1xx.h.

#define ADC_CSR_JEOC1 ((uint32_t)0x00000004)

ADC1 Injected channel end of conversion

Definition at line 1582 of file stm32l1xx.h.

#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008)

ADC1 Injected channel Start flag

Definition at line 1583 of file stm32l1xx.h.

#define ADC_CSR_OVR1 ((uint32_t)0x00000020)

ADC1 overrun flag

Definition at line 1585 of file stm32l1xx.h.

#define ADC_CSR_STRT1 ((uint32_t)0x00000010)

ADC1 Regular channel Start flag

Definition at line 1584 of file stm32l1xx.h.

#define ADC_DR_DATA ((uint32_t)0x0000FFFF)

Regular data

Definition at line 1566 of file stm32l1xx.h.

#define ADC_HTR_HT ((uint32_t)0x00000FFF)

Analog watchdog high threshold

Definition at line 1307 of file stm32l1xx.h.

#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF)

Injected data

Definition at line 1554 of file stm32l1xx.h.

#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF)

Injected data

Definition at line 1557 of file stm32l1xx.h.

#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF)

Injected data

Definition at line 1560 of file stm32l1xx.h.

#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF)

Injected data

Definition at line 1563 of file stm32l1xx.h.

#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF)

Data offset for injected channel 1

Definition at line 1295 of file stm32l1xx.h.

#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF)

Data offset for injected channel 2

Definition at line 1298 of file stm32l1xx.h.

#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF)

Data offset for injected channel 3

Definition at line 1301 of file stm32l1xx.h.

#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF)

Data offset for injected channel 4

Definition at line 1304 of file stm32l1xx.h.

#define ADC_JSQR_JL ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

Definition at line 1549 of file stm32l1xx.h.

#define ADC_JSQR_JL_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1550 of file stm32l1xx.h.

#define ADC_JSQR_JL_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1551 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

Definition at line 1521 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1522 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1523 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1524 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1525 of file stm32l1xx.h.

#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1526 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

Definition at line 1528 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1529 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1530 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1531 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1532 of file stm32l1xx.h.

#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1533 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

Definition at line 1535 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1536 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1537 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1538 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1539 of file stm32l1xx.h.

#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1540 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

Definition at line 1542 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1543 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1544 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1545 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1546 of file stm32l1xx.h.

#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1547 of file stm32l1xx.h.

#define ADC_LTR_LT ((uint32_t)0x00000FFF)

Analog watchdog low threshold

Definition at line 1310 of file stm32l1xx.h.

#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007)

SMP20[2:0] bits (Channel 20 Sample time selection)

Definition at line 1142 of file stm32l1xx.h.

#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1143 of file stm32l1xx.h.

#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1144 of file stm32l1xx.h.

#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1145 of file stm32l1xx.h.

#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038)

SMP21[2:0] bits (Channel 21 Sample time selection)

Definition at line 1147 of file stm32l1xx.h.

#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1148 of file stm32l1xx.h.

#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1149 of file stm32l1xx.h.

#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 1150 of file stm32l1xx.h.

#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0)

SMP22[2:0] bits (Channel 22 Sample time selection)

Definition at line 1152 of file stm32l1xx.h.

#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 1153 of file stm32l1xx.h.

#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 1154 of file stm32l1xx.h.

#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100)

Bit 2

Definition at line 1155 of file stm32l1xx.h.

#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00)

SMP23[2:0] bits (Channel 23 Sample time selection)

Definition at line 1157 of file stm32l1xx.h.

#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 1158 of file stm32l1xx.h.

#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 1159 of file stm32l1xx.h.

#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 1160 of file stm32l1xx.h.

#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000)

SMP24[2:0] bits (Channel 24 Sample time selection)

Definition at line 1162 of file stm32l1xx.h.

#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 1163 of file stm32l1xx.h.

#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 1164 of file stm32l1xx.h.

#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 1165 of file stm32l1xx.h.

#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000)

SMP25[2:0] bits (Channel 25 Sample time selection)

Definition at line 1167 of file stm32l1xx.h.

#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1168 of file stm32l1xx.h.

#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1169 of file stm32l1xx.h.

#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1170 of file stm32l1xx.h.

#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000)

SMP26[2:0] bits (Channel 26 Sample time selection)

Definition at line 1172 of file stm32l1xx.h.

#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 1173 of file stm32l1xx.h.

#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 1174 of file stm32l1xx.h.

#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 1175 of file stm32l1xx.h.

#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000)

SMP27[2:0] bits (Channel 27 Sample time selection)

Definition at line 1177 of file stm32l1xx.h.

#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 1178 of file stm32l1xx.h.

#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 1179 of file stm32l1xx.h.

#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 1180 of file stm32l1xx.h.

#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000)

SMP28[2:0] bits (Channel 28 Sample time selection)

Definition at line 1182 of file stm32l1xx.h.

#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1183 of file stm32l1xx.h.

#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1184 of file stm32l1xx.h.

#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1185 of file stm32l1xx.h.

#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000)

SMP29[2:0] bits (Channel 29 Sample time selection)

Definition at line 1187 of file stm32l1xx.h.

#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000)

Bit 0

Definition at line 1188 of file stm32l1xx.h.

#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000)

Bit 1

Definition at line 1189 of file stm32l1xx.h.

#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000)

Bit 2

Definition at line 1190 of file stm32l1xx.h.

#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

Definition at line 1193 of file stm32l1xx.h.

#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1194 of file stm32l1xx.h.

#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1195 of file stm32l1xx.h.

#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1196 of file stm32l1xx.h.

#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

Definition at line 1198 of file stm32l1xx.h.

#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1199 of file stm32l1xx.h.

#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1200 of file stm32l1xx.h.

#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 1201 of file stm32l1xx.h.

#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

Definition at line 1203 of file stm32l1xx.h.

#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 1204 of file stm32l1xx.h.

#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 1205 of file stm32l1xx.h.

#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100)

Bit 2

Definition at line 1206 of file stm32l1xx.h.

#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

Definition at line 1208 of file stm32l1xx.h.

#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 1209 of file stm32l1xx.h.

#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 1210 of file stm32l1xx.h.

#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 1211 of file stm32l1xx.h.

#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

Definition at line 1213 of file stm32l1xx.h.

#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 1214 of file stm32l1xx.h.

#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 1215 of file stm32l1xx.h.

#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 1216 of file stm32l1xx.h.

#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 5 Sample time selection)

Definition at line 1218 of file stm32l1xx.h.

#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1219 of file stm32l1xx.h.

#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1220 of file stm32l1xx.h.

#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1221 of file stm32l1xx.h.

#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

Definition at line 1223 of file stm32l1xx.h.

#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 1224 of file stm32l1xx.h.

#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 1225 of file stm32l1xx.h.

#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 1226 of file stm32l1xx.h.

#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

Definition at line 1228 of file stm32l1xx.h.

#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 1229 of file stm32l1xx.h.

#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 1230 of file stm32l1xx.h.

#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 1231 of file stm32l1xx.h.

#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000)

SMP18[2:0] bits (Channel 18 Sample time selection)

Definition at line 1233 of file stm32l1xx.h.

#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1234 of file stm32l1xx.h.

#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1235 of file stm32l1xx.h.

#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1236 of file stm32l1xx.h.

#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000)

SMP19[2:0] bits (Channel 19 Sample time selection)

Definition at line 1238 of file stm32l1xx.h.

#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000)

Bit 0

Definition at line 1239 of file stm32l1xx.h.

#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000)

Bit 1

Definition at line 1240 of file stm32l1xx.h.

#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000)

Bit 2

Definition at line 1241 of file stm32l1xx.h.

#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

Definition at line 1244 of file stm32l1xx.h.

#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1245 of file stm32l1xx.h.

#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1246 of file stm32l1xx.h.

#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1247 of file stm32l1xx.h.

#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

Definition at line 1249 of file stm32l1xx.h.

#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1250 of file stm32l1xx.h.

#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1251 of file stm32l1xx.h.

#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 1252 of file stm32l1xx.h.

#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

Definition at line 1254 of file stm32l1xx.h.

#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 1255 of file stm32l1xx.h.

#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 1256 of file stm32l1xx.h.

#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100)

Bit 2

Definition at line 1257 of file stm32l1xx.h.

#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

Definition at line 1259 of file stm32l1xx.h.

#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007)

SMP30[2:0] bits (Channel 30 Sample time selection)

Definition at line 1569 of file stm32l1xx.h.

#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1570 of file stm32l1xx.h.

#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1571 of file stm32l1xx.h.

#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1572 of file stm32l1xx.h.

#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038)

SMP31[2:0] bits (Channel 31 Sample time selection)

Definition at line 1574 of file stm32l1xx.h.

#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1575 of file stm32l1xx.h.

#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1576 of file stm32l1xx.h.

#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 1577 of file stm32l1xx.h.

#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 1260 of file stm32l1xx.h.

#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 1261 of file stm32l1xx.h.

#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 1262 of file stm32l1xx.h.

#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

Definition at line 1264 of file stm32l1xx.h.

#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 1265 of file stm32l1xx.h.

#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 1266 of file stm32l1xx.h.

#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 1267 of file stm32l1xx.h.

#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

Definition at line 1269 of file stm32l1xx.h.

#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1270 of file stm32l1xx.h.

#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1271 of file stm32l1xx.h.

#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1272 of file stm32l1xx.h.

#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

Definition at line 1274 of file stm32l1xx.h.

#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 1275 of file stm32l1xx.h.

#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 1276 of file stm32l1xx.h.

#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 1277 of file stm32l1xx.h.

#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

Definition at line 1279 of file stm32l1xx.h.

#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 1280 of file stm32l1xx.h.

#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 1281 of file stm32l1xx.h.

#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 1282 of file stm32l1xx.h.

#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

Definition at line 1284 of file stm32l1xx.h.

#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1285 of file stm32l1xx.h.

#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1286 of file stm32l1xx.h.

#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1287 of file stm32l1xx.h.

#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

Definition at line 1289 of file stm32l1xx.h.

#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000)

Bit 0

Definition at line 1290 of file stm32l1xx.h.

#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000)

Bit 1

Definition at line 1291 of file stm32l1xx.h.

#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000)

Bit 2

Definition at line 1292 of file stm32l1xx.h.

#define ADC_SQR1_L ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

Definition at line 1313 of file stm32l1xx.h.

#define ADC_SQR1_L_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1314 of file stm32l1xx.h.

#define ADC_SQR1_L_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1315 of file stm32l1xx.h.

#define ADC_SQR1_L_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 1316 of file stm32l1xx.h.

#define ADC_SQR1_L_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 1317 of file stm32l1xx.h.

#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F)

SQ25[4:0] bits (25th conversion in regular sequence)

Definition at line 1340 of file stm32l1xx.h.

#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1341 of file stm32l1xx.h.

#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1342 of file stm32l1xx.h.

#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1343 of file stm32l1xx.h.

#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1344 of file stm32l1xx.h.

#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1345 of file stm32l1xx.h.

#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0)

SQ26[4:0] bits (26th conversion in regular sequence)

Definition at line 1333 of file stm32l1xx.h.

#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1334 of file stm32l1xx.h.

#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1335 of file stm32l1xx.h.

#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1336 of file stm32l1xx.h.

#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1337 of file stm32l1xx.h.

#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1338 of file stm32l1xx.h.

#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00)

SQ27[4:0] bits (27th conversion in regular sequence)

Definition at line 1326 of file stm32l1xx.h.

#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1327 of file stm32l1xx.h.

#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1328 of file stm32l1xx.h.

#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1329 of file stm32l1xx.h.

#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1330 of file stm32l1xx.h.

#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1331 of file stm32l1xx.h.

#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000)

SQ28[4:0] bits (25th conversion in regular sequence)

Definition at line 1319 of file stm32l1xx.h.

#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1320 of file stm32l1xx.h.

#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1321 of file stm32l1xx.h.

#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1322 of file stm32l1xx.h.

#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1323 of file stm32l1xx.h.

#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1324 of file stm32l1xx.h.

#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F)

SQ19[4:0] bits (19th conversion in regular sequence)

Definition at line 1348 of file stm32l1xx.h.

#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1349 of file stm32l1xx.h.

#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1350 of file stm32l1xx.h.

#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1351 of file stm32l1xx.h.

#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1352 of file stm32l1xx.h.

#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1353 of file stm32l1xx.h.

#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0)

SQ20[4:0] bits (20th conversion in regular sequence)

Definition at line 1355 of file stm32l1xx.h.

#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1356 of file stm32l1xx.h.

#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1357 of file stm32l1xx.h.

#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1358 of file stm32l1xx.h.

#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1359 of file stm32l1xx.h.

#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1360 of file stm32l1xx.h.

#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00)

SQ21[4:0] bits (21th conversion in regular sequence)

Definition at line 1362 of file stm32l1xx.h.

#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1363 of file stm32l1xx.h.

#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1364 of file stm32l1xx.h.

#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1365 of file stm32l1xx.h.

#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1366 of file stm32l1xx.h.

#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1367 of file stm32l1xx.h.

#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000)

SQ22[4:0] bits (22th conversion in regular sequence)

Definition at line 1369 of file stm32l1xx.h.

#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1370 of file stm32l1xx.h.

#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1371 of file stm32l1xx.h.

#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1372 of file stm32l1xx.h.

#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1373 of file stm32l1xx.h.

#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1374 of file stm32l1xx.h.

#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000)

SQ23[4:0] bits (23th conversion in regular sequence)

Definition at line 1376 of file stm32l1xx.h.

#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1377 of file stm32l1xx.h.

#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1378 of file stm32l1xx.h.

#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 1379 of file stm32l1xx.h.

#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 1380 of file stm32l1xx.h.

#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 1381 of file stm32l1xx.h.

#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000)

SQ24[4:0] bits (24th conversion in regular sequence)

Definition at line 1383 of file stm32l1xx.h.

#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 1384 of file stm32l1xx.h.

#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 1385 of file stm32l1xx.h.

#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 1386 of file stm32l1xx.h.

#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 1387 of file stm32l1xx.h.

#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 1388 of file stm32l1xx.h.

#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

Definition at line 1391 of file stm32l1xx.h.

#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1392 of file stm32l1xx.h.

#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1393 of file stm32l1xx.h.

#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1394 of file stm32l1xx.h.

#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1395 of file stm32l1xx.h.

#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1396 of file stm32l1xx.h.

#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

Definition at line 1398 of file stm32l1xx.h.

#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1399 of file stm32l1xx.h.

#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1400 of file stm32l1xx.h.

#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1401 of file stm32l1xx.h.

#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1402 of file stm32l1xx.h.

#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1403 of file stm32l1xx.h.

#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

Definition at line 1405 of file stm32l1xx.h.

#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1406 of file stm32l1xx.h.

#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1407 of file stm32l1xx.h.

#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1408 of file stm32l1xx.h.

#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1409 of file stm32l1xx.h.

#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1410 of file stm32l1xx.h.

#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

Definition at line 1412 of file stm32l1xx.h.

#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1413 of file stm32l1xx.h.

#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1414 of file stm32l1xx.h.

#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1415 of file stm32l1xx.h.

#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1416 of file stm32l1xx.h.

#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1417 of file stm32l1xx.h.

#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000)

SQ17[4:0] bits (17th conversion in regular sequence)

Definition at line 1419 of file stm32l1xx.h.

#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1420 of file stm32l1xx.h.

#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1421 of file stm32l1xx.h.

#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 1422 of file stm32l1xx.h.

#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 1423 of file stm32l1xx.h.

#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 1424 of file stm32l1xx.h.

#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000)

SQ18[4:0] bits (18th conversion in regular sequence)

Definition at line 1426 of file stm32l1xx.h.

#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 1427 of file stm32l1xx.h.

#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 1428 of file stm32l1xx.h.

#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 1429 of file stm32l1xx.h.

#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 1430 of file stm32l1xx.h.

#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 1431 of file stm32l1xx.h.

#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

Definition at line 1455 of file stm32l1xx.h.

#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1456 of file stm32l1xx.h.

#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1457 of file stm32l1xx.h.

#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1458 of file stm32l1xx.h.

#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1459 of file stm32l1xx.h.

#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1460 of file stm32l1xx.h.

#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

Definition at line 1462 of file stm32l1xx.h.

#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1463 of file stm32l1xx.h.

#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1464 of file stm32l1xx.h.

#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 1465 of file stm32l1xx.h.

#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 1466 of file stm32l1xx.h.

#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 1467 of file stm32l1xx.h.

#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

Definition at line 1469 of file stm32l1xx.h.

#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 1470 of file stm32l1xx.h.

#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 1471 of file stm32l1xx.h.

#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 1472 of file stm32l1xx.h.

#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 1473 of file stm32l1xx.h.

#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 1474 of file stm32l1xx.h.

#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

Definition at line 1434 of file stm32l1xx.h.

#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1435 of file stm32l1xx.h.

#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1436 of file stm32l1xx.h.

#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1437 of file stm32l1xx.h.

#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1438 of file stm32l1xx.h.

#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1439 of file stm32l1xx.h.

#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

Definition at line 1441 of file stm32l1xx.h.

#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1442 of file stm32l1xx.h.

#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1443 of file stm32l1xx.h.

#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1444 of file stm32l1xx.h.

#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1445 of file stm32l1xx.h.

#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1446 of file stm32l1xx.h.

#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

Definition at line 1448 of file stm32l1xx.h.

#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1449 of file stm32l1xx.h.

#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1450 of file stm32l1xx.h.

#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1451 of file stm32l1xx.h.

#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1452 of file stm32l1xx.h.

#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1453 of file stm32l1xx.h.

#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

Definition at line 1477 of file stm32l1xx.h.

#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1478 of file stm32l1xx.h.

#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1479 of file stm32l1xx.h.

#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 1480 of file stm32l1xx.h.

#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 1481 of file stm32l1xx.h.

#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 1482 of file stm32l1xx.h.

#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

Definition at line 1484 of file stm32l1xx.h.

#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1485 of file stm32l1xx.h.

#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1486 of file stm32l1xx.h.

#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 1487 of file stm32l1xx.h.

#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 1488 of file stm32l1xx.h.

#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 1489 of file stm32l1xx.h.

#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

Definition at line 1491 of file stm32l1xx.h.

#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 1492 of file stm32l1xx.h.

#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 1493 of file stm32l1xx.h.

#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 1494 of file stm32l1xx.h.

#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 1495 of file stm32l1xx.h.

#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 1496 of file stm32l1xx.h.

#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

Definition at line 1498 of file stm32l1xx.h.

#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 1499 of file stm32l1xx.h.

#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 1500 of file stm32l1xx.h.

#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 1501 of file stm32l1xx.h.

#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 1502 of file stm32l1xx.h.

#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 1503 of file stm32l1xx.h.

#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

Definition at line 1505 of file stm32l1xx.h.

#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 1506 of file stm32l1xx.h.

#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 1507 of file stm32l1xx.h.

#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 1508 of file stm32l1xx.h.

#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 1509 of file stm32l1xx.h.

#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 1510 of file stm32l1xx.h.

#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

Definition at line 1512 of file stm32l1xx.h.

#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 1513 of file stm32l1xx.h.

#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 1514 of file stm32l1xx.h.

#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 1515 of file stm32l1xx.h.

#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 1516 of file stm32l1xx.h.

#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 1517 of file stm32l1xx.h.

#define ADC_SR_ADONS ((uint32_t)0x00000040)

ADC ON status

Definition at line 1064 of file stm32l1xx.h.

#define ADC_SR_AWD ((uint32_t)0x00000001)

Analog watchdog flag

Definition at line 1058 of file stm32l1xx.h.

#define ADC_SR_EOC ((uint32_t)0x00000002)

End of conversion

Definition at line 1059 of file stm32l1xx.h.

#define ADC_SR_JCNR ((uint32_t)0x00000200)

Injected channel not ready flag

Definition at line 1066 of file stm32l1xx.h.

#define ADC_SR_JEOC ((uint32_t)0x00000004)

Injected channel end of conversion

Definition at line 1060 of file stm32l1xx.h.

#define ADC_SR_JSTRT ((uint32_t)0x00000008)

Injected channel Start flag

Definition at line 1061 of file stm32l1xx.h.

#define ADC_SR_OVR ((uint32_t)0x00000020)

Overrun flag

Definition at line 1063 of file stm32l1xx.h.

#define ADC_SR_RCNR ((uint32_t)0x00000100)

Regular channel not ready flag

Definition at line 1065 of file stm32l1xx.h.

#define ADC_SR_STRT ((uint32_t)0x00000010)

Regular channel Start flag

Definition at line 1062 of file stm32l1xx.h.

#define AES_CR_CCFC ((uint32_t)0x00000080)

Computation Complete Flag Clear

Definition at line 1613 of file stm32l1xx.h.

Referenced by AES_ClearFlag().

#define AES_CR_CCIE ((uint32_t)0x00000200)

Computation Complete Interrupt Enable

Definition at line 1615 of file stm32l1xx.h.

Referenced by AES_GetITStatus().

#define AES_CR_CHMOD ((uint32_t)0x00000060)

AES Chaining Mode

Definition at line 1609 of file stm32l1xx.h.

#define AES_CR_CHMOD_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 1610 of file stm32l1xx.h.

#define AES_CR_CHMOD_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 1611 of file stm32l1xx.h.

#define AES_CR_DATATYPE ((uint32_t)0x00000006)

Data type selection

Definition at line 1601 of file stm32l1xx.h.

#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002)

Bit 0

Definition at line 1602 of file stm32l1xx.h.

#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004)

Bit 1

Definition at line 1603 of file stm32l1xx.h.

#define AES_CR_DMAINEN ((uint32_t)0x00000800)

DMA ENable managing the data input phase

Definition at line 1617 of file stm32l1xx.h.

#define AES_CR_DMAOUTEN ((uint32_t)0x00001000)

DMA Enable managing the data output phase

Definition at line 1618 of file stm32l1xx.h.

#define AES_CR_EN ((uint32_t)0x00000001)

AES Enable

Definition at line 1600 of file stm32l1xx.h.

Referenced by AES_Cmd().

#define AES_CR_ERRC ((uint32_t)0x00000100)

Error Clear

Definition at line 1614 of file stm32l1xx.h.

Referenced by AES_ClearFlag().

#define AES_CR_ERRIE ((uint32_t)0x00000400)

Error Interrupt Enable

Definition at line 1616 of file stm32l1xx.h.

Referenced by AES_GetITStatus().

#define AES_CR_MODE ((uint32_t)0x00000018)

AES Mode Of Operation

Definition at line 1605 of file stm32l1xx.h.

#define AES_CR_MODE_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1606 of file stm32l1xx.h.

#define AES_CR_MODE_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1607 of file stm32l1xx.h.

#define AES_DINR ((uint32_t)0x0000FFFF)

AES Data Input Register

Definition at line 1626 of file stm32l1xx.h.

#define AES_DOUTR ((uint32_t)0x0000FFFF)

AES Data Output Register

Definition at line 1629 of file stm32l1xx.h.

#define AES_IVR0 ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 0

Definition at line 1644 of file stm32l1xx.h.

#define AES_IVR1 ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 1

Definition at line 1647 of file stm32l1xx.h.

#define AES_IVR2 ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 2

Definition at line 1650 of file stm32l1xx.h.

#define AES_IVR3 ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 3

Definition at line 1653 of file stm32l1xx.h.

#define AES_KEYR0 ((uint32_t)0x0000FFFF)

AES Key Register 0

Definition at line 1632 of file stm32l1xx.h.

#define AES_KEYR1 ((uint32_t)0x0000FFFF)

AES Key Register 1

Definition at line 1635 of file stm32l1xx.h.

#define AES_KEYR2 ((uint32_t)0x0000FFFF)

AES Key Register 2

Definition at line 1638 of file stm32l1xx.h.

#define AES_KEYR3 ((uint32_t)0x0000FFFF)

AES Key Register 3

Definition at line 1641 of file stm32l1xx.h.

#define AES_SR_CCF ((uint32_t)0x00000001)

Computation Complete Flag

Definition at line 1621 of file stm32l1xx.h.

Referenced by AES_GetITStatus().

#define AES_SR_RDERR ((uint32_t)0x00000002)

Read Error Flag

Definition at line 1622 of file stm32l1xx.h.

Referenced by AES_GetITStatus().

#define AES_SR_WRERR ((uint32_t)0x00000004)

Write Error Flag

Definition at line 1623 of file stm32l1xx.h.

Referenced by AES_GetITStatus().

#define COMP_CSR_10KPD ((uint32_t)0x00000004)

10K pull-down resistor

Definition at line 1664 of file stm32l1xx.h.

#define COMP_CSR_10KPU ((uint32_t)0x00000001)

10K pull-up resistor

Definition at line 1662 of file stm32l1xx.h.

#define COMP_CSR_400KPD ((uint32_t)0x00000008)

400K pull-down resistor

Definition at line 1665 of file stm32l1xx.h.

#define COMP_CSR_400KPU ((uint32_t)0x00000002)

400K pull-up resistor

Definition at line 1663 of file stm32l1xx.h.

#define COMP_CSR_CAIE ((uint32_t)0x20000000)

Bit 29

Definition at line 1691 of file stm32l1xx.h.

#define COMP_CSR_CAIF ((uint32_t)0x40000000)

Bit 30

Definition at line 1692 of file stm32l1xx.h.

#define COMP_CSR_CMP1EN ((uint32_t)0x00000010)

Comparator 1 enable

Definition at line 1667 of file stm32l1xx.h.

Referenced by COMP_Cmd().

#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080)

Comparator 1 output

Definition at line 1669 of file stm32l1xx.h.

Referenced by COMP_GetOutputLevel().

#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000)

Comparator 2 ouput

Definition at line 1672 of file stm32l1xx.h.

Referenced by COMP_GetOutputLevel().

#define COMP_CSR_FCH3 ((uint32_t)0x04000000)

Bit 26

Definition at line 1687 of file stm32l1xx.h.

#define COMP_CSR_FCH8 ((uint32_t)0x08000000)

Bit 27

Definition at line 1688 of file stm32l1xx.h.

#define COMP_CSR_INSEL ((uint32_t)0x001C0000)

INSEL[2:0] Inversion input Selection

Definition at line 1677 of file stm32l1xx.h.

Referenced by COMP_Init().

#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 1678 of file stm32l1xx.h.

#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 1679 of file stm32l1xx.h.

#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 1680 of file stm32l1xx.h.

#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000)

OUTSEL[2:0] comparator 2 output redirection

Definition at line 1682 of file stm32l1xx.h.

Referenced by COMP_Init().

#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 1683 of file stm32l1xx.h.

#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 1684 of file stm32l1xx.h.

#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 1685 of file stm32l1xx.h.

#define COMP_CSR_RCH13 ((uint32_t)0x10000000)

Bit 28

Definition at line 1689 of file stm32l1xx.h.

#define COMP_CSR_SPEED ((uint32_t)0x00001000)

Comparator 2 speed

Definition at line 1671 of file stm32l1xx.h.

Referenced by COMP_Init().

#define COMP_CSR_SW1 ((uint32_t)0x00000020)

SW1 analog switch enable

Definition at line 1668 of file stm32l1xx.h.

Referenced by COMP_SW1SwitchConfig().

#define COMP_CSR_TSUSP ((uint32_t)0x80000000)

Bit 31

Definition at line 1693 of file stm32l1xx.h.

#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000)

Comparator Vref Enable

Definition at line 1674 of file stm32l1xx.h.

Referenced by COMP_VrefintOutputCmd().

#define COMP_CSR_WNDWE ((uint32_t)0x00020000)

Window mode enable

Definition at line 1675 of file stm32l1xx.h.

Referenced by COMP_WindowCmd().

#define CRC_CR_RESET ((uint32_t)0x00000001)

RESET bit

Definition at line 1758 of file stm32l1xx.h.

Referenced by CRC_ResetDR().

#define CRC_DR_DR ((uint32_t)0xFFFFFFFF)

Data register bits

Definition at line 1752 of file stm32l1xx.h.

#define CRC_IDR_IDR ((uint8_t)0xFF)

General-purpose 8-bit data register bits

Definition at line 1755 of file stm32l1xx.h.

#define DAC_CR_BOFF1 ((uint32_t)0x00000002)

DAC channel1 output buffer disable

Definition at line 1768 of file stm32l1xx.h.

#define DAC_CR_BOFF2 ((uint32_t)0x00020000)

DAC channel2 output buffer disable

Definition at line 1789 of file stm32l1xx.h.

#define DAC_CR_DMAEN1 ((uint32_t)0x00001000)

DAC channel1 DMA enable

Definition at line 1786 of file stm32l1xx.h.

Referenced by DAC_DMACmd().

#define DAC_CR_DMAEN2 ((uint32_t)0x10000000)

DAC channel2 DMA enabled

Definition at line 1807 of file stm32l1xx.h.

#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000)

DAC channel1 DMA underrun interrupt enable

Definition at line 1787 of file stm32l1xx.h.

#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000)

DAC channel2 DMA underrun interrupt enable

Definition at line 1808 of file stm32l1xx.h.

#define DAC_CR_EN1 ((uint32_t)0x00000001)

DAC channel1 enable

Definition at line 1767 of file stm32l1xx.h.

Referenced by DAC_Cmd().

#define DAC_CR_EN2 ((uint32_t)0x00010000)

DAC channel2 enable

Definition at line 1788 of file stm32l1xx.h.

#define DAC_CR_MAMP1 ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

Definition at line 1780 of file stm32l1xx.h.

#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 1781 of file stm32l1xx.h.

#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 1782 of file stm32l1xx.h.

#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 1783 of file stm32l1xx.h.

#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 1784 of file stm32l1xx.h.

#define DAC_CR_MAMP2 ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

Definition at line 1801 of file stm32l1xx.h.

#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1802 of file stm32l1xx.h.

#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1803 of file stm32l1xx.h.

#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1804 of file stm32l1xx.h.

#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 1805 of file stm32l1xx.h.

#define DAC_CR_TEN1 ((uint32_t)0x00000004)

DAC channel1 Trigger enable

Definition at line 1769 of file stm32l1xx.h.

#define DAC_CR_TEN2 ((uint32_t)0x00040000)

DAC channel2 Trigger enable

Definition at line 1790 of file stm32l1xx.h.

#define DAC_CR_TSEL1 ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

Definition at line 1771 of file stm32l1xx.h.

#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 1772 of file stm32l1xx.h.

#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 1773 of file stm32l1xx.h.

#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 1774 of file stm32l1xx.h.

#define DAC_CR_TSEL2 ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

Definition at line 1792 of file stm32l1xx.h.

#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)

Bit 0

Definition at line 1793 of file stm32l1xx.h.

#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)

Bit 1

Definition at line 1794 of file stm32l1xx.h.

#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)

Bit 2

Definition at line 1795 of file stm32l1xx.h.

#define DAC_CR_WAVE1 ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

Definition at line 1776 of file stm32l1xx.h.

#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 1777 of file stm32l1xx.h.

#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 1778 of file stm32l1xx.h.

#define DAC_CR_WAVE2 ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

Definition at line 1797 of file stm32l1xx.h.

#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)

Bit 0

Definition at line 1798 of file stm32l1xx.h.

#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)

Bit 1

Definition at line 1799 of file stm32l1xx.h.

#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

Definition at line 1817 of file stm32l1xx.h.

#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

Definition at line 1826 of file stm32l1xx.h.

#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

Definition at line 1836 of file stm32l1xx.h.

#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

Definition at line 1837 of file stm32l1xx.h.

#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

Definition at line 1814 of file stm32l1xx.h.

#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

Definition at line 1823 of file stm32l1xx.h.

#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

Definition at line 1832 of file stm32l1xx.h.

#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

Definition at line 1833 of file stm32l1xx.h.

#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

Definition at line 1820 of file stm32l1xx.h.

#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

Definition at line 1829 of file stm32l1xx.h.

#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

Definition at line 1840 of file stm32l1xx.h.

#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

Definition at line 1841 of file stm32l1xx.h.

#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)

DAC channel1 data output

Definition at line 1844 of file stm32l1xx.h.

#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)

DAC channel2 data output

Definition at line 1847 of file stm32l1xx.h.

#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

Definition at line 1850 of file stm32l1xx.h.

#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

Definition at line 1851 of file stm32l1xx.h.

#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)

DAC channel1 software trigger

Definition at line 1810 of file stm32l1xx.h.

Referenced by DAC_SoftwareTriggerCmd().

#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)

DAC channel2 software trigger

Definition at line 1811 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)

SMBUS timeout mode stopped when Core is halted

Definition at line 1901 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)

SMBUS timeout mode stopped when Core is halted

Definition at line 1902 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)

Debug Independent Watchdog stopped when Core is halted

Definition at line 1900 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)

RTC Counter stopped when Core is halted

Definition at line 1898 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)

TIM2 counter stopped when core is halted

Definition at line 1892 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)

TIM3 counter stopped when core is halted

Definition at line 1893 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)

TIM4 counter stopped when core is halted

Definition at line 1894 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)

TIM5 counter stopped when core is halted

Definition at line 1895 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)

TIM6 counter stopped when core is halted

Definition at line 1896 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)

TIM7 counter stopped when core is halted

Definition at line 1897 of file stm32l1xx.h.

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)

Debug Window Watchdog stopped when Core is halted

Definition at line 1899 of file stm32l1xx.h.

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008)

TIM10 counter stopped when core is halted

Definition at line 1907 of file stm32l1xx.h.

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010)

TIM11 counter stopped when core is halted

Definition at line 1908 of file stm32l1xx.h.

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004)

TIM9 counter stopped when core is halted

Definition at line 1906 of file stm32l1xx.h.

#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)

Debug Sleep Mode

Definition at line 1881 of file stm32l1xx.h.

#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)

Debug Standby mode

Definition at line 1883 of file stm32l1xx.h.

#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)

Debug Stop Mode

Definition at line 1882 of file stm32l1xx.h.

#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)

Trace Pin Assignment Control

Definition at line 1884 of file stm32l1xx.h.

#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)

TRACE_MODE[1:0] bits (Trace Pin Assignment Control)

Definition at line 1886 of file stm32l1xx.h.

#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 1887 of file stm32l1xx.h.

#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 1888 of file stm32l1xx.h.

#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)

Device Identifier

Definition at line 1860 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)

REV_ID[15:0] bits (Revision Identifier)

Definition at line 1862 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 1863 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 1864 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)

Bit 10

Definition at line 1873 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)

Bit 11

Definition at line 1874 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)

Bit 12

Definition at line 1875 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)

Bit 13

Definition at line 1876 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)

Bit 14

Definition at line 1877 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)

Bit 15

Definition at line 1878 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 1865 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 1866 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 1867 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 1868 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 1869 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 1870 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)

Bit 8

Definition at line 1871 of file stm32l1xx.h.

#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)

Bit 9

Definition at line 1872 of file stm32l1xx.h.

#define DMA_CCR1_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 1982 of file stm32l1xx.h.

#define DMA_CCR1_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 1981 of file stm32l1xx.h.

#define DMA_CCR1_EN ((uint16_t)0x0001)

Channel enable

Definition at line 1977 of file stm32l1xx.h.

Referenced by DMA_Cmd(), and DMA_DeInit().

#define DMA_CCR1_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 1979 of file stm32l1xx.h.

#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 1998 of file stm32l1xx.h.

#define DMA_CCR1_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 1984 of file stm32l1xx.h.

#define DMA_CCR1_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 1990 of file stm32l1xx.h.

#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 1991 of file stm32l1xx.h.

#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 1992 of file stm32l1xx.h.

#define DMA_CCR1_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 1983 of file stm32l1xx.h.

#define DMA_CCR1_PL ((uint16_t)0x3000)

PL[1:0] bits(Channel Priority level)

Definition at line 1994 of file stm32l1xx.h.

#define DMA_CCR1_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 1995 of file stm32l1xx.h.

#define DMA_CCR1_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 1996 of file stm32l1xx.h.

#define DMA_CCR1_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 1986 of file stm32l1xx.h.

#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 1987 of file stm32l1xx.h.

#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 1988 of file stm32l1xx.h.

#define DMA_CCR1_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 1978 of file stm32l1xx.h.

#define DMA_CCR1_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 1980 of file stm32l1xx.h.

#define DMA_CCR2_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2006 of file stm32l1xx.h.

#define DMA_CCR2_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2005 of file stm32l1xx.h.

#define DMA_CCR2_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2001 of file stm32l1xx.h.

#define DMA_CCR2_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2003 of file stm32l1xx.h.

#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 2022 of file stm32l1xx.h.

#define DMA_CCR2_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2008 of file stm32l1xx.h.

#define DMA_CCR2_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2014 of file stm32l1xx.h.

#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2015 of file stm32l1xx.h.

#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2016 of file stm32l1xx.h.

#define DMA_CCR2_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2007 of file stm32l1xx.h.

#define DMA_CCR2_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2018 of file stm32l1xx.h.

#define DMA_CCR2_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2019 of file stm32l1xx.h.

#define DMA_CCR2_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2020 of file stm32l1xx.h.

#define DMA_CCR2_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2010 of file stm32l1xx.h.

#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2011 of file stm32l1xx.h.

#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2012 of file stm32l1xx.h.

#define DMA_CCR2_TCIE ((uint16_t)0x0002)

ransfer complete interrupt enable

Definition at line 2002 of file stm32l1xx.h.

#define DMA_CCR2_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2004 of file stm32l1xx.h.

#define DMA_CCR3_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2030 of file stm32l1xx.h.

#define DMA_CCR3_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2029 of file stm32l1xx.h.

#define DMA_CCR3_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2025 of file stm32l1xx.h.

#define DMA_CCR3_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2027 of file stm32l1xx.h.

#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode ****************** Bit definition for DMA_CCR4 register

Definition at line 2046 of file stm32l1xx.h.

#define DMA_CCR3_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2032 of file stm32l1xx.h.

#define DMA_CCR3_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2038 of file stm32l1xx.h.

#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2039 of file stm32l1xx.h.

#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2040 of file stm32l1xx.h.

#define DMA_CCR3_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2031 of file stm32l1xx.h.

#define DMA_CCR3_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2042 of file stm32l1xx.h.

#define DMA_CCR3_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2043 of file stm32l1xx.h.

#define DMA_CCR3_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2044 of file stm32l1xx.h.

#define DMA_CCR3_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2034 of file stm32l1xx.h.

#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2035 of file stm32l1xx.h.

#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2036 of file stm32l1xx.h.

#define DMA_CCR3_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 2026 of file stm32l1xx.h.

#define DMA_CCR3_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2028 of file stm32l1xx.h.

#define DMA_CCR4_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2054 of file stm32l1xx.h.

#define DMA_CCR4_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2053 of file stm32l1xx.h.

#define DMA_CCR4_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2049 of file stm32l1xx.h.

#define DMA_CCR4_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2051 of file stm32l1xx.h.

#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 2070 of file stm32l1xx.h.

#define DMA_CCR4_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2056 of file stm32l1xx.h.

#define DMA_CCR4_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2062 of file stm32l1xx.h.

#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2063 of file stm32l1xx.h.

#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2064 of file stm32l1xx.h.

#define DMA_CCR4_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2055 of file stm32l1xx.h.

#define DMA_CCR4_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2066 of file stm32l1xx.h.

#define DMA_CCR4_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2067 of file stm32l1xx.h.

#define DMA_CCR4_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2068 of file stm32l1xx.h.

#define DMA_CCR4_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2058 of file stm32l1xx.h.

#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2059 of file stm32l1xx.h.

#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2060 of file stm32l1xx.h.

#define DMA_CCR4_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 2050 of file stm32l1xx.h.

#define DMA_CCR4_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2052 of file stm32l1xx.h.

#define DMA_CCR5_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2078 of file stm32l1xx.h.

#define DMA_CCR5_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2077 of file stm32l1xx.h.

#define DMA_CCR5_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2073 of file stm32l1xx.h.

#define DMA_CCR5_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2075 of file stm32l1xx.h.

#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode enable

Definition at line 2094 of file stm32l1xx.h.

#define DMA_CCR5_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2080 of file stm32l1xx.h.

#define DMA_CCR5_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2086 of file stm32l1xx.h.

#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2087 of file stm32l1xx.h.

#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2088 of file stm32l1xx.h.

#define DMA_CCR5_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2079 of file stm32l1xx.h.

#define DMA_CCR5_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2090 of file stm32l1xx.h.

#define DMA_CCR5_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2091 of file stm32l1xx.h.

#define DMA_CCR5_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2092 of file stm32l1xx.h.

#define DMA_CCR5_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2082 of file stm32l1xx.h.

#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2083 of file stm32l1xx.h.

#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2084 of file stm32l1xx.h.

#define DMA_CCR5_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 2074 of file stm32l1xx.h.

#define DMA_CCR5_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2076 of file stm32l1xx.h.

#define DMA_CCR6_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2102 of file stm32l1xx.h.

#define DMA_CCR6_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2101 of file stm32l1xx.h.

#define DMA_CCR6_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2097 of file stm32l1xx.h.

#define DMA_CCR6_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2099 of file stm32l1xx.h.

#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 2118 of file stm32l1xx.h.

#define DMA_CCR6_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2104 of file stm32l1xx.h.

#define DMA_CCR6_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2110 of file stm32l1xx.h.

#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2111 of file stm32l1xx.h.

#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2112 of file stm32l1xx.h.

#define DMA_CCR6_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2103 of file stm32l1xx.h.

#define DMA_CCR6_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2114 of file stm32l1xx.h.

#define DMA_CCR6_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2115 of file stm32l1xx.h.

#define DMA_CCR6_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2116 of file stm32l1xx.h.

#define DMA_CCR6_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2106 of file stm32l1xx.h.

#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2107 of file stm32l1xx.h.

#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2108 of file stm32l1xx.h.

#define DMA_CCR6_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 2098 of file stm32l1xx.h.

#define DMA_CCR6_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2100 of file stm32l1xx.h.

#define DMA_CCR7_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 2126 of file stm32l1xx.h.

#define DMA_CCR7_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 2125 of file stm32l1xx.h.

#define DMA_CCR7_EN ((uint16_t)0x0001)

Channel enable

Definition at line 2121 of file stm32l1xx.h.

#define DMA_CCR7_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 2123 of file stm32l1xx.h.

#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode enable

Definition at line 2142 of file stm32l1xx.h.

#define DMA_CCR7_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 2128 of file stm32l1xx.h.

#define DMA_CCR7_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 2134 of file stm32l1xx.h.

#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 2135 of file stm32l1xx.h.

#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 2136 of file stm32l1xx.h.

#define DMA_CCR7_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 2127 of file stm32l1xx.h.

#define DMA_CCR7_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 2138 of file stm32l1xx.h.

#define DMA_CCR7_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 2139 of file stm32l1xx.h.

#define DMA_CCR7_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 2140 of file stm32l1xx.h.

#define DMA_CCR7_PSIZE , ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 2130 of file stm32l1xx.h.

#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 2131 of file stm32l1xx.h.

#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 2132 of file stm32l1xx.h.

#define DMA_CCR7_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 2122 of file stm32l1xx.h.

#define DMA_CCR7_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 2124 of file stm32l1xx.h.

#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2189 of file stm32l1xx.h.

#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2192 of file stm32l1xx.h.

#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2195 of file stm32l1xx.h.

#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2199 of file stm32l1xx.h.

#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2202 of file stm32l1xx.h.

#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2205 of file stm32l1xx.h.

#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 2208 of file stm32l1xx.h.

#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2145 of file stm32l1xx.h.

#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2148 of file stm32l1xx.h.

#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2151 of file stm32l1xx.h.

#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2154 of file stm32l1xx.h.

#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2157 of file stm32l1xx.h.

#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2160 of file stm32l1xx.h.

#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 2163 of file stm32l1xx.h.

#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2166 of file stm32l1xx.h.

#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2169 of file stm32l1xx.h.

#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2172 of file stm32l1xx.h.

#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2176 of file stm32l1xx.h.

#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2179 of file stm32l1xx.h.

#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2182 of file stm32l1xx.h.

#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 2186 of file stm32l1xx.h.

#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001)

Channel 1 Global interrupt clearr

Definition at line 1947 of file stm32l1xx.h.

#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010)

Channel 2 Global interrupt clear

Definition at line 1951 of file stm32l1xx.h.

#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100)

Channel 3 Global interrupt clear

Definition at line 1955 of file stm32l1xx.h.

#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000)

Channel 4 Global interrupt clear

Definition at line 1959 of file stm32l1xx.h.

#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000)

Channel 5 Global interrupt clear

Definition at line 1963 of file stm32l1xx.h.

#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000)

Channel 6 Global interrupt clear

Definition at line 1967 of file stm32l1xx.h.

#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000)

Channel 7 Global interrupt clear

Definition at line 1971 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)

Channel 1 Half Transfer clear

Definition at line 1949 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)

Channel 2 Half Transfer clear

Definition at line 1953 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)

Channel 3 Half Transfer clear

Definition at line 1957 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)

Channel 4 Half Transfer clear

Definition at line 1961 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)

Channel 5 Half Transfer clear

Definition at line 1965 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)

Channel 6 Half Transfer clear

Definition at line 1969 of file stm32l1xx.h.

#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)

Channel 7 Half Transfer clear

Definition at line 1973 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)

Channel 1 Transfer Complete clear

Definition at line 1948 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)

Channel 2 Transfer Complete clear

Definition at line 1952 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)

Channel 3 Transfer Complete clear

Definition at line 1956 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)

Channel 4 Transfer Complete clear

Definition at line 1960 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)

Channel 5 Transfer Complete clear

Definition at line 1964 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)

Channel 6 Transfer Complete clear

Definition at line 1968 of file stm32l1xx.h.

#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)

Channel 7 Transfer Complete clear

Definition at line 1972 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)

Channel 1 Transfer Error clear

Definition at line 1950 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)

Channel 2 Transfer Error clear

Definition at line 1954 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)

Channel 3 Transfer Error clear

Definition at line 1958 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)

Channel 4 Transfer Error clear

Definition at line 1962 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)

Channel 5 Transfer Error clear

Definition at line 1966 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)

Channel 6 Transfer Error clear

Definition at line 1970 of file stm32l1xx.h.

#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)

Channel 7 Transfer Error clear

Definition at line 1974 of file stm32l1xx.h.

#define DMA_ISR_GIF1 ((uint32_t)0x00000001)

Channel 1 Global interrupt flag

Definition at line 1917 of file stm32l1xx.h.

#define DMA_ISR_GIF2 ((uint32_t)0x00000010)

Channel 2 Global interrupt flag

Definition at line 1921 of file stm32l1xx.h.

#define DMA_ISR_GIF3 ((uint32_t)0x00000100)

Channel 3 Global interrupt flag

Definition at line 1925 of file stm32l1xx.h.

#define DMA_ISR_GIF4 ((uint32_t)0x00001000)

Channel 4 Global interrupt flag

Definition at line 1929 of file stm32l1xx.h.

#define DMA_ISR_GIF5 ((uint32_t)0x00010000)

Channel 5 Global interrupt flag

Definition at line 1933 of file stm32l1xx.h.

#define DMA_ISR_GIF6 ((uint32_t)0x00100000)

Channel 6 Global interrupt flag

Definition at line 1937 of file stm32l1xx.h.

#define DMA_ISR_GIF7 ((uint32_t)0x01000000)

Channel 7 Global interrupt flag

Definition at line 1941 of file stm32l1xx.h.

#define DMA_ISR_HTIF1 ((uint32_t)0x00000004)

Channel 1 Half Transfer flag

Definition at line 1919 of file stm32l1xx.h.

#define DMA_ISR_HTIF2 ((uint32_t)0x00000040)

Channel 2 Half Transfer flag

Definition at line 1923 of file stm32l1xx.h.

#define DMA_ISR_HTIF3 ((uint32_t)0x00000400)

Channel 3 Half Transfer flag

Definition at line 1927 of file stm32l1xx.h.

#define DMA_ISR_HTIF4 ((uint32_t)0x00004000)

Channel 4 Half Transfer flag

Definition at line 1931 of file stm32l1xx.h.

#define DMA_ISR_HTIF5 ((uint32_t)0x00040000)

Channel 5 Half Transfer flag

Definition at line 1935 of file stm32l1xx.h.

#define DMA_ISR_HTIF6 ((uint32_t)0x00400000)

Channel 6 Half Transfer flag

Definition at line 1939 of file stm32l1xx.h.

#define DMA_ISR_HTIF7 ((uint32_t)0x04000000)

Channel 7 Half Transfer flag

Definition at line 1943 of file stm32l1xx.h.

#define DMA_ISR_TCIF1 ((uint32_t)0x00000002)

Channel 1 Transfer Complete flag

Definition at line 1918 of file stm32l1xx.h.

#define DMA_ISR_TCIF2 ((uint32_t)0x00000020)

Channel 2 Transfer Complete flag

Definition at line 1922 of file stm32l1xx.h.

#define DMA_ISR_TCIF3 ((uint32_t)0x00000200)

Channel 3 Transfer Complete flag

Definition at line 1926 of file stm32l1xx.h.

#define DMA_ISR_TCIF4 ((uint32_t)0x00002000)

Channel 4 Transfer Complete flag

Definition at line 1930 of file stm32l1xx.h.

#define DMA_ISR_TCIF5 ((uint32_t)0x00020000)

Channel 5 Transfer Complete flag

Definition at line 1934 of file stm32l1xx.h.

#define DMA_ISR_TCIF6 ((uint32_t)0x00200000)

Channel 6 Transfer Complete flag

Definition at line 1938 of file stm32l1xx.h.

#define DMA_ISR_TCIF7 ((uint32_t)0x02000000)

Channel 7 Transfer Complete flag

Definition at line 1942 of file stm32l1xx.h.

#define DMA_ISR_TEIF1 ((uint32_t)0x00000008)

Channel 1 Transfer Error flag

Definition at line 1920 of file stm32l1xx.h.

#define DMA_ISR_TEIF2 ((uint32_t)0x00000080)

Channel 2 Transfer Error flag

Definition at line 1924 of file stm32l1xx.h.

#define DMA_ISR_TEIF3 ((uint32_t)0x00000800)

Channel 3 Transfer Error flag

Definition at line 1928 of file stm32l1xx.h.

#define DMA_ISR_TEIF4 ((uint32_t)0x00008000)

Channel 4 Transfer Error flag

Definition at line 1932 of file stm32l1xx.h.

#define DMA_ISR_TEIF5 ((uint32_t)0x00080000)

Channel 5 Transfer Error flag

Definition at line 1936 of file stm32l1xx.h.

#define DMA_ISR_TEIF6 ((uint32_t)0x00800000)

Channel 6 Transfer Error flag

Definition at line 1940 of file stm32l1xx.h.

#define DMA_ISR_TEIF7 ((uint32_t)0x08000000)

Channel 7 Transfer Error flag

Definition at line 1944 of file stm32l1xx.h.

#define EXTI_EMR_MR0 ((uint32_t)0x00000001)

Event Mask on line 0

Definition at line 2243 of file stm32l1xx.h.

#define EXTI_EMR_MR1 ((uint32_t)0x00000002)

Event Mask on line 1

Definition at line 2244 of file stm32l1xx.h.

#define EXTI_EMR_MR10 ((uint32_t)0x00000400)

Event Mask on line 10

Definition at line 2253 of file stm32l1xx.h.

#define EXTI_EMR_MR11 ((uint32_t)0x00000800)

Event Mask on line 11

Definition at line 2254 of file stm32l1xx.h.

#define EXTI_EMR_MR12 ((uint32_t)0x00001000)

Event Mask on line 12

Definition at line 2255 of file stm32l1xx.h.

#define EXTI_EMR_MR13 ((uint32_t)0x00002000)

Event Mask on line 13

Definition at line 2256 of file stm32l1xx.h.

#define EXTI_EMR_MR14 ((uint32_t)0x00004000)

Event Mask on line 14

Definition at line 2257 of file stm32l1xx.h.

#define EXTI_EMR_MR15 ((uint32_t)0x00008000)

Event Mask on line 15

Definition at line 2258 of file stm32l1xx.h.

#define EXTI_EMR_MR16 ((uint32_t)0x00010000)

Event Mask on line 16

Definition at line 2259 of file stm32l1xx.h.

#define EXTI_EMR_MR17 ((uint32_t)0x00020000)

Event Mask on line 17

Definition at line 2260 of file stm32l1xx.h.

#define EXTI_EMR_MR18 ((uint32_t)0x00040000)

Event Mask on line 18

Definition at line 2261 of file stm32l1xx.h.

#define EXTI_EMR_MR19 ((uint32_t)0x00080000)

Event Mask on line 19

Definition at line 2262 of file stm32l1xx.h.

#define EXTI_EMR_MR2 ((uint32_t)0x00000004)

Event Mask on line 2

Definition at line 2245 of file stm32l1xx.h.

#define EXTI_EMR_MR20 ((uint32_t)0x00100000)

Event Mask on line 20

Definition at line 2263 of file stm32l1xx.h.

#define EXTI_EMR_MR21 ((uint32_t)0x00200000)

Event Mask on line 21

Definition at line 2264 of file stm32l1xx.h.

#define EXTI_EMR_MR22 ((uint32_t)0x00400000)

Event Mask on line 22

Definition at line 2265 of file stm32l1xx.h.

#define EXTI_EMR_MR23 ((uint32_t)0x00800000)

Event Mask on line 23

Definition at line 2266 of file stm32l1xx.h.

#define EXTI_EMR_MR3 ((uint32_t)0x00000008)

Event Mask on line 3

Definition at line 2246 of file stm32l1xx.h.

#define EXTI_EMR_MR4 ((uint32_t)0x00000010)

Event Mask on line 4

Definition at line 2247 of file stm32l1xx.h.

#define EXTI_EMR_MR5 ((uint32_t)0x00000020)

Event Mask on line 5

Definition at line 2248 of file stm32l1xx.h.

#define EXTI_EMR_MR6 ((uint32_t)0x00000040)

Event Mask on line 6

Definition at line 2249 of file stm32l1xx.h.

#define EXTI_EMR_MR7 ((uint32_t)0x00000080)

Event Mask on line 7

Definition at line 2250 of file stm32l1xx.h.

#define EXTI_EMR_MR8 ((uint32_t)0x00000100)

Event Mask on line 8

Definition at line 2251 of file stm32l1xx.h.

#define EXTI_EMR_MR9 ((uint32_t)0x00000200)

Event Mask on line 9

Definition at line 2252 of file stm32l1xx.h.

#define EXTI_FTSR_TR0 ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

Definition at line 2295 of file stm32l1xx.h.

#define EXTI_FTSR_TR1 ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

Definition at line 2296 of file stm32l1xx.h.

#define EXTI_FTSR_TR10 ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

Definition at line 2305 of file stm32l1xx.h.

#define EXTI_FTSR_TR11 ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

Definition at line 2306 of file stm32l1xx.h.

#define EXTI_FTSR_TR12 ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

Definition at line 2307 of file stm32l1xx.h.

#define EXTI_FTSR_TR13 ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

Definition at line 2308 of file stm32l1xx.h.

#define EXTI_FTSR_TR14 ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

Definition at line 2309 of file stm32l1xx.h.

#define EXTI_FTSR_TR15 ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

Definition at line 2310 of file stm32l1xx.h.

#define EXTI_FTSR_TR16 ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

Definition at line 2311 of file stm32l1xx.h.

#define EXTI_FTSR_TR17 ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

Definition at line 2312 of file stm32l1xx.h.

#define EXTI_FTSR_TR18 ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

Definition at line 2313 of file stm32l1xx.h.

#define EXTI_FTSR_TR19 ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

Definition at line 2314 of file stm32l1xx.h.

#define EXTI_FTSR_TR2 ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

Definition at line 2297 of file stm32l1xx.h.

#define EXTI_FTSR_TR20 ((uint32_t)0x00100000)

Falling trigger event configuration bit of line 20

Definition at line 2315 of file stm32l1xx.h.

#define EXTI_FTSR_TR21 ((uint32_t)0x00200000)

Falling trigger event configuration bit of line 21

Definition at line 2316 of file stm32l1xx.h.

#define EXTI_FTSR_TR22 ((uint32_t)0x00400000)

Falling trigger event configuration bit of line 22

Definition at line 2317 of file stm32l1xx.h.

#define EXTI_FTSR_TR23 ((uint32_t)0x00800000)

Falling trigger event configuration bit of line 23

Definition at line 2318 of file stm32l1xx.h.

#define EXTI_FTSR_TR3 ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

Definition at line 2298 of file stm32l1xx.h.

#define EXTI_FTSR_TR4 ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

Definition at line 2299 of file stm32l1xx.h.

#define EXTI_FTSR_TR5 ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

Definition at line 2300 of file stm32l1xx.h.

#define EXTI_FTSR_TR6 ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

Definition at line 2301 of file stm32l1xx.h.

#define EXTI_FTSR_TR7 ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

Definition at line 2302 of file stm32l1xx.h.

#define EXTI_FTSR_TR8 ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

Definition at line 2303 of file stm32l1xx.h.

#define EXTI_FTSR_TR9 ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

Definition at line 2304 of file stm32l1xx.h.

#define EXTI_IMR_MR0 ((uint32_t)0x00000001)

Interrupt Mask on line 0

Definition at line 2217 of file stm32l1xx.h.

#define EXTI_IMR_MR1 ((uint32_t)0x00000002)

Interrupt Mask on line 1

Definition at line 2218 of file stm32l1xx.h.

#define EXTI_IMR_MR10 ((uint32_t)0x00000400)

Interrupt Mask on line 10

Definition at line 2227 of file stm32l1xx.h.

#define EXTI_IMR_MR11 ((uint32_t)0x00000800)

Interrupt Mask on line 11

Definition at line 2228 of file stm32l1xx.h.

#define EXTI_IMR_MR12 ((uint32_t)0x00001000)

Interrupt Mask on line 12

Definition at line 2229 of file stm32l1xx.h.

#define EXTI_IMR_MR13 ((uint32_t)0x00002000)

Interrupt Mask on line 13

Definition at line 2230 of file stm32l1xx.h.

#define EXTI_IMR_MR14 ((uint32_t)0x00004000)

Interrupt Mask on line 14

Definition at line 2231 of file stm32l1xx.h.

#define EXTI_IMR_MR15 ((uint32_t)0x00008000)

Interrupt Mask on line 15

Definition at line 2232 of file stm32l1xx.h.

#define EXTI_IMR_MR16 ((uint32_t)0x00010000)

Interrupt Mask on line 16

Definition at line 2233 of file stm32l1xx.h.

#define EXTI_IMR_MR17 ((uint32_t)0x00020000)

Interrupt Mask on line 17

Definition at line 2234 of file stm32l1xx.h.

#define EXTI_IMR_MR18 ((uint32_t)0x00040000)

Interrupt Mask on line 18

Definition at line 2235 of file stm32l1xx.h.

#define EXTI_IMR_MR19 ((uint32_t)0x00080000)

Interrupt Mask on line 19

Definition at line 2236 of file stm32l1xx.h.

#define EXTI_IMR_MR2 ((uint32_t)0x00000004)

Interrupt Mask on line 2

Definition at line 2219 of file stm32l1xx.h.

#define EXTI_IMR_MR20 ((uint32_t)0x00100000)

Interrupt Mask on line 20

Definition at line 2237 of file stm32l1xx.h.

#define EXTI_IMR_MR21 ((uint32_t)0x00200000)

Interrupt Mask on line 21

Definition at line 2238 of file stm32l1xx.h.

#define EXTI_IMR_MR22 ((uint32_t)0x00400000)

Interrupt Mask on line 22

Definition at line 2239 of file stm32l1xx.h.

#define EXTI_IMR_MR23 ((uint32_t)0x00800000)

Interrupt Mask on line 23

Definition at line 2240 of file stm32l1xx.h.

#define EXTI_IMR_MR3 ((uint32_t)0x00000008)

Interrupt Mask on line 3

Definition at line 2220 of file stm32l1xx.h.

#define EXTI_IMR_MR4 ((uint32_t)0x00000010)

Interrupt Mask on line 4

Definition at line 2221 of file stm32l1xx.h.

#define EXTI_IMR_MR5 ((uint32_t)0x00000020)

Interrupt Mask on line 5

Definition at line 2222 of file stm32l1xx.h.

#define EXTI_IMR_MR6 ((uint32_t)0x00000040)

Interrupt Mask on line 6

Definition at line 2223 of file stm32l1xx.h.

#define EXTI_IMR_MR7 ((uint32_t)0x00000080)

Interrupt Mask on line 7

Definition at line 2224 of file stm32l1xx.h.

#define EXTI_IMR_MR8 ((uint32_t)0x00000100)

Interrupt Mask on line 8

Definition at line 2225 of file stm32l1xx.h.

#define EXTI_IMR_MR9 ((uint32_t)0x00000200)

Interrupt Mask on line 9

Definition at line 2226 of file stm32l1xx.h.

#define EXTI_PR_PR0 ((uint32_t)0x00000001)

Pending bit 0

Definition at line 2347 of file stm32l1xx.h.

#define EXTI_PR_PR1 ((uint32_t)0x00000002)

Pending bit 1

Definition at line 2348 of file stm32l1xx.h.

#define EXTI_PR_PR10 ((uint32_t)0x00000400)

Pending bit 10

Definition at line 2357 of file stm32l1xx.h.

#define EXTI_PR_PR11 ((uint32_t)0x00000800)

Pending bit 11

Definition at line 2358 of file stm32l1xx.h.

#define EXTI_PR_PR12 ((uint32_t)0x00001000)

Pending bit 12

Definition at line 2359 of file stm32l1xx.h.

#define EXTI_PR_PR13 ((uint32_t)0x00002000)

Pending bit 13

Definition at line 2360 of file stm32l1xx.h.

#define EXTI_PR_PR14 ((uint32_t)0x00004000)

Pending bit 14

Definition at line 2361 of file stm32l1xx.h.

#define EXTI_PR_PR15 ((uint32_t)0x00008000)

Pending bit 15

Definition at line 2362 of file stm32l1xx.h.

#define EXTI_PR_PR16 ((uint32_t)0x00010000)

Pending bit 16

Definition at line 2363 of file stm32l1xx.h.

#define EXTI_PR_PR17 ((uint32_t)0x00020000)

Pending bit 17

Definition at line 2364 of file stm32l1xx.h.

#define EXTI_PR_PR18 ((uint32_t)0x00040000)

Pending bit 18

Definition at line 2365 of file stm32l1xx.h.

#define EXTI_PR_PR19 ((uint32_t)0x00080000)

Pending bit 19

Definition at line 2366 of file stm32l1xx.h.

#define EXTI_PR_PR2 ((uint32_t)0x00000004)

Pending bit 2

Definition at line 2349 of file stm32l1xx.h.

#define EXTI_PR_PR20 ((uint32_t)0x00100000)

Pending bit 20

Definition at line 2367 of file stm32l1xx.h.

#define EXTI_PR_PR21 ((uint32_t)0x00200000)

Pending bit 21

Definition at line 2368 of file stm32l1xx.h.

#define EXTI_PR_PR22 ((uint32_t)0x00400000)

Pending bit 22

Definition at line 2369 of file stm32l1xx.h.

#define EXTI_PR_PR23 ((uint32_t)0x00800000)

Pending bit 23

Definition at line 2370 of file stm32l1xx.h.

#define EXTI_PR_PR3 ((uint32_t)0x00000008)

Pending bit 3

Definition at line 2350 of file stm32l1xx.h.

#define EXTI_PR_PR4 ((uint32_t)0x00000010)

Pending bit 4

Definition at line 2351 of file stm32l1xx.h.

#define EXTI_PR_PR5 ((uint32_t)0x00000020)

Pending bit 5

Definition at line 2352 of file stm32l1xx.h.

#define EXTI_PR_PR6 ((uint32_t)0x00000040)

Pending bit 6

Definition at line 2353 of file stm32l1xx.h.

#define EXTI_PR_PR7 ((uint32_t)0x00000080)

Pending bit 7

Definition at line 2354 of file stm32l1xx.h.

#define EXTI_PR_PR8 ((uint32_t)0x00000100)

Pending bit 8

Definition at line 2355 of file stm32l1xx.h.

#define EXTI_PR_PR9 ((uint32_t)0x00000200)

Pending bit 9

Definition at line 2356 of file stm32l1xx.h.

#define EXTI_RTSR_TR0 ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

Definition at line 2269 of file stm32l1xx.h.

#define EXTI_RTSR_TR1 ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

Definition at line 2270 of file stm32l1xx.h.

#define EXTI_RTSR_TR10 ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

Definition at line 2279 of file stm32l1xx.h.

#define EXTI_RTSR_TR11 ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

Definition at line 2280 of file stm32l1xx.h.

#define EXTI_RTSR_TR12 ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

Definition at line 2281 of file stm32l1xx.h.

#define EXTI_RTSR_TR13 ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

Definition at line 2282 of file stm32l1xx.h.

#define EXTI_RTSR_TR14 ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

Definition at line 2283 of file stm32l1xx.h.

#define EXTI_RTSR_TR15 ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

Definition at line 2284 of file stm32l1xx.h.

#define EXTI_RTSR_TR16 ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

Definition at line 2285 of file stm32l1xx.h.

#define EXTI_RTSR_TR17 ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

Definition at line 2286 of file stm32l1xx.h.

#define EXTI_RTSR_TR18 ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

Definition at line 2287 of file stm32l1xx.h.

#define EXTI_RTSR_TR19 ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

Definition at line 2288 of file stm32l1xx.h.

#define EXTI_RTSR_TR2 ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

Definition at line 2271 of file stm32l1xx.h.

#define EXTI_RTSR_TR20 ((uint32_t)0x00100000)

Rising trigger event configuration bit of line 20

Definition at line 2289 of file stm32l1xx.h.

#define EXTI_RTSR_TR21 ((uint32_t)0x00200000)

Rising trigger event configuration bit of line 21

Definition at line 2290 of file stm32l1xx.h.

#define EXTI_RTSR_TR22 ((uint32_t)0x00400000)

Rising trigger event configuration bit of line 22

Definition at line 2291 of file stm32l1xx.h.

#define EXTI_RTSR_TR23 ((uint32_t)0x00800000)

Rising trigger event configuration bit of line 23

Definition at line 2292 of file stm32l1xx.h.

#define EXTI_RTSR_TR3 ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

Definition at line 2272 of file stm32l1xx.h.

#define EXTI_RTSR_TR4 ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

Definition at line 2273 of file stm32l1xx.h.

#define EXTI_RTSR_TR5 ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

Definition at line 2274 of file stm32l1xx.h.

#define EXTI_RTSR_TR6 ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

Definition at line 2275 of file stm32l1xx.h.

#define EXTI_RTSR_TR7 ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

Definition at line 2276 of file stm32l1xx.h.

#define EXTI_RTSR_TR8 ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

Definition at line 2277 of file stm32l1xx.h.

#define EXTI_RTSR_TR9 ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

Definition at line 2278 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)

Software Interrupt on line 0

Definition at line 2321 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)

Software Interrupt on line 1

Definition at line 2322 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)

Software Interrupt on line 10

Definition at line 2331 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)

Software Interrupt on line 11

Definition at line 2332 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)

Software Interrupt on line 12

Definition at line 2333 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)

Software Interrupt on line 13

Definition at line 2334 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)

Software Interrupt on line 14

Definition at line 2335 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)

Software Interrupt on line 15

Definition at line 2336 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)

Software Interrupt on line 16

Definition at line 2337 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)

Software Interrupt on line 17

Definition at line 2338 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)

Software Interrupt on line 18

Definition at line 2339 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)

Software Interrupt on line 19

Definition at line 2340 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)

Software Interrupt on line 2

Definition at line 2323 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000)

Software Interrupt on line 20

Definition at line 2341 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000)

Software Interrupt on line 21

Definition at line 2342 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000)

Software Interrupt on line 22

Definition at line 2343 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000)

Software Interrupt on line 23

Definition at line 2344 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)

Software Interrupt on line 3

Definition at line 2324 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)

Software Interrupt on line 4

Definition at line 2325 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)

Software Interrupt on line 5

Definition at line 2326 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)

Software Interrupt on line 6

Definition at line 2327 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)

Software Interrupt on line 7

Definition at line 2328 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)

Software Interrupt on line 8

Definition at line 2329 of file stm32l1xx.h.

#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)

Software Interrupt on line 9

Definition at line 2330 of file stm32l1xx.h.

#define FLASH_ACR_ACC64 ((uint32_t)0x00000004)

Access 64 bits

Definition at line 2382 of file stm32l1xx.h.

Referenced by FLASH_ReadAccess64Cmd(), and SetSysClock().

#define FLASH_ACR_LATENCY ((uint32_t)0x00000001)

Latency

Definition at line 2380 of file stm32l1xx.h.

Referenced by FLASH_SetLatency(), and SetSysClock().

#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002)

Prefetch Buffer Enable

Definition at line 2381 of file stm32l1xx.h.

Referenced by FLASH_PrefetchBufferCmd(), and SetSysClock().

#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010)

Flash mode during RUN mode

Definition at line 2384 of file stm32l1xx.h.

Referenced by FLASH_RUNPowerDownCmd().

#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008)

Flash mode during sleep mode

Definition at line 2383 of file stm32l1xx.h.

Referenced by FLASH_SLEEPPowerDownCmd().

#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000)

BOR_LEV[3:0] Brown Out Reset Threshold Level

Definition at line 2426 of file stm32l1xx.h.

#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000)

IWDG_SW

Definition at line 2428 of file stm32l1xx.h.

#define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000)

BFB2

Definition at line 2431 of file stm32l1xx.h.

#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000)

nRST_STDBY

Definition at line 2430 of file stm32l1xx.h.

#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000)

nRST_STOP

Definition at line 2429 of file stm32l1xx.h.

#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA)

Read Protection

Definition at line 2425 of file stm32l1xx.h.

#define FLASH_OBR_USER ((uint32_t)0x00700000)

User Option Bytes

Definition at line 2427 of file stm32l1xx.h.

#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)

Option bytes matrix Key

Definition at line 2410 of file stm32l1xx.h.

#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF)

FLASH_PEC and data matrix Key

Definition at line 2401 of file stm32l1xx.h.

#define FLASH_PECR_DATA ((uint32_t)0x00000010)

Data matrix selection

Definition at line 2391 of file stm32l1xx.h.

Referenced by DATA_EEPROM_EraseDoubleWord(), and DATA_EEPROM_ProgramDoubleWord().

#define FLASH_PECR_EOPIE ((uint32_t)0x00010000)

End of programming interrupt

Definition at line 2396 of file stm32l1xx.h.

#define FLASH_PECR_ERASE ((uint32_t)0x00000200)

Page erasing mode

Definition at line 2393 of file stm32l1xx.h.

Referenced by DATA_EEPROM_EraseDoubleWord(), FLASH_ErasePage(), and FLASH_EraseParallelPage().

#define FLASH_PECR_ERRIE ((uint32_t)0x00020000)

Error interrupt

Definition at line 2397 of file stm32l1xx.h.

#define FLASH_PECR_FPRG ((uint32_t)0x00000400)

Fast Page/Half Page programming mode

Definition at line 2394 of file stm32l1xx.h.

Referenced by DATA_EEPROM_ProgramDoubleWord(), FLASH_ProgramHalfPage(), and FLASH_ProgramParallelHalfPage().

#define FLASH_PECR_FTDW ((uint32_t)0x00000100)

Fixed Time Data write for Word/Half Word/Byte programming

Definition at line 2392 of file stm32l1xx.h.

Referenced by DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), and DATA_EEPROM_FixedTimeProgramCmd().

#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000)

Launch the option byte loading

Definition at line 2398 of file stm32l1xx.h.

Referenced by FLASH_OB_Launch().

#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004)

Option byte matrix Lock

Definition at line 2389 of file stm32l1xx.h.

Referenced by FLASH_OB_Lock(), and FLASH_OB_Unlock().

#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000)

Parallel Bank mode

Definition at line 2395 of file stm32l1xx.h.

Referenced by FLASH_EraseParallelPage(), and FLASH_ProgramParallelHalfPage().

#define FLASH_PECR_PELOCK ((uint32_t)0x00000001)

FLASH_PECR and Flash data Lock

Definition at line 2387 of file stm32l1xx.h.

Referenced by DATA_EEPROM_Lock(), and DATA_EEPROM_Unlock().

#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002)

Program matrix Lock

Definition at line 2388 of file stm32l1xx.h.

Referenced by FLASH_Lock(), and FLASH_Unlock().

#define FLASH_PECR_PROG ((uint32_t)0x00000008)

Program matrix selection

Definition at line 2390 of file stm32l1xx.h.

Referenced by FLASH_ErasePage(), FLASH_EraseParallelPage(), FLASH_ProgramHalfPage(), and FLASH_ProgramParallelHalfPage().

#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF)

FLASH_PEC and data matrix Key

Definition at line 2404 of file stm32l1xx.h.

#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF)

Program matrix Key

Definition at line 2407 of file stm32l1xx.h.

#define FLASH_SR_BSY ((uint32_t)0x00000001)

Busy

Definition at line 2413 of file stm32l1xx.h.

#define FLASH_SR_ENHV ((uint32_t)0x00000004)

End of high voltage

Definition at line 2415 of file stm32l1xx.h.

#define FLASH_SR_EOP ((uint32_t)0x00000002)

End Of Programming

Definition at line 2414 of file stm32l1xx.h.

#define FLASH_SR_OPTVERR ((uint32_t)0x00000800)

Option validity error

Definition at line 2421 of file stm32l1xx.h.

#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000)

Option User validity error

Definition at line 2422 of file stm32l1xx.h.

#define FLASH_SR_PGAERR ((uint32_t)0x00000200)

Programming Alignment Error

Definition at line 2419 of file stm32l1xx.h.

#define FLASH_SR_READY ((uint32_t)0x00000008)

Flash ready after low power mode

Definition at line 2416 of file stm32l1xx.h.

#define FLASH_SR_SIZERR ((uint32_t)0x00000400)

Size error

Definition at line 2420 of file stm32l1xx.h.

#define FLASH_SR_WRPERR ((uint32_t)0x00000100)

Write protected error

Definition at line 2418 of file stm32l1xx.h.

#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF)

Write Protect

Definition at line 2437 of file stm32l1xx.h.

#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF)

Write Protect

Definition at line 2440 of file stm32l1xx.h.

#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)

Write Protect

Definition at line 2434 of file stm32l1xx.h.

#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 2466 of file stm32l1xx.h.

#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 2459 of file stm32l1xx.h.

#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 2467 of file stm32l1xx.h.

#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 2465 of file stm32l1xx.h.

#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 2458 of file stm32l1xx.h.

Referenced by FSMC_NORSRAMInit().

#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 2447 of file stm32l1xx.h.

Referenced by FSMC_NORSRAMCmd().

#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 2450 of file stm32l1xx.h.

#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2451 of file stm32l1xx.h.

#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2452 of file stm32l1xx.h.

#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 2448 of file stm32l1xx.h.

#define FSMC_BCR1_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 2454 of file stm32l1xx.h.

#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2455 of file stm32l1xx.h.

#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2456 of file stm32l1xx.h.

#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 2462 of file stm32l1xx.h.

#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 2464 of file stm32l1xx.h.

#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 2460 of file stm32l1xx.h.

#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 2461 of file stm32l1xx.h.

#define FSMC_BCR1_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 2463 of file stm32l1xx.h.

#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 2489 of file stm32l1xx.h.

#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 2482 of file stm32l1xx.h.

#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 2490 of file stm32l1xx.h.

#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 2488 of file stm32l1xx.h.

#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 2481 of file stm32l1xx.h.

#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 2470 of file stm32l1xx.h.

#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 2473 of file stm32l1xx.h.

#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2474 of file stm32l1xx.h.

#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2475 of file stm32l1xx.h.

#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 2471 of file stm32l1xx.h.

#define FSMC_BCR2_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 2477 of file stm32l1xx.h.

#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2478 of file stm32l1xx.h.

#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2479 of file stm32l1xx.h.

#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 2485 of file stm32l1xx.h.

#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 2487 of file stm32l1xx.h.

#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 2483 of file stm32l1xx.h.

#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 2484 of file stm32l1xx.h.

#define FSMC_BCR2_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 2486 of file stm32l1xx.h.

#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 2512 of file stm32l1xx.h.

#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 2505 of file stm32l1xx.h.

#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 2513 of file stm32l1xx.h.

#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 2511 of file stm32l1xx.h.

#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 2504 of file stm32l1xx.h.

#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 2493 of file stm32l1xx.h.

#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 2496 of file stm32l1xx.h.

#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2497 of file stm32l1xx.h.

#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2498 of file stm32l1xx.h.

#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 2494 of file stm32l1xx.h.

#define FSMC_BCR3_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 2500 of file stm32l1xx.h.

#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2501 of file stm32l1xx.h.

#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2502 of file stm32l1xx.h.

#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 2508 of file stm32l1xx.h.

#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 2510 of file stm32l1xx.h.

#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit.

Definition at line 2506 of file stm32l1xx.h.

#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 2507 of file stm32l1xx.h.

#define FSMC_BCR3_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 2509 of file stm32l1xx.h.

#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 2535 of file stm32l1xx.h.

#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 2528 of file stm32l1xx.h.

#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 2536 of file stm32l1xx.h.

#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 2534 of file stm32l1xx.h.

#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 2527 of file stm32l1xx.h.

#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 2516 of file stm32l1xx.h.

#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 2519 of file stm32l1xx.h.

#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2520 of file stm32l1xx.h.

#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2521 of file stm32l1xx.h.

#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 2517 of file stm32l1xx.h.

#define FSMC_BCR4_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 2523 of file stm32l1xx.h.

#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2524 of file stm32l1xx.h.

#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2525 of file stm32l1xx.h.

#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 2531 of file stm32l1xx.h.

#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 2533 of file stm32l1xx.h.

#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 2529 of file stm32l1xx.h.

#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 2530 of file stm32l1xx.h.

#define FSMC_BCR4_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 2532 of file stm32l1xx.h.

#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2575 of file stm32l1xx.h.

#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2576 of file stm32l1xx.h.

#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2577 of file stm32l1xx.h.

#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2545 of file stm32l1xx.h.

#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2546 of file stm32l1xx.h.

#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2547 of file stm32l1xx.h.

#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2548 of file stm32l1xx.h.

#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2549 of file stm32l1xx.h.

#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2539 of file stm32l1xx.h.

#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2540 of file stm32l1xx.h.

#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2541 of file stm32l1xx.h.

#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2542 of file stm32l1xx.h.

#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2543 of file stm32l1xx.h.

#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 2557 of file stm32l1xx.h.

#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2558 of file stm32l1xx.h.

#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2559 of file stm32l1xx.h.

#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 2560 of file stm32l1xx.h.

#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 2561 of file stm32l1xx.h.

#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2563 of file stm32l1xx.h.

#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2564 of file stm32l1xx.h.

#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2565 of file stm32l1xx.h.

#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2566 of file stm32l1xx.h.

#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2567 of file stm32l1xx.h.

#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2551 of file stm32l1xx.h.

#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2552 of file stm32l1xx.h.

#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2553 of file stm32l1xx.h.

#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2554 of file stm32l1xx.h.

#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2555 of file stm32l1xx.h.

#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2569 of file stm32l1xx.h.

#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2570 of file stm32l1xx.h.

#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2571 of file stm32l1xx.h.

#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2572 of file stm32l1xx.h.

#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2573 of file stm32l1xx.h.

#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2616 of file stm32l1xx.h.

#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2617 of file stm32l1xx.h.

#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2618 of file stm32l1xx.h.

#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2586 of file stm32l1xx.h.

#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2587 of file stm32l1xx.h.

#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2588 of file stm32l1xx.h.

#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2589 of file stm32l1xx.h.

#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2590 of file stm32l1xx.h.

#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2580 of file stm32l1xx.h.

#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2581 of file stm32l1xx.h.

#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2582 of file stm32l1xx.h.

#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2583 of file stm32l1xx.h.

#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2584 of file stm32l1xx.h.

#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 2598 of file stm32l1xx.h.

#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2599 of file stm32l1xx.h.

#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2600 of file stm32l1xx.h.

#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 2601 of file stm32l1xx.h.

#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 2602 of file stm32l1xx.h.

#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2604 of file stm32l1xx.h.

#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2605 of file stm32l1xx.h.

#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2606 of file stm32l1xx.h.

#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2607 of file stm32l1xx.h.

#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2608 of file stm32l1xx.h.

#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2592 of file stm32l1xx.h.

#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2593 of file stm32l1xx.h.

#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2594 of file stm32l1xx.h.

#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2595 of file stm32l1xx.h.

#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2596 of file stm32l1xx.h.

#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2610 of file stm32l1xx.h.

#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2611 of file stm32l1xx.h.

#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2612 of file stm32l1xx.h.

#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2613 of file stm32l1xx.h.

#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2614 of file stm32l1xx.h.

#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2657 of file stm32l1xx.h.

#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2658 of file stm32l1xx.h.

#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2659 of file stm32l1xx.h.

#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2627 of file stm32l1xx.h.

#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2628 of file stm32l1xx.h.

#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2629 of file stm32l1xx.h.

#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2630 of file stm32l1xx.h.

#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2631 of file stm32l1xx.h.

#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2621 of file stm32l1xx.h.

#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2622 of file stm32l1xx.h.

#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2623 of file stm32l1xx.h.

#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2624 of file stm32l1xx.h.

#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2625 of file stm32l1xx.h.

#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 2639 of file stm32l1xx.h.

#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2640 of file stm32l1xx.h.

#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2641 of file stm32l1xx.h.

#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 2642 of file stm32l1xx.h.

#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 2643 of file stm32l1xx.h.

#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2645 of file stm32l1xx.h.

#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2646 of file stm32l1xx.h.

#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2647 of file stm32l1xx.h.

#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2648 of file stm32l1xx.h.

#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2649 of file stm32l1xx.h.

#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2633 of file stm32l1xx.h.

#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2634 of file stm32l1xx.h.

#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2635 of file stm32l1xx.h.

#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2636 of file stm32l1xx.h.

#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2637 of file stm32l1xx.h.

#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2651 of file stm32l1xx.h.

#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2652 of file stm32l1xx.h.

#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2653 of file stm32l1xx.h.

#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2654 of file stm32l1xx.h.

#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2655 of file stm32l1xx.h.

#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2698 of file stm32l1xx.h.

#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2699 of file stm32l1xx.h.

#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2700 of file stm32l1xx.h.

#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2668 of file stm32l1xx.h.

#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2669 of file stm32l1xx.h.

#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2670 of file stm32l1xx.h.

#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2671 of file stm32l1xx.h.

#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2672 of file stm32l1xx.h.

#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2662 of file stm32l1xx.h.

#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2663 of file stm32l1xx.h.

#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2664 of file stm32l1xx.h.

#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2665 of file stm32l1xx.h.

#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2666 of file stm32l1xx.h.

#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 2680 of file stm32l1xx.h.

#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2681 of file stm32l1xx.h.

#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2682 of file stm32l1xx.h.

#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 2683 of file stm32l1xx.h.

#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 2684 of file stm32l1xx.h.

#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2686 of file stm32l1xx.h.

#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2687 of file stm32l1xx.h.

#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2688 of file stm32l1xx.h.

#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2689 of file stm32l1xx.h.

#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2690 of file stm32l1xx.h.

#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2674 of file stm32l1xx.h.

#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2675 of file stm32l1xx.h.

#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2676 of file stm32l1xx.h.

#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2677 of file stm32l1xx.h.

#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2678 of file stm32l1xx.h.

#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2692 of file stm32l1xx.h.

#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2693 of file stm32l1xx.h.

#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2694 of file stm32l1xx.h.

#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2695 of file stm32l1xx.h.

#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2696 of file stm32l1xx.h.

#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2733 of file stm32l1xx.h.

#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2734 of file stm32l1xx.h.

#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2735 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2709 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2710 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2711 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2712 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2713 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2703 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2704 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2705 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2706 of file stm32l1xx.h.

#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2707 of file stm32l1xx.h.

#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2721 of file stm32l1xx.h.

#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2722 of file stm32l1xx.h.

#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2723 of file stm32l1xx.h.

#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2724 of file stm32l1xx.h.

#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2725 of file stm32l1xx.h.

#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2715 of file stm32l1xx.h.

#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2716 of file stm32l1xx.h.

#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2717 of file stm32l1xx.h.

#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2718 of file stm32l1xx.h.

#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2719 of file stm32l1xx.h.

#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2727 of file stm32l1xx.h.

#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2728 of file stm32l1xx.h.

#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2729 of file stm32l1xx.h.

#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2730 of file stm32l1xx.h.

#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2731 of file stm32l1xx.h.

#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2768 of file stm32l1xx.h.

#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2769 of file stm32l1xx.h.

#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2770 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2744 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2745 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2746 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2747 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2748 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2738 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2739 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2740 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2741 of file stm32l1xx.h.

#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2742 of file stm32l1xx.h.

#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2756 of file stm32l1xx.h.

#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2757 of file stm32l1xx.h.

#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2758 of file stm32l1xx.h.

#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2759 of file stm32l1xx.h.

#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2760 of file stm32l1xx.h.

#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2750 of file stm32l1xx.h.

#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2751 of file stm32l1xx.h.

#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2752 of file stm32l1xx.h.

#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2753 of file stm32l1xx.h.

#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2754 of file stm32l1xx.h.

#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2762 of file stm32l1xx.h.

#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2763 of file stm32l1xx.h.

#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2764 of file stm32l1xx.h.

#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2765 of file stm32l1xx.h.

#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2766 of file stm32l1xx.h.

#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2803 of file stm32l1xx.h.

#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2804 of file stm32l1xx.h.

#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2805 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2779 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2780 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2781 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2782 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2783 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2773 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2774 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2775 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2776 of file stm32l1xx.h.

#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2777 of file stm32l1xx.h.

#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2791 of file stm32l1xx.h.

#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2792 of file stm32l1xx.h.

#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2793 of file stm32l1xx.h.

#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2794 of file stm32l1xx.h.

#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2795 of file stm32l1xx.h.

#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2785 of file stm32l1xx.h.

#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2786 of file stm32l1xx.h.

#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2787 of file stm32l1xx.h.

#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2788 of file stm32l1xx.h.

#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2789 of file stm32l1xx.h.

#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2797 of file stm32l1xx.h.

#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2798 of file stm32l1xx.h.

#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2799 of file stm32l1xx.h.

#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2800 of file stm32l1xx.h.

#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2801 of file stm32l1xx.h.

#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 2838 of file stm32l1xx.h.

#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2839 of file stm32l1xx.h.

#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2840 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 2814 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2815 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2816 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 2817 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 2818 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 2808 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2809 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2810 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 2811 of file stm32l1xx.h.

#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 2812 of file stm32l1xx.h.

#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 2826 of file stm32l1xx.h.

#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2827 of file stm32l1xx.h.

#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2828 of file stm32l1xx.h.

#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 2829 of file stm32l1xx.h.

#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 2830 of file stm32l1xx.h.

#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 2820 of file stm32l1xx.h.

#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2821 of file stm32l1xx.h.

#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2822 of file stm32l1xx.h.

#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 2823 of file stm32l1xx.h.

#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 2824 of file stm32l1xx.h.

#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 2832 of file stm32l1xx.h.

#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2833 of file stm32l1xx.h.

#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2834 of file stm32l1xx.h.

#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2835 of file stm32l1xx.h.

#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 2836 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)

Definition at line 3151 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)

Definition at line 3152 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)

Definition at line 3153 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)

Definition at line 3154 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)

Definition at line 3155 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)

Definition at line 3156 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)

Definition at line 3149 of file stm32l1xx.h.

#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)

Definition at line 3150 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)

Definition at line 3139 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)

Definition at line 3140 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)

Definition at line 3141 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)

Definition at line 3142 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)

Definition at line 3143 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)

Definition at line 3144 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)

Definition at line 3145 of file stm32l1xx.h.

#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)

Definition at line 3146 of file stm32l1xx.h.

#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)

Definition at line 3102 of file stm32l1xx.h.

#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)

Definition at line 3103 of file stm32l1xx.h.

#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)

Definition at line 3112 of file stm32l1xx.h.

#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)

Definition at line 3113 of file stm32l1xx.h.

#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)

Definition at line 3114 of file stm32l1xx.h.

#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)

Definition at line 3115 of file stm32l1xx.h.

#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)

Definition at line 3116 of file stm32l1xx.h.

#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)

Definition at line 3117 of file stm32l1xx.h.

#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)

Definition at line 3104 of file stm32l1xx.h.

#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)

Definition at line 3105 of file stm32l1xx.h.

#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)

Definition at line 3106 of file stm32l1xx.h.

#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)

Definition at line 3107 of file stm32l1xx.h.

#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)

Definition at line 3108 of file stm32l1xx.h.

#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)

Definition at line 3109 of file stm32l1xx.h.

#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)

Definition at line 3110 of file stm32l1xx.h.

#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)

Definition at line 3111 of file stm32l1xx.h.

#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)

Definition at line 3086 of file stm32l1xx.h.

#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)

Definition at line 3087 of file stm32l1xx.h.

#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)

Definition at line 3096 of file stm32l1xx.h.

#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)

Definition at line 3097 of file stm32l1xx.h.

#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)

Definition at line 3098 of file stm32l1xx.h.

#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)

Definition at line 3099 of file stm32l1xx.h.

#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)

Definition at line 3100 of file stm32l1xx.h.

#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)

Definition at line 3101 of file stm32l1xx.h.

#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)

Definition at line 3088 of file stm32l1xx.h.

#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)

Definition at line 3089 of file stm32l1xx.h.

#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)

Definition at line 3090 of file stm32l1xx.h.

#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)

Definition at line 3091 of file stm32l1xx.h.

#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)

Definition at line 3092 of file stm32l1xx.h.

#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)

Definition at line 3093 of file stm32l1xx.h.

#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)

Definition at line 3094 of file stm32l1xx.h.

#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)

Definition at line 3095 of file stm32l1xx.h.

#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)

Definition at line 3016 of file stm32l1xx.h.

#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)

Definition at line 3017 of file stm32l1xx.h.

#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)

Definition at line 3026 of file stm32l1xx.h.

#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)

Definition at line 3027 of file stm32l1xx.h.

#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)

Definition at line 3028 of file stm32l1xx.h.

#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)

Definition at line 3029 of file stm32l1xx.h.

#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)

Definition at line 3030 of file stm32l1xx.h.

#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)

Definition at line 3031 of file stm32l1xx.h.

#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)

Definition at line 3018 of file stm32l1xx.h.

#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)

Definition at line 3019 of file stm32l1xx.h.

#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)

Definition at line 3020 of file stm32l1xx.h.

#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)

Definition at line 3021 of file stm32l1xx.h.

#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)

Definition at line 3022 of file stm32l1xx.h.

#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)

Definition at line 3023 of file stm32l1xx.h.

#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)

Definition at line 3024 of file stm32l1xx.h.

#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)

Definition at line 3025 of file stm32l1xx.h.

#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)

Definition at line 3120 of file stm32l1xx.h.

#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)

Definition at line 3121 of file stm32l1xx.h.

#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)

Definition at line 3130 of file stm32l1xx.h.

#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)

Definition at line 3131 of file stm32l1xx.h.

#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)

Definition at line 3132 of file stm32l1xx.h.

#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)

Definition at line 3133 of file stm32l1xx.h.

#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)

Definition at line 3134 of file stm32l1xx.h.

#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)

Definition at line 3135 of file stm32l1xx.h.

#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)

Definition at line 3122 of file stm32l1xx.h.

#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)

Definition at line 3123 of file stm32l1xx.h.

#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)

Definition at line 3124 of file stm32l1xx.h.

#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)

Definition at line 3125 of file stm32l1xx.h.

#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)

Definition at line 3126 of file stm32l1xx.h.

#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)

Definition at line 3127 of file stm32l1xx.h.

#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)

Definition at line 3128 of file stm32l1xx.h.

#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)

Definition at line 3129 of file stm32l1xx.h.

#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)

Definition at line 3136 of file stm32l1xx.h.

#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)

Definition at line 2848 of file stm32l1xx.h.

Referenced by GPIO_Init().

#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)

Definition at line 2849 of file stm32l1xx.h.

#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)

Definition at line 2850 of file stm32l1xx.h.

#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)

Definition at line 2851 of file stm32l1xx.h.

#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)

Definition at line 2878 of file stm32l1xx.h.

#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)

Definition at line 2879 of file stm32l1xx.h.

#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)

Definition at line 2880 of file stm32l1xx.h.

#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)

Definition at line 2881 of file stm32l1xx.h.

#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)

Definition at line 2882 of file stm32l1xx.h.

#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)

Definition at line 2883 of file stm32l1xx.h.

#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)

Definition at line 2884 of file stm32l1xx.h.

#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)

Definition at line 2885 of file stm32l1xx.h.

#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)

Definition at line 2886 of file stm32l1xx.h.

#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)

Definition at line 2887 of file stm32l1xx.h.

#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)

Definition at line 2888 of file stm32l1xx.h.

#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)

Definition at line 2889 of file stm32l1xx.h.

#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)

Definition at line 2890 of file stm32l1xx.h.

#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)

Definition at line 2891 of file stm32l1xx.h.

#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)

Definition at line 2892 of file stm32l1xx.h.

#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)

Definition at line 2893 of file stm32l1xx.h.

#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)

Definition at line 2894 of file stm32l1xx.h.

#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)

Definition at line 2895 of file stm32l1xx.h.

#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)

Definition at line 2852 of file stm32l1xx.h.

#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)

Definition at line 2853 of file stm32l1xx.h.

#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)

Definition at line 2854 of file stm32l1xx.h.

#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)

Definition at line 2855 of file stm32l1xx.h.

#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)

Definition at line 2856 of file stm32l1xx.h.

#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)

Definition at line 2857 of file stm32l1xx.h.

#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)

Definition at line 2858 of file stm32l1xx.h.

#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)

Definition at line 2859 of file stm32l1xx.h.

#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)

Definition at line 2860 of file stm32l1xx.h.

#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)

Definition at line 2861 of file stm32l1xx.h.

#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)

Definition at line 2862 of file stm32l1xx.h.

#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)

Definition at line 2863 of file stm32l1xx.h.

#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)

Definition at line 2864 of file stm32l1xx.h.

#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)

Definition at line 2865 of file stm32l1xx.h.

#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)

Definition at line 2866 of file stm32l1xx.h.

#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)

Definition at line 2867 of file stm32l1xx.h.

#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)

Definition at line 2868 of file stm32l1xx.h.

#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)

Definition at line 2869 of file stm32l1xx.h.

#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)

Definition at line 2870 of file stm32l1xx.h.

#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)

Definition at line 2871 of file stm32l1xx.h.

#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)

Definition at line 2872 of file stm32l1xx.h.

#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)

Definition at line 2873 of file stm32l1xx.h.

#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)

Definition at line 2874 of file stm32l1xx.h.

#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)

Definition at line 2875 of file stm32l1xx.h.

#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)

Definition at line 2876 of file stm32l1xx.h.

#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)

Definition at line 2877 of file stm32l1xx.h.

#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)

Definition at line 3051 of file stm32l1xx.h.

#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)

Definition at line 3052 of file stm32l1xx.h.

#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)

Definition at line 3061 of file stm32l1xx.h.

#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)

Definition at line 3062 of file stm32l1xx.h.

#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)

Definition at line 3063 of file stm32l1xx.h.

#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)

Definition at line 3064 of file stm32l1xx.h.

#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)

Definition at line 3065 of file stm32l1xx.h.

#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)

Definition at line 3066 of file stm32l1xx.h.

#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)

Definition at line 3053 of file stm32l1xx.h.

#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)

Definition at line 3054 of file stm32l1xx.h.

#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)

Definition at line 3055 of file stm32l1xx.h.

#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)

Definition at line 3056 of file stm32l1xx.h.

#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)

Definition at line 3057 of file stm32l1xx.h.

#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)

Definition at line 3058 of file stm32l1xx.h.

#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)

Definition at line 3059 of file stm32l1xx.h.

#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)

Definition at line 3060 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)

Definition at line 2916 of file stm32l1xx.h.

Referenced by GPIO_Init().

#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)

Definition at line 2917 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)

Definition at line 2918 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)

Definition at line 2919 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)

Definition at line 2946 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)

Definition at line 2947 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)

Definition at line 2948 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)

Definition at line 2949 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)

Definition at line 2950 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)

Definition at line 2951 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)

Definition at line 2952 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)

Definition at line 2953 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)

Definition at line 2954 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)

Definition at line 2955 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)

Definition at line 2956 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)

Definition at line 2957 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)

Definition at line 2958 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)

Definition at line 2959 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)

Definition at line 2960 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)

Definition at line 2961 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)

Definition at line 2962 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)

Definition at line 2963 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)

Definition at line 2920 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)

Definition at line 2921 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)

Definition at line 2922 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)

Definition at line 2923 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)

Definition at line 2924 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)

Definition at line 2925 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)

Definition at line 2926 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)

Definition at line 2927 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)

Definition at line 2928 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)

Definition at line 2929 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)

Definition at line 2930 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)

Definition at line 2931 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)

Definition at line 2932 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)

Definition at line 2933 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)

Definition at line 2934 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)

Definition at line 2935 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)

Definition at line 2936 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)

Definition at line 2937 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)

Definition at line 2938 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)

Definition at line 2939 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)

Definition at line 2940 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)

Definition at line 2941 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)

Definition at line 2942 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)

Definition at line 2943 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)

Definition at line 2944 of file stm32l1xx.h.

#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)

Definition at line 2945 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0

Definition at line 3033 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1

Definition at line 3034 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10

Definition at line 3043 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11

Definition at line 3044 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12

Definition at line 3045 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13

Definition at line 3046 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14

Definition at line 3047 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15

Definition at line 3048 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2

Definition at line 3035 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3

Definition at line 3036 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4

Definition at line 3037 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5

Definition at line 3038 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6

Definition at line 3039 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7

Definition at line 3040 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8

Definition at line 3041 of file stm32l1xx.h.

#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9

Definition at line 3042 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0

Definition at line 3068 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1

Definition at line 3069 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10

Definition at line 3078 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11

Definition at line 3079 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12

Definition at line 3080 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13

Definition at line 3081 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14

Definition at line 3082 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15

Definition at line 3083 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2

Definition at line 3070 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3

Definition at line 3071 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4

Definition at line 3072 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5

Definition at line 3073 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6

Definition at line 3074 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7

Definition at line 3075 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8

Definition at line 3076 of file stm32l1xx.h.

#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9

Definition at line 3077 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)

Definition at line 2898 of file stm32l1xx.h.

Referenced by GPIO_Init().

#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)

Definition at line 2899 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)

Definition at line 2908 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)

Definition at line 2909 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)

Definition at line 2910 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)

Definition at line 2911 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)

Definition at line 2912 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)

Definition at line 2913 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)

Definition at line 2900 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)

Definition at line 2901 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)

Definition at line 2902 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)

Definition at line 2903 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)

Definition at line 2904 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)

Definition at line 2905 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)

Definition at line 2906 of file stm32l1xx.h.

#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)

Definition at line 2907 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)

Definition at line 2966 of file stm32l1xx.h.

Referenced by GPIO_Init().

#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)

Definition at line 2967 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)

Definition at line 2968 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)

Definition at line 2969 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)

Definition at line 2996 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)

Definition at line 2997 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)

Definition at line 2998 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)

Definition at line 2999 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)

Definition at line 3000 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)

Definition at line 3001 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)

Definition at line 3002 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)

Definition at line 3003 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)

Definition at line 3004 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)

Definition at line 3005 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)

Definition at line 3006 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)

Definition at line 3007 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)

Definition at line 3008 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)

Definition at line 3009 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)

Definition at line 3010 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)

Definition at line 3011 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)

Definition at line 3012 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)

Definition at line 3013 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)

Definition at line 2970 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)

Definition at line 2971 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)

Definition at line 2972 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)

Definition at line 2973 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)

Definition at line 2974 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)

Definition at line 2975 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)

Definition at line 2976 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)

Definition at line 2977 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)

Definition at line 2978 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)

Definition at line 2979 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)

Definition at line 2980 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)

Definition at line 2981 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)

Definition at line 2982 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)

Definition at line 2983 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)

Definition at line 2984 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)

Definition at line 2985 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)

Definition at line 2986 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)

Definition at line 2987 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)

Definition at line 2988 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)

Definition at line 2989 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)

Definition at line 2990 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)

Definition at line 2991 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)

Definition at line 2992 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)

Definition at line 2993 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)

Definition at line 2994 of file stm32l1xx.h.

#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)

Definition at line 2995 of file stm32l1xx.h.

#define I2C_CCR_CCR ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

Definition at line 3246 of file stm32l1xx.h.

Referenced by I2C_Init().

#define I2C_CCR_DUTY ((uint16_t)0x4000)

Fast Mode Duty Cycle

Definition at line 3247 of file stm32l1xx.h.

#define I2C_CCR_FS ((uint16_t)0x8000)

I2C Master Mode Selection

Definition at line 3248 of file stm32l1xx.h.

Referenced by I2C_Init().

#define I2C_CR1_ACK ((uint16_t)0x0400)

Acknowledge Enable

Definition at line 3174 of file stm32l1xx.h.

Referenced by I2C_AcknowledgeConfig().

#define I2C_CR1_ALERT ((uint16_t)0x2000)

SMBus Alert

Definition at line 3177 of file stm32l1xx.h.

#define I2C_CR1_ENARP ((uint16_t)0x0010)

ARP Enable

Definition at line 3168 of file stm32l1xx.h.

Referenced by I2C_ARPCmd().

#define I2C_CR1_ENGC ((uint16_t)0x0040)

General Call Enable

Definition at line 3170 of file stm32l1xx.h.

Referenced by I2C_GeneralCallCmd().

#define I2C_CR1_ENPEC ((uint16_t)0x0020)

PEC Enable

Definition at line 3169 of file stm32l1xx.h.

Referenced by I2C_CalculatePEC().

#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

Definition at line 3171 of file stm32l1xx.h.

Referenced by I2C_StretchClockCmd().

#define I2C_CR1_PE ((uint16_t)0x0001)

Peripheral Enable

Definition at line 3165 of file stm32l1xx.h.

Referenced by I2C_Cmd(), and I2C_Init().

#define I2C_CR1_PEC ((uint16_t)0x1000)

Packet Error Checking

Definition at line 3176 of file stm32l1xx.h.

Referenced by I2C_TransmitPEC().

#define I2C_CR1_POS ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

Definition at line 3175 of file stm32l1xx.h.

#define I2C_CR1_SMBTYPE ((uint16_t)0x0008)

SMBus Type

Definition at line 3167 of file stm32l1xx.h.

#define I2C_CR1_SMBUS ((uint16_t)0x0002)

SMBus Mode

Definition at line 3166 of file stm32l1xx.h.

#define I2C_CR1_START ((uint16_t)0x0100)

Start Generation

Definition at line 3172 of file stm32l1xx.h.

Referenced by I2C_GenerateSTART().

#define I2C_CR1_STOP ((uint16_t)0x0200)

Stop Generation

Definition at line 3173 of file stm32l1xx.h.

Referenced by I2C_GenerateSTOP().

#define I2C_CR1_SWRST ((uint16_t)0x8000)

Software Reset

Definition at line 3178 of file stm32l1xx.h.

Referenced by I2C_SoftwareResetCmd().

#define I2C_CR2_DMAEN ((uint16_t)0x0800)

DMA Requests Enable

Definition at line 3192 of file stm32l1xx.h.

Referenced by I2C_DMACmd().

#define I2C_CR2_FREQ ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

Definition at line 3181 of file stm32l1xx.h.

Referenced by I2C_Init().

#define I2C_CR2_FREQ_0 ((uint16_t)0x0001)

Bit 0

Definition at line 3182 of file stm32l1xx.h.

#define I2C_CR2_FREQ_1 ((uint16_t)0x0002)

Bit 1

Definition at line 3183 of file stm32l1xx.h.

#define I2C_CR2_FREQ_2 ((uint16_t)0x0004)

Bit 2

Definition at line 3184 of file stm32l1xx.h.

#define I2C_CR2_FREQ_3 ((uint16_t)0x0008)

Bit 3

Definition at line 3185 of file stm32l1xx.h.

#define I2C_CR2_FREQ_4 ((uint16_t)0x0010)

Bit 4

Definition at line 3186 of file stm32l1xx.h.

#define I2C_CR2_FREQ_5 ((uint16_t)0x0020)

Bit 5

Definition at line 3187 of file stm32l1xx.h.

#define I2C_CR2_ITBUFEN ((uint16_t)0x0400)

Buffer Interrupt Enable

Definition at line 3191 of file stm32l1xx.h.

#define I2C_CR2_ITERREN ((uint16_t)0x0100)

Error Interrupt Enable

Definition at line 3189 of file stm32l1xx.h.

#define I2C_CR2_ITEVTEN ((uint16_t)0x0200)

Event Interrupt Enable

Definition at line 3190 of file stm32l1xx.h.

#define I2C_CR2_LAST ((uint16_t)0x1000)

DMA Last Transfer

Definition at line 3193 of file stm32l1xx.h.

Referenced by I2C_DMALastTransferCmd().

#define I2C_DR_DR ((uint8_t)0xFF)

8-bit Data Register

Definition at line 3217 of file stm32l1xx.h.

#define I2C_OAR1_ADD0 ((uint16_t)0x0001)

Bit 0

Definition at line 3199 of file stm32l1xx.h.

Referenced by I2C_Send7bitAddress().

#define I2C_OAR1_ADD1 ((uint16_t)0x0002)

Bit 1

Definition at line 3200 of file stm32l1xx.h.

#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)

Interface Address

Definition at line 3196 of file stm32l1xx.h.

#define I2C_OAR1_ADD2 ((uint16_t)0x0004)

Bit 2

Definition at line 3201 of file stm32l1xx.h.

#define I2C_OAR1_ADD3 ((uint16_t)0x0008)

Bit 3

Definition at line 3202 of file stm32l1xx.h.

#define I2C_OAR1_ADD4 ((uint16_t)0x0010)

Bit 4

Definition at line 3203 of file stm32l1xx.h.

#define I2C_OAR1_ADD5 ((uint16_t)0x0020)

Bit 5

Definition at line 3204 of file stm32l1xx.h.

#define I2C_OAR1_ADD6 ((uint16_t)0x0040)

Bit 6

Definition at line 3205 of file stm32l1xx.h.

#define I2C_OAR1_ADD7 ((uint16_t)0x0080)

Bit 7

Definition at line 3206 of file stm32l1xx.h.

#define I2C_OAR1_ADD8 ((uint16_t)0x0100)

Bit 8

Definition at line 3207 of file stm32l1xx.h.

#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300)

Interface Address

Definition at line 3197 of file stm32l1xx.h.

#define I2C_OAR1_ADD9 ((uint16_t)0x0200)

Bit 9

Definition at line 3208 of file stm32l1xx.h.

#define I2C_OAR1_ADDMODE ((uint16_t)0x8000)

Addressing Mode (Slave mode)

Definition at line 3210 of file stm32l1xx.h.

#define I2C_OAR2_ADD2 ((uint8_t)0xFE)

Interface address

Definition at line 3214 of file stm32l1xx.h.

Referenced by I2C_OwnAddress2Config().

#define I2C_OAR2_ENDUAL ((uint8_t)0x01)

Dual addressing mode enable

Definition at line 3213 of file stm32l1xx.h.

Referenced by I2C_DualAddressCmd().

#define I2C_SR1_ADD10 ((uint16_t)0x0008)

10-bit header sent (Master mode)

Definition at line 3223 of file stm32l1xx.h.

#define I2C_SR1_ADDR ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

Definition at line 3221 of file stm32l1xx.h.

#define I2C_SR1_AF ((uint16_t)0x0400)

Acknowledge Failure

Definition at line 3229 of file stm32l1xx.h.

#define I2C_SR1_ARLO ((uint16_t)0x0200)

Arbitration Lost (master mode)

Definition at line 3228 of file stm32l1xx.h.

#define I2C_SR1_BERR ((uint16_t)0x0100)

Bus Error

Definition at line 3227 of file stm32l1xx.h.

#define I2C_SR1_BTF ((uint16_t)0x0004)

Byte Transfer Finished

Definition at line 3222 of file stm32l1xx.h.

#define I2C_SR1_OVR ((uint16_t)0x0800)

Overrun/Underrun

Definition at line 3230 of file stm32l1xx.h.

#define I2C_SR1_PECERR ((uint16_t)0x1000)

PEC Error in reception

Definition at line 3231 of file stm32l1xx.h.

#define I2C_SR1_RXNE ((uint16_t)0x0040)

Data Register not Empty (receivers)

Definition at line 3225 of file stm32l1xx.h.

#define I2C_SR1_SB ((uint16_t)0x0001)

Start Bit (Master mode)

Definition at line 3220 of file stm32l1xx.h.

#define I2C_SR1_SMBALERT ((uint16_t)0x8000)

SMBus Alert

Definition at line 3233 of file stm32l1xx.h.

#define I2C_SR1_STOPF ((uint16_t)0x0010)

Stop detection (Slave mode)

Definition at line 3224 of file stm32l1xx.h.

#define I2C_SR1_TIMEOUT ((uint16_t)0x4000)

Timeout or Tlow Error

Definition at line 3232 of file stm32l1xx.h.

#define I2C_SR1_TXE ((uint16_t)0x0080)

Data Register Empty (transmitters)

Definition at line 3226 of file stm32l1xx.h.

#define I2C_SR2_BUSY ((uint16_t)0x0002)

Bus Busy

Definition at line 3237 of file stm32l1xx.h.

#define I2C_SR2_DUALF ((uint16_t)0x0080)

Dual Flag (Slave mode)

Definition at line 3242 of file stm32l1xx.h.

#define I2C_SR2_GENCALL ((uint16_t)0x0010)

General Call Address (Slave mode)

Definition at line 3239 of file stm32l1xx.h.

#define I2C_SR2_MSL ((uint16_t)0x0001)

Master/Slave

Definition at line 3236 of file stm32l1xx.h.

#define I2C_SR2_PEC ((uint16_t)0xFF00)

Packet Error Checking Register

Definition at line 3243 of file stm32l1xx.h.

#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

Definition at line 3240 of file stm32l1xx.h.

#define I2C_SR2_SMBHOST ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

Definition at line 3241 of file stm32l1xx.h.

#define I2C_SR2_TRA ((uint16_t)0x0004)

Transmitter/Receiver

Definition at line 3238 of file stm32l1xx.h.

#define I2C_TRISE_TRISE ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

Definition at line 3251 of file stm32l1xx.h.

#define IWDG_KR_KEY ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

Definition at line 3260 of file stm32l1xx.h.

#define IWDG_PR_PR ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

Definition at line 3263 of file stm32l1xx.h.

#define IWDG_PR_PR_0 ((uint8_t)0x01)

Bit 0

Definition at line 3264 of file stm32l1xx.h.

#define IWDG_PR_PR_1 ((uint8_t)0x02)

Bit 1

Definition at line 3265 of file stm32l1xx.h.

#define IWDG_PR_PR_2 ((uint8_t)0x04)

Bit 2

Definition at line 3266 of file stm32l1xx.h.

#define IWDG_RLR_RL ((uint16_t)0x0FFF)

Watchdog counter reload value

Definition at line 3269 of file stm32l1xx.h.

#define IWDG_SR_PVU ((uint8_t)0x01)

Watchdog prescaler value update

Definition at line 3272 of file stm32l1xx.h.

#define IWDG_SR_RVU ((uint8_t)0x02)

Watchdog counter reload value update

Definition at line 3273 of file stm32l1xx.h.

#define LCD_CLR_SOFC ((uint32_t)0x00000002)

Start Of Frame Flag Clear Bit

Definition at line 3337 of file stm32l1xx.h.

#define LCD_CLR_UDDC ((uint32_t)0x00000008)

Update Display Done Flag Clear Bit

Definition at line 3338 of file stm32l1xx.h.

#define LCD_CR_BIAS ((uint32_t)0x00000060)

BIAS[1:0] bits (Bias selector)

Definition at line 3290 of file stm32l1xx.h.

#define LCD_CR_BIAS_0 ((uint32_t)0x00000020)

Bias selector Bit 0

Definition at line 3291 of file stm32l1xx.h.

#define LCD_CR_BIAS_1 ((uint32_t)0x00000040)

Bias selector Bit 1

Definition at line 3292 of file stm32l1xx.h.

#define LCD_CR_DUTY ((uint32_t)0x0000001C)

DUTY[2:0] bits (Duty selector)

Definition at line 3285 of file stm32l1xx.h.

#define LCD_CR_DUTY_0 ((uint32_t)0x00000004)

Duty selector Bit 0

Definition at line 3286 of file stm32l1xx.h.

#define LCD_CR_DUTY_1 ((uint32_t)0x00000008)

Duty selector Bit 1

Definition at line 3287 of file stm32l1xx.h.

#define LCD_CR_DUTY_2 ((uint32_t)0x00000010)

Duty selector Bit 2

Definition at line 3288 of file stm32l1xx.h.

#define LCD_CR_LCDEN ((uint32_t)0x00000001)

LCD Enable Bit

Definition at line 3282 of file stm32l1xx.h.

#define LCD_CR_MUX_SEG ((uint32_t)0x00000080)

Mux Segment Enable Bit

Definition at line 3294 of file stm32l1xx.h.

#define LCD_CR_VSEL ((uint32_t)0x00000002)

Voltage source selector Bit

Definition at line 3283 of file stm32l1xx.h.

#define LCD_FCR_BLINK ((uint32_t)0x00030000)

BLINK[1:0] bits (Blink Enable)

Definition at line 3321 of file stm32l1xx.h.

#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 3322 of file stm32l1xx.h.

#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 3323 of file stm32l1xx.h.

#define LCD_FCR_BLINKF ((uint32_t)0x0000E000)

BLINKF[2:0] bits (Blink Frequency)

Definition at line 3316 of file stm32l1xx.h.

#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 3317 of file stm32l1xx.h.

#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 3318 of file stm32l1xx.h.

#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 3319 of file stm32l1xx.h.

#define LCD_FCR_CC ((uint32_t)0x00001C00)

CC[2:0] bits (Contrast Control)

Definition at line 3311 of file stm32l1xx.h.

#define LCD_FCR_CC_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 3312 of file stm32l1xx.h.

#define LCD_FCR_CC_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 3313 of file stm32l1xx.h.

#define LCD_FCR_CC_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 3314 of file stm32l1xx.h.

#define LCD_FCR_DEAD ((uint32_t)0x00000380)

DEAD[2:0] bits (DEAD Time)

Definition at line 3306 of file stm32l1xx.h.

#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080)

Bit 0

Definition at line 3307 of file stm32l1xx.h.

#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100)

Bit 1

Definition at line 3308 of file stm32l1xx.h.

#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200)

Bit 2

Definition at line 3309 of file stm32l1xx.h.

#define LCD_FCR_DIV ((uint32_t)0x003C0000)

DIV[3:0] bits (Divider)

Definition at line 3325 of file stm32l1xx.h.

#define LCD_FCR_HD ((uint32_t)0x00000001)

High Drive Enable Bit

Definition at line 3297 of file stm32l1xx.h.

#define LCD_FCR_PON ((uint32_t)0x00000070)

PON[2:0] bits (Puls ON Duration)

Definition at line 3301 of file stm32l1xx.h.

#define LCD_FCR_PON_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 3302 of file stm32l1xx.h.

#define LCD_FCR_PON_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 3303 of file stm32l1xx.h.

#define LCD_FCR_PON_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 3304 of file stm32l1xx.h.

#define LCD_FCR_PS ((uint32_t)0x03C00000)

PS[3:0] bits (Prescaler)

Definition at line 3326 of file stm32l1xx.h.

#define LCD_FCR_SOFIE ((uint32_t)0x00000002)

Start of Frame Interrupt Enable Bit

Definition at line 3298 of file stm32l1xx.h.

#define LCD_FCR_UDDIE ((uint32_t)0x00000008)

Update Display Done Interrupt Enable Bit

Definition at line 3299 of file stm32l1xx.h.

#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF)

Segment Data Bits

Definition at line 3341 of file stm32l1xx.h.

#define LCD_SR_ENS ((uint32_t)0x00000001)

LCD Enabled Bit

Definition at line 3329 of file stm32l1xx.h.

#define LCD_SR_FCRSR ((uint32_t)0x00000020)

LCD FCR Register Synchronization Flag Bit

Definition at line 3334 of file stm32l1xx.h.

#define LCD_SR_RDY ((uint32_t)0x00000010)

Ready Flag Bit

Definition at line 3333 of file stm32l1xx.h.

#define LCD_SR_SOF ((uint32_t)0x00000002)

Start Of Frame Flag Bit

Definition at line 3330 of file stm32l1xx.h.

#define LCD_SR_UDD ((uint32_t)0x00000008)

Update Display Done Flag Bit

Definition at line 3332 of file stm32l1xx.h.

#define LCD_SR_UDR ((uint32_t)0x00000004)

Update Display Request Bit

Definition at line 3331 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)

Interrupt active flags

Definition at line 6095 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)

bit 0

Definition at line 6096 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)

bit 1

Definition at line 6097 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)

bit 10

Definition at line 6106 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)

bit 11

Definition at line 6107 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)

bit 12

Definition at line 6108 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)

bit 13

Definition at line 6109 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)

bit 14

Definition at line 6110 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)

bit 15

Definition at line 6111 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)

bit 16

Definition at line 6112 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)

bit 17

Definition at line 6113 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)

bit 18

Definition at line 6114 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)

bit 19

Definition at line 6115 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)

bit 2

Definition at line 6098 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)

bit 20

Definition at line 6116 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)

bit 21

Definition at line 6117 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)

bit 22

Definition at line 6118 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)

bit 23

Definition at line 6119 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)

bit 24

Definition at line 6120 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)

bit 25

Definition at line 6121 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)

bit 26

Definition at line 6122 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)

bit 27

Definition at line 6123 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)

bit 28

Definition at line 6124 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)

bit 29

Definition at line 6125 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)

bit 3

Definition at line 6099 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)

bit 30

Definition at line 6126 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)

bit 31

Definition at line 6127 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)

bit 4

Definition at line 6100 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)

bit 5

Definition at line 6101 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)

bit 6

Definition at line 6102 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)

bit 7

Definition at line 6103 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)

bit 8

Definition at line 6104 of file stm32l1xx.h.

#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)

bit 9

Definition at line 6105 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)

Interrupt clear-enable bits

Definition at line 5990 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)

bit 0

Definition at line 5991 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)

bit 1

Definition at line 5992 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)

bit 10

Definition at line 6001 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)

bit 11

Definition at line 6002 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)

bit 12

Definition at line 6003 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)

bit 13

Definition at line 6004 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)

bit 14

Definition at line 6005 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)

bit 15

Definition at line 6006 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)

bit 16

Definition at line 6007 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)

bit 17

Definition at line 6008 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)

bit 18

Definition at line 6009 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)

bit 19

Definition at line 6010 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)

bit 2

Definition at line 5993 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)

bit 20

Definition at line 6011 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)

bit 21

Definition at line 6012 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)

bit 22

Definition at line 6013 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)

bit 23

Definition at line 6014 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)

bit 24

Definition at line 6015 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)

bit 25

Definition at line 6016 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)

bit 26

Definition at line 6017 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)

bit 27

Definition at line 6018 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)

bit 28

Definition at line 6019 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)

bit 29

Definition at line 6020 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)

bit 3

Definition at line 5994 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)

bit 30

Definition at line 6021 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)

bit 31

Definition at line 6022 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)

bit 4

Definition at line 5995 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)

bit 5

Definition at line 5996 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)

bit 6

Definition at line 5997 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)

bit 7

Definition at line 5998 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)

bit 8

Definition at line 5999 of file stm32l1xx.h.

#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)

bit 9

Definition at line 6000 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)

Interrupt clear-pending bits

Definition at line 6060 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)

bit 0

Definition at line 6061 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)

bit 1

Definition at line 6062 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)

bit 10

Definition at line 6071 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)

bit 11

Definition at line 6072 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)

bit 12

Definition at line 6073 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)

bit 13

Definition at line 6074 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)

bit 14

Definition at line 6075 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)

bit 15

Definition at line 6076 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)

bit 16

Definition at line 6077 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)

bit 17

Definition at line 6078 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)

bit 18

Definition at line 6079 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)

bit 19

Definition at line 6080 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)

bit 2

Definition at line 6063 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)

bit 20

Definition at line 6081 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)

bit 21

Definition at line 6082 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)

bit 22

Definition at line 6083 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)

bit 23

Definition at line 6084 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)

bit 24

Definition at line 6085 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)

bit 25

Definition at line 6086 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)

bit 26

Definition at line 6087 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)

bit 27

Definition at line 6088 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)

bit 28

Definition at line 6089 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)

bit 29

Definition at line 6090 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)

bit 3

Definition at line 6064 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)

bit 30

Definition at line 6091 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)

bit 31

Definition at line 6092 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)

bit 4

Definition at line 6065 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)

bit 5

Definition at line 6066 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)

bit 6

Definition at line 6067 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)

bit 7

Definition at line 6068 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)

bit 8

Definition at line 6069 of file stm32l1xx.h.

#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)

bit 9

Definition at line 6070 of file stm32l1xx.h.

#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)

Priority of interrupt 0

Definition at line 6130 of file stm32l1xx.h.

#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)

Priority of interrupt 1

Definition at line 6131 of file stm32l1xx.h.

#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)

Priority of interrupt 2

Definition at line 6132 of file stm32l1xx.h.

#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)

Priority of interrupt 3

Definition at line 6133 of file stm32l1xx.h.

#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)

Priority of interrupt 4

Definition at line 6136 of file stm32l1xx.h.

#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)

Priority of interrupt 5

Definition at line 6137 of file stm32l1xx.h.

#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)

Priority of interrupt 6

Definition at line 6138 of file stm32l1xx.h.

#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)

Priority of interrupt 7

Definition at line 6139 of file stm32l1xx.h.

#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)

Priority of interrupt 10

Definition at line 6144 of file stm32l1xx.h.

#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)

Priority of interrupt 11

Definition at line 6145 of file stm32l1xx.h.

#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)

Priority of interrupt 8

Definition at line 6142 of file stm32l1xx.h.

#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)

Priority of interrupt 9

Definition at line 6143 of file stm32l1xx.h.

#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)

Priority of interrupt 12

Definition at line 6148 of file stm32l1xx.h.

#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)

Priority of interrupt 13

Definition at line 6149 of file stm32l1xx.h.

#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)

Priority of interrupt 14

Definition at line 6150 of file stm32l1xx.h.

#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)

Priority of interrupt 15

Definition at line 6151 of file stm32l1xx.h.

#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)

Priority of interrupt 16

Definition at line 6154 of file stm32l1xx.h.

#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)

Priority of interrupt 17

Definition at line 6155 of file stm32l1xx.h.

#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)

Priority of interrupt 18

Definition at line 6156 of file stm32l1xx.h.

#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)

Priority of interrupt 19

Definition at line 6157 of file stm32l1xx.h.

#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)

Priority of interrupt 20

Definition at line 6160 of file stm32l1xx.h.

#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)

Priority of interrupt 21

Definition at line 6161 of file stm32l1xx.h.

#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)

Priority of interrupt 22

Definition at line 6162 of file stm32l1xx.h.

#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)

Priority of interrupt 23

Definition at line 6163 of file stm32l1xx.h.

#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)

Priority of interrupt 24

Definition at line 6166 of file stm32l1xx.h.

#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)

Priority of interrupt 25

Definition at line 6167 of file stm32l1xx.h.

#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)

Priority of interrupt 26

Definition at line 6168 of file stm32l1xx.h.

#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)

Priority of interrupt 27

Definition at line 6169 of file stm32l1xx.h.

#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)

Priority of interrupt 28

Definition at line 6172 of file stm32l1xx.h.

#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)

Priority of interrupt 29

Definition at line 6173 of file stm32l1xx.h.

#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)

Priority of interrupt 30

Definition at line 6174 of file stm32l1xx.h.

#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)

Priority of interrupt 31

Definition at line 6175 of file stm32l1xx.h.

#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)

Interrupt set enable bits

Definition at line 5955 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)

bit 0

Definition at line 5956 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)

bit 1

Definition at line 5957 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)

bit 10

Definition at line 5966 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)

bit 11

Definition at line 5967 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)

bit 12

Definition at line 5968 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)

bit 13

Definition at line 5969 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)

bit 14

Definition at line 5970 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)

bit 15

Definition at line 5971 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)

bit 16

Definition at line 5972 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)

bit 17

Definition at line 5973 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)

bit 18

Definition at line 5974 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)

bit 19

Definition at line 5975 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)

bit 2

Definition at line 5958 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)

bit 20

Definition at line 5976 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)

bit 21

Definition at line 5977 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)

bit 22

Definition at line 5978 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)

bit 23

Definition at line 5979 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)

bit 24

Definition at line 5980 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)

bit 25

Definition at line 5981 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)

bit 26

Definition at line 5982 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)

bit 27

Definition at line 5983 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)

bit 28

Definition at line 5984 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)

bit 29

Definition at line 5985 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)

bit 3

Definition at line 5959 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)

bit 30

Definition at line 5986 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)

bit 31

Definition at line 5987 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)

bit 4

Definition at line 5960 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)

bit 5

Definition at line 5961 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)

bit 6

Definition at line 5962 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)

bit 7

Definition at line 5963 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)

bit 8

Definition at line 5964 of file stm32l1xx.h.

#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)

bit 9

Definition at line 5965 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)

Interrupt set-pending bits

Definition at line 6025 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)

bit 0

Definition at line 6026 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)

bit 1

Definition at line 6027 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)

bit 10

Definition at line 6036 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)

bit 11

Definition at line 6037 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)

bit 12

Definition at line 6038 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)

bit 13

Definition at line 6039 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)

bit 14

Definition at line 6040 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)

bit 15

Definition at line 6041 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)

bit 16

Definition at line 6042 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)

bit 17

Definition at line 6043 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)

bit 18

Definition at line 6044 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)

bit 19

Definition at line 6045 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)

bit 2

Definition at line 6028 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)

bit 20

Definition at line 6046 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)

bit 21

Definition at line 6047 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)

bit 22

Definition at line 6048 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)

bit 23

Definition at line 6049 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)

bit 24

Definition at line 6050 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)

bit 25

Definition at line 6051 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)

bit 26

Definition at line 6052 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)

bit 27

Definition at line 6053 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)

bit 28

Definition at line 6054 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)

bit 29

Definition at line 6055 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)

bit 3

Definition at line 6029 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)

bit 30

Definition at line 6056 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)

bit 31

Definition at line 6057 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)

bit 4

Definition at line 6030 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)

bit 5

Definition at line 6031 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)

bit 6

Definition at line 6032 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)

bit 7

Definition at line 6033 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)

bit 8

Definition at line 6034 of file stm32l1xx.h.

#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)

bit 9

Definition at line 6035 of file stm32l1xx.h.

#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000)

Switch ANA Enable for OPAMP1

Definition at line 1725 of file stm32l1xx.h.

#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000)

Switch ANA Enable for OPAMP2

Definition at line 1726 of file stm32l1xx.h.

#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000)

Switch ANA Enable for OPAMP3

Definition at line 1727 of file stm32l1xx.h.

#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000)

Power range selection

Definition at line 1729 of file stm32l1xx.h.

Referenced by OPAMP_PowerRangeSelect().

#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040)

OPAMP1 Offset calibration for N differential pair

Definition at line 1707 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020)

OPAMP1 Offset calibration for P differential pair

Definition at line 1706 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000)

OPAMP1 calibration output

Definition at line 1730 of file stm32l1xx.h.

Referenced by OPAMP_GetFlagStatus().

#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080)

OPAMP1 Low power enable

Definition at line 1708 of file stm32l1xx.h.

#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001)

OPAMP1 disable

Definition at line 1701 of file stm32l1xx.h.

#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000)

OPAMP2 Offset calibration for N differential pair

Definition at line 1715 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000)

OPAMP2 Offset calibration for P differential pair

Definition at line 1714 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000)

OPAMP2 calibration output

Definition at line 1731 of file stm32l1xx.h.

Referenced by OPAMP_GetFlagStatus().

#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000)

OPAMP2 Low power enable

Definition at line 1716 of file stm32l1xx.h.

#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100)

OPAMP2 disable

Definition at line 1709 of file stm32l1xx.h.

#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000)

OPAMP3 Offset calibration for N differential pair

Definition at line 1723 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000)

OPAMP3 Offset calibration for P differential pair

Definition at line 1722 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000)

OPAMP3 calibration output

Definition at line 1732 of file stm32l1xx.h.

Referenced by OPAMP_GetFlagStatus().

#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000)

OPAMP3 Low power enable

Definition at line 1724 of file stm32l1xx.h.

#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000)

OPAMP3 disable

Definition at line 1717 of file stm32l1xx.h.

#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002)

Switch 3 for OPAMP1 Enable

Definition at line 1702 of file stm32l1xx.h.

#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200)

Switch 3 for OPAMP2 Enable

Definition at line 1710 of file stm32l1xx.h.

#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000)

Switch 3 for OPAMP3 Enable

Definition at line 1718 of file stm32l1xx.h.

#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004)

Switch 4 for OPAMP1 Enable

Definition at line 1703 of file stm32l1xx.h.

#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400)

Switch 4 for OPAMP2 Enable

Definition at line 1711 of file stm32l1xx.h.

#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000)

Switch 4 for OPAMP3 Enable

Definition at line 1719 of file stm32l1xx.h.

#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008)

Switch 5 for OPAMP1 Enable

Definition at line 1704 of file stm32l1xx.h.

#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800)

Switch 5 for OPAMP2 Enable

Definition at line 1712 of file stm32l1xx.h.

#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000)

Switch 5 for OPAMP3 Enable

Definition at line 1720 of file stm32l1xx.h.

#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010)

Switch 6 for OPAMP1 Enable

Definition at line 1705 of file stm32l1xx.h.

#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000)

Switch 6 for OPAMP2 Enable

Definition at line 1713 of file stm32l1xx.h.

#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000)

Switch 6 for OPAMP3 Enable

Definition at line 1721 of file stm32l1xx.h.

#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000)

Switch 7 for OPAMP2 Enable

Definition at line 1728 of file stm32l1xx.h.

#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF)

Offset trim in low power for OPAMP1

Definition at line 1741 of file stm32l1xx.h.

#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00)

Offset trim in low power for OPAMP2

Definition at line 1742 of file stm32l1xx.h.

#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000)

Offset trim in low power for OPAMP3

Definition at line 1743 of file stm32l1xx.h.

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF)

Offset trim for OPAMP1

Definition at line 1735 of file stm32l1xx.h.

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00)

Offset trim for OPAMP2

Definition at line 1736 of file stm32l1xx.h.

#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000)

Offset trim for OPAMP2

Definition at line 1737 of file stm32l1xx.h.

#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000)

Switch to OPAMP offset user trimmed values

Definition at line 1738 of file stm32l1xx.h.

Referenced by OPAMP_OffsetTrimmingModeSelect().

#define PWR_CR_CSBF ((uint16_t)0x0008)

Clear Standby Flag

Definition at line 3353 of file stm32l1xx.h.

#define PWR_CR_CWUF ((uint16_t)0x0004)

Clear Wakeup Flag

Definition at line 3352 of file stm32l1xx.h.

Referenced by PWR_EnterSTANDBYMode().

#define PWR_CR_DBP ((uint16_t)0x0100)

Disable Backup Domain write protection

Definition at line 3371 of file stm32l1xx.h.

#define PWR_CR_FWU ((uint16_t)0x0400)

Fast wakeup

Definition at line 3373 of file stm32l1xx.h.

#define PWR_CR_LPRUN ((uint16_t)0x4000)

Low power run mode

Definition at line 3378 of file stm32l1xx.h.

Referenced by PWR_EnterLowPowerRunMode().

#define PWR_CR_LPSDSR ((uint16_t)0x0001)

Low-power deepsleep/sleep/low power run

Definition at line 3350 of file stm32l1xx.h.

Referenced by PWR_EnterLowPowerRunMode().

#define PWR_CR_PDDS ((uint16_t)0x0002)

Power Down Deepsleep

Definition at line 3351 of file stm32l1xx.h.

Referenced by PWR_EnterSTANDBYMode().

#define PWR_CR_PLS ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

Definition at line 3356 of file stm32l1xx.h.

#define PWR_CR_PLS_0 ((uint16_t)0x0020)

Bit 0

Definition at line 3357 of file stm32l1xx.h.

#define PWR_CR_PLS_1 ((uint16_t)0x0040)

Bit 1

Definition at line 3358 of file stm32l1xx.h.

#define PWR_CR_PLS_2 ((uint16_t)0x0080)

Bit 2 PVD level configuration

Definition at line 3359 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000)

PVD level 0

Definition at line 3362 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020)

PVD level 1

Definition at line 3363 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040)

PVD level 2

Definition at line 3364 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060)

PVD level 3

Definition at line 3365 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080)

PVD level 4

Definition at line 3366 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0)

PVD level 5

Definition at line 3367 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0)

PVD level 6

Definition at line 3368 of file stm32l1xx.h.

#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0)

PVD level 7

Definition at line 3369 of file stm32l1xx.h.

#define PWR_CR_PVDE ((uint16_t)0x0010)

Power Voltage Detector Enable

Definition at line 3354 of file stm32l1xx.h.

#define PWR_CR_ULP ((uint16_t)0x0200)

Ultra Low Power mode

Definition at line 3372 of file stm32l1xx.h.

#define PWR_CR_VOS ((uint16_t)0x1800)

VOS[1:0] bits (Voltage scaling range selection)

Definition at line 3375 of file stm32l1xx.h.

#define PWR_CR_VOS_0 ((uint16_t)0x0800)

Bit 0

Definition at line 3376 of file stm32l1xx.h.

Referenced by SetSysClock().

#define PWR_CR_VOS_1 ((uint16_t)0x1000)

Bit 1

Definition at line 3377 of file stm32l1xx.h.

#define PWR_CSR_EWUP1 ((uint16_t)0x0100)

Enable WKUP pin 1

Definition at line 3388 of file stm32l1xx.h.

#define PWR_CSR_EWUP2 ((uint16_t)0x0200)

Enable WKUP pin 2

Definition at line 3389 of file stm32l1xx.h.

#define PWR_CSR_EWUP3 ((uint16_t)0x0400)

Enable WKUP pin 3

Definition at line 3390 of file stm32l1xx.h.

#define PWR_CSR_PVDO ((uint16_t)0x0004)

PVD Output

Definition at line 3383 of file stm32l1xx.h.

#define PWR_CSR_REGLPF ((uint16_t)0x0020)

Regulator LP flag

Definition at line 3386 of file stm32l1xx.h.

#define PWR_CSR_SBF ((uint16_t)0x0002)

Standby Flag

Definition at line 3382 of file stm32l1xx.h.

#define PWR_CSR_VOSF ((uint16_t)0x0010)

Voltage Scaling select flag

Definition at line 3385 of file stm32l1xx.h.

Referenced by SetSysClock().

#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008)

Internal voltage reference (VREFINT) ready flag

Definition at line 3384 of file stm32l1xx.h.

#define PWR_CSR_WUF ((uint16_t)0x0001)

Wakeup Flag

Definition at line 3381 of file stm32l1xx.h.

#define RCC_AHBENR_AESEN ((uint32_t)0x08000000)

AES clock enable

Definition at line 3647 of file stm32l1xx.h.

#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000)

CRC clock enable

Definition at line 3642 of file stm32l1xx.h.

#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000)

DMA1 clock enable

Definition at line 3645 of file stm32l1xx.h.

#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000)

DMA2 clock enable

Definition at line 3646 of file stm32l1xx.h.

#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000)

FLITF clock enable (has effect only when the Flash memory is in power down mode)

Definition at line 3643 of file stm32l1xx.h.

#define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000)

FSMC clock enable

Definition at line 3648 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001)

GPIO port A clock enable

Definition at line 3634 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002)

GPIO port B clock enable

Definition at line 3635 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004)

GPIO port C clock enable

Definition at line 3636 of file stm32l1xx.h.

#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008)

GPIO port D clock enable

Definition at line 3637 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010)

GPIO port E clock enable

Definition at line 3638 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040)

GPIO port F clock enable

Definition at line 3640 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080)

GPIO port G clock enable

Definition at line 3641 of file stm32l1xx.h.

#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020)

GPIO port H clock enable

Definition at line 3639 of file stm32l1xx.h.

#define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000)

AES clock enabled in sleep mode

Definition at line 3700 of file stm32l1xx.h.

#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000)

CRC clock enabled in sleep mode

Definition at line 3693 of file stm32l1xx.h.

#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000)

DMA1 clock enabled in sleep mode

Definition at line 3698 of file stm32l1xx.h.

#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000)

DMA2 clock enabled in sleep mode

Definition at line 3699 of file stm32l1xx.h.

#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000)

Flash Interface clock enabled in sleep mode (has effect only when the Flash memory is in power down mode)

Definition at line 3694 of file stm32l1xx.h.

#define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000)

FSMC clock enabled in sleep mode

Definition at line 3701 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001)

GPIO port A clock enabled in sleep mode

Definition at line 3685 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002)

GPIO port B clock enabled in sleep mode

Definition at line 3686 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004)

GPIO port C clock enabled in sleep mode

Definition at line 3687 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008)

GPIO port D clock enabled in sleep mode

Definition at line 3688 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010)

GPIO port E clock enabled in sleep mode

Definition at line 3689 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040)

GPIO port F clock enabled in sleep mode

Definition at line 3691 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080)

GPIO port G clock enabled in sleep mode

Definition at line 3692 of file stm32l1xx.h.

#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020)

GPIO port H clock enabled in sleep mode

Definition at line 3690 of file stm32l1xx.h.

#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000)

SRAM clock enabled in sleep mode

Definition at line 3697 of file stm32l1xx.h.

#define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000)

AES reset

Definition at line 3598 of file stm32l1xx.h.

#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000)

CRC reset

Definition at line 3594 of file stm32l1xx.h.

#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000)

DMA1 reset

Definition at line 3596 of file stm32l1xx.h.

#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000)

DMA2 reset

Definition at line 3597 of file stm32l1xx.h.

#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000)

FLITF reset

Definition at line 3595 of file stm32l1xx.h.

#define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000)

FSMC reset

Definition at line 3599 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001)

GPIO port A reset

Definition at line 3586 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002)

GPIO port B reset

Definition at line 3587 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004)

GPIO port C reset

Definition at line 3588 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008)

GPIO port D reset

Definition at line 3589 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010)

GPIO port E reset

Definition at line 3590 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040)

GPIO port F reset

Definition at line 3592 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080)

GPIO port G reset

Definition at line 3593 of file stm32l1xx.h.

#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020)

GPIO port H reset

Definition at line 3591 of file stm32l1xx.h.

#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000)

Comparator interface clock enable

Definition at line 3682 of file stm32l1xx.h.

#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)

DAC interface clock enable

Definition at line 3681 of file stm32l1xx.h.

#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)

I2C 1 clock enable

Definition at line 3677 of file stm32l1xx.h.

#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)

I2C 2 clock enable

Definition at line 3678 of file stm32l1xx.h.

#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200)

LCD clock enable

Definition at line 3669 of file stm32l1xx.h.

#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)

Power interface clock enable

Definition at line 3680 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)

SPI 2 clock enable

Definition at line 3671 of file stm32l1xx.h.

#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)

SPI 3 clock enable

Definition at line 3672 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)

Timer 2 clock enabled

Definition at line 3663 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)

Timer 3 clock enable

Definition at line 3664 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)

Timer 4 clock enable

Definition at line 3665 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)

Timer 5 clock enable

Definition at line 3666 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)

Timer 6 clock enable

Definition at line 3667 of file stm32l1xx.h.

#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)

Timer 7 clock enable

Definition at line 3668 of file stm32l1xx.h.

#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)

UART 4 clock enable

Definition at line 3675 of file stm32l1xx.h.

#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)

UART 5 clock enable

Definition at line 3676 of file stm32l1xx.h.

#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)

USART 2 clock enable

Definition at line 3673 of file stm32l1xx.h.

#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)

USART 3 clock enable

Definition at line 3674 of file stm32l1xx.h.

#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000)

USB clock enable

Definition at line 3679 of file stm32l1xx.h.

#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)

Window Watchdog clock enable

Definition at line 3670 of file stm32l1xx.h.

#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000)

Comparator interface clock enabled in sleep mode

Definition at line 3733 of file stm32l1xx.h.

#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)

DAC interface clock enabled in sleep mode

Definition at line 3732 of file stm32l1xx.h.

#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)

I2C 1 clock enabled in sleep mode

Definition at line 3728 of file stm32l1xx.h.

#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)

I2C 2 clock enabled in sleep mode

Definition at line 3729 of file stm32l1xx.h.

#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200)

LCD clock enabled in sleep mode

Definition at line 3720 of file stm32l1xx.h.

#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)

Power interface clock enabled in sleep mode

Definition at line 3731 of file stm32l1xx.h.

#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)

SPI 2 clock enabled in sleep mode

Definition at line 3722 of file stm32l1xx.h.

#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)

SPI 3 clock enabled in sleep mode

Definition at line 3723 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)

Timer 2 clock enabled in sleep mode

Definition at line 3714 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)

Timer 3 clock enabled in sleep mode

Definition at line 3715 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)

Timer 4 clock enabled in sleep mode

Definition at line 3716 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)

Timer 5 clock enabled in sleep mode

Definition at line 3717 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)

Timer 6 clock enabled in sleep mode

Definition at line 3718 of file stm32l1xx.h.

#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)

Timer 7 clock enabled in sleep mode

Definition at line 3719 of file stm32l1xx.h.

#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)

UART 4 clock enabled in sleep mode

Definition at line 3726 of file stm32l1xx.h.

#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)

UART 5 clock enabled in sleep mode

Definition at line 3727 of file stm32l1xx.h.

#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)

USART 2 clock enabled in sleep mode

Definition at line 3724 of file stm32l1xx.h.

#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)

USART 3 clock enabled in sleep mode

Definition at line 3725 of file stm32l1xx.h.

#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000)

USB clock enabled in sleep mode

Definition at line 3730 of file stm32l1xx.h.

#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)

Window Watchdog clock enabled in sleep mode

Definition at line 3721 of file stm32l1xx.h.

#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000)

Comparator interface reset

Definition at line 3631 of file stm32l1xx.h.

#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)

DAC interface reset

Definition at line 3630 of file stm32l1xx.h.

#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)

I2C 1 reset

Definition at line 3626 of file stm32l1xx.h.

#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)

I2C 2 reset

Definition at line 3627 of file stm32l1xx.h.

#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200)

LCD reset

Definition at line 3618 of file stm32l1xx.h.

#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)

Power interface reset

Definition at line 3629 of file stm32l1xx.h.

#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)

SPI 2 reset

Definition at line 3620 of file stm32l1xx.h.

#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)

SPI 3 reset

Definition at line 3621 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)

Timer 2 reset

Definition at line 3612 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)

Timer 3 reset

Definition at line 3613 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)

Timer 4 reset

Definition at line 3614 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)

Timer 5 reset

Definition at line 3615 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)

Timer 6 reset

Definition at line 3616 of file stm32l1xx.h.

#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)

Timer 7 reset

Definition at line 3617 of file stm32l1xx.h.

#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)

UART 4 reset

Definition at line 3624 of file stm32l1xx.h.

#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)

UART 5 reset

Definition at line 3625 of file stm32l1xx.h.

#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)

USART 2 reset

Definition at line 3622 of file stm32l1xx.h.

#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)

USART 3 reset

Definition at line 3623 of file stm32l1xx.h.

#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)

USB reset

Definition at line 3628 of file stm32l1xx.h.

#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)

Window Watchdog reset

Definition at line 3619 of file stm32l1xx.h.

#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)

ADC1 clock enable

Definition at line 3656 of file stm32l1xx.h.

#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)

SDIO clock enable

Definition at line 3657 of file stm32l1xx.h.

#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)

SPI1 clock enable

Definition at line 3658 of file stm32l1xx.h.

#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001)

System Configuration SYSCFG clock enable

Definition at line 3652 of file stm32l1xx.h.

#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008)

TIM10 interface clock enable

Definition at line 3654 of file stm32l1xx.h.

#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010)

TIM11 Timer clock enable

Definition at line 3655 of file stm32l1xx.h.

#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004)

TIM9 interface clock enable

Definition at line 3653 of file stm32l1xx.h.

#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)

USART1 clock enable

Definition at line 3659 of file stm32l1xx.h.

#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200)

ADC1 clock enabled in sleep mode

Definition at line 3708 of file stm32l1xx.h.

#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)

SDIO clock enabled in sleep mode

Definition at line 3709 of file stm32l1xx.h.

#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)

SPI1 clock enabled in sleep mode

Definition at line 3710 of file stm32l1xx.h.

#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001)

System Configuration SYSCFG clock enabled in sleep mode

Definition at line 3704 of file stm32l1xx.h.

#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008)

TIM10 interface clock enabled in sleep mode

Definition at line 3706 of file stm32l1xx.h.

#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010)

TIM11 Timer clock enabled in sleep mode

Definition at line 3707 of file stm32l1xx.h.

#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004)

TIM9 interface clock enabled in sleep mode

Definition at line 3705 of file stm32l1xx.h.

#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000)

USART1 clock enabled in sleep mode

Definition at line 3711 of file stm32l1xx.h.

#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)

ADC1 reset

Definition at line 3606 of file stm32l1xx.h.

#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)

SDIO reset

Definition at line 3607 of file stm32l1xx.h.

#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)

SPI1 reset

Definition at line 3608 of file stm32l1xx.h.

#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001)

System Configuration SYSCFG reset

Definition at line 3602 of file stm32l1xx.h.

#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008)

TIM10 reset

Definition at line 3604 of file stm32l1xx.h.

#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010)

TIM11 reset

Definition at line 3605 of file stm32l1xx.h.

#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004)

TIM9 reset

Definition at line 3603 of file stm32l1xx.h.

#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)

USART1 reset

Definition at line 3609 of file stm32l1xx.h.

#define RCC_CFGR_HPRE ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

Definition at line 3452 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), RCC_HCLKConfig(), and SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 3453 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 3454 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 3455 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)

Bit 3 HPRE configuration

Definition at line 3456 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)

SYSCLK not divided

Definition at line 3459 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)

SYSCLK divided by 128

Definition at line 3465 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)

SYSCLK divided by 16

Definition at line 3463 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)

SYSCLK divided by 2

Definition at line 3460 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)

SYSCLK divided by 256

Definition at line 3466 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)

SYSCLK divided by 4

Definition at line 3461 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)

SYSCLK divided by 512

Definition at line 3467 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)

SYSCLK divided by 64

Definition at line 3464 of file stm32l1xx.h.

#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)

SYSCLK divided by 8

Definition at line 3462 of file stm32l1xx.h.

#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000)

MCO Clock divided by 1

Definition at line 3551 of file stm32l1xx.h.

#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000)

MCO Clock divided by 16 ****************** Bit definition for RCC_CIR register

Definition at line 3555 of file stm32l1xx.h.

#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000)

MCO Clock divided by 2

Definition at line 3552 of file stm32l1xx.h.

#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000)

MCO Clock divided by 4

Definition at line 3553 of file stm32l1xx.h.

#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000)

MCO Clock divided by 8

Definition at line 3554 of file stm32l1xx.h.

#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000)

External 1-25 MHz oscillator clock selected

Definition at line 3540 of file stm32l1xx.h.

#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000)

Internal 16 MHz RC oscillator clock selected

Definition at line 3538 of file stm32l1xx.h.

#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000)

LSE selected

Definition at line 3543 of file stm32l1xx.h.

#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000)

LSI selected

Definition at line 3542 of file stm32l1xx.h.

#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000)

Internal Medium Speed RC oscillator clock selected

Definition at line 3539 of file stm32l1xx.h.

#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)

No clock

Definition at line 3536 of file stm32l1xx.h.

#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000)

PLL clock divided

Definition at line 3541 of file stm32l1xx.h.

#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000)

System clock selected

Definition at line 3537 of file stm32l1xx.h.

#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000)

MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler)

Definition at line 3545 of file stm32l1xx.h.

#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 3546 of file stm32l1xx.h.

#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 3547 of file stm32l1xx.h.

#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000)

Bit 2 MCO Prescaler configuration

Definition at line 3548 of file stm32l1xx.h.

#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000)

MCO[2:0] bits (Microcontroller Clock Output)

Definition at line 3530 of file stm32l1xx.h.

#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 3531 of file stm32l1xx.h.

#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 3532 of file stm32l1xx.h.

#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000)

Bit 2 MCO configuration

Definition at line 3533 of file stm32l1xx.h.

#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000)

PLLDIV[1:0] bits (PLL Output Division)

Definition at line 3518 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), SetSysClock(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000)

PLL clock output = CKVCO / 1

Definition at line 3524 of file stm32l1xx.h.

#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000)

PLL clock output = CKVCO / 2

Definition at line 3525 of file stm32l1xx.h.

#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000)

PLL clock output = CKVCO / 3

Definition at line 3526 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000)

PLL clock output = CKVCO / 4

Definition at line 3527 of file stm32l1xx.h.

#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000)

Bit0

Definition at line 3519 of file stm32l1xx.h.

#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000)

Bit1 PLLDIV configuration

Definition at line 3520 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000)

PLLMUL[3:0] bits (PLL multiplication factor)

Definition at line 3500 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), SetSysClock(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000)

PLL input clock * 12

Definition at line 3511 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000)

PLL input clock * 16

Definition at line 3512 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000)

PLL input clock * 24

Definition at line 3513 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000)

PLL input clock * 3

Definition at line 3507 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000)

PLL input clock * 32

Definition at line 3514 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000)

PLL input clock * 4

Definition at line 3508 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000)

PLL input clock * 48 PLLDIV configuration

Definition at line 3515 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000)

PLL input clock * 6

Definition at line 3509 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000)

PLL input clock * 8

Definition at line 3510 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 3501 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 3502 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 3503 of file stm32l1xx.h.

#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000)

Bit 3 PLLMUL configuration

Definition at line 3504 of file stm32l1xx.h.

#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000)

PLL entry clock source

Definition at line 3494 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), SetSysClock(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)

HSE as PLL entry clock source

Definition at line 3497 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000)

HSI as PLL entry clock source

Definition at line 3496 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700)

PRE1[2:0] bits (APB1 prescaler)

Definition at line 3469 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), and RCC_PCLK1Config().

#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 3470 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 3471 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)

Bit 2 PPRE1 configuration

Definition at line 3472 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)

HCLK not divided

Definition at line 3475 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)

HCLK divided by 16

Definition at line 3479 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)

HCLK divided by 2

Definition at line 3476 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)

HCLK divided by 4

Definition at line 3477 of file stm32l1xx.h.

#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)

HCLK divided by 8

Definition at line 3478 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800)

PRE2[2:0] bits (APB2 prescaler)

Definition at line 3481 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), and RCC_PCLK2Config().

#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)

Bit 0

Definition at line 3482 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)

Bit 1

Definition at line 3483 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)

Bit 2 PPRE2 configuration

Definition at line 3484 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)

HCLK not divided

Definition at line 3487 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)

HCLK divided by 16 PLL entry clock source

Definition at line 3491 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)

HCLK divided by 2

Definition at line 3488 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)

HCLK divided by 4

Definition at line 3489 of file stm32l1xx.h.

#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)

HCLK divided by 8

Definition at line 3490 of file stm32l1xx.h.

#define RCC_CFGR_SW ((uint32_t)0x00000003)

SW[1:0] bits (System clock Switch)

Definition at line 3432 of file stm32l1xx.h.

Referenced by RCC_SYSCLKConfig(), and SetSysClock().

#define RCC_CFGR_SW_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3433 of file stm32l1xx.h.

#define RCC_CFGR_SW_1 ((uint32_t)0x00000002)

Bit 1 SW configuration

Definition at line 3434 of file stm32l1xx.h.

#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002)

HSE selected as system clock

Definition at line 3439 of file stm32l1xx.h.

#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001)

HSI selected as system clock

Definition at line 3438 of file stm32l1xx.h.

#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000)

MSI selected as system clock

Definition at line 3437 of file stm32l1xx.h.

#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003)

PLL selected as system clock

Definition at line 3440 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CFGR_SWS ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

Definition at line 3442 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), RCC_GetSYSCLKSource(), SetSysClock(), and SystemCoreClockUpdate().

#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 3443 of file stm32l1xx.h.

#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)

Bit 1 SWS configuration

Definition at line 3444 of file stm32l1xx.h.

#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008)

HSE oscillator used as system clock

Definition at line 3449 of file stm32l1xx.h.

#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004)

HSI oscillator used as system clock

Definition at line 3448 of file stm32l1xx.h.

#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000)

MSI oscillator used as system clock

Definition at line 3447 of file stm32l1xx.h.

#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C)

PLL used as system clock

Definition at line 3450 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CIR_CSSC ((uint32_t)0x00800000)

Clock Security System Interrupt Clear

Definition at line 3582 of file stm32l1xx.h.

#define RCC_CIR_CSSF ((uint32_t)0x00000080)

Clock Security System Interrupt flag

Definition at line 3565 of file stm32l1xx.h.

#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)

HSE Ready Interrupt Clear

Definition at line 3578 of file stm32l1xx.h.

#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)

HSE Ready Interrupt flag

Definition at line 3561 of file stm32l1xx.h.

#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)

HSE Ready Interrupt Enable

Definition at line 3570 of file stm32l1xx.h.

#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)

HSI Ready Interrupt Clear

Definition at line 3577 of file stm32l1xx.h.

#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)

HSI Ready Interrupt flag

Definition at line 3560 of file stm32l1xx.h.

#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)

HSI Ready Interrupt Enable

Definition at line 3569 of file stm32l1xx.h.

#define RCC_CIR_LSECSS ((uint32_t)0x00000040)

LSE CSS Interrupt flag

Definition at line 3564 of file stm32l1xx.h.

#define RCC_CIR_LSECSSC ((uint32_t)0x00400000)

LSE CSS Interrupt Clear

Definition at line 3581 of file stm32l1xx.h.

#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000)

LSE CSS Interrupt Enable

Definition at line 3573 of file stm32l1xx.h.

#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)

LSE Ready Interrupt Clear

Definition at line 3576 of file stm32l1xx.h.

#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)

LSE Ready Interrupt flag

Definition at line 3559 of file stm32l1xx.h.

#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)

LSE Ready Interrupt Enable

Definition at line 3568 of file stm32l1xx.h.

#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)

LSI Ready Interrupt Clear

Definition at line 3575 of file stm32l1xx.h.

#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)

LSI Ready Interrupt flag

Definition at line 3558 of file stm32l1xx.h.

#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)

LSI Ready Interrupt Enable

Definition at line 3567 of file stm32l1xx.h.

#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000)

MSI Ready Interrupt Clear

Definition at line 3580 of file stm32l1xx.h.

#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020)

MSI Ready Interrupt flag

Definition at line 3563 of file stm32l1xx.h.

#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000)

MSI Ready Interrupt Enable

Definition at line 3572 of file stm32l1xx.h.

#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)

PLL Ready Interrupt Clear

Definition at line 3579 of file stm32l1xx.h.

#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)

PLL Ready Interrupt flag

Definition at line 3562 of file stm32l1xx.h.

#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)

PLL Ready Interrupt Enable

Definition at line 3571 of file stm32l1xx.h.

#define RCC_CR_CSSON ((uint32_t)0x10000000)

Clock Security System enable

Definition at line 3410 of file stm32l1xx.h.

#define RCC_CR_HSEBYP ((uint32_t)0x00040000)

External High Speed clock Bypass

Definition at line 3406 of file stm32l1xx.h.

#define RCC_CR_HSEON ((uint32_t)0x00010000)

External High Speed clock enable

Definition at line 3404 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CR_HSERDY ((uint32_t)0x00020000)

External High Speed clock ready flag

Definition at line 3405 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CR_HSION ((uint32_t)0x00000001)

Internal High Speed clock enable

Definition at line 3398 of file stm32l1xx.h.

#define RCC_CR_HSIRDY ((uint32_t)0x00000002)

Internal High Speed clock ready flag

Definition at line 3399 of file stm32l1xx.h.

#define RCC_CR_MSION ((uint32_t)0x00000100)

Internal Multi Speed clock enable

Definition at line 3401 of file stm32l1xx.h.

#define RCC_CR_MSIRDY ((uint32_t)0x00000200)

Internal Multi Speed clock ready flag

Definition at line 3402 of file stm32l1xx.h.

#define RCC_CR_PLLON ((uint32_t)0x01000000)

PLL enable

Definition at line 3408 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CR_PLLRDY ((uint32_t)0x02000000)

PLL clock ready flag

Definition at line 3409 of file stm32l1xx.h.

Referenced by SetSysClock().

#define RCC_CR_RTCPRE ((uint32_t)0x60000000)

RTC/LCD Prescaler

Definition at line 3412 of file stm32l1xx.h.

Referenced by RCC_RTCCLKConfig().

#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000)

Bit0

Definition at line 3413 of file stm32l1xx.h.

#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000)

Bit1

Definition at line 3414 of file stm32l1xx.h.

#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)

Independent Watchdog reset flag

Definition at line 3763 of file stm32l1xx.h.

#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

Low-Power reset flag

Definition at line 3765 of file stm32l1xx.h.

#define RCC_CSR_LSEBYP ((uint32_t)0x00000400)

External Low Speed oscillator Bypass

Definition at line 3741 of file stm32l1xx.h.

#define RCC_CSR_LSECSSD ((uint32_t)0x00001000)

External Low Speed oscillator CSS Detected

Definition at line 3743 of file stm32l1xx.h.

#define RCC_CSR_LSECSSON ((uint32_t)0x00000800)

External Low Speed oscillator CSS Enable

Definition at line 3742 of file stm32l1xx.h.

#define RCC_CSR_LSEON ((uint32_t)0x00000100)

External Low Speed oscillator enable

Definition at line 3739 of file stm32l1xx.h.

#define RCC_CSR_LSERDY ((uint32_t)0x00000200)

External Low Speed oscillator Ready

Definition at line 3740 of file stm32l1xx.h.

#define RCC_CSR_LSION ((uint32_t)0x00000001)

Internal Low Speed oscillator enable

Definition at line 3736 of file stm32l1xx.h.

#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)

Internal Low Speed oscillator Ready

Definition at line 3737 of file stm32l1xx.h.

#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000)

Option Bytes Loader reset flag

Definition at line 3759 of file stm32l1xx.h.

#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)

PIN reset flag

Definition at line 3760 of file stm32l1xx.h.

#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)

POR/PDR reset flag

Definition at line 3761 of file stm32l1xx.h.

#define RCC_CSR_RMVF ((uint32_t)0x01000000)

Remove reset flag

Definition at line 3758 of file stm32l1xx.h.

Referenced by RCC_ClearFlag().

#define RCC_CSR_RTCEN ((uint32_t)0x00400000)

RTC clock enable

Definition at line 3755 of file stm32l1xx.h.

#define RCC_CSR_RTCRST ((uint32_t)0x00800000)

RTC reset

Definition at line 3756 of file stm32l1xx.h.

#define RCC_CSR_RTCSEL ((uint32_t)0x00030000)

RTCSEL[1:0] bits (RTC clock source selection)

Definition at line 3745 of file stm32l1xx.h.

Referenced by RCC_RTCCLKConfig().

#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 3746 of file stm32l1xx.h.

#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000)

Bit 1 RTC congiguration

Definition at line 3747 of file stm32l1xx.h.

#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000)

HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock

Definition at line 3753 of file stm32l1xx.h.

Referenced by RCC_RTCCLKConfig().

#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000)

LSE oscillator clock used as RTC clock

Definition at line 3751 of file stm32l1xx.h.

#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000)

LSI oscillator clock used as RTC clock

Definition at line 3752 of file stm32l1xx.h.

#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)

No clock

Definition at line 3750 of file stm32l1xx.h.

#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)

Software Reset flag

Definition at line 3762 of file stm32l1xx.h.

#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)

Window watchdog reset flag

Definition at line 3764 of file stm32l1xx.h.

#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF)

Internal High Speed clock Calibration

Definition at line 3417 of file stm32l1xx.h.

#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00)

Internal High Speed clock trimming

Definition at line 3418 of file stm32l1xx.h.

Referenced by RCC_AdjustHSICalibrationValue().

#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000)

Internal Multi Speed clock Calibration

Definition at line 3428 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000)

Internal Multi Speed clock Range

Definition at line 3420 of file stm32l1xx.h.

Referenced by RCC_GetClocksFreq(), RCC_MSIRangeConfig(), and SystemCoreClockUpdate().

#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000)

Internal Multi Speed clock Range 65.536 KHz

Definition at line 3421 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000)

Internal Multi Speed clock Range 131.072 KHz

Definition at line 3422 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000)

Internal Multi Speed clock Range 262.144 KHz

Definition at line 3423 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000)

Internal Multi Speed clock Range 524.288 KHz

Definition at line 3424 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000)

Internal Multi Speed clock Range 1.048 MHz

Definition at line 3425 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000)

Internal Multi Speed clock Range 2.097 MHz

Definition at line 3426 of file stm32l1xx.h.

#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000)

Internal Multi Speed clock Range 4.194 MHz

Definition at line 3427 of file stm32l1xx.h.

#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000)

Internal Multi Speed clock trimming

Definition at line 3429 of file stm32l1xx.h.

#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF)

AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits)

Definition at line 4689 of file stm32l1xx.h.

#define RI_ASCR1_CH_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4690 of file stm32l1xx.h.

#define RI_ASCR1_CH_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4691 of file stm32l1xx.h.

#define RI_ASCR1_CH_10 ((uint32_t)0x00000400)

Bit 10

Definition at line 4700 of file stm32l1xx.h.

#define RI_ASCR1_CH_11 ((uint32_t)0x00000800)

Bit 11

Definition at line 4701 of file stm32l1xx.h.

#define RI_ASCR1_CH_12 ((uint32_t)0x00001000)

Bit 12

Definition at line 4702 of file stm32l1xx.h.

#define RI_ASCR1_CH_13 ((uint32_t)0x00002000)

Bit 13

Definition at line 4703 of file stm32l1xx.h.

#define RI_ASCR1_CH_14 ((uint32_t)0x00004000)

Bit 14

Definition at line 4704 of file stm32l1xx.h.

#define RI_ASCR1_CH_15 ((uint32_t)0x00008000)

Bit 15

Definition at line 4705 of file stm32l1xx.h.

#define RI_ASCR1_CH_18 ((uint32_t)0x00040000)

Bit 18

Definition at line 4707 of file stm32l1xx.h.

#define RI_ASCR1_CH_19 ((uint32_t)0x00080000)

Bit 19

Definition at line 4708 of file stm32l1xx.h.

#define RI_ASCR1_CH_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4692 of file stm32l1xx.h.

#define RI_ASCR1_CH_20 ((uint32_t)0x00100000)

Bit 20

Definition at line 4709 of file stm32l1xx.h.

#define RI_ASCR1_CH_21 ((uint32_t)0x00200000)

Bit 21

Definition at line 4710 of file stm32l1xx.h.

#define RI_ASCR1_CH_22 ((uint32_t)0x00400000)

Bit 22

Definition at line 4711 of file stm32l1xx.h.

#define RI_ASCR1_CH_23 ((uint32_t)0x00800000)

Bit 23

Definition at line 4712 of file stm32l1xx.h.

#define RI_ASCR1_CH_24 ((uint32_t)0x01000000)

Bit 24

Definition at line 4713 of file stm32l1xx.h.

#define RI_ASCR1_CH_25 ((uint32_t)0x02000000)

Bit 25

Definition at line 4714 of file stm32l1xx.h.

#define RI_ASCR1_CH_27 ((uint32_t)0x00400000)

Bit 27

Definition at line 4716 of file stm32l1xx.h.

#define RI_ASCR1_CH_28 ((uint32_t)0x00800000)

Bit 28

Definition at line 4717 of file stm32l1xx.h.

#define RI_ASCR1_CH_29 ((uint32_t)0x01000000)

Bit 29

Definition at line 4718 of file stm32l1xx.h.

#define RI_ASCR1_CH_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4693 of file stm32l1xx.h.

#define RI_ASCR1_CH_30 ((uint32_t)0x02000000)

Bit 30

Definition at line 4719 of file stm32l1xx.h.

#define RI_ASCR1_CH_31 ((uint32_t)0x00010000)

Bit 16

Definition at line 4706 of file stm32l1xx.h.

#define RI_ASCR1_CH_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4694 of file stm32l1xx.h.

#define RI_ASCR1_CH_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 4695 of file stm32l1xx.h.

#define RI_ASCR1_CH_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 4696 of file stm32l1xx.h.

#define RI_ASCR1_CH_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 4697 of file stm32l1xx.h.

#define RI_ASCR1_CH_8 ((uint32_t)0x00000100)

Bit 8

Definition at line 4698 of file stm32l1xx.h.

#define RI_ASCR1_CH_9 ((uint32_t)0x00000200)

Bit 9

Definition at line 4699 of file stm32l1xx.h.

#define RI_ASCR1_SCM ((uint32_t)0x80000000)

I/O Switch control mode

Definition at line 4720 of file stm32l1xx.h.

Referenced by SYSCFG_RISwitchControlModeCmd().

#define RI_ASCR1_VCOMP ((uint32_t)0x04000000)

ADC analog switch selection for internal node to COMP1

Definition at line 4715 of file stm32l1xx.h.

#define RI_ASCR2_CH0b ((uint32_t)0x00010000)

CH0b selection bit

Definition at line 4736 of file stm32l1xx.h.

#define RI_ASCR2_CH10b ((uint32_t)0x01000000)

CH10b selection bit

Definition at line 4744 of file stm32l1xx.h.

#define RI_ASCR2_CH11b ((uint32_t)0x02000000)

CH11b selection bit

Definition at line 4745 of file stm32l1xx.h.

#define RI_ASCR2_CH12b ((uint32_t)0x04000000)

CH12b selection bit

Definition at line 4746 of file stm32l1xx.h.

#define RI_ASCR2_CH1b ((uint32_t)0x00020000)

CH1b selection bit

Definition at line 4737 of file stm32l1xx.h.

#define RI_ASCR2_CH2b ((uint32_t)0x00040000)

CH2b selection bit

Definition at line 4738 of file stm32l1xx.h.

#define RI_ASCR2_CH3b ((uint32_t)0x00080000)

CH3b selection bit

Definition at line 4739 of file stm32l1xx.h.

#define RI_ASCR2_CH6b ((uint32_t)0x00100000)

CH6b selection bit

Definition at line 4740 of file stm32l1xx.h.

#define RI_ASCR2_CH7b ((uint32_t)0x00200000)

CH7b selection bit

Definition at line 4741 of file stm32l1xx.h.

#define RI_ASCR2_CH8b ((uint32_t)0x00400000)

CH8b selection bit

Definition at line 4742 of file stm32l1xx.h.

#define RI_ASCR2_CH9b ((uint32_t)0x00800000)

CH9b selection bit

Definition at line 4743 of file stm32l1xx.h.

#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001)

GR10-1 selection bit

Definition at line 4723 of file stm32l1xx.h.

#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002)

GR10-2 selection bit

Definition at line 4724 of file stm32l1xx.h.

#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004)

GR10-3 selection bit

Definition at line 4725 of file stm32l1xx.h.

#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008)

GR10-4 selection bit

Definition at line 4726 of file stm32l1xx.h.

#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200)

GR4-1 selection bit

Definition at line 4732 of file stm32l1xx.h.

#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400)

GR4-2 selection bit

Definition at line 4733 of file stm32l1xx.h.

#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800)

GR4-3 selection bit

Definition at line 4734 of file stm32l1xx.h.

#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000)

GR4-4 selection bit

Definition at line 4735 of file stm32l1xx.h.

#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040)

GR5-1 selection bit

Definition at line 4729 of file stm32l1xx.h.

#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080)

GR5-2 selection bit

Definition at line 4730 of file stm32l1xx.h.

#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100)

GR5-3 selection bit

Definition at line 4731 of file stm32l1xx.h.

#define RI_ASCR2_GR5_4 ((uint32_t)0x20000000)

GR5-4 selection bit

Definition at line 4749 of file stm32l1xx.h.

#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010)

GR6-1 selection bit

Definition at line 4727 of file stm32l1xx.h.

#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020)

GR6-2 selection bit

Definition at line 4728 of file stm32l1xx.h.

#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000)

GR6-3 selection bit

Definition at line 4747 of file stm32l1xx.h.

#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000)

GR6-4 selection bit

Definition at line 4748 of file stm32l1xx.h.

#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF)

PA[15:0] Port A Hysteresis selection

Definition at line 4752 of file stm32l1xx.h.

#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4753 of file stm32l1xx.h.

#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4754 of file stm32l1xx.h.

#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400)

Bit 10

Definition at line 4763 of file stm32l1xx.h.

#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800)

Bit 11

Definition at line 4764 of file stm32l1xx.h.

#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000)

Bit 12

Definition at line 4765 of file stm32l1xx.h.

#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000)

Bit 13

Definition at line 4766 of file stm32l1xx.h.

#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000)

Bit 14

Definition at line 4767 of file stm32l1xx.h.

#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000)

Bit 15

Definition at line 4768 of file stm32l1xx.h.

#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4755 of file stm32l1xx.h.

#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4756 of file stm32l1xx.h.

#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4757 of file stm32l1xx.h.

#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 4758 of file stm32l1xx.h.

#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 4759 of file stm32l1xx.h.

#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 4760 of file stm32l1xx.h.

#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100)

Bit 8

Definition at line 4761 of file stm32l1xx.h.

#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200)

Bit 9

Definition at line 4762 of file stm32l1xx.h.

#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000)

PB[15:0] Port B Hysteresis selection

Definition at line 4770 of file stm32l1xx.h.

#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4771 of file stm32l1xx.h.

#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4772 of file stm32l1xx.h.

#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000)

Bit 10

Definition at line 4781 of file stm32l1xx.h.

#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000)

Bit 11

Definition at line 4782 of file stm32l1xx.h.

#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000)

Bit 12

Definition at line 4783 of file stm32l1xx.h.

#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000)

Bit 13

Definition at line 4784 of file stm32l1xx.h.

#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000)

Bit 14

Definition at line 4785 of file stm32l1xx.h.

#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000)

Bit 15

Definition at line 4786 of file stm32l1xx.h.

#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4773 of file stm32l1xx.h.

#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4774 of file stm32l1xx.h.

#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 4775 of file stm32l1xx.h.

#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 4776 of file stm32l1xx.h.

#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 4777 of file stm32l1xx.h.

#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 4778 of file stm32l1xx.h.

#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000)

Bit 8

Definition at line 4779 of file stm32l1xx.h.

#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000)

Bit 9

Definition at line 4780 of file stm32l1xx.h.

#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF)

PC[15:0] Port C Hysteresis selection

Definition at line 4789 of file stm32l1xx.h.

#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4790 of file stm32l1xx.h.

#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4791 of file stm32l1xx.h.

#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400)

Bit 10

Definition at line 4800 of file stm32l1xx.h.

#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800)

Bit 11

Definition at line 4801 of file stm32l1xx.h.

#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000)

Bit 12

Definition at line 4802 of file stm32l1xx.h.

#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000)

Bit 13

Definition at line 4803 of file stm32l1xx.h.

#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000)

Bit 14

Definition at line 4804 of file stm32l1xx.h.

#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000)

Bit 15

Definition at line 4805 of file stm32l1xx.h.

#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4792 of file stm32l1xx.h.

#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4793 of file stm32l1xx.h.

#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4794 of file stm32l1xx.h.

#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 4795 of file stm32l1xx.h.

#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 4796 of file stm32l1xx.h.

#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 4797 of file stm32l1xx.h.

#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100)

Bit 8

Definition at line 4798 of file stm32l1xx.h.

#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200)

Bit 9

Definition at line 4799 of file stm32l1xx.h.

#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000)

PD[15:0] Port D Hysteresis selection

Definition at line 4807 of file stm32l1xx.h.

#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4808 of file stm32l1xx.h.

#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4809 of file stm32l1xx.h.

#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000)

Bit 10

Definition at line 4818 of file stm32l1xx.h.

#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000)

Bit 11

Definition at line 4819 of file stm32l1xx.h.

#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000)

Bit 12

Definition at line 4820 of file stm32l1xx.h.

#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000)

Bit 13

Definition at line 4821 of file stm32l1xx.h.

#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000)

Bit 14

Definition at line 4822 of file stm32l1xx.h.

#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000)

Bit 15

Definition at line 4823 of file stm32l1xx.h.

#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4810 of file stm32l1xx.h.

#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4811 of file stm32l1xx.h.

#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 4812 of file stm32l1xx.h.

#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 4813 of file stm32l1xx.h.

#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 4814 of file stm32l1xx.h.

#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 4815 of file stm32l1xx.h.

#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000)

Bit 8

Definition at line 4816 of file stm32l1xx.h.

#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000)

Bit 9

Definition at line 4817 of file stm32l1xx.h.

#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF)

PE[15:0] Port E Hysteresis selection

Definition at line 4826 of file stm32l1xx.h.

#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4827 of file stm32l1xx.h.

#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4828 of file stm32l1xx.h.

#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400)

Bit 10

Definition at line 4837 of file stm32l1xx.h.

#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800)

Bit 11

Definition at line 4838 of file stm32l1xx.h.

#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000)

Bit 12

Definition at line 4839 of file stm32l1xx.h.

#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000)

Bit 13

Definition at line 4840 of file stm32l1xx.h.

#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000)

Bit 14

Definition at line 4841 of file stm32l1xx.h.

#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000)

Bit 15

Definition at line 4842 of file stm32l1xx.h.

#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4829 of file stm32l1xx.h.

#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4830 of file stm32l1xx.h.

#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4831 of file stm32l1xx.h.

#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 4832 of file stm32l1xx.h.

#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 4833 of file stm32l1xx.h.

#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 4834 of file stm32l1xx.h.

#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100)

Bit 8

Definition at line 4835 of file stm32l1xx.h.

#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200)

Bit 9

Definition at line 4836 of file stm32l1xx.h.

#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000)

PF[15:0] Port F Hysteresis selection

Definition at line 4844 of file stm32l1xx.h.

#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4845 of file stm32l1xx.h.

#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4846 of file stm32l1xx.h.

#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000)

Bit 10

Definition at line 4855 of file stm32l1xx.h.

#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000)

Bit 11

Definition at line 4856 of file stm32l1xx.h.

#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000)

Bit 12

Definition at line 4857 of file stm32l1xx.h.

#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000)

Bit 13

Definition at line 4858 of file stm32l1xx.h.

#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000)

Bit 14

Definition at line 4859 of file stm32l1xx.h.

#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000)

Bit 15

Definition at line 4860 of file stm32l1xx.h.

#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4847 of file stm32l1xx.h.

#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4848 of file stm32l1xx.h.

#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 4849 of file stm32l1xx.h.

#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 4850 of file stm32l1xx.h.

#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 4851 of file stm32l1xx.h.

#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 4852 of file stm32l1xx.h.

#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000)

Bit 8

Definition at line 4853 of file stm32l1xx.h.

#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000)

Bit 9

Definition at line 4854 of file stm32l1xx.h.

#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF)

PG[15:0] Port G Hysteresis selection

Definition at line 4863 of file stm32l1xx.h.

#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4864 of file stm32l1xx.h.

#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4865 of file stm32l1xx.h.

#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400)

Bit 10

Definition at line 4874 of file stm32l1xx.h.

#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800)

Bit 11

Definition at line 4875 of file stm32l1xx.h.

#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000)

Bit 12

Definition at line 4876 of file stm32l1xx.h.

#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000)

Bit 13

Definition at line 4877 of file stm32l1xx.h.

#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000)

Bit 14

Definition at line 4878 of file stm32l1xx.h.

#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000)

Bit 15

Definition at line 4879 of file stm32l1xx.h.

#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4866 of file stm32l1xx.h.

#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4867 of file stm32l1xx.h.

#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4868 of file stm32l1xx.h.

#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 4869 of file stm32l1xx.h.

#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 4870 of file stm32l1xx.h.

#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 4871 of file stm32l1xx.h.

#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100)

Bit 8

Definition at line 4872 of file stm32l1xx.h.

#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200)

Bit 9

Definition at line 4873 of file stm32l1xx.h.

#define RI_ICR_IC1 ((uint32_t)0x00040000)

Input capture 1

Definition at line 4683 of file stm32l1xx.h.

#define RI_ICR_IC1Z ((uint32_t)0x0000000F)

IC1Z[3:0] bits (Input Capture 1 select bits)

Definition at line 4655 of file stm32l1xx.h.

#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4656 of file stm32l1xx.h.

#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4657 of file stm32l1xx.h.

#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4658 of file stm32l1xx.h.

#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4659 of file stm32l1xx.h.

#define RI_ICR_IC2 ((uint32_t)0x00080000)

Input capture 2

Definition at line 4684 of file stm32l1xx.h.

#define RI_ICR_IC2Z ((uint32_t)0x000000F0)

IC2Z[3:0] bits (Input Capture 2 select bits)

Definition at line 4661 of file stm32l1xx.h.

#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4662 of file stm32l1xx.h.

#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4663 of file stm32l1xx.h.

#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4664 of file stm32l1xx.h.

#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4665 of file stm32l1xx.h.

#define RI_ICR_IC3 ((uint32_t)0x00100000)

Input capture 3

Definition at line 4685 of file stm32l1xx.h.

#define RI_ICR_IC3Z ((uint32_t)0x00000F00)

IC3Z[3:0] bits (Input Capture 3 select bits)

Definition at line 4667 of file stm32l1xx.h.

#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4668 of file stm32l1xx.h.

#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4669 of file stm32l1xx.h.

#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4670 of file stm32l1xx.h.

#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4671 of file stm32l1xx.h.

#define RI_ICR_IC4 ((uint32_t)0x00200000)

Input capture 4

Definition at line 4686 of file stm32l1xx.h.

#define RI_ICR_IC4Z ((uint32_t)0x0000F000)

IC4Z[3:0] bits (Input Capture 4 select bits)

Definition at line 4673 of file stm32l1xx.h.

#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 4674 of file stm32l1xx.h.

#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 4675 of file stm32l1xx.h.

#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 4676 of file stm32l1xx.h.

#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000)

Bit 3

Definition at line 4677 of file stm32l1xx.h.

#define RI_ICR_TIM ((uint32_t)0x00030000)

TIM[3:0] bits (Timers select bits)

Definition at line 4679 of file stm32l1xx.h.

#define RI_ICR_TIM_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4680 of file stm32l1xx.h.

#define RI_ICR_TIM_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4681 of file stm32l1xx.h.

#define RTC_ALRMAR_DT ((uint32_t)0x30000000)

Definition at line 3893 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)

Definition at line 3894 of file stm32l1xx.h.

#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)

Definition at line 3895 of file stm32l1xx.h.

#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)

Definition at line 3896 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)

Definition at line 3897 of file stm32l1xx.h.

#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)

Definition at line 3898 of file stm32l1xx.h.

#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)

Definition at line 3899 of file stm32l1xx.h.

#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)

Definition at line 3900 of file stm32l1xx.h.

#define RTC_ALRMAR_HT ((uint32_t)0x00300000)

Definition at line 3903 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)

Definition at line 3904 of file stm32l1xx.h.

#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)

Definition at line 3905 of file stm32l1xx.h.

#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)

Definition at line 3906 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)

Definition at line 3907 of file stm32l1xx.h.

#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)

Definition at line 3908 of file stm32l1xx.h.

#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)

Definition at line 3909 of file stm32l1xx.h.

#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)

Definition at line 3910 of file stm32l1xx.h.

#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)

Definition at line 3912 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)

Definition at line 3913 of file stm32l1xx.h.

#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)

Definition at line 3914 of file stm32l1xx.h.

#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)

Definition at line 3915 of file stm32l1xx.h.

#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)

Definition at line 3916 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)

Definition at line 3917 of file stm32l1xx.h.

#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)

Definition at line 3918 of file stm32l1xx.h.

#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)

Definition at line 3919 of file stm32l1xx.h.

#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)

Definition at line 3920 of file stm32l1xx.h.

#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)

Definition at line 3921 of file stm32l1xx.h.

#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)

Definition at line 3911 of file stm32l1xx.h.

#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)

Definition at line 3901 of file stm32l1xx.h.

#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)

Definition at line 3891 of file stm32l1xx.h.

#define RTC_ALRMAR_PM ((uint32_t)0x00400000)

Definition at line 3902 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_ST ((uint32_t)0x00000070)

Definition at line 3922 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)

Definition at line 3923 of file stm32l1xx.h.

#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)

Definition at line 3924 of file stm32l1xx.h.

#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)

Definition at line 3925 of file stm32l1xx.h.

#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)

Definition at line 3926 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)

Definition at line 3927 of file stm32l1xx.h.

#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)

Definition at line 3928 of file stm32l1xx.h.

#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)

Definition at line 3929 of file stm32l1xx.h.

#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)

Definition at line 3930 of file stm32l1xx.h.

#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)

Definition at line 3892 of file stm32l1xx.h.

Referenced by RTC_GetAlarm().

#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)

Definition at line 4074 of file stm32l1xx.h.

#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)

Definition at line 4075 of file stm32l1xx.h.

#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)

Definition at line 4076 of file stm32l1xx.h.

#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)

Definition at line 4077 of file stm32l1xx.h.

#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)

Definition at line 4078 of file stm32l1xx.h.

#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)

Definition at line 4079 of file stm32l1xx.h.

Referenced by RTC_GetAlarmSubSecond().

#define RTC_ALRMBR_DT ((uint32_t)0x30000000)

Definition at line 3935 of file stm32l1xx.h.

#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)

Definition at line 3936 of file stm32l1xx.h.

#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)

Definition at line 3937 of file stm32l1xx.h.

#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)

Definition at line 3938 of file stm32l1xx.h.

#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)

Definition at line 3939 of file stm32l1xx.h.

#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)

Definition at line 3940 of file stm32l1xx.h.

#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)

Definition at line 3941 of file stm32l1xx.h.

#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)

Definition at line 3942 of file stm32l1xx.h.

#define RTC_ALRMBR_HT ((uint32_t)0x00300000)

Definition at line 3945 of file stm32l1xx.h.

#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)

Definition at line 3946 of file stm32l1xx.h.

#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)

Definition at line 3947 of file stm32l1xx.h.

#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)

Definition at line 3948 of file stm32l1xx.h.

#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)

Definition at line 3949 of file stm32l1xx.h.

#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)

Definition at line 3950 of file stm32l1xx.h.

#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)

Definition at line 3951 of file stm32l1xx.h.

#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)

Definition at line 3952 of file stm32l1xx.h.

#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)

Definition at line 3954 of file stm32l1xx.h.

#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)

Definition at line 3955 of file stm32l1xx.h.

#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)

Definition at line 3956 of file stm32l1xx.h.

#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)

Definition at line 3957 of file stm32l1xx.h.

#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)

Definition at line 3958 of file stm32l1xx.h.

#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)

Definition at line 3959 of file stm32l1xx.h.

#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)

Definition at line 3960 of file stm32l1xx.h.

#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)

Definition at line 3961 of file stm32l1xx.h.

#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)

Definition at line 3962 of file stm32l1xx.h.

#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)

Definition at line 3963 of file stm32l1xx.h.

#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)

Definition at line 3953 of file stm32l1xx.h.

#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)

Definition at line 3943 of file stm32l1xx.h.

#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)

Definition at line 3933 of file stm32l1xx.h.

#define RTC_ALRMBR_PM ((uint32_t)0x00400000)

Definition at line 3944 of file stm32l1xx.h.

#define RTC_ALRMBR_ST ((uint32_t)0x00000070)

Definition at line 3964 of file stm32l1xx.h.

#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)

Definition at line 3965 of file stm32l1xx.h.

#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)

Definition at line 3966 of file stm32l1xx.h.

#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)

Definition at line 3967 of file stm32l1xx.h.

#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)

Definition at line 3968 of file stm32l1xx.h.

#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)

Definition at line 3969 of file stm32l1xx.h.

#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)

Definition at line 3970 of file stm32l1xx.h.

#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)

Definition at line 3971 of file stm32l1xx.h.

#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)

Definition at line 3972 of file stm32l1xx.h.

#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)

Definition at line 3934 of file stm32l1xx.h.

#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)

Definition at line 4082 of file stm32l1xx.h.

#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)

Definition at line 4083 of file stm32l1xx.h.

#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)

Definition at line 4084 of file stm32l1xx.h.

#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)

Definition at line 4085 of file stm32l1xx.h.

#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)

Definition at line 4086 of file stm32l1xx.h.

#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)

Definition at line 4087 of file stm32l1xx.h.

Referenced by RTC_GetAlarmSubSecond().

#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)

Definition at line 4090 of file stm32l1xx.h.

#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)

Definition at line 4120 of file stm32l1xx.h.

#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)

Definition at line 4123 of file stm32l1xx.h.

#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)

Definition at line 4126 of file stm32l1xx.h.

#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)

Definition at line 4129 of file stm32l1xx.h.

#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)

Definition at line 4132 of file stm32l1xx.h.

#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)

Definition at line 4135 of file stm32l1xx.h.

#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)

Definition at line 4138 of file stm32l1xx.h.

#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)

Definition at line 4141 of file stm32l1xx.h.

#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)

Definition at line 4144 of file stm32l1xx.h.

#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)

Definition at line 4147 of file stm32l1xx.h.

#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)

Definition at line 4093 of file stm32l1xx.h.

#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)

Definition at line 4150 of file stm32l1xx.h.

#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)

Definition at line 4153 of file stm32l1xx.h.

#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)

Definition at line 4156 of file stm32l1xx.h.

#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)

Definition at line 4159 of file stm32l1xx.h.

#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)

Definition at line 4162 of file stm32l1xx.h.

#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)

Definition at line 4165 of file stm32l1xx.h.

#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)

Definition at line 4168 of file stm32l1xx.h.

#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)

Definition at line 4171 of file stm32l1xx.h.

#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)

Definition at line 4174 of file stm32l1xx.h.

#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)

Definition at line 4177 of file stm32l1xx.h.

#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)

Definition at line 4096 of file stm32l1xx.h.

#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)

Definition at line 4180 of file stm32l1xx.h.

#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)

Definition at line 4183 of file stm32l1xx.h.

#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)

Definition at line 4099 of file stm32l1xx.h.

#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)

Definition at line 4102 of file stm32l1xx.h.

#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)

Definition at line 4105 of file stm32l1xx.h.

#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)

Definition at line 4108 of file stm32l1xx.h.

#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)

Definition at line 4111 of file stm32l1xx.h.

#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)

Definition at line 4114 of file stm32l1xx.h.

#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)

Definition at line 4117 of file stm32l1xx.h.

#define RTC_CALIBR_DC ((uint32_t)0x0000001F)

Definition at line 3888 of file stm32l1xx.h.

#define RTC_CALIBR_DCS ((uint32_t)0x00000080)

Definition at line 3887 of file stm32l1xx.h.

#define RTC_CALR_CALM ((uint32_t)0x000001FF)

Definition at line 4040 of file stm32l1xx.h.

#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)

Definition at line 4041 of file stm32l1xx.h.

#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)

Definition at line 4042 of file stm32l1xx.h.

#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)

Definition at line 4043 of file stm32l1xx.h.

#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)

Definition at line 4044 of file stm32l1xx.h.

#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)

Definition at line 4045 of file stm32l1xx.h.

#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)

Definition at line 4046 of file stm32l1xx.h.

#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)

Definition at line 4047 of file stm32l1xx.h.

#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)

Definition at line 4048 of file stm32l1xx.h.

#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)

Definition at line 4049 of file stm32l1xx.h.

#define RTC_CALR_CALP ((uint32_t)0x00008000)

Definition at line 4037 of file stm32l1xx.h.

#define RTC_CALR_CALW16 ((uint32_t)0x00002000)

Definition at line 4039 of file stm32l1xx.h.

#define RTC_CALR_CALW8 ((uint32_t)0x00004000)

Definition at line 4038 of file stm32l1xx.h.

#define RTC_CR_ADD1H ((uint32_t)0x00010000)

Definition at line 3841 of file stm32l1xx.h.

#define RTC_CR_ALRAE ((uint32_t)0x00000100)

Definition at line 3849 of file stm32l1xx.h.

#define RTC_CR_ALRAIE ((uint32_t)0x00001000)

Definition at line 3845 of file stm32l1xx.h.

#define RTC_CR_ALRBE ((uint32_t)0x00000200)

Definition at line 3848 of file stm32l1xx.h.

#define RTC_CR_ALRBIE ((uint32_t)0x00002000)

Definition at line 3844 of file stm32l1xx.h.

#define RTC_CR_BCK ((uint32_t)0x00040000)

Definition at line 3839 of file stm32l1xx.h.

Referenced by RTC_DayLightSavingConfig(), and RTC_GetStoreOperation().

#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)

Definition at line 3852 of file stm32l1xx.h.

Referenced by RTC_BypassShadowCmd(), RTC_SetDate(), and RTC_SetTime().

#define RTC_CR_COE ((uint32_t)0x00800000)

Definition at line 3833 of file stm32l1xx.h.

Referenced by RTC_CalibOutputCmd().

#define RTC_CR_COSEL ((uint32_t)0x00080000)

Definition at line 3838 of file stm32l1xx.h.

Referenced by RTC_CalibOutputConfig().

#define RTC_CR_DCE ((uint32_t)0x00000080)

Definition at line 3850 of file stm32l1xx.h.

Referenced by RTC_CoarseCalibCmd().

#define RTC_CR_FMT ((uint32_t)0x00000040)

Definition at line 3851 of file stm32l1xx.h.

Referenced by RTC_Init(), RTC_SetAlarm(), and RTC_SetTime().

#define RTC_CR_OSEL ((uint32_t)0x00600000)

Definition at line 3834 of file stm32l1xx.h.

Referenced by RTC_OutputConfig().

#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)

Definition at line 3835 of file stm32l1xx.h.

#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)

Definition at line 3836 of file stm32l1xx.h.

#define RTC_CR_POL ((uint32_t)0x00100000)

Definition at line 3837 of file stm32l1xx.h.

Referenced by RTC_OutputConfig().

#define RTC_CR_REFCKON ((uint32_t)0x00000010)

Definition at line 3853 of file stm32l1xx.h.

Referenced by RTC_RefClockCmd(), and RTC_SynchroShiftConfig().

#define RTC_CR_SUB1H ((uint32_t)0x00020000)

Definition at line 3840 of file stm32l1xx.h.

#define RTC_CR_TSE ((uint32_t)0x00000800)

Definition at line 3846 of file stm32l1xx.h.

Referenced by RTC_TimeStampCmd().

#define RTC_CR_TSEDGE ((uint32_t)0x00000008)

Definition at line 3854 of file stm32l1xx.h.

Referenced by RTC_TimeStampCmd().

#define RTC_CR_TSIE ((uint32_t)0x00008000)

Definition at line 3842 of file stm32l1xx.h.

#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)

Definition at line 3855 of file stm32l1xx.h.

Referenced by RTC_WakeUpClockConfig().

#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)

Definition at line 3856 of file stm32l1xx.h.

#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)

Definition at line 3857 of file stm32l1xx.h.

#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)

Definition at line 3858 of file stm32l1xx.h.

#define RTC_CR_WUTE ((uint32_t)0x00000400)

Definition at line 3847 of file stm32l1xx.h.

Referenced by RTC_WakeUpCmd().

#define RTC_CR_WUTIE ((uint32_t)0x00004000)

Definition at line 3843 of file stm32l1xx.h.

#define RTC_DR_DT ((uint32_t)0x00000030)

Definition at line 3823 of file stm32l1xx.h.

Referenced by RTC_GetDate(), and RTC_GetTimeStamp().

#define RTC_DR_DT_0 ((uint32_t)0x00000010)

Definition at line 3824 of file stm32l1xx.h.

#define RTC_DR_DT_1 ((uint32_t)0x00000020)

Definition at line 3825 of file stm32l1xx.h.

#define RTC_DR_DU ((uint32_t)0x0000000F)

Definition at line 3826 of file stm32l1xx.h.

Referenced by RTC_GetDate(), and RTC_GetTimeStamp().

#define RTC_DR_DU_0 ((uint32_t)0x00000001)

Definition at line 3827 of file stm32l1xx.h.

#define RTC_DR_DU_1 ((uint32_t)0x00000002)

Definition at line 3828 of file stm32l1xx.h.

#define RTC_DR_DU_2 ((uint32_t)0x00000004)

Definition at line 3829 of file stm32l1xx.h.

#define RTC_DR_DU_3 ((uint32_t)0x00000008)

Definition at line 3830 of file stm32l1xx.h.

#define RTC_DR_MT ((uint32_t)0x00001000)

Definition at line 3817 of file stm32l1xx.h.

Referenced by RTC_GetDate(), and RTC_GetTimeStamp().

#define RTC_DR_MU ((uint32_t)0x00000F00)

Definition at line 3818 of file stm32l1xx.h.

Referenced by RTC_GetDate(), and RTC_GetTimeStamp().

#define RTC_DR_MU_0 ((uint32_t)0x00000100)

Definition at line 3819 of file stm32l1xx.h.

#define RTC_DR_MU_1 ((uint32_t)0x00000200)

Definition at line 3820 of file stm32l1xx.h.

#define RTC_DR_MU_2 ((uint32_t)0x00000400)

Definition at line 3821 of file stm32l1xx.h.

#define RTC_DR_MU_3 ((uint32_t)0x00000800)

Definition at line 3822 of file stm32l1xx.h.

#define RTC_DR_WDU ((uint32_t)0x0000E000)

Definition at line 3813 of file stm32l1xx.h.

Referenced by RTC_GetDate(), and RTC_GetTimeStamp().

#define RTC_DR_WDU_0 ((uint32_t)0x00002000)

Definition at line 3814 of file stm32l1xx.h.

#define RTC_DR_WDU_1 ((uint32_t)0x00004000)

Definition at line 3815 of file stm32l1xx.h.

#define RTC_DR_WDU_2 ((uint32_t)0x00008000)

Definition at line 3816 of file stm32l1xx.h.

#define RTC_DR_YT ((uint32_t)0x00F00000)

Definition at line 3803 of file stm32l1xx.h.

Referenced by RTC_GetDate().

#define RTC_DR_YT_0 ((uint32_t)0x00100000)

Definition at line 3804 of file stm32l1xx.h.

#define RTC_DR_YT_1 ((uint32_t)0x00200000)

Definition at line 3805 of file stm32l1xx.h.

#define RTC_DR_YT_2 ((uint32_t)0x00400000)

Definition at line 3806 of file stm32l1xx.h.

#define RTC_DR_YT_3 ((uint32_t)0x00800000)

Definition at line 3807 of file stm32l1xx.h.

#define RTC_DR_YU ((uint32_t)0x000F0000)

Definition at line 3808 of file stm32l1xx.h.

Referenced by RTC_GetDate().

#define RTC_DR_YU_0 ((uint32_t)0x00010000)

Definition at line 3809 of file stm32l1xx.h.

#define RTC_DR_YU_1 ((uint32_t)0x00020000)

Definition at line 3810 of file stm32l1xx.h.

#define RTC_DR_YU_2 ((uint32_t)0x00040000)

Definition at line 3811 of file stm32l1xx.h.

#define RTC_DR_YU_3 ((uint32_t)0x00080000)

Definition at line 3812 of file stm32l1xx.h.

#define RTC_ISR_ALRAF ((uint32_t)0x00000100)

Definition at line 3869 of file stm32l1xx.h.

#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)

Definition at line 3877 of file stm32l1xx.h.

#define RTC_ISR_ALRBF ((uint32_t)0x00000200)

Definition at line 3868 of file stm32l1xx.h.

#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)

Definition at line 3876 of file stm32l1xx.h.

#define RTC_ISR_INIT ((uint32_t)0x00000080)

Definition at line 3870 of file stm32l1xx.h.

Referenced by RTC_ClearFlag(), RTC_ClearITPendingBit(), and RTC_ExitInitMode().

#define RTC_ISR_INITF ((uint32_t)0x00000040)

Definition at line 3871 of file stm32l1xx.h.

Referenced by RTC_EnterInitMode().

#define RTC_ISR_INITS ((uint32_t)0x00000010)

Definition at line 3873 of file stm32l1xx.h.

#define RTC_ISR_RECALPF ((uint32_t)0x00010000)

Definition at line 3861 of file stm32l1xx.h.

Referenced by RTC_SmoothCalibConfig().

#define RTC_ISR_RSF ((uint32_t)0x00000020)

Definition at line 3872 of file stm32l1xx.h.

Referenced by RTC_WaitForSynchro().

#define RTC_ISR_SHPF ((uint32_t)0x00000008)

Definition at line 3874 of file stm32l1xx.h.

Referenced by RTC_SynchroShiftConfig().

#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)

Definition at line 3864 of file stm32l1xx.h.

#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)

Definition at line 3863 of file stm32l1xx.h.

#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)

Definition at line 3862 of file stm32l1xx.h.

#define RTC_ISR_TSF ((uint32_t)0x00000800)

Definition at line 3866 of file stm32l1xx.h.

#define RTC_ISR_TSOVF ((uint32_t)0x00001000)

Definition at line 3865 of file stm32l1xx.h.

#define RTC_ISR_WUTF ((uint32_t)0x00000400)

Definition at line 3867 of file stm32l1xx.h.

#define RTC_ISR_WUTWF ((uint32_t)0x00000004)

Definition at line 3875 of file stm32l1xx.h.

Referenced by RTC_DeInit(), and RTC_WakeUpCmd().

#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)

Definition at line 3880 of file stm32l1xx.h.

#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)

Definition at line 3881 of file stm32l1xx.h.

#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)

Definition at line 3982 of file stm32l1xx.h.

#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)

Definition at line 3981 of file stm32l1xx.h.

#define RTC_SSR_SS ((uint32_t)0x0000FFFF)

Definition at line 3978 of file stm32l1xx.h.

#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)

Definition at line 4052 of file stm32l1xx.h.

Referenced by RTC_OutputTypeConfig().

#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)

Definition at line 4071 of file stm32l1xx.h.

#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)

Definition at line 4070 of file stm32l1xx.h.

#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)

Definition at line 4068 of file stm32l1xx.h.

#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)

Definition at line 4067 of file stm32l1xx.h.

#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)

Definition at line 4066 of file stm32l1xx.h.

#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)

Definition at line 4065 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)

Definition at line 4057 of file stm32l1xx.h.

Referenced by RTC_TamperFilterConfig().

#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)

Definition at line 4058 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)

Definition at line 4059 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)

Definition at line 4060 of file stm32l1xx.h.

Referenced by RTC_TamperSamplingFreqConfig().

#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)

Definition at line 4061 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)

Definition at line 4062 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)

Definition at line 4063 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)

Definition at line 4069 of file stm32l1xx.h.

Referenced by RTC_GetITStatus(), and RTC_ITConfig().

#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)

Definition at line 4054 of file stm32l1xx.h.

Referenced by RTC_TamperPinsPrechargeDuration().

#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)

Definition at line 4055 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)

Definition at line 4056 of file stm32l1xx.h.

#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)

Definition at line 4053 of file stm32l1xx.h.

Referenced by RTC_TamperPullUpCmd().

#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)

Definition at line 4064 of file stm32l1xx.h.

Referenced by RTC_TimeStampOnTamperDetectionCmd().

#define RTC_TR_HT ((uint32_t)0x00300000)

Definition at line 3775 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_HT_0 ((uint32_t)0x00100000)

Definition at line 3776 of file stm32l1xx.h.

#define RTC_TR_HT_1 ((uint32_t)0x00200000)

Definition at line 3777 of file stm32l1xx.h.

#define RTC_TR_HU ((uint32_t)0x000F0000)

Definition at line 3778 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_HU_0 ((uint32_t)0x00010000)

Definition at line 3779 of file stm32l1xx.h.

#define RTC_TR_HU_1 ((uint32_t)0x00020000)

Definition at line 3780 of file stm32l1xx.h.

#define RTC_TR_HU_2 ((uint32_t)0x00040000)

Definition at line 3781 of file stm32l1xx.h.

#define RTC_TR_HU_3 ((uint32_t)0x00080000)

Definition at line 3782 of file stm32l1xx.h.

#define RTC_TR_MNT ((uint32_t)0x00007000)

Definition at line 3783 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_MNT_0 ((uint32_t)0x00001000)

Definition at line 3784 of file stm32l1xx.h.

#define RTC_TR_MNT_1 ((uint32_t)0x00002000)

Definition at line 3785 of file stm32l1xx.h.

#define RTC_TR_MNT_2 ((uint32_t)0x00004000)

Definition at line 3786 of file stm32l1xx.h.

#define RTC_TR_MNU ((uint32_t)0x00000F00)

Definition at line 3787 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_MNU_0 ((uint32_t)0x00000100)

Definition at line 3788 of file stm32l1xx.h.

#define RTC_TR_MNU_1 ((uint32_t)0x00000200)

Definition at line 3789 of file stm32l1xx.h.

#define RTC_TR_MNU_2 ((uint32_t)0x00000400)

Definition at line 3790 of file stm32l1xx.h.

#define RTC_TR_MNU_3 ((uint32_t)0x00000800)

Definition at line 3791 of file stm32l1xx.h.

#define RTC_TR_PM ((uint32_t)0x00400000)

Definition at line 3774 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_ST ((uint32_t)0x00000070)

Definition at line 3792 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_ST_0 ((uint32_t)0x00000010)

Definition at line 3793 of file stm32l1xx.h.

#define RTC_TR_ST_1 ((uint32_t)0x00000020)

Definition at line 3794 of file stm32l1xx.h.

#define RTC_TR_ST_2 ((uint32_t)0x00000040)

Definition at line 3795 of file stm32l1xx.h.

#define RTC_TR_SU ((uint32_t)0x0000000F)

Definition at line 3796 of file stm32l1xx.h.

Referenced by RTC_GetTime(), and RTC_GetTimeStamp().

#define RTC_TR_SU_0 ((uint32_t)0x00000001)

Definition at line 3797 of file stm32l1xx.h.

#define RTC_TR_SU_1 ((uint32_t)0x00000002)

Definition at line 3798 of file stm32l1xx.h.

#define RTC_TR_SU_2 ((uint32_t)0x00000004)

Definition at line 3799 of file stm32l1xx.h.

#define RTC_TR_SU_3 ((uint32_t)0x00000008)

Definition at line 3800 of file stm32l1xx.h.

#define RTC_TSDR_DT ((uint32_t)0x00000030)

Definition at line 4024 of file stm32l1xx.h.

#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)

Definition at line 4025 of file stm32l1xx.h.

#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)

Definition at line 4026 of file stm32l1xx.h.

#define RTC_TSDR_DU ((uint32_t)0x0000000F)

Definition at line 4027 of file stm32l1xx.h.

#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)

Definition at line 4028 of file stm32l1xx.h.

#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)

Definition at line 4029 of file stm32l1xx.h.

#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)

Definition at line 4030 of file stm32l1xx.h.

#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)

Definition at line 4031 of file stm32l1xx.h.

#define RTC_TSDR_MT ((uint32_t)0x00001000)

Definition at line 4018 of file stm32l1xx.h.

#define RTC_TSDR_MU ((uint32_t)0x00000F00)

Definition at line 4019 of file stm32l1xx.h.

#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)

Definition at line 4020 of file stm32l1xx.h.

#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)

Definition at line 4021 of file stm32l1xx.h.

#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)

Definition at line 4022 of file stm32l1xx.h.

#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)

Definition at line 4023 of file stm32l1xx.h.

#define RTC_TSDR_WDU ((uint32_t)0x0000E000)

Definition at line 4014 of file stm32l1xx.h.

#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)

Definition at line 4015 of file stm32l1xx.h.

#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)

Definition at line 4016 of file stm32l1xx.h.

#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)

Definition at line 4017 of file stm32l1xx.h.

#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)

Definition at line 4034 of file stm32l1xx.h.

#define RTC_TSTR_HT ((uint32_t)0x00300000)

Definition at line 3986 of file stm32l1xx.h.

#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)

Definition at line 3987 of file stm32l1xx.h.

#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)

Definition at line 3988 of file stm32l1xx.h.

#define RTC_TSTR_HU ((uint32_t)0x000F0000)

Definition at line 3989 of file stm32l1xx.h.

#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)

Definition at line 3990 of file stm32l1xx.h.

#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)

Definition at line 3991 of file stm32l1xx.h.

#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)

Definition at line 3992 of file stm32l1xx.h.

#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)

Definition at line 3993 of file stm32l1xx.h.

#define RTC_TSTR_MNT ((uint32_t)0x00007000)

Definition at line 3994 of file stm32l1xx.h.

#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)

Definition at line 3995 of file stm32l1xx.h.

#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)

Definition at line 3996 of file stm32l1xx.h.

#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)

Definition at line 3997 of file stm32l1xx.h.

#define RTC_TSTR_MNU ((uint32_t)0x00000F00)

Definition at line 3998 of file stm32l1xx.h.

#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)

Definition at line 3999 of file stm32l1xx.h.

#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)

Definition at line 4000 of file stm32l1xx.h.

#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)

Definition at line 4001 of file stm32l1xx.h.

#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)

Definition at line 4002 of file stm32l1xx.h.

#define RTC_TSTR_PM ((uint32_t)0x00400000)

Definition at line 3985 of file stm32l1xx.h.

#define RTC_TSTR_ST ((uint32_t)0x00000070)

Definition at line 4003 of file stm32l1xx.h.

#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)

Definition at line 4004 of file stm32l1xx.h.

#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)

Definition at line 4005 of file stm32l1xx.h.

#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)

Definition at line 4006 of file stm32l1xx.h.

#define RTC_TSTR_SU ((uint32_t)0x0000000F)

Definition at line 4007 of file stm32l1xx.h.

#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)

Definition at line 4008 of file stm32l1xx.h.

#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)

Definition at line 4009 of file stm32l1xx.h.

#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)

Definition at line 4010 of file stm32l1xx.h.

#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)

Definition at line 4011 of file stm32l1xx.h.

#define RTC_WPR_KEY ((uint32_t)0x000000FF)

Definition at line 3975 of file stm32l1xx.h.

#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)

Definition at line 3884 of file stm32l1xx.h.

Referenced by RTC_GetWakeUpCounter().

#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)

Implementation defined

Definition at line 6299 of file stm32l1xx.h.

#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)

Data endianness bit

Definition at line 6220 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)

PRIGROUP[2:0] bits (Priority group)

Definition at line 6205 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)

Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)

Definition at line 6211 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)

Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)

Definition at line 6212 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)

Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)

Definition at line 6213 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)

Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)

Definition at line 6214 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)

Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)

Definition at line 6215 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)

Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)

Definition at line 6216 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)

Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)

Definition at line 6217 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)

Priority group=7 (no pre-emption priority, 8 bits of subpriority)

Definition at line 6218 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 6206 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 6207 of file stm32l1xx.h.

#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 6208 of file stm32l1xx.h.

#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)

Requests chip control logic to generate a reset

Definition at line 6203 of file stm32l1xx.h.

#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)

Clear active vector bit

Definition at line 6202 of file stm32l1xx.h.

#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)

Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)

Definition at line 6221 of file stm32l1xx.h.

#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)

System Reset bit

Definition at line 6201 of file stm32l1xx.h.

#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

Bus fault address field

Definition at line 6296 of file stm32l1xx.h.

#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)

Handlers running at priority -1 and -2

Definition at line 6233 of file stm32l1xx.h.

#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)

Trap on Divide by 0

Definition at line 6232 of file stm32l1xx.h.

#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)

Thread mode can be entered from any level in Handler mode by controlled return value

Definition at line 6229 of file stm32l1xx.h.

#define SCB_CCR_STKALIGN ((uint16_t)0x0200)

On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned

Definition at line 6234 of file stm32l1xx.h.

#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)

Trap for unaligned access

Definition at line 6231 of file stm32l1xx.h.

#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002)

Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception

Definition at line 6230 of file stm32l1xx.h.

#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000)

Bus Fault Address Register address valid flag UFSR

Definition at line 6271 of file stm32l1xx.h.

#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)

Data access violation

Definition at line 6261 of file stm32l1xx.h.

#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)

Fault occurs when SDIV or DIV instruction is used with a divisor of 0

Definition at line 6278 of file stm32l1xx.h.

#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)

< MFSR Instruction access violation

Definition at line 6260 of file stm32l1xx.h.

#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100)

Instruction bus error flag

Definition at line 6266 of file stm32l1xx.h.

#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)

Imprecise data bus error

Definition at line 6268 of file stm32l1xx.h.

#define SCB_CFSR_INVPC ((uint32_t)0x00040000)

Attempt to load EXC_RETURN into pc illegally

Definition at line 6275 of file stm32l1xx.h.

#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000)

Invalid combination of EPSR and instruction

Definition at line 6274 of file stm32l1xx.h.

#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080)

Memory Manage Address Register address valid flag BFSR

Definition at line 6264 of file stm32l1xx.h.

#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010)

Stacking error

Definition at line 6263 of file stm32l1xx.h.

#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)

Unstacking error

Definition at line 6262 of file stm32l1xx.h.

#define SCB_CFSR_NOCP ((uint32_t)0x00080000)

Attempt to use a coprocessor instruction

Definition at line 6276 of file stm32l1xx.h.

#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200)

Precise data bus error

Definition at line 6267 of file stm32l1xx.h.

#define SCB_CFSR_STKERR ((uint32_t)0x00001000)

Stacking error

Definition at line 6270 of file stm32l1xx.h.

#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)

Fault occurs when there is an attempt to make an unaligned memory access

Definition at line 6277 of file stm32l1xx.h.

#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)

The processor attempt to excecute an undefined instruction

Definition at line 6273 of file stm32l1xx.h.

#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)

Unstacking error

Definition at line 6269 of file stm32l1xx.h.

#define SCB_CPUID_Constant ((uint32_t)0x000F0000)

Reads as 0x0F

Definition at line 6180 of file stm32l1xx.h.

#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)

Implementer code. ARM is 0x41

Definition at line 6182 of file stm32l1xx.h.

#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)

Number of processor within family

Definition at line 6179 of file stm32l1xx.h.

#define SCB_CPUID_REVISION ((uint32_t)0x0000000F)

Implementation defined revision number

Definition at line 6178 of file stm32l1xx.h.

#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000)

Implementation defined variant number

Definition at line 6181 of file stm32l1xx.h.

#define SCB_DFSR_BKPT ((uint8_t)0x02)

BKPT flag

Definition at line 6287 of file stm32l1xx.h.

#define SCB_DFSR_DWTTRAP ((uint8_t)0x04)

Data Watchpoint and Trace (DWT) flag

Definition at line 6288 of file stm32l1xx.h.

#define SCB_DFSR_EXTERNAL ((uint8_t)0x10)

External debug request flag

Definition at line 6290 of file stm32l1xx.h.

#define SCB_DFSR_HALTED ((uint8_t)0x01)

Halt request flag

Definition at line 6286 of file stm32l1xx.h.

#define SCB_DFSR_VCATCH ((uint8_t)0x08)

Vector catch flag

Definition at line 6289 of file stm32l1xx.h.

#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)

Fault related to debug

Definition at line 6283 of file stm32l1xx.h.

#define SCB_HFSR_FORCED ((uint32_t)0x40000000)

Hard Fault activated when a configurable Fault was received and cannot activate

Definition at line 6282 of file stm32l1xx.h.

#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002)

Fault occures because of vector table read on exception processing

Definition at line 6281 of file stm32l1xx.h.

#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)

Interrupt pending flag

Definition at line 6188 of file stm32l1xx.h.

#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)

It indicates that a pending interrupt becomes active in the next running cycle

Definition at line 6189 of file stm32l1xx.h.

#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)

Set pending NMI bit

Definition at line 6194 of file stm32l1xx.h.

#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)

Clear pending SysTick bit

Definition at line 6190 of file stm32l1xx.h.

#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)

Set pending SysTick bit

Definition at line 6191 of file stm32l1xx.h.

#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)

Clear pending pendSV bit

Definition at line 6192 of file stm32l1xx.h.

#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)

Set pending pendSV bit

Definition at line 6193 of file stm32l1xx.h.

#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)

All active exceptions minus the IPSR_current_exception yields the empty set

Definition at line 6186 of file stm32l1xx.h.

#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)

Active ISR number field

Definition at line 6185 of file stm32l1xx.h.

#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)

Pending ISR number field

Definition at line 6187 of file stm32l1xx.h.

#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

Mem Manage fault address field

Definition at line 6293 of file stm32l1xx.h.

#define SCB_SCR_SEVONPEND ((uint8_t)0x10)

Wake up from WFE

Definition at line 6226 of file stm32l1xx.h.

#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

Sleep deep bit

Definition at line 6225 of file stm32l1xx.h.

Referenced by PWR_EnterSleepMode(), PWR_EnterSTANDBYMode(), and PWR_EnterSTOPMode().

#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

Sleep on exit bit

Definition at line 6224 of file stm32l1xx.h.

#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)

BusFault is active

Definition at line 6244 of file stm32l1xx.h.

#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)

Bus Fault enable

Definition at line 6255 of file stm32l1xx.h.

#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)

Bus Fault is pended

Definition at line 6252 of file stm32l1xx.h.

#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)

MemManage is active

Definition at line 6243 of file stm32l1xx.h.

#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)

MemManage enable

Definition at line 6254 of file stm32l1xx.h.

#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)

MemManage is pended

Definition at line 6251 of file stm32l1xx.h.

#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)

Monitor is active

Definition at line 6247 of file stm32l1xx.h.

#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)

PendSV is active

Definition at line 6248 of file stm32l1xx.h.

#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)

SVCall is active

Definition at line 6246 of file stm32l1xx.h.

#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)

SVCall is pended

Definition at line 6253 of file stm32l1xx.h.

#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)

SysTick is active

Definition at line 6249 of file stm32l1xx.h.

#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)

UsageFault is active

Definition at line 6245 of file stm32l1xx.h.

#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)

UsageFault enable

Definition at line 6256 of file stm32l1xx.h.

#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)

Usage Fault is pended

Definition at line 6250 of file stm32l1xx.h.

#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF)

Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor

Definition at line 6237 of file stm32l1xx.h.

#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)

Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved

Definition at line 6238 of file stm32l1xx.h.

#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)

Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV

Definition at line 6239 of file stm32l1xx.h.

#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)

Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick

Definition at line 6240 of file stm32l1xx.h.

#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000)

Table base in code(0) or RAM(1) ***************** Bit definition for SCB_AIRCR register

Definition at line 6198 of file stm32l1xx.h.

#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)

Vector table base offset field

Definition at line 6197 of file stm32l1xx.h.

#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)

Command argument

Definition at line 4210 of file stm32l1xx.h.

#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400)

Clock divider bypass enable bit

Definition at line 4200 of file stm32l1xx.h.

#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)

Clock divide factor

Definition at line 4197 of file stm32l1xx.h.

#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100)

Clock enable bit

Definition at line 4198 of file stm32l1xx.h.

#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)

HW Flow Control enable

Definition at line 4207 of file stm32l1xx.h.

#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

Definition at line 4206 of file stm32l1xx.h.

#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)

Power saving configuration bit

Definition at line 4199 of file stm32l1xx.h.

#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

Definition at line 4202 of file stm32l1xx.h.

#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)

Bit 0

Definition at line 4203 of file stm32l1xx.h.

#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)

Bit 1

Definition at line 4204 of file stm32l1xx.h.

#define SDIO_CMD_CEATACMD ((uint16_t)0x4000)

CE-ATA command

Definition at line 4225 of file stm32l1xx.h.

#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F)

Command Index

Definition at line 4213 of file stm32l1xx.h.

#define SDIO_CMD_CPSMEN ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

Definition at line 4221 of file stm32l1xx.h.

#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)

Enable CMD completion

Definition at line 4223 of file stm32l1xx.h.

#define SDIO_CMD_NIEN ((uint16_t)0x2000)

Not Interrupt Enable

Definition at line 4224 of file stm32l1xx.h.

#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)

SD I/O suspend command

Definition at line 4222 of file stm32l1xx.h.

#define SDIO_CMD_WAITINT ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

Definition at line 4219 of file stm32l1xx.h.

#define SDIO_CMD_WAITPEND ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

Definition at line 4220 of file stm32l1xx.h.

#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

Definition at line 4215 of file stm32l1xx.h.

#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)

Bit 0

Definition at line 4216 of file stm32l1xx.h.

#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)

Bit 1

Definition at line 4217 of file stm32l1xx.h.

#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)

Data count value

Definition at line 4269 of file stm32l1xx.h.

#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

Definition at line 4257 of file stm32l1xx.h.

#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4258 of file stm32l1xx.h.

#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4259 of file stm32l1xx.h.

#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4260 of file stm32l1xx.h.

#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)

Bit 3

Definition at line 4261 of file stm32l1xx.h.

#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008)

DMA enabled bit

Definition at line 4255 of file stm32l1xx.h.

#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002)

Data transfer direction selection

Definition at line 4253 of file stm32l1xx.h.

#define SDIO_DCTRL_DTEN ((uint16_t)0x0001)

Data transfer enabled bit

Definition at line 4252 of file stm32l1xx.h.

#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004)

Data transfer mode selection

Definition at line 4254 of file stm32l1xx.h.

#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400)

Read wait mode

Definition at line 4265 of file stm32l1xx.h.

#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100)

Read wait start

Definition at line 4263 of file stm32l1xx.h.

#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)

Read wait stop

Definition at line 4264 of file stm32l1xx.h.

#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)

SD I/O enable functions

Definition at line 4266 of file stm32l1xx.h.

#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)

Data length value

Definition at line 4249 of file stm32l1xx.h.

#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)

Data timeout period.

Definition at line 4246 of file stm32l1xx.h.

#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

Definition at line 4342 of file stm32l1xx.h.

#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

Definition at line 4339 of file stm32l1xx.h.

#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

Definition at line 4298 of file stm32l1xx.h.

#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)

CEATAEND flag clear bit

Definition at line 4310 of file stm32l1xx.h.

#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)

CMDREND flag clear bit

Definition at line 4304 of file stm32l1xx.h.

#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)

CMDSENT flag clear bit

Definition at line 4305 of file stm32l1xx.h.

#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

Definition at line 4300 of file stm32l1xx.h.

#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100)

DATAEND flag clear bit

Definition at line 4306 of file stm32l1xx.h.

#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)

DBCKEND flag clear bit

Definition at line 4308 of file stm32l1xx.h.

#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

Definition at line 4299 of file stm32l1xx.h.

#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

Definition at line 4301 of file stm32l1xx.h.

#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)

RXOVERR flag clear bit

Definition at line 4303 of file stm32l1xx.h.

#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000)

SDIOIT flag clear bit

Definition at line 4309 of file stm32l1xx.h.

#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200)

STBITERR flag clear bit

Definition at line 4307 of file stm32l1xx.h.

#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)

TXUNDERR flag clear bit

Definition at line 4302 of file stm32l1xx.h.

#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

Definition at line 4313 of file stm32l1xx.h.

#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

Definition at line 4336 of file stm32l1xx.h.

#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)

Command Acting Interrupt Enable

Definition at line 4324 of file stm32l1xx.h.

#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

Definition at line 4319 of file stm32l1xx.h.

#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)

Command Sent Interrupt Enable

Definition at line 4320 of file stm32l1xx.h.

#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

Definition at line 4315 of file stm32l1xx.h.

#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)

Data End Interrupt Enable

Definition at line 4321 of file stm32l1xx.h.

#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)

Data Block End Interrupt Enable

Definition at line 4323 of file stm32l1xx.h.

#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

Definition at line 4314 of file stm32l1xx.h.

#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

Definition at line 4316 of file stm32l1xx.h.

#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000)

Data receive acting interrupt enabled

Definition at line 4326 of file stm32l1xx.h.

#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

Definition at line 4334 of file stm32l1xx.h.

#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

Definition at line 4332 of file stm32l1xx.h.

#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

Definition at line 4330 of file stm32l1xx.h.

#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

Definition at line 4328 of file stm32l1xx.h.

#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

Definition at line 4318 of file stm32l1xx.h.

#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

Definition at line 4335 of file stm32l1xx.h.

#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

Definition at line 4322 of file stm32l1xx.h.

#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

Definition at line 4325 of file stm32l1xx.h.

#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

Definition at line 4333 of file stm32l1xx.h.

#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

Definition at line 4331 of file stm32l1xx.h.

#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

Definition at line 4329 of file stm32l1xx.h.

#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

Definition at line 4327 of file stm32l1xx.h.

#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

Definition at line 4317 of file stm32l1xx.h.

#define SDIO_POWER_PWRCTRL ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

Definition at line 4192 of file stm32l1xx.h.

#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)

Bit 0

Definition at line 4193 of file stm32l1xx.h.

#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)

Bit 1

Definition at line 4194 of file stm32l1xx.h.

#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 4231 of file stm32l1xx.h.

#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 4234 of file stm32l1xx.h.

#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 4237 of file stm32l1xx.h.

#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 4240 of file stm32l1xx.h.

#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 4243 of file stm32l1xx.h.

#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)

Response command index

Definition at line 4228 of file stm32l1xx.h.

#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)

Command response received (CRC check failed)

Definition at line 4272 of file stm32l1xx.h.

#define SDIO_STA_CEATAEND ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

Definition at line 4295 of file stm32l1xx.h.

#define SDIO_STA_CMDACT ((uint32_t)0x00000800)

Command transfer in progress

Definition at line 4283 of file stm32l1xx.h.

#define SDIO_STA_CMDREND ((uint32_t)0x00000040)

Command response received (CRC check passed)

Definition at line 4278 of file stm32l1xx.h.

#define SDIO_STA_CMDSENT ((uint32_t)0x00000080)

Command sent (no response required)

Definition at line 4279 of file stm32l1xx.h.

#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)

Command response timeout

Definition at line 4274 of file stm32l1xx.h.

#define SDIO_STA_DATAEND ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

Definition at line 4280 of file stm32l1xx.h.

#define SDIO_STA_DBCKEND ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

Definition at line 4282 of file stm32l1xx.h.

#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

Definition at line 4273 of file stm32l1xx.h.

#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)

Data timeout

Definition at line 4275 of file stm32l1xx.h.

#define SDIO_STA_RXACT ((uint32_t)0x00002000)

Data receive in progress

Definition at line 4285 of file stm32l1xx.h.

#define SDIO_STA_RXDAVL ((uint32_t)0x00200000)

Data available in receive FIFO

Definition at line 4293 of file stm32l1xx.h.

#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000)

Receive FIFO empty

Definition at line 4291 of file stm32l1xx.h.

#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000)

Receive FIFO full

Definition at line 4289 of file stm32l1xx.h.

#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

Definition at line 4287 of file stm32l1xx.h.

#define SDIO_STA_RXOVERR ((uint32_t)0x00000020)

Received FIFO overrun error

Definition at line 4277 of file stm32l1xx.h.

#define SDIO_STA_SDIOIT ((uint32_t)0x00400000)

SDIO interrupt received

Definition at line 4294 of file stm32l1xx.h.

#define SDIO_STA_STBITERR ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

Definition at line 4281 of file stm32l1xx.h.

#define SDIO_STA_TXACT ((uint32_t)0x00001000)

Data transmit in progress

Definition at line 4284 of file stm32l1xx.h.

#define SDIO_STA_TXDAVL ((uint32_t)0x00100000)

Data available in transmit FIFO

Definition at line 4292 of file stm32l1xx.h.

#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000)

Transmit FIFO empty

Definition at line 4290 of file stm32l1xx.h.

#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000)

Transmit FIFO full

Definition at line 4288 of file stm32l1xx.h.

#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

Definition at line 4286 of file stm32l1xx.h.

#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010)

Transmit FIFO underrun error

Definition at line 4276 of file stm32l1xx.h.

#define SPI_CR1_BIDIMODE ((uint16_t)0x8000)

Bidirectional data mode enable

Definition at line 4369 of file stm32l1xx.h.

#define SPI_CR1_BIDIOE ((uint16_t)0x4000)

Output enable in bidirectional mode

Definition at line 4368 of file stm32l1xx.h.

#define SPI_CR1_BR ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

Definition at line 4355 of file stm32l1xx.h.

#define SPI_CR1_BR_0 ((uint16_t)0x0008)

Bit 0

Definition at line 4356 of file stm32l1xx.h.

#define SPI_CR1_BR_1 ((uint16_t)0x0010)

Bit 1

Definition at line 4357 of file stm32l1xx.h.

#define SPI_CR1_BR_2 ((uint16_t)0x0020)

Bit 2

Definition at line 4358 of file stm32l1xx.h.

#define SPI_CR1_CPHA ((uint16_t)0x0001)

Clock Phase

Definition at line 4351 of file stm32l1xx.h.

#define SPI_CR1_CPOL ((uint16_t)0x0002)

Clock Polarity

Definition at line 4352 of file stm32l1xx.h.

#define SPI_CR1_CRCEN ((uint16_t)0x2000)

Hardware CRC calculation enable

Definition at line 4367 of file stm32l1xx.h.

Referenced by SPI_CalculateCRC().

#define SPI_CR1_CRCNEXT ((uint16_t)0x1000)

Transmit CRC next

Definition at line 4366 of file stm32l1xx.h.

Referenced by SPI_TransmitCRC().

#define SPI_CR1_DFF ((uint16_t)0x0800)

Data Frame Format

Definition at line 4365 of file stm32l1xx.h.

#define SPI_CR1_LSBFIRST ((uint16_t)0x0080)

Frame Format

Definition at line 4361 of file stm32l1xx.h.

#define SPI_CR1_MSTR ((uint16_t)0x0004)

Master Selection

Definition at line 4353 of file stm32l1xx.h.

#define SPI_CR1_RXONLY ((uint16_t)0x0400)

Receive only

Definition at line 4364 of file stm32l1xx.h.

#define SPI_CR1_SPE ((uint16_t)0x0040)

SPI Enable

Definition at line 4360 of file stm32l1xx.h.

Referenced by SPI_Cmd().

#define SPI_CR1_SSI ((uint16_t)0x0100)

Internal slave select

Definition at line 4362 of file stm32l1xx.h.

#define SPI_CR1_SSM ((uint16_t)0x0200)

Software slave management

Definition at line 4363 of file stm32l1xx.h.

#define SPI_CR2_ERRIE ((uint8_t)0x20)

Error Interrupt Enable

Definition at line 4376 of file stm32l1xx.h.

#define SPI_CR2_FRF ((uint8_t)0x08)

Frame format

Definition at line 4375 of file stm32l1xx.h.

#define SPI_CR2_RXDMAEN ((uint8_t)0x01)

Rx Buffer DMA Enable

Definition at line 4372 of file stm32l1xx.h.

#define SPI_CR2_RXNEIE ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

Definition at line 4377 of file stm32l1xx.h.

#define SPI_CR2_SSOE ((uint8_t)0x04)

SS Output Enable

Definition at line 4374 of file stm32l1xx.h.

Referenced by SPI_SSOutputCmd().

#define SPI_CR2_TXDMAEN ((uint8_t)0x02)

Tx Buffer DMA Enable

Definition at line 4373 of file stm32l1xx.h.

#define SPI_CR2_TXEIE ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

Definition at line 4378 of file stm32l1xx.h.

#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)

CRC polynomial register

Definition at line 4394 of file stm32l1xx.h.

#define SPI_DR_DR ((uint16_t)0xFFFF)

Data Register

Definition at line 4391 of file stm32l1xx.h.

#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

Definition at line 4403 of file stm32l1xx.h.

#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)

steady state clock polarity

Definition at line 4409 of file stm32l1xx.h.

#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

Definition at line 4405 of file stm32l1xx.h.

#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)

Bit 0

Definition at line 4406 of file stm32l1xx.h.

#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)

Bit 1

Definition at line 4407 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

Definition at line 4417 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4418 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4419 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400)

I2S Enable

Definition at line 4421 of file stm32l1xx.h.

Referenced by I2S_Cmd().

#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)

I2S mode selection

Definition at line 4422 of file stm32l1xx.h.

Referenced by I2S_Init(), and SPI_Init().

#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

Definition at line 4411 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4412 of file stm32l1xx.h.

#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4413 of file stm32l1xx.h.

#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)

PCM frame synchronization

Definition at line 4415 of file stm32l1xx.h.

#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)

I2S Linear prescaler

Definition at line 4425 of file stm32l1xx.h.

#define SPI_I2SPR_MCKOE ((uint16_t)0x0200)

Master Clock Output Enable

Definition at line 4427 of file stm32l1xx.h.

#define SPI_I2SPR_ODD ((uint16_t)0x0100)

Odd factor for the prescaler

Definition at line 4426 of file stm32l1xx.h.

#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)

Rx CRC Register

Definition at line 4397 of file stm32l1xx.h.

#define SPI_SR_BSY ((uint8_t)0x80)

Busy flag

Definition at line 4388 of file stm32l1xx.h.

#define SPI_SR_CHSIDE ((uint8_t)0x04)

Channel side

Definition at line 4383 of file stm32l1xx.h.

#define SPI_SR_CRCERR ((uint8_t)0x10)

CRC Error flag

Definition at line 4385 of file stm32l1xx.h.

#define SPI_SR_MODF ((uint8_t)0x20)

Mode fault

Definition at line 4386 of file stm32l1xx.h.

#define SPI_SR_OVR ((uint8_t)0x40)

Overrun flag

Definition at line 4387 of file stm32l1xx.h.

#define SPI_SR_RXNE ((uint8_t)0x01)

Receive buffer Not Empty

Definition at line 4381 of file stm32l1xx.h.

#define SPI_SR_TXE ((uint8_t)0x02)

Transmit buffer Empty

Definition at line 4382 of file stm32l1xx.h.

#define SPI_SR_UDR ((uint8_t)0x08)

Underrun flag

Definition at line 4384 of file stm32l1xx.h.

#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)

Tx CRC Register

Definition at line 4400 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F)

EXTI 0 configuration

Definition at line 4446 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000)

EXTI0 configuration.

PA[0] pin

Definition at line 4454 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001)

PB[0] pin

Definition at line 4455 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002)

PC[0] pin

Definition at line 4456 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003)

PD[0] pin

Definition at line 4457 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004)

PE[0] pin

Definition at line 4458 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006)

PF[0] pin

Definition at line 4460 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007)

PG[0] pin

Definition at line 4461 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005)

PH[0] pin

Definition at line 4459 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0)

EXTI 1 configuration

Definition at line 4447 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000)

EXTI1 configuration.

PA[1] pin

Definition at line 4466 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010)

PB[1] pin

Definition at line 4467 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020)

PC[1] pin

Definition at line 4468 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030)

PD[1] pin

Definition at line 4469 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040)

PE[1] pin

Definition at line 4470 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060)

PF[1] pin

Definition at line 4472 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070)

PG[1] pin

Definition at line 4473 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050)

PH[1] pin

Definition at line 4471 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00)

EXTI 2 configuration

Definition at line 4448 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)

EXTI2 configuration.

PA[2] pin

Definition at line 4478 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100)

PB[2] pin

Definition at line 4479 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200)

PC[2] pin

Definition at line 4480 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300)

PD[2] pin

Definition at line 4481 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400)

PE[2] pin

Definition at line 4482 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600)

PF[2] pin

Definition at line 4484 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700)

PG[2] pin

Definition at line 4485 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500)

PH[2] pin

Definition at line 4483 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000)

EXTI 3 configuration

Definition at line 4449 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000)

EXTI3 configuration.

PA[3] pin

Definition at line 4490 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000)

PB[3] pin

Definition at line 4491 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000)

PC[3] pin

Definition at line 4492 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000)

PD[3] pin

Definition at line 4493 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000)

PE[3] pin

Definition at line 4494 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000)

PF[3] pin

Definition at line 4495 of file stm32l1xx.h.

#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000)

PG[3] pin

Definition at line 4496 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F)

EXTI 4 configuration

Definition at line 4499 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000)

EXTI4 configuration.

PA[4] pin

Definition at line 4507 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001)

PB[4] pin

Definition at line 4508 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002)

PC[4] pin

Definition at line 4509 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003)

PD[4] pin

Definition at line 4510 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004)

PE[4] pin

Definition at line 4511 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006)

PF[4] pin

Definition at line 4512 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007)

PG[4] pin

Definition at line 4513 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0)

EXTI 5 configuration

Definition at line 4500 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000)

EXTI5 configuration.

PA[5] pin

Definition at line 4518 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010)

PB[5] pin

Definition at line 4519 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020)

PC[5] pin

Definition at line 4520 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030)

PD[5] pin

Definition at line 4521 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040)

PE[5] pin

Definition at line 4522 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060)

PF[5] pin

Definition at line 4523 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070)

PG[5] pin

Definition at line 4524 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00)

EXTI 6 configuration

Definition at line 4501 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000)

EXTI6 configuration.

PA[6] pin

Definition at line 4529 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100)

PB[6] pin

Definition at line 4530 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200)

PC[6] pin

Definition at line 4531 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300)

PD[6] pin

Definition at line 4532 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400)

PE[6] pin

Definition at line 4533 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600)

PF[6] pin

Definition at line 4534 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700)

PG[6] pin

Definition at line 4535 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000)

EXTI 7 configuration

Definition at line 4502 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000)

EXTI7 configuration.

PA[7] pin

Definition at line 4540 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000)

PB[7] pin

Definition at line 4541 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000)

PC[7] pin

Definition at line 4542 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000)

PD[7] pin

Definition at line 4543 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000)

PE[7] pin

Definition at line 4544 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000)

PF[7] pin

Definition at line 4545 of file stm32l1xx.h.

#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000)

PG[7] pin

Definition at line 4546 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00)

EXTI 10 configuration

Definition at line 4551 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000)

EXTI10 configuration.

PA[10] pin

Definition at line 4579 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100)

PB[10] pin

Definition at line 4580 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200)

PC[10] pin

Definition at line 4581 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300)

PD[10] pin

Definition at line 4582 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400)

PE[10] pin

Definition at line 4583 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600)

PF[10] pin

Definition at line 4584 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700)

PG[10] pin

Definition at line 4585 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000)

EXTI 11 configuration

Definition at line 4552 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000)

EXTI11 configuration.

PA[11] pin

Definition at line 4590 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000)

PB[11] pin

Definition at line 4591 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000)

PC[11] pin

Definition at line 4592 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000)

PD[11] pin

Definition at line 4593 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000)

PE[11] pin

Definition at line 4594 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000)

PF[11] pin

Definition at line 4595 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000)

PG[11] pin

Definition at line 4596 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F)

EXTI 8 configuration

Definition at line 4549 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000)

EXTI8 configuration.

PA[8] pin

Definition at line 4557 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001)

PB[8] pin

Definition at line 4558 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002)

PC[8] pin

Definition at line 4559 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003)

PD[8] pin

Definition at line 4560 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004)

PE[8] pin

Definition at line 4561 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006)

PF[8] pin

Definition at line 4562 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007)

PG[8] pin

Definition at line 4563 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0)

EXTI 9 configuration

Definition at line 4550 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000)

EXTI9 configuration.

PA[9] pin

Definition at line 4568 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010)

PB[9] pin

Definition at line 4569 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020)

PC[9] pin

Definition at line 4570 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030)

PD[9] pin

Definition at line 4571 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040)

PE[9] pin

Definition at line 4572 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060)

PF[9] pin

Definition at line 4573 of file stm32l1xx.h.

#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070)

PG[9] pin

Definition at line 4574 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F)

EXTI 12 configuration

Definition at line 4599 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000)

EXTI12 configuration.

PA[12] pin

Definition at line 4607 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001)

PB[12] pin

Definition at line 4608 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002)

PC[12] pin

Definition at line 4609 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003)

PD[12] pin

Definition at line 4610 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004)

PE[12] pin

Definition at line 4611 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006)

PF[12] pin

Definition at line 4612 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007)

PG[12] pin

Definition at line 4613 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0)

EXTI 13 configuration

Definition at line 4600 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000)

EXTI13 configuration.

PA[13] pin

Definition at line 4618 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010)

PB[13] pin

Definition at line 4619 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020)

PC[13] pin

Definition at line 4620 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030)

PD[13] pin

Definition at line 4621 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040)

PE[13] pin

Definition at line 4622 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060)

PF[13] pin

Definition at line 4623 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070)

PG[13] pin

Definition at line 4624 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00)

EXTI 14 configuration

Definition at line 4601 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000)

EXTI14 configuration.

PA[14] pin

Definition at line 4629 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100)

PB[14] pin

Definition at line 4630 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200)

PC[14] pin

Definition at line 4631 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300)

PD[14] pin

Definition at line 4632 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400)

PE[14] pin

Definition at line 4633 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600)

PF[14] pin

Definition at line 4634 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700)

PG[14] pin

Definition at line 4635 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)

EXTI 15 configuration

Definition at line 4602 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000)

EXTI15 configuration.

PA[15] pin

Definition at line 4640 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000)

PB[15] pin

Definition at line 4641 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000)

PC[15] pin

Definition at line 4642 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000)

PD[15] pin

Definition at line 4643 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000)

PE[15] pin

Definition at line 4644 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000)

PF[15] pin

Definition at line 4645 of file stm32l1xx.h.

#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000)

PG[15] pin

Definition at line 4646 of file stm32l1xx.h.

#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300)

Boot mode Config

Definition at line 4438 of file stm32l1xx.h.

Referenced by SYSCFG_GetBootMode().

#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4439 of file stm32l1xx.h.

#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4440 of file stm32l1xx.h.

#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003)

SYSCFG_Memory Remap Config

Definition at line 4435 of file stm32l1xx.h.

#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4436 of file stm32l1xx.h.

#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4437 of file stm32l1xx.h.

#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001)

SYSCFG PMC

Definition at line 4443 of file stm32l1xx.h.

Referenced by SYSCFG_USBPuCmd().

#define SysTick_CALIB_NOREF ((uint32_t)0x80000000)

The reference clock is not provided

Definition at line 5946 of file stm32l1xx.h.

#define SysTick_CALIB_SKEW ((uint32_t)0x40000000)

Calibration value is not exactly 10 ms

Definition at line 5945 of file stm32l1xx.h.

#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)

Reload value to use for 10ms timing

Definition at line 5944 of file stm32l1xx.h.

#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)

Clock source

Definition at line 5934 of file stm32l1xx.h.

#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)

Count Flag

Definition at line 5935 of file stm32l1xx.h.

#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001)

Counter enable

Definition at line 5932 of file stm32l1xx.h.

#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002)

Counting down to 0 pends the SysTick handler

Definition at line 5933 of file stm32l1xx.h.

#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)

Value to load into the SysTick Current Value Register when the counter reaches 0

Definition at line 5938 of file stm32l1xx.h.

#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)

Current value at the time the register is accessed

Definition at line 5941 of file stm32l1xx.h.

#define TIM_ARR_ARR ((uint16_t)0xFFFF)

actual auto-reload Value

Definition at line 5099 of file stm32l1xx.h.

#define TIM_CCER_CC1E ((uint16_t)0x0001)

Capture/Compare 1 output enable

Definition at line 5079 of file stm32l1xx.h.

Referenced by TI1_Config(), and TIM_OC1Init().

#define TIM_CCER_CC1NP ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

Definition at line 5081 of file stm32l1xx.h.

Referenced by TI1_Config().

#define TIM_CCER_CC1P ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

Definition at line 5080 of file stm32l1xx.h.

Referenced by TI1_Config(), TIM_EncoderInterfaceConfig(), TIM_OC1Init(), and TIM_OC1PolarityConfig().

#define TIM_CCER_CC2E ((uint16_t)0x0010)

Capture/Compare 2 output enable

Definition at line 5082 of file stm32l1xx.h.

Referenced by TI2_Config(), and TIM_OC2Init().

#define TIM_CCER_CC2NP ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

Definition at line 5084 of file stm32l1xx.h.

Referenced by TI2_Config().

#define TIM_CCER_CC2P ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

Definition at line 5083 of file stm32l1xx.h.

Referenced by TI2_Config(), TIM_EncoderInterfaceConfig(), TIM_OC2Init(), and TIM_OC2PolarityConfig().

#define TIM_CCER_CC3E ((uint16_t)0x0100)

Capture/Compare 3 output enable

Definition at line 5085 of file stm32l1xx.h.

Referenced by TI3_Config(), and TIM_OC3Init().

#define TIM_CCER_CC3NP ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

Definition at line 5087 of file stm32l1xx.h.

Referenced by TI3_Config().

#define TIM_CCER_CC3P ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

Definition at line 5086 of file stm32l1xx.h.

Referenced by TI3_Config(), TIM_OC3Init(), and TIM_OC3PolarityConfig().

#define TIM_CCER_CC4E ((uint16_t)0x1000)

Capture/Compare 4 output enable

Definition at line 5088 of file stm32l1xx.h.

Referenced by TI4_Config(), and TIM_OC4Init().

#define TIM_CCER_CC4NP ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

Definition at line 5090 of file stm32l1xx.h.

Referenced by TI4_Config().

#define TIM_CCER_CC4P ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

Definition at line 5089 of file stm32l1xx.h.

Referenced by TI4_Config(), TIM_OC4Init(), and TIM_OC4PolarityConfig().

#define TIM_CCMR1_CC1S ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

Definition at line 4977 of file stm32l1xx.h.

Referenced by TI1_Config(), TIM_EncoderInterfaceConfig(), and TIM_OC1Init().

#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4978 of file stm32l1xx.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4979 of file stm32l1xx.h.

#define TIM_CCMR1_CC2S ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

Definition at line 4991 of file stm32l1xx.h.

Referenced by TI2_Config(), and TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4992 of file stm32l1xx.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4993 of file stm32l1xx.h.

#define TIM_CCMR1_IC1F ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

Definition at line 5011 of file stm32l1xx.h.

Referenced by TI1_Config().

#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5012 of file stm32l1xx.h.

#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5013 of file stm32l1xx.h.

#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)

Bit 2

Definition at line 5014 of file stm32l1xx.h.

#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)

Bit 3

Definition at line 5015 of file stm32l1xx.h.

#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

Definition at line 5007 of file stm32l1xx.h.

Referenced by TIM_SetIC1Prescaler().

#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)

Bit 0

Definition at line 5008 of file stm32l1xx.h.

#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)

Bit 1

Definition at line 5009 of file stm32l1xx.h.

#define TIM_CCMR1_IC2F ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

Definition at line 5021 of file stm32l1xx.h.

Referenced by TI2_Config().

#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5022 of file stm32l1xx.h.

#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5023 of file stm32l1xx.h.

#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)

Bit 2

Definition at line 5024 of file stm32l1xx.h.

#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)

Bit 3

Definition at line 5025 of file stm32l1xx.h.

#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

Definition at line 5017 of file stm32l1xx.h.

Referenced by TIM_SetIC2Prescaler().

#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5018 of file stm32l1xx.h.

#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5019 of file stm32l1xx.h.

#define TIM_CCMR1_OC1CE ((uint16_t)0x0080)

Output Compare 1Clear Enable

Definition at line 4989 of file stm32l1xx.h.

Referenced by TIM_ClearOC1Ref().

#define TIM_CCMR1_OC1FE ((uint16_t)0x0004)

Output Compare 1 Fast enable

Definition at line 4981 of file stm32l1xx.h.

Referenced by TIM_OC1FastConfig().

#define TIM_CCMR1_OC1M ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

Definition at line 4984 of file stm32l1xx.h.

Referenced by TIM_ForcedOC1Config(), TIM_OC1Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4985 of file stm32l1xx.h.

#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4986 of file stm32l1xx.h.

#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4987 of file stm32l1xx.h.

#define TIM_CCMR1_OC1PE ((uint16_t)0x0008)

Output Compare 1 Preload enable

Definition at line 4982 of file stm32l1xx.h.

Referenced by TIM_OC1PreloadConfig().

#define TIM_CCMR1_OC2CE ((uint16_t)0x8000)

Output Compare 2 Clear Enable

Definition at line 5003 of file stm32l1xx.h.

Referenced by TIM_ClearOC2Ref().

#define TIM_CCMR1_OC2FE ((uint16_t)0x0400)

Output Compare 2 Fast enable

Definition at line 4995 of file stm32l1xx.h.

Referenced by TIM_OC2FastConfig().

#define TIM_CCMR1_OC2M ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

Definition at line 4998 of file stm32l1xx.h.

Referenced by TIM_ForcedOC2Config(), TIM_OC2Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4999 of file stm32l1xx.h.

#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5000 of file stm32l1xx.h.

#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)

Bit 2

Definition at line 5001 of file stm32l1xx.h.

#define TIM_CCMR1_OC2PE ((uint16_t)0x0800)

Output Compare 2 Preload enable

Definition at line 4996 of file stm32l1xx.h.

Referenced by TIM_OC2PreloadConfig().

#define TIM_CCMR2_CC3S ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

Definition at line 5028 of file stm32l1xx.h.

Referenced by TI3_Config().

#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)

Bit 0

Definition at line 5029 of file stm32l1xx.h.

#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)

Bit 1

Definition at line 5030 of file stm32l1xx.h.

#define TIM_CCMR2_CC4S ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

Definition at line 5042 of file stm32l1xx.h.

Referenced by TI4_Config().

#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)

Bit 0

Definition at line 5043 of file stm32l1xx.h.

#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)

Bit 1

Definition at line 5044 of file stm32l1xx.h.

#define TIM_CCMR2_IC3F ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

Definition at line 5062 of file stm32l1xx.h.

Referenced by TI3_Config().

#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5063 of file stm32l1xx.h.

#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5064 of file stm32l1xx.h.

#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)

Bit 2

Definition at line 5065 of file stm32l1xx.h.

#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)

Bit 3

Definition at line 5066 of file stm32l1xx.h.

#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

Definition at line 5058 of file stm32l1xx.h.

Referenced by TIM_SetIC3Prescaler().

#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)

Bit 0

Definition at line 5059 of file stm32l1xx.h.

#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)

Bit 1

Definition at line 5060 of file stm32l1xx.h.

#define TIM_CCMR2_IC4F ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

Definition at line 5072 of file stm32l1xx.h.

Referenced by TI4_Config().

#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5073 of file stm32l1xx.h.

#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5074 of file stm32l1xx.h.

#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)

Bit 2

Definition at line 5075 of file stm32l1xx.h.

#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)

Bit 3

Definition at line 5076 of file stm32l1xx.h.

#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

Definition at line 5068 of file stm32l1xx.h.

Referenced by TIM_SetIC4Prescaler().

#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5069 of file stm32l1xx.h.

#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5070 of file stm32l1xx.h.

#define TIM_CCMR2_OC3CE ((uint16_t)0x0080)

Output Compare 3 Clear Enable

Definition at line 5040 of file stm32l1xx.h.

Referenced by TIM_ClearOC3Ref().

#define TIM_CCMR2_OC3FE ((uint16_t)0x0004)

Output Compare 3 Fast enable

Definition at line 5032 of file stm32l1xx.h.

Referenced by TIM_OC3FastConfig().

#define TIM_CCMR2_OC3M ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

Definition at line 5035 of file stm32l1xx.h.

Referenced by TIM_ForcedOC3Config(), and TIM_OC3Init().

#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5036 of file stm32l1xx.h.

#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5037 of file stm32l1xx.h.

#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)

Bit 2

Definition at line 5038 of file stm32l1xx.h.

#define TIM_CCMR2_OC3PE ((uint16_t)0x0008)

Output Compare 3 Preload enable

Definition at line 5033 of file stm32l1xx.h.

Referenced by TIM_OC3PreloadConfig().

#define TIM_CCMR2_OC4CE ((uint16_t)0x8000)

Output Compare 4 Clear Enable

Definition at line 5054 of file stm32l1xx.h.

Referenced by TIM_ClearOC4Ref().

#define TIM_CCMR2_OC4FE ((uint16_t)0x0400)

Output Compare 4 Fast enable

Definition at line 5046 of file stm32l1xx.h.

Referenced by TIM_OC4FastConfig().

#define TIM_CCMR2_OC4M ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

Definition at line 5049 of file stm32l1xx.h.

Referenced by TIM_ForcedOC4Config(), and TIM_OC4Init().

#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5050 of file stm32l1xx.h.

#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5051 of file stm32l1xx.h.

#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)

Bit 2

Definition at line 5052 of file stm32l1xx.h.

#define TIM_CCMR2_OC4PE ((uint16_t)0x0800)

Output Compare 4 Preload enable

Definition at line 5047 of file stm32l1xx.h.

Referenced by TIM_OC4PreloadConfig().

#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)

Capture/Compare 1 Value

Definition at line 5102 of file stm32l1xx.h.

#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)

Capture/Compare 2 Value

Definition at line 5105 of file stm32l1xx.h.

#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)

Capture/Compare 3 Value

Definition at line 5108 of file stm32l1xx.h.

#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)

Capture/Compare 4 Value

Definition at line 5111 of file stm32l1xx.h.

#define TIM_CNT_CNT ((uint16_t)0xFFFF)

Counter Value

Definition at line 5093 of file stm32l1xx.h.

#define TIM_CR1_ARPE ((uint16_t)0x0080)

Auto-reload preload enable

Definition at line 4898 of file stm32l1xx.h.

Referenced by TIM_ARRPreloadConfig().

#define TIM_CR1_CEN ((uint16_t)0x0001)

Counter enable

Definition at line 4888 of file stm32l1xx.h.

Referenced by TIM_Cmd().

#define TIM_CR1_CKD ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

Definition at line 4900 of file stm32l1xx.h.

Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().

#define TIM_CR1_CKD_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4901 of file stm32l1xx.h.

#define TIM_CR1_CKD_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4902 of file stm32l1xx.h.

#define TIM_CR1_CMS ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

Definition at line 4894 of file stm32l1xx.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_CMS_0 ((uint16_t)0x0020)

Bit 0

Definition at line 4895 of file stm32l1xx.h.

#define TIM_CR1_CMS_1 ((uint16_t)0x0040)

Bit 1

Definition at line 4896 of file stm32l1xx.h.

#define TIM_CR1_DIR ((uint16_t)0x0010)

Direction

Definition at line 4892 of file stm32l1xx.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_OPM ((uint16_t)0x0008)

One pulse mode

Definition at line 4891 of file stm32l1xx.h.

Referenced by TIM_SelectOnePulseMode().

#define TIM_CR1_UDIS ((uint16_t)0x0002)

Update disable

Definition at line 4889 of file stm32l1xx.h.

Referenced by TIM_UpdateDisableConfig().

#define TIM_CR1_URS ((uint16_t)0x0004)

Update request source

Definition at line 4890 of file stm32l1xx.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_CR2_CCDS ((uint16_t)0x0008)

Capture/Compare DMA Selection

Definition at line 4905 of file stm32l1xx.h.

Referenced by TIM_SelectCCDMA().

#define TIM_CR2_MMS ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

Definition at line 4907 of file stm32l1xx.h.

Referenced by TIM_SelectOutputTrigger().

#define TIM_CR2_MMS_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4908 of file stm32l1xx.h.

#define TIM_CR2_MMS_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4909 of file stm32l1xx.h.

#define TIM_CR2_MMS_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4910 of file stm32l1xx.h.

#define TIM_CR2_TI1S ((uint16_t)0x0080)

TI1 Selection

Definition at line 4912 of file stm32l1xx.h.

Referenced by TIM_SelectHallSensor().

#define TIM_DCR_DBA ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

Definition at line 5114 of file stm32l1xx.h.

#define TIM_DCR_DBA_0 ((uint16_t)0x0001)

Bit 0

Definition at line 5115 of file stm32l1xx.h.

#define TIM_DCR_DBA_1 ((uint16_t)0x0002)

Bit 1

Definition at line 5116 of file stm32l1xx.h.

#define TIM_DCR_DBA_2 ((uint16_t)0x0004)

Bit 2

Definition at line 5117 of file stm32l1xx.h.

#define TIM_DCR_DBA_3 ((uint16_t)0x0008)

Bit 3

Definition at line 5118 of file stm32l1xx.h.

#define TIM_DCR_DBA_4 ((uint16_t)0x0010)

Bit 4

Definition at line 5119 of file stm32l1xx.h.

#define TIM_DCR_DBL ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

Definition at line 5121 of file stm32l1xx.h.

#define TIM_DCR_DBL_0 ((uint16_t)0x0100)

Bit 0

Definition at line 5122 of file stm32l1xx.h.

#define TIM_DCR_DBL_1 ((uint16_t)0x0200)

Bit 1

Definition at line 5123 of file stm32l1xx.h.

#define TIM_DCR_DBL_2 ((uint16_t)0x0400)

Bit 2

Definition at line 5124 of file stm32l1xx.h.

#define TIM_DCR_DBL_3 ((uint16_t)0x0800)

Bit 3

Definition at line 5125 of file stm32l1xx.h.

#define TIM_DCR_DBL_4 ((uint16_t)0x1000)

Bit 4

Definition at line 5126 of file stm32l1xx.h.

#define TIM_DIER_CC1DE ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

Definition at line 4950 of file stm32l1xx.h.

#define TIM_DIER_CC1IE ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

Definition at line 4944 of file stm32l1xx.h.

#define TIM_DIER_CC2DE ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

Definition at line 4951 of file stm32l1xx.h.

#define TIM_DIER_CC2IE ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

Definition at line 4945 of file stm32l1xx.h.

#define TIM_DIER_CC3DE ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

Definition at line 4952 of file stm32l1xx.h.

#define TIM_DIER_CC3IE ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

Definition at line 4946 of file stm32l1xx.h.

#define TIM_DIER_CC4DE ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

Definition at line 4953 of file stm32l1xx.h.

#define TIM_DIER_CC4IE ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

Definition at line 4947 of file stm32l1xx.h.

#define TIM_DIER_TDE ((uint16_t)0x4000)

Trigger DMA request enable

Definition at line 4954 of file stm32l1xx.h.

#define TIM_DIER_TIE ((uint16_t)0x0040)

Trigger interrupt enable

Definition at line 4948 of file stm32l1xx.h.

#define TIM_DIER_UDE ((uint16_t)0x0100)

Update DMA request enable

Definition at line 4949 of file stm32l1xx.h.

#define TIM_DIER_UIE ((uint16_t)0x0001)

Update interrupt enable

Definition at line 4943 of file stm32l1xx.h.

#define TIM_DMAR_DMAB ((uint16_t)0xFFFF)

DMA register for burst accesses

Definition at line 5129 of file stm32l1xx.h.

#define TIM_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation

Definition at line 4970 of file stm32l1xx.h.

#define TIM_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation

Definition at line 4971 of file stm32l1xx.h.

#define TIM_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation

Definition at line 4972 of file stm32l1xx.h.

#define TIM_EGR_CC4G ((uint8_t)0x10)

Capture/Compare 4 Generation

Definition at line 4973 of file stm32l1xx.h.

#define TIM_EGR_TG ((uint8_t)0x40)

Trigger Generation

Definition at line 4974 of file stm32l1xx.h.

#define TIM_EGR_UG ((uint8_t)0x01)

Update Generation

Definition at line 4969 of file stm32l1xx.h.

#define TIM_OR_TI1RMP ((uint16_t)0x0003)

Option register for TI1 Remapping

Definition at line 5132 of file stm32l1xx.h.

#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001)

Bit 0

Definition at line 5133 of file stm32l1xx.h.

#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002)

Bit 1

Definition at line 5134 of file stm32l1xx.h.

#define TIM_PSC_PSC ((uint16_t)0xFFFF)

Prescaler Value

Definition at line 5096 of file stm32l1xx.h.

#define TIM_SMCR_ECE ((uint16_t)0x4000)

External clock enable

Definition at line 4939 of file stm32l1xx.h.

Referenced by TIM_ETRClockMode2Config().

#define TIM_SMCR_ETF ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

Definition at line 4929 of file stm32l1xx.h.

#define TIM_SMCR_ETF_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4930 of file stm32l1xx.h.

#define TIM_SMCR_ETF_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4931 of file stm32l1xx.h.

#define TIM_SMCR_ETF_2 ((uint16_t)0x0400)

Bit 2

Definition at line 4932 of file stm32l1xx.h.

#define TIM_SMCR_ETF_3 ((uint16_t)0x0800)

Bit 3

Definition at line 4933 of file stm32l1xx.h.

#define TIM_SMCR_ETP ((uint16_t)0x8000)

External trigger polarity

Definition at line 4940 of file stm32l1xx.h.

#define TIM_SMCR_ETPS ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

Definition at line 4935 of file stm32l1xx.h.

#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4936 of file stm32l1xx.h.

#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4937 of file stm32l1xx.h.

#define TIM_SMCR_MSM ((uint16_t)0x0080)

Master/slave mode

Definition at line 4927 of file stm32l1xx.h.

Referenced by TIM_SelectMasterSlaveMode().

#define TIM_SMCR_OCCS ((uint16_t)0x0008)

OCCS bits (OCref Clear Selection)

Definition at line 4920 of file stm32l1xx.h.

Referenced by TIM_SelectOCREFClear().

#define TIM_SMCR_SMS ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

Definition at line 4915 of file stm32l1xx.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_InternalClockConfig(), and TIM_SelectSlaveMode().

#define TIM_SMCR_SMS_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4916 of file stm32l1xx.h.

#define TIM_SMCR_SMS_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4917 of file stm32l1xx.h.

#define TIM_SMCR_SMS_2 ((uint16_t)0x0004)

Bit 2

Definition at line 4918 of file stm32l1xx.h.

#define TIM_SMCR_TS ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

Definition at line 4922 of file stm32l1xx.h.

Referenced by TIM_ETRClockMode1Config(), and TIM_SelectInputTrigger().

#define TIM_SMCR_TS_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4923 of file stm32l1xx.h.

#define TIM_SMCR_TS_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4924 of file stm32l1xx.h.

#define TIM_SMCR_TS_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4925 of file stm32l1xx.h.

#define TIM_SR_CC1IF ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

Definition at line 4958 of file stm32l1xx.h.

#define TIM_SR_CC1OF ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

Definition at line 4963 of file stm32l1xx.h.

#define TIM_SR_CC2IF ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

Definition at line 4959 of file stm32l1xx.h.

#define TIM_SR_CC2OF ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

Definition at line 4964 of file stm32l1xx.h.

#define TIM_SR_CC3IF ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

Definition at line 4960 of file stm32l1xx.h.

#define TIM_SR_CC3OF ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

Definition at line 4965 of file stm32l1xx.h.

#define TIM_SR_CC4IF ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

Definition at line 4961 of file stm32l1xx.h.

#define TIM_SR_CC4OF ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

Definition at line 4966 of file stm32l1xx.h.

#define TIM_SR_TIF ((uint16_t)0x0040)

Trigger interrupt Flag

Definition at line 4962 of file stm32l1xx.h.

#define TIM_SR_UIF ((uint16_t)0x0001)

Update interrupt Flag

Definition at line 4957 of file stm32l1xx.h.

#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F)

Fraction of USARTDIV

Definition at line 5158 of file stm32l1xx.h.

#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0)

Mantissa of USARTDIV

Definition at line 5159 of file stm32l1xx.h.

#define USART_CR1_IDLEIE ((uint16_t)0x0010)

IDLE Interrupt Enable

Definition at line 5166 of file stm32l1xx.h.

#define USART_CR1_M ((uint16_t)0x1000)

Word length

Definition at line 5174 of file stm32l1xx.h.

#define USART_CR1_OVER8 ((uint16_t)0x8000)

Oversampling by 8-bit mode

Definition at line 5176 of file stm32l1xx.h.

Referenced by USART_Init(), and USART_OverSampling8Cmd().

#define USART_CR1_PCE ((uint16_t)0x0400)

Parity Control Enable

Definition at line 5172 of file stm32l1xx.h.

#define USART_CR1_PEIE ((uint16_t)0x0100)

PE Interrupt Enable

Definition at line 5170 of file stm32l1xx.h.

#define USART_CR1_PS ((uint16_t)0x0200)

Parity Selection

Definition at line 5171 of file stm32l1xx.h.

#define USART_CR1_RE ((uint16_t)0x0004)

Receiver Enable

Definition at line 5164 of file stm32l1xx.h.

#define USART_CR1_RWU ((uint16_t)0x0002)

Receiver wakeup

Definition at line 5163 of file stm32l1xx.h.

Referenced by USART_ReceiverWakeUpCmd().

#define USART_CR1_RXNEIE ((uint16_t)0x0020)

RXNE Interrupt Enable

Definition at line 5167 of file stm32l1xx.h.

#define USART_CR1_SBK ((uint16_t)0x0001)

Send Break

Definition at line 5162 of file stm32l1xx.h.

Referenced by USART_SendBreak().

#define USART_CR1_TCIE ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

Definition at line 5168 of file stm32l1xx.h.

#define USART_CR1_TE ((uint16_t)0x0008)

Transmitter Enable

Definition at line 5165 of file stm32l1xx.h.

#define USART_CR1_TXEIE ((uint16_t)0x0080)

PE Interrupt Enable

Definition at line 5169 of file stm32l1xx.h.

#define USART_CR1_UE ((uint16_t)0x2000)

USART Enable

Definition at line 5175 of file stm32l1xx.h.

Referenced by USART_Cmd().

#define USART_CR1_WAKE ((uint16_t)0x0800)

Wakeup method

Definition at line 5173 of file stm32l1xx.h.

Referenced by USART_WakeUpConfig().

#define USART_CR2_ADD ((uint16_t)0x000F)

Address of the USART node

Definition at line 5179 of file stm32l1xx.h.

Referenced by USART_SetAddress().

#define USART_CR2_CLKEN ((uint16_t)0x0800)

Clock Enable

Definition at line 5185 of file stm32l1xx.h.

#define USART_CR2_CPHA ((uint16_t)0x0200)

Clock Phase

Definition at line 5183 of file stm32l1xx.h.

#define USART_CR2_CPOL ((uint16_t)0x0400)

Clock Polarity

Definition at line 5184 of file stm32l1xx.h.

#define USART_CR2_LBCL ((uint16_t)0x0100)

Last Bit Clock pulse

Definition at line 5182 of file stm32l1xx.h.

#define USART_CR2_LBDIE ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

Definition at line 5181 of file stm32l1xx.h.

#define USART_CR2_LBDL ((uint16_t)0x0020)

LIN Break Detection Length

Definition at line 5180 of file stm32l1xx.h.

Referenced by USART_LINBreakDetectLengthConfig().

#define USART_CR2_LINEN ((uint16_t)0x4000)

LIN mode enable

Definition at line 5191 of file stm32l1xx.h.

Referenced by USART_LINCmd().

#define USART_CR2_STOP ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

Definition at line 5187 of file stm32l1xx.h.

Referenced by USART_Init().

#define USART_CR2_STOP_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5188 of file stm32l1xx.h.

#define USART_CR2_STOP_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5189 of file stm32l1xx.h.

#define USART_CR3_CTSE ((uint16_t)0x0200)

CTS Enable

Definition at line 5203 of file stm32l1xx.h.

#define USART_CR3_CTSIE ((uint16_t)0x0400)

CTS Interrupt Enable

Definition at line 5204 of file stm32l1xx.h.

#define USART_CR3_DMAR ((uint16_t)0x0040)

DMA Enable Receiver

Definition at line 5200 of file stm32l1xx.h.

#define USART_CR3_DMAT ((uint16_t)0x0080)

DMA Enable Transmitter

Definition at line 5201 of file stm32l1xx.h.

#define USART_CR3_EIE ((uint16_t)0x0001)

Error Interrupt Enable

Definition at line 5194 of file stm32l1xx.h.

#define USART_CR3_HDSEL ((uint16_t)0x0008)

Half-Duplex Selection

Definition at line 5197 of file stm32l1xx.h.

Referenced by USART_HalfDuplexCmd().

#define USART_CR3_IREN ((uint16_t)0x0002)

IrDA mode Enable

Definition at line 5195 of file stm32l1xx.h.

Referenced by USART_IrDACmd().

#define USART_CR3_IRLP ((uint16_t)0x0004)

IrDA Low-Power

Definition at line 5196 of file stm32l1xx.h.

Referenced by USART_IrDAConfig().

#define USART_CR3_NACK ((uint16_t)0x0010)

Smartcard NACK enable

Definition at line 5198 of file stm32l1xx.h.

Referenced by USART_SmartCardNACKCmd().

#define USART_CR3_ONEBIT ((uint16_t)0x0800)

One sample bit method enable

Definition at line 5205 of file stm32l1xx.h.

Referenced by USART_OneBitMethodCmd().

#define USART_CR3_RTSE ((uint16_t)0x0100)

RTS Enable

Definition at line 5202 of file stm32l1xx.h.

#define USART_CR3_SCEN ((uint16_t)0x0020)

Smartcard mode enable

Definition at line 5199 of file stm32l1xx.h.

Referenced by USART_SmartCardCmd().

#define USART_DR_DR ((uint16_t)0x01FF)

Data value

Definition at line 5155 of file stm32l1xx.h.

#define USART_GTPR_GT ((uint16_t)0xFF00)

Guard time value

Definition at line 5218 of file stm32l1xx.h.

Referenced by USART_SetPrescaler().

#define USART_GTPR_PSC ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

Definition at line 5208 of file stm32l1xx.h.

Referenced by USART_SetGuardTime().

#define USART_GTPR_PSC_0 ((uint16_t)0x0001)

Bit 0

Definition at line 5209 of file stm32l1xx.h.

#define USART_GTPR_PSC_1 ((uint16_t)0x0002)

Bit 1

Definition at line 5210 of file stm32l1xx.h.

#define USART_GTPR_PSC_2 ((uint16_t)0x0004)

Bit 2

Definition at line 5211 of file stm32l1xx.h.

#define USART_GTPR_PSC_3 ((uint16_t)0x0008)

Bit 3

Definition at line 5212 of file stm32l1xx.h.

#define USART_GTPR_PSC_4 ((uint16_t)0x0010)

Bit 4

Definition at line 5213 of file stm32l1xx.h.

#define USART_GTPR_PSC_5 ((uint16_t)0x0020)

Bit 5

Definition at line 5214 of file stm32l1xx.h.

#define USART_GTPR_PSC_6 ((uint16_t)0x0040)

Bit 6

Definition at line 5215 of file stm32l1xx.h.

#define USART_GTPR_PSC_7 ((uint16_t)0x0080)

Bit 7

Definition at line 5216 of file stm32l1xx.h.

#define USART_SR_CTS ((uint16_t)0x0200)

CTS Flag

Definition at line 5152 of file stm32l1xx.h.

#define USART_SR_FE ((uint16_t)0x0002)

Framing Error

Definition at line 5144 of file stm32l1xx.h.

#define USART_SR_IDLE ((uint16_t)0x0010)

IDLE line detected

Definition at line 5147 of file stm32l1xx.h.

#define USART_SR_LBD ((uint16_t)0x0100)

LIN Break Detection Flag

Definition at line 5151 of file stm32l1xx.h.

#define USART_SR_NE ((uint16_t)0x0004)

Noise Error Flag

Definition at line 5145 of file stm32l1xx.h.

#define USART_SR_ORE ((uint16_t)0x0008)

OverRun Error

Definition at line 5146 of file stm32l1xx.h.

#define USART_SR_PE ((uint16_t)0x0001)

Parity Error

Definition at line 5143 of file stm32l1xx.h.

#define USART_SR_RXNE ((uint16_t)0x0020)

Read Data Register Not Empty

Definition at line 5148 of file stm32l1xx.h.

#define USART_SR_TC ((uint16_t)0x0040)

Transmission Complete

Definition at line 5149 of file stm32l1xx.h.

#define USART_SR_TXE ((uint16_t)0x0080)

Transmit Data Register Empty

Definition at line 5150 of file stm32l1xx.h.

#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)

Reception Buffer Address 0

Definition at line 5573 of file stm32l1xx.h.

#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 0

Definition at line 5471 of file stm32l1xx.h.

#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)

Reception Buffer Address 1

Definition at line 5576 of file stm32l1xx.h.

#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 1

Definition at line 5474 of file stm32l1xx.h.

#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)

Reception Buffer Address 2

Definition at line 5579 of file stm32l1xx.h.

#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 2

Definition at line 5477 of file stm32l1xx.h.

#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)

Reception Buffer Address 3

Definition at line 5582 of file stm32l1xx.h.

#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 3

Definition at line 5480 of file stm32l1xx.h.

#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)

Reception Buffer Address 4

Definition at line 5585 of file stm32l1xx.h.

#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 4

Definition at line 5483 of file stm32l1xx.h.

#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)

Reception Buffer Address 5

Definition at line 5588 of file stm32l1xx.h.

#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 5

Definition at line 5486 of file stm32l1xx.h.

#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)

Reception Buffer Address 6

Definition at line 5591 of file stm32l1xx.h.

#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 6

Definition at line 5489 of file stm32l1xx.h.

#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)

Reception Buffer Address 7

Definition at line 5594 of file stm32l1xx.h.

#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 7

Definition at line 5492 of file stm32l1xx.h.

#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8)

Buffer Table Buffer descriptor table

Definition at line 5467 of file stm32l1xx.h.

#define USB_CNTR_CTRM ((uint16_t)0x8000)

Correct Transfer Interrupt Mask

Definition at line 5433 of file stm32l1xx.h.

#define USB_CNTR_ERRM ((uint16_t)0x2000)

Error Interrupt Mask

Definition at line 5431 of file stm32l1xx.h.

#define USB_CNTR_ESOFM ((uint16_t)0x0100)

Expected Start Of Frame Interrupt Mask

Definition at line 5426 of file stm32l1xx.h.

#define USB_CNTR_FRES ((uint16_t)0x0001)

Force USB Reset

Definition at line 5421 of file stm32l1xx.h.

#define USB_CNTR_FSUSP ((uint16_t)0x0008)

Force suspend

Definition at line 5424 of file stm32l1xx.h.

#define USB_CNTR_LP_MODE ((uint16_t)0x0004)

Low-power mode

Definition at line 5423 of file stm32l1xx.h.

#define USB_CNTR_PDWN ((uint16_t)0x0002)

Power down

Definition at line 5422 of file stm32l1xx.h.

#define USB_CNTR_PMAOVRM ((uint16_t)0x4000)

Packet Memory Area Over / Underrun Interrupt Mask

Definition at line 5432 of file stm32l1xx.h.

#define USB_CNTR_RESETM ((uint16_t)0x0400)

RESET Interrupt Mask

Definition at line 5428 of file stm32l1xx.h.

#define USB_CNTR_RESUME ((uint16_t)0x0010)

Resume request

Definition at line 5425 of file stm32l1xx.h.

#define USB_CNTR_SOFM ((uint16_t)0x0200)

Start Of Frame Interrupt Mask

Definition at line 5427 of file stm32l1xx.h.

#define USB_CNTR_SUSPM ((uint16_t)0x0800)

Suspend mode Interrupt Mask

Definition at line 5429 of file stm32l1xx.h.

#define USB_CNTR_WKUPM ((uint16_t)0x1000)

Wakeup Interrupt Mask

Definition at line 5430 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5706 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5697 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5699 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5700 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5701 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5702 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5703 of file stm32l1xx.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5704 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5718 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5709 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5711 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 1

Definition at line 5712 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5713 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5714 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5715 of file stm32l1xx.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5716 of file stm32l1xx.h.

#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5608 of file stm32l1xx.h.

#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5599 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5601 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5602 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5603 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5604 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5605 of file stm32l1xx.h.

#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5606 of file stm32l1xx.h.

#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 0 (low)

Definition at line 5523 of file stm32l1xx.h.

#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 0 (high)

Definition at line 5526 of file stm32l1xx.h.

#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)

Transmission Byte Count 0

Definition at line 5497 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5730 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5721 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5723 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5724 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5725 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5726 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5727 of file stm32l1xx.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5728 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5742 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5733 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5735 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5736 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5737 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5738 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5739 of file stm32l1xx.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5740 of file stm32l1xx.h.

#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5620 of file stm32l1xx.h.

#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5611 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5613 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5614 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5615 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5616 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5617 of file stm32l1xx.h.

#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5618 of file stm32l1xx.h.

#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 1 (low)

Definition at line 5529 of file stm32l1xx.h.

#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 1 (high)

Definition at line 5532 of file stm32l1xx.h.

#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)

Transmission Byte Count 1

Definition at line 5500 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5754 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5745 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5747 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5748 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5749 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5750 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5751 of file stm32l1xx.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5752 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5766 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5757 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5759 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5760 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5761 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5762 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5763 of file stm32l1xx.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5764 of file stm32l1xx.h.

#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5632 of file stm32l1xx.h.

#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5623 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5625 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5626 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5627 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5628 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5629 of file stm32l1xx.h.

#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5630 of file stm32l1xx.h.

#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 2 (low)

Definition at line 5535 of file stm32l1xx.h.

#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 2 (high)

Definition at line 5538 of file stm32l1xx.h.

#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)

Transmission Byte Count 2

Definition at line 5503 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5778 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5769 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5771 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5772 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5773 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5774 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5775 of file stm32l1xx.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5776 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5790 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5781 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5783 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5784 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5785 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5786 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5787 of file stm32l1xx.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5788 of file stm32l1xx.h.

#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5644 of file stm32l1xx.h.

#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5635 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5637 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5638 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5639 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5640 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5641 of file stm32l1xx.h.

#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5642 of file stm32l1xx.h.

#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)

Transmission Byte Count 3 (low)

Definition at line 5541 of file stm32l1xx.h.

#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)

Transmission Byte Count 3 (high)

Definition at line 5544 of file stm32l1xx.h.

#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)

Transmission Byte Count 3

Definition at line 5506 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5802 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5793 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5795 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5796 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5797 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5798 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5799 of file stm32l1xx.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5800 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5814 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5805 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5807 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5808 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5809 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5810 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5811 of file stm32l1xx.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5812 of file stm32l1xx.h.

#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5656 of file stm32l1xx.h.

#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5647 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5649 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5650 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5651 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5652 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5653 of file stm32l1xx.h.

#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5654 of file stm32l1xx.h.

#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 4 (low)

Definition at line 5547 of file stm32l1xx.h.

#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 4 (high)

Definition at line 5550 of file stm32l1xx.h.

#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)

Transmission Byte Count 4

Definition at line 5509 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5826 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5817 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5819 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5820 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5821 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5822 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5823 of file stm32l1xx.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5824 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5838 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5829 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5831 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5832 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5833 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5834 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5835 of file stm32l1xx.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5836 of file stm32l1xx.h.

#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5668 of file stm32l1xx.h.

#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5659 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5661 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5662 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5663 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5664 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5665 of file stm32l1xx.h.

#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5666 of file stm32l1xx.h.

#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 5 (low)

Definition at line 5553 of file stm32l1xx.h.

#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 5 (high)

Definition at line 5556 of file stm32l1xx.h.

#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)

Transmission Byte Count 5

Definition at line 5512 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5850 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5841 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5843 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5844 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5845 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5846 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5847 of file stm32l1xx.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5848 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5862 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5853 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5855 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5856 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5857 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5858 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5859 of file stm32l1xx.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5860 of file stm32l1xx.h.

#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5680 of file stm32l1xx.h.

#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5671 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5673 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5674 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5675 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5676 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5677 of file stm32l1xx.h.

#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5678 of file stm32l1xx.h.

#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 6 (low)

Definition at line 5559 of file stm32l1xx.h.

#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 6 (high)

Definition at line 5562 of file stm32l1xx.h.

#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)

Transmission Byte Count 6

Definition at line 5515 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 5874 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 5865 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 5867 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 5868 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 5869 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 5870 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 5871 of file stm32l1xx.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 5872 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 5886 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 5877 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 5879 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 5880 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 5881 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 5882 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 5883 of file stm32l1xx.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 5884 of file stm32l1xx.h.

#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5692 of file stm32l1xx.h.

#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5683 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5685 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5686 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5687 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5688 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5689 of file stm32l1xx.h.

#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5690 of file stm32l1xx.h.

#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 7 (low)

Definition at line 5565 of file stm32l1xx.h.

#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 7 (high)

Definition at line 5568 of file stm32l1xx.h.

#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)

Transmission Byte Count 7

Definition at line 5518 of file stm32l1xx.h.

#define USB_DADDR_ADD ((uint8_t)0x7F)

ADD[6:0] bits (Device Address)

Definition at line 5455 of file stm32l1xx.h.

#define USB_DADDR_ADD0 ((uint8_t)0x01)

Bit 0

Definition at line 5456 of file stm32l1xx.h.

#define USB_DADDR_ADD1 ((uint8_t)0x02)

Bit 1

Definition at line 5457 of file stm32l1xx.h.

#define USB_DADDR_ADD2 ((uint8_t)0x04)

Bit 2

Definition at line 5458 of file stm32l1xx.h.

#define USB_DADDR_ADD3 ((uint8_t)0x08)

Bit 3

Definition at line 5459 of file stm32l1xx.h.

#define USB_DADDR_ADD4 ((uint8_t)0x10)

Bit 4

Definition at line 5460 of file stm32l1xx.h.

#define USB_DADDR_ADD5 ((uint8_t)0x20)

Bit 5

Definition at line 5461 of file stm32l1xx.h.

#define USB_DADDR_ADD6 ((uint8_t)0x40)

Bit 6

Definition at line 5462 of file stm32l1xx.h.

#define USB_DADDR_EF ((uint8_t)0x80)

Enable Function

Definition at line 5464 of file stm32l1xx.h.

#define USB_EP0R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5249 of file stm32l1xx.h.

#define USB_EP0R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5235 of file stm32l1xx.h.

#define USB_EP0R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5248 of file stm32l1xx.h.

#define USB_EP0R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5234 of file stm32l1xx.h.

#define USB_EP0R_EA ((uint16_t)0x000F)

<Endpoint-specific registers Endpoint Address

Definition at line 5228 of file stm32l1xx.h.

#define USB_EP0R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5236 of file stm32l1xx.h.

#define USB_EP0R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5238 of file stm32l1xx.h.

#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5239 of file stm32l1xx.h.

#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5240 of file stm32l1xx.h.

#define USB_EP0R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5242 of file stm32l1xx.h.

#define USB_EP0R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5244 of file stm32l1xx.h.

#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5245 of file stm32l1xx.h.

#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5246 of file stm32l1xx.h.

#define USB_EP0R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5230 of file stm32l1xx.h.

#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5231 of file stm32l1xx.h.

#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5232 of file stm32l1xx.h.

#define USB_EP1R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5273 of file stm32l1xx.h.

#define USB_EP1R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5259 of file stm32l1xx.h.

#define USB_EP1R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5272 of file stm32l1xx.h.

#define USB_EP1R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5258 of file stm32l1xx.h.

#define USB_EP1R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5252 of file stm32l1xx.h.

#define USB_EP1R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5260 of file stm32l1xx.h.

#define USB_EP1R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5262 of file stm32l1xx.h.

#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5263 of file stm32l1xx.h.

#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5264 of file stm32l1xx.h.

#define USB_EP1R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5266 of file stm32l1xx.h.

#define USB_EP1R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5268 of file stm32l1xx.h.

#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5269 of file stm32l1xx.h.

#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5270 of file stm32l1xx.h.

#define USB_EP1R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5254 of file stm32l1xx.h.

#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5255 of file stm32l1xx.h.

#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5256 of file stm32l1xx.h.

#define USB_EP2R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5297 of file stm32l1xx.h.

#define USB_EP2R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5283 of file stm32l1xx.h.

#define USB_EP2R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5296 of file stm32l1xx.h.

#define USB_EP2R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5282 of file stm32l1xx.h.

#define USB_EP2R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5276 of file stm32l1xx.h.

#define USB_EP2R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5284 of file stm32l1xx.h.

#define USB_EP2R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5286 of file stm32l1xx.h.

#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5287 of file stm32l1xx.h.

#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5288 of file stm32l1xx.h.

#define USB_EP2R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5290 of file stm32l1xx.h.

#define USB_EP2R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5292 of file stm32l1xx.h.

#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5293 of file stm32l1xx.h.

#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5294 of file stm32l1xx.h.

#define USB_EP2R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5278 of file stm32l1xx.h.

#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5279 of file stm32l1xx.h.

#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5280 of file stm32l1xx.h.

#define USB_EP3R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5321 of file stm32l1xx.h.

#define USB_EP3R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5307 of file stm32l1xx.h.

#define USB_EP3R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5320 of file stm32l1xx.h.

#define USB_EP3R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5306 of file stm32l1xx.h.

#define USB_EP3R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5300 of file stm32l1xx.h.

#define USB_EP3R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5308 of file stm32l1xx.h.

#define USB_EP3R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5310 of file stm32l1xx.h.

#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5311 of file stm32l1xx.h.

#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5312 of file stm32l1xx.h.

#define USB_EP3R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5314 of file stm32l1xx.h.

#define USB_EP3R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5316 of file stm32l1xx.h.

#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5317 of file stm32l1xx.h.

#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5318 of file stm32l1xx.h.

#define USB_EP3R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5302 of file stm32l1xx.h.

#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5303 of file stm32l1xx.h.

#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5304 of file stm32l1xx.h.

#define USB_EP4R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5345 of file stm32l1xx.h.

#define USB_EP4R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5331 of file stm32l1xx.h.

#define USB_EP4R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5344 of file stm32l1xx.h.

#define USB_EP4R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5330 of file stm32l1xx.h.

#define USB_EP4R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5324 of file stm32l1xx.h.

#define USB_EP4R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5332 of file stm32l1xx.h.

#define USB_EP4R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5334 of file stm32l1xx.h.

#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5335 of file stm32l1xx.h.

#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5336 of file stm32l1xx.h.

#define USB_EP4R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5338 of file stm32l1xx.h.

#define USB_EP4R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5340 of file stm32l1xx.h.

#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5341 of file stm32l1xx.h.

#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5342 of file stm32l1xx.h.

#define USB_EP4R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5326 of file stm32l1xx.h.

#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5327 of file stm32l1xx.h.

#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5328 of file stm32l1xx.h.

#define USB_EP5R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5369 of file stm32l1xx.h.

#define USB_EP5R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5355 of file stm32l1xx.h.

#define USB_EP5R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5368 of file stm32l1xx.h.

#define USB_EP5R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5354 of file stm32l1xx.h.

#define USB_EP5R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5348 of file stm32l1xx.h.

#define USB_EP5R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5356 of file stm32l1xx.h.

#define USB_EP5R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5358 of file stm32l1xx.h.

#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5359 of file stm32l1xx.h.

#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5360 of file stm32l1xx.h.

#define USB_EP5R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5362 of file stm32l1xx.h.

#define USB_EP5R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5364 of file stm32l1xx.h.

#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5365 of file stm32l1xx.h.

#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5366 of file stm32l1xx.h.

#define USB_EP5R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5350 of file stm32l1xx.h.

#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5351 of file stm32l1xx.h.

#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5352 of file stm32l1xx.h.

#define USB_EP6R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5393 of file stm32l1xx.h.

#define USB_EP6R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5379 of file stm32l1xx.h.

#define USB_EP6R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5392 of file stm32l1xx.h.

#define USB_EP6R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5378 of file stm32l1xx.h.

#define USB_EP6R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5372 of file stm32l1xx.h.

#define USB_EP6R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5380 of file stm32l1xx.h.

#define USB_EP6R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5382 of file stm32l1xx.h.

#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5383 of file stm32l1xx.h.

#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5384 of file stm32l1xx.h.

#define USB_EP6R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5386 of file stm32l1xx.h.

#define USB_EP6R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5388 of file stm32l1xx.h.

#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5389 of file stm32l1xx.h.

#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5390 of file stm32l1xx.h.

#define USB_EP6R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5374 of file stm32l1xx.h.

#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5375 of file stm32l1xx.h.

#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5376 of file stm32l1xx.h.

#define USB_EP7R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception Common registers

Definition at line 5417 of file stm32l1xx.h.

#define USB_EP7R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5403 of file stm32l1xx.h.

#define USB_EP7R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5416 of file stm32l1xx.h.

#define USB_EP7R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5402 of file stm32l1xx.h.

#define USB_EP7R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5396 of file stm32l1xx.h.

#define USB_EP7R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5404 of file stm32l1xx.h.

#define USB_EP7R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5406 of file stm32l1xx.h.

#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5407 of file stm32l1xx.h.

#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5408 of file stm32l1xx.h.

#define USB_EP7R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5410 of file stm32l1xx.h.

#define USB_EP7R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5412 of file stm32l1xx.h.

#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5413 of file stm32l1xx.h.

#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5414 of file stm32l1xx.h.

#define USB_EP7R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5398 of file stm32l1xx.h.

#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5399 of file stm32l1xx.h.

#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5400 of file stm32l1xx.h.

#define USB_FNR_FN ((uint16_t)0x07FF)

Frame Number

Definition at line 5448 of file stm32l1xx.h.

#define USB_FNR_LCK ((uint16_t)0x2000)

Locked

Definition at line 5450 of file stm32l1xx.h.

#define USB_FNR_LSOF ((uint16_t)0x1800)

Lost SOF

Definition at line 5449 of file stm32l1xx.h.

#define USB_FNR_RXDM ((uint16_t)0x4000)

Receive Data - Line Status

Definition at line 5451 of file stm32l1xx.h.

#define USB_FNR_RXDP ((uint16_t)0x8000)

Receive Data + Line Status

Definition at line 5452 of file stm32l1xx.h.

#define USB_ISTR_CTR ((uint16_t)0x8000)

Correct Transfer

Definition at line 5445 of file stm32l1xx.h.

#define USB_ISTR_DIR ((uint16_t)0x0010)

Direction of transaction

Definition at line 5437 of file stm32l1xx.h.

#define USB_ISTR_EP_ID ((uint16_t)0x000F)

Endpoint Identifier

Definition at line 5436 of file stm32l1xx.h.

#define USB_ISTR_ERR ((uint16_t)0x2000)

Error

Definition at line 5443 of file stm32l1xx.h.

#define USB_ISTR_ESOF ((uint16_t)0x0100)

Expected Start Of Frame

Definition at line 5438 of file stm32l1xx.h.

#define USB_ISTR_PMAOVR ((uint16_t)0x4000)

Packet Memory Area Over / Underrun

Definition at line 5444 of file stm32l1xx.h.

#define USB_ISTR_RESET ((uint16_t)0x0400)

USB RESET request

Definition at line 5440 of file stm32l1xx.h.

#define USB_ISTR_SOF ((uint16_t)0x0200)

Start Of Frame

Definition at line 5439 of file stm32l1xx.h.

#define USB_ISTR_SUSP ((uint16_t)0x0800)

Suspend mode request

Definition at line 5441 of file stm32l1xx.h.

#define USB_ISTR_WKUP ((uint16_t)0x1000)

Wake up

Definition at line 5442 of file stm32l1xx.h.

#define WWDG_CFR_EWI ((uint16_t)0x0200)

Early Wakeup Interrupt

Definition at line 5920 of file stm32l1xx.h.

#define WWDG_CFR_W ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

Definition at line 5907 of file stm32l1xx.h.

#define WWDG_CFR_W0 ((uint16_t)0x0001)

Bit 0

Definition at line 5908 of file stm32l1xx.h.

#define WWDG_CFR_W1 ((uint16_t)0x0002)

Bit 1

Definition at line 5909 of file stm32l1xx.h.

#define WWDG_CFR_W2 ((uint16_t)0x0004)

Bit 2

Definition at line 5910 of file stm32l1xx.h.

#define WWDG_CFR_W3 ((uint16_t)0x0008)

Bit 3

Definition at line 5911 of file stm32l1xx.h.

#define WWDG_CFR_W4 ((uint16_t)0x0010)

Bit 4

Definition at line 5912 of file stm32l1xx.h.

#define WWDG_CFR_W5 ((uint16_t)0x0020)

Bit 5

Definition at line 5913 of file stm32l1xx.h.

#define WWDG_CFR_W6 ((uint16_t)0x0040)

Bit 6

Definition at line 5914 of file stm32l1xx.h.

#define WWDG_CFR_WDGTB ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

Definition at line 5916 of file stm32l1xx.h.

#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)

Bit 0

Definition at line 5917 of file stm32l1xx.h.

#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)

Bit 1

Definition at line 5918 of file stm32l1xx.h.

#define WWDG_CR_T ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

Definition at line 5895 of file stm32l1xx.h.

#define WWDG_CR_T0 ((uint8_t)0x01)

Bit 0

Definition at line 5896 of file stm32l1xx.h.

#define WWDG_CR_T1 ((uint8_t)0x02)

Bit 1

Definition at line 5897 of file stm32l1xx.h.

#define WWDG_CR_T2 ((uint8_t)0x04)

Bit 2

Definition at line 5898 of file stm32l1xx.h.

#define WWDG_CR_T3 ((uint8_t)0x08)

Bit 3

Definition at line 5899 of file stm32l1xx.h.

#define WWDG_CR_T4 ((uint8_t)0x10)

Bit 4

Definition at line 5900 of file stm32l1xx.h.

#define WWDG_CR_T5 ((uint8_t)0x20)

Bit 5

Definition at line 5901 of file stm32l1xx.h.

#define WWDG_CR_T6 ((uint8_t)0x40)

Bit 6

Definition at line 5902 of file stm32l1xx.h.

#define WWDG_CR_WDGA ((uint8_t)0x80)

Activation bit

Definition at line 5904 of file stm32l1xx.h.

Referenced by WWDG_Enable().

#define WWDG_SR_EWIF ((uint8_t)0x01)

Early Wakeup Interrupt Flag

Definition at line 5923 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: Exported_macro

Defines

Exported_macro

Stm32l1xx

Defines

#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define | CLEAR_REG(REG) ((REG) = (0x0))
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define | READ_BIT(REG, BIT) ((REG) & (BIT))
#define | READ_REG(REG) ((REG))
#define | SET_BIT(REG, BIT) ((REG) |= (BIT))
#define | WRITE_REG(REG, VAL) ((REG) = (VAL))

Define Documentation

#define CLEAR_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) &= ~(BIT))

Definition at line 6318 of file stm32l1xx.h.

#define CLEAR_REG ( REG ) ((REG) = (0x0))

Definition at line 6322 of file stm32l1xx.h.

#define MODIFY_REG | ( | REG,
 |  | CLEARMASK,
 |  | SETMASK
 | ) | WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

Definition at line 6328 of file stm32l1xx.h.

#define READ_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) & (BIT))

Definition at line 6320 of file stm32l1xx.h.

#define READ_REG ( REG ) ((REG))

Definition at line 6326 of file stm32l1xx.h.

#define SET_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) |= (BIT))

Definition at line 6316 of file stm32l1xx.h.

#define WRITE_REG | ( | REG,
 |  | VAL
 | ) | ((REG) = (VAL))

Definition at line 6324 of file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Includes

STM32L1xx_System_Includes

Stm32l1xx_system

Define to prevent recursive inclusion. More...

Define to prevent recursive inclusion.


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Exported_types

Variables

STM32L1xx_System_Exported_types

Stm32l1xx_system

Variables

uint32_t SystemCoreClock

Variable Documentation

uint32_t SystemCoreClock

System Clock Frequency (Core Clock)

Definition at line 146 of file system_stm32l1xx.c.

Referenced by SystemCoreClockUpdate().


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Exported_Constants

STM32L1xx_System_Exported_Constants

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Exported_Macros

STM32L1xx_System_Exported_Macros

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Exported_Functions

Functions

STM32L1xx_System_Exported_Functions

Stm32l1xx_system

Functions

void | SystemCoreClockUpdate (void)
Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
void | SystemInit (void)
Setup the microcontroller system.

Function Documentation

void SystemCoreClockUpdate ( void )

Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

Note:
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
  • If SYSCLK source is MSI, SystemCoreClock will contain the MSI value as defined by the MSI range.
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
    Parameters:
    None
    Return values:
    None

Definition at line 250 of file system_stm32l1xx.c.

References AHBPrescTable, HSE_VALUE, HSI_VALUE, PLLMulTable, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLDIV, RCC_CFGR_PLLMUL, RCC_CFGR_PLLSRC, RCC_CFGR_SWS, RCC_ICSCR_MSIRANGE, and SystemCoreClock.

void SystemInit ( void )

Setup the microcontroller system.

Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Parameters:
None
Return values:
None

< Set MSION bit

< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits

< Reset HSION, HSEON, CSSON and PLLON bits

< Reset HSEBYP bit

< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits

< Disable all interrupts

Definition at line 178 of file system_stm32l1xx.c.

References FLASH_BASE, RCC, SetSysClock(), SRAM_BASE, and VECT_TAB_OFFSET.


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_Includes

STM32L1xx_System_Private_Includes

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_TypesDefinitions

STM32L1xx_System_Private_TypesDefinitions

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_Defines

Defines

STM32L1xx_System_Private_Defines

Stm32l1xx_system

Defines

#define VECT_TAB_OFFSET 0x0

Define Documentation

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM32L152D_EVAL board as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 129 of file system_stm32l1xx.c.

Referenced by SystemInit().


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_Macros

STM32L1xx_System_Private_Macros

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_Variables

Variables

STM32L1xx_System_Private_Variables

Stm32l1xx_system

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | PLLMulTable [9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}
uint32_t | SystemCoreClock = 32000000

Variable Documentation

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 148 of file system_stm32l1xx.c.

Referenced by SystemCoreClockUpdate().

__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}

Definition at line 147 of file system_stm32l1xx.c.

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

uint32_t SystemCoreClock = 32000000

System Clock Frequency (Core Clock)

Definition at line 146 of file system_stm32l1xx.c.

Referenced by SystemCoreClockUpdate().


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_FunctionPrototypes

STM32L1xx_System_Private_FunctionPrototypes

Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_System_Private_Functions

Functions

STM32L1xx_System_Private_Functions

Stm32l1xx_system

Functions

static void | SetSysClock (void)
Configures the System clock frequency, AHB/APBx prescalers and Flash settings.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
void | SystemInit (void)
Setup the microcontroller system.

Function Documentation

static void SetSysClock ( void ) [static]

Configures the System clock frequency, AHB/APBx prescalers and Flash settings.

Note:
This function should be called only once the RCC clock configuration is reset to the default reset state (done in SystemInit() function).
Parameters:
None
Return values:
None

Definition at line 309 of file system_stm32l1xx.c.

References FLASH, FLASH_ACR_ACC64, FLASH_ACR_LATENCY, FLASH_ACR_PRFTEN, HSE_STARTUP_TIMEOUT, PWR, PWR_CR_VOS_0, PWR_CSR_VOSF, RCC, RCC_APB1ENR_PWREN, RCC_CFGR_HPRE_DIV1, RCC_CFGR_PLLDIV, RCC_CFGR_PLLDIV3, RCC_CFGR_PLLMUL, RCC_CFGR_PLLMUL12, RCC_CFGR_PLLSRC, RCC_CFGR_PLLSRC_HSE, RCC_CFGR_PPRE1_DIV1, RCC_CFGR_PPRE2_DIV1, RCC_CFGR_SW, RCC_CFGR_SW_PLL, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL, RCC_CR_HSEON, RCC_CR_HSERDY, RCC_CR_PLLON, RCC_CR_PLLRDY, and RESET.

Referenced by SystemInit().

void SystemCoreClockUpdate ( void )

Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

Note:
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
  • If SYSCLK source is MSI, SystemCoreClock will contain the MSI value as defined by the MSI range.
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
    Parameters:
    None
    Return values:
    None

Definition at line 250 of file system_stm32l1xx.c.

References AHBPrescTable, HSE_VALUE, HSI_VALUE, PLLMulTable, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLDIV, RCC_CFGR_PLLMUL, RCC_CFGR_PLLSRC, RCC_CFGR_SWS, RCC_ICSCR_MSIRANGE, and SystemCoreClock.

void SystemInit ( void )

Setup the microcontroller system.

Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Parameters:
None
Return values:
None

< Set MSION bit

< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits

< Reset HSION, HSEON, CSSON and PLLON bits

< Reset HSEBYP bit

< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits

< Disable all interrupts

Definition at line 178 of file system_stm32l1xx.c.

References FLASH_BASE, RCC, SetSysClock(), SRAM_BASE, and VECT_TAB_OFFSET.


STM32L1xx Standard Peripherals Firmware Library: Vector_Table_Base

Defines

Vector_Table_Base

MISC_Exported_Constants

Defines

#define | IS_NVIC_VECTTAB(VECTTAB)
#define | NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define | NVIC_VectTab_RAM ((uint32_t)0x20000000)

Define Documentation

#define IS_NVIC_VECTTAB ( VECTTAB )
Value:
(((VECTTAB) == NVIC_VectTab_RAM) || \
                                  ((VECTTAB) == NVIC_VectTab_FLASH))

Definition at line 109 of file misc.h.

Referenced by NVIC_SetVectorTable().

#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)

Definition at line 108 of file misc.h.

#define NVIC_VectTab_RAM ((uint32_t)0x20000000)

Definition at line 107 of file misc.h.


STM32L1xx Standard Peripherals Firmware Library: System_Low_Power

Defines

System_Low_Power

MISC_Exported_Constants

Defines

#define | IS_NVIC_LP(LP)
#define | NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define | NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define | NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)

Define Documentation

#define IS_NVIC_LP ( LP )
Value:
(((LP) == NVIC_LP_SEVONPEND) || \
                        ((LP) == NVIC_LP_SLEEPDEEP) || \
                        ((LP) == NVIC_LP_SLEEPONEXIT))

Definition at line 122 of file misc.h.

Referenced by NVIC_SystemLPConfig().

#define NVIC_LP_SEVONPEND ((uint8_t)0x10)

Definition at line 119 of file misc.h.

#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)

Definition at line 120 of file misc.h.

#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)

Definition at line 121 of file misc.h.


STM32L1xx Standard Peripherals Firmware Library: Preemption_Priority_Group

Defines

Preemption_Priority_Group

MISC_Exported_Constants

Defines

#define | IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | NVIC_PriorityGroup_0 ((uint32_t)0x700)
#define | NVIC_PriorityGroup_1 ((uint32_t)0x600)
#define | NVIC_PriorityGroup_2 ((uint32_t)0x500)
#define | NVIC_PriorityGroup_3 ((uint32_t)0x400)
#define | NVIC_PriorityGroup_4 ((uint32_t)0x300)

Define Documentation

#define IS_NVIC_OFFSET ( OFFSET ) ((OFFSET) < 0x0005FFFF)

Definition at line 154 of file misc.h.

Referenced by NVIC_SetVectorTable().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 150 of file misc.h.

Referenced by NVIC_Init().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PriorityGroup_0) || \
                                       ((GROUP) == NVIC_PriorityGroup_1) || \
                                       ((GROUP) == NVIC_PriorityGroup_2) || \
                                       ((GROUP) == NVIC_PriorityGroup_3) || \
                                       ((GROUP) == NVIC_PriorityGroup_4))

Definition at line 144 of file misc.h.

Referenced by NVIC_PriorityGroupConfig().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 152 of file misc.h.

Referenced by NVIC_Init().

#define NVIC_PriorityGroup_0 ((uint32_t)0x700)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 133 of file misc.h.

#define NVIC_PriorityGroup_1 ((uint32_t)0x600)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 135 of file misc.h.

#define NVIC_PriorityGroup_2 ((uint32_t)0x500)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 137 of file misc.h.

#define NVIC_PriorityGroup_3 ((uint32_t)0x400)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 139 of file misc.h.

#define NVIC_PriorityGroup_4 ((uint32_t)0x300)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 141 of file misc.h.


STM32L1xx Standard Peripherals Firmware Library: SysTick_clock_source

Defines

SysTick_clock_source

MISC_Exported_Constants

Defines

#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define | SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Define Documentation

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SysTick_CLKSource_HCLK) || \
                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))

Definition at line 166 of file misc.h.

Referenced by SysTick_CLKSourceConfig().

#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)

Definition at line 165 of file misc.h.

Referenced by SysTick_CLKSourceConfig().

#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Definition at line 164 of file misc.h.

Referenced by SysTick_CLKSourceConfig().


STM32L1xx Standard Peripherals Firmware Library: MISC_Private_Functions

Functions

MISC_Private_Functions

MISC

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: preemption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Function Documentation

void NVIC_Init ( NVIC_InitTypeDef * NVIC_InitStruct )

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
NVIC_InitStruct,: pointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
Return values:
None

Definition at line 134 of file misc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_PREEMPTION_PRIORITY, IS_NVIC_SUB_PRIORITY, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, and NVIC_InitTypeDef::NVIC_IRQChannelSubPriority.

void NVIC_PriorityGroupConfig ( uint32_t NVIC_PriorityGroup )

Configures the priority grouping: preemption priority and subpriority.

 *******************************************************************************
                   ##### Interrupts configuration functions #####
 *******************************************************************************
    [..] This section provide functions allowing to configure the NVIC interrupts
         (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
         (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
             function according to the following table.
             The table below gives the allowed values of the preemption priority
             and subpriority according to the Priority Grouping configuration
             performed by NVIC_PriorityGroupConfig function.
  ============================================================================================================================
    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
  ============================================================================================================================
   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for preemption priority
                         |                                   |                             |   4 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for preemption priority
                         |                                   |                             |   3 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for preemption priority
                         |                                   |                             |   2 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for preemption priority
                         |                                   |                             |   1 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for preemption priority
                         |                                   |                             |   0 bits for subpriority
  ============================================================================================================================

         (#) Enable and Configure the priority of the selected IRQ Channels.

        -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
            the IRQ priority will be managed only by subpriority.
            The sub-priority is only used to sort pending exception priorities,
            and does not affect active exceptions.
        -@- Lower priority values gives higher priority.
        -@- Priority Order:
            (#@) Lowest Preemption priority.
            (#@) Lowest Subpriority.
            (#@) Lowest hardware priority (IRQn position).
Parameters:
NVIC_PriorityGroup,: specifies the priority grouping bits length. This parameter can be one of the following values:

  • NVIC_PriorityGroup_0: 0 bits for preemption priority 4 bits for subpriority.
Note:
When NVIC_PriorityGroup_0 is selected, it will no be any nested interrupt. This interrupts priority is managed only with subpriority.
  • NVIC_PriorityGroup_1: 1 bits for preemption priority. 3 bits for subpriority.
  • NVIC_PriorityGroup_2: 2 bits for preemption priority. 2 bits for subpriority.
  • NVIC_PriorityGroup_3: 3 bits for preemption priority. 1 bits for subpriority.
  • NVIC_PriorityGroup_4: 4 bits for preemption priority. 0 bits for subpriority.
Return values:
None

Definition at line 116 of file misc.c.

References AIRCR_VECTKEY_MASK, and IS_NVIC_PRIORITY_GROUP.

void NVIC_SetVectorTable | ( | uint32_t | NVIC_VectTab,
 |  | uint32_t | Offset
 | ) |  |

Sets the vector table location and Offset.

Parameters:
NVIC_VectTab,: specifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:

  • NVIC_VectTab_RAM: Vector Table in internal SRAM.
  • NVIC_VectTab_FLASH: Vector Table in internal FLASH.
Offset,: Vector Table base offset field. This value must be a multiple of 0x200.
Return values:
None

Definition at line 177 of file misc.c.

References IS_NVIC_OFFSET, and IS_NVIC_VECTTAB.

void NVIC_SystemLPConfig | ( | uint8_t | LowPowerMode,
 |  | FunctionalState | NewState
 | ) |  |

Selects the condition for the system to enter low power mode.

Parameters:
LowPowerMode,: Specifies the new mode for the system to enter low power mode. This parameter can be one of the following values:

  • NVIC_LP_SEVONPEND: Low Power SEV on Pend.
  • NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
  • NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
NewState,: new state of LP condition. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 197 of file misc.c.

References DISABLE, IS_FUNCTIONAL_STATE, and IS_NVIC_LP.

void SysTick_CLKSourceConfig ( uint32_t SysTick_CLKSource )

Configures the SysTick clock source.

Parameters:
SysTick_CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:

  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 221 of file misc.c.

References IS_SYSTICK_CLK_SOURCE, SysTick_CLKSource_HCLK, and SysTick_CLKSource_HCLK_Div8.


STM32L1xx Standard Peripherals Firmware Library: MISC

Data Structures | Modules | Defines | Functions

MISC

STM32L1xx_StdPeriph_Driver

MISC driver modules. More...

Data Structures

struct | NVIC_InitTypeDef
NVIC Init Structure definition. More...

Modules

MISC_Exported_Constants
MISC_Private_Functions

Defines

#define | AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: preemption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Detailed Description

MISC driver modules.

Define Documentation

#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Definition at line 40 of file misc.c.

Referenced by NVIC_PriorityGroupConfig().

Function Documentation

void NVIC_Init ( NVIC_InitTypeDef * NVIC_InitStruct )

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
NVIC_InitStruct,: pointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
Return values:
None

Definition at line 134 of file misc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_PREEMPTION_PRIORITY, IS_NVIC_SUB_PRIORITY, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, and NVIC_InitTypeDef::NVIC_IRQChannelSubPriority.

void NVIC_PriorityGroupConfig ( uint32_t NVIC_PriorityGroup )

Configures the priority grouping: preemption priority and subpriority.

 *******************************************************************************
                   ##### Interrupts configuration functions #####
 *******************************************************************************
    [..] This section provide functions allowing to configure the NVIC interrupts
         (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
         (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
             function according to the following table.
             The table below gives the allowed values of the preemption priority
             and subpriority according to the Priority Grouping configuration
             performed by NVIC_PriorityGroupConfig function.
  ============================================================================================================================
    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
  ============================================================================================================================
   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for preemption priority
                         |                                   |                             |   4 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for preemption priority
                         |                                   |                             |   3 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for preemption priority
                         |                                   |                             |   2 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for preemption priority
                         |                                   |                             |   1 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for preemption priority
                         |                                   |                             |   0 bits for subpriority
  ============================================================================================================================

         (#) Enable and Configure the priority of the selected IRQ Channels.

        -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
            the IRQ priority will be managed only by subpriority.
            The sub-priority is only used to sort pending exception priorities,
            and does not affect active exceptions.
        -@- Lower priority values gives higher priority.
        -@- Priority Order:
            (#@) Lowest Preemption priority.
            (#@) Lowest Subpriority.
            (#@) Lowest hardware priority (IRQn position).
Parameters:
NVIC_PriorityGroup,: specifies the priority grouping bits length. This parameter can be one of the following values:

  • NVIC_PriorityGroup_0: 0 bits for preemption priority 4 bits for subpriority.
Note:
When NVIC_PriorityGroup_0 is selected, it will no be any nested interrupt. This interrupts priority is managed only with subpriority.
  • NVIC_PriorityGroup_1: 1 bits for preemption priority. 3 bits for subpriority.
  • NVIC_PriorityGroup_2: 2 bits for preemption priority. 2 bits for subpriority.
  • NVIC_PriorityGroup_3: 3 bits for preemption priority. 1 bits for subpriority.
  • NVIC_PriorityGroup_4: 4 bits for preemption priority. 0 bits for subpriority.
Return values:
None

Definition at line 116 of file misc.c.

References AIRCR_VECTKEY_MASK, and IS_NVIC_PRIORITY_GROUP.

void NVIC_SetVectorTable | ( | uint32_t | NVIC_VectTab,
 |  | uint32_t | Offset
 | ) |  |

Sets the vector table location and Offset.

Parameters:
NVIC_VectTab,: specifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:

  • NVIC_VectTab_RAM: Vector Table in internal SRAM.
  • NVIC_VectTab_FLASH: Vector Table in internal FLASH.
Offset,: Vector Table base offset field. This value must be a multiple of 0x200.
Return values:
None

Definition at line 177 of file misc.c.

References IS_NVIC_OFFSET, and IS_NVIC_VECTTAB.

void NVIC_SystemLPConfig | ( | uint8_t | LowPowerMode,
 |  | FunctionalState | NewState
 | ) |  |

Selects the condition for the system to enter low power mode.

Parameters:
LowPowerMode,: Specifies the new mode for the system to enter low power mode. This parameter can be one of the following values:

  • NVIC_LP_SEVONPEND: Low Power SEV on Pend.
  • NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
  • NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
NewState,: new state of LP condition. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 197 of file misc.c.

References DISABLE, IS_FUNCTIONAL_STATE, and IS_NVIC_LP.

void SysTick_CLKSourceConfig ( uint32_t SysTick_CLKSource )

Configures the SysTick clock source.

Parameters:
SysTick_CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:

  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 221 of file misc.c.

References IS_SYSTICK_CLK_SOURCE, SysTick_CLKSource_HCLK, and SysTick_CLKSource_HCLK_Div8.


STM32L1xx Standard Peripherals Firmware Library: NVIC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

NVIC_InitTypeDef Struct Reference
MISC

NVIC Init Structure definition. More...

#include <misc.h>

Data Fields

uint8_t | NVIC_IRQChannel
FunctionalState NVIC_IRQChannelCmd
uint8_t | NVIC_IRQChannelPreemptionPriority
uint8_t | NVIC_IRQChannelSubPriority

Detailed Description

NVIC Init Structure definition.

Definition at line 51 of file misc.h.

Field Documentation

uint8_t NVIC_InitTypeDef::NVIC_IRQChannel

Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of IRQn_Type (For the complete STM32 Devices IRQ Channels list, please refer to stm32l1xx.h file)

Definition at line 53 of file misc.h.

Referenced by NVIC_Init().

FunctionalState NVIC_InitTypeDef::NVIC_IRQChannelCmd

Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE

Definition at line 66 of file misc.h.

Referenced by NVIC_Init().

uint8_t NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority

Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table NVIC_Priority_Table

Definition at line 58 of file misc.h.

Referenced by NVIC_Init().

uint8_t NVIC_InitTypeDef::NVIC_IRQChannelSubPriority

Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table NVIC_Priority_Table

Definition at line 62 of file misc.h.

Referenced by NVIC_Init().

The documentation for this struct was generated from the following file:
  • misc.h


STM32L1xx Standard Peripherals Firmware Library: ADC_Power_down_during_Idle_and_or_Delay_phase

Defines

ADC_Power_down_during_Idle_and_or_Delay_phase

ADC_Exported_Constants

Defines

#define | ADC_PowerDown_Delay ((uint32_t)0x00010000)
#define | ADC_PowerDown_Idle ((uint32_t)0x00020000)
#define | ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
#define | IS_ADC_POWER_DOWN(DWON)

Define Documentation

#define ADC_PowerDown_Delay ((uint32_t)0x00010000)

Definition at line 98 of file stm32l1xx_adc.h.

#define ADC_PowerDown_Idle ((uint32_t)0x00020000)

Definition at line 99 of file stm32l1xx_adc.h.

#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)

Definition at line 100 of file stm32l1xx_adc.h.

#define IS_ADC_POWER_DOWN ( DWON )
Value:
(((DWON) == ADC_PowerDown_Delay) || \
                                 ((DWON) == ADC_PowerDown_Idle) || \
                                 ((DWON) == ADC_PowerDown_Idle_Delay))

Definition at line 102 of file stm32l1xx_adc.h.

Referenced by ADC_PowerDownCmd().


STM32L1xx Standard Peripherals Firmware Library: ADC_Prescaler

Defines

ADC_Prescaler

ADC_Exported_Constants

Defines

#define | ADC_Prescaler_Div1 ((uint32_t)0x00000000)
#define | ADC_Prescaler_Div2 ((uint32_t)0x00010000)
#define | ADC_Prescaler_Div4 ((uint32_t)0x00020000)
#define | IS_ADC_PRESCALER(PRESCALER)

Define Documentation

#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)

Definition at line 113 of file stm32l1xx_adc.h.

Referenced by ADC_CommonStructInit().

#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)

Definition at line 114 of file stm32l1xx_adc.h.

#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)

Definition at line 115 of file stm32l1xx_adc.h.

#define IS_ADC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == ADC_Prescaler_Div1) || \
                                     ((PRESCALER) == ADC_Prescaler_Div2) || \
                                     ((PRESCALER) == ADC_Prescaler_Div4))

Definition at line 117 of file stm32l1xx_adc.h.

Referenced by ADC_CommonInit().


STM32L1xx Standard Peripherals Firmware Library: ADC_Resolution

Defines

ADC_Resolution

ADC_Exported_Constants

Defines

#define | ADC_Resolution_10b ((uint32_t)0x01000000)
#define | ADC_Resolution_12b ((uint32_t)0x00000000)
#define | ADC_Resolution_6b ((uint32_t)0x03000000)
#define | ADC_Resolution_8b ((uint32_t)0x02000000)
#define | IS_ADC_RESOLUTION(RESOLUTION)

Define Documentation

#define ADC_Resolution_10b ((uint32_t)0x01000000)

Definition at line 130 of file stm32l1xx_adc.h.

#define ADC_Resolution_12b ((uint32_t)0x00000000)

Definition at line 129 of file stm32l1xx_adc.h.

Referenced by ADC_StructInit().

#define ADC_Resolution_6b ((uint32_t)0x03000000)

Definition at line 132 of file stm32l1xx_adc.h.

#define ADC_Resolution_8b ((uint32_t)0x02000000)

Definition at line 131 of file stm32l1xx_adc.h.

#define IS_ADC_RESOLUTION ( RESOLUTION )
Value:
(((RESOLUTION) == ADC_Resolution_12b) || \
                                       ((RESOLUTION) == ADC_Resolution_10b) || \
                                       ((RESOLUTION) == ADC_Resolution_8b) || \
                                       ((RESOLUTION) == ADC_Resolution_6b))

Definition at line 134 of file stm32l1xx_adc.h.

Referenced by ADC_Init().


STM32L1xx Standard Peripherals Firmware Library: ADC_external_trigger_edge_for_regular_channels_conversion

Defines

ADC_external_trigger_edge_for_regular_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
#define | ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
#define | ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
#define | IS_ADC_EXT_TRIG_EDGE(EDGE)

Define Documentation

#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)

Definition at line 148 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)

Definition at line 146 of file stm32l1xx_adc.h.

Referenced by ADC_StructInit().

#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)

Definition at line 147 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)

Definition at line 149 of file stm32l1xx_adc.h.

#define IS_ADC_EXT_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_ExternalTrigConvEdge_None) || \
                                    ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
                                    ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
                                    ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))

Definition at line 151 of file stm32l1xx_adc.h.

Referenced by ADC_Init().


STM32L1xx Standard Peripherals Firmware Library: ADC_external_trigger_sources_for_regular_channels_conversion

Defines

ADC_external_trigger_sources_for_regular_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
#define | ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
#define | ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
#define | ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
#define | ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
#define | ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
#define | ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
#define | ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
#define | ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
#define | ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
#define | ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
#define | IS_ADC_EXT_TRIG(REGTRIG)

Define Documentation

#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)

Definition at line 185 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)

Definition at line 165 of file stm32l1xx_adc.h.

Referenced by ADC_StructInit().

#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)

Definition at line 164 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)

Definition at line 166 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)

Definition at line 169 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)

Definition at line 170 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)

Definition at line 171 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)

Definition at line 174 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)

Definition at line 175 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)

Definition at line 178 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)

Definition at line 181 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)

Definition at line 182 of file stm32l1xx_adc.h.

#define IS_ADC_EXT_TRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_ExternalTrigConv_T9_CC2)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3)  || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))

Definition at line 187 of file stm32l1xx_adc.h.

Referenced by ADC_Init().


STM32L1xx Standard Peripherals Firmware Library: ADC_data_align

Defines

ADC_data_align

ADC_Exported_Constants

Defines

#define | ADC_DataAlign_Left ((uint32_t)0x00000800)
#define | ADC_DataAlign_Right ((uint32_t)0x00000000)
#define | IS_ADC_DATA_ALIGN(ALIGN)

Define Documentation

#define ADC_DataAlign_Left ((uint32_t)0x00000800)

Definition at line 208 of file stm32l1xx_adc.h.

#define ADC_DataAlign_Right ((uint32_t)0x00000000)

Definition at line 207 of file stm32l1xx_adc.h.

Referenced by ADC_StructInit().

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DataAlign_Right) || \
                                  ((ALIGN) == ADC_DataAlign_Left))

Definition at line 210 of file stm32l1xx_adc.h.

Referenced by ADC_Init().


STM32L1xx Standard Peripherals Firmware Library: ADC_channels

Defines

ADC_channels

ADC_Exported_Constants

Defines

#define | ADC_Channel_0 ((uint8_t)0x00)
#define | ADC_Channel_0b ADC_Channel_0
#define | ADC_Channel_1 ((uint8_t)0x01)
#define | ADC_Channel_10 ((uint8_t)0x0A)
#define | ADC_Channel_10b ADC_Channel_10
#define | ADC_Channel_11 ((uint8_t)0x0B)
#define | ADC_Channel_11b ADC_Channel_11
#define | ADC_Channel_12 ((uint8_t)0x0C)
#define | ADC_Channel_12b ADC_Channel_12
#define | ADC_Channel_13 ((uint8_t)0x0D)
#define | ADC_Channel_14 ((uint8_t)0x0E)
#define | ADC_Channel_15 ((uint8_t)0x0F)
#define | ADC_Channel_16 ((uint8_t)0x10)
#define | ADC_Channel_17 ((uint8_t)0x11)
#define | ADC_Channel_18 ((uint8_t)0x12)
#define | ADC_Channel_19 ((uint8_t)0x13)
#define | ADC_Channel_1b ADC_Channel_1
#define | ADC_Channel_2 ((uint8_t)0x02)
#define | ADC_Channel_20 ((uint8_t)0x14)
#define | ADC_Channel_21 ((uint8_t)0x15)
#define | ADC_Channel_22 ((uint8_t)0x16)
#define | ADC_Channel_23 ((uint8_t)0x17)
#define | ADC_Channel_24 ((uint8_t)0x18)
#define | ADC_Channel_25 ((uint8_t)0x19)
#define | ADC_Channel_27 ((uint8_t)0x1B)
#define | ADC_Channel_28 ((uint8_t)0x1C)
#define | ADC_Channel_29 ((uint8_t)0x1D)
#define | ADC_Channel_2b ADC_Channel_2
#define | ADC_Channel_3 ((uint8_t)0x03)
#define | ADC_Channel_30 ((uint8_t)0x1E)
#define | ADC_Channel_31 ((uint8_t)0x1F)
#define | ADC_Channel_3b ADC_Channel_3
#define | ADC_Channel_4 ((uint8_t)0x04)
#define | ADC_Channel_5 ((uint8_t)0x05)
#define | ADC_Channel_6 ((uint8_t)0x06)
#define | ADC_Channel_6b ADC_Channel_6
#define | ADC_Channel_7 ((uint8_t)0x07)
#define | ADC_Channel_7b ADC_Channel_7
#define | ADC_Channel_8 ((uint8_t)0x08)
#define | ADC_Channel_8b ADC_Channel_8
#define | ADC_Channel_9 ((uint8_t)0x09)
#define | ADC_Channel_9b ADC_Channel_9
#define | ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define | ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define | IS_ADC_CHANNEL(CHANNEL)

Define Documentation

#define ADC_Channel_0 ((uint8_t)0x00)

Definition at line 220 of file stm32l1xx_adc.h.

#define ADC_Channel_0b ADC_Channel_0

Definition at line 235 of file stm32l1xx_adc.h.

#define ADC_Channel_1 ((uint8_t)0x01)

Definition at line 221 of file stm32l1xx_adc.h.

#define ADC_Channel_10 ((uint8_t)0x0A)

Definition at line 229 of file stm32l1xx_adc.h.

#define ADC_Channel_10b ADC_Channel_10

Definition at line 244 of file stm32l1xx_adc.h.

#define ADC_Channel_11 ((uint8_t)0x0B)

Definition at line 230 of file stm32l1xx_adc.h.

#define ADC_Channel_11b ADC_Channel_11

Definition at line 245 of file stm32l1xx_adc.h.

#define ADC_Channel_12 ((uint8_t)0x0C)

Definition at line 231 of file stm32l1xx_adc.h.

#define ADC_Channel_12b ADC_Channel_12

Definition at line 246 of file stm32l1xx_adc.h.

#define ADC_Channel_13 ((uint8_t)0x0D)

Definition at line 252 of file stm32l1xx_adc.h.

#define ADC_Channel_14 ((uint8_t)0x0E)

Definition at line 253 of file stm32l1xx_adc.h.

#define ADC_Channel_15 ((uint8_t)0x0F)

Definition at line 254 of file stm32l1xx_adc.h.

#define ADC_Channel_16 ((uint8_t)0x10)

Definition at line 255 of file stm32l1xx_adc.h.

#define ADC_Channel_17 ((uint8_t)0x11)

Definition at line 256 of file stm32l1xx_adc.h.

#define ADC_Channel_18 ((uint8_t)0x12)

Definition at line 257 of file stm32l1xx_adc.h.

#define ADC_Channel_19 ((uint8_t)0x13)

Definition at line 258 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define ADC_Channel_1b ADC_Channel_1

Definition at line 236 of file stm32l1xx_adc.h.

#define ADC_Channel_2 ((uint8_t)0x02)

Definition at line 222 of file stm32l1xx_adc.h.

#define ADC_Channel_20 ((uint8_t)0x14)

Definition at line 259 of file stm32l1xx_adc.h.

#define ADC_Channel_21 ((uint8_t)0x15)

Definition at line 260 of file stm32l1xx_adc.h.

#define ADC_Channel_22 ((uint8_t)0x16)

Definition at line 261 of file stm32l1xx_adc.h.

#define ADC_Channel_23 ((uint8_t)0x17)

Definition at line 262 of file stm32l1xx_adc.h.

#define ADC_Channel_24 ((uint8_t)0x18)

Definition at line 263 of file stm32l1xx_adc.h.

#define ADC_Channel_25 ((uint8_t)0x19)

Definition at line 264 of file stm32l1xx_adc.h.

#define ADC_Channel_27 ((uint8_t)0x1B)

Definition at line 266 of file stm32l1xx_adc.h.

#define ADC_Channel_28 ((uint8_t)0x1C)

Definition at line 267 of file stm32l1xx_adc.h.

#define ADC_Channel_29 ((uint8_t)0x1D)

Definition at line 268 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define ADC_Channel_2b ADC_Channel_2

Definition at line 237 of file stm32l1xx_adc.h.

#define ADC_Channel_3 ((uint8_t)0x03)

Definition at line 223 of file stm32l1xx_adc.h.

#define ADC_Channel_30 ((uint8_t)0x1E)

Definition at line 269 of file stm32l1xx_adc.h.

#define ADC_Channel_31 ((uint8_t)0x1F)

Definition at line 270 of file stm32l1xx_adc.h.

#define ADC_Channel_3b ADC_Channel_3

Definition at line 238 of file stm32l1xx_adc.h.

#define ADC_Channel_4 ((uint8_t)0x04)

Definition at line 249 of file stm32l1xx_adc.h.

#define ADC_Channel_5 ((uint8_t)0x05)

Definition at line 250 of file stm32l1xx_adc.h.

#define ADC_Channel_6 ((uint8_t)0x06)

Definition at line 225 of file stm32l1xx_adc.h.

#define ADC_Channel_6b ADC_Channel_6

Definition at line 240 of file stm32l1xx_adc.h.

#define ADC_Channel_7 ((uint8_t)0x07)

Definition at line 226 of file stm32l1xx_adc.h.

#define ADC_Channel_7b ADC_Channel_7

Definition at line 241 of file stm32l1xx_adc.h.

#define ADC_Channel_8 ((uint8_t)0x08)

Definition at line 227 of file stm32l1xx_adc.h.

#define ADC_Channel_8b ADC_Channel_8

Definition at line 242 of file stm32l1xx_adc.h.

#define ADC_Channel_9 ((uint8_t)0x09)

Definition at line 228 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define ADC_Channel_9b ADC_Channel_9

Definition at line 243 of file stm32l1xx_adc.h.

#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)

Definition at line 272 of file stm32l1xx_adc.h.

#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)

Definition at line 273 of file stm32l1xx_adc.h.

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_Channel_0)  || ((CHANNEL) == ADC_Channel_1)  || \
                                 ((CHANNEL) == ADC_Channel_2)  || ((CHANNEL) == ADC_Channel_3)  || \
                                 ((CHANNEL) == ADC_Channel_4)  || ((CHANNEL) == ADC_Channel_5)  || \
                                 ((CHANNEL) == ADC_Channel_6)  || ((CHANNEL) == ADC_Channel_7)  || \
                                 ((CHANNEL) == ADC_Channel_8)  || ((CHANNEL) == ADC_Channel_9)  || \
                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
                                 ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
                                 ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
                                 ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
                                 ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
                                 ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
                                 ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
                                 ((CHANNEL) == ADC_Channel_31))

Definition at line 275 of file stm32l1xx_adc.h.

Referenced by ADC_AnalogWatchdogSingleChannelConfig(), ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_sampling_times

Defines

ADC_sampling_times

ADC_Exported_Constants

Defines

#define | ADC_SampleTime_16Cycles ((uint8_t)0x02)
#define | ADC_SampleTime_192Cycles ((uint8_t)0x06)
#define | ADC_SampleTime_24Cycles ((uint8_t)0x03)
#define | ADC_SampleTime_384Cycles ((uint8_t)0x07)
#define | ADC_SampleTime_48Cycles ((uint8_t)0x04)
#define | ADC_SampleTime_4Cycles ((uint8_t)0x00)
#define | ADC_SampleTime_96Cycles ((uint8_t)0x05)
#define | ADC_SampleTime_9Cycles ((uint8_t)0x01)
#define | IS_ADC_SAMPLE_TIME(TIME)

Define Documentation

#define ADC_SampleTime_16Cycles ((uint8_t)0x02)

Definition at line 301 of file stm32l1xx_adc.h.

#define ADC_SampleTime_192Cycles ((uint8_t)0x06)

Definition at line 305 of file stm32l1xx_adc.h.

#define ADC_SampleTime_24Cycles ((uint8_t)0x03)

Definition at line 302 of file stm32l1xx_adc.h.

#define ADC_SampleTime_384Cycles ((uint8_t)0x07)

Definition at line 306 of file stm32l1xx_adc.h.

#define ADC_SampleTime_48Cycles ((uint8_t)0x04)

Definition at line 303 of file stm32l1xx_adc.h.

#define ADC_SampleTime_4Cycles ((uint8_t)0x00)

Definition at line 299 of file stm32l1xx_adc.h.

#define ADC_SampleTime_96Cycles ((uint8_t)0x05)

Definition at line 304 of file stm32l1xx_adc.h.

#define ADC_SampleTime_9Cycles ((uint8_t)0x01)

Definition at line 300 of file stm32l1xx_adc.h.

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SampleTime_4Cycles)   || \
                                  ((TIME) == ADC_SampleTime_9Cycles)   || \
                                  ((TIME) == ADC_SampleTime_16Cycles)  || \
                                  ((TIME) == ADC_SampleTime_24Cycles)  || \
                                  ((TIME) == ADC_SampleTime_48Cycles)  || \
                                  ((TIME) == ADC_SampleTime_96Cycles)  || \
                                  ((TIME) == ADC_SampleTime_192Cycles) || \
                                  ((TIME) == ADC_SampleTime_384Cycles))

Definition at line 308 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_Delay_length

Defines

ADC_Delay_length

ADC_Exported_Constants

Defines

#define | ADC_DelayLength_127Cycles ((uint8_t)0x60)
#define | ADC_DelayLength_15Cycles ((uint8_t)0x30)
#define | ADC_DelayLength_255Cycles ((uint8_t)0x70)
#define | ADC_DelayLength_31Cycles ((uint8_t)0x40)
#define | ADC_DelayLength_63Cycles ((uint8_t)0x50)
#define | ADC_DelayLength_7Cycles ((uint8_t)0x20)
#define | ADC_DelayLength_Freeze ((uint8_t)0x10)
#define | ADC_DelayLength_None ((uint8_t)0x00)
#define | IS_ADC_DELAY_LENGTH(LENGTH)

Define Documentation

#define ADC_DelayLength_127Cycles ((uint8_t)0x60)

Definition at line 330 of file stm32l1xx_adc.h.

#define ADC_DelayLength_15Cycles ((uint8_t)0x30)

Definition at line 327 of file stm32l1xx_adc.h.

#define ADC_DelayLength_255Cycles ((uint8_t)0x70)

Definition at line 331 of file stm32l1xx_adc.h.

#define ADC_DelayLength_31Cycles ((uint8_t)0x40)

Definition at line 328 of file stm32l1xx_adc.h.

#define ADC_DelayLength_63Cycles ((uint8_t)0x50)

Definition at line 329 of file stm32l1xx_adc.h.

#define ADC_DelayLength_7Cycles ((uint8_t)0x20)

Definition at line 326 of file stm32l1xx_adc.h.

#define ADC_DelayLength_Freeze ((uint8_t)0x10)

Definition at line 325 of file stm32l1xx_adc.h.

#define ADC_DelayLength_None ((uint8_t)0x00)

Definition at line 324 of file stm32l1xx_adc.h.

#define IS_ADC_DELAY_LENGTH ( LENGTH )
Value:
(((LENGTH) == ADC_DelayLength_None)      || \
                                     ((LENGTH) == ADC_DelayLength_Freeze)    || \
                                     ((LENGTH) == ADC_DelayLength_7Cycles)   || \
                                     ((LENGTH) == ADC_DelayLength_15Cycles)  || \
                                     ((LENGTH) == ADC_DelayLength_31Cycles)  || \
                                     ((LENGTH) == ADC_DelayLength_63Cycles)  || \
                                     ((LENGTH) == ADC_DelayLength_127Cycles) || \
                                     ((LENGTH) == ADC_DelayLength_255Cycles))

Definition at line 333 of file stm32l1xx_adc.h.

Referenced by ADC_DelaySelectionConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_external_trigger_edge_for_injected_channels_conversion

Defines

ADC_external_trigger_edge_for_injected_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define | ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define | ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)

Define Documentation

#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)

Definition at line 351 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)

Definition at line 349 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)

Definition at line 350 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)

Definition at line 352 of file stm32l1xx_adc.h.

#define IS_ADC_EXT_INJEC_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_ExternalTrigInjecConvEdge_None)    || \
                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising)  || \
                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))

Definition at line 354 of file stm32l1xx_adc.h.

Referenced by ADC_ExternalTrigInjectedConvEdgeConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_external_trigger_sources_for_injected_channels_conversion

Defines

ADC_external_trigger_sources_for_injected_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
#define | ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
#define | ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
#define | ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
#define | ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
#define | ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
#define | ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
#define | ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
#define | ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)

Define Documentation

#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)

Definition at line 392 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)

Definition at line 389 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)

Definition at line 370 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)

Definition at line 369 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)

Definition at line 373 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)

Definition at line 377 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)

Definition at line 378 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)

Definition at line 379 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)

Definition at line 376 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)

Definition at line 382 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)

Definition at line 385 of file stm32l1xx_adc.h.

#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)

Definition at line 386 of file stm32l1xx_adc.h.

#define IS_ADC_EXT_INJEC_TRIG ( INJTRIG )
Value:
(((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3)  || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))

Definition at line 394 of file stm32l1xx_adc.h.

Referenced by ADC_ExternalTrigInjectedConvConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_injected_channel_selection

Defines

ADC_injected_channel_selection

ADC_Exported_Constants

Defines

#define | ADC_InjectedChannel_1 ((uint8_t)0x18)
#define | ADC_InjectedChannel_2 ((uint8_t)0x1C)
#define | ADC_InjectedChannel_3 ((uint8_t)0x20)
#define | ADC_InjectedChannel_4 ((uint8_t)0x24)
#define | IS_ADC_INJECTED_CHANNEL(CHANNEL)

Define Documentation

#define ADC_InjectedChannel_1 ((uint8_t)0x18)

Definition at line 413 of file stm32l1xx_adc.h.

#define ADC_InjectedChannel_2 ((uint8_t)0x1C)

Definition at line 414 of file stm32l1xx_adc.h.

#define ADC_InjectedChannel_3 ((uint8_t)0x20)

Definition at line 415 of file stm32l1xx_adc.h.

#define ADC_InjectedChannel_4 ((uint8_t)0x24)

Definition at line 416 of file stm32l1xx_adc.h.

#define IS_ADC_INJECTED_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_InjectedChannel_1) || \
                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
                                          ((CHANNEL) == ADC_InjectedChannel_4))

Definition at line 418 of file stm32l1xx_adc.h.

Referenced by ADC_GetInjectedConversionValue(), and ADC_SetInjectedOffset().


STM32L1xx Standard Peripherals Firmware Library: ADC_analog_watchdog_selection

Defines

ADC_analog_watchdog_selection

ADC_Exported_Constants

Defines

#define | ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define | ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define | ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define | ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define | ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define | ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define | ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)

Define Documentation

#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)

Definition at line 434 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)

Definition at line 435 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)

Definition at line 433 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)

Definition at line 436 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)

Definition at line 431 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)

Definition at line 430 of file stm32l1xx_adc.h.

#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)

Definition at line 432 of file stm32l1xx_adc.h.

#define IS_ADC_ANALOG_WATCHDOG ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable)        || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable)      || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable)           || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable)         || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable)   || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))

Definition at line 438 of file stm32l1xx_adc.h.

Referenced by ADC_AnalogWatchdogCmd().


STM32L1xx Standard Peripherals Firmware Library: ADC_interrupts_definition

Defines

ADC_interrupts_definition

ADC_Exported_Constants

Defines

#define | ADC_IT_AWD ((uint16_t)0x0106)
#define | ADC_IT_EOC ((uint16_t)0x0205)
#define | ADC_IT_JEOC ((uint16_t)0x0407)
#define | ADC_IT_OVR ((uint16_t)0x201A)
#define | IS_ADC_IT(IT)

Define Documentation

#define ADC_IT_AWD ((uint16_t)0x0106)

Definition at line 453 of file stm32l1xx_adc.h.

#define ADC_IT_EOC ((uint16_t)0x0205)

Definition at line 454 of file stm32l1xx_adc.h.

#define ADC_IT_JEOC ((uint16_t)0x0407)

Definition at line 455 of file stm32l1xx_adc.h.

#define ADC_IT_OVR ((uint16_t)0x201A)

Definition at line 456 of file stm32l1xx_adc.h.

#define IS_ADC_IT ( IT )
Value:
(((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))

Definition at line 458 of file stm32l1xx_adc.h.

Referenced by ADC_ClearITPendingBit(), ADC_GetITStatus(), and ADC_ITConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_flags_definition

Defines

ADC_flags_definition

ADC_Exported_Constants

Defines

#define | ADC_FLAG_ADONS ((uint16_t)0x0040)
#define | ADC_FLAG_AWD ((uint16_t)0x0001)
#define | ADC_FLAG_EOC ((uint16_t)0x0002)
#define | ADC_FLAG_JCNR ((uint16_t)0x0200)
#define | ADC_FLAG_JEOC ((uint16_t)0x0004)
#define | ADC_FLAG_JSTRT ((uint16_t)0x0008)
#define | ADC_FLAG_OVR ((uint16_t)0x0020)
#define | ADC_FLAG_RCNR ((uint16_t)0x0100)
#define | ADC_FLAG_STRT ((uint16_t)0x0010)
#define | IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
#define | IS_ADC_GET_FLAG(FLAG)

Define Documentation

#define ADC_FLAG_ADONS ((uint16_t)0x0040)

Definition at line 474 of file stm32l1xx_adc.h.

#define ADC_FLAG_AWD ((uint16_t)0x0001)

Definition at line 468 of file stm32l1xx_adc.h.

#define ADC_FLAG_EOC ((uint16_t)0x0002)

Definition at line 469 of file stm32l1xx_adc.h.

#define ADC_FLAG_JCNR ((uint16_t)0x0200)

Definition at line 476 of file stm32l1xx_adc.h.

#define ADC_FLAG_JEOC ((uint16_t)0x0004)

Definition at line 470 of file stm32l1xx_adc.h.

#define ADC_FLAG_JSTRT ((uint16_t)0x0008)

Definition at line 471 of file stm32l1xx_adc.h.

#define ADC_FLAG_OVR ((uint16_t)0x0020)

Definition at line 473 of file stm32l1xx_adc.h.

#define ADC_FLAG_RCNR ((uint16_t)0x0100)

Definition at line 475 of file stm32l1xx_adc.h.

#define ADC_FLAG_STRT ((uint16_t)0x0010)

Definition at line 472 of file stm32l1xx_adc.h.

#define IS_ADC_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))

Definition at line 478 of file stm32l1xx_adc.h.

Referenced by ADC_ClearFlag().

#define IS_ADC_GET_FLAG ( FLAG )
Value:
(((FLAG) == ADC_FLAG_AWD)   || ((FLAG) == ADC_FLAG_EOC)  || \
                               ((FLAG) == ADC_FLAG_JEOC)  || ((FLAG)== ADC_FLAG_JSTRT) || \
                               ((FLAG) == ADC_FLAG_STRT)  || ((FLAG)== ADC_FLAG_OVR)   || \
                               ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR)  || \
                               ((FLAG) == ADC_FLAG_JCNR))

Definition at line 480 of file stm32l1xx_adc.h.

Referenced by ADC_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: ADC_thresholds

Defines

ADC_thresholds

ADC_Exported_Constants

Defines

#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)

Define Documentation

#define IS_ADC_THRESHOLD ( THRESHOLD ) ((THRESHOLD) <= 0xFFF)

Definition at line 493 of file stm32l1xx_adc.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_injected_offset

Defines

ADC_injected_offset

ADC_Exported_Constants

Defines

#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)

Define Documentation

#define IS_ADC_OFFSET ( OFFSET ) ((OFFSET) <= 0xFFF)

Definition at line 503 of file stm32l1xx_adc.h.

Referenced by ADC_SetInjectedOffset().


STM32L1xx Standard Peripherals Firmware Library: ADC_injected_length

Defines

ADC_injected_length

ADC_Exported_Constants

Defines

#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))

Define Documentation

#define IS_ADC_INJECTED_LENGTH ( LENGTH ) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))

Definition at line 513 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedSequencerLengthConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_injected_rank

Defines

ADC_injected_rank

ADC_Exported_Constants

Defines

#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))

Define Documentation

#define IS_ADC_INJECTED_RANK ( RANK ) (((RANK) >= 0x1) && ((RANK) <= 0x4))

Definition at line 523 of file stm32l1xx_adc.h.

Referenced by ADC_InjectedChannelConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_regular_length

Defines

ADC_regular_length

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))

Define Documentation

#define IS_ADC_REGULAR_LENGTH ( LENGTH ) (((LENGTH) >= 1) && ((LENGTH) <= 28))

Definition at line 533 of file stm32l1xx_adc.h.

Referenced by ADC_Init().


STM32L1xx Standard Peripherals Firmware Library: ADC_regular_rank

Defines

ADC_regular_rank

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))

Define Documentation

#define IS_ADC_REGULAR_RANK ( RANK ) (((RANK) >= 1) && ((RANK) <= 28))

Definition at line 543 of file stm32l1xx_adc.h.

Referenced by ADC_RegularChannelConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_regular_discontinuous_mode_number

Defines

ADC_regular_discontinuous_mode_number

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))

Define Documentation

#define IS_ADC_REGULAR_DISC_NUMBER ( NUMBER ) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))

Definition at line 553 of file stm32l1xx_adc.h.

Referenced by ADC_DiscModeChannelCountConfig().


STM32L1xx Standard Peripherals Firmware Library: ADC_Bank_Selection

Defines

ADC_Bank_Selection

ADC_Exported_Constants

Defines

#define | ADC_Bank_A ((uint8_t)0x00)
#define | ADC_Bank_B ((uint8_t)0x01)
#define | IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))

Define Documentation

#define ADC_Bank_A ((uint8_t)0x00)

Definition at line 562 of file stm32l1xx_adc.h.

Referenced by ADC_BankSelection().

#define ADC_Bank_B ((uint8_t)0x01)

Definition at line 563 of file stm32l1xx_adc.h.

#define IS_ADC_BANK ( BANK ) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))

Definition at line 564 of file stm32l1xx_adc.h.

Referenced by ADC_BankSelection().


STM32L1xx Standard Peripherals Firmware Library: ADC_Exported_Constants

Modules | Defines

ADC_Exported_Constants

ADC

Modules

ADC_Power_down_during_Idle_and_or_Delay_phase
ADC_Prescaler
ADC_Resolution
ADC_external_trigger_edge_for_regular_channels_conversion
ADC_external_trigger_sources_for_regular_channels_conversion
ADC_data_align
ADC_channels
ADC_sampling_times
ADC_Delay_length
ADC_external_trigger_edge_for_injected_channels_conversion
ADC_external_trigger_sources_for_injected_channels_conversion
ADC_injected_channel_selection
ADC_analog_watchdog_selection
ADC_interrupts_definition
ADC_flags_definition
ADC_thresholds
ADC_injected_offset
ADC_injected_length
ADC_injected_rank
ADC_regular_length
ADC_regular_rank
ADC_regular_discontinuous_mode_number
ADC_Bank_Selection

Defines

#define | IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
#define | IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)

Define Documentation

#define IS_ADC_ALL_PERIPH ( PERIPH ) ((PERIPH) == ADC1)

Definition at line 92 of file stm32l1xx_adc.h.

Referenced by ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AnalogWatchdogThresholdsConfig(), ADC_AutoInjectedConvCmd(), ADC_BankSelection(), ADC_ClearFlag(), ADC_ClearITPendingBit(), ADC_Cmd(), ADC_ContinuousModeCmd(), ADC_DeInit(), ADC_DelaySelectionConfig(), ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_DMARequestAfterLastTransferCmd(), ADC_EOCOnEachRegularChannelCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_ExternalTrigInjectedConvEdgeConfig(), ADC_GetConversionValue(), ADC_GetFlagStatus(), ADC_GetInjectedConversionValue(), ADC_GetITStatus(), ADC_GetSoftwareStartConvStatus(), ADC_GetSoftwareStartInjectedConvCmdStatus(), ADC_Init(), ADC_InjectedChannelConfig(), ADC_InjectedDiscModeCmd(), ADC_InjectedSequencerLengthConfig(), ADC_ITConfig(), ADC_PowerDownCmd(), ADC_RegularChannelConfig(), ADC_SetInjectedOffset(), ADC_SoftwareStartConv(), and ADC_SoftwareStartInjectedConv().

#define IS_ADC_DMA_PERIPH ( PERIPH ) ((PERIPH) == ADC1)

Definition at line 93 of file stm32l1xx_adc.h.

Referenced by ADC_DMACmd().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

ADC_Private_Functions

Initialization and Configuration functions. More...

Functions

void | ADC_BankSelection (ADC_TypeDef *ADCx, uint8_t ADC_Bank)
Selects the specified ADC Channels Bank.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
void | ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes ADC1 peripheral registers to their default reset values.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and Configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
        (+) Initialize and configure the ADC Prescaler.
        (+) ADC Conversion Resolution (12bit..6bit).
        (+) Scan Conversion Mode (multichannel or one channel) for regular group.
        (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
            regular group.
        (+) External trigger Edge and source of regular group.
        (+) Converted data alignment (left or right).
        (+) The number of ADC conversions that will be done using the sequencer
            for regular channel group.
        (+) Enable or disable the ADC peripheral.

Function Documentation

void ADC_BankSelection | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Bank
 | ) |  |

Selects the specified ADC Channels Bank.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Bank,: ADC Channels Bank.

  • ADC_Bank_A: ADC Channels Bank A.
  • ADC_Bank_B: ADC Channels Bank B.
Return values:
None

Definition at line 379 of file stm32l1xx_adc.c.

References ADC_Bank_A, ADC_CR2_CFG, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, and IS_ADC_BANK.

void ADC_Cmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC peripheral.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 353 of file stm32l1xx_adc.c.

References ADC_CR2_ADON, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_CommonInit ( ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.

Parameters:
ADC_CommonInitStruct,: pointer to an ADC_CommonInitTypeDef structure that contains the configuration information (Prescaler) for ADC1 peripheral.
Return values:
None

Definition at line 312 of file stm32l1xx_adc.c.

References ADC, ADC_CommonInitTypeDef::ADC_Prescaler, CR_CLEAR_MASK, and IS_ADC_PRESCALER.

void ADC_CommonStructInit ( ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Fills each ADC_CommonInitStruct member with its default value.

Parameters:
ADC_CommonInitStruct,: pointer to an ADC_CommonInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 339 of file stm32l1xx_adc.c.

References ADC_CommonInitTypeDef::ADC_Prescaler, and ADC_Prescaler_Div1.

void ADC_DeInit ( ADC_TypeDef * ADCx )

Deinitializes ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 187 of file stm32l1xx_adc.c.

References ADC1, DISABLE, ENABLE, IS_ADC_ALL_PERIPH, RCC_APB2Periph_ADC1, and RCC_APB2PeriphResetCmd().

void ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

Note:
This function is used to configure the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
Return values:
None

Definition at line 214 of file stm32l1xx_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_InitTypeDef::ADC_ExternalTrigConvEdge, ADC_InitTypeDef::ADC_NbrOfConversion, ADC_InitTypeDef::ADC_Resolution, ADC_InitTypeDef::ADC_ScanConvMode, ADC_TypeDef::CR1, CR1_CLEAR_MASK, ADC_TypeDef::CR2, CR2_CLEAR_MASK, IS_ADC_ALL_PERIPH, IS_ADC_DATA_ALIGN, IS_ADC_EXT_TRIG, IS_ADC_EXT_TRIG_EDGE, IS_ADC_REGULAR_LENGTH, IS_ADC_RESOLUTION, IS_FUNCTIONAL_STATE, ADC_TypeDef::SQR1, and SQR1_L_RESET.

void ADC_StructInit ( ADC_InitTypeDef * ADC_InitStruct )

Fills each ADC_InitStruct member with its default value.

Note:
This function is used to initialize the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
Parameters:
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 280 of file stm32l1xx_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_T2_CC2, ADC_InitTypeDef::ADC_ExternalTrigConvEdge, ADC_ExternalTrigConvEdge_None, ADC_InitTypeDef::ADC_NbrOfConversion, ADC_InitTypeDef::ADC_Resolution, ADC_Resolution_12b, ADC_InitTypeDef::ADC_ScanConvMode, and DISABLE.


STM32L1xx Standard Peripherals Firmware Library: Power saving functions

Functions

Power saving functions

ADC_Private_Functions

Power saving functions. More...

Functions

void | ADC_DelaySelectionConfig (ADC_TypeDef *ADCx, uint8_t ADC_DelayLength)
Defines the length of the delay which is applied after a conversion or a sequence of conversion.
void | ADC_PowerDownCmd (ADC_TypeDef *ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
Enables or disables the ADC Power Down during Delay and/or Idle phase.

Detailed Description

Power saving functions.

 ===============================================================================
                    ##### Power saving functions #####
 ===============================================================================
    [..] This section provides functions allowing to reduce power consumption.
    [..] The two function must be combined to get the maximal benefits:
         When the ADC frequency is higher than the CPU one, it is recommended to:
         (#) Insert a freeze delay :
             ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze).
         (#) Enable the power down in Idle and Delay phases :
             ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE).

Function Documentation

void ADC_DelaySelectionConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_DelayLength
 | ) |  |

Defines the length of the delay which is applied after a conversion or a sequence of conversion.

Note:
When the CPU clock is not fast enough to manage the data rate, a Hardware delay can be introduced between ADC conversions to reduce this data rate.
The Hardware delay is inserted after :
  • each regular conversion.
  • after each sequence of injected conversions.
No Hardware delay is inserted between conversions of different groups.
When the hardware delay is not enough, the Freeze Delay Mode can be selected and a new conversion can start only if all the previous data of the same group have been treated:
  • for a regular conversion: once the ADC conversion data register has been read (using ADC_GetConversionValue() function) or if the EOC Flag has been cleared (using ADC_ClearFlag() function).
  • for an injected conversion: when the JEOC bit has been cleared (using ADC_ClearFlag() function).
Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_DelayLength,: The length of delay which is applied after a conversion or a sequence of conversion. This parameter can be one of the following values:

  • ADC_DelayLength_None: No delay.
  • ADC_DelayLength_Freeze: Delay until the converted data has been read.
  • ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.
  • ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles
  • ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles
  • ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles
  • ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles
  • ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles
Return values:
None

Definition at line 496 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_DELS_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_DELAY_LENGTH.

void ADC_PowerDownCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_PowerDown,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC Power Down during Delay and/or Idle phase.

Note:
ADC power-on and power-off can be managed by hardware to cut the consumption when the ADC is not converting.
Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_PowerDown,: The ADC power down configuration. This parameter can be one of the following values:

  • ADC_PowerDown_Delay: ADC is powered down during delay phase.
  • ADC_PowerDown_Idle: ADC is powered down during Idle phase.
  • ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.
Note:
The ADC can be powered down:
During the hardware delay insertion (using the ADC_PowerDown_Delay parameter). => The ADC is powered up again at the end of the delay.
During the ADC is waiting for a trigger event ( using the ADC_PowerDown_Idle parameter). => The ADC is powered up at the next trigger event.
During the hardware delay insertion or the ADC is waiting for a trigger event (using the ADC_PowerDown_Idle_Delay parameter). => The ADC is powered up only at the end of the delay and at the next trigger event.
Parameters:
NewState,: new state of the ADCx power down. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 445 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_POWER_DOWN, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Analog Watchdog configuration functions

Functions

Analog Watchdog configuration functions

ADC_Private_Functions

Analog Watchdog configuration functions. More...

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.

Detailed Description

Analog Watchdog configuration functions.

 ===============================================================================
                   ##### Analog Watchdog configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to configure the Analog Watchdog
         (AWD) feature in the ADC.
    [..] A typical configuration Analog Watchdog is done following these steps :
         (#) the ADC guarded channel(s) is (are) selected using the
             ADC_AnalogWatchdogSingleChannelConfig() function.
         (#) The Analog watchdog lower and higher threshold are configured using
             the ADC_AnalogWatchdogThresholdsConfig() function.
         (#) The Analog watchdog is enabled and configured to enable the check,
             on one or more channels, using the  ADC_AnalogWatchdogCmd() function.

Function Documentation

void ADC_AnalogWatchdogCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_AnalogWatchdog
 | ) |  |

Enables or disables the analog watchdog on single/all regular or injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_AnalogWatchdog,: the ADC analog watchdog configuration. This parameter can be one of the following values:

  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel.
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel.
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel.
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel.
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel.
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels.
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.
Return values:
None

Definition at line 561 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_AWDMODE_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_ANALOG_WATCHDOG.

void ADC_AnalogWatchdogSingleChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel
 | ) |  |

Configures the analog watchdog guarded single channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Channel,: the ADC channel to configure for the analog watchdog. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Return values:
None

Definition at line 651 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_AWDCH_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_CHANNEL.

void ADC_AnalogWatchdogThresholdsConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | HighThreshold,
 |  | uint16_t | LowThreshold
 | ) |  |

Configures the high and low thresholds of the analog watchdog.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
HighThreshold,: the ADC analog watchdog High threshold value. This parameter must be a 12bit value.
LowThreshold,: the ADC analog watchdog Low threshold value. This parameter must be a 12bit value.
Return values:
None

Definition at line 588 of file stm32l1xx_adc.c.

References ADC_TypeDef::HTR, IS_ADC_ALL_PERIPH, IS_ADC_THRESHOLD, and ADC_TypeDef::LTR.


STM32L1xx Standard Peripherals Firmware Library: Temperature Sensor & Vrefint (Voltage Reference internal) management function

Functions

Temperature Sensor & Vrefint (Voltage Reference internal) management function

ADC_Private_Functions

Temperature Sensor & Vrefint (Voltage Reference internal) management function. More...

Functions

void ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

Temperature Sensor & Vrefint (Voltage Reference internal) management function.

 =========================================================================================
 ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####
 =========================================================================================
    [..] This section provides a function allowing to enable/ disable the internal
         connections between the ADC and the Temperature Sensor and the Vrefint
         source.
    [..] A typical configuration to get the Temperature sensor and Vrefint channels
         voltages is done following these steps :
         (#) Enable the internal connection of Temperature sensor and Vrefint sources
             with the ADC channels using ADC_TempSensorVrefintCmd() function.
         (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
             ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions.
         (#) Get the voltage values, using ADC_GetConversionValue() or
             ADC_GetInjectedConversionValue().

Function Documentation

void ADC_TempSensorVrefintCmd ( FunctionalState NewState )

Enables or disables the temperature sensor and Vrefint channel.

Parameters:
NewState,: new state of the temperature sensor and Vref int channels. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 701 of file stm32l1xx_adc.c.

References ADC, ADC_CCR_TSVREFE, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Regular Channels Configuration functions

Functions

Regular Channels Configuration functions

ADC_Private_Functions

Regular Channels Configuration functions. More...

Functions

void | ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.
void | ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.

Detailed Description

Regular Channels Configuration functions.

 ===============================================================================
            ##### Regular Channels Configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to manage the ADC regular channels,
         it is composed of 2 sub sections :
         (#) Configuration and management functions for regular channels: This
             subsection provides functions allowing to configure the ADC regular
             channels :
             (++) Configure the rank in the regular group sequencer for each channel.
             (++) Configure the sampling time for each channel.
             (++) select the conversion Trigger for regular channels.
             (++) select the desired EOC event behavior configuration.
             (++) Activate the continuous Mode  (*).
             (++) Activate the Discontinuous Mode.
             -@@- Please Note that the following features for regular channels are
                  configurated using the ADC_Init() function :
                  (+@@) scan mode activation.
                  (+@@) continuous mode activation (**).
                  (+@@) External trigger source.
                  (+@@) External trigger edge.
                  (+@@) number of conversion in the regular channels group sequencer.
             -@@- (*) and (**) are performing the same configuration.
         (#) Get the conversion data: This subsection provides an important function
             in the ADC peripheral since it returns the converted data of the current
             regular channel. When the Conversion value is read, the EOC Flag is
             automatically cleared.

Function Documentation

void ADC_ContinuousModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC continuous conversion mode.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC continuous conversion mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1049 of file stm32l1xx_adc.c.

References ADC_CR2_CONT, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_DiscModeChannelCountConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Number
 | ) |  |

Configures the discontinuous mode for the selected ADC regular group channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Number,: specifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
Return values:
None

Definition at line 1075 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_DISCNUM_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_REGULAR_DISC_NUMBER.

void ADC_DiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1104 of file stm32l1xx_adc.c.

References ADC_CR1_DISCEN, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_EOCOnEachRegularChannelCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the EOC on each regular channel conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1024 of file stm32l1xx_adc.c.

References ADC_CR2_EOCS, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

uint16_t ADC_GetConversionValue ( ADC_TypeDef * ADCx )

Returns the last ADCx conversion result data for regular channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The Data conversion value.

Definition at line 1127 of file stm32l1xx_adc.c.

References ADC_TypeDef::DR, and IS_ADC_ALL_PERIPH.

FlagStatus ADC_GetSoftwareStartConvStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start regular conversion Status.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The new state of ADC software start conversion (SET or RESET).

Definition at line 995 of file stm32l1xx_adc.c.

References ADC_CR2_SWSTART, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, RESET, and SET.

void ADC_RegularChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.

Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Rank,: The rank in the regular group sequencer. This parameter must be between 1 to 28.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
  • ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
  • ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
  • ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
  • ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
  • ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
  • ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
  • ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
Return values:
None

Definition at line 819 of file stm32l1xx_adc.c.

References ADC_Channel_19, ADC_Channel_29, ADC_Channel_9, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::SMPR0, SMPR0_SMP_SET, ADC_TypeDef::SMPR1, SMPR1_SMP_SET, ADC_TypeDef::SMPR2, SMPR2_SMP_SET, ADC_TypeDef::SMPR3, SMPR3_SMP_SET, ADC_TypeDef::SQR1, SQR1_SQ_SET, ADC_TypeDef::SQR2, SQR2_SQ_SET, ADC_TypeDef::SQR3, SQR3_SQ_SET, ADC_TypeDef::SQR4, SQR4_SQ_SET, ADC_TypeDef::SQR5, and SQR5_SQ_SET.

void ADC_SoftwareStartConv ( ADC_TypeDef * ADCx )

Enables the selected ADC software start conversion of the regular channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
None

Definition at line 981 of file stm32l1xx_adc.c.

References ADC_CR2_SWSTART, ADC_TypeDef::CR2, and IS_ADC_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Regular Channels DMA Configuration functions

Functions

Regular Channels DMA Configuration functions

ADC_Private_Functions

Regular Channels DMA Configuration functions. More...

Functions

void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode).

Detailed Description

Regular Channels DMA Configuration functions.

 ===============================================================================
          ##### Regular Channels DMA Configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to configure the DMA for ADC regular
         channels.Since converted regular channel values are stored into a unique
         data register, it is useful to use DMA for conversion of more than one
         regular channel. This avoids the loss of the data already stored in the
         ADC Data register.
         When the DMA mode is enabled (using the ADC_DMACmd() function), after each
         conversion of a regular channel, a DMA request is generated.
    [..] Depending on the "DMA disable selection" configuration (using the
         ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA
         transfer, two possibilities are allowed:
         (+) No new DMA request is issued to the DMA controller (feature DISABLED).
         (+) Requests can continue to be generated (feature ENABLED).

Function Documentation

void ADC_DMACmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC DMA request.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1171 of file stm32l1xx_adc.c.

References ADC_CR2_DMA, ADC_TypeDef::CR2, DISABLE, IS_ADC_DMA_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_DMARequestAfterLastTransferCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC DMA request after last transfer (Single-ADC mode).

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1197 of file stm32l1xx_adc.c.

References ADC_CR2_DDS, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Injected channels Configuration functions

Functions

Injected channels Configuration functions

ADC_Private_Functions

Injected channels Configuration functions. More...

Functions

void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
void | ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.

Detailed Description

Injected channels Configuration functions.

 ===============================================================================
            ##### Injected channels Configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the ADC Injected channels,
         it is composed of 2 sub sections :
         (#) Configuration functions for Injected channels: This subsection provides
             functions allowing to configure the ADC injected channels :
             (++) Configure the rank in the injected group sequencer for each channel.
             (++) Configure the sampling time for each channel.
             (++) Activate the Auto injected Mode.
             (++) Activate the Discontinuous Mode.
             (++) scan mode activation.
             (++) External/software trigger source.
             (++) External trigger edge.
             (++) injected channels sequencer.

         (#) Get the Specified Injected channel conversion data: This subsection
             provides an important function in the ADC peripheral since it returns
             the converted data of the specific injected channel.

Function Documentation

void ADC_AutoInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC automatic injected group conversion after regular one.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC auto injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1575 of file stm32l1xx_adc.c.

References ADC_CR1_JAUTO, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_ExternalTrigInjectedConvConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConv
 | ) |  |

Configures the ADCx external trigger for injected channels conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_ExternalTrigInjecConv,: specifies the ADC trigger to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
  • ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
  • ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected
  • ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
Return values:
None

Definition at line 1475 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_JEXTSEL_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG.

void ADC_ExternalTrigInjectedConvEdgeConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConvEdge
 | ) |  |

Configures the ADCx external trigger edge for injected channels conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_ExternalTrigInjecConvEdge,: specifies the ADC external trigger edge to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigConvEdge_None: external trigger disabled for injected conversion.
  • ADC_ExternalTrigConvEdge_Rising: detection on rising edge
  • ADC_ExternalTrigConvEdge_Falling: detection on falling edge
  • ADC_ExternalTrigConvEdge_RisingFalling: detection on both rising and falling edge
Return values:
None

Definition at line 1507 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_JEXTEN_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG_EDGE.

uint16_t ADC_GetInjectedConversionValue | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel
 | ) |  |

Returns the ADC injected channel conversion result.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_InjectedChannel,: the converted ADC injected channel. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Return values:
The Data conversion value.

Definition at line 1630 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and JDR_OFFSET.

FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start injected conversion Status.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The new state of ADC software start injected conversion (SET or RESET).

Definition at line 1544 of file stm32l1xx_adc.c.

References ADC_CR2_JSWSTART, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, RESET, and SET.

void ADC_InjectedChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Rank,: The rank in the injected group sequencer. This parameter must be between 1 to 4.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
  • ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
  • ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
  • ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
  • ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
  • ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
  • ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
  • ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
Return values:
None

Definition at line 1309 of file stm32l1xx_adc.c.

References ADC_Channel_19, ADC_Channel_29, ADC_Channel_9, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_INJECTED_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::JSQR, JSQR_JL_SET, JSQR_JSQ_SET, ADC_TypeDef::SMPR0, SMPR0_SMP_SET, ADC_TypeDef::SMPR1, SMPR1_SMP_SET, ADC_TypeDef::SMPR2, SMPR2_SMP_SET, ADC_TypeDef::SMPR3, and SMPR3_SMP_SET.

void ADC_InjectedDiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1601 of file stm32l1xx_adc.c.

References ADC_CR1_JDISCEN, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_InjectedSequencerLengthConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Length
 | ) |  |

Configures the sequencer length for injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Length,: The sequencer length. This parameter must be a number between 1 to 4.
Return values:
None

Definition at line 1407 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_LENGTH, ADC_TypeDef::JSQR, and JSQR_JL_RESET.

void ADC_SetInjectedOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel,
 |  | uint16_t | Offset
 | ) |  |

Set the injected channels conversion value offset.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_InjectedChannel,: the ADC injected channel to set its offset. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected.
  • ADC_InjectedChannel_2: Injected Channel2 selected.
  • ADC_InjectedChannel_3: Injected Channel3 selected.
  • ADC_InjectedChannel_4: Injected Channel4 selected.
Offset,: the offset value for the selected ADC injected channel This parameter must be a 12bit value.
Return values:
None

Definition at line 1440 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and IS_ADC_OFFSET.

void ADC_SoftwareStartInjectedConv ( ADC_TypeDef * ADCx )

Enables the selected ADC software start conversion of the injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
None

Definition at line 1531 of file stm32l1xx_adc.c.

References ADC_CR2_JSWSTART, ADC_TypeDef::CR2, and IS_ADC_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

ADC_Private_Functions

Interrupts and flags management functions. More...

Functions

void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
            ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] This section provides functions allowing to configure the ADC Interrupts
         and get the status and clear flags and Interrupts pending bits.

    [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into
         3 groups:
  *** Flags and Interrupts for ADC regular channels ***
  =====================================================
    [..]
        (+)Flags :
           (##) ADC_FLAG_OVR : Overrun detection when regular converted data are
                lost.
           (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate
                (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
                the end of :
                (+++) a regular CHANNEL conversion.
                (+++) sequence of regular GROUP conversions.

           (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular
                CHANNEL conversion starts.
           (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new
                regular conversion can be launched.
        (+)Interrupts :
           (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
                event.
           (##) ADC_IT_EOC : specifies the interrupt source for Regular channel
                end of conversion event.

  *** Flags and Interrupts for ADC Injected channels ***
  ======================================================
        (+)Flags :
           (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at
                the end of injected GROUP conversion.
           (##) ADC_FLAG_JSTRT: Injected channel start +  to indicate hardware when
                injected GROUP conversion starts.
           (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new
                injected conversion can be launched.
        (+)Interrupts
           (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
                end of conversion event.
  *** General Flags and Interrupts for the ADC ***
  ================================================
        (+)Flags :
           (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage
                crosses the programmed thresholds values.
           (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready
                to convert.
        (+)Interrupts :
           (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog
                event.

    [..] The user should identify which mode will be used in his application to
         manage the ADC controller events: Polling mode or Interrupt mode.

    [..] In the Polling Mode it is advised to use the following functions:
         (+) ADC_GetFlagStatus() : to check if flags events occur.
         (+) ADC_ClearFlag()     : to clear the flags events.

    [..] In the Interrupt Mode it is advised to use the following functions:
         (+) ADC_ITConfig()       : to enable or disable the interrupt source.
         (+) ADC_GetITStatus()    : to check if Interrupt occurs.
         (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
             (corresponding Flag).

Function Documentation

void ADC_ClearFlag | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_FLAG
 | ) |  |

Clears the ADCx's pending flags.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
  • ADC_FLAG_OVR: overrun flag
Return values:
None

Definition at line 1813 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_CLEAR_FLAG, and ADC_TypeDef::SR.

void ADC_ClearITPendingBit | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Clears the ADCx's interrupt pending bits.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_IT,: specifies the ADC interrupt pending bit to clear. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: Overrun interrupt
Return values:
None

Definition at line 1875 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_IT, and ADC_TypeDef::SR.

FlagStatus ADC_GetFlagStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_FLAG
 | ) |  |

Checks whether the specified ADC flag is set or not.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
  • ADC_FLAG_OVR: Overrun flag
  • ADC_FLAG_ADONS: ADC ON status
  • ADC_FLAG_RCNR: Regular channel not ready
  • ADC_FLAG_JCNR: Injected channel not ready
Return values:
The new state of ADC_FLAG (SET or RESET).

Definition at line 1777 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_GET_FLAG, RESET, SET, and ADC_TypeDef::SR.

ITStatus ADC_GetITStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Checks whether the specified ADC interrupt has occurred or not.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_IT,: specifies the ADC interrupt source to check. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: Overrun interrupt
Return values:
The new state of ADC_IT (SET or RESET).

Definition at line 1834 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, IS_ADC_ALL_PERIPH, IS_ADC_IT, RESET, SET, and ADC_TypeDef::SR.

void ADC_ITConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC interrupts.

Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: overrun interrupt
NewState,: new state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1736 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_IT, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: ADC

Data Structures | Modules | Defines | Functions

ADC

STM32L1xx_StdPeriph_Driver

ADC driver modules. More...

Data Structures

struct | ADC_CommonInitTypeDef
struct | ADC_InitTypeDef
ADC Init structure definition. More...

Modules

ADC_Exported_Constants
ADC_Private_Functions

Defines

#define | CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
#define | CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
#define | CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
#define | CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
#define | CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
#define | CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)
#define | CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
#define | CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
#define | CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF)
#define | JDR_OFFSET ((uint8_t)0x30)
#define | JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
#define | JSQR_JL_SET ((uint32_t)0x00300000)
#define | JSQR_JSQ_SET ((uint32_t)0x0000001F)
#define | SMPR0_SMP_SET ((uint32_t)0x00000007)
#define | SMPR1_SMP_SET ((uint32_t)0x00000007)
#define | SMPR2_SMP_SET ((uint32_t)0x00000007)
#define | SMPR3_SMP_SET ((uint32_t)0x00000007)
#define | SQR1_L_RESET ((uint32_t)0xFE0FFFFF)
#define | SQR1_SQ_SET ((uint32_t)0x0000001F)
#define | SQR2_SQ_SET ((uint32_t)0x0000001F)
#define | SQR3_SQ_SET ((uint32_t)0x0000001F)
#define | SQR4_SQ_SET ((uint32_t)0x0000001F)
#define | SQR5_SQ_SET ((uint32_t)0x0000001F)

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_BankSelection (ADC_TypeDef *ADCx, uint8_t ADC_Bank)
Selects the specified ADC Channels Bank.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
void | ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
void | ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes ADC1 peripheral registers to their default reset values.
void | ADC_DelaySelectionConfig (ADC_TypeDef *ADCx, uint8_t ADC_DelayLength)
Defines the length of the delay which is applied after a conversion or a sequence of conversion.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode).
void | ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
void | ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_PowerDownCmd (ADC_TypeDef *ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
Enables or disables the ADC Power Down during Delay and/or Idle phase.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.
void | ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

ADC driver modules.

Define Documentation

#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)

Definition at line 101 of file stm32l1xx_adc.c.

Referenced by ADC_AnalogWatchdogSingleChannelConfig().

#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)

Definition at line 104 of file stm32l1xx_adc.c.

Referenced by ADC_AnalogWatchdogCmd().

#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)

Definition at line 107 of file stm32l1xx_adc.c.

Referenced by ADC_Init().

#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)

Definition at line 98 of file stm32l1xx_adc.c.

Referenced by ADC_DiscModeChannelCountConfig().

#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)

Definition at line 119 of file stm32l1xx_adc.c.

Referenced by ADC_Init().

#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)

Definition at line 110 of file stm32l1xx_adc.c.

Referenced by ADC_DelaySelectionConfig().

#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)

Definition at line 113 of file stm32l1xx_adc.c.

Referenced by ADC_ExternalTrigInjectedConvEdgeConfig().

#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)

Definition at line 116 of file stm32l1xx_adc.c.

Referenced by ADC_ExternalTrigInjectedConvConfig().

#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF)

Definition at line 148 of file stm32l1xx_adc.c.

Referenced by ADC_CommonInit().

#define JDR_OFFSET ((uint8_t)0x30)

Definition at line 145 of file stm32l1xx_adc.c.

Referenced by ADC_GetInjectedConversionValue().

#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)

Definition at line 136 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedSequencerLengthConfig().

#define JSQR_JL_SET ((uint32_t)0x00300000)

Definition at line 135 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig().

#define JSQR_JSQ_SET ((uint32_t)0x0000001F)

Definition at line 132 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig().

#define SMPR0_SMP_SET ((uint32_t)0x00000007)

Definition at line 142 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SMPR1_SMP_SET ((uint32_t)0x00000007)

Definition at line 139 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SMPR2_SMP_SET ((uint32_t)0x00000007)

Definition at line 140 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SMPR3_SMP_SET ((uint32_t)0x00000007)

Definition at line 141 of file stm32l1xx_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF)

Definition at line 129 of file stm32l1xx_adc.c.

Referenced by ADC_Init().

#define SQR1_SQ_SET ((uint32_t)0x0000001F)

Definition at line 126 of file stm32l1xx_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR2_SQ_SET ((uint32_t)0x0000001F)

Definition at line 125 of file stm32l1xx_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR3_SQ_SET ((uint32_t)0x0000001F)

Definition at line 124 of file stm32l1xx_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR4_SQ_SET ((uint32_t)0x0000001F)

Definition at line 123 of file stm32l1xx_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR5_SQ_SET ((uint32_t)0x0000001F)

Definition at line 122 of file stm32l1xx_adc.c.

Referenced by ADC_RegularChannelConfig().

Function Documentation

void ADC_AnalogWatchdogCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_AnalogWatchdog
 | ) |  |

Enables or disables the analog watchdog on single/all regular or injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_AnalogWatchdog,: the ADC analog watchdog configuration. This parameter can be one of the following values:

  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel.
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel.
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel.
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel.
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel.
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels.
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.
Return values:
None

Definition at line 561 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_AWDMODE_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_ANALOG_WATCHDOG.

void ADC_AnalogWatchdogSingleChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel
 | ) |  |

Configures the analog watchdog guarded single channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Channel,: the ADC channel to configure for the analog watchdog. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Return values:
None

Definition at line 651 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_AWDCH_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_CHANNEL.

void ADC_AnalogWatchdogThresholdsConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | HighThreshold,
 |  | uint16_t | LowThreshold
 | ) |  |

Configures the high and low thresholds of the analog watchdog.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
HighThreshold,: the ADC analog watchdog High threshold value. This parameter must be a 12bit value.
LowThreshold,: the ADC analog watchdog Low threshold value. This parameter must be a 12bit value.
Return values:
None

Definition at line 588 of file stm32l1xx_adc.c.

References ADC_TypeDef::HTR, IS_ADC_ALL_PERIPH, IS_ADC_THRESHOLD, and ADC_TypeDef::LTR.

void ADC_AutoInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC automatic injected group conversion after regular one.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC auto injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1575 of file stm32l1xx_adc.c.

References ADC_CR1_JAUTO, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_BankSelection | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Bank
 | ) |  |

Selects the specified ADC Channels Bank.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Bank,: ADC Channels Bank.

  • ADC_Bank_A: ADC Channels Bank A.
  • ADC_Bank_B: ADC Channels Bank B.
Return values:
None

Definition at line 379 of file stm32l1xx_adc.c.

References ADC_Bank_A, ADC_CR2_CFG, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, and IS_ADC_BANK.

void ADC_ClearFlag | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_FLAG
 | ) |  |

Clears the ADCx's pending flags.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
  • ADC_FLAG_OVR: overrun flag
Return values:
None

Definition at line 1813 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_CLEAR_FLAG, and ADC_TypeDef::SR.

void ADC_ClearITPendingBit | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Clears the ADCx's interrupt pending bits.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_IT,: specifies the ADC interrupt pending bit to clear. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: Overrun interrupt
Return values:
None

Definition at line 1875 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_IT, and ADC_TypeDef::SR.

void ADC_Cmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC peripheral.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 353 of file stm32l1xx_adc.c.

References ADC_CR2_ADON, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_CommonInit ( ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.

Parameters:
ADC_CommonInitStruct,: pointer to an ADC_CommonInitTypeDef structure that contains the configuration information (Prescaler) for ADC1 peripheral.
Return values:
None

Definition at line 312 of file stm32l1xx_adc.c.

References ADC, ADC_CommonInitTypeDef::ADC_Prescaler, CR_CLEAR_MASK, and IS_ADC_PRESCALER.

void ADC_CommonStructInit ( ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Fills each ADC_CommonInitStruct member with its default value.

Parameters:
ADC_CommonInitStruct,: pointer to an ADC_CommonInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 339 of file stm32l1xx_adc.c.

References ADC_CommonInitTypeDef::ADC_Prescaler, and ADC_Prescaler_Div1.

void ADC_ContinuousModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC continuous conversion mode.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC continuous conversion mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1049 of file stm32l1xx_adc.c.

References ADC_CR2_CONT, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_DeInit ( ADC_TypeDef * ADCx )

Deinitializes ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 187 of file stm32l1xx_adc.c.

References ADC1, DISABLE, ENABLE, IS_ADC_ALL_PERIPH, RCC_APB2Periph_ADC1, and RCC_APB2PeriphResetCmd().

void ADC_DelaySelectionConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_DelayLength
 | ) |  |

Defines the length of the delay which is applied after a conversion or a sequence of conversion.

Note:
When the CPU clock is not fast enough to manage the data rate, a Hardware delay can be introduced between ADC conversions to reduce this data rate.
The Hardware delay is inserted after :
  • each regular conversion.
  • after each sequence of injected conversions.
No Hardware delay is inserted between conversions of different groups.
When the hardware delay is not enough, the Freeze Delay Mode can be selected and a new conversion can start only if all the previous data of the same group have been treated:
  • for a regular conversion: once the ADC conversion data register has been read (using ADC_GetConversionValue() function) or if the EOC Flag has been cleared (using ADC_ClearFlag() function).
  • for an injected conversion: when the JEOC bit has been cleared (using ADC_ClearFlag() function).
Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_DelayLength,: The length of delay which is applied after a conversion or a sequence of conversion. This parameter can be one of the following values:

  • ADC_DelayLength_None: No delay.
  • ADC_DelayLength_Freeze: Delay until the converted data has been read.
  • ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.
  • ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles
  • ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles
  • ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles
  • ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles
  • ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles
Return values:
None

Definition at line 496 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_DELS_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_DELAY_LENGTH.

void ADC_DiscModeChannelCountConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Number
 | ) |  |

Configures the discontinuous mode for the selected ADC regular group channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Number,: specifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
Return values:
None

Definition at line 1075 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, CR1_DISCNUM_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_REGULAR_DISC_NUMBER.

void ADC_DiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1104 of file stm32l1xx_adc.c.

References ADC_CR1_DISCEN, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_DMACmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC DMA request.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1171 of file stm32l1xx_adc.c.

References ADC_CR2_DMA, ADC_TypeDef::CR2, DISABLE, IS_ADC_DMA_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_DMARequestAfterLastTransferCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC DMA request after last transfer (Single-ADC mode).

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1197 of file stm32l1xx_adc.c.

References ADC_CR2_DDS, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_EOCOnEachRegularChannelCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the EOC on each regular channel conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1024 of file stm32l1xx_adc.c.

References ADC_CR2_EOCS, ADC_TypeDef::CR2, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_ExternalTrigInjectedConvConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConv
 | ) |  |

Configures the ADCx external trigger for injected channels conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_ExternalTrigInjecConv,: specifies the ADC trigger to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
  • ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
  • ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected
  • ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected
  • ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
Return values:
None

Definition at line 1475 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_JEXTSEL_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG.

void ADC_ExternalTrigInjectedConvEdgeConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConvEdge
 | ) |  |

Configures the ADCx external trigger edge for injected channels conversion.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_ExternalTrigInjecConvEdge,: specifies the ADC external trigger edge to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigConvEdge_None: external trigger disabled for injected conversion.
  • ADC_ExternalTrigConvEdge_Rising: detection on rising edge
  • ADC_ExternalTrigConvEdge_Falling: detection on falling edge
  • ADC_ExternalTrigConvEdge_RisingFalling: detection on both rising and falling edge
Return values:
None

Definition at line 1507 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR2, CR2_JEXTEN_RESET, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG_EDGE.

uint16_t ADC_GetConversionValue ( ADC_TypeDef * ADCx )

Returns the last ADCx conversion result data for regular channel.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The Data conversion value.

Definition at line 1127 of file stm32l1xx_adc.c.

References ADC_TypeDef::DR, and IS_ADC_ALL_PERIPH.

FlagStatus ADC_GetFlagStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_FLAG
 | ) |  |

Checks whether the specified ADC flag is set or not.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
  • ADC_FLAG_OVR: Overrun flag
  • ADC_FLAG_ADONS: ADC ON status
  • ADC_FLAG_RCNR: Regular channel not ready
  • ADC_FLAG_JCNR: Injected channel not ready
Return values:
The new state of ADC_FLAG (SET or RESET).

Definition at line 1777 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_GET_FLAG, RESET, SET, and ADC_TypeDef::SR.

uint16_t ADC_GetInjectedConversionValue | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel
 | ) |  |

Returns the ADC injected channel conversion result.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_InjectedChannel,: the converted ADC injected channel. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Return values:
The Data conversion value.

Definition at line 1630 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and JDR_OFFSET.

ITStatus ADC_GetITStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Checks whether the specified ADC interrupt has occurred or not.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_IT,: specifies the ADC interrupt source to check. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: Overrun interrupt
Return values:
The new state of ADC_IT (SET or RESET).

Definition at line 1834 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, IS_ADC_ALL_PERIPH, IS_ADC_IT, RESET, SET, and ADC_TypeDef::SR.

FlagStatus ADC_GetSoftwareStartConvStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start regular conversion Status.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The new state of ADC software start conversion (SET or RESET).

Definition at line 995 of file stm32l1xx_adc.c.

References ADC_CR2_SWSTART, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, RESET, and SET.

FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start injected conversion Status.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
The new state of ADC software start injected conversion (SET or RESET).

Definition at line 1544 of file stm32l1xx_adc.c.

References ADC_CR2_JSWSTART, ADC_TypeDef::CR2, IS_ADC_ALL_PERIPH, RESET, and SET.

void ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

Note:
This function is used to configure the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
Return values:
None

Definition at line 214 of file stm32l1xx_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_InitTypeDef::ADC_ExternalTrigConvEdge, ADC_InitTypeDef::ADC_NbrOfConversion, ADC_InitTypeDef::ADC_Resolution, ADC_InitTypeDef::ADC_ScanConvMode, ADC_TypeDef::CR1, CR1_CLEAR_MASK, ADC_TypeDef::CR2, CR2_CLEAR_MASK, IS_ADC_ALL_PERIPH, IS_ADC_DATA_ALIGN, IS_ADC_EXT_TRIG, IS_ADC_EXT_TRIG_EDGE, IS_ADC_REGULAR_LENGTH, IS_ADC_RESOLUTION, IS_FUNCTIONAL_STATE, ADC_TypeDef::SQR1, and SQR1_L_RESET.

void ADC_InjectedChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Rank,: The rank in the injected group sequencer. This parameter must be between 1 to 4.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
  • ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
  • ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
  • ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
  • ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
  • ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
  • ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
  • ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
Return values:
None

Definition at line 1309 of file stm32l1xx_adc.c.

References ADC_Channel_19, ADC_Channel_29, ADC_Channel_9, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_INJECTED_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::JSQR, JSQR_JL_SET, JSQR_JSQ_SET, ADC_TypeDef::SMPR0, SMPR0_SMP_SET, ADC_TypeDef::SMPR1, SMPR1_SMP_SET, ADC_TypeDef::SMPR2, SMPR2_SMP_SET, ADC_TypeDef::SMPR3, and SMPR3_SMP_SET.

void ADC_InjectedDiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
NewState,: new state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1601 of file stm32l1xx_adc.c.

References ADC_CR1_JDISCEN, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_InjectedSequencerLengthConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Length
 | ) |  |

Configures the sequencer length for injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Length,: The sequencer length. This parameter must be a number between 1 to 4.
Return values:
None

Definition at line 1407 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_LENGTH, ADC_TypeDef::JSQR, and JSQR_JL_RESET.

void ADC_ITConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC interrupts.

Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt
  • ADC_IT_AWD: Analog watchdog interrupt
  • ADC_IT_JEOC: End of injected conversion interrupt
  • ADC_IT_OVR: overrun interrupt
NewState,: new state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1736 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_IT, and IS_FUNCTIONAL_STATE.

void ADC_PowerDownCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_PowerDown,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC Power Down during Delay and/or Idle phase.

Note:
ADC power-on and power-off can be managed by hardware to cut the consumption when the ADC is not converting.
Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_PowerDown,: The ADC power down configuration. This parameter can be one of the following values:

  • ADC_PowerDown_Delay: ADC is powered down during delay phase.
  • ADC_PowerDown_Idle: ADC is powered down during Idle phase.
  • ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.
Note:
The ADC can be powered down:
During the hardware delay insertion (using the ADC_PowerDown_Delay parameter). => The ADC is powered up again at the end of the delay.
During the ADC is waiting for a trigger event ( using the ADC_PowerDown_Idle parameter). => The ADC is powered up at the next trigger event.
During the hardware delay insertion or the ADC is waiting for a trigger event (using the ADC_PowerDown_Idle_Delay parameter). => The ADC is powered up only at the end of the delay and at the next trigger event.
Parameters:
NewState,: new state of the ADCx power down. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 445 of file stm32l1xx_adc.c.

References ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_POWER_DOWN, and IS_FUNCTIONAL_STATE.

void ADC_RegularChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.

Parameters:
ADCx,: where x can be 1 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
  • ADC_Channel_18: ADC Channel18 selected
  • ADC_Channel_19: ADC Channel19 selected
  • ADC_Channel_20: ADC Channel20 selected
  • ADC_Channel_21: ADC Channel21 selected
  • ADC_Channel_22: ADC Channel22 selected
  • ADC_Channel_23: ADC Channel23 selected
  • ADC_Channel_24: ADC Channel24 selected
  • ADC_Channel_25: ADC Channel25 selected
  • ADC_Channel_27: ADC Channel27 selected
  • ADC_Channel_28: ADC Channel28 selected
  • ADC_Channel_29: ADC Channel29 selected
  • ADC_Channel_30: ADC Channel30 selected
  • ADC_Channel_31: ADC Channel31 selected
  • ADC_Channel_0b: ADC Channel0b selected
  • ADC_Channel_1b: ADC Channel1b selected
  • ADC_Channel_2b: ADC Channel2b selected
  • ADC_Channel_3b: ADC Channel3b selected
  • ADC_Channel_6b: ADC Channel6b selected
  • ADC_Channel_7b: ADC Channel7b selected
  • ADC_Channel_8b: ADC Channel8b selected
  • ADC_Channel_9b: ADC Channel9b selected
  • ADC_Channel_10b: ADC Channel10b selected
  • ADC_Channel_11b: ADC Channel11b selected
  • ADC_Channel_12b: ADC Channel12b selected
Rank,: The rank in the regular group sequencer. This parameter must be between 1 to 28.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
  • ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
  • ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
  • ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
  • ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
  • ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
  • ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
  • ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
Return values:
None

Definition at line 819 of file stm32l1xx_adc.c.

References ADC_Channel_19, ADC_Channel_29, ADC_Channel_9, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::SMPR0, SMPR0_SMP_SET, ADC_TypeDef::SMPR1, SMPR1_SMP_SET, ADC_TypeDef::SMPR2, SMPR2_SMP_SET, ADC_TypeDef::SMPR3, SMPR3_SMP_SET, ADC_TypeDef::SQR1, SQR1_SQ_SET, ADC_TypeDef::SQR2, SQR2_SQ_SET, ADC_TypeDef::SQR3, SQR3_SQ_SET, ADC_TypeDef::SQR4, SQR4_SQ_SET, ADC_TypeDef::SQR5, and SQR5_SQ_SET.

void ADC_SetInjectedOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel,
 |  | uint16_t | Offset
 | ) |  |

Set the injected channels conversion value offset.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
ADC_InjectedChannel,: the ADC injected channel to set its offset. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected.
  • ADC_InjectedChannel_2: Injected Channel2 selected.
  • ADC_InjectedChannel_3: Injected Channel3 selected.
  • ADC_InjectedChannel_4: Injected Channel4 selected.
Offset,: the offset value for the selected ADC injected channel This parameter must be a 12bit value.
Return values:
None

Definition at line 1440 of file stm32l1xx_adc.c.

References IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and IS_ADC_OFFSET.

void ADC_SoftwareStartConv ( ADC_TypeDef * ADCx )

Enables the selected ADC software start conversion of the regular channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
None

Definition at line 981 of file stm32l1xx_adc.c.

References ADC_CR2_SWSTART, ADC_TypeDef::CR2, and IS_ADC_ALL_PERIPH.

void ADC_SoftwareStartInjectedConv ( ADC_TypeDef * ADCx )

Enables the selected ADC software start conversion of the injected channels.

Parameters:
ADCx,: where x can be 1 to select the ADC1 peripheral.
Return values:
None

Definition at line 1531 of file stm32l1xx_adc.c.

References ADC_CR2_JSWSTART, ADC_TypeDef::CR2, and IS_ADC_ALL_PERIPH.

void ADC_StructInit ( ADC_InitTypeDef * ADC_InitStruct )

Fills each ADC_InitStruct member with its default value.

Note:
This function is used to initialize the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
Parameters:
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 280 of file stm32l1xx_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_T2_CC2, ADC_InitTypeDef::ADC_ExternalTrigConvEdge, ADC_ExternalTrigConvEdge_None, ADC_InitTypeDef::ADC_NbrOfConversion, ADC_InitTypeDef::ADC_Resolution, ADC_Resolution_12b, ADC_InitTypeDef::ADC_ScanConvMode, and DISABLE.

void ADC_TempSensorVrefintCmd ( FunctionalState NewState )

Enables or disables the temperature sensor and Vrefint channel.

Parameters:
NewState,: new state of the temperature sensor and Vref int channels. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 701 of file stm32l1xx_adc.c.

References ADC, ADC_CCR_TSVREFE, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: ADC_CommonInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_CommonInitTypeDef Struct Reference
ADC

#include <stm32l1xx_adc.h>

Data Fields

uint32_t ADC_Prescaler

Detailed Description

Definition at line 80 of file stm32l1xx_adc.h.

Field Documentation

uint32_t ADC_CommonInitTypeDef::ADC_Prescaler

Selects the ADC prescaler. This parameter can be a value of ADC_Prescaler

Definition at line 82 of file stm32l1xx_adc.h.

Referenced by ADC_CommonInit(), and ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_adc.h


STM32L1xx Standard Peripherals Firmware Library: ADC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_InitTypeDef Struct Reference
ADC

ADC Init structure definition. More...

#include <stm32l1xx_adc.h>

Data Fields

FunctionalState ADC_ContinuousConvMode
uint32_t | ADC_DataAlign
uint32_t | ADC_ExternalTrigConv
uint32_t | ADC_ExternalTrigConvEdge
uint8_t | ADC_NbrOfConversion
uint32_t | ADC_Resolution
FunctionalState ADC_ScanConvMode

Detailed Description

ADC Init structure definition.

Definition at line 51 of file stm32l1xx_adc.h.

Field Documentation

FunctionalState ADC_InitTypeDef::ADC_ContinuousConvMode

Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 60 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

uint32_t ADC_InitTypeDef::ADC_DataAlign

Specifies whether the ADC data alignment is left or right. This parameter can be a value of ADC_data_align

Definition at line 72 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

uint32_t ADC_InitTypeDef::ADC_ExternalTrigConv

Defines the external trigger used to start the analog to digital conversion of regular channels. This parameter can be a value of ADC_external_trigger_sources_for_regular_channels_conversion

Definition at line 68 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

uint32_t ADC_InitTypeDef::ADC_ExternalTrigConvEdge

Selects the external trigger Edge and enables the trigger of a regular group. This parameter can be a value of ADC_external_trigger_edge_for_regular_channels_conversion

Definition at line 64 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

uint8_t ADC_InitTypeDef::ADC_NbrOfConversion

Specifies the number of ADC conversions that will be done using the sequencer for regular channel group. This parameter must range from 1 to 27.

Definition at line 75 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

uint32_t ADC_InitTypeDef::ADC_Resolution

Selects the resolution of the conversion. This parameter can be a value of ADC_Resolution

Definition at line 53 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

FunctionalState ADC_InitTypeDef::ADC_ScanConvMode

Specifies whether the conversion is performed in Scan (multichannel) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE

Definition at line 56 of file stm32l1xx_adc.h.

Referenced by ADC_Init(), and ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_adc.h


STM32L1xx Standard Peripherals Firmware Library: AES_possible_Operation_modes

Defines

AES_possible_Operation_modes

AES_Exported_Constants

Defines

#define | AES_Operation_Decryp AES_CR_MODE_1
#define | AES_Operation_Encryp ((uint32_t)0x00000000)
#define | AES_Operation_KeyDeriv AES_CR_MODE_0
#define | AES_Operation_KeyDerivAndDecryp AES_CR_MODE
#define | IS_AES_MODE(OPERATION)

Define Documentation

#define AES_Operation_Decryp AES_CR_MODE_1

AES in Decryption mode

Definition at line 93 of file stm32l1xx_aes.h.

#define AES_Operation_Encryp ((uint32_t)0x00000000)

AES in Encryption mode

Definition at line 91 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Encrypt(), AES_CTR_Encrypt(), AES_ECB_Encrypt(), and AES_StructInit().

#define AES_Operation_KeyDeriv AES_CR_MODE_0

AES in Key Derivation mode

Definition at line 92 of file stm32l1xx_aes.h.

#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE

AES in Key Derivation and Decryption mode

Definition at line 94 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CTR_Decrypt(), and AES_ECB_Decrypt().

#define IS_AES_MODE ( OPERATION )
Value:
(((OPERATION) == AES_Operation_Encryp)    || \
                                ((OPERATION) == AES_Operation_KeyDeriv)  || \
                                ((OPERATION) == AES_Operation_Decryp)    || \
                                ((OPERATION) == AES_Operation_KeyDerivAndDecryp))

Definition at line 96 of file stm32l1xx_aes.h.

Referenced by AES_Init().


STM32L1xx Standard Peripherals Firmware Library: AES_possible_chaining_modes

Defines

AES_possible_chaining_modes

AES_Exported_Constants

Defines

#define | AES_Chaining_CBC AES_CR_CHMOD_0
#define | AES_Chaining_CTR AES_CR_CHMOD_1
#define | AES_Chaining_ECB ((uint32_t)0x00000000)
#define | IS_AES_CHAINING(CHAINING)

Define Documentation

#define AES_Chaining_CBC AES_CR_CHMOD_0

AES in CBC chaining mode

Definition at line 109 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), and AES_CBC_Encrypt().

#define AES_Chaining_CTR AES_CR_CHMOD_1

AES in CTR chaining mode

Definition at line 110 of file stm32l1xx_aes.h.

Referenced by AES_CTR_Decrypt(), and AES_CTR_Encrypt().

#define AES_Chaining_ECB ((uint32_t)0x00000000)

AES in ECB chaining mode

Definition at line 108 of file stm32l1xx_aes.h.

Referenced by AES_ECB_Decrypt(), AES_ECB_Encrypt(), and AES_StructInit().

#define IS_AES_CHAINING ( CHAINING )
Value:
(((CHAINING) == AES_Chaining_ECB) || \
                                   ((CHAINING) == AES_Chaining_CBC) || \
                                   ((CHAINING) == AES_Chaining_CTR))

Definition at line 112 of file stm32l1xx_aes.h.

Referenced by AES_Init().


STM32L1xx Standard Peripherals Firmware Library: AES_Data_Types

Defines

AES_Data_Types

AES_Exported_Constants

Defines

#define | AES_DataType_16b AES_CR_DATATYPE_0
#define | AES_DataType_1b AES_CR_DATATYPE
#define | AES_DataType_32b ((uint32_t)0x00000000)
#define | AES_DataType_8b AES_CR_DATATYPE_1
#define | IS_AES_DATATYPE(DATATYPE)

Define Documentation

#define AES_DataType_16b AES_CR_DATATYPE_0

16-bit data. Each half word is swapped

Definition at line 123 of file stm32l1xx_aes.h.

#define AES_DataType_1b AES_CR_DATATYPE

1-bit data. In the word all bits are swapped

Definition at line 125 of file stm32l1xx_aes.h.

#define AES_DataType_32b ((uint32_t)0x00000000)

32-bit data. No swapping

Definition at line 122 of file stm32l1xx_aes.h.

Referenced by AES_StructInit().

#define AES_DataType_8b AES_CR_DATATYPE_1

8-bit data. All bytes are swapped

Definition at line 124 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

#define IS_AES_DATATYPE ( DATATYPE )
Value:
(((DATATYPE) == AES_DataType_32b) || \
                                    ((DATATYPE) == AES_DataType_16b)|| \
                                    ((DATATYPE) == AES_DataType_8b) || \
                                    ((DATATYPE) == AES_DataType_1b))

Definition at line 127 of file stm32l1xx_aes.h.

Referenced by AES_Init().


STM32L1xx Standard Peripherals Firmware Library: AES_Flags

Defines

AES_Flags

AES_Exported_Constants

Defines

#define | AES_FLAG_CCF AES_SR_CCF
#define | AES_FLAG_RDERR AES_SR_RDERR
#define | AES_FLAG_WRERR AES_SR_WRERR
#define | IS_AES_FLAG(FLAG)

Define Documentation

#define AES_FLAG_CCF AES_SR_CCF

Computation Complete Flag

Definition at line 138 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_ClearFlag(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

#define AES_FLAG_RDERR AES_SR_RDERR

Read Error Flag

Definition at line 139 of file stm32l1xx_aes.h.

#define AES_FLAG_WRERR AES_SR_WRERR

Write Error Flag

Definition at line 140 of file stm32l1xx_aes.h.

#define IS_AES_FLAG ( FLAG )
Value:
(((FLAG) == AES_FLAG_CCF)    || \
                           ((FLAG) == AES_FLAG_RDERR)  || \
                           ((FLAG) == AES_FLAG_WRERR))

Definition at line 142 of file stm32l1xx_aes.h.

Referenced by AES_ClearFlag(), and AES_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: AES_Interrupts

Defines

AES_Interrupts

AES_Exported_Constants

Defines

#define | AES_IT_CC AES_CR_CCIE
#define | AES_IT_ERR AES_CR_ERRIE
#define | IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
#define | IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))

Define Documentation

#define AES_IT_CC AES_CR_CCIE

Computation Complete interrupt

Definition at line 152 of file stm32l1xx_aes.h.

Referenced by AES_GetITStatus().

#define AES_IT_ERR AES_CR_ERRIE

Error interrupt

Definition at line 153 of file stm32l1xx_aes.h.

#define IS_AES_GET_IT ( IT ) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))

Definition at line 156 of file stm32l1xx_aes.h.

Referenced by AES_GetITStatus().

#define IS_AES_IT ( IT ) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))

Definition at line 155 of file stm32l1xx_aes.h.

Referenced by AES_ClearITPendingBit(), and AES_ITConfig().


STM32L1xx Standard Peripherals Firmware Library: AES_DMA_Transfer_modes

Defines

AES_DMA_Transfer_modes

AES_Exported_Constants

Defines

#define | AES_DMATransfer_In AES_CR_DMAINEN
#define | AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN)
#define | AES_DMATransfer_Out AES_CR_DMAOUTEN
#define | IS_AES_DMA_TRANSFER(TRANSFER)

Define Documentation

#define AES_DMATransfer_In AES_CR_DMAINEN

DMA requests enabled for input transfer phase

Definition at line 165 of file stm32l1xx_aes.h.

#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN)

DMA requests enabled for both input and output phases

Definition at line 167 of file stm32l1xx_aes.h.

#define AES_DMATransfer_Out AES_CR_DMAOUTEN

DMA requests enabled for input transfer phase

Definition at line 166 of file stm32l1xx_aes.h.

#define IS_AES_DMA_TRANSFER ( TRANSFER )
Value:
(((TRANSFER) == AES_DMATransfer_In)  || \
                                         ((TRANSFER) == AES_DMATransfer_Out)  || \
                                         ((TRANSFER) == AES_DMATransfer_InOut))

Definition at line 169 of file stm32l1xx_aes.h.

Referenced by AES_DMAConfig().


STM32L1xx Standard Peripherals Firmware Library: Initialization and configuration

Functions

Initialization and configuration

AES_Private_Functions

Initialization and configuration. More...

Functions

void | AES_Cmd (FunctionalState NewState)
Enable or disable the AES peripheral.
void | AES_DeInit (void)
Deinitializes AES peripheral registers to their default reset values.
void | AES_Init (AES_InitTypeDef *AES_InitStruct)
Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

void | AES_IVInit (AES_IVInitTypeDef *AES_IVInitStruct)
Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.
void | AES_KeyInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.

Detailed Description

Initialization and configuration.

 ===============================================================================
                ##### Initialization and configuration #####
 ===============================================================================

Function Documentation

void AES_Cmd ( FunctionalState NewState )

Enable or disable the AES peripheral.

Parameters:
NewState,: new state of the AES peripheral. This parameter can be: ENABLE or DISABLE.
Note:
The key must be written while AES is disabled.
Return values:
None

< AES Enable

< AES Disable

Definition at line 196 of file stm32l1xx_aes.c.

References AES, AES_CR_EN, DISABLE, and IS_FUNCTIONAL_STATE.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_DeInit ( void )

Deinitializes AES peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 112 of file stm32l1xx_aes.c.

References DISABLE, ENABLE, RCC_AHBPeriph_AES, and RCC_AHBPeriphResetCmd().

void AES_Init ( AES_InitTypeDef * AES_InitStruct )

Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

  • AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
  • AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
    Note:
    If AES is already enabled, use AES_Cmd(DISABLE) before setting the new configuration (When AES is enabled, setting configuration is forbidden).
    Parameters:
    AES_InitStruct,: pointer to an AES_InitTypeDef structure that contains the configuration information for AES peripheral.
    Return values:
    None

Definition at line 132 of file stm32l1xx_aes.c.

References AES, AES_InitTypeDef::AES_Chaining, AES_InitTypeDef::AES_DataType, AES_InitTypeDef::AES_Operation, CR_CLEAR_MASK, IS_AES_CHAINING, IS_AES_DATATYPE, and IS_AES_MODE.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_IVInit ( AES_IVInitTypeDef * AES_IVInitStruct )

Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.

Parameters:
AES_KeyInitStruct,: pointer to an AES_IVInitTypeDef structure that contains the configuration information for the specified AES IV.
Note:
When ECB chaining mode is selected, Initialization Vector IV has no meaning. When CTR chaining mode is selected, AES_IV0 contains the CTR value. AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
Return values:
None

Definition at line 181 of file stm32l1xx_aes.c.

References AES, AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), and AES_CTR_Encrypt().

void AES_KeyInit ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitTypeDef structure that contains the configuration information for the specified AES Keys.
Note:
This function must be called while the AES is disabled.
In encryption, key derivation and key derivation + decryption modes, AES_KeyInitStruct must contain the encryption key. In decryption mode, AES_KeyInitStruct must contain the decryption key.
Return values:
None

Definition at line 162 of file stm32l1xx_aes.c.

References AES, AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().


STM32L1xx Standard Peripherals Firmware Library: Structures initialization functions

Functions

Structures initialization functions

AES_Private_Functions

Structures initialization. More...

Functions

void | AES_IVStructInit (AES_IVInitTypeDef *AES_IVInitStruct)
Fills each AES_IVInitStruct member with its default value.
void | AES_KeyStructInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Fills each AES_KeyInitStruct member with its default value.
void | AES_StructInit (AES_InitTypeDef *AES_InitStruct)
Fills each AES_InitStruct member with its default value.

Detailed Description

Structures initialization.

 ===============================================================================
              ##### Structures initialization functions #####
 ===============================================================================

Function Documentation

void AES_IVStructInit ( AES_IVInitTypeDef * AES_IVInitStruct )

Fills each AES_IVInitStruct member with its default value.

Parameters:
AES_IVInitStruct,: pointer to an AES_IVInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 262 of file stm32l1xx_aes.c.

References AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

void AES_KeyStructInit ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Fills each AES_KeyInitStruct member with its default value.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitStruct structure which will be initialized.
Return values:
None

Definition at line 248 of file stm32l1xx_aes.c.

References AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

void AES_StructInit ( AES_InitTypeDef * AES_InitStruct )

Fills each AES_InitStruct member with its default value.

Parameters:
AES_InitStruct,: pointer to an AES_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 235 of file stm32l1xx_aes.c.

References AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_InitTypeDef::AES_DataType, AES_DataType_32b, AES_InitTypeDef::AES_Operation, and AES_Operation_Encryp.


STM32L1xx Standard Peripherals Firmware Library: AES Read and Write

Functions

AES Read and Write

AES_Private_Functions

AES Read and Write. More...

Functions

void | AES_ReadIV (AES_IVInitTypeDef *AES_IVInitStruct)
Read the Initialization Vector IV value.
void | AES_ReadKey (AES_KeyInitTypeDef *AES_KeyInitStruct)
Read the Key value.
uint32_t | AES_ReadSubData (void)
Returns the data in DOUTR register processed by AES peripheral.
void | AES_WriteSubData (uint32_t Data)
Write data in DINR register to be processed by AES peripheral.

Detailed Description

AES Read and Write.

 ===============================================================================
                  ##### AES Read and Write functions #####
 ===============================================================================

Function Documentation

void AES_ReadIV ( AES_IVInitTypeDef * AES_IVInitStruct )

Read the Initialization Vector IV value.

Parameters:
AES_IVInitStruct,: pointer to an AES_IVInitTypeDef structure which will contain the Initialization Vector IV.
Note:
When the AES is enabled Reading the Initialization Vector IV value will return 0. The AES must be disabled using AES_Cmd(DISABLE) to get the right value.
When ECB chaining mode is selected, Initialization Vector IV has no meaning. When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value. AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
Return values:
None

Definition at line 345 of file stm32l1xx_aes.c.

References AES, AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

void AES_ReadKey ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Read the Key value.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitTypeDef structure which will contain the key.
Note:
When the key derivation mode is selected, AES must be disabled (AES_Cmd(DISABLE)) before reading the decryption key. Reading the key while the AES is enabled will return unpredictable value.
Return values:
None

Definition at line 324 of file stm32l1xx_aes.c.

References AES, AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

uint32_t AES_ReadSubData ( void )

Returns the data in DOUTR register processed by AES peripheral.

Note:
This function must be called four times to get the 128-bit data.
When an unexpected read of DINR register is detected, RDERR flag is set.
Return values:
The processed data.

Definition at line 308 of file stm32l1xx_aes.c.

References AES.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_WriteSubData ( uint32_t Data )

Write data in DINR register to be processed by AES peripheral.

Note:
To process 128-bit data (4 * 32-bit), this function must be called four times to write the 128-bit data in the 32-bit register DINR.
When an unexpected write to DOUTR register is detected, WRERR flag is set.
Parameters:
Data,: The data to be processed.
Return values:
None

Definition at line 295 of file stm32l1xx_aes.c.

References AES.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().


STM32L1xx Standard Peripherals Firmware Library: DMA transfers management functions

Functions

DMA transfers management functions

AES_Private_Functions

DMA transfers management function. More...

Functions

void AES_DMAConfig (uint32_t AES_DMATransfer, FunctionalState NewState)
Configures the AES DMA interface.

Detailed Description

DMA transfers management function.

 ===============================================================================
               ##### DMA transfers management functions #####
 ===============================================================================

Function Documentation

void AES_DMAConfig | ( | uint32_t | AES_DMATransfer,
 |  | FunctionalState | NewState
 | ) |  |

Configures the AES DMA interface.

Parameters:
AES_DMATransfer,: Specifies the AES DMA transfer. This parameter can be one of the following values:

  • AES_DMATransfer_In: When selected, DMA manages the data input phase.
  • AES_DMATransfer_Out: When selected, DMA manages the data output phase.
  • AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
NewState Indicates the new state of the AES DMA interface. This parameter can be: ENABLE or DISABLE.
Note:
The DMA has no action in key derivation mode.
Return values:
None

Definition at line 381 of file stm32l1xx_aes.c.

References AES, DISABLE, and IS_AES_DMA_TRANSFER.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

AES_Private_Functions

Interrupts and flags management functions. More...

Functions

void | AES_ClearFlag (uint32_t AES_FLAG)
Clears the AES flags.
void | AES_ClearITPendingBit (uint32_t AES_IT)
Clears the AES's interrupt pending bits.
FlagStatus | AES_GetFlagStatus (uint32_t AES_FLAG)
Checks whether the specified AES flag is set or not.
ITStatus | AES_GetITStatus (uint32_t AES_IT)
Checks whether the specified AES interrupt has occurred or not.
void | AES_ITConfig (uint32_t AES_IT, FunctionalState NewState)
Enables or disables the specified AES interrupt.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
           ##### Interrupts and flags management functions #####
 ===============================================================================

Function Documentation

void AES_ClearFlag ( uint32_t AES_FLAG )

Clears the AES flags.

Parameters:
AES_FLAG,: specifies the flag to clear. This parameter can be:

  • AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC bit in CR register.
  • AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in CR register.
  • AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in CR register.
Return values:
None

Definition at line 487 of file stm32l1xx_aes.c.

References AES, AES_CR_CCFC, AES_CR_ERRC, AES_FLAG_CCF, and IS_AES_FLAG.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_ClearITPendingBit ( uint32_t AES_IT )

Clears the AES's interrupt pending bits.

Parameters:
AES_IT,: specifies the interrupt pending bit to clear. This parameter can be any combinations of the following values:

  • AES_IT_CC: Computation Complete Interrupt.
  • AES_IT_ERR: Error Interrupt.
Return values:
None

Definition at line 575 of file stm32l1xx_aes.c.

References AES, and IS_AES_IT.

FlagStatus AES_GetFlagStatus ( uint32_t AES_FLAG )

Checks whether the specified AES flag is set or not.

Parameters:
AES_FLAG specifies the flag to check. This parameter can be one of the following values:

  • AES_FLAG_CCF: Computation Complete Flag is set by hardware when he computation phase is completed.
  • AES_FLAG_RDERR: Read Error Flag is set when an unexpected read operation of DOUTR register is detected.
  • AES_FLAG_WRERR: Write Error Flag is set when an unexpected write operation in DINR is detected.
Return values:
FlagStatus (SET or RESET)

Definition at line 455 of file stm32l1xx_aes.c.

References AES, IS_AES_FLAG, RESET, and SET.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

ITStatus AES_GetITStatus ( uint32_t AES_IT )

Checks whether the specified AES interrupt has occurred or not.

Parameters:
AES_IT,: Specifies the AES interrupt pending bit to check. This parameter can be:

  • AES_IT_CC: Computation Complete Interrupt.
  • AES_IT_ERR: Error Interrupt.
Return values:
ITStatus The new state of AES_IT (SET or RESET).

Definition at line 513 of file stm32l1xx_aes.c.

References AES, AES_CR_CCIE, AES_CR_ERRIE, AES_IT_CC, AES_SR_CCF, AES_SR_RDERR, AES_SR_WRERR, IS_AES_GET_IT, RESET, and SET.

void AES_ITConfig | ( | uint32_t | AES_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified AES interrupt.

Parameters:
AES_IT,: Specifies the AES interrupt source to enable/disable. This parameter can be any combinations of the following values:

  • AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF flag is set an interrupt is generated.
  • AES_IT_ERR: Error Interrupt. If enabled, once a read error flags (RDERR) or write error flag (WRERR) is set, an interrupt is generated.
NewState,: The new state of the AES interrupt source. This parameter can be: ENABLE or DISABLE.
Return values:
None

< AES_IT Enable

< AES_IT Disable

Definition at line 427 of file stm32l1xx_aes.c.

References AES, DISABLE, IS_AES_IT, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: High Level AES functions

Functions

High Level AES functions

AES_Private_Functions

High Level AES functions. More...

Functions

ErrorStatus | AES_CBC_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CBC Mode.
ErrorStatus | AES_CBC_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CBC Mode.
ErrorStatus | AES_CTR_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CTR Mode.
ErrorStatus | AES_CTR_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CTR Mode.
ErrorStatus | AES_ECB_Decrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in ECB Mode.
ErrorStatus | AES_ECB_Encrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in ECB Mode.

Detailed Description

High Level AES functions.

================================================================================
                         ##### High Level AES functions #####
================================================================================

Function Documentation

ErrorStatus AES_CBC_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in CBC Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 368 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CBC, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_CBC_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in CBC Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 268 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CBC, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_CTR_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in CTR Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 569 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CTR, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_CTR_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in CTR Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 468 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CTR, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_ECB_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in ECB Mode.

Parameters:
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 180 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_ECB_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in ECB Mode.

Parameters:
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 94 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.


STM32L1xx Standard Peripherals Firmware Library: AES

Data Structures | Modules | Defines | Functions

AES

STM32L1xx_StdPeriph_Driver

AES driver modules. More...

Data Structures

struct | AES_InitTypeDef
AES Init structure definition. More...
struct | AES_IVInitTypeDef
AES Initialization Vectors (IV) structure definition. More...
struct | AES_KeyInitTypeDef
AES Key(s) structure definition. More...

Modules

AES_Exported_Constants
AES_Private_Functions

Defines

#define | AES_CC_TIMEOUT ((uint32_t) 0x00010000)
#define | CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)

Functions

ErrorStatus | AES_CBC_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CBC Mode.
ErrorStatus | AES_CBC_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CBC Mode.
void | AES_ClearFlag (uint32_t AES_FLAG)
Clears the AES flags.
void | AES_ClearITPendingBit (uint32_t AES_IT)
Clears the AES's interrupt pending bits.
void | AES_Cmd (FunctionalState NewState)
Enable or disable the AES peripheral.
ErrorStatus | AES_CTR_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CTR Mode.
ErrorStatus | AES_CTR_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CTR Mode.
void | AES_DeInit (void)
Deinitializes AES peripheral registers to their default reset values.
void | AES_DMAConfig (uint32_t AES_DMATransfer, FunctionalState NewState)
Configures the AES DMA interface.
ErrorStatus | AES_ECB_Decrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in ECB Mode.
ErrorStatus | AES_ECB_Encrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in ECB Mode.
FlagStatus | AES_GetFlagStatus (uint32_t AES_FLAG)
Checks whether the specified AES flag is set or not.
ITStatus | AES_GetITStatus (uint32_t AES_IT)
Checks whether the specified AES interrupt has occurred or not.
void | AES_Init (AES_InitTypeDef *AES_InitStruct)
Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

void | AES_ITConfig (uint32_t AES_IT, FunctionalState NewState)
Enables or disables the specified AES interrupt.
void | AES_IVInit (AES_IVInitTypeDef *AES_IVInitStruct)
Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.
void | AES_IVStructInit (AES_IVInitTypeDef *AES_IVInitStruct)
Fills each AES_IVInitStruct member with its default value.
void | AES_KeyInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
void | AES_KeyStructInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Fills each AES_KeyInitStruct member with its default value.
void | AES_ReadIV (AES_IVInitTypeDef *AES_IVInitStruct)
Read the Initialization Vector IV value.
void | AES_ReadKey (AES_KeyInitTypeDef *AES_KeyInitStruct)
Read the Key value.
uint32_t | AES_ReadSubData (void)
Returns the data in DOUTR register processed by AES peripheral.
void | AES_StructInit (AES_InitTypeDef *AES_InitStruct)
Fills each AES_InitStruct member with its default value.
void | AES_WriteSubData (uint32_t Data)
Write data in DINR register to be processed by AES peripheral.

Detailed Description

AES driver modules.

Define Documentation

#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)

Definition at line 61 of file stm32l1xx_aes_util.c.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)

Definition at line 84 of file stm32l1xx_aes.c.

Referenced by AES_Init().

Function Documentation

ErrorStatus AES_CBC_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in CBC Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 368 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CBC, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_CBC_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in CBC Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 268 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CBC, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

void AES_ClearFlag ( uint32_t AES_FLAG )

Clears the AES flags.

Parameters:
AES_FLAG,: specifies the flag to clear. This parameter can be:

  • AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC bit in CR register.
  • AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in CR register.
  • AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in CR register.
Return values:
None

Definition at line 487 of file stm32l1xx_aes.c.

References AES, AES_CR_CCFC, AES_CR_ERRC, AES_FLAG_CCF, and IS_AES_FLAG.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_ClearITPendingBit ( uint32_t AES_IT )

Clears the AES's interrupt pending bits.

Parameters:
AES_IT,: specifies the interrupt pending bit to clear. This parameter can be any combinations of the following values:

  • AES_IT_CC: Computation Complete Interrupt.
  • AES_IT_ERR: Error Interrupt.
Return values:
None

Definition at line 575 of file stm32l1xx_aes.c.

References AES, and IS_AES_IT.

void AES_Cmd ( FunctionalState NewState )

Enable or disable the AES peripheral.

Parameters:
NewState,: new state of the AES peripheral. This parameter can be: ENABLE or DISABLE.
Note:
The key must be written while AES is disabled.
Return values:
None

< AES Enable

< AES Disable

Definition at line 196 of file stm32l1xx_aes.c.

References AES, AES_CR_EN, DISABLE, and IS_FUNCTIONAL_STATE.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

ErrorStatus AES_CTR_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in CTR Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 569 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CTR, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_CTR_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t | InitVectors[16],
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in CTR Mode.

Parameters:
InitVectors,: Initialisation Vectors used for AES algorithm.
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 468 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_CTR, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, AES_IVInitTypeDef::AES_IV3, AES_IVInit(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

void AES_DeInit ( void )

Deinitializes AES peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 112 of file stm32l1xx_aes.c.

References DISABLE, ENABLE, RCC_AHBPeriph_AES, and RCC_AHBPeriphResetCmd().

void AES_DMAConfig | ( | uint32_t | AES_DMATransfer,
 |  | FunctionalState | NewState
 | ) |  |

Configures the AES DMA interface.

Parameters:
AES_DMATransfer,: Specifies the AES DMA transfer. This parameter can be one of the following values:

  • AES_DMATransfer_In: When selected, DMA manages the data input phase.
  • AES_DMATransfer_Out: When selected, DMA manages the data output phase.
  • AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
NewState Indicates the new state of the AES DMA interface. This parameter can be: ENABLE or DISABLE.
Note:
The DMA has no action in key derivation mode.
Return values:
None

Definition at line 381 of file stm32l1xx_aes.c.

References AES, DISABLE, and IS_AES_DMA_TRANSFER.

ErrorStatus AES_ECB_Decrypt | ( | uint8_t * | Key,
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Decrypt using AES in ECB Mode.

Parameters:
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 180 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_KeyDerivAndDecryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

ErrorStatus AES_ECB_Encrypt | ( | uint8_t * | Key,
 |  | uint8_t * | Input,
 |  | uint32_t | Ilength,
 |  | uint8_t * | Output
 | ) |  |

Encrypt using AES in ECB Mode.

Parameters:
Key,: Key used for AES algorithm.
Input,: pointer to the Input buffer.
Ilength,: length of the Input buffer, must be a multiple of 16 bytes.
Output,: pointer to the returned buffer.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Operation done
  • ERROR: Operation failed

Definition at line 94 of file stm32l1xx_aes_util.c.

References AES_CC_TIMEOUT, AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_ClearFlag(), AES_Cmd(), AES_InitTypeDef::AES_DataType, AES_DataType_8b, AES_FLAG_CCF, AES_GetFlagStatus(), AES_Init(), AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, AES_KeyInitTypeDef::AES_Key3, AES_KeyInit(), AES_InitTypeDef::AES_Operation, AES_Operation_Encryp, AES_ReadSubData(), AES_WriteSubData(), DISABLE, ENABLE, ERROR, RESET, and SUCCESS.

FlagStatus AES_GetFlagStatus ( uint32_t AES_FLAG )

Checks whether the specified AES flag is set or not.

Parameters:
AES_FLAG specifies the flag to check. This parameter can be one of the following values:

  • AES_FLAG_CCF: Computation Complete Flag is set by hardware when he computation phase is completed.
  • AES_FLAG_RDERR: Read Error Flag is set when an unexpected read operation of DOUTR register is detected.
  • AES_FLAG_WRERR: Write Error Flag is set when an unexpected write operation in DINR is detected.
Return values:
FlagStatus (SET or RESET)

Definition at line 455 of file stm32l1xx_aes.c.

References AES, IS_AES_FLAG, RESET, and SET.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

ITStatus AES_GetITStatus ( uint32_t AES_IT )

Checks whether the specified AES interrupt has occurred or not.

Parameters:
AES_IT,: Specifies the AES interrupt pending bit to check. This parameter can be:

  • AES_IT_CC: Computation Complete Interrupt.
  • AES_IT_ERR: Error Interrupt.
Return values:
ITStatus The new state of AES_IT (SET or RESET).

Definition at line 513 of file stm32l1xx_aes.c.

References AES, AES_CR_CCIE, AES_CR_ERRIE, AES_IT_CC, AES_SR_CCF, AES_SR_RDERR, AES_SR_WRERR, IS_AES_GET_IT, RESET, and SET.

void AES_Init ( AES_InitTypeDef * AES_InitStruct )

Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

  • AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
  • AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
    Note:
    If AES is already enabled, use AES_Cmd(DISABLE) before setting the new configuration (When AES is enabled, setting configuration is forbidden).
    Parameters:
    AES_InitStruct,: pointer to an AES_InitTypeDef structure that contains the configuration information for AES peripheral.
    Return values:
    None

Definition at line 132 of file stm32l1xx_aes.c.

References AES, AES_InitTypeDef::AES_Chaining, AES_InitTypeDef::AES_DataType, AES_InitTypeDef::AES_Operation, CR_CLEAR_MASK, IS_AES_CHAINING, IS_AES_DATATYPE, and IS_AES_MODE.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_ITConfig | ( | uint32_t | AES_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified AES interrupt.

Parameters:
AES_IT,: Specifies the AES interrupt source to enable/disable. This parameter can be any combinations of the following values:

  • AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF flag is set an interrupt is generated.
  • AES_IT_ERR: Error Interrupt. If enabled, once a read error flags (RDERR) or write error flag (WRERR) is set, an interrupt is generated.
NewState,: The new state of the AES interrupt source. This parameter can be: ENABLE or DISABLE.
Return values:
None

< AES_IT Enable

< AES_IT Disable

Definition at line 427 of file stm32l1xx_aes.c.

References AES, DISABLE, IS_AES_IT, and IS_FUNCTIONAL_STATE.

void AES_IVInit ( AES_IVInitTypeDef * AES_IVInitStruct )

Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.

Parameters:
AES_KeyInitStruct,: pointer to an AES_IVInitTypeDef structure that contains the configuration information for the specified AES IV.
Note:
When ECB chaining mode is selected, Initialization Vector IV has no meaning. When CTR chaining mode is selected, AES_IV0 contains the CTR value. AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
Return values:
None

Definition at line 181 of file stm32l1xx_aes.c.

References AES, AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), and AES_CTR_Encrypt().

void AES_IVStructInit ( AES_IVInitTypeDef * AES_IVInitStruct )

Fills each AES_IVInitStruct member with its default value.

Parameters:
AES_IVInitStruct,: pointer to an AES_IVInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 262 of file stm32l1xx_aes.c.

References AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

void AES_KeyInit ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitTypeDef structure that contains the configuration information for the specified AES Keys.
Note:
This function must be called while the AES is disabled.
In encryption, key derivation and key derivation + decryption modes, AES_KeyInitStruct must contain the encryption key. In decryption mode, AES_KeyInitStruct must contain the decryption key.
Return values:
None

Definition at line 162 of file stm32l1xx_aes.c.

References AES, AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_KeyStructInit ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Fills each AES_KeyInitStruct member with its default value.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitStruct structure which will be initialized.
Return values:
None

Definition at line 248 of file stm32l1xx_aes.c.

References AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

void AES_ReadIV ( AES_IVInitTypeDef * AES_IVInitStruct )

Read the Initialization Vector IV value.

Parameters:
AES_IVInitStruct,: pointer to an AES_IVInitTypeDef structure which will contain the Initialization Vector IV.
Note:
When the AES is enabled Reading the Initialization Vector IV value will return 0. The AES must be disabled using AES_Cmd(DISABLE) to get the right value.
When ECB chaining mode is selected, Initialization Vector IV has no meaning. When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value. AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
Return values:
None

Definition at line 345 of file stm32l1xx_aes.c.

References AES, AES_IVInitTypeDef::AES_IV0, AES_IVInitTypeDef::AES_IV1, AES_IVInitTypeDef::AES_IV2, and AES_IVInitTypeDef::AES_IV3.

void AES_ReadKey ( AES_KeyInitTypeDef * AES_KeyInitStruct )

Read the Key value.

Parameters:
AES_KeyInitStruct,: pointer to an AES_KeyInitTypeDef structure which will contain the key.
Note:
When the key derivation mode is selected, AES must be disabled (AES_Cmd(DISABLE)) before reading the decryption key. Reading the key while the AES is enabled will return unpredictable value.
Return values:
None

Definition at line 324 of file stm32l1xx_aes.c.

References AES, AES_KeyInitTypeDef::AES_Key0, AES_KeyInitTypeDef::AES_Key1, AES_KeyInitTypeDef::AES_Key2, and AES_KeyInitTypeDef::AES_Key3.

uint32_t AES_ReadSubData ( void )

Returns the data in DOUTR register processed by AES peripheral.

Note:
This function must be called four times to get the 128-bit data.
When an unexpected read of DINR register is detected, RDERR flag is set.
Return values:
The processed data.

Definition at line 308 of file stm32l1xx_aes.c.

References AES.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().

void AES_StructInit ( AES_InitTypeDef * AES_InitStruct )

Fills each AES_InitStruct member with its default value.

Parameters:
AES_InitStruct,: pointer to an AES_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 235 of file stm32l1xx_aes.c.

References AES_InitTypeDef::AES_Chaining, AES_Chaining_ECB, AES_InitTypeDef::AES_DataType, AES_DataType_32b, AES_InitTypeDef::AES_Operation, and AES_Operation_Encryp.

void AES_WriteSubData ( uint32_t Data )

Write data in DINR register to be processed by AES peripheral.

Note:
To process 128-bit data (4 * 32-bit), this function must be called four times to write the 128-bit data in the 32-bit register DINR.
When an unexpected write to DOUTR register is detected, WRERR flag is set.
Parameters:
Data,: The data to be processed.
Return values:
None

Definition at line 295 of file stm32l1xx_aes.c.

References AES.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), and AES_ECB_Encrypt().


STM32L1xx Standard Peripherals Firmware Library: AES_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AES_InitTypeDef Struct Reference
AES

AES Init structure definition. More...

#include <stm32l1xx_aes.h>

Data Fields

uint32_t | AES_Chaining
uint32_t | AES_DataType
uint32_t | AES_Operation

Detailed Description

AES Init structure definition.

Definition at line 50 of file stm32l1xx_aes.h.

Field Documentation

uint32_t AES_InitTypeDef::AES_Chaining

Specifies the AES Chaining modes: ECB, CBC or CTR. This parameter can be a value of AES_possible_chaining_modes

Definition at line 54 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_Init(), and AES_StructInit().

uint32_t AES_InitTypeDef::AES_DataType

Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit. This parameter can be a value of AES_Data_Types

Definition at line 56 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_Init(), and AES_StructInit().

uint32_t AES_InitTypeDef::AES_Operation

Specifies the AES mode of operation. This parameter can be a value of AES_possible_Operation_modes

Definition at line 52 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_Init(), and AES_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_aes.h


STM32L1xx Standard Peripherals Firmware Library: AES_IVInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AES_IVInitTypeDef Struct Reference
AES

AES Initialization Vectors (IV) structure definition. More...

#include <stm32l1xx_aes.h>

Data Fields

uint32_t | AES_IV0
uint32_t | AES_IV1
uint32_t | AES_IV2
uint32_t | AES_IV3

Detailed Description

AES Initialization Vectors (IV) structure definition.

Definition at line 74 of file stm32l1xx_aes.h.

Field Documentation

uint32_t AES_IVInitTypeDef::AES_IV0

Init Vector IV[31:0]

Definition at line 76 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_IVInit(), AES_IVStructInit(), and AES_ReadIV().

uint32_t AES_IVInitTypeDef::AES_IV1

Init Vector IV[63:32]

Definition at line 77 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_IVInit(), AES_IVStructInit(), and AES_ReadIV().

uint32_t AES_IVInitTypeDef::AES_IV2

Init Vector IV[95:64]

Definition at line 78 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_IVInit(), AES_IVStructInit(), and AES_ReadIV().

uint32_t AES_IVInitTypeDef::AES_IV3

Init Vector IV[127:96]

Definition at line 79 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_IVInit(), AES_IVStructInit(), and AES_ReadIV().

The documentation for this struct was generated from the following file:
  • stm32l1xx_aes.h


STM32L1xx Standard Peripherals Firmware Library: AES_KeyInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AES_KeyInitTypeDef Struct Reference
AES

AES Key(s) structure definition. More...

#include <stm32l1xx_aes.h>

Data Fields

uint32_t | AES_Key0
uint32_t | AES_Key1
uint32_t | AES_Key2
uint32_t | AES_Key3

Detailed Description

AES Key(s) structure definition.

Definition at line 63 of file stm32l1xx_aes.h.

Field Documentation

uint32_t AES_KeyInitTypeDef::AES_Key0

Key[31:0]

Definition at line 65 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_KeyInit(), AES_KeyStructInit(), and AES_ReadKey().

uint32_t AES_KeyInitTypeDef::AES_Key1

Key[63:32]

Definition at line 66 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_KeyInit(), AES_KeyStructInit(), and AES_ReadKey().

uint32_t AES_KeyInitTypeDef::AES_Key2

Key[95:64]

Definition at line 67 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_KeyInit(), AES_KeyStructInit(), and AES_ReadKey().

uint32_t AES_KeyInitTypeDef::AES_Key3

Key[127:96]

Definition at line 68 of file stm32l1xx_aes.h.

Referenced by AES_CBC_Decrypt(), AES_CBC_Encrypt(), AES_CTR_Decrypt(), AES_CTR_Encrypt(), AES_ECB_Decrypt(), AES_ECB_Encrypt(), AES_KeyInit(), AES_KeyStructInit(), and AES_ReadKey().

The documentation for this struct was generated from the following file:
  • stm32l1xx_aes.h


STM32L1xx Standard Peripherals Firmware Library: COMP_Selection

Defines

COMP_Selection

COMP_Exported_Constants

Defines

#define | COMP_Selection_COMP1 ((uint32_t)0x00000001)
#define | COMP_Selection_COMP2 ((uint32_t)0x00000002)
#define | IS_COMP_ALL_PERIPH(PERIPH)

Define Documentation

#define COMP_Selection_COMP1 ((uint32_t)0x00000001)

Definition at line 75 of file stm32l1xx_comp.h.

Referenced by COMP_GetOutputLevel().

#define COMP_Selection_COMP2 ((uint32_t)0x00000002)

Definition at line 76 of file stm32l1xx_comp.h.

#define IS_COMP_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == COMP_Selection_COMP1) || \
                                    ((PERIPH) == COMP_Selection_COMP2))

Definition at line 78 of file stm32l1xx_comp.h.

Referenced by COMP_GetOutputLevel().


STM32L1xx Standard Peripherals Firmware Library: COMP_InvertingInput

Defines

COMP_InvertingInput

COMP_Exported_Constants

Defines

#define | COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
#define | COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
#define | COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
#define | COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
#define | COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
#define | COMP_InvertingInput_IO ((uint32_t)0x00040000)
#define | COMP_InvertingInput_None ((uint32_t)0x00000000)
#define | COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
#define | IS_COMP_INVERTING_INPUT(INPUT)

Define Documentation

#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)

Definition at line 93 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)

Definition at line 94 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)

Definition at line 92 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)

Definition at line 95 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)

Definition at line 96 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_IO ((uint32_t)0x00040000)

Definition at line 90 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_None ((uint32_t)0x00000000)

Definition at line 89 of file stm32l1xx_comp.h.

#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)

Definition at line 91 of file stm32l1xx_comp.h.

#define IS_COMP_INVERTING_INPUT ( INPUT )
Value:
(((INPUT) == COMP_InvertingInput_None) || \
                                        ((INPUT) == COMP_InvertingInput_IO) || \
                                        ((INPUT) == COMP_InvertingInput_VREFINT) || \
                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
                                        ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
                                        ((INPUT) == COMP_InvertingInput_DAC1) || \
                                        ((INPUT) == COMP_InvertingInput_DAC2))

Definition at line 98 of file stm32l1xx_comp.h.

Referenced by COMP_Init().


STM32L1xx Standard Peripherals Firmware Library: COMP_OutputSelect

Defines

COMP_OutputSelect

COMP_Exported_Constants

Defines

#define | COMP_OutputSelect_None ((uint32_t)0x00E00000)
#define | COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
#define | COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
#define | COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
#define | COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
#define | COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
#define | COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
#define | COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
#define | IS_COMP_OUTPUT(OUTPUT)

Define Documentation

#define COMP_OutputSelect_None ((uint32_t)0x00E00000)

Definition at line 121 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)

Definition at line 120 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)

Definition at line 114 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)

Definition at line 115 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)

Definition at line 116 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)

Definition at line 117 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)

Definition at line 118 of file stm32l1xx_comp.h.

#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)

Definition at line 119 of file stm32l1xx_comp.h.

#define IS_COMP_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
                                ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
                                ((OUTPUT) == COMP_OutputSelect_None))

Definition at line 123 of file stm32l1xx_comp.h.

Referenced by COMP_Init().


STM32L1xx Standard Peripherals Firmware Library: COMP_Speed

Defines

COMP_Speed

COMP_Exported_Constants

Defines

#define | COMP_Speed_Fast ((uint32_t)0x00001000)
#define | COMP_Speed_Slow ((uint32_t)0x00000000)
#define | IS_COMP_SPEED(SPEED)

Define Documentation

#define COMP_Speed_Fast ((uint32_t)0x00001000)

Definition at line 140 of file stm32l1xx_comp.h.

#define COMP_Speed_Slow ((uint32_t)0x00000000)

Definition at line 139 of file stm32l1xx_comp.h.

#define IS_COMP_SPEED ( SPEED )
Value:
(((SPEED) == COMP_Speed_Slow) || \
                                 ((SPEED) == COMP_Speed_Fast))

Definition at line 142 of file stm32l1xx_comp.h.

Referenced by COMP_Init().


STM32L1xx Standard Peripherals Firmware Library: COMP_Exported_Constants

Modules | Defines

COMP_Exported_Constants

COMP

Modules

COMP_Selection
COMP_InvertingInput
COMP_OutputSelect
COMP_Speed

Defines

#define | COMP_OutputLevel_High ((uint32_t)0x00000001)
#define | COMP_OutputLevel_Low ((uint32_t)0x00000000)

Define Documentation

#define COMP_OutputLevel_High ((uint32_t)0x00000001)

Definition at line 68 of file stm32l1xx_comp.h.

Referenced by COMP_GetOutputLevel().

#define COMP_OutputLevel_Low ((uint32_t)0x00000000)

Definition at line 69 of file stm32l1xx_comp.h.

Referenced by COMP_GetOutputLevel().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

COMP_Private_Functions

Initialization and Configuration functions. More...

Functions

void | COMP_Cmd (FunctionalState NewState)
Enable or disable the COMP1 peripheral.
void | COMP_DeInit (void)
Deinitializes COMP peripheral registers to their default reset values.
uint8_t | COMP_GetOutputLevel (uint32_t COMP_Selection)
Return the output level (high or low) of the selected comparator.
void | COMP_Init (COMP_InitTypeDef *COMP_InitStruct)
Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.
void | COMP_SW1SwitchConfig (FunctionalState NewState)
Close or Open the SW1 switch.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and Configuration functions #####
 ===============================================================================

Function Documentation

void COMP_Cmd ( FunctionalState NewState )

Enable or disable the COMP1 peripheral.

Note:
After enabling COMP1, the following functions should be called to connect the selected GPIO input to COMP1 non inverting input:
Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
Close the I/O switch number n corresponding to the I/O using SYSCFG_RIIOSwitchConfig()
Parameters:
NewState,: new state of the COMP1 peripheral. This parameter can be: ENABLE or DISABLE.
Note:
This function enables/disables only the COMP1.
Return values:
None

Definition at line 169 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_CMP1EN, DISABLE, and IS_FUNCTIONAL_STATE.

void COMP_DeInit ( void )

Deinitializes COMP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

< Set COMP->CSR to reset value

Definition at line 113 of file stm32l1xx_comp.c.

References COMP.

uint8_t COMP_GetOutputLevel ( uint32_t COMP_Selection )

Return the output level (high or low) of the selected comparator.

Note:
Comparator output is low when the noninverting input is at a lower voltage than the inverting input.
Comparator output is high when the noninverting input is at a higher voltage than the inverting input.
Comparators outputs aren't available on GPIO (outputs levels are only internal). The COMP1 and COMP2 outputs are connected internally to the EXTI Line 21 and Line 22 respectively.
Parameters:
COMP_Selection,: the selected comparator. This parameter can be one of the following values:

  • COMP_Selection_COMP1: COMP1 selected
  • COMP_Selection_COMP2: COMP2 selected
Return values:
Returns the selected comparator output level.

Definition at line 201 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_CMP1OUT, COMP_CSR_CMP2OUT, COMP_OutputLevel_High, COMP_OutputLevel_Low, COMP_Selection_COMP1, IS_COMP_ALL_PERIPH, and RESET.

void COMP_Init ( COMP_InitTypeDef * COMP_InitStruct )

Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.

Note:
This function configures only COMP2.
COMP2 comparator is enabled as soon as the INSEL[2:0] bits are different from "000".
Parameters:
COMP_InitStruct,: pointer to an COMP_InitTypeDef structure that contains the configuration information for the specified COMP peripheral.
Return values:
None

< Get the COMP CSR value

< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits

< Configure COMP: speed, inversion input selection and output redirection

< Set SPEED bit according to COMP_InitStruct->COMP_Speed value

< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value

< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value

< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are different from "000"

< Write to COMP_CSR register

Definition at line 128 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_INSEL, COMP_CSR_OUTSEL, COMP_CSR_SPEED, COMP_InitTypeDef::COMP_InvertingInput, COMP_InitTypeDef::COMP_OutputSelect, COMP_InitTypeDef::COMP_Speed, IS_COMP_INVERTING_INPUT, IS_COMP_OUTPUT, and IS_COMP_SPEED.

void COMP_SW1SwitchConfig ( FunctionalState NewState )

Close or Open the SW1 switch.

Parameters:
NewState,: new state of the SW1 switch. This parameter can be: ENABLE or DISABLE.
Note:
ENABLE to close the SW1 switch
DISABLE to open the SW1 switch
Return values:
None.

Definition at line 252 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_SW1, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Window mode control function

Functions

Window mode control function

COMP_Private_Functions

Window mode control function. More...

Functions

void COMP_WindowCmd (FunctionalState NewState)
Enables or disables the window mode.

Detailed Description

Window mode control function.

 ===============================================================================
                  ##### Window mode control function #####
 ===============================================================================

Function Documentation

void COMP_WindowCmd ( FunctionalState NewState )

Enables or disables the window mode.

In window mode:

Note:
COMP1 inverting input is fixed to VREFINT defining the first threshold.
COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT sub-multiples, PB3) defining the second threshold.
COMP1 and COMP2 non inverting inputs are connected together.
In window mode, only the Group 6 (PB4 or PB5) can be used as noninverting inputs.
Parameters:
NewState,: new state of the window mode. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 299 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_WNDWE, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Internal Reference Voltage output function

Functions

Internal Reference Voltage output function

COMP_Private_Functions

Internal Reference Voltage (VREFINT) output function. More...

Functions

void COMP_VrefintOutputCmd (FunctionalState NewState)
Enables or disables the output of internal reference voltage (VREFINT).

Detailed Description

Internal Reference Voltage (VREFINT) output function.

 ===============================================================================
      ##### Internal Reference Voltage (VREFINT) output function #####
 ===============================================================================

Function Documentation

void COMP_VrefintOutputCmd ( FunctionalState NewState )

Enables or disables the output of internal reference voltage (VREFINT).

The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or CH9 (PB1). To correctly use this function, the SYSCFG_RIIOSwitchConfig() function should be called after.

Parameters:
NewState,: new state of the Vrefint output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 342 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_VREFOUTEN, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: COMP

Data Structures | Modules | Functions

COMP

STM32L1xx_StdPeriph_Driver

COMP driver modules. More...

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...

Modules

COMP_Exported_Constants
COMP_Private_Functions

Functions

void | COMP_Cmd (FunctionalState NewState)
Enable or disable the COMP1 peripheral.
void | COMP_DeInit (void)
Deinitializes COMP peripheral registers to their default reset values.
uint8_t | COMP_GetOutputLevel (uint32_t COMP_Selection)
Return the output level (high or low) of the selected comparator.
void | COMP_Init (COMP_InitTypeDef *COMP_InitStruct)
Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.
void | COMP_SW1SwitchConfig (FunctionalState NewState)
Close or Open the SW1 switch.
void | COMP_VrefintOutputCmd (FunctionalState NewState)
Enables or disables the output of internal reference voltage (VREFINT).
void | COMP_WindowCmd (FunctionalState NewState)
Enables or disables the window mode.

Detailed Description

COMP driver modules.

Function Documentation

void COMP_Cmd ( FunctionalState NewState )

Enable or disable the COMP1 peripheral.

Note:
After enabling COMP1, the following functions should be called to connect the selected GPIO input to COMP1 non inverting input:
Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
Close the I/O switch number n corresponding to the I/O using SYSCFG_RIIOSwitchConfig()
Parameters:
NewState,: new state of the COMP1 peripheral. This parameter can be: ENABLE or DISABLE.
Note:
This function enables/disables only the COMP1.
Return values:
None

Definition at line 169 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_CMP1EN, DISABLE, and IS_FUNCTIONAL_STATE.

void COMP_DeInit ( void )

Deinitializes COMP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

< Set COMP->CSR to reset value

Definition at line 113 of file stm32l1xx_comp.c.

References COMP.

uint8_t COMP_GetOutputLevel ( uint32_t COMP_Selection )

Return the output level (high or low) of the selected comparator.

Note:
Comparator output is low when the noninverting input is at a lower voltage than the inverting input.
Comparator output is high when the noninverting input is at a higher voltage than the inverting input.
Comparators outputs aren't available on GPIO (outputs levels are only internal). The COMP1 and COMP2 outputs are connected internally to the EXTI Line 21 and Line 22 respectively.
Parameters:
COMP_Selection,: the selected comparator. This parameter can be one of the following values:

  • COMP_Selection_COMP1: COMP1 selected
  • COMP_Selection_COMP2: COMP2 selected
Return values:
Returns the selected comparator output level.

Definition at line 201 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_CMP1OUT, COMP_CSR_CMP2OUT, COMP_OutputLevel_High, COMP_OutputLevel_Low, COMP_Selection_COMP1, IS_COMP_ALL_PERIPH, and RESET.

void COMP_Init ( COMP_InitTypeDef * COMP_InitStruct )

Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.

Note:
This function configures only COMP2.
COMP2 comparator is enabled as soon as the INSEL[2:0] bits are different from "000".
Parameters:
COMP_InitStruct,: pointer to an COMP_InitTypeDef structure that contains the configuration information for the specified COMP peripheral.
Return values:
None

< Get the COMP CSR value

< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits

< Configure COMP: speed, inversion input selection and output redirection

< Set SPEED bit according to COMP_InitStruct->COMP_Speed value

< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value

< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value

< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are different from "000"

< Write to COMP_CSR register

Definition at line 128 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_INSEL, COMP_CSR_OUTSEL, COMP_CSR_SPEED, COMP_InitTypeDef::COMP_InvertingInput, COMP_InitTypeDef::COMP_OutputSelect, COMP_InitTypeDef::COMP_Speed, IS_COMP_INVERTING_INPUT, IS_COMP_OUTPUT, and IS_COMP_SPEED.

void COMP_SW1SwitchConfig ( FunctionalState NewState )

Close or Open the SW1 switch.

Parameters:
NewState,: new state of the SW1 switch. This parameter can be: ENABLE or DISABLE.
Note:
ENABLE to close the SW1 switch
DISABLE to open the SW1 switch
Return values:
None.

Definition at line 252 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_SW1, DISABLE, and IS_FUNCTIONAL_STATE.

void COMP_VrefintOutputCmd ( FunctionalState NewState )

Enables or disables the output of internal reference voltage (VREFINT).

The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or CH9 (PB1). To correctly use this function, the SYSCFG_RIIOSwitchConfig() function should be called after.

Parameters:
NewState,: new state of the Vrefint output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 342 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_VREFOUTEN, DISABLE, and IS_FUNCTIONAL_STATE.

void COMP_WindowCmd ( FunctionalState NewState )

Enables or disables the window mode.

In window mode:

Note:
COMP1 inverting input is fixed to VREFINT defining the first threshold.
COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT sub-multiples, PB3) defining the second threshold.
COMP1 and COMP2 non inverting inputs are connected together.
In window mode, only the Group 6 (PB4 or PB5) can be used as noninverting inputs.
Parameters:
NewState,: new state of the window mode. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 299 of file stm32l1xx_comp.c.

References COMP, COMP_CSR_WNDWE, DISABLE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: COMP_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

COMP_InitTypeDef Struct Reference
COMP

COMP Init structure definition. More...

#include <stm32l1xx_comp.h>

Data Fields

uint32_t | COMP_InvertingInput
uint32_t | COMP_OutputSelect
uint32_t | COMP_Speed

Detailed Description

COMP Init structure definition.

Definition at line 51 of file stm32l1xx_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::COMP_InvertingInput

Selects the inverting input of the comparator 2. This parameter can be a value of COMP_InvertingInput

Definition at line 55 of file stm32l1xx_comp.h.

Referenced by COMP_Init().

uint32_t COMP_InitTypeDef::COMP_OutputSelect

Selects the output redirection of the comparator 2. This parameter can be a value of COMP_OutputSelect

Definition at line 57 of file stm32l1xx_comp.h.

Referenced by COMP_Init().

uint32_t COMP_InitTypeDef::COMP_Speed

Defines the speed of comparator 2. This parameter can be a value of COMP_Speed

Definition at line 53 of file stm32l1xx_comp.h.

Referenced by COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32l1xx_comp.h


STM32L1xx Standard Peripherals Firmware Library: CRC_Exported_Constants

CRC_Exported_Constants

CRC


STM32L1xx Standard Peripherals Firmware Library: CRC_Private_Functions

Functions

CRC_Private_Functions

CRC

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Function Documentation

uint32_t CRC_CalcBlockCRC | ( | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of a given buffer of data word(32-bit).

Parameters:
pBuffer,: pointer to the buffer containing the data to be computed.
BufferLength,: length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 77 of file stm32l1xx_crc.c.

References CRC.

uint32_t CRC_CalcCRC ( uint32_t Data )

Computes the 32-bit CRC of a given data word(32-bit).

Parameters:
Data,: data word(32-bit) to compute its CRC.
Return values:
32-bit CRC

Definition at line 64 of file stm32l1xx_crc.c.

References CRC.

uint32_t CRC_GetCRC ( void )

Returns the current CRC value.

Parameters:
None
Return values:
32-bit CRC

Definition at line 93 of file stm32l1xx_crc.c.

References CRC.

uint8_t CRC_GetIDRegister ( void )

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
None
Return values:
8-bit value of the ID register

Definition at line 113 of file stm32l1xx_crc.c.

References CRC.

void CRC_ResetDR ( void )

Resets the CRC Data register (DR).

Parameters:
None
Return values:
None

Definition at line 53 of file stm32l1xx_crc.c.

References CRC, and CRC_CR_RESET.

void CRC_SetIDRegister ( uint8_t IDValue )

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
IDValue,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 103 of file stm32l1xx_crc.c.

References CRC.


STM32L1xx Standard Peripherals Firmware Library: CRC

Modules | Functions

CRC

STM32L1xx_StdPeriph_Driver

CRC driver modules. More...

Modules

CRC_Exported_Constants
CRC_Private_Functions

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Detailed Description

CRC driver modules.

Function Documentation

uint32_t CRC_CalcBlockCRC | ( | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of a given buffer of data word(32-bit).

Parameters:
pBuffer,: pointer to the buffer containing the data to be computed.
BufferLength,: length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 77 of file stm32l1xx_crc.c.

References CRC.

uint32_t CRC_CalcCRC ( uint32_t Data )

Computes the 32-bit CRC of a given data word(32-bit).

Parameters:
Data,: data word(32-bit) to compute its CRC.
Return values:
32-bit CRC

Definition at line 64 of file stm32l1xx_crc.c.

References CRC.

uint32_t CRC_GetCRC ( void )

Returns the current CRC value.

Parameters:
None
Return values:
32-bit CRC

Definition at line 93 of file stm32l1xx_crc.c.

References CRC.

uint8_t CRC_GetIDRegister ( void )

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
None
Return values:
8-bit value of the ID register

Definition at line 113 of file stm32l1xx_crc.c.

References CRC.

void CRC_ResetDR ( void )

Resets the CRC Data register (DR).

Parameters:
None
Return values:
None

Definition at line 53 of file stm32l1xx_crc.c.

References CRC, and CRC_CR_RESET.

void CRC_SetIDRegister ( uint8_t IDValue )

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
IDValue,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 103 of file stm32l1xx_crc.c.

References CRC.


STM32L1xx Standard Peripherals Firmware Library: DAC_trigger_selection

Defines

DAC_trigger_selection

DAC_Exported_Constants

Defines

#define | DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
#define | DAC_Trigger_None ((uint32_t)0x00000000)
#define | DAC_Trigger_Software ((uint32_t)0x0000003C)
#define | DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
#define | DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
#define | DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
#define | DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
#define | DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C)
#define | IS_DAC_TRIGGER(TRIGGER)

Define Documentation

#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 85 of file stm32l1xx_dac.h.

#define DAC_Trigger_None ((uint32_t)0x00000000)

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

Definition at line 78 of file stm32l1xx_dac.h.

Referenced by DAC_StructInit().

#define DAC_Trigger_Software ((uint32_t)0x0000003C)

Conversion started by software trigger for DAC channel

Definition at line 86 of file stm32l1xx_dac.h.

#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 83 of file stm32l1xx_dac.h.

#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 84 of file stm32l1xx_dac.h.

#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 80 of file stm32l1xx_dac.h.

#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 81 of file stm32l1xx_dac.h.

#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C)

TIM9 TRGO selected as external conversion trigger for DAC channel

Definition at line 82 of file stm32l1xx_dac.h.

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_Trigger_None) || \
                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T9_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
                                 ((TRIGGER) == DAC_Trigger_Software))

Definition at line 88 of file stm32l1xx_dac.h.

Referenced by DAC_Init().


STM32L1xx Standard Peripherals Firmware Library: DAC_wave_generation

Defines

DAC_wave_generation

DAC_Exported_Constants

Defines

#define | DAC_Wave_Noise ((uint32_t)0x00000040)
#define | DAC_Wave_Triangle ((uint32_t)0x00000080)
#define | DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define | DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define | DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define | IS_DAC_GENERATE_WAVE(WAVE)
#define | IS_DAC_WAVE(WAVE)

Define Documentation

#define DAC_Wave_Noise ((uint32_t)0x00000040)

Definition at line 214 of file stm32l1xx_dac.h.

#define DAC_Wave_Triangle ((uint32_t)0x00000080)

Definition at line 215 of file stm32l1xx_dac.h.

#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)

Definition at line 106 of file stm32l1xx_dac.h.

#define DAC_WaveGeneration_None ((uint32_t)0x00000000)

Definition at line 105 of file stm32l1xx_dac.h.

Referenced by DAC_StructInit().

#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)

Definition at line 107 of file stm32l1xx_dac.h.

#define IS_DAC_GENERATE_WAVE ( WAVE )
Value:
(((WAVE) == DAC_WaveGeneration_None) || \
                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
                                    ((WAVE) == DAC_WaveGeneration_Triangle))

Definition at line 108 of file stm32l1xx_dac.h.

Referenced by DAC_Init().

#define IS_DAC_WAVE ( WAVE )
Value:
(((WAVE) == DAC_Wave_Noise) || \
                           ((WAVE) == DAC_Wave_Triangle))

Definition at line 216 of file stm32l1xx_dac.h.

Referenced by DAC_WaveGenerationCmd().


STM32L1xx Standard Peripherals Firmware Library: DAC_lfsrunmask_triangleamplitude

Defines

DAC_lfsrunmask_triangleamplitude

DAC_Exported_Constants

Defines

#define | DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
#define | DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
#define | DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
#define | DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
#define | DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
#define | DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
#define | DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
#define | DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
#define | DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
#define | DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
#define | DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
#define | DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
#define | DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
#define | DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
#define | DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
#define | DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
#define | DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
#define | DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
#define | DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
#define | DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
#define | DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 119 of file stm32l1xx_dac.h.

Referenced by DAC_StructInit().

#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 129 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 130 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 120 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 121 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 122 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 123 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 124 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 125 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 126 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 127 of file stm32l1xx_dac.h.

#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 128 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)

Select max triangle amplitude of 1

Definition at line 131 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)

Select max triangle amplitude of 1023

Definition at line 140 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)

Select max triangle amplitude of 127

Definition at line 137 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)

Select max triangle amplitude of 15

Definition at line 134 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)

Select max triangle amplitude of 2047

Definition at line 141 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)

Select max triangle amplitude of 255

Definition at line 138 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)

Select max triangle amplitude of 3

Definition at line 132 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)

Select max triangle amplitude of 31

Definition at line 135 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)

Select max triangle amplitude of 4095

Definition at line 142 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)

Select max triangle amplitude of 511

Definition at line 139 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)

Select max triangle amplitude of 63

Definition at line 136 of file stm32l1xx_dac.h.

#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)

Select max triangle amplitude of 7

Definition at line 133 of file stm32l1xx_dac.h.

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUnmask_Bit0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_4095))

Definition at line 144 of file stm32l1xx_dac.h.

Referenced by DAC_Init().


STM32L1xx Standard Peripherals Firmware Library: DAC_output_buffer

Defines

DAC_output_buffer

DAC_Exported_Constants

Defines

#define | DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define | DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)

Define Documentation

#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)

Definition at line 177 of file stm32l1xx_dac.h.

#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)

Definition at line 176 of file stm32l1xx_dac.h.

Referenced by DAC_StructInit().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OutputBuffer_Enable) || \
                                           ((STATE) == DAC_OutputBuffer_Disable))

Definition at line 178 of file stm32l1xx_dac.h.

Referenced by DAC_Init().


STM32L1xx Standard Peripherals Firmware Library: DAC_Channel_selection

Defines

DAC_Channel_selection

DAC_Exported_Constants

Defines

#define | DAC_Channel_1 ((uint32_t)0x00000000)
#define | DAC_Channel_2 ((uint32_t)0x00000010)
#define | IS_DAC_CHANNEL(CHANNEL)

Define Documentation

#define DAC_Channel_1 ((uint32_t)0x00000000)

Definition at line 188 of file stm32l1xx_dac.h.

#define DAC_Channel_2 ((uint32_t)0x00000010)

Definition at line 189 of file stm32l1xx_dac.h.

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_Channel_1) || \
                                 ((CHANNEL) == DAC_Channel_2))

Definition at line 190 of file stm32l1xx_dac.h.

Referenced by DAC_ClearFlag(), DAC_ClearITPendingBit(), DAC_Cmd(), DAC_DMACmd(), DAC_GetDataOutputValue(), DAC_GetFlagStatus(), DAC_GetITStatus(), DAC_Init(), DAC_ITConfig(), DAC_SoftwareTriggerCmd(), and DAC_WaveGenerationCmd().


STM32L1xx Standard Peripherals Firmware Library: DAC_data_alignment

Defines

DAC_data_alignment

DAC_Exported_Constants

Defines

#define | DAC_Align_12b_L ((uint32_t)0x00000004)
#define | DAC_Align_12b_R ((uint32_t)0x00000000)
#define | DAC_Align_8b_R ((uint32_t)0x00000008)
#define | IS_DAC_ALIGN(ALIGN)

Define Documentation

#define DAC_Align_12b_L ((uint32_t)0x00000004)

Definition at line 201 of file stm32l1xx_dac.h.

#define DAC_Align_12b_R ((uint32_t)0x00000000)

Definition at line 200 of file stm32l1xx_dac.h.

#define DAC_Align_8b_R ((uint32_t)0x00000008)

Definition at line 202 of file stm32l1xx_dac.h.

Referenced by DAC_SetDualChannelData().

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_Align_12b_R) || \
                             ((ALIGN) == DAC_Align_12b_L) || \
                             ((ALIGN) == DAC_Align_8b_R))

Definition at line 203 of file stm32l1xx_dac.h.

Referenced by DAC_SetChannel1Data(), DAC_SetChannel2Data(), and DAC_SetDualChannelData().


STM32L1xx Standard Peripherals Firmware Library: DAC_data

Defines

DAC_data

DAC_Exported_Constants

Defines

#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)

Define Documentation

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0)

Definition at line 226 of file stm32l1xx_dac.h.

Referenced by DAC_SetChannel1Data(), DAC_SetChannel2Data(), and DAC_SetDualChannelData().


STM32L1xx Standard Peripherals Firmware Library: DAC_interrupts_definition

Defines

DAC_interrupts_definition

DAC_Exported_Constants

Defines

#define | DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define | IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))

Define Documentation

#define DAC_IT_DMAUDR ((uint32_t)0x00002000)

Definition at line 236 of file stm32l1xx_dac.h.

#define IS_DAC_IT ( IT ) (((IT) == DAC_IT_DMAUDR))

Definition at line 237 of file stm32l1xx_dac.h.

Referenced by DAC_ClearITPendingBit(), DAC_GetITStatus(), and DAC_ITConfig().


STM32L1xx Standard Peripherals Firmware Library: DAC_flags_definition

Defines

DAC_flags_definition

DAC_Exported_Constants

Defines

#define | DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define | IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))

Define Documentation

#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)

Definition at line 248 of file stm32l1xx_dac.h.

#define IS_DAC_FLAG ( FLAG ) (((FLAG) == DAC_FLAG_DMAUDR))

Definition at line 250 of file stm32l1xx_dac.h.

Referenced by DAC_ClearFlag(), and DAC_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: DAC channels configuration

Functions

DAC channels configuration

DAC_Private_Functions

DAC channels configuration: trigger, output buffer, data format. More...

Functions

void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

DAC channels configuration: trigger, output buffer, data format.

 ===============================================================================
  ##### DAC channels configuration: trigger, output buffer, data format #####
 ===============================================================================

Function Documentation

void DAC_Cmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel.

Parameters:
DAC_Channel,: The selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the DAC channel. This parameter can be: ENABLE or DISABLE.
Note:
When the DAC channel is enabled the trigger source can no more be modified.
Return values:
None

Definition at line 236 of file stm32l1xx_dac.c.

References DAC, DAC_CR_EN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

void DAC_DeInit ( void )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 156 of file stm32l1xx_dac.c.

References DISABLE, ENABLE, RCC_APB1Periph_DAC, and RCC_APB1PeriphResetCmd().

void DAC_DualSoftwareTriggerCmd ( FunctionalState NewState )

Enables or disables simultaneously the two DAC channels software triggers.

Parameters:
NewState,: new state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 289 of file stm32l1xx_dac.c.

References DAC, DISABLE, DUAL_SWTRIG_RESET, DUAL_SWTRIG_SET, and IS_FUNCTIONAL_STATE.

uint16_t DAC_GetDataOutputValue ( uint32_t DAC_Channel )

Returns the last data output value of the selected DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 439 of file stm32l1xx_dac.c.

References DAC_BASE, DOR_OFFSET, and IS_DAC_CHANNEL.

void DAC_Init | ( | uint32_t | DAC_Channel,
 |  | DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected.
  • DAC_Channel_2: DAC Channel2 selected.
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
Return values:
None

Definition at line 175 of file stm32l1xx_dac.c.

References CR_CLEAR_MASK, DAC, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_InitTypeDef::DAC_Trigger, DAC_InitTypeDef::DAC_WaveGeneration, IS_DAC_CHANNEL, IS_DAC_GENERATE_WAVE, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, IS_DAC_OUTPUT_BUFFER_STATE, and IS_DAC_TRIGGER.

void DAC_SetChannel1Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel1.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel1. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 350 of file stm32l1xx_dac.c.

References DAC_BASE, DHR12R1_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetChannel2Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel2.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel2. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 375 of file stm32l1xx_dac.c.

References DAC_BASE, DHR12R2_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetDualChannelData | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data2,
 |  | uint16_t | Data1
 | ) |  |

Set the specified data holding register value for dual channel DAC.

Parameters:
DAC_Align,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
None

Definition at line 405 of file stm32l1xx_dac.c.

References DAC_Align_8b_R, DAC_BASE, DHR12RD_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SoftwareTriggerCmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel software trigger.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 264 of file stm32l1xx_dac.c.

References DAC, DAC_SWTRIGR_SWTRIG1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

void DAC_StructInit ( DAC_InitTypeDef * DAC_InitStruct )

Fills each DAC_InitStruct member with its default value.

Parameters:
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 211 of file stm32l1xx_dac.c.

References DAC_LFSRUnmask_Bit0, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Enable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_None, DAC_InitTypeDef::DAC_WaveGeneration, and DAC_WaveGeneration_None.

void DAC_WaveGenerationCmd | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_Wave,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_Wave,: Specifies the wave type to enable or disable. This parameter can be one of the following values:

  • DAC_Wave_Noise: noise wave generation
  • DAC_Wave_Triangle: triangle wave generation
NewState,: new state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
Note:
Return values:
None

Definition at line 321 of file stm32l1xx_dac.c.

References DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_WAVE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: DMA management functions

Functions

DMA management functions

DAC_Private_Functions

DMA management functions. More...

Functions

void DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.

Detailed Description

DMA management functions.

 ===============================================================================
                    ##### DMA management functions #####
 ===============================================================================

Function Documentation

void DAC_DMACmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel DMA request.

When enabled DMA1 is generated when an external trigger (EXTI Line9, TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
Note:
The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which must be already configured.
Return values:
None

Definition at line 483 of file stm32l1xx_dac.c.

References DAC, DAC_CR_DMAEN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

DAC_Private_Functions

Interrupts and flags management functions. More...

Functions

void | DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel's pending flags.
void | DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel's interrupt pending bits.
FlagStatus | DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
ITStatus | DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
void | DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
            ##### Interrupts and flags management functions #####
 ===============================================================================

Function Documentation

void DAC_ClearFlag | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_FLAG
 | ) |  |

Clears the DAC channel's pending flags.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_FLAG,: specifies the flag to clear. This parameter can be the following value:

  • DAC_FLAG_DMAUDR: DMA underrun flag
Return values:
None

Definition at line 597 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, and IS_DAC_FLAG.

void DAC_ClearITPendingBit | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT
 | ) |  |

Clears the DAC channel's interrupt pending bits.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt pending bit to clear. This parameter can be the following values:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Return values:
None

Definition at line 658 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, and IS_DAC_IT.

FlagStatus DAC_GetFlagStatus | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_FLAG
 | ) |  |

Checks whether the specified DAC flag is set or not.

Parameters:
DAC_Channel,: thee selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_FLAG,: specifies the flag to check. This parameter can be only of the following value:

  • DAC_FLAG_DMAUDR: DMA underrun flag
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Return values:
The new state of DAC_FLAG (SET or RESET).

Definition at line 564 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, IS_DAC_FLAG, RESET, and SET.

ITStatus DAC_GetITStatus | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT
 | ) |  |

Checks whether the specified DAC interrupt has occurred or not.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt source to check. This parameter can be the following values:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Return values:
The new state of DAC_IT (SET or RESET).

Definition at line 620 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, IS_DAC_IT, RESET, and SET.

void DAC_ITConfig | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC interrupts.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt sources to be enabled or disabled. This parameter can be the following value:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Parameters:
NewState,: new state of the specified DAC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 532 of file stm32l1xx_dac.c.

References DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_IT, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: DAC

Data Structures | Modules | Defines | Functions

DAC

STM32L1xx_StdPeriph_Driver

DAC driver modules. More...

Data Structures

struct | DAC_InitTypeDef
DAC Init structure definition. More...

Modules

DAC_Exported_Constants
DAC_Private_Functions

Defines

#define | CR_CLEAR_MASK ((uint32_t)0x00000FFE)
#define | DHR12R1_OFFSET ((uint32_t)0x00000008)
#define | DHR12R2_OFFSET ((uint32_t)0x00000014)
#define | DHR12RD_OFFSET ((uint32_t)0x00000020)
#define | DOR_OFFSET ((uint32_t)0x0000002C)
#define | DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
#define | DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Functions

void | DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel's pending flags.
void | DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel's interrupt pending bits.
void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
FlagStatus | DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
ITStatus | DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

DAC driver modules.

Define Documentation

#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)

Definition at line 116 of file stm32l1xx_dac.c.

Referenced by DAC_Init().

#define DHR12R1_OFFSET ((uint32_t)0x00000008)

Definition at line 123 of file stm32l1xx_dac.c.

Referenced by DAC_SetChannel1Data().

#define DHR12R2_OFFSET ((uint32_t)0x00000014)

Definition at line 124 of file stm32l1xx_dac.c.

Referenced by DAC_SetChannel2Data().

#define DHR12RD_OFFSET ((uint32_t)0x00000020)

Definition at line 125 of file stm32l1xx_dac.c.

Referenced by DAC_SetDualChannelData().

#define DOR_OFFSET ((uint32_t)0x0000002C)

Definition at line 128 of file stm32l1xx_dac.c.

Referenced by DAC_GetDataOutputValue().

#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)

Definition at line 120 of file stm32l1xx_dac.c.

Referenced by DAC_DualSoftwareTriggerCmd().

#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Definition at line 119 of file stm32l1xx_dac.c.

Referenced by DAC_DualSoftwareTriggerCmd().

Function Documentation

void DAC_ClearFlag | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_FLAG
 | ) |  |

Clears the DAC channel's pending flags.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_FLAG,: specifies the flag to clear. This parameter can be the following value:

  • DAC_FLAG_DMAUDR: DMA underrun flag
Return values:
None

Definition at line 597 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, and IS_DAC_FLAG.

void DAC_ClearITPendingBit | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT
 | ) |  |

Clears the DAC channel's interrupt pending bits.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt pending bit to clear. This parameter can be the following values:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Return values:
None

Definition at line 658 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, and IS_DAC_IT.

void DAC_Cmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel.

Parameters:
DAC_Channel,: The selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the DAC channel. This parameter can be: ENABLE or DISABLE.
Note:
When the DAC channel is enabled the trigger source can no more be modified.
Return values:
None

Definition at line 236 of file stm32l1xx_dac.c.

References DAC, DAC_CR_EN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

void DAC_DeInit ( void )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 156 of file stm32l1xx_dac.c.

References DISABLE, ENABLE, RCC_APB1Periph_DAC, and RCC_APB1PeriphResetCmd().

void DAC_DMACmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel DMA request.

When enabled DMA1 is generated when an external trigger (EXTI Line9, TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
Note:
The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which must be already configured.
Return values:
None

Definition at line 483 of file stm32l1xx_dac.c.

References DAC, DAC_CR_DMAEN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

void DAC_DualSoftwareTriggerCmd ( FunctionalState NewState )

Enables or disables simultaneously the two DAC channels software triggers.

Parameters:
NewState,: new state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 289 of file stm32l1xx_dac.c.

References DAC, DISABLE, DUAL_SWTRIG_RESET, DUAL_SWTRIG_SET, and IS_FUNCTIONAL_STATE.

uint16_t DAC_GetDataOutputValue ( uint32_t DAC_Channel )

Returns the last data output value of the selected DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 439 of file stm32l1xx_dac.c.

References DAC_BASE, DOR_OFFSET, and IS_DAC_CHANNEL.

FlagStatus DAC_GetFlagStatus | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_FLAG
 | ) |  |

Checks whether the specified DAC flag is set or not.

Parameters:
DAC_Channel,: thee selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_FLAG,: specifies the flag to check. This parameter can be only of the following value:

  • DAC_FLAG_DMAUDR: DMA underrun flag
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Return values:
The new state of DAC_FLAG (SET or RESET).

Definition at line 564 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, IS_DAC_FLAG, RESET, and SET.

ITStatus DAC_GetITStatus | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT
 | ) |  |

Checks whether the specified DAC interrupt has occurred or not.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt source to check. This parameter can be the following values:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Return values:
The new state of DAC_IT (SET or RESET).

Definition at line 620 of file stm32l1xx_dac.c.

References DAC, IS_DAC_CHANNEL, IS_DAC_IT, RESET, and SET.

void DAC_Init | ( | uint32_t | DAC_Channel,
 |  | DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected.
  • DAC_Channel_2: DAC Channel2 selected.
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
Return values:
None

Definition at line 175 of file stm32l1xx_dac.c.

References CR_CLEAR_MASK, DAC, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_InitTypeDef::DAC_Trigger, DAC_InitTypeDef::DAC_WaveGeneration, IS_DAC_CHANNEL, IS_DAC_GENERATE_WAVE, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, IS_DAC_OUTPUT_BUFFER_STATE, and IS_DAC_TRIGGER.

void DAC_ITConfig | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC interrupts.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_IT,: specifies the DAC interrupt sources to be enabled or disabled. This parameter can be the following value:

  • DAC_IT_DMAUDR: DMA underrun interrupt mask
Note:
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
Parameters:
NewState,: new state of the specified DAC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 532 of file stm32l1xx_dac.c.

References DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_IT, and IS_FUNCTIONAL_STATE.

void DAC_SetChannel1Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel1.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel1. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 350 of file stm32l1xx_dac.c.

References DAC_BASE, DHR12R1_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetChannel2Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel2.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel2. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 375 of file stm32l1xx_dac.c.

References DAC_BASE, DHR12R2_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetDualChannelData | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data2,
 |  | uint16_t | Data1
 | ) |  |

Set the specified data holding register value for dual channel DAC.

Parameters:
DAC_Align,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
None

Definition at line 405 of file stm32l1xx_dac.c.

References DAC_Align_8b_R, DAC_BASE, DHR12RD_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SoftwareTriggerCmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel software trigger.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 264 of file stm32l1xx_dac.c.

References DAC, DAC_SWTRIGR_SWTRIG1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

void DAC_StructInit ( DAC_InitTypeDef * DAC_InitStruct )

Fills each DAC_InitStruct member with its default value.

Parameters:
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 211 of file stm32l1xx_dac.c.

References DAC_LFSRUnmask_Bit0, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Enable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_None, DAC_InitTypeDef::DAC_WaveGeneration, and DAC_WaveGeneration_None.

void DAC_WaveGenerationCmd | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_Wave,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_Wave,: Specifies the wave type to enable or disable. This parameter can be one of the following values:

  • DAC_Wave_Noise: noise wave generation
  • DAC_Wave_Triangle: triangle wave generation
NewState,: new state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
Note:
Return values:
None

Definition at line 321 of file stm32l1xx_dac.c.

References DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_WAVE, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: DAC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DAC_InitTypeDef Struct Reference
DAC

DAC Init structure definition. More...

#include <stm32l1xx_dac.h>

Data Fields

uint32_t | DAC_LFSRUnmask_TriangleAmplitude
uint32_t | DAC_OutputBuffer
uint32_t | DAC_Trigger
uint32_t | DAC_WaveGeneration

Detailed Description

DAC Init structure definition.

Definition at line 51 of file stm32l1xx_dac.h.

Field Documentation

uint32_t DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude

Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of DAC_lfsrunmask_triangleamplitude

Definition at line 60 of file stm32l1xx_dac.h.

Referenced by DAC_Init(), and DAC_StructInit().

uint32_t DAC_InitTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC_output_buffer

Definition at line 64 of file stm32l1xx_dac.h.

Referenced by DAC_Init(), and DAC_StructInit().

uint32_t DAC_InitTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC_trigger_selection

Definition at line 53 of file stm32l1xx_dac.h.

Referenced by DAC_Init(), and DAC_StructInit().

uint32_t DAC_InitTypeDef::DAC_WaveGeneration

Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of DAC_wave_generation

Definition at line 56 of file stm32l1xx_dac.h.

Referenced by DAC_Init(), and DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_dac.h


STM32L1xx Standard Peripherals Firmware Library: DBGMCU_Exported_Constants

Defines

DBGMCU_Exported_Constants

DBGMCU

Defines

#define | DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define | DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define | DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
#define | DBGMCU_RTC_STOP ((uint32_t)0x00000400)
#define | DBGMCU_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM10_STOP ((uint32_t)0x00000008)
#define | DBGMCU_TIM11_STOP ((uint32_t)0x00000010)
#define | DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
#define | DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
#define | DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
#define | DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
#define | DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
#define | DBGMCU_TIM9_STOP ((uint32_t)0x00000004)
#define | DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
#define | IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
#define | IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
#define | IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))

Define Documentation

#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)

Definition at line 66 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)

Definition at line 67 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)

Definition at line 65 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)

Definition at line 63 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_SLEEP ((uint32_t)0x00000001)

Definition at line 52 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_STANDBY ((uint32_t)0x00000004)

Definition at line 54 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_STOP ((uint32_t)0x00000002)

Definition at line 53 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)

Definition at line 71 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)

Definition at line 72 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)

Definition at line 57 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)

Definition at line 58 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)

Definition at line 59 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)

Definition at line 60 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)

Definition at line 61 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)

Definition at line 62 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)

Definition at line 70 of file stm32l1xx_dbgmcu.h.

#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)

Definition at line 64 of file stm32l1xx_dbgmcu.h.

#define IS_DBGMCU_APB1PERIPH ( PERIPH ) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))

Definition at line 68 of file stm32l1xx_dbgmcu.h.

Referenced by DBGMCU_APB1PeriphConfig().

#define IS_DBGMCU_APB2PERIPH ( PERIPH ) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))

Definition at line 73 of file stm32l1xx_dbgmcu.h.

Referenced by DBGMCU_APB2PeriphConfig().

#define IS_DBGMCU_PERIPH ( PERIPH ) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))

Definition at line 55 of file stm32l1xx_dbgmcu.h.

Referenced by DBGMCU_Config().


STM32L1xx Standard Peripherals Firmware Library: DBGMCU_Private_Functions

Functions

DBGMCU_Private_Functions

DBGMCU

Functions

void | DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB1 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB2 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures low power mode behavior when the MCU is in Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Function Documentation

void DBGMCU_APB1PeriphConfig | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures APB1 peripheral behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the APB1 peripheral. This parameter can be any combination of the following values:

  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
  • DBGMCU_RTC_STOP: + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when Core is halted. + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar and Wakeup counter stopped when Core is halted.
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
NewState,: new state of the specified APB1 peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 123 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_APB1PERIPH, and IS_FUNCTIONAL_STATE.

void DBGMCU_APB2PeriphConfig | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures APB2 peripheral behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the APB2 peripheral. This parameter can be any combination of the following values:

  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
NewState,: new state of the specified APB2 peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 150 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_APB2PERIPH, and IS_FUNCTIONAL_STATE.

void DBGMCU_Config | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures low power mode behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the low power mode. This parameter can be any combination of the following values:

  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
  • DBGMCU_STOP: Keep debugger connection during STOP mode
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
NewState,: new state of the specified low power mode in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 81 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_PERIPH, and IS_FUNCTIONAL_STATE.

uint32_t DBGMCU_GetDEVID ( void )

Returns the device identifier.

Parameters:
None
Return values:
Device identifier

Definition at line 65 of file stm32l1xx_dbgmcu.c.

References DBGMCU, and IDCODE_DEVID_MASK.

uint32_t DBGMCU_GetREVID ( void )

Returns the device revision identifier.

Parameters:
None
Return values:
Device revision identifier

Definition at line 55 of file stm32l1xx_dbgmcu.c.

References DBGMCU.


STM32L1xx Standard Peripherals Firmware Library: DBGMCU

Modules | Defines | Functions

DBGMCU

STM32L1xx_StdPeriph_Driver

DBGMCU driver modules. More...

Modules

DBGMCU_Exported_Constants
DBGMCU_Private_Functions

Defines

#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Functions

void | DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB1 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB2 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures low power mode behavior when the MCU is in Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Detailed Description

DBGMCU driver modules.

Define Documentation

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Definition at line 39 of file stm32l1xx_dbgmcu.c.

Referenced by DBGMCU_GetDEVID().

Function Documentation

void DBGMCU_APB1PeriphConfig | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures APB1 peripheral behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the APB1 peripheral. This parameter can be any combination of the following values:

  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
  • DBGMCU_RTC_STOP: + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when Core is halted. + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar and Wakeup counter stopped when Core is halted.
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
NewState,: new state of the specified APB1 peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 123 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_APB1PERIPH, and IS_FUNCTIONAL_STATE.

void DBGMCU_APB2PeriphConfig | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures APB2 peripheral behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the APB2 peripheral. This parameter can be any combination of the following values:

  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
NewState,: new state of the specified APB2 peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 150 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_APB2PERIPH, and IS_FUNCTIONAL_STATE.

void DBGMCU_Config | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures low power mode behavior when the MCU is in Debug mode.

Parameters:
DBGMCU_Periph,: specifies the low power mode. This parameter can be any combination of the following values:

  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
  • DBGMCU_STOP: Keep debugger connection during STOP mode
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
NewState,: new state of the specified low power mode in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 81 of file stm32l1xx_dbgmcu.c.

References DBGMCU, DISABLE, IS_DBGMCU_PERIPH, and IS_FUNCTIONAL_STATE.

uint32_t DBGMCU_GetDEVID ( void )

Returns the device identifier.

Parameters:
None
Return values:
Device identifier

Definition at line 65 of file stm32l1xx_dbgmcu.c.

References DBGMCU, and IDCODE_DEVID_MASK.

uint32_t DBGMCU_GetREVID ( void )

Returns the device revision identifier.

Parameters:
None
Return values:
Device revision identifier

Definition at line 55 of file stm32l1xx_dbgmcu.c.

References DBGMCU.


STM32L1xx Standard Peripherals Firmware Library: DMA_data_transfer_direction

Defines

DMA_data_transfer_direction

DMA_Exported_Constants

Defines

#define | DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define | DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define | IS_DMA_DIR(DIR)

Define Documentation

#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)

Definition at line 111 of file stm32l1xx_dma.h.

#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)

Definition at line 112 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define IS_DMA_DIR ( DIR )
Value:
(((DIR) == DMA_DIR_PeripheralDST) || \
                         ((DIR) == DMA_DIR_PeripheralSRC))

Definition at line 113 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_peripheral_incremented_mode

Defines

DMA_peripheral_incremented_mode

DMA_Exported_Constants

Defines

#define | DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define | DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)

Define Documentation

#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)

Definition at line 124 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)

Definition at line 123 of file stm32l1xx_dma.h.

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PeripheralInc_Enable) || \
                                            ((STATE) == DMA_PeripheralInc_Disable))

Definition at line 125 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_memory_incremented_mode

Defines

DMA_memory_incremented_mode

DMA_Exported_Constants

Defines

#define | DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define | DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define | IS_DMA_MEMORY_INC_STATE(STATE)

Define Documentation

#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)

Definition at line 136 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)

Definition at line 135 of file stm32l1xx_dma.h.

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MemoryInc_Enable) || \
                                        ((STATE) == DMA_MemoryInc_Disable))

Definition at line 137 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_peripheral_data_size

Defines

DMA_peripheral_data_size

DMA_Exported_Constants

Defines

#define | DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define | DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)

Define Documentation

#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)

Definition at line 147 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)

Definition at line 148 of file stm32l1xx_dma.h.

#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)

Definition at line 149 of file stm32l1xx_dma.h.

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PeripheralDataSize_Byte) || \
                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
                                           ((SIZE) == DMA_PeripheralDataSize_Word))

Definition at line 150 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_memory_data_size

Defines

DMA_memory_data_size

DMA_Exported_Constants

Defines

#define | DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define | DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)

Define Documentation

#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)

Definition at line 161 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)

Definition at line 162 of file stm32l1xx_dma.h.

#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)

Definition at line 163 of file stm32l1xx_dma.h.

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MemoryDataSize_Byte) || \
                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
                                       ((SIZE) == DMA_MemoryDataSize_Word))

Definition at line 164 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_circular_normal_mode

Defines

DMA_circular_normal_mode

DMA_Exported_Constants

Defines

#define | DMA_Mode_Circular ((uint32_t)0x00000020)
#define | DMA_Mode_Normal ((uint32_t)0x00000000)
#define | IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))

Define Documentation

#define DMA_Mode_Circular ((uint32_t)0x00000020)

Definition at line 175 of file stm32l1xx_dma.h.

#define DMA_Mode_Normal ((uint32_t)0x00000000)

Definition at line 176 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define IS_DMA_MODE ( MODE ) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))

Definition at line 177 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_priority_level

Defines

DMA_priority_level

DMA_Exported_Constants

Defines

#define | DMA_Priority_High ((uint32_t)0x00002000)
#define | DMA_Priority_Low ((uint32_t)0x00000000)
#define | DMA_Priority_Medium ((uint32_t)0x00001000)
#define | DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define DMA_Priority_High ((uint32_t)0x00002000)

Definition at line 187 of file stm32l1xx_dma.h.

#define DMA_Priority_Low ((uint32_t)0x00000000)

Definition at line 189 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_Priority_Medium ((uint32_t)0x00001000)

Definition at line 188 of file stm32l1xx_dma.h.

#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)

Definition at line 186 of file stm32l1xx_dma.h.

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_Priority_VeryHigh) || \
                                   ((PRIORITY) == DMA_Priority_High) || \
                                   ((PRIORITY) == DMA_Priority_Medium) || \
                                   ((PRIORITY) == DMA_Priority_Low))

Definition at line 190 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_memory_to_memory

Defines

DMA_memory_to_memory

DMA_Exported_Constants

Defines

#define | DMA_M2M_Disable ((uint32_t)0x00000000)
#define | DMA_M2M_Enable ((uint32_t)0x00004000)
#define | IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))

Define Documentation

#define DMA_M2M_Disable ((uint32_t)0x00000000)

Definition at line 203 of file stm32l1xx_dma.h.

Referenced by DMA_StructInit().

#define DMA_M2M_Enable ((uint32_t)0x00004000)

Definition at line 202 of file stm32l1xx_dma.h.

#define IS_DMA_M2M_STATE ( STATE ) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))

Definition at line 204 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_interrupts_definition

Defines

DMA_interrupts_definition

DMA_Exported_Constants

Defines

#define | DMA1_IT_GL1 ((uint32_t)0x00000001)
#define | DMA1_IT_GL2 ((uint32_t)0x00000010)
#define | DMA1_IT_GL3 ((uint32_t)0x00000100)
#define | DMA1_IT_GL4 ((uint32_t)0x00001000)
#define | DMA1_IT_GL5 ((uint32_t)0x00010000)
#define | DMA1_IT_GL6 ((uint32_t)0x00100000)
#define | DMA1_IT_GL7 ((uint32_t)0x01000000)
#define | DMA1_IT_HT1 ((uint32_t)0x00000004)
#define | DMA1_IT_HT2 ((uint32_t)0x00000040)
#define | DMA1_IT_HT3 ((uint32_t)0x00000400)
#define | DMA1_IT_HT4 ((uint32_t)0x00004000)
#define | DMA1_IT_HT5 ((uint32_t)0x00040000)
#define | DMA1_IT_HT6 ((uint32_t)0x00400000)
#define | DMA1_IT_HT7 ((uint32_t)0x04000000)
#define | DMA1_IT_TC1 ((uint32_t)0x00000002)
#define | DMA1_IT_TC2 ((uint32_t)0x00000020)
#define | DMA1_IT_TC3 ((uint32_t)0x00000200)
#define | DMA1_IT_TC4 ((uint32_t)0x00002000)
#define | DMA1_IT_TC5 ((uint32_t)0x00020000)
#define | DMA1_IT_TC6 ((uint32_t)0x00200000)
#define | DMA1_IT_TC7 ((uint32_t)0x02000000)
#define | DMA1_IT_TE1 ((uint32_t)0x00000008)
#define | DMA1_IT_TE2 ((uint32_t)0x00000080)
#define | DMA1_IT_TE3 ((uint32_t)0x00000800)
#define | DMA1_IT_TE4 ((uint32_t)0x00008000)
#define | DMA1_IT_TE5 ((uint32_t)0x00080000)
#define | DMA1_IT_TE6 ((uint32_t)0x00800000)
#define | DMA1_IT_TE7 ((uint32_t)0x08000000)
#define | DMA2_IT_GL1 ((uint32_t)0x10000001)
#define | DMA2_IT_GL2 ((uint32_t)0x10000010)
#define | DMA2_IT_GL3 ((uint32_t)0x10000100)
#define | DMA2_IT_GL4 ((uint32_t)0x10001000)
#define | DMA2_IT_GL5 ((uint32_t)0x10010000)
#define | DMA2_IT_HT1 ((uint32_t)0x10000004)
#define | DMA2_IT_HT2 ((uint32_t)0x10000040)
#define | DMA2_IT_HT3 ((uint32_t)0x10000400)
#define | DMA2_IT_HT4 ((uint32_t)0x10004000)
#define | DMA2_IT_HT5 ((uint32_t)0x10040000)
#define | DMA2_IT_TC1 ((uint32_t)0x10000002)
#define | DMA2_IT_TC2 ((uint32_t)0x10000020)
#define | DMA2_IT_TC3 ((uint32_t)0x10000200)
#define | DMA2_IT_TC4 ((uint32_t)0x10002000)
#define | DMA2_IT_TC5 ((uint32_t)0x10020000)
#define | DMA2_IT_TE1 ((uint32_t)0x10000008)
#define | DMA2_IT_TE2 ((uint32_t)0x10000080)
#define | DMA2_IT_TE3 ((uint32_t)0x10000800)
#define | DMA2_IT_TE4 ((uint32_t)0x10008000)
#define | DMA2_IT_TE5 ((uint32_t)0x10080000)
#define | DMA_IT_HT ((uint32_t)0x00000004)
#define | DMA_IT_TC ((uint32_t)0x00000002)
#define | DMA_IT_TE ((uint32_t)0x00000008)
#define | IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define | IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define | IS_DMA_GET_IT(IT)

Define Documentation

#define DMA1_IT_GL1 ((uint32_t)0x00000001)

Definition at line 219 of file stm32l1xx_dma.h.

#define DMA1_IT_GL2 ((uint32_t)0x00000010)

Definition at line 223 of file stm32l1xx_dma.h.

#define DMA1_IT_GL3 ((uint32_t)0x00000100)

Definition at line 227 of file stm32l1xx_dma.h.

#define DMA1_IT_GL4 ((uint32_t)0x00001000)

Definition at line 231 of file stm32l1xx_dma.h.

#define DMA1_IT_GL5 ((uint32_t)0x00010000)

Definition at line 235 of file stm32l1xx_dma.h.

#define DMA1_IT_GL6 ((uint32_t)0x00100000)

Definition at line 239 of file stm32l1xx_dma.h.

#define DMA1_IT_GL7 ((uint32_t)0x01000000)

Definition at line 243 of file stm32l1xx_dma.h.

#define DMA1_IT_HT1 ((uint32_t)0x00000004)

Definition at line 221 of file stm32l1xx_dma.h.

#define DMA1_IT_HT2 ((uint32_t)0x00000040)

Definition at line 225 of file stm32l1xx_dma.h.

#define DMA1_IT_HT3 ((uint32_t)0x00000400)

Definition at line 229 of file stm32l1xx_dma.h.

#define DMA1_IT_HT4 ((uint32_t)0x00004000)

Definition at line 233 of file stm32l1xx_dma.h.

#define DMA1_IT_HT5 ((uint32_t)0x00040000)

Definition at line 237 of file stm32l1xx_dma.h.

#define DMA1_IT_HT6 ((uint32_t)0x00400000)

Definition at line 241 of file stm32l1xx_dma.h.

#define DMA1_IT_HT7 ((uint32_t)0x04000000)

Definition at line 245 of file stm32l1xx_dma.h.

#define DMA1_IT_TC1 ((uint32_t)0x00000002)

Definition at line 220 of file stm32l1xx_dma.h.

#define DMA1_IT_TC2 ((uint32_t)0x00000020)

Definition at line 224 of file stm32l1xx_dma.h.

#define DMA1_IT_TC3 ((uint32_t)0x00000200)

Definition at line 228 of file stm32l1xx_dma.h.

#define DMA1_IT_TC4 ((uint32_t)0x00002000)

Definition at line 232 of file stm32l1xx_dma.h.

#define DMA1_IT_TC5 ((uint32_t)0x00020000)

Definition at line 236 of file stm32l1xx_dma.h.

#define DMA1_IT_TC6 ((uint32_t)0x00200000)

Definition at line 240 of file stm32l1xx_dma.h.

#define DMA1_IT_TC7 ((uint32_t)0x02000000)

Definition at line 244 of file stm32l1xx_dma.h.

#define DMA1_IT_TE1 ((uint32_t)0x00000008)

Definition at line 222 of file stm32l1xx_dma.h.

#define DMA1_IT_TE2 ((uint32_t)0x00000080)

Definition at line 226 of file stm32l1xx_dma.h.

#define DMA1_IT_TE3 ((uint32_t)0x00000800)

Definition at line 230 of file stm32l1xx_dma.h.

#define DMA1_IT_TE4 ((uint32_t)0x00008000)

Definition at line 234 of file stm32l1xx_dma.h.

#define DMA1_IT_TE5 ((uint32_t)0x00080000)

Definition at line 238 of file stm32l1xx_dma.h.

#define DMA1_IT_TE6 ((uint32_t)0x00800000)

Definition at line 242 of file stm32l1xx_dma.h.

#define DMA1_IT_TE7 ((uint32_t)0x08000000)

Definition at line 246 of file stm32l1xx_dma.h.

#define DMA2_IT_GL1 ((uint32_t)0x10000001)

Definition at line 248 of file stm32l1xx_dma.h.

#define DMA2_IT_GL2 ((uint32_t)0x10000010)

Definition at line 252 of file stm32l1xx_dma.h.

#define DMA2_IT_GL3 ((uint32_t)0x10000100)

Definition at line 256 of file stm32l1xx_dma.h.

#define DMA2_IT_GL4 ((uint32_t)0x10001000)

Definition at line 260 of file stm32l1xx_dma.h.

#define DMA2_IT_GL5 ((uint32_t)0x10010000)

Definition at line 264 of file stm32l1xx_dma.h.

#define DMA2_IT_HT1 ((uint32_t)0x10000004)

Definition at line 250 of file stm32l1xx_dma.h.

#define DMA2_IT_HT2 ((uint32_t)0x10000040)

Definition at line 254 of file stm32l1xx_dma.h.

#define DMA2_IT_HT3 ((uint32_t)0x10000400)

Definition at line 258 of file stm32l1xx_dma.h.

#define DMA2_IT_HT4 ((uint32_t)0x10004000)

Definition at line 262 of file stm32l1xx_dma.h.

#define DMA2_IT_HT5 ((uint32_t)0x10040000)

Definition at line 266 of file stm32l1xx_dma.h.

#define DMA2_IT_TC1 ((uint32_t)0x10000002)

Definition at line 249 of file stm32l1xx_dma.h.

#define DMA2_IT_TC2 ((uint32_t)0x10000020)

Definition at line 253 of file stm32l1xx_dma.h.

#define DMA2_IT_TC3 ((uint32_t)0x10000200)

Definition at line 257 of file stm32l1xx_dma.h.

#define DMA2_IT_TC4 ((uint32_t)0x10002000)

Definition at line 261 of file stm32l1xx_dma.h.

#define DMA2_IT_TC5 ((uint32_t)0x10020000)

Definition at line 265 of file stm32l1xx_dma.h.

#define DMA2_IT_TE1 ((uint32_t)0x10000008)

Definition at line 251 of file stm32l1xx_dma.h.

#define DMA2_IT_TE2 ((uint32_t)0x10000080)

Definition at line 255 of file stm32l1xx_dma.h.

#define DMA2_IT_TE3 ((uint32_t)0x10000800)

Definition at line 259 of file stm32l1xx_dma.h.

#define DMA2_IT_TE4 ((uint32_t)0x10008000)

Definition at line 263 of file stm32l1xx_dma.h.

#define DMA2_IT_TE5 ((uint32_t)0x10080000)

Definition at line 267 of file stm32l1xx_dma.h.

#define DMA_IT_HT ((uint32_t)0x00000004)

Definition at line 215 of file stm32l1xx_dma.h.

#define DMA_IT_TC ((uint32_t)0x00000002)

Definition at line 214 of file stm32l1xx_dma.h.

#define DMA_IT_TE ((uint32_t)0x00000008)

Definition at line 216 of file stm32l1xx_dma.h.

#define IS_DMA_CLEAR_IT ( IT ) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))

Definition at line 269 of file stm32l1xx_dma.h.

Referenced by DMA_ClearITPendingBit().

#define IS_DMA_CONFIG_IT ( IT ) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))

Definition at line 217 of file stm32l1xx_dma.h.

Referenced by DMA_ITConfig().

#define IS_DMA_GET_IT ( IT )
Value:
(((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))

Definition at line 271 of file stm32l1xx_dma.h.

Referenced by DMA_GetITStatus().


STM32L1xx Standard Peripherals Firmware Library: DMA_flags_definition

Defines

DMA_flags_definition

DMA_Exported_Constants

Defines

#define | DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define | DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define | DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define | DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define | DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define | DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define | DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define | DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define | DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define | DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define | DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define | DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define | DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define | DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define | DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define | DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define | DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define | DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define | DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define | DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define | DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define | IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define | IS_DMA_GET_FLAG(FLAG)

Define Documentation

#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)

Definition at line 302 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)

Definition at line 306 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)

Definition at line 310 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)

Definition at line 314 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)

Definition at line 318 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)

Definition at line 322 of file stm32l1xx_dma.h.

#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)

Definition at line 326 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)

Definition at line 304 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)

Definition at line 308 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)

Definition at line 312 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)

Definition at line 316 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)

Definition at line 320 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)

Definition at line 324 of file stm32l1xx_dma.h.

#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)

Definition at line 328 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)

Definition at line 303 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)

Definition at line 307 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)

Definition at line 311 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)

Definition at line 315 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)

Definition at line 319 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)

Definition at line 323 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)

Definition at line 327 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)

Definition at line 305 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)

Definition at line 309 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)

Definition at line 313 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)

Definition at line 317 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)

Definition at line 321 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)

Definition at line 325 of file stm32l1xx_dma.h.

#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)

Definition at line 329 of file stm32l1xx_dma.h.

#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)

Definition at line 331 of file stm32l1xx_dma.h.

#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)

Definition at line 335 of file stm32l1xx_dma.h.

#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)

Definition at line 339 of file stm32l1xx_dma.h.

#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)

Definition at line 343 of file stm32l1xx_dma.h.

#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)

Definition at line 347 of file stm32l1xx_dma.h.

#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)

Definition at line 333 of file stm32l1xx_dma.h.

#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)

Definition at line 337 of file stm32l1xx_dma.h.

#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)

Definition at line 341 of file stm32l1xx_dma.h.

#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)

Definition at line 345 of file stm32l1xx_dma.h.

#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)

Definition at line 349 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)

Definition at line 332 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)

Definition at line 336 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)

Definition at line 340 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)

Definition at line 344 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)

Definition at line 348 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)

Definition at line 334 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)

Definition at line 338 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)

Definition at line 342 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)

Definition at line 346 of file stm32l1xx_dma.h.

#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)

Definition at line 350 of file stm32l1xx_dma.h.

#define IS_DMA_CLEAR_FLAG ( FLAG ) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))

Definition at line 352 of file stm32l1xx_dma.h.

Referenced by DMA_ClearFlag().

#define IS_DMA_GET_FLAG ( FLAG )
Value:
(((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))

Definition at line 354 of file stm32l1xx_dma.h.

Referenced by DMA_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: DMA_Buffer_Size

Defines

DMA_Buffer_Size

DMA_Exported_Constants

Defines

#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Definition at line 386 of file stm32l1xx_dma.h.

Referenced by DMA_Init().


STM32L1xx Standard Peripherals Firmware Library: DMA_Exported_Constants

Modules | Defines

DMA_Exported_Constants

DMA

Modules

DMA_data_transfer_direction
DMA_peripheral_incremented_mode
DMA_memory_incremented_mode
DMA_peripheral_data_size
DMA_memory_data_size
DMA_circular_normal_mode
DMA_priority_level
DMA_memory_to_memory
DMA_interrupts_definition
DMA_flags_definition
DMA_Buffer_Size

Defines

#define IS_DMA_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_DMA_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == DMA1_Channel1) || \
                                   ((PERIPH) == DMA1_Channel2) || \
                                   ((PERIPH) == DMA1_Channel3) || \
                                   ((PERIPH) == DMA1_Channel4) || \
                                   ((PERIPH) == DMA1_Channel5) || \
                                   ((PERIPH) == DMA1_Channel6) || \
                                   ((PERIPH) == DMA1_Channel7) || \
                                   ((PERIPH) == DMA2_Channel1) || \
                                   ((PERIPH) == DMA2_Channel2) || \
                                   ((PERIPH) == DMA2_Channel3) || \
                                   ((PERIPH) == DMA2_Channel4) || \
                                   ((PERIPH) == DMA2_Channel5))

Definition at line 94 of file stm32l1xx_dma.h.

Referenced by DMA_Cmd(), DMA_DeInit(), DMA_GetCurrDataCounter(), DMA_Init(), DMA_ITConfig(), and DMA_SetCurrDataCounter().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

DMA_Private_Functions

Initialization and Configuration functions. More...

Functions

void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..] This subsection provides functions allowing to initialize the DMA channel
         source and destination addresses, incrementation and data sizes, transfer
         direction, buffer size, circular/normal mode selection, memory-to-memory
         mode selection and channel priority value.
    [..] The DMA_Init() function follows the DMA configuration procedures as described
         in reference manual (RM0038).

Function Documentation

void DMA_Cmd | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
NewState,: new state of the DMAy Channelx. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 327 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DISABLE, DMA_CCR1_EN, IS_DMA_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void DMA_DeInit ( DMA_Channel_TypeDef * DMAy_Channelx )

Deinitializes the DMAy Channelx registers to their default reset values.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
None

Definition at line 141 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA1, DMA1_Channel1, DMA1_CHANNEL1_IT_MASK, DMA1_Channel2, DMA1_CHANNEL2_IT_MASK, DMA1_Channel3, DMA1_CHANNEL3_IT_MASK, DMA1_Channel4, DMA1_CHANNEL4_IT_MASK, DMA1_Channel5, DMA1_CHANNEL5_IT_MASK, DMA1_Channel6, DMA1_CHANNEL6_IT_MASK, DMA1_Channel7, DMA1_CHANNEL7_IT_MASK, DMA2, DMA2_Channel1, DMA2_CHANNEL1_IT_MASK, DMA2_Channel2, DMA2_CHANNEL2_IT_MASK, DMA2_Channel3, DMA2_CHANNEL3_IT_MASK, DMA2_Channel4, DMA2_CHANNEL4_IT_MASK, DMA2_Channel5, DMA2_CHANNEL5_IT_MASK, DMA_CCR1_EN, and IS_DMA_ALL_PERIPH.

void DMA_Init | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 235 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, CCR_CLEAR_MASK, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_InitTypeDef::DMA_M2M, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_InitTypeDef::DMA_MemoryInc, DMA_InitTypeDef::DMA_Mode, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_InitTypeDef::DMA_Priority, IS_DMA_ALL_PERIPH, IS_DMA_BUFFER_SIZE, IS_DMA_DIR, IS_DMA_M2M_STATE, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, and IS_DMA_PRIORITY.

void DMA_StructInit ( DMA_InitTypeDef * DMA_InitStruct )

Fills each DMA_InitStruct member with its default value.

Parameters:
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 292 of file stm32l1xx_dma.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, and DMA_Priority_Low.


STM32L1xx Standard Peripherals Firmware Library: Data Counter functions

Functions

Data Counter functions

DMA_Private_Functions

Data Counter functions. More...

Functions

uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.

Detailed Description

Data Counter functions.

 ===============================================================================
                      ##### Data Counter functions #####
 ===============================================================================
    [..] This subsection provides function allowing to configure and read the buffer
         size (number of data to be transferred).The DMA data counter can be written
         only when the DMA channel is disabled (ie. after transfer complete event).
    [..] The following function can be used to write the Channel data counter value:
         (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
             DataNumber).
    -@- It is advised to use this function rather than DMA_Init() in situations
        where only the Data buffer needs to be reloaded.
    [..] The DMA data counter can be read to indicate the number of remaining transfers
         for the relative DMA channel. This counter is decremented at the end of each
         data transfer and when the transfer is complete:
         (+) If Normal mode is selected: the counter is set to 0.
         (+) If Circular mode is selected: the counter is reloaded with the initial
         value(configured before enabling the DMA channel).
    [..] The following function can be used to read the Channel data counter value:
         (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).

Function Documentation

uint16_t DMA_GetCurrDataCounter ( DMA_Channel_TypeDef * DMAy_Channelx )

Returns the number of remaining data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
The number of remaining data units in the current DMAy Channelx transfer.

Definition at line 404 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

void DMA_SetCurrDataCounter | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint16_t | DataNumber
 | ) |  |

Sets the number of data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DataNumber,: The number of data units in the current DMAy Channelx transfer.
Note:
This function can only be used when the DMAy_Channelx is disabled.
Return values:
None.

Definition at line 386 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

DMA_Private_Functions

Interrupts and flags management functions. More...

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
          ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] This subsection provides functions allowing to configure the DMA Interrupts
         sources and check or clear the flags or pending bits status.
         The user should identify which mode will be used in his application to manage
         the DMA controller events: Polling mode or Interrupt mode.
  *** Polling Mode ***
  ====================
    [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
         number  x : DMA channel number ).
         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
             above occurred.
    -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
    [..]In this Mode it is advised to use the following functions:
        (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
        (+) void DMA_ClearFlag(uint32_t DMA_FLAG);

  *** Interrupt Mode ***
  ======================
    [..] Each DMA channel can be managed through 4 Interrupts:
    (+) Interrupt Source
       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
            event.
       (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
            event.
       (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
       (##) DMA_IT_GL : to indicate that at least one of the interrupts described
            above occurred.
    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
        the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
    [..]In this Mode it is advised to use the following functions:
        (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
            FunctionalState NewState);
        (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
        (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);

Function Documentation

void DMA_ClearFlag ( uint32_t DMAy_FLAG )

Clears the DMAy Channelx's pending flags.

Parameters:
DMAy_FLAG,: specifies the flag to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note:
Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
Return values:
None

Definition at line 655 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_CLEAR_FLAG, and RESET.

void DMA_ClearITPendingBit ( uint32_t DMAy_IT )

Clears the DMAy Channelx's interrupt pending bits.

Parameters:
DMAy_IT,: specifies the DMAy interrupt pending bit to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note:
Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other interrupts relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and DMAy_IT_TEx).
Return values:
None

Definition at line 829 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_CLEAR_IT, and RESET.

FlagStatus DMA_GetFlagStatus ( uint32_t DMAy_FLAG )

Checks whether the specified DMAy Channelx flag is set or not.

Parameters:
DMAy_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note:
The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or DMAy_FLAG_TEx).
Return values:
The new state of DMAy_FLAG (SET or RESET).

Definition at line 559 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_GET_FLAG, RESET, and SET.

ITStatus DMA_GetITStatus ( uint32_t DMAy_IT )

Checks whether the specified DMAy Channelx interrupt has occurred or not.

Parameters:
DMAy_IT,: specifies the DMAy interrupt source to check. This parameter can be one of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note:
The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other interrupts relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx or DMAy_IT_TEx).
Return values:
The new state of DMAy_IT (SET or RESET).

Definition at line 733 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_GET_IT, RESET, and SET.

void DMA_ITConfig | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint32_t | DMA_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx interrupts.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_IT,: specifies the DMA interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
NewState,: new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 479 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DISABLE, IS_DMA_ALL_PERIPH, IS_DMA_CONFIG_IT, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: DMA

Data Structures | Modules | Defines | Functions

DMA

STM32L1xx_StdPeriph_Driver

DMA driver modules. More...

Data Structures

struct | DMA_InitTypeDef
DMA Init structure definition. More...

Modules

DMA_Exported_Constants
DMA_Private_Functions

Defines

#define | CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
#define | DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define | DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
#define | DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | FLAG_MASK ((uint32_t)0x10000000)

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

DMA driver modules.

Define Documentation

#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)

Definition at line 105 of file stm32l1xx_dma.c.

Referenced by DMA_Init().

#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))

Definition at line 86 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))

Definition at line 87 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))

Definition at line 88 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))

Definition at line 89 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))

Definition at line 90 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))

Definition at line 91 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))

Definition at line 92 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))

Definition at line 95 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))

Definition at line 96 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))

Definition at line 97 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))

Definition at line 98 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))

Definition at line 99 of file stm32l1xx_dma.c.

Referenced by DMA_DeInit().

#define FLAG_MASK ((uint32_t)0x10000000)

Definition at line 102 of file stm32l1xx_dma.c.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_GetFlagStatus(), and DMA_GetITStatus().

Function Documentation

void DMA_ClearFlag ( uint32_t DMAy_FLAG )

Clears the DMAy Channelx's pending flags.

Parameters:
DMAy_FLAG,: specifies the flag to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note:
Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
Return values:
None

Definition at line 655 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_CLEAR_FLAG, and RESET.

void DMA_ClearITPendingBit ( uint32_t DMAy_IT )

Clears the DMAy Channelx's interrupt pending bits.

Parameters:
DMAy_IT,: specifies the DMAy interrupt pending bit to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note:
Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other interrupts relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and DMAy_IT_TEx).
Return values:
None

Definition at line 829 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_CLEAR_IT, and RESET.

void DMA_Cmd | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
NewState,: new state of the DMAy Channelx. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 327 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DISABLE, DMA_CCR1_EN, IS_DMA_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void DMA_DeInit ( DMA_Channel_TypeDef * DMAy_Channelx )

Deinitializes the DMAy Channelx registers to their default reset values.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
None

Definition at line 141 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA1, DMA1_Channel1, DMA1_CHANNEL1_IT_MASK, DMA1_Channel2, DMA1_CHANNEL2_IT_MASK, DMA1_Channel3, DMA1_CHANNEL3_IT_MASK, DMA1_Channel4, DMA1_CHANNEL4_IT_MASK, DMA1_Channel5, DMA1_CHANNEL5_IT_MASK, DMA1_Channel6, DMA1_CHANNEL6_IT_MASK, DMA1_Channel7, DMA1_CHANNEL7_IT_MASK, DMA2, DMA2_Channel1, DMA2_CHANNEL1_IT_MASK, DMA2_Channel2, DMA2_CHANNEL2_IT_MASK, DMA2_Channel3, DMA2_CHANNEL3_IT_MASK, DMA2_Channel4, DMA2_CHANNEL4_IT_MASK, DMA2_Channel5, DMA2_CHANNEL5_IT_MASK, DMA_CCR1_EN, and IS_DMA_ALL_PERIPH.

uint16_t DMA_GetCurrDataCounter ( DMA_Channel_TypeDef * DMAy_Channelx )

Returns the number of remaining data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
The number of remaining data units in the current DMAy Channelx transfer.

Definition at line 404 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

FlagStatus DMA_GetFlagStatus ( uint32_t DMAy_FLAG )

Checks whether the specified DMAy Channelx flag is set or not.

Parameters:
DMAy_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note:
The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or DMAy_FLAG_TEx).
Return values:
The new state of DMAy_FLAG (SET or RESET).

Definition at line 559 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_GET_FLAG, RESET, and SET.

ITStatus DMA_GetITStatus ( uint32_t DMAy_IT )

Checks whether the specified DMAy Channelx interrupt has occurred or not.

Parameters:
DMAy_IT,: specifies the DMAy interrupt source to check. This parameter can be one of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note:
The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other interrupts relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx or DMAy_IT_TEx).
Return values:
The new state of DMAy_IT (SET or RESET).

Definition at line 733 of file stm32l1xx_dma.c.

References DMA1, DMA2, FLAG_MASK, IS_DMA_GET_IT, RESET, and SET.

void DMA_Init | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 235 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, CCR_CLEAR_MASK, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_InitTypeDef::DMA_M2M, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_InitTypeDef::DMA_MemoryInc, DMA_InitTypeDef::DMA_Mode, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_InitTypeDef::DMA_Priority, IS_DMA_ALL_PERIPH, IS_DMA_BUFFER_SIZE, IS_DMA_DIR, IS_DMA_M2M_STATE, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, and IS_DMA_PRIORITY.

void DMA_ITConfig | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint32_t | DMA_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx interrupts.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_IT,: specifies the DMA interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
NewState,: new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 479 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CCR, DISABLE, IS_DMA_ALL_PERIPH, IS_DMA_CONFIG_IT, and IS_FUNCTIONAL_STATE.

void DMA_SetCurrDataCounter | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint16_t | DataNumber
 | ) |  |

Sets the number of data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DataNumber,: The number of data units in the current DMAy Channelx transfer.
Note:
This function can only be used when the DMAy_Channelx is disabled.
Return values:
None.

Definition at line 386 of file stm32l1xx_dma.c.

References DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

void DMA_StructInit ( DMA_InitTypeDef * DMA_InitStruct )

Fills each DMA_InitStruct member with its default value.

Parameters:
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 292 of file stm32l1xx_dma.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, and DMA_Priority_Low.


STM32L1xx Standard Peripherals Firmware Library: DMA_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_InitTypeDef Struct Reference
DMA

DMA Init structure definition. More...

#include <stm32l1xx_dma.h>

Data Fields

uint32_t | DMA_BufferSize
uint32_t | DMA_DIR
uint32_t | DMA_M2M
uint32_t | DMA_MemoryBaseAddr
uint32_t | DMA_MemoryDataSize
uint32_t | DMA_MemoryInc
uint32_t | DMA_Mode
uint32_t | DMA_PeripheralBaseAddr
uint32_t | DMA_PeripheralDataSize
uint32_t | DMA_PeripheralInc
uint32_t | DMA_Priority

Detailed Description

DMA Init structure definition.

Definition at line 51 of file stm32l1xx_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::DMA_BufferSize

Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction.

Definition at line 60 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_DIR

Specifies if the peripheral is the source or destination. This parameter can be a value of DMA_data_transfer_direction

Definition at line 57 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_M2M

Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of DMA_memory_to_memory

Definition at line 84 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_MemoryBaseAddr

Specifies the memory base address for DMAy Channelx.

Definition at line 55 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_MemoryDataSize

Specifies the Memory data width. This parameter can be a value of DMA_memory_data_size

Definition at line 73 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_MemoryInc

Specifies whether the memory address register is incremented or not. This parameter can be a value of DMA_memory_incremented_mode

Definition at line 67 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA_circular_normal_mode

Note:
: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 76 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_PeripheralBaseAddr

Specifies the peripheral base address for DMAy Channelx.

Definition at line 53 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_PeripheralDataSize

Specifies the Peripheral data width. This parameter can be a value of DMA_peripheral_data_size

Definition at line 70 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_PeripheralInc

Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of DMA_peripheral_incremented_mode

Definition at line 64 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

uint32_t DMA_InitTypeDef::DMA_Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA_priority_level

Definition at line 81 of file stm32l1xx_dma.h.

Referenced by DMA_Init(), and DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_dma.h


STM32L1xx Standard Peripherals Firmware Library: EXTI_Lines

Defines

EXTI_Lines

EXTI_Exported_Constants

Defines

#define | EXTI_Line0 ((uint32_t)0x00000001)
#define | EXTI_Line1 ((uint32_t)0x00000002)
#define | EXTI_Line10 ((uint32_t)0x00000400)
#define | EXTI_Line11 ((uint32_t)0x00000800)
#define | EXTI_Line12 ((uint32_t)0x00001000)
#define | EXTI_Line13 ((uint32_t)0x00002000)
#define | EXTI_Line14 ((uint32_t)0x00004000)
#define | EXTI_Line15 ((uint32_t)0x00008000)
#define | EXTI_Line16 ((uint32_t)0x00010000)
#define | EXTI_Line17 ((uint32_t)0x00020000)
#define | EXTI_Line18 ((uint32_t)0x00040000)
#define | EXTI_Line19 ((uint32_t)0x00080000)
#define | EXTI_Line2 ((uint32_t)0x00000004)
#define | EXTI_Line20 ((uint32_t)0x00100000)
#define | EXTI_Line21 ((uint32_t)0x00200000)
#define | EXTI_Line22 ((uint32_t)0x00400000)
#define | EXTI_Line23 ((uint32_t)0x00800000)
#define | EXTI_Line3 ((uint32_t)0x00000008)
#define | EXTI_Line4 ((uint32_t)0x00000010)
#define | EXTI_Line5 ((uint32_t)0x00000020)
#define | EXTI_Line6 ((uint32_t)0x00000040)
#define | EXTI_Line7 ((uint32_t)0x00000080)
#define | EXTI_Line8 ((uint32_t)0x00000100)
#define | EXTI_Line9 ((uint32_t)0x00000200)
#define | IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define | IS_GET_EXTI_LINE(LINE)

Define Documentation

#define EXTI_Line0 ((uint32_t)0x00000001)

External interrupt line 0

Definition at line 102 of file stm32l1xx_exti.h.

#define EXTI_Line1 ((uint32_t)0x00000002)

External interrupt line 1

Definition at line 103 of file stm32l1xx_exti.h.

#define EXTI_Line10 ((uint32_t)0x00000400)

External interrupt line 10

Definition at line 112 of file stm32l1xx_exti.h.

#define EXTI_Line11 ((uint32_t)0x00000800)

External interrupt line 11

Definition at line 113 of file stm32l1xx_exti.h.

#define EXTI_Line12 ((uint32_t)0x00001000)

External interrupt line 12

Definition at line 114 of file stm32l1xx_exti.h.

#define EXTI_Line13 ((uint32_t)0x00002000)

External interrupt line 13

Definition at line 115 of file stm32l1xx_exti.h.

#define EXTI_Line14 ((uint32_t)0x00004000)

External interrupt line 14

Definition at line 116 of file stm32l1xx_exti.h.

#define EXTI_Line15 ((uint32_t)0x00008000)

External interrupt line 15

Definition at line 117 of file stm32l1xx_exti.h.

#define EXTI_Line16 ((uint32_t)0x00010000)

External interrupt line 16 Connected to the PVD Output

Definition at line 118 of file stm32l1xx_exti.h.

#define EXTI_Line17 ((uint32_t)0x00020000)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 120 of file stm32l1xx_exti.h.

#define EXTI_Line18 ((uint32_t)0x00040000)

External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event

Definition at line 123 of file stm32l1xx_exti.h.

#define EXTI_Line19 ((uint32_t)0x00080000)

External interrupt line 19 Connected to the RTC Tamper and Time Stamp events

Definition at line 126 of file stm32l1xx_exti.h.

#define EXTI_Line2 ((uint32_t)0x00000004)

External interrupt line 2

Definition at line 104 of file stm32l1xx_exti.h.

#define EXTI_Line20 ((uint32_t)0x00100000)

External interrupt line 20 Connected to the RTC Wakeup event

Definition at line 129 of file stm32l1xx_exti.h.

#define EXTI_Line21 ((uint32_t)0x00200000)

External interrupt line 21 Connected to the Comparator 1 event

Definition at line 132 of file stm32l1xx_exti.h.

#define EXTI_Line22 ((uint32_t)0x00400000)

External interrupt line 22 Connected to the Comparator 2 event

Definition at line 136 of file stm32l1xx_exti.h.

#define EXTI_Line23 ((uint32_t)0x00800000)

External interrupt line 23 Comparator channel acquisition event

Definition at line 140 of file stm32l1xx_exti.h.

#define EXTI_Line3 ((uint32_t)0x00000008)

External interrupt line 3

Definition at line 105 of file stm32l1xx_exti.h.

#define EXTI_Line4 ((uint32_t)0x00000010)

External interrupt line 4

Definition at line 106 of file stm32l1xx_exti.h.

#define EXTI_Line5 ((uint32_t)0x00000020)

External interrupt line 5

Definition at line 107 of file stm32l1xx_exti.h.

#define EXTI_Line6 ((uint32_t)0x00000040)

External interrupt line 6

Definition at line 108 of file stm32l1xx_exti.h.

#define EXTI_Line7 ((uint32_t)0x00000080)

External interrupt line 7

Definition at line 109 of file stm32l1xx_exti.h.

#define EXTI_Line8 ((uint32_t)0x00000100)

External interrupt line 8

Definition at line 110 of file stm32l1xx_exti.h.

#define EXTI_Line9 ((uint32_t)0x00000200)

External interrupt line 9

Definition at line 111 of file stm32l1xx_exti.h.

#define IS_EXTI_LINE ( LINE ) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))

Definition at line 143 of file stm32l1xx_exti.h.

Referenced by EXTI_ClearFlag(), EXTI_ClearITPendingBit(), EXTI_GenerateSWInterrupt(), and EXTI_Init().

#define IS_GET_EXTI_LINE ( LINE )
Value:
(((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))

Definition at line 145 of file stm32l1xx_exti.h.

Referenced by EXTI_GetFlagStatus(), and EXTI_GetITStatus().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

EXTI_Private_Functions

Initialization and Configuration functions. More...

Functions

void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and Configuration functions #####
  ==============================================================================

Function Documentation

void EXTI_DeInit ( void )

Deinitializes the EXTI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 104 of file stm32l1xx_exti.c.

References EXTI.

void EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt on selected EXTI line.

Parameters:
EXTI_Line,: specifies the EXTI line on which the software interrupt will be generated. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 196 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

void EXTI_Init ( EXTI_InitTypeDef * EXTI_InitStruct )

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

EXTI_Line specifies the EXTI line (EXTI0....EXTI23). EXTI_Mode specifies which EXTI line is used as interrupt or an event. EXTI_Trigger selects the trigger. When the trigger occurs, interrupt pending bit will be set. EXTI_LineCmd controls (Enable/Disable) the EXTI line.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
Return values:
None

Definition at line 125 of file stm32l1xx_exti.c.

References DISABLE, EXTI, EXTI_BASE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, and IS_FUNCTIONAL_STATE.

void EXTI_StructInit ( EXTI_InitTypeDef * EXTI_InitStruct )

Fills each EXTI_InitStruct member with its reset value.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 181 of file stm32l1xx_exti.c.

References DISABLE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_LINENONE, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, and EXTI_Trigger_Falling.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

EXTI_Private_Functions

Interrupts and flags management functions. More...

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.

Detailed Description

Interrupts and flags management functions.

  ==============================================================================
             ##### Interrupts and flags management functions #####
  ==============================================================================

Function Documentation

void EXTI_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags.

Parameters:
EXTI_Line,: specifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 250 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

void EXTI_ClearITPendingBit ( uint32_t EXTI_Line )

Clears the EXTI's line pending bits.

Parameters:
EXTI_Line,: specifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 290 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

FlagStatus EXTI_GetFlagStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line flag is set or not.

Parameters:
EXTI_Line,: specifies the EXTI line flag to check. This parameter can be: EXTI_Linex: External interrupt line x where x(0..23).
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 227 of file stm32l1xx_exti.c.

References EXTI, IS_GET_EXTI_LINE, RESET, and SET.

ITStatus EXTI_GetITStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line is asserted or not.

Parameters:
EXTI_Line,: specifies the EXTI line to check. This parameter can be: EXTI_Linex: External interrupt line x where x(0..23).
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 265 of file stm32l1xx_exti.c.

References EXTI, IS_GET_EXTI_LINE, RESET, and SET.


STM32L1xx Standard Peripherals Firmware Library: EXTI

Data Structures | Modules | Defines | Enumerations | Functions

EXTI

STM32L1xx_StdPeriph_Driver

EXTI driver modules. More...

Data Structures

struct | EXTI_InitTypeDef
EXTI Init Structure definition. More...

Modules

EXTI_Exported_Constants
EXTI_Private_Functions

Defines

#define | EXTI_LINENONE ((uint32_t)0x00000)
#define | IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define | IS_EXTI_TRIGGER(TRIGGER)

Enumerations

enum | EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }

EXTI mode enumeration.

More...
enum | EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }

EXTI Trigger enumeration.

More...

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

EXTI driver modules.

Define Documentation

#define EXTI_LINENONE ((uint32_t)0x00000)

Definition at line 76 of file stm32l1xx_exti.c.

Referenced by EXTI_StructInit().

#define IS_EXTI_MODE ( MODE ) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))

Definition at line 57 of file stm32l1xx_exti.h.

Referenced by EXTI_Init().

#define IS_EXTI_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == EXTI_Trigger_Rising) || \
                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))

Definition at line 70 of file stm32l1xx_exti.h.

Referenced by EXTI_Init().

Enumeration Type Documentation

enum EXTIMode_TypeDef

EXTI mode enumeration.

Enumerator:
EXTI_Mode_Interrupt
EXTI_Mode_Event

Definition at line 51 of file stm32l1xx_exti.h.

enum EXTITrigger_TypeDef

EXTI Trigger enumeration.

Enumerator:
EXTI_Trigger_Rising
EXTI_Trigger_Falling
EXTI_Trigger_Rising_Falling

Definition at line 63 of file stm32l1xx_exti.h.

Function Documentation

void EXTI_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags.

Parameters:
EXTI_Line,: specifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 250 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

void EXTI_ClearITPendingBit ( uint32_t EXTI_Line )

Clears the EXTI's line pending bits.

Parameters:
EXTI_Line,: specifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 290 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

void EXTI_DeInit ( void )

Deinitializes the EXTI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 104 of file stm32l1xx_exti.c.

References EXTI.

void EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt on selected EXTI line.

Parameters:
EXTI_Line,: specifies the EXTI line on which the software interrupt will be generated. This parameter can be any combination of EXTI_Linex where x can be (0..23).
Return values:
None

Definition at line 196 of file stm32l1xx_exti.c.

References EXTI, and IS_EXTI_LINE.

FlagStatus EXTI_GetFlagStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line flag is set or not.

Parameters:
EXTI_Line,: specifies the EXTI line flag to check. This parameter can be: EXTI_Linex: External interrupt line x where x(0..23).
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 227 of file stm32l1xx_exti.c.

References EXTI, IS_GET_EXTI_LINE, RESET, and SET.

ITStatus EXTI_GetITStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line is asserted or not.

Parameters:
EXTI_Line,: specifies the EXTI line to check. This parameter can be: EXTI_Linex: External interrupt line x where x(0..23).
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 265 of file stm32l1xx_exti.c.

References EXTI, IS_GET_EXTI_LINE, RESET, and SET.

void EXTI_Init ( EXTI_InitTypeDef * EXTI_InitStruct )

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

EXTI_Line specifies the EXTI line (EXTI0....EXTI23). EXTI_Mode specifies which EXTI line is used as interrupt or an event. EXTI_Trigger selects the trigger. When the trigger occurs, interrupt pending bit will be set. EXTI_LineCmd controls (Enable/Disable) the EXTI line.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
Return values:
None

Definition at line 125 of file stm32l1xx_exti.c.

References DISABLE, EXTI, EXTI_BASE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, and IS_FUNCTIONAL_STATE.

void EXTI_StructInit ( EXTI_InitTypeDef * EXTI_InitStruct )

Fills each EXTI_InitStruct member with its reset value.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 181 of file stm32l1xx_exti.c.

References DISABLE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_LINENONE, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, and EXTI_Trigger_Falling.


STM32L1xx Standard Peripherals Firmware Library: EXTI_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

EXTI_InitTypeDef Struct Reference
EXTI

EXTI Init Structure definition. More...

#include <stm32l1xx_exti.h>

Data Fields

uint32_t EXTI_Line
FunctionalState EXTI_LineCmd
EXTIMode_TypeDef EXTI_Mode
EXTITrigger_TypeDef EXTI_Trigger

Detailed Description

EXTI Init Structure definition.

Definition at line 77 of file stm32l1xx_exti.h.

Field Documentation

uint32_t EXTI_InitTypeDef::EXTI_Line

Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of EXTI_Lines

Definition at line 79 of file stm32l1xx_exti.h.

Referenced by EXTI_Init(), and EXTI_StructInit().

FunctionalState EXTI_InitTypeDef::EXTI_LineCmd

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 88 of file stm32l1xx_exti.h.

Referenced by EXTI_Init(), and EXTI_StructInit().

EXTIMode_TypeDef EXTI_InitTypeDef::EXTI_Mode

Specifies the mode for the EXTI lines. This parameter can be a value of EXTIMode_TypeDef

Definition at line 82 of file stm32l1xx_exti.h.

Referenced by EXTI_Init(), and EXTI_StructInit().

EXTITrigger_TypeDef EXTI_InitTypeDef::EXTI_Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of EXTITrigger_TypeDef

Definition at line 85 of file stm32l1xx_exti.h.

Referenced by EXTI_Init(), and EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_exti.h


STM32L1xx Standard Peripherals Firmware Library: FLASH_Latency

Defines

FLASH_Latency

FLASH_Exported_Constants

Defines

#define | FLASH_Latency_0 ((uint8_t)0x00)
#define | FLASH_Latency_1 ((uint8_t)0x01)
#define | IS_FLASH_LATENCY(LATENCY)

Define Documentation

#define FLASH_Latency_0 ((uint8_t)0x00)

FLASH Zero Latency cycle

Definition at line 68 of file stm32l1xx_flash.h.

#define FLASH_Latency_1 ((uint8_t)0x01)

FLASH One Latency cycle

Definition at line 69 of file stm32l1xx_flash.h.

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_Latency_0) || \
                                   ((LATENCY) == FLASH_Latency_1))

Definition at line 71 of file stm32l1xx_flash.h.

Referenced by FLASH_SetLatency().


STM32L1xx Standard Peripherals Firmware Library: FLASH_Interrupts

Defines

FLASH_Interrupts

FLASH_Exported_Constants

Defines

#define | FLASH_IT_EOP FLASH_PECR_EOPIE
#define | FLASH_IT_ERR FLASH_PECR_ERRIE
#define | IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))

Define Documentation

#define FLASH_IT_EOP FLASH_PECR_EOPIE

End of programming interrupt source

Definition at line 81 of file stm32l1xx_flash.h.

#define FLASH_IT_ERR FLASH_PECR_ERRIE

Error interrupt source

Definition at line 82 of file stm32l1xx_flash.h.

#define IS_FLASH_IT ( IT ) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))

Definition at line 83 of file stm32l1xx_flash.h.

Referenced by FLASH_ITConfig().


STM32L1xx Standard Peripherals Firmware Library: FLASH_Address

Defines

FLASH_Address

FLASH_Exported_Constants

Defines

#define | IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))

Define Documentation

#define IS_FLASH_DATA_ADDRESS ( ADDRESS ) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))

Definition at line 92 of file stm32l1xx_flash.h.

Referenced by DATA_EEPROM_EraseByte(), DATA_EEPROM_EraseHalfWord(), DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), DATA_EEPROM_ProgramByte(), DATA_EEPROM_ProgramHalfWord(), and DATA_EEPROM_ProgramWord().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS ) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))

Definition at line 93 of file stm32l1xx_flash.h.

Referenced by FLASH_ErasePage(), and FLASH_FastProgramWord().


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_Write_Protection

Defines

Option_Bytes_Write_Protection

FLASH_Exported_Constants

Defines

#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
#define | OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000)
#define | OB_WRP1_Pages512to527 ((uint32_t)0x00000001)
#define | OB_WRP1_Pages528to543 ((uint32_t)0x00000002)
#define | OB_WRP1_Pages544to559 ((uint32_t)0x00000004)
#define | OB_WRP1_Pages560to575 ((uint32_t)0x00000008)
#define | OB_WRP1_Pages576to591 ((uint32_t)0x00000010)
#define | OB_WRP1_Pages592to607 ((uint32_t)0x00000020)
#define | OB_WRP1_Pages608to623 ((uint32_t)0x00000040)
#define | OB_WRP1_Pages624to639 ((uint32_t)0x00000080)
#define | OB_WRP1_Pages640to655 ((uint32_t)0x00000100)
#define | OB_WRP1_Pages656to671 ((uint32_t)0x00000200)
#define | OB_WRP1_Pages672to687 ((uint32_t)0x00000400)
#define | OB_WRP1_Pages688to703 ((uint32_t)0x00000800)
#define | OB_WRP1_Pages704to719 ((uint32_t)0x00001000)
#define | OB_WRP1_Pages720to735 ((uint32_t)0x00002000)
#define | OB_WRP1_Pages736to751 ((uint32_t)0x00004000)
#define | OB_WRP1_Pages752to767 ((uint32_t)0x00008000)
#define | OB_WRP1_Pages768to783 ((uint32_t)0x00010000)
#define | OB_WRP1_Pages784to799 ((uint32_t)0x00020000)
#define | OB_WRP1_Pages800to815 ((uint32_t)0x00040000)
#define | OB_WRP1_Pages816to831 ((uint32_t)0x00080000)
#define | OB_WRP1_Pages832to847 ((uint32_t)0x00100000)
#define | OB_WRP1_Pages848to863 ((uint32_t)0x00200000)
#define | OB_WRP1_Pages864to879 ((uint32_t)0x00400000)
#define | OB_WRP1_Pages880to895 ((uint32_t)0x00800000)
#define | OB_WRP1_Pages896to911 ((uint32_t)0x01000000)
#define | OB_WRP1_Pages912to927 ((uint32_t)0x02000000)
#define | OB_WRP1_Pages928to943 ((uint32_t)0x04000000)
#define | OB_WRP1_Pages944to959 ((uint32_t)0x08000000)
#define | OB_WRP1_Pages960to975 ((uint32_t)0x10000000)
#define | OB_WRP1_Pages976to991 ((uint32_t)0x20000000)
#define | OB_WRP1_Pages992to1007 ((uint32_t)0x40000000)
#define | OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001)
#define | OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002)
#define | OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004)
#define | OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008)
#define | OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010)
#define | OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020)
#define | OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040)
#define | OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080)
#define | OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100)
#define | OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200)
#define | OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400)
#define | OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800)
#define | OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000)
#define | OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000)
#define | OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000)
#define | OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000)
#define | OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000)
#define | OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000)
#define | OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000)
#define | OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000)
#define | OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000)
#define | OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000)
#define | OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000)
#define | OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000)
#define | OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000)
#define | OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000)
#define | OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000)
#define | OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000)
#define | OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000)
#define | OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000)
#define | OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000)
#define | OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000)
#define | OB_WRP_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP_Pages0to15 ((uint32_t)0x00000001)
#define | OB_WRP_Pages112to127 ((uint32_t)0x00000080)
#define | OB_WRP_Pages128to143 ((uint32_t)0x00000100)
#define | OB_WRP_Pages144to159 ((uint32_t)0x00000200)
#define | OB_WRP_Pages160to175 ((uint32_t)0x00000400)
#define | OB_WRP_Pages16to31 ((uint32_t)0x00000002)
#define | OB_WRP_Pages176to191 ((uint32_t)0x00000800)
#define | OB_WRP_Pages192to207 ((uint32_t)0x00001000)
#define | OB_WRP_Pages208to223 ((uint32_t)0x00002000)
#define | OB_WRP_Pages224to239 ((uint32_t)0x00004000)
#define | OB_WRP_Pages240to255 ((uint32_t)0x00008000)
#define | OB_WRP_Pages256to271 ((uint32_t)0x00010000)
#define | OB_WRP_Pages272to287 ((uint32_t)0x00020000)
#define | OB_WRP_Pages288to303 ((uint32_t)0x00040000)
#define | OB_WRP_Pages304to319 ((uint32_t)0x00080000)
#define | OB_WRP_Pages320to335 ((uint32_t)0x00100000)
#define | OB_WRP_Pages32to47 ((uint32_t)0x00000004)
#define | OB_WRP_Pages336to351 ((uint32_t)0x00200000)
#define | OB_WRP_Pages352to367 ((uint32_t)0x00400000)
#define | OB_WRP_Pages368to383 ((uint32_t)0x00800000)
#define | OB_WRP_Pages384to399 ((uint32_t)0x01000000)
#define | OB_WRP_Pages400to415 ((uint32_t)0x02000000)
#define | OB_WRP_Pages416to431 ((uint32_t)0x04000000)
#define | OB_WRP_Pages432to447 ((uint32_t)0x08000000)
#define | OB_WRP_Pages448to463 ((uint32_t)0x10000000)
#define | OB_WRP_Pages464to479 ((uint32_t)0x20000000)
#define | OB_WRP_Pages480to495 ((uint32_t)0x40000000)
#define | OB_WRP_Pages48to63 ((uint32_t)0x00000008)
#define | OB_WRP_Pages496to511 ((uint32_t)0x80000000)
#define | OB_WRP_Pages64to79 ((uint32_t)0x00000010)
#define | OB_WRP_Pages80to95 ((uint32_t)0x00000020)
#define | OB_WRP_Pages96to111 ((uint32_t)0x00000040)

Define Documentation

#define IS_OB_WRP ( PAGE ) (((PAGE) != 0x0000000))

Definition at line 208 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), and FLASH_OB_WRPConfig().

#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF)

Write protection of all Sectors

Definition at line 171 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000)

Definition at line 169 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001)

Definition at line 138 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002)

Definition at line 139 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004)

Definition at line 140 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008)

Definition at line 141 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010)

Definition at line 142 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020)

Definition at line 143 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040)

Definition at line 144 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080)

Definition at line 145 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100)

Definition at line 146 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200)

Definition at line 147 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400)

Definition at line 148 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800)

Definition at line 149 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000)

Definition at line 150 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000)

Definition at line 151 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000)

Definition at line 152 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000)

Definition at line 153 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000)

Definition at line 154 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000)

Definition at line 155 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000)

Definition at line 156 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000)

Definition at line 157 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000)

Definition at line 158 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000)

Definition at line 159 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000)

Definition at line 160 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000)

Definition at line 161 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000)

Definition at line 162 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000)

Definition at line 163 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000)

Definition at line 164 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000)

Definition at line 165 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000)

Definition at line 166 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000)

Definition at line 167 of file stm32l1xx_flash.h.

#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000)

Definition at line 168 of file stm32l1xx_flash.h.

#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF)

Write protection of all Sectors

Definition at line 206 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001)

Definition at line 173 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002)

Definition at line 174 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004)

Definition at line 175 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008)

Definition at line 176 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010)

Definition at line 177 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020)

Definition at line 178 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040)

Definition at line 179 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080)

Definition at line 180 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100)

Definition at line 181 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200)

Definition at line 182 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400)

Definition at line 183 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800)

Definition at line 184 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000)

Definition at line 185 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000)

Definition at line 186 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000)

Definition at line 187 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000)

Definition at line 188 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000)

Definition at line 189 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000)

Definition at line 190 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000)

Definition at line 191 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000)

Definition at line 192 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000)

Definition at line 193 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000)

Definition at line 194 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000)

Definition at line 195 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000)

Definition at line 196 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000)

Definition at line 197 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000)

Definition at line 198 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000)

Definition at line 199 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000)

Definition at line 200 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000)

Definition at line 201 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000)

Definition at line 202 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000)

Definition at line 203 of file stm32l1xx_flash.h.

#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000)

Definition at line 204 of file stm32l1xx_flash.h.

#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF)

Write protection of all Sectors

Definition at line 136 of file stm32l1xx_flash.h.

#define OB_WRP_Pages0to15 ((uint32_t)0x00000001)

Definition at line 103 of file stm32l1xx_flash.h.

#define OB_WRP_Pages112to127 ((uint32_t)0x00000080)

Definition at line 110 of file stm32l1xx_flash.h.

#define OB_WRP_Pages128to143 ((uint32_t)0x00000100)

Definition at line 111 of file stm32l1xx_flash.h.

#define OB_WRP_Pages144to159 ((uint32_t)0x00000200)

Definition at line 112 of file stm32l1xx_flash.h.

#define OB_WRP_Pages160to175 ((uint32_t)0x00000400)

Definition at line 113 of file stm32l1xx_flash.h.

#define OB_WRP_Pages16to31 ((uint32_t)0x00000002)

Definition at line 104 of file stm32l1xx_flash.h.

#define OB_WRP_Pages176to191 ((uint32_t)0x00000800)

Definition at line 114 of file stm32l1xx_flash.h.

#define OB_WRP_Pages192to207 ((uint32_t)0x00001000)

Definition at line 115 of file stm32l1xx_flash.h.

#define OB_WRP_Pages208to223 ((uint32_t)0x00002000)

Definition at line 116 of file stm32l1xx_flash.h.

#define OB_WRP_Pages224to239 ((uint32_t)0x00004000)

Definition at line 117 of file stm32l1xx_flash.h.

#define OB_WRP_Pages240to255 ((uint32_t)0x00008000)

Definition at line 118 of file stm32l1xx_flash.h.

#define OB_WRP_Pages256to271 ((uint32_t)0x00010000)

Definition at line 119 of file stm32l1xx_flash.h.

#define OB_WRP_Pages272to287 ((uint32_t)0x00020000)

Definition at line 120 of file stm32l1xx_flash.h.

#define OB_WRP_Pages288to303 ((uint32_t)0x00040000)

Definition at line 121 of file stm32l1xx_flash.h.

#define OB_WRP_Pages304to319 ((uint32_t)0x00080000)

Definition at line 122 of file stm32l1xx_flash.h.

#define OB_WRP_Pages320to335 ((uint32_t)0x00100000)

Definition at line 123 of file stm32l1xx_flash.h.

#define OB_WRP_Pages32to47 ((uint32_t)0x00000004)

Definition at line 105 of file stm32l1xx_flash.h.

#define OB_WRP_Pages336to351 ((uint32_t)0x00200000)

Definition at line 124 of file stm32l1xx_flash.h.

#define OB_WRP_Pages352to367 ((uint32_t)0x00400000)

Definition at line 125 of file stm32l1xx_flash.h.

#define OB_WRP_Pages368to383 ((uint32_t)0x00800000)

Definition at line 126 of file stm32l1xx_flash.h.

#define OB_WRP_Pages384to399 ((uint32_t)0x01000000)

Definition at line 127 of file stm32l1xx_flash.h.

#define OB_WRP_Pages400to415 ((uint32_t)0x02000000)

Definition at line 128 of file stm32l1xx_flash.h.

#define OB_WRP_Pages416to431 ((uint32_t)0x04000000)

Definition at line 129 of file stm32l1xx_flash.h.

#define OB_WRP_Pages432to447 ((uint32_t)0x08000000)

Definition at line 130 of file stm32l1xx_flash.h.

#define OB_WRP_Pages448to463 ((uint32_t)0x10000000)

Definition at line 131 of file stm32l1xx_flash.h.

#define OB_WRP_Pages464to479 ((uint32_t)0x20000000)

Definition at line 132 of file stm32l1xx_flash.h.

#define OB_WRP_Pages480to495 ((uint32_t)0x40000000)

Definition at line 133 of file stm32l1xx_flash.h.

#define OB_WRP_Pages48to63 ((uint32_t)0x00000008)

Definition at line 106 of file stm32l1xx_flash.h.

#define OB_WRP_Pages496to511 ((uint32_t)0x80000000)

Definition at line 134 of file stm32l1xx_flash.h.

#define OB_WRP_Pages64to79 ((uint32_t)0x00000010)

Definition at line 107 of file stm32l1xx_flash.h.

#define OB_WRP_Pages80to95 ((uint32_t)0x00000020)

Definition at line 108 of file stm32l1xx_flash.h.

#define OB_WRP_Pages96to111 ((uint32_t)0x00000040)

Definition at line 109 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_Read_Protection

Defines

Option_Bytes_Read_Protection

FLASH_Exported_Constants

Defines

#define | IS_OB_RDP(LEVEL)
#define | OB_RDP_Level_0 ((uint8_t)0xAA)
Read Protection Level.
#define | OB_RDP_Level_1 ((uint8_t)0xBB)

Define Documentation

#define IS_OB_RDP ( LEVEL )
Value:
(((LEVEL) == OB_RDP_Level_0)||\
                          ((LEVEL) == OB_RDP_Level_1))

Definition at line 226 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_RDPConfig().

#define OB_RDP_Level_0 ((uint8_t)0xAA)

Read Protection Level.

Definition at line 221 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_Level_1 ((uint8_t)0xBB)

Definition at line 222 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_IWatchdog

Defines

Option_Bytes_IWatchdog

FLASH_Exported_Constants

Defines

#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | OB_IWDG_HW ((uint8_t)0x00)
#define | OB_IWDG_SW ((uint8_t)0x10)

Define Documentation

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 239 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_IWDG_HW ((uint8_t)0x00)

Hardware WDG selected

Definition at line 238 of file stm32l1xx_flash.h.

#define OB_IWDG_SW ((uint8_t)0x10)

Software WDG selected

Definition at line 237 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_nRST_STOP

Defines

Option_Bytes_nRST_STOP

FLASH_Exported_Constants

Defines

#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
#define | OB_STOP_NoRST ((uint8_t)0x20)
#define | OB_STOP_RST ((uint8_t)0x00)

Define Documentation

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))

Definition at line 251 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STOP_NoRST ((uint8_t)0x20)

No reset generated when entering in STOP

Definition at line 249 of file stm32l1xx_flash.h.

#define OB_STOP_RST ((uint8_t)0x00)

Reset generated when entering in STOP

Definition at line 250 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_nRST_STDBY

Defines

Option_Bytes_nRST_STDBY

FLASH_Exported_Constants

Defines

#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#define | OB_STDBY_NoRST ((uint8_t)0x40)
#define | OB_STDBY_RST ((uint8_t)0x00)

Define Documentation

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 263 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STDBY_NoRST ((uint8_t)0x40)

No reset generated when entering in STANDBY

Definition at line 261 of file stm32l1xx_flash.h.

#define OB_STDBY_RST ((uint8_t)0x00)

Reset generated when entering in STANDBY

Definition at line 262 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_BOOT

Defines

Option_Bytes_BOOT

FLASH_Exported_Constants

Defines

#define | IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
#define | OB_BOOT_BANK1 ((uint8_t)0x80)
#define | OB_BOOT_BANK2 ((uint8_t)0x00)

Define Documentation

#define IS_OB_BOOT_BANK ( BANK ) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))

Definition at line 278 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_BootConfig().

#define OB_BOOT_BANK1 ((uint8_t)0x80)

At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default)

Definition at line 276 of file stm32l1xx_flash.h.

#define OB_BOOT_BANK2 ((uint8_t)0x00)

At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank 2 or Bank 1, depending on the activation of the bank

Definition at line 273 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: Option_Bytes_BOR_Level

Defines

Option_Bytes_BOR_Level

FLASH_Exported_Constants

Defines

#define | IS_OB_BOR_LEVEL(LEVEL)
#define | OB_BOR_LEVEL1 ((uint8_t)0x08)
#define | OB_BOR_LEVEL2 ((uint8_t)0x09)
#define | OB_BOR_LEVEL3 ((uint8_t)0x0A)
#define | OB_BOR_LEVEL4 ((uint8_t)0x0B)
#define | OB_BOR_LEVEL5 ((uint8_t)0x0C)
#define | OB_BOR_OFF ((uint8_t)0x00)

Define Documentation

#define IS_OB_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_OFF) || \
                                 ((LEVEL) == OB_BOR_LEVEL1) || \
                                 ((LEVEL) == OB_BOR_LEVEL2) || \
                                 ((LEVEL) == OB_BOR_LEVEL3) || \
                                 ((LEVEL) == OB_BOR_LEVEL4) || \
                                 ((LEVEL) == OB_BOR_LEVEL5))

Definition at line 296 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_BORConfig().

#define OB_BOR_LEVEL1 ((uint8_t)0x08)

BOR Reset threshold levels for 1.7V - 1.8V VDD power supply

Definition at line 290 of file stm32l1xx_flash.h.

#define OB_BOR_LEVEL2 ((uint8_t)0x09)

BOR Reset threshold levels for 1.9V - 2.0V VDD power supply

Definition at line 291 of file stm32l1xx_flash.h.

#define OB_BOR_LEVEL3 ((uint8_t)0x0A)

BOR Reset threshold levels for 2.3V - 2.4V VDD power supply

Definition at line 292 of file stm32l1xx_flash.h.

#define OB_BOR_LEVEL4 ((uint8_t)0x0B)

BOR Reset threshold levels for 2.55V - 2.65V VDD power supply

Definition at line 293 of file stm32l1xx_flash.h.

#define OB_BOR_LEVEL5 ((uint8_t)0x0C)

BOR Reset threshold levels for 2.8V - 2.9V VDD power supply

Definition at line 294 of file stm32l1xx_flash.h.

#define OB_BOR_OFF ((uint8_t)0x00)

BOR is disabled at power down, the reset is asserted when the VDD power supply reaches the PDR(Power Down Reset) threshold (1.5V)

Definition at line 288 of file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: FLASH_Flags

Defines

FLASH_Flags

FLASH_Exported_Constants

Defines

#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ENDHV FLASH_SR_ENHV
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_READY FLASH_SR_READY
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FLASH_GET_FLAG(FLAG)

Define Documentation

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 311 of file stm32l1xx_flash.h.

Referenced by FLASH_GetStatus(), and GetStatus().

#define FLASH_FLAG_ENDHV FLASH_SR_ENHV

FLASH End of High Voltage flag

Definition at line 313 of file stm32l1xx_flash.h.

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of Programming flag

Definition at line 312 of file stm32l1xx_flash.h.

#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR

FLASH Option Validity error flag

Definition at line 318 of file stm32l1xx_flash.h.

#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR

FLASH Option User Validity error flag

Definition at line 319 of file stm32l1xx_flash.h.

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming Alignment error flag

Definition at line 316 of file stm32l1xx_flash.h.

#define FLASH_FLAG_READY FLASH_SR_READY

FLASH Ready flag after low power mode

Definition at line 314 of file stm32l1xx_flash.h.

#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR

FLASH Size error flag

Definition at line 317 of file stm32l1xx_flash.h.

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protected error flag

Definition at line 315 of file stm32l1xx_flash.h.

Referenced by FLASH_GetStatus(), and GetStatus().

#define IS_FLASH_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))

Definition at line 321 of file stm32l1xx_flash.h.

Referenced by FLASH_ClearFlag().

#define IS_FLASH_GET_FLAG ( FLAG )
Value:
(((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
                                  ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
                                  ((FLAG) ==  FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
                                  ((FLAG) ==  FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
                                  ((FLAG) ==  FLASH_FLAG_OPTVERRUSR))

Definition at line 323 of file stm32l1xx_flash.h.

Referenced by FLASH_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: FLASH_Keys

Defines

FLASH_Keys

FLASH_Exported_Constants

Defines

#define | FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8)
#define | FLASH_OPTKEY2 ((uint32_t)0x24252627)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637)
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD)
#define | FLASH_PEKEY1 ((uint32_t)0x89ABCDEF)
#define | FLASH_PEKEY2 ((uint32_t)0x02030405)
#define | FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF)
#define | FLASH_PRGKEY2 ((uint32_t)0x13141516)

Define Documentation

#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8)

Flash option key1

Definition at line 349 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_Unlock().

#define FLASH_OPTKEY2 ((uint32_t)0x24252627)

Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block

Definition at line 350 of file stm32l1xx_flash.h.

Referenced by FLASH_OB_Unlock().

#define FLASH_PDKEY1 ((uint32_t)0x04152637)

Flash power down key1

Definition at line 336 of file stm32l1xx_flash.h.

Referenced by FLASH_RUNPowerDownCmd().

#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD)

Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR

Definition at line 337 of file stm32l1xx_flash.h.

Referenced by FLASH_RUNPowerDownCmd().

#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF)

Flash program erase key1

Definition at line 340 of file stm32l1xx_flash.h.

Referenced by DATA_EEPROM_Unlock().

#define FLASH_PEKEY2 ((uint32_t)0x02030405)

Flash program erase key: used with FLASH_PEKEY2 to unlock the write access to the FLASH_PECR register and data EEPROM

Definition at line 341 of file stm32l1xx_flash.h.

Referenced by DATA_EEPROM_Unlock().

#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF)

Flash program memory key1

Definition at line 345 of file stm32l1xx_flash.h.

Referenced by FLASH_Unlock().

#define FLASH_PRGKEY2 ((uint32_t)0x13141516)

Flash program memory key2: used with FLASH_PRGKEY2 to unlock the program memory

Definition at line 346 of file stm32l1xx_flash.h.

Referenced by FLASH_Unlock().


STM32L1xx Standard Peripherals Firmware Library: Timeout_definition

Defines

Timeout_definition

FLASH_Exported_Constants

Defines

#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)

Define Documentation

#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)

Definition at line 359 of file stm32l1xx_flash.h.

Referenced by DATA_EEPROM_EraseByte(), DATA_EEPROM_EraseDoubleWord(), DATA_EEPROM_EraseHalfWord(), DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), DATA_EEPROM_ProgramByte(), DATA_EEPROM_ProgramDoubleWord(), DATA_EEPROM_ProgramHalfWord(), DATA_EEPROM_ProgramWord(), FLASH_ErasePage(), FLASH_EraseParallelPage(), FLASH_FastProgramWord(), FLASH_OB_BootConfig(), FLASH_OB_BORConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), FLASH_OB_WRPConfig(), FLASH_ProgramHalfPage(), and FLASH_ProgramParallelHalfPage().


STM32L1xx Standard Peripherals Firmware Library: CMSIS_Legacy

CMSIS_Legacy

FLASH_Exported_Constants


STM32L1xx Standard Peripherals Firmware Library: FLASH Interface configuration functions

Functions

FLASH Interface configuration functions

FLASH_Private_Functions

FLASH Interface configuration functions. More...

Functions

void | FLASH_PrefetchBufferCmd (FunctionalState NewState)
Enables or disables the Prefetch Buffer.
void | FLASH_ReadAccess64Cmd (FunctionalState NewState)
Enables or disables read access to flash by 64 bits.
__RAM_FUNC | FLASH_RUNPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during RUN mode.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_SLEEPPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during Sleep mode.

Detailed Description

FLASH Interface configuration functions.

  ==============================================================================
             ##### FLASH Interface configuration functions #####
  ==============================================================================

    [..] FLASH_Interface configuration_Functions, includes the following functions:
     (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
    [..] To correctly read data from Flash memory, the number of wait states (LATENCY)
         must be correctly programmed according to the frequency of the CPU clock
        (HCLK) and the supply voltage of the device.
  [..]
  ----------------------------------------------------------------
 |  Wait states  |                HCLK clock frequency (MHz)      |
 |               |------------------------------------------------|
 |   (Latency)   |            voltage range       | voltage range |
 |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
 |               |----------------|---------------|---------------|
 |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
 |-------------- |----------------|---------------|---------------|
 |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
 |---------------|----------------|---------------|---------------|
 |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
  ----------------------------------------------------------------
  [..]
     (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
     (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState);
     (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState);
     (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
     (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
  [..]
  Here below the allowed configuration of Latency, 64Bit access and prefetch buffer
  [..]
  --------------------------------------------------------------------------------
 |               |              ACC64 = 0         |              ACC64 = 1        |
 |   Latency     |----------------|---------------|---------------|---------------|
 |               |   PRFTEN = 0   |   PRFTEN = 1  |   PRFTEN = 0  |   PRFTEN = 1  |
 |---------------|----------------|---------------|---------------|---------------|
 |0WS(1CPU cycle)|     YES        |     NO        |     YES       |     YES       |
 |---------------|----------------|---------------|---------------|---------------|
 |1WS(2CPU cycle)|     NO         |     NO        |     YES       |     YES       |
  --------------------------------------------------------------------------------
  [..]
   All these functions don't need the unlock sequence.

Function Documentation

          void FLASH_PrefetchBufferCmd
          (
          FunctionalState
          NewState )

Enables or disables the Prefetch Buffer.

Parameters:

NewState,: new state of the FLASH prefetch buffer. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 207 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_PRFTEN, and IS_FUNCTIONAL_STATE.

          void FLASH_ReadAccess64Cmd
          (
          FunctionalState
          NewState )

Enables or disables read access to flash by 64 bits.

Parameters:

NewState,: new state of the FLASH read access mode. This parameter can be: ENABLE or DISABLE.

Note:
If this bit is set, the Read access 64 bit is used. If this bit is reset, the Read access 32 bit is used.

This bit cannot be written at the same time as the LATENCY and PRFTEN bits. To reset this bit, the LATENCY should be zero wait state and the prefetch off.

Return values:

None

Definition at line 234 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_ACC64, and IS_FUNCTIONAL_STATE.

          __RAM_FUNC FLASH_RUNPowerDownCmd
          (
          FunctionalState
          NewState )

Enable or disable the power down mode during RUN mode.

FLASH memory functions that should be executed from internal SRAM.

Note:
This function can be used only when the user code is running from Internal SRAM.

Parameters:

NewState,: new state of the power down mode during RUN mode. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 99 of file stm32l1xx_flash_ramfunc.c.

References DISABLE, FLASH, FLASH_ACR_RUN_PD, FLASH_COMPLETE, FLASH_ERROR_PROGRAM, FLASH_PDKEY1, and FLASH_PDKEY2.

          void FLASH_SetLatency
          (
          uint32_t
          FLASH_Latency )

Sets the code latency value.

FLASH memory functions that can be executed from FLASH.

Parameters:

FLASH_Latency,: specifies the FLASH Latency value. This parameter can be one of the following values:

  • FLASH_Latency_0: FLASH Zero Latency cycle.
    •

  • FLASH_Latency_1: FLASH One Latency cycle.
    •

Return values:

None

Definition at line 183 of file stm32l1xx_flash.c.

References FLASH, FLASH_ACR_LATENCY, and IS_FLASH_LATENCY.

          void FLASH_SLEEPPowerDownCmd
          (
          FunctionalState
          NewState )

Enable or disable the power down mode during Sleep mode.

Note:
This function is used to power down the FLASH when the system is in SLEEP LP mode.

Parameters:

NewState,: new state of the power down mode during sleep mode. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 256 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_SLEEP_PD, and IS_FUNCTIONAL_STATE.

STM32L1xx Standard Peripherals Library: Footer

      For complete
documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: FLASH Memory Programming functions

Functions

FLASH Memory Programming functions

FLASH_Private_Functions

FLASH Memory Programming functions. More...

Functions

FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified page in program memory.
FLASH_Status | FLASH_EraseParallelPage (uint32_t Page_Address1, uint32_t Page_Address2)
Erases a specified 2 page in program memory in parallel.
FLASH_Status | FLASH_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in program memory.
void | FLASH_Lock (void)
Locks the Program memory access.
__RAM_FUNC | FLASH_ProgramHalfPage (uint32_t Address, uint32_t *pBuffer)
Programs a half page in program memory.
__RAM_FUNC | FLASH_ProgramParallelHalfPage (uint32_t Address1, uint32_t *pBuffer1, uint32_t Address2, uint32_t *pBuffer2)
Programs 2 half page in program memory in parallel.
void | FLASH_Unlock (void)
Unlocks the FLASH control register and program memory access.

Detailed Description

FLASH Memory Programming functions.

  ==============================================================================
                ##### FLASH Memory Programming functions #####
  ==============================================================================

    [..] The FLASH Memory Programming functions, includes the following functions:
    (+) void FLASH_Unlock(void);
    (+) void FLASH_Lock(void);
    (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
    (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);

    [..] Any operation of erase or program should follow these steps:
    (#) Call the FLASH_Unlock() function to enable the flash control register and
        program memory access.
    (#) Call the desired function to erase page or program data.
    (#) Call the FLASH_Lock() to disable the flash program memory access
       (recommended to protect the FLASH memory against possible unwanted operation).

Function Documentation

          FLASH_Status FLASH_ErasePage
          (
          uint32_t
          Page_Address )

Erases a specified page in program memory.

Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)

Parameters:

Page_Address,: The page address in program memory to be erased.

Note:
A Page is erased in the Program memory only if the address to load is the start address of a page (multiple of 256 bytes).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 343 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_ERASE, FLASH_PECR_PROG, FLASH_WaitForLastOperation(), and IS_FLASH_PROGRAM_ADDRESS.

FLASH_Status FLASH_EraseParallelPage | ( | uint32_t | Page_Address1,
 |  | uint32_t | Page_Address2
 | ) |  |

Erases a specified 2 page in program memory in parallel.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).

Parameters:

Page_Address1,: The page address in program memory to be erased in the first Bank (BANK1). This parameter should be between 0x08000000 and 0x0802FF00.

Page_Address2,: The page address in program memory to be erased in the second Bank (BANK2). This parameter should be between 0x08030000 and 0x0805FF00.

Note:
A Page is erased in the Program memory only if the address to load is the start address of a page (multiple of 256 bytes).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 156 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_ERASE, FLASH_PECR_PARALLBANK, FLASH_PECR_PROG, and WaitForLastOperation().

FLASH_Status FLASH_FastProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in program memory.

Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 388 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_PROGRAM_ADDRESS.

          void FLASH_Lock
          (
          void
           )

Locks the Program memory access.

Parameters:

None

Return values:

None

Definition at line 325 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_PRGLOCK.

__RAM_FUNC FLASH_ProgramHalfPage | ( | uint32_t | Address,
 |  | uint32_t * | pBuffer
 | ) |  |

Programs a half page in program memory.

Parameters:

Address,: specifies the address to be written.

pBuffer,: pointer to the buffer containing the data to be written to the half page.

Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)

Half page write is possible only from SRAM.

If there are more than 32 words to write, after 32 words another Half Page programming operation starts and has to be finished.

A half page is written to the program memory only if the first address to load is the start address of a half page (multiple of 128 bytes) and the 31 remaining words to load are in the same half page.

During the Program memory half page write all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).

If a PGAERR is set during a Program memory half page write, the complete write operation is aborted. Software should then reset the FPRG and PROG/DATA bits and restart the write operation from the beginning.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 218 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FPRG, FLASH_PECR_PROG, and WaitForLastOperation().

__RAM_FUNC FLASH_ProgramParallelHalfPage | ( | uint32_t | Address1,
 |  | uint32_t * | pBuffer1,
 |  | uint32_t | Address2,
 |  | uint32_t * | pBuffer2
 | ) |  |

Programs 2 half page in program memory in parallel.

Parameters:

Address1,: specifies the first address to be written in the first bank (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.

pBuffer1,: pointer to the buffer containing the data to be written to the first half page in the first bank.

Address2,: specifies the second address to be written in the second bank (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.

pBuffer2,: pointer to the buffer containing the data to be written to the second half page in the second bank.

Note:
This function can be used only for STM32L1XX_HD density devices.

To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).

Half page write is possible only from SRAM.

If there are more than 32 words to write, after 32 words another Half Page programming operation starts and has to be finished.

A half page is written to the program memory only if the first address to load is the start address of a half page (multiple of 128 bytes) and the 31 remaining words to load are in the same half page.

During the Program memory half page write all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).

If a PGAERR is set during a Program memory half page write, the complete write operation is aborted. Software should then reset the FPRG and PROG/DATA bits and restart the write operation from the beginning.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 290 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FPRG, FLASH_PECR_PARALLBANK, FLASH_PECR_PROG, and WaitForLastOperation().

          void FLASH_Unlock
          (
          void
           )

Unlocks the FLASH control register and program memory access.

Parameters:

None

Return values:

None

Definition at line 307 of file stm32l1xx_flash.c.

References DATA_EEPROM_Unlock(), FLASH, FLASH_PECR_PRGLOCK, FLASH_PRGKEY1, FLASH_PRGKEY2, and RESET.

STM32L1xx Standard Peripherals Library: Footer

      For complete
documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: DATA EEPROM Programming functions

Functions

DATA EEPROM Programming functions

FLASH_Private_Functions

DATA EEPROM Programming functions. More...

Functions

FLASH_Status | DATA_EEPROM_EraseByte (uint32_t Address)
Erase a byte in data memory.
__RAM_FUNC | DATA_EEPROM_EraseDoubleWord (uint32_t Address)
Erase a double word in data memory.
FLASH_Status | DATA_EEPROM_EraseHalfWord (uint32_t Address)
Erase a halfword in data memory.
FLASH_Status | DATA_EEPROM_EraseWord (uint32_t Address)
Erase a word in data memory.
FLASH_Status | DATA_EEPROM_FastProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory.
void | DATA_EEPROM_FixedTimeProgramCmd (FunctionalState NewState)
Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
void | DATA_EEPROM_Lock (void)
Locks the Data memory and FLASH_PECR register access.
FLASH_Status | DATA_EEPROM_ProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory without erase.
__RAM_FUNC | DATA_EEPROM_ProgramDoubleWord (uint32_t Address, uint64_t Data)
Write a double word in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory without erase.
void | DATA_EEPROM_Unlock (void)
Unlocks the data memory and FLASH_PECR register access.

Detailed Description

DATA EEPROM Programming functions.

 ===============================================================================
                     ##### DATA EEPROM Programming functions #####
 ===============================================================================

    [..] The DATA_EEPROM Programming_Functions, includes the following functions:
        (+) void DATA_EEPROM_Unlock(void);
        (+) void DATA_EEPROM_Lock(void);
        (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
        (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
        (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
        (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
        (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
        (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
        (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
        (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
        (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);

    [..] Any operation of erase or program should follow these steps:
    (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access
        and Flash program erase control register access.
    (#) Call the desired function to erase or program data.
    (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access
        and Flash program erase control register access(recommended
        to protect the DATA_EEPROM against possible unwanted operation).

Function Documentation

          FLASH_Status DATA_EEPROM_EraseByte
          (
          uint32_t
          Address )

Erase a byte in data memory.

Parameters:

Address,: specifies the address to be erased.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.

To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 507 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

          __RAM_FUNC DATA_EEPROM_EraseDoubleWord
          (
          uint32_t
          Address )

Erase a double word in data memory.

Parameters:

Address,: specifies the address to be erased.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Data memory double word erase is possible only from SRAM.

A double word is erased to the data memory only if the first address to load is the start address of a double word (multiple of 8 bytes).

During the Data memory double word erase, all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 369 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_DATA, FLASH_PECR_ERASE, and WaitForLastOperation().

          FLASH_Status DATA_EEPROM_EraseHalfWord
          (
          uint32_t
          Address )

Erase a halfword in data memory.

Parameters:

Address,: specifies the address to be erased.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.

To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 540 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

          FLASH_Status DATA_EEPROM_EraseWord
          (
          uint32_t
          Address )

Erase a word in data memory.

Parameters:

Address,: specifies the address to be erased.

Note:
For STM32L1XX_MD, A data memory word is erased in the data memory only if the address to load is the start address of a word (multiple of a word).

To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 573 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte(), and DATA_EEPROM_ProgramHalfWord().

FLASH_Status DATA_EEPROM_FastProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Write a Byte at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Note:
This function assumes that the is data word is already erased.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 606 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramWord(), FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramHalfWord(), and DATA_EEPROM_ProgramHalfWord().

FLASH_Status DATA_EEPROM_FastProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Writes a half word at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Note:
This function assumes that the is data word is already erased.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 667 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramWord(), FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

FLASH_Status DATA_EEPROM_FastProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to the data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Note:
This function assumes that the is data word is already erased.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 736 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte(), and DATA_EEPROM_ProgramHalfWord().

          void DATA_EEPROM_FixedTimeProgramCmd
          (
          FunctionalState
          NewState )

Enables or disables DATA EEPROM fixed Time programming (2*Tprog).

Parameters:

NewState,: new state of the DATA EEPROM fixed Time programming mode. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 479 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_PECR_FTDW, and IS_FUNCTIONAL_STATE.

          void DATA_EEPROM_Lock
          (
          void
           )

Locks the Data memory and FLASH_PECR register access.

Parameters:

None

Return values:

None

Definition at line 467 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_PELOCK.

FLASH_Status DATA_EEPROM_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Write a Byte at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming.

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 775 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramWord(), FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

__RAM_FUNC DATA_EEPROM_ProgramDoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Write a double word in data memory without erase.

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

Data memory double word write is possible only from SRAM.

A data memory double word is written to the data memory only if the first address to load is the start address of a double word (multiple of double word).

During the Data memory double word write, all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 428 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_DATA, FLASH_PECR_FPRG, and WaitForLastOperation().

FLASH_Status DATA_EEPROM_ProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Writes a half word at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 833 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramWord(), FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

FLASH_Status DATA_EEPROM_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).

The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming.

Parameters:

Address,: specifies the address to be written.

Data,: specifies the data to be written.

Return values:

FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 898 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

          void DATA_EEPROM_Unlock
          (
          void
           )

Unlocks the data memory and FLASH_PECR register access.

Parameters:

None

Return values:

None

Definition at line 452 of file stm32l1xx_flash.c.

References FLASH, FLASH_PECR_PELOCK, FLASH_PEKEY1, FLASH_PEKEY2, and RESET.

Referenced by FLASH_OB_Unlock(), and FLASH_Unlock().

STM32L1xx Standard Peripherals Library: Footer

      For complete
documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: Option Bytes Programming functions

Functions

Option Bytes Programming functions

FLASH_Private_Functions

Option Bytes Programming functions. More...

Functions

FLASH_Status | FLASH_OB_BootConfig (uint8_t OB_BOOT)
Configures to boot from Bank1 or Bank2.
FLASH_Status | FLASH_OB_BORConfig (uint8_t OB_BOR)
Programs the FLASH brownout reset threshold level Option Byte.
uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
FlagStatus | FLASH_OB_GetRDP (void)
Checks whether the FLASH Read out Protection Status is set or not.
uint8_t | FLASH_OB_GetUser (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_OB_GetWRP (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP1 (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP2 (void)
Returns the FLASH Write Protection Option Bytes value.
void | FLASH_OB_Launch (void)
Launch the option byte loading.
void | FLASH_OB_Lock (void)
Locks the option bytes block access.
FLASH_Status | FLASH_OB_RDPConfig (uint8_t OB_RDP)
Enables or disables the read out protection.
void | FLASH_OB_Unlock (void)
Unlocks the option bytes block access.
FLASH_Status | FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_OB_WRP1Config (uint32_t OB_WRP1, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRP2Config (uint32_t OB_WRP2, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
Write protects the desired pages.

Detailed Description

Option Bytes Programming functions.

  ==============================================================================
                ##### Option Bytes Programming functions #####
  ==============================================================================

    [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
    (+) void FLASH_OB_Unlock(void);
    (+) void FLASH_OB_Lock(void);
    (+) void FLASH_OB_Launch(void);
    (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
    (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
    (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
    (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
    (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
    (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
    (+) uint8_t FLASH_OB_GetUser(void);
    (+) uint32_t FLASH_OB_GetWRP(void);
    (+) uint32_t FLASH_OB_GetWRP1(void);
    (+) uint32_t FLASH_OB_GetWRP2(void);
    (+) FlagStatus FLASH_OB_GetRDP(void);
    (+) uint8_t FLASH_OB_GetBOR(void);
    (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT);

    [..] Any operation of erase or program should follow these steps:
    (#) Call the FLASH_OB_Unlock() function to enable the Flash option control
        register access.
    (#) Call one or several functions to program the desired option bytes.
        (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable
             the desired sector write protection.
        (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level.
        (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure
             the user option Bytes: IWDG, STOP and the Standby.
        (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level.
        (++) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes			.
    (#) Once all needed option bytes to be programmed are correctly written, call the
        FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
    (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended
        to protect the option Bytes against possible unwanted operations).

Function Documentation

FLASH_Status FLASH_OB_BootConfig ( uint8_t OB_BOOT )

Configures to boot from Bank1 or Bank2.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_BOOT,: select the FLASH Bank to boot from. This parameter can be one of the following values:

  • OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank2 or Bank1, depending on the activation of the bank. The active banks are checked in the following order: Bank2, followed by Bank1. The active bank is recognized by the value programmed at the base address of the respective bank (corresponding to the initial stack pointer value in the interrupt vector table).
  • OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default). For more information, please refer to AN2606 from www.st.com.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1361 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_BOOT_BANK, and OB.

FLASH_Status FLASH_OB_BORConfig ( uint8_t OB_BOR )

Programs the FLASH brownout reset threshold level Option Byte.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_BOR,: Selects the brownout reset threshold level. This parameter can be one of the following values:

  • OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD power supply reaches the PDR(Power Down Reset) threshold (1.5V)
  • OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
  • OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
  • OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
  • OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
  • OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1308 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_BOR_LEVEL, and OB.

uint8_t FLASH_OB_GetBOR ( void )

Returns the FLASH BOR level.

Parameters:
None
Return values:
The FLASH User Option Bytes.

Definition at line 1464 of file stm32l1xx_flash.c.

References FLASH.

FlagStatus FLASH_OB_GetRDP ( void )

Checks whether the FLASH Read out Protection Status is set or not.

Parameters:
None
Return values:
FLASH ReadOut Protection Status(SET or RESET).

Definition at line 1444 of file stm32l1xx_flash.c.

References FLASH, OB_RDP_Level_0, RESET, and SET.

uint8_t FLASH_OB_GetUser ( void )

Returns the FLASH User Option Bytes values.

Parameters:
None
Return values:
The FLASH User Option Bytes.

Definition at line 1397 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP ( void )

Returns the FLASH Write Protection Option Bytes value.

Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1408 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP1 ( void )

Returns the FLASH Write Protection Option Bytes value.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1421 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP2 ( void )

Returns the FLASH Write Protection Option Bytes value.

Note:
This function can be used only for STM32L1XX_HD density devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1433 of file stm32l1xx_flash.c.

References FLASH.

void FLASH_OB_Launch ( void )

Launch the option byte loading.

Parameters:
None
Return values:
None

Definition at line 1003 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_OBL_LAUNCH.

void FLASH_OB_Lock ( void )

Locks the option bytes block access.

Parameters:
None
Return values:
None

Definition at line 992 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_OPTLOCK.

FLASH_Status FLASH_OB_RDPConfig ( uint8_t OB_RDP )

Enables or disables the read out protection.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
FLASH_ReadProtection_Level,: specifies the read protection level. This parameter can be:

  • OB_RDP_Level_0: No protection
  • OB_RDP_Level_1: Read protection of the memory
  • OB_RDP_Level_2: Chip protection
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1209 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_RDP, and OB.

void FLASH_OB_Unlock ( void )

Unlocks the option bytes block access.

Parameters:
None
Return values:
None

Definition at line 974 of file stm32l1xx_flash.c.

References DATA_EEPROM_Unlock(), FLASH, FLASH_OPTKEY1, FLASH_OPTKEY2, FLASH_PECR_OPTLOCK, and RESET.

FLASH_Status FLASH_OB_UserConfig | ( | uint8_t | OB_IWDG,
 |  | uint8_t | OB_STOP,
 |  | uint8_t | OB_STDBY
 | ) |  |

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_IWDG,: Selects the WDG mode. This parameter can be one of the following values:

  • OB_IWDG_SW: Software WDG selected
  • OB_IWDG_HW: Hardware WDG selected
OB_STOP,: Reset event when entering STOP mode. This parameter can be one of the following values:

  • OB_STOP_NoRST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
OB_STDBY,: Reset event when entering Standby mode. This parameter can be one of the following values:

  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1257 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, and OB.

FLASH_Status FLASH_OB_WRP1Config | ( | uint32_t | OB_WRP1,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP1,: specifies the address of the pages to be write protected. This parameter can be:

  • value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023
  • OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1087 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP45_MASK, and WRP67_MASK.

FLASH_Status FLASH_OB_WRP2Config | ( | uint32_t | OB_WRP2,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP2,: specifies the address of the pages to be write protected. This parameter can be:

  • value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535
  • OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1149 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP1011_MASK, and WRP89_MASK.

FLASH_Status FLASH_OB_WRPConfig | ( | uint32_t | OB_WRP,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP,: specifies the address of the pages to be write protected. This parameter can be:
value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511
OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1024 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP01_MASK, and WRP23_MASK.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

FLASH_Private_Functions

Interrupts and flags management functions. More...

Functions

void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Detailed Description

Interrupts and flags management functions.

  ==============================================================================
              ##### Interrupts and flags management functions #####
  ==============================================================================

Function Documentation

void FLASH_ClearFlag ( uint32_t FLASH_FLAG )

Clears the FLASH's pending flags.

Parameters:
FLASH_FLAG,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:

  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_SIZERR: FLASH size error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
Return values:
None

Definition at line 1559 of file stm32l1xx_flash.c.

References FLASH, and IS_FLASH_CLEAR_FLAG.

FlagStatus FLASH_GetFlagStatus ( uint32_t FLASH_FLAG )

Checks whether the specified FLASH flag is set or not.

Parameters:
FLASH_FLAG,: specifies the FLASH flag to check. This parameter can be one of the following values:

  • FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_READY: FLASH Ready flag after low power mode
  • FLASH_FLAG_ENDHV: FLASH End of high voltage flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_SIZERR: FLASH size error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 1528 of file stm32l1xx_flash.c.

References FLASH, IS_FLASH_GET_FLAG, RESET, and SET.

FLASH_Status FLASH_GetStatus ( void )

Returns the FLASH Status.

Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.

Definition at line 1574 of file stm32l1xx_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_FLAG_BSY, and FLASH_FLAG_WRPERR.

Referenced by FLASH_WaitForLastOperation().

void FLASH_ITConfig | ( | uint32_t | FLASH_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FLASH interrupts.

Parameters:
FLASH_IT,: specifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FLASH_IT_EOP: FLASH end of programming Interrupt
  • FLASH_IT_ERR: FLASH Error Interrupt
Return values:
None

Definition at line 1495 of file stm32l1xx_flash.c.

References DISABLE, FLASH, IS_FLASH_IT, and IS_FUNCTIONAL_STATE.

FLASH_Status FLASH_WaitForLastOperation ( uint32_t Timeout )

Waits for a FLASH operation to complete or a TIMEOUT to occur.

Parameters:
Timeout,: FLASH programming Timeout.
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1611 of file stm32l1xx_flash.c.

References FLASH_BUSY, FLASH_COMPLETE, FLASH_GetStatus(), and FLASH_TIMEOUT.

Referenced by DATA_EEPROM_EraseByte(), DATA_EEPROM_EraseHalfWord(), DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), DATA_EEPROM_ProgramByte(), DATA_EEPROM_ProgramHalfWord(), DATA_EEPROM_ProgramWord(), FLASH_ErasePage(), FLASH_FastProgramWord(), FLASH_OB_BootConfig(), FLASH_OB_BORConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), and FLASH_OB_WRPConfig().


STM32L1xx Standard Peripherals Firmware Library: FLASH_Private_Functions

Modules | Functions

FLASH_Private_Functions

FLASH

Modules

FLASH Interface configuration functions

FLASH Interface configuration functions.

FLASH Memory Programming functions

FLASH Memory Programming functions.

DATA EEPROM Programming functions

DATA EEPROM Programming functions.

Option Bytes Programming functions

Option Bytes Programming functions.

Interrupts and flags management functions

Interrupts and flags management functions.

Functions

static __RAM_FUNC | GetStatus (void)
Returns the FLASH Status.
static __RAM_FUNC | WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Function Documentation

static __RAM_FUNC GetStatus ( void ) [static]

Returns the FLASH Status.

Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE

Definition at line 475 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_FLAG_BSY, and FLASH_FLAG_WRPERR.

Referenced by WaitForLastOperation().

static __RAM_FUNC WaitForLastOperation ( uint32_t Timeout ) [static]

Waits for a FLASH operation to complete or a TIMEOUT to occur.

Parameters:
Timeout,: FLASH programming Timeout
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 512 of file stm32l1xx_flash_ramfunc.c.

References FLASH_BUSY, FLASH_COMPLETE, FLASH_TIMEOUT, and GetStatus().

Referenced by DATA_EEPROM_EraseDoubleWord(), DATA_EEPROM_ProgramDoubleWord(), FLASH_EraseParallelPage(), FLASH_ProgramHalfPage(), and FLASH_ProgramParallelHalfPage().


STM32L1xx Standard Peripherals Firmware Library: FLASH

Modules | Defines | Enumerations | Functions

FLASH

STM32L1xx_StdPeriph_Driver

FLASH driver modules. More...

Modules

FLASH_Exported_Constants
FLASH_Private_Functions

Defines

#define | WRP01_MASK ((uint32_t)0x0000FFFF)
#define | WRP1011_MASK ((uint32_t)0xFFFF0000)
#define | WRP23_MASK ((uint32_t)0xFFFF0000)
#define | WRP45_MASK ((uint32_t)0x0000FFFF)
#define | WRP67_MASK ((uint32_t)0xFFFF0000)
#define | WRP89_MASK ((uint32_t)0x0000FFFF)

Enumerations

enum FLASH_Status {
FLASH_BUSY = 1, FLASH_ERROR_WRP, FLASH_ERROR_PROGRAM, FLASH_COMPLETE,
FLASH_TIMEOUT
}

FLASH Status.

More...

Functions

FLASH_Status | DATA_EEPROM_EraseByte (uint32_t Address)
Erase a byte in data memory.
__RAM_FUNC | DATA_EEPROM_EraseDoubleWord (uint32_t Address)
Erase a double word in data memory.
FLASH_Status | DATA_EEPROM_EraseHalfWord (uint32_t Address)
Erase a halfword in data memory.
FLASH_Status | DATA_EEPROM_EraseWord (uint32_t Address)
Erase a word in data memory.
FLASH_Status | DATA_EEPROM_FastProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory.
void | DATA_EEPROM_FixedTimeProgramCmd (FunctionalState NewState)
Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
void | DATA_EEPROM_Lock (void)
Locks the Data memory and FLASH_PECR register access.
FLASH_Status | DATA_EEPROM_ProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory without erase.
__RAM_FUNC | DATA_EEPROM_ProgramDoubleWord (uint32_t Address, uint64_t Data)
Write a double word in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory without erase.
void | DATA_EEPROM_Unlock (void)
Unlocks the data memory and FLASH_PECR register access.
void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified page in program memory.
__RAM_FUNC | FLASH_EraseParallelPage (uint32_t Page_Address1, uint32_t Page_Address2)
Erases a specified 2 page in program memory in parallel.
FLASH_Status | FLASH_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in program memory.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the Program memory access.
FLASH_Status | FLASH_OB_BootConfig (uint8_t OB_BOOT)
Configures to boot from Bank1 or Bank2.
FLASH_Status | FLASH_OB_BORConfig (uint8_t OB_BOR)
Programs the FLASH brownout reset threshold level Option Byte.
uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
FlagStatus | FLASH_OB_GetRDP (void)
Checks whether the FLASH Read out Protection Status is set or not.
uint8_t | FLASH_OB_GetUser (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_OB_GetWRP (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP1 (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP2 (void)
Returns the FLASH Write Protection Option Bytes value.
void | FLASH_OB_Launch (void)
Launch the option byte loading.
void | FLASH_OB_Lock (void)
Locks the option bytes block access.
FLASH_Status | FLASH_OB_RDPConfig (uint8_t OB_RDP)
Enables or disables the read out protection.
void | FLASH_OB_Unlock (void)
Unlocks the option bytes block access.
FLASH_Status | FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_OB_WRP1Config (uint32_t OB_WRP1, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRP2Config (uint32_t OB_WRP2, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
Write protects the desired pages.
void | FLASH_PrefetchBufferCmd (FunctionalState NewState)
Enables or disables the Prefetch Buffer.
__RAM_FUNC | FLASH_ProgramHalfPage (uint32_t Address, uint32_t *pBuffer)
Programs a half page in program memory.
__RAM_FUNC | FLASH_ProgramParallelHalfPage (uint32_t Address1, uint32_t *pBuffer1, uint32_t Address2, uint32_t *pBuffer2)
Programs 2 half page in program memory in parallel.
void | FLASH_ReadAccess64Cmd (FunctionalState NewState)
Enables or disables read access to flash by 64 bits.
__RAM_FUNC | FLASH_RUNPowerDownCmd (FunctionalState NewState)
FLASH memory functions that should be executed from internal SRAM.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
FLASH memory functions that can be executed from FLASH.
void | FLASH_SLEEPPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during Sleep mode.
void | FLASH_Unlock (void)
Unlocks the FLASH control register and program memory access.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Detailed Description

FLASH driver modules.

Define Documentation

#define WRP01_MASK ((uint32_t)0x0000FFFF)

Definition at line 108 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRPConfig().

#define WRP1011_MASK ((uint32_t)0xFFFF0000)

Definition at line 113 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRP2Config().

#define WRP23_MASK ((uint32_t)0xFFFF0000)

Definition at line 109 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRPConfig().

#define WRP45_MASK ((uint32_t)0x0000FFFF)

Definition at line 110 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRP1Config().

#define WRP67_MASK ((uint32_t)0xFFFF0000)

Definition at line 111 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRP1Config().

#define WRP89_MASK ((uint32_t)0x0000FFFF)

Definition at line 112 of file stm32l1xx_flash.c.

Referenced by FLASH_OB_WRP2Config().

Enumeration Type Documentation

enum FLASH_Status

FLASH Status.

Enumerator:
FLASH_BUSY
FLASH_ERROR_WRP
FLASH_ERROR_PROGRAM
FLASH_COMPLETE
FLASH_TIMEOUT

Definition at line 50 of file stm32l1xx_flash.h.

Function Documentation

FLASH_Status DATA_EEPROM_EraseByte ( uint32_t Address )

Erase a byte in data memory.

Parameters:
Address,: specifies the address to be erased.
Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 507 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

__RAM_FUNC DATA_EEPROM_EraseDoubleWord ( uint32_t Address )

Erase a double word in data memory.

Parameters:
Address,: specifies the address to be erased.
Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Data memory double word erase is possible only from SRAM.
A double word is erased to the data memory only if the first address to load is the start address of a double word (multiple of 8 bytes).
During the Data memory double word erase, all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 369 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_DATA, FLASH_PECR_ERASE, and WaitForLastOperation().

FLASH_Status DATA_EEPROM_EraseHalfWord ( uint32_t Address )

Erase a halfword in data memory.

Parameters:
Address,: specifies the address to be erased.
Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 540 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

FLASH_Status DATA_EEPROM_EraseWord ( uint32_t Address )

Erase a word in data memory.

Parameters:
Address,: specifies the address to be erased.
Note:
For STM32L1XX_MD, A data memory word is erased in the data memory only if the address to load is the start address of a word (multiple of a word).
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 573 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte(), and DATA_EEPROM_ProgramHalfWord().

FLASH_Status DATA_EEPROM_FastProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Write a Byte at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Note:
This function assumes that the is data word is already erased.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 606 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramWord(), FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramHalfWord(), and DATA_EEPROM_ProgramHalfWord().

FLASH_Status DATA_EEPROM_FastProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Writes a half word at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Note:
This function assumes that the is data word is already erased.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 667 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramWord(), FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

FLASH_Status DATA_EEPROM_FastProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in data memory.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to the data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Note:
This function assumes that the is data word is already erased.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 736 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FTDW, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

Referenced by DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte(), and DATA_EEPROM_ProgramHalfWord().

void DATA_EEPROM_FixedTimeProgramCmd ( FunctionalState NewState )

Enables or disables DATA EEPROM fixed Time programming (2*Tprog).

Parameters:
NewState,: new state of the DATA EEPROM fixed Time programming mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 479 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_PECR_FTDW, and IS_FUNCTIONAL_STATE.

void DATA_EEPROM_Lock ( void )

Locks the Data memory and FLASH_PECR register access.

Parameters:
None
Return values:
None

Definition at line 467 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_PELOCK.

FLASH_Status DATA_EEPROM_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Write a Byte at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming.
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 775 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramWord(), FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

__RAM_FUNC DATA_EEPROM_ProgramDoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Write a double word in data memory without erase.

Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
Data memory double word write is possible only from SRAM.
A data memory double word is written to the data memory only if the first address to load is the start address of a double word (multiple of double word).
During the Data memory double word write, all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 428 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_DATA, FLASH_PECR_FPRG, and WaitForLastOperation().

FLASH_Status DATA_EEPROM_ProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Writes a half word at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 833 of file stm32l1xx_flash.c.

References DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramWord(), FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

FLASH_Status DATA_EEPROM_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in data memory without erase.

Note:
To correctly run this function, the DATA_EEPROM_Unlock() function must be called before. Call the DATA_EEPROM_Lock() to he data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation).
The function DATA_EEPROM_FixedTimeProgramCmd() can be called before this function to configure the Fixed Time Programming.
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 898 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_DATA_ADDRESS.

void DATA_EEPROM_Unlock ( void )

Unlocks the data memory and FLASH_PECR register access.

Parameters:
None
Return values:
None

Definition at line 452 of file stm32l1xx_flash.c.

References FLASH, FLASH_PECR_PELOCK, FLASH_PEKEY1, FLASH_PEKEY2, and RESET.

Referenced by FLASH_OB_Unlock(), and FLASH_Unlock().

void FLASH_ClearFlag ( uint32_t FLASH_FLAG )

Clears the FLASH's pending flags.

Parameters:
FLASH_FLAG,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:

  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_SIZERR: FLASH size error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
Return values:
None

Definition at line 1559 of file stm32l1xx_flash.c.

References FLASH, and IS_FLASH_CLEAR_FLAG.

FLASH_Status FLASH_ErasePage ( uint32_t Page_Address )

Erases a specified page in program memory.

Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Parameters:
Page_Address,: The page address in program memory to be erased.
Note:
A Page is erased in the Program memory only if the address to load is the start address of a page (multiple of 256 bytes).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 343 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_ERASE, FLASH_PECR_PROG, FLASH_WaitForLastOperation(), and IS_FLASH_PROGRAM_ADDRESS.

__RAM_FUNC FLASH_EraseParallelPage | ( | uint32_t | Page_Address1,
 |  | uint32_t | Page_Address2
 | ) |  |

Erases a specified 2 page in program memory in parallel.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
Page_Address1,: The page address in program memory to be erased in the first Bank (BANK1). This parameter should be between 0x08000000 and 0x0802FF00.
Page_Address2,: The page address in program memory to be erased in the second Bank (BANK2). This parameter should be between 0x08030000 and 0x0805FF00.
Note:
A Page is erased in the Program memory only if the address to load is the start address of a page (multiple of 256 bytes).
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 156 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_ERASE, FLASH_PECR_PARALLBANK, FLASH_PECR_PROG, and WaitForLastOperation().

FLASH_Status FLASH_FastProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address in program memory.

Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
Address,: specifies the address to be written.
Data,: specifies the data to be written.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 388 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), and IS_FLASH_PROGRAM_ADDRESS.

FlagStatus FLASH_GetFlagStatus ( uint32_t FLASH_FLAG )

Checks whether the specified FLASH flag is set or not.

Parameters:
FLASH_FLAG,: specifies the FLASH flag to check. This parameter can be one of the following values:

  • FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_READY: FLASH Ready flag after low power mode
  • FLASH_FLAG_ENDHV: FLASH End of high voltage flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_SIZERR: FLASH size error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 1528 of file stm32l1xx_flash.c.

References FLASH, IS_FLASH_GET_FLAG, RESET, and SET.

FLASH_Status FLASH_GetStatus ( void )

Returns the FLASH Status.

Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.

Definition at line 1574 of file stm32l1xx_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_FLAG_BSY, and FLASH_FLAG_WRPERR.

Referenced by FLASH_WaitForLastOperation().

void FLASH_ITConfig | ( | uint32_t | FLASH_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FLASH interrupts.

Parameters:
FLASH_IT,: specifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FLASH_IT_EOP: FLASH end of programming Interrupt
  • FLASH_IT_ERR: FLASH Error Interrupt
Return values:
None

Definition at line 1495 of file stm32l1xx_flash.c.

References DISABLE, FLASH, IS_FLASH_IT, and IS_FUNCTIONAL_STATE.

void FLASH_Lock ( void )

Locks the Program memory access.

Parameters:
None
Return values:
None

Definition at line 325 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_PRGLOCK.

FLASH_Status FLASH_OB_BootConfig ( uint8_t OB_BOOT )

Configures to boot from Bank1 or Bank2.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_BOOT,: select the FLASH Bank to boot from. This parameter can be one of the following values:

  • OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank2 or Bank1, depending on the activation of the bank. The active banks are checked in the following order: Bank2, followed by Bank1. The active bank is recognized by the value programmed at the base address of the respective bank (corresponding to the initial stack pointer value in the interrupt vector table).
  • OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default). For more information, please refer to AN2606 from www.st.com.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1361 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_BOOT_BANK, and OB.

FLASH_Status FLASH_OB_BORConfig ( uint8_t OB_BOR )

Programs the FLASH brownout reset threshold level Option Byte.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_BOR,: Selects the brownout reset threshold level. This parameter can be one of the following values:

  • OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD power supply reaches the PDR(Power Down Reset) threshold (1.5V)
  • OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
  • OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
  • OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
  • OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
  • OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1308 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_BOR_LEVEL, and OB.

uint8_t FLASH_OB_GetBOR ( void )

Returns the FLASH BOR level.

Parameters:
None
Return values:
The FLASH User Option Bytes.

Definition at line 1464 of file stm32l1xx_flash.c.

References FLASH.

FlagStatus FLASH_OB_GetRDP ( void )

Checks whether the FLASH Read out Protection Status is set or not.

Parameters:
None
Return values:
FLASH ReadOut Protection Status(SET or RESET).

Definition at line 1444 of file stm32l1xx_flash.c.

References FLASH, OB_RDP_Level_0, RESET, and SET.

uint8_t FLASH_OB_GetUser ( void )

Returns the FLASH User Option Bytes values.

Parameters:
None
Return values:
The FLASH User Option Bytes.

Definition at line 1397 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP ( void )

Returns the FLASH Write Protection Option Bytes value.

Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1408 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP1 ( void )

Returns the FLASH Write Protection Option Bytes value.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1421 of file stm32l1xx_flash.c.

References FLASH.

uint32_t FLASH_OB_GetWRP2 ( void )

Returns the FLASH Write Protection Option Bytes value.

Note:
This function can be used only for STM32L1XX_HD density devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes value.

Definition at line 1433 of file stm32l1xx_flash.c.

References FLASH.

void FLASH_OB_Launch ( void )

Launch the option byte loading.

Parameters:
None
Return values:
None

Definition at line 1003 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_OBL_LAUNCH.

void FLASH_OB_Lock ( void )

Locks the option bytes block access.

Parameters:
None
Return values:
None

Definition at line 992 of file stm32l1xx_flash.c.

References FLASH, and FLASH_PECR_OPTLOCK.

FLASH_Status FLASH_OB_RDPConfig ( uint8_t OB_RDP )

Enables or disables the read out protection.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
FLASH_ReadProtection_Level,: specifies the read protection level. This parameter can be:

  • OB_RDP_Level_0: No protection
  • OB_RDP_Level_1: Read protection of the memory
  • OB_RDP_Level_2: Chip protection
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1209 of file stm32l1xx_flash.c.

References FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_RDP, and OB.

void FLASH_OB_Unlock ( void )

Unlocks the option bytes block access.

Parameters:
None
Return values:
None

Definition at line 974 of file stm32l1xx_flash.c.

References DATA_EEPROM_Unlock(), FLASH, FLASH_OPTKEY1, FLASH_OPTKEY2, FLASH_PECR_OPTLOCK, and RESET.

FLASH_Status FLASH_OB_UserConfig | ( | uint8_t | OB_IWDG,
 |  | uint8_t | OB_STOP,
 |  | uint8_t | OB_STDBY
 | ) |  |

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_IWDG,: Selects the WDG mode. This parameter can be one of the following values:

  • OB_IWDG_SW: Software WDG selected
  • OB_IWDG_HW: Hardware WDG selected
OB_STOP,: Reset event when entering STOP mode. This parameter can be one of the following values:

  • OB_STOP_NoRST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
OB_STDBY,: Reset event when entering Standby mode. This parameter can be one of the following values:

  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1257 of file stm32l1xx_flash.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, and OB.

FLASH_Status FLASH_OB_WRP1Config | ( | uint32_t | OB_WRP1,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
This function can be used only for STM32L1XX_HD and STM32L1XX_MDP density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP1,: specifies the address of the pages to be write protected. This parameter can be:

  • value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023
  • OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1087 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP45_MASK, and WRP67_MASK.

FLASH_Status FLASH_OB_WRP2Config | ( | uint32_t | OB_WRP2,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
This function can be used only for STM32L1XX_HD density devices. To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP2,: specifies the address of the pages to be write protected. This parameter can be:

  • value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535
  • OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1149 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP1011_MASK, and WRP89_MASK.

FLASH_Status FLASH_OB_WRPConfig | ( | uint32_t | OB_WRP,
 |  | FunctionalState | NewState
 | ) |  |

Write protects the desired pages.

Note:
To correctly run this function, the FLASH_OB_Unlock() function must be called before. Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes (recommended to protect the FLASH memory against possible unwanted operation).
Parameters:
OB_WRP,: specifies the address of the pages to be write protected. This parameter can be:
value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511
OB_WRP_AllPages
NewState,: new state of the specified FLASH Pages Wtite protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1024 of file stm32l1xx_flash.c.

References DISABLE, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, IS_OB_WRP, OB, WRP01_MASK, and WRP23_MASK.

void FLASH_PrefetchBufferCmd ( FunctionalState NewState )

Enables or disables the Prefetch Buffer.

Parameters:
NewState,: new state of the FLASH prefetch buffer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 207 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_PRFTEN, and IS_FUNCTIONAL_STATE.

__RAM_FUNC FLASH_ProgramHalfPage | ( | uint32_t | Address,
 |  | uint32_t * | pBuffer
 | ) |  |

Programs a half page in program memory.

Parameters:
Address,: specifies the address to be written.
pBuffer,: pointer to the buffer containing the data to be written to the half page.
Note:
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Half page write is possible only from SRAM.
If there are more than 32 words to write, after 32 words another Half Page programming operation starts and has to be finished.
A half page is written to the program memory only if the first address to load is the start address of a half page (multiple of 128 bytes) and the 31 remaining words to load are in the same half page.
During the Program memory half page write all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).
If a PGAERR is set during a Program memory half page write, the complete write operation is aborted. Software should then reset the FPRG and PROG/DATA bits and restart the write operation from the beginning.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 218 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FPRG, FLASH_PECR_PROG, and WaitForLastOperation().

__RAM_FUNC FLASH_ProgramParallelHalfPage | ( | uint32_t | Address1,
 |  | uint32_t * | pBuffer1,
 |  | uint32_t | Address2,
 |  | uint32_t * | pBuffer2
 | ) |  |

Programs 2 half page in program memory in parallel.

Parameters:
Address1,: specifies the first address to be written in the first bank (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.
pBuffer1,: pointer to the buffer containing the data to be written to the first half page in the first bank.
Address2,: specifies the second address to be written in the second bank (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.
pBuffer2,: pointer to the buffer containing the data to be written to the second half page in the second bank.
Note:
This function can be used only for STM32L1XX_HD density devices.
To correctly run this function, the FLASH_Unlock() function must be called before. Call the FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation).
Half page write is possible only from SRAM.
If there are more than 32 words to write, after 32 words another Half Page programming operation starts and has to be finished.
A half page is written to the program memory only if the first address to load is the start address of a half page (multiple of 128 bytes) and the 31 remaining words to load are in the same half page.
During the Program memory half page write all read operations are forbidden (this includes DMA read operations and debugger read operations such as breakpoints, periodic updates, etc.).
If a PGAERR is set during a Program memory half page write, the complete write operation is aborted. Software should then reset the FPRG and PROG/DATA bits and restart the write operation from the beginning.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 290 of file stm32l1xx_flash_ramfunc.c.

References FLASH, FLASH_COMPLETE, FLASH_ER_PRG_TIMEOUT, FLASH_PECR_FPRG, FLASH_PECR_PARALLBANK, FLASH_PECR_PROG, and WaitForLastOperation().

void FLASH_ReadAccess64Cmd ( FunctionalState NewState )

Enables or disables read access to flash by 64 bits.

Parameters:
NewState,: new state of the FLASH read access mode. This parameter can be: ENABLE or DISABLE.
Note:
If this bit is set, the Read access 64 bit is used. If this bit is reset, the Read access 32 bit is used.
This bit cannot be written at the same time as the LATENCY and PRFTEN bits. To reset this bit, the LATENCY should be zero wait state and the prefetch off.
Return values:
None

Definition at line 234 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_ACC64, and IS_FUNCTIONAL_STATE.

__RAM_FUNC FLASH_RUNPowerDownCmd ( FunctionalState NewState )

FLASH memory functions that should be executed from internal SRAM.

These functions are defined inside the "stm32l1xx_flash_ramfunc.c" file.

FLASH memory functions that should be executed from internal SRAM.

Note:
This function can be used only when the user code is running from Internal SRAM.
Parameters:
NewState,: new state of the power down mode during RUN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 99 of file stm32l1xx_flash_ramfunc.c.

References DISABLE, FLASH, FLASH_ACR_RUN_PD, FLASH_COMPLETE, FLASH_ERROR_PROGRAM, FLASH_PDKEY1, and FLASH_PDKEY2.

void FLASH_SetLatency ( uint32_t FLASH_Latency )

FLASH memory functions that can be executed from FLASH.

FLASH memory functions that can be executed from FLASH.

Parameters:
FLASH_Latency,: specifies the FLASH Latency value. This parameter can be one of the following values:

  • FLASH_Latency_0: FLASH Zero Latency cycle.
  • FLASH_Latency_1: FLASH One Latency cycle.
Return values:
None

Definition at line 183 of file stm32l1xx_flash.c.

References FLASH, FLASH_ACR_LATENCY, and IS_FLASH_LATENCY.

void FLASH_SLEEPPowerDownCmd ( FunctionalState NewState )

Enable or disable the power down mode during Sleep mode.

Note:
This function is used to power down the FLASH when the system is in SLEEP LP mode.
Parameters:
NewState,: new state of the power down mode during sleep mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 256 of file stm32l1xx_flash.c.

References DISABLE, FLASH, FLASH_ACR_SLEEP_PD, and IS_FUNCTIONAL_STATE.

void FLASH_Unlock ( void )

Unlocks the FLASH control register and program memory access.

Parameters:
None
Return values:
None

Definition at line 307 of file stm32l1xx_flash.c.

References DATA_EEPROM_Unlock(), FLASH, FLASH_PECR_PRGLOCK, FLASH_PRGKEY1, FLASH_PRGKEY2, and RESET.

FLASH_Status FLASH_WaitForLastOperation ( uint32_t Timeout )

Waits for a FLASH operation to complete or a TIMEOUT to occur.

Parameters:
Timeout,: FLASH programming Timeout.
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1611 of file stm32l1xx_flash.c.

References FLASH_BUSY, FLASH_COMPLETE, FLASH_GetStatus(), and FLASH_TIMEOUT.

Referenced by DATA_EEPROM_EraseByte(), DATA_EEPROM_EraseHalfWord(), DATA_EEPROM_EraseWord(), DATA_EEPROM_FastProgramByte(), DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_FastProgramWord(), DATA_EEPROM_ProgramByte(), DATA_EEPROM_ProgramHalfWord(), DATA_EEPROM_ProgramWord(), FLASH_ErasePage(), FLASH_FastProgramWord(), FLASH_OB_BootConfig(), FLASH_OB_BORConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(), and FLASH_OB_WRPConfig().


STM32L1xx Standard Peripherals Firmware Library: FSMC_NORSRAM_Bank

Defines

FSMC_NORSRAM_Bank

FSMC_Exported_Constants

Defines

#define | FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define | FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define | FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define | FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define | IS_FSMC_NORSRAM_BANK(BANK)

Define Documentation

#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)

Definition at line 157 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMDeInit(), and FSMC_NORSRAMStructInit().

#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)

Definition at line 158 of file stm32l1xx_fsmc.h.

#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)

Definition at line 159 of file stm32l1xx_fsmc.h.

#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)

Definition at line 160 of file stm32l1xx_fsmc.h.

#define IS_FSMC_NORSRAM_BANK ( BANK )
Value:
(((BANK) == FSMC_Bank1_NORSRAM1) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM4))

Definition at line 162 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Data_Address_Bus_Multiplexing

Defines

FSMC_Data_Address_Bus_Multiplexing

NOR_SRAM_Controller

Defines

#define | FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define | FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define | IS_FSMC_MUX(MUX)

Define Documentation

#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)

Definition at line 178 of file stm32l1xx_fsmc.h.

#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)

Definition at line 179 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_MUX ( MUX )
Value:
(((MUX) == FSMC_DataAddressMux_Disable) || \
                          ((MUX) == FSMC_DataAddressMux_Enable))

Definition at line 180 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Memory_Type

Defines

FSMC_Memory_Type

NOR_SRAM_Controller

Defines

#define | FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define | FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define | FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define | IS_FSMC_MEMORY(MEMORY)

Define Documentation

#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)

Definition at line 193 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().

#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)

Definition at line 192 of file stm32l1xx_fsmc.h.

#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)

Definition at line 191 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_MEMORY ( MEMORY )
Value:
(((MEMORY) == FSMC_MemoryType_SRAM) || \
                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
                                ((MEMORY) == FSMC_MemoryType_NOR))

Definition at line 194 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Data_Width

Defines

FSMC_Data_Width

NOR_SRAM_Controller

Defines

#define | FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define | FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define | IS_FSMC_MEMORY_WIDTH(WIDTH)

Define Documentation

#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)

Definition at line 207 of file stm32l1xx_fsmc.h.

#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)

Definition at line 206 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_MEMORY_WIDTH ( WIDTH )
Value:
(((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))

Definition at line 208 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Burst_Access_Mode

Defines

FSMC_Burst_Access_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define | FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define | IS_FSMC_BURSTMODE(STATE)

Define Documentation

#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)

Definition at line 219 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)

Definition at line 220 of file stm32l1xx_fsmc.h.

#define IS_FSMC_BURSTMODE ( STATE )
Value:
(((STATE) == FSMC_BurstAccessMode_Disable) || \
                                  ((STATE) == FSMC_BurstAccessMode_Enable))

Definition at line 221 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_AsynchronousWait

Defines

FSMC_AsynchronousWait

NOR_SRAM_Controller

Defines

#define | FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define | FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define | IS_FSMC_ASYNWAIT(STATE)

Define Documentation

#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)

Definition at line 230 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)

Definition at line 231 of file stm32l1xx_fsmc.h.

#define IS_FSMC_ASYNWAIT ( STATE )
Value:
(((STATE) == FSMC_AsynchronousWait_Disable) || \
                                 ((STATE) == FSMC_AsynchronousWait_Enable))

Definition at line 232 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Wait_Signal_Polarity

Defines

FSMC_Wait_Signal_Polarity

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define | FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define | IS_FSMC_WAIT_POLARITY(POLARITY)

Define Documentation

#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)

Definition at line 244 of file stm32l1xx_fsmc.h.

#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)

Definition at line 243 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_WAIT_POLARITY ( POLARITY )
Value:
(((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))

Definition at line 245 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Wrap_Mode

Defines

FSMC_Wrap_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define | IS_FSMC_WRAP_MODE(MODE)

Define Documentation

#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)

Definition at line 256 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)

Definition at line 257 of file stm32l1xx_fsmc.h.

#define IS_FSMC_WRAP_MODE ( MODE )
Value:
(((MODE) == FSMC_WrapMode_Disable) || \
                                 ((MODE) == FSMC_WrapMode_Enable))

Definition at line 258 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Wait_Timing

Defines

FSMC_Wait_Timing

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define | FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define | IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)

Define Documentation

#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)

Definition at line 269 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)

Definition at line 270 of file stm32l1xx_fsmc.h.

#define IS_FSMC_WAIT_SIGNAL_ACTIVE ( ACTIVE )
Value:
(((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))

Definition at line 271 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Write_Operation

Defines

FSMC_Write_Operation

NOR_SRAM_Controller

Defines

#define | FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define | IS_FSMC_WRITE_OPERATION(OPERATION)

Define Documentation

#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)

Definition at line 282 of file stm32l1xx_fsmc.h.

#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)

Definition at line 283 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_WRITE_OPERATION ( OPERATION )
Value:
(((OPERATION) == FSMC_WriteOperation_Disable) || \
                                            ((OPERATION) == FSMC_WriteOperation_Enable))

Definition at line 284 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Wait_Signal

Defines

FSMC_Wait_Signal

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define | FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define | IS_FSMC_WAITE_SIGNAL(SIGNAL)

Define Documentation

#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)

Definition at line 295 of file stm32l1xx_fsmc.h.

#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)

Definition at line 296 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_WAITE_SIGNAL ( SIGNAL )
Value:
(((SIGNAL) == FSMC_WaitSignal_Disable) || \
                                      ((SIGNAL) == FSMC_WaitSignal_Enable))

Definition at line 297 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Extended_Mode

Defines

FSMC_Extended_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define | FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define | IS_FSMC_EXTENDED_MODE(MODE)

Define Documentation

#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)

Definition at line 307 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)

Definition at line 308 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().

#define IS_FSMC_EXTENDED_MODE ( MODE )
Value:
(((MODE) == FSMC_ExtendedMode_Disable) || \
                                     ((MODE) == FSMC_ExtendedMode_Enable))

Definition at line 310 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Write_Burst

Defines

FSMC_Write_Burst

NOR_SRAM_Controller

Defines

#define | FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define | IS_FSMC_WRITE_BURST(BURST)

Define Documentation

#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)

Definition at line 321 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)

Definition at line 322 of file stm32l1xx_fsmc.h.

#define IS_FSMC_WRITE_BURST ( BURST )
Value:
(((BURST) == FSMC_WriteBurst_Disable) || \
                                    ((BURST) == FSMC_WriteBurst_Enable))

Definition at line 323 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Address_Setup_Time

Defines

FSMC_Address_Setup_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_ADDRESS_SETUP_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 333 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Address_Hold_Time

Defines

FSMC_Address_Hold_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_ADDRESS_HOLD_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 343 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Data_Setup_Time

Defines

FSMC_Data_Setup_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))

Define Documentation

#define IS_FSMC_DATASETUP_TIME ( TIME ) (((TIME) > 0) && ((TIME) <= 0xFF))

Definition at line 353 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Bus_Turn_around_Duration

Defines

FSMC_Bus_Turn_around_Duration

NOR_SRAM_Controller

Defines

#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_TURNAROUND_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 363 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_CLK_Division

Defines

FSMC_CLK_Division

NOR_SRAM_Controller

Defines

#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)

Define Documentation

#define IS_FSMC_CLK_DIV ( DIV ) ((DIV) <= 0xF)

Definition at line 373 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Data_Latency

Defines

FSMC_Data_Latency

NOR_SRAM_Controller

Defines

#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)

Define Documentation

#define IS_FSMC_DATA_LATENCY ( LATENCY ) ((LATENCY) <= 0xF)

Definition at line 383 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: FSMC_Access_Mode

Defines

FSMC_Access_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_AccessMode_A ((uint32_t)0x00000000)
#define | FSMC_AccessMode_B ((uint32_t)0x10000000)
#define | FSMC_AccessMode_C ((uint32_t)0x20000000)
#define | FSMC_AccessMode_D ((uint32_t)0x30000000)
#define | IS_FSMC_ACCESS_MODE(MODE)

Define Documentation

#define FSMC_AccessMode_A ((uint32_t)0x00000000)

Definition at line 393 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define FSMC_AccessMode_B ((uint32_t)0x10000000)

Definition at line 394 of file stm32l1xx_fsmc.h.

#define FSMC_AccessMode_C ((uint32_t)0x20000000)

Definition at line 395 of file stm32l1xx_fsmc.h.

#define FSMC_AccessMode_D ((uint32_t)0x30000000)

Definition at line 396 of file stm32l1xx_fsmc.h.

#define IS_FSMC_ACCESS_MODE ( MODE )
Value:
(((MODE) == FSMC_AccessMode_A) || \
                                   ((MODE) == FSMC_AccessMode_B) || \
                                   ((MODE) == FSMC_AccessMode_C) || \
                                   ((MODE) == FSMC_AccessMode_D))

Definition at line 397 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32L1xx Standard Peripherals Firmware Library: NOR/SRAM Controller functions

Functions

NOR/SRAM Controller functions

FSMC_Private_Functions

NOR/SRAM Controller functions. More...

Functions

void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.

Detailed Description

NOR/SRAM Controller functions.

  ==============================================================================
                  ##### NOR-SRAM Controller functions #####
  ==============================================================================
    [..] The following sequence should be followed to configure the FSMC to
         interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
         NOR/SRAM Bank:
    (#) Enable the clock for the FSMC and associated GPIOs using the following
        functions:
        (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
        (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
    (#) FSMC pins configuration
        (++) Connect the involved FSMC pins to AF12 using the following function
             GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
        (++) Configure these FSMC pins in alternate function mode by calling the
             function GPIO_Init();
    (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
        FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure; and fill the
        FSMC_NORSRAMInitStructure variable with the allowed values of the
        structure member.
    (#) Initialize the NOR/SRAM Controller by calling the function
        FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
    (#) Then enable the NOR/SRAM Bank, for example:
        FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
    (#) At this stage you can read/write from/to the memory connected to the
        NOR/SRAM Bank.

Function Documentation

void FSMC_NORSRAMCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NOR/SRAM Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 253 of file stm32l1xx_fsmc.c.

References DISABLE, FSMC_Bank1, FSMC_BCR1_MBKEN, IS_FSMC_NORSRAM_BANK, and IS_FUNCTIONAL_STATE.

void FSMC_NORSRAMDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
Return values:
None

Definition at line 99 of file stm32l1xx_fsmc.c.

References FSMC_Bank1, FSMC_Bank1_NORSRAM1, FSMC_Bank1E, and IS_FSMC_NORSRAM_BANK.

void FSMC_NORSRAMInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

Parameters:
FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
Return values:
None

Definition at line 126 of file stm32l1xx_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1, FSMC_Bank1E, FSMC_BCR1_FACCEN, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Enable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, IS_FSMC_ACCESS_MODE, IS_FSMC_ADDRESS_HOLD_TIME, IS_FSMC_ADDRESS_SETUP_TIME, IS_FSMC_ASYNWAIT, IS_FSMC_BURSTMODE, IS_FSMC_CLK_DIV, IS_FSMC_DATA_LATENCY, IS_FSMC_DATASETUP_TIME, IS_FSMC_EXTENDED_MODE, IS_FSMC_MEMORY, IS_FSMC_MEMORY_WIDTH, IS_FSMC_MUX, IS_FSMC_NORSRAM_BANK, IS_FSMC_TURNAROUND_TIME, IS_FSMC_WAIT_POLARITY, IS_FSMC_WAIT_SIGNAL_ACTIVE, IS_FSMC_WAITE_SIGNAL, IS_FSMC_WRAP_MODE, IS_FSMC_WRITE_BURST, and IS_FSMC_WRITE_OPERATION.

void FSMC_NORSRAMStructInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Fills each FSMC_NORSRAMInitStruct member with its default value.

Parameters:
FSMC_NORSRAMInitStruct,: pointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 210 of file stm32l1xx_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, and FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct.


STM32L1xx Standard Peripherals Firmware Library: FSMC

Data Structures | Modules | Functions

FSMC

STM32L1xx_StdPeriph_Driver

FSMC driver modules. More...

Data Structures

struct | FSMC_NORSRAMInitTypeDef
FSMC NOR/SRAM Init structure definition. More...
struct | FSMC_NORSRAMTimingInitTypeDef
Timing parameters For NOR/SRAM Banks. More...

Modules

FSMC_Exported_Constants
FSMC_Private_Functions

Functions

void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.

Detailed Description

FSMC driver modules.

Function Documentation

void FSMC_NORSRAMCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NOR/SRAM Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 253 of file stm32l1xx_fsmc.c.

References DISABLE, FSMC_Bank1, FSMC_BCR1_MBKEN, IS_FSMC_NORSRAM_BANK, and IS_FUNCTIONAL_STATE.

void FSMC_NORSRAMDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
Return values:
None

Definition at line 99 of file stm32l1xx_fsmc.c.

References FSMC_Bank1, FSMC_Bank1_NORSRAM1, FSMC_Bank1E, and IS_FSMC_NORSRAM_BANK.

void FSMC_NORSRAMInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

Parameters:
FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
Return values:
None

Definition at line 126 of file stm32l1xx_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1, FSMC_Bank1E, FSMC_BCR1_FACCEN, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Enable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, IS_FSMC_ACCESS_MODE, IS_FSMC_ADDRESS_HOLD_TIME, IS_FSMC_ADDRESS_SETUP_TIME, IS_FSMC_ASYNWAIT, IS_FSMC_BURSTMODE, IS_FSMC_CLK_DIV, IS_FSMC_DATA_LATENCY, IS_FSMC_DATASETUP_TIME, IS_FSMC_EXTENDED_MODE, IS_FSMC_MEMORY, IS_FSMC_MEMORY_WIDTH, IS_FSMC_MUX, IS_FSMC_NORSRAM_BANK, IS_FSMC_TURNAROUND_TIME, IS_FSMC_WAIT_POLARITY, IS_FSMC_WAIT_SIGNAL_ACTIVE, IS_FSMC_WAITE_SIGNAL, IS_FSMC_WRAP_MODE, IS_FSMC_WRITE_BURST, and IS_FSMC_WRITE_OPERATION.

void FSMC_NORSRAMStructInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Fills each FSMC_NORSRAMInitStruct member with its default value.

Parameters:
FSMC_NORSRAMInitStruct,: pointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 210 of file stm32l1xx_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, and FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct.


STM32L1xx Standard Peripherals Firmware Library: FSMC_NORSRAMInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NORSRAMInitTypeDef Struct Reference
FSMC

FSMC NOR/SRAM Init structure definition. More...

#include <stm32l1xx_fsmc.h>

Data Fields

uint32_t | FSMC_AsynchronousWait
uint32_t | FSMC_Bank
uint32_t | FSMC_BurstAccessMode
uint32_t | FSMC_DataAddressMux
uint32_t | FSMC_ExtendedMode
uint32_t | FSMC_MemoryDataWidth
uint32_t | FSMC_MemoryType
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
uint32_t | FSMC_WaitSignal
uint32_t | FSMC_WaitSignalActive
uint32_t | FSMC_WaitSignalPolarity
uint32_t | FSMC_WrapMode
uint32_t | FSMC_WriteBurst
uint32_t | FSMC_WriteOperation
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct

Detailed Description

FSMC NOR/SRAM Init structure definition.

Definition at line 93 of file stm32l1xx_fsmc.h.

Field Documentation

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait

Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of FSMC_AsynchronousWait

Definition at line 113 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_Bank

Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of FSMC_NORSRAM_Bank

Definition at line 95 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode

Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of FSMC_Burst_Access_Mode

Definition at line 109 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux

Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of FSMC_Data_Address_Bus_Multiplexing

Definition at line 98 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode

Enables or disables the extended mode. This parameter can be a value of FSMC_Extended_Mode

Definition at line 137 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth

Specifies the external memory device width. This parameter can be a value of FSMC_Data_Width

Definition at line 106 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryType

Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of FSMC_Memory_Type

Definition at line 102 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct

Timing Parameters for write and read access if the ExtendedMode is not used

Definition at line 143 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal

Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of FSMC_Wait_Signal

Definition at line 133 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive

Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of FSMC_Wait_Timing

Definition at line 125 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity

Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of FSMC_Wait_Signal_Polarity

Definition at line 117 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WrapMode

Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of FSMC_Wrap_Mode

Definition at line 121 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst

Enables or disables the write burst operation. This parameter can be a value of FSMC_Write_Burst

Definition at line 140 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation

Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of FSMC_Write_Operation

Definition at line 130 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct

Timing Parameters for write access if the ExtendedMode is used

Definition at line 145 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_fsmc.h


STM32L1xx Standard Peripherals Firmware Library: FSMC_NORSRAMTimingInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NORSRAMTimingInitTypeDef Struct Reference
FSMC

Timing parameters For NOR/SRAM Banks. More...

#include <stm32l1xx_fsmc.h>

Data Fields

uint32_t | FSMC_AccessMode
uint32_t | FSMC_AddressHoldTime
uint32_t | FSMC_AddressSetupTime
uint32_t | FSMC_BusTurnAroundDuration
uint32_t | FSMC_CLKDivision
uint32_t | FSMC_DataLatency
uint32_t | FSMC_DataSetupTime

Detailed Description

Timing parameters For NOR/SRAM Banks.

Definition at line 51 of file stm32l1xx_fsmc.h.

Field Documentation

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode

Specifies the asynchronous access mode. This parameter can be a value of FSMC_Access_Mode

Definition at line 85 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime

Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF.

Note:
It is not used with synchronous NOR Flash memories.

Definition at line 58 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime

Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF.

Note:
It is not used with synchronous NOR Flash memories.

Definition at line 53 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration

Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF.

Note:
It is only used for multiplexed NOR Flash memories.

Definition at line 68 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision

Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF.

Note:
This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses.

Definition at line 73 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency

Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below:

  • It must be set to 0 in case of a CRAM
  • It is don't care in asynchronous NOR, SRAM or ROM accesses
  • It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable

Definition at line 77 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime

Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF.

Note:
It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories.

Definition at line 63 of file stm32l1xx_fsmc.h.

Referenced by FSMC_NORSRAMInit(), and FSMC_NORSRAMStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_fsmc.h


STM32L1xx Standard Peripherals Firmware Library: Configuration_Mode_enumeration

Defines | Enumerations

Configuration_Mode_enumeration

GPIO

Defines

#define | IS_GPIO_MODE(MODE)

Enumerations

enum | GPIOMode_TypeDef { GPIO_Mode_IN = 0x00, GPIO_Mode_OUT = 0x01, GPIO_Mode_AF = 0x02, GPIO_Mode_AN = 0x03 }

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))

Definition at line 66 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init().

Enumeration Type Documentation

enum GPIOMode_TypeDef
Enumerator:
GPIO_Mode_IN

GPIO Input Mode

GPIO_Mode_OUT

GPIO Output Mode

GPIO_Mode_AF

GPIO Alternate function Mode

GPIO_Mode_AN

GPIO Analog Mode

Definition at line 59 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: Output_type_enumeration

Defines | Enumerations

Output_type_enumeration

GPIO

Defines

#define | IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))

Enumerations

enum | GPIOOType_TypeDef { GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01 }

Define Documentation

#define IS_GPIO_OTYPE ( OTYPE ) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))

Definition at line 79 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init().

Enumeration Type Documentation

enum GPIOOType_TypeDef
Enumerator:
GPIO_OType_PP
GPIO_OType_OD

Definition at line 75 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: Output_Maximum_frequency_enumeration

Defines | Enumerations

Output_Maximum_frequency_enumeration

GPIO

Defines

#define | IS_GPIO_SPEED(SPEED)

Enumerations

enum | GPIOSpeed_TypeDef { GPIO_Speed_400KHz = 0x00, GPIO_Speed_2MHz = 0x01, GPIO_Speed_10MHz = 0x02, GPIO_Speed_40MHz = 0x03 }

Define Documentation

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
                              ((SPEED) == GPIO_Speed_10MHz)||  ((SPEED) == GPIO_Speed_40MHz))

Definition at line 95 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init().

Enumeration Type Documentation

enum GPIOSpeed_TypeDef
Enumerator:
GPIO_Speed_400KHz

Very Low Speed

GPIO_Speed_2MHz

Low Speed

GPIO_Speed_10MHz

Medium Speed

GPIO_Speed_40MHz

High Speed

Definition at line 88 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: Configuration_Pull-Up_Pull-Down_enumeration

Defines | Enumerations

Configuration_Pull-Up_Pull-Down_enumeration

GPIO

Defines

#define | IS_GPIO_PUPD(PUPD)

Enumerations

enum | GPIOPuPd_TypeDef { GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02 }

Define Documentation

#define IS_GPIO_PUPD ( PUPD )
Value:
(((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
                            ((PUPD) == GPIO_PuPd_DOWN))

Definition at line 109 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init().

Enumeration Type Documentation

enum GPIOPuPd_TypeDef
Enumerator:
GPIO_PuPd_NOPULL
GPIO_PuPd_UP
GPIO_PuPd_DOWN

Definition at line 104 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: Bit_SET_and_Bit_RESET_enumeration

Defines | Enumerations

Bit_SET_and_Bit_RESET_enumeration

GPIO

Defines

#define | IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))

Enumerations

enum | BitAction { Bit_RESET = 0, Bit_SET }

Define Documentation

#define IS_GPIO_BIT_ACTION ( ACTION ) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))

Definition at line 122 of file stm32l1xx_gpio.h.

Referenced by GPIO_WriteBit().

Enumeration Type Documentation

enum BitAction
Enumerator:
Bit_RESET
Bit_SET

Definition at line 118 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: GPIO_pins_define

Defines

GPIO_pins_define

GPIO_Exported_Constants

Defines

#define | GPIO_Pin_0 ((uint16_t)0x0001)
#define | GPIO_Pin_1 ((uint16_t)0x0002)
#define | GPIO_Pin_10 ((uint16_t)0x0400)
#define | GPIO_Pin_11 ((uint16_t)0x0800)
#define | GPIO_Pin_12 ((uint16_t)0x1000)
#define | GPIO_Pin_13 ((uint16_t)0x2000)
#define | GPIO_Pin_14 ((uint16_t)0x4000)
#define | GPIO_Pin_15 ((uint16_t)0x8000)
#define | GPIO_Pin_2 ((uint16_t)0x0004)
#define | GPIO_Pin_3 ((uint16_t)0x0008)
#define | GPIO_Pin_4 ((uint16_t)0x0010)
#define | GPIO_Pin_5 ((uint16_t)0x0020)
#define | GPIO_Pin_6 ((uint16_t)0x0040)
#define | GPIO_Pin_7 ((uint16_t)0x0080)
#define | GPIO_Pin_8 ((uint16_t)0x0100)
#define | GPIO_Pin_9 ((uint16_t)0x0200)
#define | GPIO_Pin_All ((uint16_t)0xFFFF)
#define | IS_GET_GPIO_PIN(PIN)
#define | IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)

Define Documentation

#define GPIO_Pin_0 ((uint16_t)0x0001)

Pin 0 selected

Definition at line 158 of file stm32l1xx_gpio.h.

#define GPIO_Pin_1 ((uint16_t)0x0002)

Pin 1 selected

Definition at line 159 of file stm32l1xx_gpio.h.

#define GPIO_Pin_10 ((uint16_t)0x0400)

Pin 10 selected

Definition at line 168 of file stm32l1xx_gpio.h.

#define GPIO_Pin_11 ((uint16_t)0x0800)

Pin 11 selected

Definition at line 169 of file stm32l1xx_gpio.h.

#define GPIO_Pin_12 ((uint16_t)0x1000)

Pin 12 selected

Definition at line 170 of file stm32l1xx_gpio.h.

#define GPIO_Pin_13 ((uint16_t)0x2000)

Pin 13 selected

Definition at line 171 of file stm32l1xx_gpio.h.

#define GPIO_Pin_14 ((uint16_t)0x4000)

Pin 14 selected

Definition at line 172 of file stm32l1xx_gpio.h.

#define GPIO_Pin_15 ((uint16_t)0x8000)

Pin 15 selected

Definition at line 173 of file stm32l1xx_gpio.h.

#define GPIO_Pin_2 ((uint16_t)0x0004)

Pin 2 selected

Definition at line 160 of file stm32l1xx_gpio.h.

#define GPIO_Pin_3 ((uint16_t)0x0008)

Pin 3 selected

Definition at line 161 of file stm32l1xx_gpio.h.

#define GPIO_Pin_4 ((uint16_t)0x0010)

Pin 4 selected

Definition at line 162 of file stm32l1xx_gpio.h.

#define GPIO_Pin_5 ((uint16_t)0x0020)

Pin 5 selected

Definition at line 163 of file stm32l1xx_gpio.h.

#define GPIO_Pin_6 ((uint16_t)0x0040)

Pin 6 selected

Definition at line 164 of file stm32l1xx_gpio.h.

#define GPIO_Pin_7 ((uint16_t)0x0080)

Pin 7 selected

Definition at line 165 of file stm32l1xx_gpio.h.

#define GPIO_Pin_8 ((uint16_t)0x0100)

Pin 8 selected

Definition at line 166 of file stm32l1xx_gpio.h.

#define GPIO_Pin_9 ((uint16_t)0x0200)

Pin 9 selected

Definition at line 167 of file stm32l1xx_gpio.h.

#define GPIO_Pin_All ((uint16_t)0xFFFF)

All pins selected

Definition at line 174 of file stm32l1xx_gpio.h.

Referenced by GPIO_StructInit().

#define IS_GET_GPIO_PIN ( PIN )
Value:
(((PIN) == GPIO_Pin_0) || \
                              ((PIN) == GPIO_Pin_1) || \
                              ((PIN) == GPIO_Pin_2) || \
                              ((PIN) == GPIO_Pin_3) || \
                              ((PIN) == GPIO_Pin_4) || \
                              ((PIN) == GPIO_Pin_5) || \
                              ((PIN) == GPIO_Pin_6) || \
                              ((PIN) == GPIO_Pin_7) || \
                              ((PIN) == GPIO_Pin_8) || \
                              ((PIN) == GPIO_Pin_9) || \
                              ((PIN) == GPIO_Pin_10) || \
                              ((PIN) == GPIO_Pin_11) || \
                              ((PIN) == GPIO_Pin_12) || \
                              ((PIN) == GPIO_Pin_13) || \
                              ((PIN) == GPIO_Pin_14) || \
                              ((PIN) == GPIO_Pin_15))

Definition at line 177 of file stm32l1xx_gpio.h.

Referenced by GPIO_ReadInputDataBit(), GPIO_ReadOutputDataBit(), and GPIO_WriteBit().

#define IS_GPIO_PIN ( PIN ) ((PIN) != (uint16_t)0x00)

Definition at line 176 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), GPIO_PinLockConfig(), GPIO_ResetBits(), and GPIO_SetBits().


STM32L1xx Standard Peripherals Firmware Library: GPIO_Pin_sources

Defines

GPIO_Pin_sources

GPIO_Exported_Constants

Defines

#define | GPIO_PinSource0 ((uint8_t)0x00)
#define | GPIO_PinSource1 ((uint8_t)0x01)
#define | GPIO_PinSource10 ((uint8_t)0x0A)
#define | GPIO_PinSource11 ((uint8_t)0x0B)
#define | GPIO_PinSource12 ((uint8_t)0x0C)
#define | GPIO_PinSource13 ((uint8_t)0x0D)
#define | GPIO_PinSource14 ((uint8_t)0x0E)
#define | GPIO_PinSource15 ((uint8_t)0x0F)
#define | GPIO_PinSource2 ((uint8_t)0x02)
#define | GPIO_PinSource3 ((uint8_t)0x03)
#define | GPIO_PinSource4 ((uint8_t)0x04)
#define | GPIO_PinSource5 ((uint8_t)0x05)
#define | GPIO_PinSource6 ((uint8_t)0x06)
#define | GPIO_PinSource7 ((uint8_t)0x07)
#define | GPIO_PinSource8 ((uint8_t)0x08)
#define | GPIO_PinSource9 ((uint8_t)0x09)
#define | IS_GPIO_PIN_SOURCE(PINSOURCE)

Define Documentation

#define GPIO_PinSource0 ((uint8_t)0x00)

Definition at line 200 of file stm32l1xx_gpio.h.

#define GPIO_PinSource1 ((uint8_t)0x01)

Definition at line 201 of file stm32l1xx_gpio.h.

#define GPIO_PinSource10 ((uint8_t)0x0A)

Definition at line 210 of file stm32l1xx_gpio.h.

#define GPIO_PinSource11 ((uint8_t)0x0B)

Definition at line 211 of file stm32l1xx_gpio.h.

#define GPIO_PinSource12 ((uint8_t)0x0C)

Definition at line 212 of file stm32l1xx_gpio.h.

#define GPIO_PinSource13 ((uint8_t)0x0D)

Definition at line 213 of file stm32l1xx_gpio.h.

#define GPIO_PinSource14 ((uint8_t)0x0E)

Definition at line 214 of file stm32l1xx_gpio.h.

#define GPIO_PinSource15 ((uint8_t)0x0F)

Definition at line 215 of file stm32l1xx_gpio.h.

#define GPIO_PinSource2 ((uint8_t)0x02)

Definition at line 202 of file stm32l1xx_gpio.h.

#define GPIO_PinSource3 ((uint8_t)0x03)

Definition at line 203 of file stm32l1xx_gpio.h.

#define GPIO_PinSource4 ((uint8_t)0x04)

Definition at line 204 of file stm32l1xx_gpio.h.

#define GPIO_PinSource5 ((uint8_t)0x05)

Definition at line 205 of file stm32l1xx_gpio.h.

#define GPIO_PinSource6 ((uint8_t)0x06)

Definition at line 206 of file stm32l1xx_gpio.h.

#define GPIO_PinSource7 ((uint8_t)0x07)

Definition at line 207 of file stm32l1xx_gpio.h.

#define GPIO_PinSource8 ((uint8_t)0x08)

Definition at line 208 of file stm32l1xx_gpio.h.

#define GPIO_PinSource9 ((uint8_t)0x09)

Definition at line 209 of file stm32l1xx_gpio.h.

#define IS_GPIO_PIN_SOURCE ( PINSOURCE )
Value:
(((PINSOURCE) == GPIO_PinSource0) || \
                                       ((PINSOURCE) == GPIO_PinSource1) || \
                                       ((PINSOURCE) == GPIO_PinSource2) || \
                                       ((PINSOURCE) == GPIO_PinSource3) || \
                                       ((PINSOURCE) == GPIO_PinSource4) || \
                                       ((PINSOURCE) == GPIO_PinSource5) || \
                                       ((PINSOURCE) == GPIO_PinSource6) || \
                                       ((PINSOURCE) == GPIO_PinSource7) || \
                                       ((PINSOURCE) == GPIO_PinSource8) || \
                                       ((PINSOURCE) == GPIO_PinSource9) || \
                                       ((PINSOURCE) == GPIO_PinSource10) || \
                                       ((PINSOURCE) == GPIO_PinSource11) || \
                                       ((PINSOURCE) == GPIO_PinSource12) || \
                                       ((PINSOURCE) == GPIO_PinSource13) || \
                                       ((PINSOURCE) == GPIO_PinSource14) || \
                                       ((PINSOURCE) == GPIO_PinSource15))

Definition at line 217 of file stm32l1xx_gpio.h.

Referenced by GPIO_PinAFConfig().


STM32L1xx Standard Peripherals Firmware Library: GPIO_Alternat_function_selection_define

Defines

GPIO_Alternat_function_selection_define

GPIO_Exported_Constants

Defines

#define | GPIO_AF_EVENTOUT ((uint8_t)0x0F)
AF 15 selection.
#define | GPIO_AF_FSMC ((uint8_t)0x0C)
AF 12 selection.
#define | GPIO_AF_I2C1 ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF_I2C2 ((uint8_t)0x04)
#define | GPIO_AF_LCD ((uint8_t)0x0B)
AF 11 selection.
#define | GPIO_AF_MCO ((uint8_t)0x00)
#define | GPIO_AF_RI ((uint8_t)0x0E)
AF 14 selection.
#define | GPIO_AF_RTC_50Hz ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF_RTC_AF1 ((uint8_t)0x00)
#define | GPIO_AF_SDIO ((uint8_t)0x0C)
#define | GPIO_AF_SPI1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF_SPI2 ((uint8_t)0x05)
#define | GPIO_AF_SPI3 ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF_SWJ ((uint8_t)0x00)
#define | GPIO_AF_TIM10 ((uint8_t)0x03)
#define | GPIO_AF_TIM11 ((uint8_t)0x03)
#define | GPIO_AF_TIM2 ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF_TIM3 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF_TIM4 ((uint8_t)0x02)
#define | GPIO_AF_TIM5 ((uint8_t)0x02)
#define | GPIO_AF_TIM9 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF_TRACE ((uint8_t)0x00)
#define | GPIO_AF_UART4 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF_UART5 ((uint8_t)0x08)
#define | GPIO_AF_USART1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF_USART2 ((uint8_t)0x07)
#define | GPIO_AF_USART3 ((uint8_t)0x07)
#define | GPIO_AF_USB ((uint8_t)0xA)
AF 10 selection.
#define | GPIO_AF_WKUP ((uint8_t)0x00)
#define | IS_GPIO_AF(AF)

Define Documentation

#define GPIO_AF_EVENTOUT ((uint8_t)0x0F)

AF 15 selection.

EVENTOUT Alternate Function mapping

Definition at line 313 of file stm32l1xx_gpio.h.

#define GPIO_AF_FSMC ((uint8_t)0x0C)

AF 12 selection.

FSMC Alternate Function mapping

Definition at line 303 of file stm32l1xx_gpio.h.

#define GPIO_AF_I2C1 ((uint8_t)0x04)

AF 4 selection.

I2C1 Alternate Function mapping

Definition at line 270 of file stm32l1xx_gpio.h.

#define GPIO_AF_I2C2 ((uint8_t)0x04)

I2C2 Alternate Function mapping

Definition at line 271 of file stm32l1xx_gpio.h.

#define GPIO_AF_LCD ((uint8_t)0x0B)

AF 11 selection.

LCD Alternate Function mapping

Definition at line 299 of file stm32l1xx_gpio.h.

#define GPIO_AF_MCO ((uint8_t)0x00)

MCO Alternate Function mapping

Definition at line 245 of file stm32l1xx_gpio.h.

#define GPIO_AF_RI ((uint8_t)0x0E)

AF 14 selection.

RI Alternate Function mapping

Definition at line 308 of file stm32l1xx_gpio.h.

#define GPIO_AF_RTC_50Hz ((uint8_t)0x00)

AF 0 selection.

RTC 50/60 Hz Alternate Function mapping

Definition at line 244 of file stm32l1xx_gpio.h.

#define GPIO_AF_RTC_AF1 ((uint8_t)0x00)

RTC_AF1 Alternate Function mapping

Definition at line 246 of file stm32l1xx_gpio.h.

#define GPIO_AF_SDIO ((uint8_t)0x0C)

SDIO Alternate Function mapping

Definition at line 304 of file stm32l1xx_gpio.h.

#define GPIO_AF_SPI1 ((uint8_t)0x05)

AF 5 selection.

SPI1 Alternate Function mapping

Definition at line 275 of file stm32l1xx_gpio.h.

#define GPIO_AF_SPI2 ((uint8_t)0x05)

SPI2 Alternate Function mapping

Definition at line 276 of file stm32l1xx_gpio.h.

#define GPIO_AF_SPI3 ((uint8_t)0x06)

AF 6 selection.

SPI3 Alternate Function mapping

Definition at line 280 of file stm32l1xx_gpio.h.

#define GPIO_AF_SWJ ((uint8_t)0x00)

SWJ (SW and JTAG) Alternate Function mapping

Definition at line 248 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM10 ((uint8_t)0x03)

TIM10 Alternate Function mapping

Definition at line 265 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM11 ((uint8_t)0x03)

TIM11 Alternate Function mapping

Definition at line 266 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM2 ((uint8_t)0x01)

AF 1 selection.

TIM2 Alternate Function mapping

Definition at line 254 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM3 ((uint8_t)0x02)

AF 2 selection.

TIM3 Alternate Function mapping

Definition at line 258 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM4 ((uint8_t)0x02)

TIM4 Alternate Function mapping

Definition at line 259 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM5 ((uint8_t)0x02)

TIM5 Alternate Function mapping

Definition at line 260 of file stm32l1xx_gpio.h.

#define GPIO_AF_TIM9 ((uint8_t)0x03)

AF 3 selection.

TIM9 Alternate Function mapping

Definition at line 264 of file stm32l1xx_gpio.h.

#define GPIO_AF_TRACE ((uint8_t)0x00)

TRACE Alternate Function mapping

Definition at line 249 of file stm32l1xx_gpio.h.

#define GPIO_AF_UART4 ((uint8_t)0x08)

AF 8 selection.

UART4 Alternate Function mapping

Definition at line 290 of file stm32l1xx_gpio.h.

#define GPIO_AF_UART5 ((uint8_t)0x08)

UART5 Alternate Function mapping

Definition at line 291 of file stm32l1xx_gpio.h.

#define GPIO_AF_USART1 ((uint8_t)0x07)

AF 7 selection.

USART1 Alternate Function mapping

Definition at line 284 of file stm32l1xx_gpio.h.

#define GPIO_AF_USART2 ((uint8_t)0x07)

USART2 Alternate Function mapping

Definition at line 285 of file stm32l1xx_gpio.h.

#define GPIO_AF_USART3 ((uint8_t)0x07)

USART3 Alternate Function mapping

Definition at line 286 of file stm32l1xx_gpio.h.

#define GPIO_AF_USB ((uint8_t)0xA)

AF 10 selection.

USB Full speed device Alternate Function mapping

Definition at line 295 of file stm32l1xx_gpio.h.

#define GPIO_AF_WKUP ((uint8_t)0x00)

Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping

Definition at line 247 of file stm32l1xx_gpio.h.

#define IS_GPIO_AF ( AF )
Value:
(((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO)    || \
                          ((AF) == GPIO_AF_RTC_AF1)  || ((AF) == GPIO_AF_WKUP)   || \
                          ((AF) == GPIO_AF_SWJ)      || ((AF) == GPIO_AF_TRACE)  || \
                          ((AF) == GPIO_AF_TIM2)     || ((AF)== GPIO_AF_TIM3)    || \
                          ((AF) == GPIO_AF_TIM4)     || ((AF)== GPIO_AF_TIM9)    || \
                          ((AF) == GPIO_AF_TIM10)    || ((AF)== GPIO_AF_TIM11)   || \
                          ((AF) == GPIO_AF_I2C1)     || ((AF) == GPIO_AF_I2C2)   || \
                          ((AF) == GPIO_AF_SPI1)     || ((AF) == GPIO_AF_SPI2)   || \
                          ((AF) == GPIO_AF_USART1)   || ((AF) == GPIO_AF_USART2) || \
                          ((AF) == GPIO_AF_USART3)   || ((AF) == GPIO_AF_USB)    || \
                          ((AF) == GPIO_AF_LCD)      || ((AF) == GPIO_AF_RI)     || \
                          ((AF) == GPIO_AF_TIM5)     || ((AF) == GPIO_AF_SPI3)   || \
                          ((AF) == GPIO_AF_UART4)    || ((AF) == GPIO_AF_UART5)  || \
                          ((AF) == GPIO_AF_FSMC)     || ((AF) == GPIO_AF_SDIO)   || \
                          ((AF) == GPIO_AF_EVENTOUT))

Definition at line 315 of file stm32l1xx_gpio.h.

Referenced by GPIO_PinAFConfig().


STM32L1xx Standard Peripherals Firmware Library: GPIO_Legacy

Defines

GPIO_Legacy

GPIO_Exported_Constants

Defines

#define GPIO_Mode_AIN GPIO_Mode_AN

Define Documentation

#define GPIO_Mode_AIN GPIO_Mode_AN

Definition at line 339 of file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration

Functions

Initialization and Configuration

GPIO_Private_Functions

Initialization and Configuration. More...

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.

Detailed Description

Initialization and Configuration.

 ===============================================================================
                    ##### Initialization and Configuration #####
 ===============================================================================

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

By default, The GPIO pins are configured in input floating mode (except JTAG pins).

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
None

Definition at line 116 of file stm32l1xx_gpio.c.

References DISABLE, ENABLE, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, IS_GPIO_ALL_PERIPH, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH, and RCC_AHBPeriphResetCmd().

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_InitStruct,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 176 of file stm32l1xx_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF, GPIO_Mode_OUT, GPIO_MODER_MODER0, GPIO_OSPEEDER_OSPEEDR0, GPIO_InitTypeDef::GPIO_OType, GPIO_OTYPER_OT_0, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_PuPd, GPIO_PUPDR_PUPDR0, GPIO_InitTypeDef::GPIO_Speed, IS_GPIO_ALL_PERIPH, IS_GPIO_MODE, IS_GPIO_OTYPE, IS_GPIO_PIN, IS_GPIO_PUPD, IS_GPIO_SPEED, GPIO_TypeDef::MODER, GPIO_TypeDef::OSPEEDR, GPIO_TypeDef::OTYPER, and GPIO_TypeDef::PUPDR.

void GPIO_PinLockConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. The configuration of the locked GPIO pins can no longer be modified until the next reset.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 252 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, IS_GPIO_PIN, and GPIO_TypeDef::LCKR.

void GPIO_StructInit ( GPIO_InitTypeDef * GPIO_InitStruct )

Fills each GPIO_InitStruct member with its default value.

Parameters:
GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 231 of file stm32l1xx_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN, GPIO_InitTypeDef::GPIO_OType, GPIO_OType_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_All, GPIO_InitTypeDef::GPIO_PuPd, GPIO_PuPd_NOPULL, GPIO_InitTypeDef::GPIO_Speed, and GPIO_Speed_400KHz.


STM32L1xx Standard Peripherals Firmware Library: GPIO Read and Write

Functions

GPIO Read and Write

GPIO_Private_Functions

GPIO Read and Write. More...

Functions

uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

GPIO Read and Write.

 ===============================================================================
                      ##### GPIO Read and Write #####
 ===============================================================================

Function Documentation

uint16_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
GPIO input data port value.

Definition at line 320 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::IDR, and IS_GPIO_ALL_PERIPH.

uint8_t GPIO_ReadInputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 296 of file stm32l1xx_gpio.c.

References Bit_RESET, Bit_SET, GPIO_TypeDef::IDR, IS_GET_GPIO_PIN, and IS_GPIO_ALL_PERIPH.

uint16_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
GPIO output data port value.

Definition at line 359 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

uint8_t GPIO_ReadOutputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified output data port bit.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: Specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The output port pin value.

Definition at line 335 of file stm32l1xx_gpio.c.

References Bit_RESET, Bit_SET, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_ResetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Clears the selected data port bits.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Note:
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Return values:
None

Definition at line 396 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::BSRRH, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

void GPIO_SetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Sets the selected data port bits.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Note:
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Return values:
None

Definition at line 377 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::BSRRL, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

void GPIO_ToggleBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 454 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
PortVal,: specifies the value to be written to the port output data register.
Return values:
None

Definition at line 440 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_WriteBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | BitAction | BitVal
 | ) |  |

Sets or clears the selected data port bit.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitVal,: specifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 416 of file stm32l1xx_gpio.c.

References Bit_RESET, GPIO_TypeDef::BSRRH, GPIO_TypeDef::BSRRL, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and IS_GPIO_BIT_ACTION.


STM32L1xx Standard Peripherals Firmware Library: GPIO Alternate functions configuration functions

Functions

GPIO Alternate functions configuration functions

GPIO_Private_Functions

GPIO Alternate functions configuration functions. More...

Functions

void GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
Changes the mapping of the specified pin.

Detailed Description

GPIO Alternate functions configuration functions.

 ===============================================================================
          ##### GPIO Alternate functions configuration functions #####
 ===============================================================================

Function Documentation

void GPIO_PinAFConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_PinSource,
 |  | uint8_t | GPIO_AF
 | ) |  |

Changes the mapping of the specified pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_PinSource,: specifies the pin for the Alternate function. This parameter can be GPIO_PinSourcex where x can be (0..15).
GPIO_AFSelection,: selects the pin to used as Alternat function. This parameter can be one of the following values:

  • GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization
  • GPIO_AF_MCO: Microcontroller clock output
  • GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out, 512 Hz clock output (with an LSE oscillator of 32.768 kHz)
  • GPIO_AF_WKUP: wakeup
  • GPIO_AF_SWJ: SWJ (SW and JTAG)
  • GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
  • GPIO_AF_TIM2c: Connect TIM2 pins to AF1
  • GPIO_AF_TIM3: Connect TIM3 pins to AF2
  • GPIO_AF_TIM4: Connect TIM4 pins to AF2
  • GPIO_AF_TIM5: Connect TIM5 pins to AF2
  • GPIO_AF_TIM9: Connect TIM9 pins to AF3
  • GPIO_AF_TIM10: Connect TIM10 pins to AF3
  • GPIO_AF_TIM11: Connect TIM11 pins to AF3
  • GPIO_AF_I2C1: Connect I2C1 pins to AF4
  • GPIO_AF_I2C2: Connect I2C2 pins to AF4
  • GPIO_AF_SPI1: Connect SPI1 pins to AF5
  • GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
  • GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
  • GPIO_AF_USART1: Connect USART1 pins to AF7
  • GPIO_AF_USART2: Connect USART2 pins to AF7
  • GPIO_AF_USART3: Connect USART3 pins to AF7
  • GPIO_AF_UART4: Connect UART4 pins to AF8
  • GPIO_AF_UART5: Connect UART5 pins to AF8
  • GPIO_AF_USB: Connect USB pins to AF10
  • GPIO_AF_LCD: Connect LCD pins to AF11
  • GPIO_AF_FSMC: Connect FSMC pins to AF12
  • GPIO_AF_SDIO: Connect SDIO pins to AF12
  • GPIO_AF_RI: Connect RI pins to AF14
  • GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal
Note:
The pin should already been configured in Alternate Function mode(AF) using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
Please refer to the Alternate function mapping table in the device datasheet for the detailed mapping of the system and peripherals' alternate function I/O pins.
EVENTOUT is not mapped on PH0, PH1 and PH2.
Return values:
None

Definition at line 523 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::AFR, IS_GPIO_AF, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN_SOURCE.


STM32L1xx Standard Peripherals Firmware Library: GPIO

Data Structures | Modules | Defines | Functions

GPIO

STM32L1xx_StdPeriph_Driver

GPIO driver modules. More...

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Modules

Configuration_Mode_enumeration
Output_type_enumeration
Output_Maximum_frequency_enumeration
Configuration_Pull-Up_Pull-Down_enumeration
Bit_SET_and_Bit_RESET_enumeration
GPIO_Exported_Constants
GPIO_Private_Functions

Defines

#define | IS_GPIO_ALL_PERIPH(PERIPH)

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
Changes the mapping of the specified pin.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

GPIO driver modules.

Define Documentation

#define IS_GPIO_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == GPIOA) || \
                                    ((PERIPH) == GPIOB) || \
                                    ((PERIPH) == GPIOC) || \
                                    ((PERIPH) == GPIOD) || \
                                    ((PERIPH) == GPIOE) || \
                                    ((PERIPH) == GPIOH) || \
                                    ((PERIPH) == GPIOF) || \
                                    ((PERIPH) == GPIOG))

Definition at line 47 of file stm32l1xx_gpio.h.

Referenced by GPIO_DeInit(), GPIO_Init(), GPIO_PinAFConfig(), GPIO_PinLockConfig(), GPIO_ReadInputData(), GPIO_ReadInputDataBit(), GPIO_ReadOutputData(), GPIO_ReadOutputDataBit(), GPIO_ResetBits(), GPIO_SetBits(), GPIO_ToggleBits(), GPIO_Write(), and GPIO_WriteBit().

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

By default, The GPIO pins are configured in input floating mode (except JTAG pins).

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
None

Definition at line 116 of file stm32l1xx_gpio.c.

References DISABLE, ENABLE, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, IS_GPIO_ALL_PERIPH, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH, and RCC_AHBPeriphResetCmd().

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_InitStruct,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 176 of file stm32l1xx_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF, GPIO_Mode_OUT, GPIO_MODER_MODER0, GPIO_OSPEEDER_OSPEEDR0, GPIO_InitTypeDef::GPIO_OType, GPIO_OTYPER_OT_0, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_PuPd, GPIO_PUPDR_PUPDR0, GPIO_InitTypeDef::GPIO_Speed, IS_GPIO_ALL_PERIPH, IS_GPIO_MODE, IS_GPIO_OTYPE, IS_GPIO_PIN, IS_GPIO_PUPD, IS_GPIO_SPEED, GPIO_TypeDef::MODER, GPIO_TypeDef::OSPEEDR, GPIO_TypeDef::OTYPER, and GPIO_TypeDef::PUPDR.

void GPIO_PinAFConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_PinSource,
 |  | uint8_t | GPIO_AF
 | ) |  |

Changes the mapping of the specified pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_PinSource,: specifies the pin for the Alternate function. This parameter can be GPIO_PinSourcex where x can be (0..15).
GPIO_AFSelection,: selects the pin to used as Alternat function. This parameter can be one of the following values:

  • GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization
  • GPIO_AF_MCO: Microcontroller clock output
  • GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out, 512 Hz clock output (with an LSE oscillator of 32.768 kHz)
  • GPIO_AF_WKUP: wakeup
  • GPIO_AF_SWJ: SWJ (SW and JTAG)
  • GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
  • GPIO_AF_TIM2c: Connect TIM2 pins to AF1
  • GPIO_AF_TIM3: Connect TIM3 pins to AF2
  • GPIO_AF_TIM4: Connect TIM4 pins to AF2
  • GPIO_AF_TIM5: Connect TIM5 pins to AF2
  • GPIO_AF_TIM9: Connect TIM9 pins to AF3
  • GPIO_AF_TIM10: Connect TIM10 pins to AF3
  • GPIO_AF_TIM11: Connect TIM11 pins to AF3
  • GPIO_AF_I2C1: Connect I2C1 pins to AF4
  • GPIO_AF_I2C2: Connect I2C2 pins to AF4
  • GPIO_AF_SPI1: Connect SPI1 pins to AF5
  • GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
  • GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
  • GPIO_AF_USART1: Connect USART1 pins to AF7
  • GPIO_AF_USART2: Connect USART2 pins to AF7
  • GPIO_AF_USART3: Connect USART3 pins to AF7
  • GPIO_AF_UART4: Connect UART4 pins to AF8
  • GPIO_AF_UART5: Connect UART5 pins to AF8
  • GPIO_AF_USB: Connect USB pins to AF10
  • GPIO_AF_LCD: Connect LCD pins to AF11
  • GPIO_AF_FSMC: Connect FSMC pins to AF12
  • GPIO_AF_SDIO: Connect SDIO pins to AF12
  • GPIO_AF_RI: Connect RI pins to AF14
  • GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal
Note:
The pin should already been configured in Alternate Function mode(AF) using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
Please refer to the Alternate function mapping table in the device datasheet for the detailed mapping of the system and peripherals' alternate function I/O pins.
EVENTOUT is not mapped on PH0, PH1 and PH2.
Return values:
None

Definition at line 523 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::AFR, IS_GPIO_AF, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN_SOURCE.

void GPIO_PinLockConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. The configuration of the locked GPIO pins can no longer be modified until the next reset.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 252 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, IS_GPIO_PIN, and GPIO_TypeDef::LCKR.

uint16_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
GPIO input data port value.

Definition at line 320 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::IDR, and IS_GPIO_ALL_PERIPH.

uint8_t GPIO_ReadInputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 296 of file stm32l1xx_gpio.c.

References Bit_RESET, Bit_SET, GPIO_TypeDef::IDR, IS_GET_GPIO_PIN, and IS_GPIO_ALL_PERIPH.

uint16_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
Return values:
GPIO output data port value.

Definition at line 359 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

uint8_t GPIO_ReadOutputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified output data port bit.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: Specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The output port pin value.

Definition at line 335 of file stm32l1xx_gpio.c.

References Bit_RESET, Bit_SET, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_ResetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Clears the selected data port bits.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Note:
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Return values:
None

Definition at line 396 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::BSRRH, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

void GPIO_SetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Sets the selected data port bits.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Note:
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Return values:
None

Definition at line 377 of file stm32l1xx_gpio.c.

References GPIO_TypeDef::BSRRL, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

void GPIO_StructInit ( GPIO_InitTypeDef * GPIO_InitStruct )

Fills each GPIO_InitStruct member with its default value.

Parameters:
GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 231 of file stm32l1xx_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN, GPIO_InitTypeDef::GPIO_OType, GPIO_OType_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_All, GPIO_InitTypeDef::GPIO_PuPd, GPIO_PuPd_NOPULL, GPIO_InitTypeDef::GPIO_Speed, and GPIO_Speed_400KHz.

void GPIO_ToggleBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 454 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
PortVal,: specifies the value to be written to the port output data register.
Return values:
None

Definition at line 440 of file stm32l1xx_gpio.c.

References IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_WriteBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | BitAction | BitVal
 | ) |  |

Sets or clears the selected data port bit.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitVal,: specifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 416 of file stm32l1xx_gpio.c.

References Bit_RESET, GPIO_TypeDef::BSRRH, GPIO_TypeDef::BSRRL, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and IS_GPIO_BIT_ACTION.


STM32L1xx Standard Peripherals Firmware Library: GPIO_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

GPIO_InitTypeDef Struct Reference
GPIO

GPIO Init structure definition. More...

#include <stm32l1xx_gpio.h>

Data Fields

GPIOMode_TypeDef GPIO_Mode
GPIOOType_TypeDef GPIO_OType
uint32_t GPIO_Pin
GPIOPuPd_TypeDef GPIO_PuPd
GPIOSpeed_TypeDef GPIO_Speed

Detailed Description

GPIO Init structure definition.

Definition at line 131 of file stm32l1xx_gpio.h.

Field Documentation

GPIOMode_TypeDef GPIO_InitTypeDef::GPIO_Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIOMode_TypeDef

Definition at line 136 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), and GPIO_StructInit().

GPIOOType_TypeDef GPIO_InitTypeDef::GPIO_OType

Specifies the operating output type for the selected pins. This parameter can be a value of GPIOOType_TypeDef

Definition at line 142 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), and GPIO_StructInit().

uint32_t GPIO_InitTypeDef::GPIO_Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO_pins_define

Definition at line 133 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), and GPIO_StructInit().

GPIOPuPd_TypeDef GPIO_InitTypeDef::GPIO_PuPd

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of GPIOPuPd_TypeDef

Definition at line 145 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), and GPIO_StructInit().

GPIOSpeed_TypeDef GPIO_InitTypeDef::GPIO_Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIOSpeed_TypeDef

Definition at line 139 of file stm32l1xx_gpio.h.

Referenced by GPIO_Init(), and GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_gpio.h


STM32L1xx Standard Peripherals Firmware Library: I2C_mode

Defines

I2C_mode

I2C_Exported_Constants

Defines

#define | I2C_Mode_I2C ((uint16_t)0x0000)
#define | I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define | I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define | IS_I2C_MODE(MODE)

Define Documentation

#define I2C_Mode_I2C ((uint16_t)0x0000)

Definition at line 85 of file stm32l1xx_i2c.h.

Referenced by I2C_StructInit().

#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)

Definition at line 86 of file stm32l1xx_i2c.h.

#define I2C_Mode_SMBusHost ((uint16_t)0x000A)

Definition at line 87 of file stm32l1xx_i2c.h.

#define IS_I2C_MODE ( MODE )
Value:
(((MODE) == I2C_Mode_I2C) || \
                           ((MODE) == I2C_Mode_SMBusDevice) || \
                           ((MODE) == I2C_Mode_SMBusHost))

Definition at line 88 of file stm32l1xx_i2c.h.

Referenced by I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_duty_cycle_in_fast_mode

Defines

I2C_duty_cycle_in_fast_mode

I2C_Exported_Constants

Defines

#define | I2C_DutyCycle_16_9 ((uint16_t)0x4000)
#define | I2C_DutyCycle_2 ((uint16_t)0xBFFF)
#define | IS_I2C_DUTY_CYCLE(CYCLE)

Define Documentation

#define I2C_DutyCycle_16_9 ((uint16_t)0x4000)

I2C fast mode Tlow/Thigh = 16/9

Definition at line 99 of file stm32l1xx_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define I2C_DutyCycle_2 ((uint16_t)0xBFFF)

I2C fast mode Tlow/Thigh = 2

Definition at line 100 of file stm32l1xx_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), I2C_Init(), and I2C_StructInit().

#define IS_I2C_DUTY_CYCLE ( CYCLE )
Value:
(((CYCLE) == I2C_DutyCycle_16_9) || \
                                  ((CYCLE) == I2C_DutyCycle_2))

Definition at line 101 of file stm32l1xx_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_acknowledgement

Defines

I2C_acknowledgement

I2C_Exported_Constants

Defines

#define | I2C_Ack_Disable ((uint16_t)0x0000)
#define | I2C_Ack_Enable ((uint16_t)0x0400)
#define | IS_I2C_ACK_STATE(STATE)

Define Documentation

#define I2C_Ack_Disable ((uint16_t)0x0000)

Definition at line 112 of file stm32l1xx_i2c.h.

Referenced by I2C_StructInit().

#define I2C_Ack_Enable ((uint16_t)0x0400)

Definition at line 111 of file stm32l1xx_i2c.h.

#define IS_I2C_ACK_STATE ( STATE )
Value:
(((STATE) == I2C_Ack_Enable) || \
                                 ((STATE) == I2C_Ack_Disable))

Definition at line 113 of file stm32l1xx_i2c.h.

Referenced by I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_transfer_direction

Defines

I2C_transfer_direction

I2C_Exported_Constants

Defines

#define | I2C_Direction_Receiver ((uint8_t)0x01)
#define | I2C_Direction_Transmitter ((uint8_t)0x00)
#define | IS_I2C_DIRECTION(DIRECTION)

Define Documentation

#define I2C_Direction_Receiver ((uint8_t)0x01)

Definition at line 124 of file stm32l1xx_i2c.h.

#define I2C_Direction_Transmitter ((uint8_t)0x00)

Definition at line 123 of file stm32l1xx_i2c.h.

Referenced by I2C_Send7bitAddress().

#define IS_I2C_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == I2C_Direction_Transmitter) || \
                                     ((DIRECTION) == I2C_Direction_Receiver))

Definition at line 125 of file stm32l1xx_i2c.h.

Referenced by I2C_Send7bitAddress().


STM32L1xx Standard Peripherals Firmware Library: I2C_acknowledged_address

Defines

I2C_acknowledged_address

I2C_Exported_Constants

Defines

#define | I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define | I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define | IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)

Define Documentation

#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)

Definition at line 136 of file stm32l1xx_i2c.h.

#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)

Definition at line 135 of file stm32l1xx_i2c.h.

Referenced by I2C_StructInit().

#define IS_I2C_ACKNOWLEDGE_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))

Definition at line 137 of file stm32l1xx_i2c.h.

Referenced by I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_registers

Defines

I2C_registers

I2C_Exported_Constants

Defines

#define | I2C_Register_CCR ((uint8_t)0x1C)
#define | I2C_Register_CR1 ((uint8_t)0x00)
#define | I2C_Register_CR2 ((uint8_t)0x04)
#define | I2C_Register_DR ((uint8_t)0x10)
#define | I2C_Register_OAR1 ((uint8_t)0x08)
#define | I2C_Register_OAR2 ((uint8_t)0x0C)
#define | I2C_Register_SR1 ((uint8_t)0x14)
#define | I2C_Register_SR2 ((uint8_t)0x18)
#define | I2C_Register_TRISE ((uint8_t)0x20)
#define | IS_I2C_REGISTER(REGISTER)

Define Documentation

#define I2C_Register_CCR ((uint8_t)0x1C)

Definition at line 154 of file stm32l1xx_i2c.h.

#define I2C_Register_CR1 ((uint8_t)0x00)

Definition at line 147 of file stm32l1xx_i2c.h.

#define I2C_Register_CR2 ((uint8_t)0x04)

Definition at line 148 of file stm32l1xx_i2c.h.

#define I2C_Register_DR ((uint8_t)0x10)

Definition at line 151 of file stm32l1xx_i2c.h.

#define I2C_Register_OAR1 ((uint8_t)0x08)

Definition at line 149 of file stm32l1xx_i2c.h.

#define I2C_Register_OAR2 ((uint8_t)0x0C)

Definition at line 150 of file stm32l1xx_i2c.h.

#define I2C_Register_SR1 ((uint8_t)0x14)

Definition at line 152 of file stm32l1xx_i2c.h.

#define I2C_Register_SR2 ((uint8_t)0x18)

Definition at line 153 of file stm32l1xx_i2c.h.

#define I2C_Register_TRISE ((uint8_t)0x20)

Definition at line 155 of file stm32l1xx_i2c.h.

#define IS_I2C_REGISTER ( REGISTER )
Value:
(((REGISTER) == I2C_Register_CR1) || \
                                   ((REGISTER) == I2C_Register_CR2) || \
                                   ((REGISTER) == I2C_Register_OAR1) || \
                                   ((REGISTER) == I2C_Register_OAR2) || \
                                   ((REGISTER) == I2C_Register_DR) || \
                                   ((REGISTER) == I2C_Register_SR1) || \
                                   ((REGISTER) == I2C_Register_SR2) || \
                                   ((REGISTER) == I2C_Register_CCR) || \
                                   ((REGISTER) == I2C_Register_TRISE))

Definition at line 156 of file stm32l1xx_i2c.h.

Referenced by I2C_ReadRegister().


STM32L1xx Standard Peripherals Firmware Library: I2C_SMBus_alert_pin_level

Defines

I2C_SMBus_alert_pin_level

I2C_Exported_Constants

Defines

#define | I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define | I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define | IS_I2C_SMBUS_ALERT(ALERT)

Define Documentation

#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)

Definition at line 174 of file stm32l1xx_i2c.h.

Referenced by I2C_SMBusAlertConfig().

#define I2C_SMBusAlert_Low ((uint16_t)0x2000)

Definition at line 173 of file stm32l1xx_i2c.h.

Referenced by I2C_SMBusAlertConfig().

#define IS_I2C_SMBUS_ALERT ( ALERT )
Value:
(((ALERT) == I2C_SMBusAlert_Low) || \
                                   ((ALERT) == I2C_SMBusAlert_High))

Definition at line 175 of file stm32l1xx_i2c.h.

Referenced by I2C_SMBusAlertConfig().


STM32L1xx Standard Peripherals Firmware Library: I2C_PEC_position

Defines

I2C_PEC_position

I2C_Exported_Constants

Defines

#define | I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define | I2C_PECPosition_Next ((uint16_t)0x0800)
#define | IS_I2C_PEC_POSITION(POSITION)

Define Documentation

#define I2C_PECPosition_Current ((uint16_t)0xF7FF)

Definition at line 186 of file stm32l1xx_i2c.h.

Referenced by I2C_PECPositionConfig().

#define I2C_PECPosition_Next ((uint16_t)0x0800)

Definition at line 185 of file stm32l1xx_i2c.h.

Referenced by I2C_PECPositionConfig().

#define IS_I2C_PEC_POSITION ( POSITION )
Value:
(((POSITION) == I2C_PECPosition_Next) || \
                                       ((POSITION) == I2C_PECPosition_Current))

Definition at line 187 of file stm32l1xx_i2c.h.

Referenced by I2C_PECPositionConfig().


STM32L1xx Standard Peripherals Firmware Library: I2C_NACK_position

Defines

I2C_NACK_position

I2C_Exported_Constants

Defines

#define | I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define | I2C_NACKPosition_Next ((uint16_t)0x0800)
#define | IS_I2C_NACK_POSITION(POSITION)

Define Documentation

#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)

Definition at line 198 of file stm32l1xx_i2c.h.

Referenced by I2C_NACKPositionConfig().

#define I2C_NACKPosition_Next ((uint16_t)0x0800)

Definition at line 197 of file stm32l1xx_i2c.h.

Referenced by I2C_NACKPositionConfig().

#define IS_I2C_NACK_POSITION ( POSITION )
Value:
(((POSITION) == I2C_NACKPosition_Next) || \
                                         ((POSITION) == I2C_NACKPosition_Current))

Definition at line 199 of file stm32l1xx_i2c.h.

Referenced by I2C_NACKPositionConfig().


STM32L1xx Standard Peripherals Firmware Library: I2C_interrupts_definition

Defines

I2C_interrupts_definition

I2C_Exported_Constants

Defines

#define | I2C_IT_ADD10 ((uint32_t)0x02000008)
#define | I2C_IT_ADDR ((uint32_t)0x02000002)
#define | I2C_IT_AF ((uint32_t)0x01000400)
#define | I2C_IT_ARLO ((uint32_t)0x01000200)
#define | I2C_IT_BERR ((uint32_t)0x01000100)
#define | I2C_IT_BTF ((uint32_t)0x02000004)
#define | I2C_IT_BUF ((uint16_t)0x0400)
#define | I2C_IT_ERR ((uint16_t)0x0100)
#define | I2C_IT_EVT ((uint16_t)0x0200)
#define | I2C_IT_OVR ((uint32_t)0x01000800)
#define | I2C_IT_PECERR ((uint32_t)0x01001000)
#define | I2C_IT_RXNE ((uint32_t)0x06000040)
#define | I2C_IT_SB ((uint32_t)0x02000001)
#define | I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define | I2C_IT_STOPF ((uint32_t)0x02000010)
#define | I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define | I2C_IT_TXE ((uint32_t)0x06000080)
#define | IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define | IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
#define | IS_I2C_GET_IT(IT)

Define Documentation

#define I2C_IT_ADD10 ((uint32_t)0x02000008)

Definition at line 231 of file stm32l1xx_i2c.h.

#define I2C_IT_ADDR ((uint32_t)0x02000002)

Definition at line 233 of file stm32l1xx_i2c.h.

#define I2C_IT_AF ((uint32_t)0x01000400)

Definition at line 225 of file stm32l1xx_i2c.h.

#define I2C_IT_ARLO ((uint32_t)0x01000200)

Definition at line 226 of file stm32l1xx_i2c.h.

#define I2C_IT_BERR ((uint32_t)0x01000100)

Definition at line 227 of file stm32l1xx_i2c.h.

#define I2C_IT_BTF ((uint32_t)0x02000004)

Definition at line 232 of file stm32l1xx_i2c.h.

#define I2C_IT_BUF ((uint16_t)0x0400)

Definition at line 209 of file stm32l1xx_i2c.h.

#define I2C_IT_ERR ((uint16_t)0x0100)

Definition at line 211 of file stm32l1xx_i2c.h.

#define I2C_IT_EVT ((uint16_t)0x0200)

Definition at line 210 of file stm32l1xx_i2c.h.

#define I2C_IT_OVR ((uint32_t)0x01000800)

Definition at line 224 of file stm32l1xx_i2c.h.

#define I2C_IT_PECERR ((uint32_t)0x01001000)

Definition at line 223 of file stm32l1xx_i2c.h.

#define I2C_IT_RXNE ((uint32_t)0x06000040)

Definition at line 229 of file stm32l1xx_i2c.h.

#define I2C_IT_SB ((uint32_t)0x02000001)

Definition at line 234 of file stm32l1xx_i2c.h.

#define I2C_IT_SMBALERT ((uint32_t)0x01008000)

Definition at line 221 of file stm32l1xx_i2c.h.

#define I2C_IT_STOPF ((uint32_t)0x02000010)

Definition at line 230 of file stm32l1xx_i2c.h.

#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)

Definition at line 222 of file stm32l1xx_i2c.h.

#define I2C_IT_TXE ((uint32_t)0x06000080)

Definition at line 228 of file stm32l1xx_i2c.h.

#define IS_I2C_CLEAR_IT ( IT ) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))

Definition at line 236 of file stm32l1xx_i2c.h.

Referenced by I2C_ClearITPendingBit().

#define IS_I2C_CONFIG_IT ( IT ) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))

Definition at line 212 of file stm32l1xx_i2c.h.

Referenced by I2C_ITConfig().

#define IS_I2C_GET_IT ( IT )
Value:
(((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))

Definition at line 238 of file stm32l1xx_i2c.h.

Referenced by I2C_GetITStatus().


STM32L1xx Standard Peripherals Firmware Library: I2C_flags_definition

Defines

I2C_flags_definition

I2C_Exported_Constants

Defines

#define | I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define | I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define | I2C_FLAG_AF ((uint32_t)0x10000400)
#define | I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define | I2C_FLAG_BERR ((uint32_t)0x10000100)
#define | I2C_FLAG_BTF ((uint32_t)0x10000004)
#define | I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define | I2C_FLAG_DUALF ((uint32_t)0x00800000)
SR2 register flags.
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define | I2C_FLAG_MSL ((uint32_t)0x00010000)
#define | I2C_FLAG_OVR ((uint32_t)0x10000800)
#define | I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define | I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define | I2C_FLAG_SB ((uint32_t)0x10000001)
#define | I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
SR1 register flags.
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define | I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define | I2C_FLAG_TRA ((uint32_t)0x00040000)
#define | I2C_FLAG_TXE ((uint32_t)0x10000080)
#define | IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_I2C_GET_FLAG(FLAG)

Define Documentation

#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)

Definition at line 279 of file stm32l1xx_i2c.h.

#define I2C_FLAG_ADDR ((uint32_t)0x10000002)

Definition at line 281 of file stm32l1xx_i2c.h.

#define I2C_FLAG_AF ((uint32_t)0x10000400)

Definition at line 273 of file stm32l1xx_i2c.h.

#define I2C_FLAG_ARLO ((uint32_t)0x10000200)

Definition at line 274 of file stm32l1xx_i2c.h.

#define I2C_FLAG_BERR ((uint32_t)0x10000100)

Definition at line 275 of file stm32l1xx_i2c.h.

#define I2C_FLAG_BTF ((uint32_t)0x10000004)

Definition at line 280 of file stm32l1xx_i2c.h.

#define I2C_FLAG_BUSY ((uint32_t)0x00020000)

Definition at line 262 of file stm32l1xx_i2c.h.

#define I2C_FLAG_DUALF ((uint32_t)0x00800000)

SR2 register flags.

Definition at line 257 of file stm32l1xx_i2c.h.

#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)

Definition at line 260 of file stm32l1xx_i2c.h.

#define I2C_FLAG_MSL ((uint32_t)0x00010000)

Definition at line 263 of file stm32l1xx_i2c.h.

#define I2C_FLAG_OVR ((uint32_t)0x10000800)

Definition at line 272 of file stm32l1xx_i2c.h.

#define I2C_FLAG_PECERR ((uint32_t)0x10001000)

Definition at line 271 of file stm32l1xx_i2c.h.

#define I2C_FLAG_RXNE ((uint32_t)0x10000040)

Definition at line 277 of file stm32l1xx_i2c.h.

#define I2C_FLAG_SB ((uint32_t)0x10000001)

Definition at line 282 of file stm32l1xx_i2c.h.

#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)

SR1 register flags.

Definition at line 269 of file stm32l1xx_i2c.h.

#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)

Definition at line 259 of file stm32l1xx_i2c.h.

#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)

Definition at line 258 of file stm32l1xx_i2c.h.

#define I2C_FLAG_STOPF ((uint32_t)0x10000010)

Definition at line 278 of file stm32l1xx_i2c.h.

#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)

Definition at line 270 of file stm32l1xx_i2c.h.

#define I2C_FLAG_TRA ((uint32_t)0x00040000)

Definition at line 261 of file stm32l1xx_i2c.h.

#define I2C_FLAG_TXE ((uint32_t)0x10000080)

Definition at line 276 of file stm32l1xx_i2c.h.

#define IS_I2C_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))

Definition at line 284 of file stm32l1xx_i2c.h.

Referenced by I2C_ClearFlag().

#define IS_I2C_GET_FLAG ( FLAG )
Value:
(((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
                               ((FLAG) == I2C_FLAG_SB))

Definition at line 286 of file stm32l1xx_i2c.h.

Referenced by I2C_GetFlagStatus().


STM32L1xx Standard Peripherals Firmware Library: I2C_Events

Defines

I2C_Events

I2C_Exported_Constants

Defines

#define | I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)
Communication events.
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)
#define | I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)
#define | I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)
=============================================================================== I2C Master Events (Events grouped in order of communication) ===============================================================================
#define | I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)
#define | I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)
Address Acknowledge.
#define | I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)
#define | I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)
Communication events.
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)
#define | I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)
#define | I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)
=============================================================================== I2C Slave Events (Events grouped in order of communication) ===============================================================================
#define | I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)
#define | I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)
#define | I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)
#define | I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)
#define | IS_I2C_EVENT(EVENT)

Define Documentation

#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)

Communication events.

If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures:

1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function).

2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar:

  • EV8 means that the data has been written in the data register and is being shifted out.
  • EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensure more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation).
Note:
In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.

Definition at line 384 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)

Definition at line 390 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)

Definition at line 388 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)

Definition at line 351 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)

=============================================================================== I2C Master Events (Events grouped in order of communication) ===============================================================================

Communication start

After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating).

Definition at line 320 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)

Definition at line 349 of file stm32l1xx_i2c.h.

#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)

Address Acknowledge.

After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set:

1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.

2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set

3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6.

Definition at line 348 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)

Definition at line 475 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)

Communication events.

Wait on one of these events when EV1 has already been checked and:

  • Slave RECEIVER mode:
    • EV2: When the application is expecting a data byte to be received.
    • EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped.
  • Slave Transmitter mode:
    • EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of transfer.
    • EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus.
Note:
In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.

Definition at line 466 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)

Definition at line 472 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)

Definition at line 473 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)

Definition at line 435 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)

=============================================================================== I2C Slave Events (Events grouped in order of communication) ===============================================================================

Communication start events

Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set :

1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER).

2) In case the address sent by the master matches the second address of the peripheral (configured by the function I2C_OwnAddress2Config() and enabled by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED (where XXX could be TRANSMITTER or RECEIVER) are set.

3) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.

Definition at line 427 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)

Definition at line 431 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)

Definition at line 468 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)

Definition at line 428 of file stm32l1xx_i2c.h.

#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)

Definition at line 432 of file stm32l1xx_i2c.h.

#define IS_I2C_EVENT ( EVENT )
Value:
(((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))

Definition at line 483 of file stm32l1xx_i2c.h.

Referenced by I2C_CheckEvent().


STM32L1xx Standard Peripherals Firmware Library: I2C_own_address1

Defines

I2C_own_address1

I2C_Exported_Constants

Defines

#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)

Define Documentation

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x3FF)

Definition at line 511 of file stm32l1xx_i2c.h.

Referenced by I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_clock_speed

Defines

I2C_clock_speed

I2C_Exported_Constants

Defines

#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))

Define Documentation

#define IS_I2C_CLOCK_SPEED ( SPEED ) (((SPEED) >= 0x1) && ((SPEED) <= 400000))

Definition at line 520 of file stm32l1xx_i2c.h.

Referenced by I2C_Init().


STM32L1xx Standard Peripherals Firmware Library: I2C_Exported_Constants

Modules | Defines

I2C_Exported_Constants

I2C

Modules

I2C_mode
I2C_duty_cycle_in_fast_mode
I2C_acknowledgement
I2C_transfer_direction
I2C_acknowledged_address
I2C_registers
I2C_SMBus_alert_pin_level
I2C_PEC_position
I2C_NACK_position
I2C_interrupts_definition
I2C_flags_definition
I2C_Events
I2C_own_address1
I2C_clock_speed

Defines

#define IS_I2C_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_I2C_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == I2C1) || \
                                   ((PERIPH) == I2C2))

Definition at line 79 of file stm32l1xx_i2c.h.

Referenced by I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_DualAddressCmd(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_GetPEC(), I2C_Init(), I2C_ITConfig(), I2C_NACKPositionConfig(), I2C_OwnAddress2Config(), I2C_PECPositionConfig(), I2C_ReadRegister(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SMBusAlertConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), and I2C_TransmitPEC().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

I2C_Private_Functions

Initialization and Configuration functions. More...

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================

Function Documentation

void I2C_AcknowledgeConfig | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C acknowledge feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 357 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ACK, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_ARPCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C ARP.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 505 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENARP, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_Cmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 285 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_PE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_DeInit ( I2C_TypeDef * I2Cx )

Deinitializes the I2Cx peripheral registers to their default reset values.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 121 of file stm32l1xx_i2c.c.

References DISABLE, ENABLE, I2C1, IS_I2C_ALL_PERIPH, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, and RCC_APB1PeriphResetCmd().

void I2C_DualAddressCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C dual addressing mode.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 407 of file stm32l1xx_i2c.c.

References DISABLE, I2C_OAR2_ENDUAL, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and I2C_TypeDef::OAR2.

void I2C_FastModeDutyCycleConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_DutyCycle
 | ) |  |

Selects the specified I2C fast mode duty cycle.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_DutyCycle,: specifies the fast mode duty cycle. This parameter can be one of the following values:

  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
Return values:
None

Definition at line 555 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CCR, I2C_DutyCycle_16_9, I2C_DutyCycle_2, IS_I2C_ALL_PERIPH, and IS_I2C_DUTY_CYCLE.

void I2C_GeneralCallCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C general call feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C General call. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 431 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENGC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTART | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication START condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 309 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_START, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTOP | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication STOP condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 333 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_STOP, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

Note:
To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz.
Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_InitStruct,: pointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
Return values:
None

Definition at line 152 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CCR, I2C_TypeDef::CR1, CR1_CLEAR_MASK, I2C_TypeDef::CR2, I2C_InitTypeDef::I2C_Ack, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_CCR_CCR, I2C_CCR_FS, I2C_InitTypeDef::I2C_ClockSpeed, I2C_CR1_PE, I2C_CR2_FREQ, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_16_9, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_InitTypeDef::I2C_OwnAddress1, IS_I2C_ACK_STATE, IS_I2C_ACKNOWLEDGE_ADDRESS, IS_I2C_ALL_PERIPH, IS_I2C_CLOCK_SPEED, IS_I2C_DUTY_CYCLE, IS_I2C_MODE, IS_I2C_OWN_ADDRESS1, I2C_TypeDef::OAR1, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_GetClocksFreq(), and I2C_TypeDef::TRISE.

void I2C_OwnAddress2Config | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address
 | ) |  |

Configures the specified I2C own address2.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the 7bit I2C own address2.
Return values:
None.

Definition at line 380 of file stm32l1xx_i2c.c.

References I2C_OAR2_ADD2, IS_I2C_ALL_PERIPH, and I2C_TypeDef::OAR2.

void I2C_Send7bitAddress | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address,
 |  | uint8_t | I2C_Direction
 | ) |  |

Transmits the address byte to select the slave device.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the slave address which will be transmitted.
I2C_Direction,: specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values:

  • I2C_Direction_Transmitter: Transmitter mode
  • I2C_Direction_Receiver: Receiver mode
Return values:
None.

Definition at line 582 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, I2C_Direction_Transmitter, I2C_OAR1_ADD0, IS_I2C_ALL_PERIPH, and IS_I2C_DIRECTION.

void I2C_SMBusAlertConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_SMBusAlert
 | ) |  |

Drives the SMBusAlert pin high or low for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_SMBusAlert,: specifies SMBAlert pin level. This parameter can be one of the following values:

  • I2C_SMBusAlert_Low: SMBAlert pin driven low
  • I2C_SMBusAlert_High: SMBAlert pin driven high
Return values:
None

Definition at line 481 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_SMBusAlert_High, I2C_SMBusAlert_Low, IS_I2C_ALL_PERIPH, and IS_I2C_SMBUS_ALERT.

void I2C_SoftwareResetCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C software reset.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 455 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_SWRST, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StretchClockCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C Clock stretching.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 529 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_NOSTRETCH, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StructInit ( I2C_InitTypeDef * I2C_InitStruct )

Fills each I2C_InitStruct member with its default value.

Parameters:
I2C_InitStruct,: pointer to an I2C_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 261 of file stm32l1xx_i2c.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Disable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, and I2C_InitTypeDef::I2C_OwnAddress1.


STM32L1xx Standard Peripherals Firmware Library: Data transfers functions

Functions

Data transfers functions

I2C_Private_Functions

Data transfers functions. More...

Functions

void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.

Detailed Description

Data transfers functions.

 ===============================================================================
                    ##### Data transfers functions #####
 ===============================================================================

Function Documentation

void I2C_NACKPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_NACKPosition
 | ) |  |

Selects the specified I2C NACK position in master receiver mode.

This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_NACKPosition,: specifies the NACK position. This parameter can be one of the following values:

  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
Note:
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
Return values:
None

Definition at line 665 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_NACKPosition_Current, I2C_NACKPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_NACK_POSITION.

uint8_t I2C_ReceiveData ( I2C_TypeDef * I2Cx )

Returns the most recent received data by the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The value of the received data.

Definition at line 637 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

void I2C_SendData | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Sends a data byte through the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Data,: Byte to be transmitted.
Return values:
None

Definition at line 624 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: PEC management functions

Functions

PEC management functions

I2C_Private_Functions

PEC management functions. More...

Functions

void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

PEC management functions.

 ===============================================================================
                    ##### PEC management functions #####
 ===============================================================================

Function Documentation

void I2C_CalculatePEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the PEC value calculation of the transferred bytes.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENPEC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

uint8_t I2C_GetPEC ( I2C_TypeDef * I2Cx )

Returns the PEC value for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The PEC value.

Definition at line 782 of file stm32l1xx_i2c.c.

References IS_I2C_ALL_PERIPH, and I2C_TypeDef::SR2.

void I2C_PECPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_PECPosition
 | ) |  |

Selects the specified I2C PEC position.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_PECPosition,: specifies the PEC position. This parameter can be one of the following values:

  • I2C_PECPosition_Next: indicates that the next byte is PEC
  • I2C_PECPosition_Current: indicates that current byte is PEC
Note:
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
Return values:
None

Definition at line 736 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_PECPosition_Current, I2C_PECPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_PEC_POSITION.

void I2C_TransmitPEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C PEC transfer.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 707 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_PEC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: DMA transfers management functions

Functions

DMA transfers management functions

I2C_Private_Functions

DMA transfers management functions. More...

Functions

void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.

Detailed Description

DMA transfers management functions.

 ===============================================================================
               ##### DMA transfers management functions #####
 ===============================================================================
  [..] This section provides functions allowing to configure the I2C DMA channels
       requests.

Function Documentation

void I2C_DMACmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C DMA requests.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 814 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, I2C_CR2_DMAEN, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_DMALastTransferCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Specifies that the next DMA transfer is the last one.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 838 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, I2C_CR2_LAST, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Interrupts events and flags management functions

Functions

Interrupts events and flags management functions

I2C_Private_Functions

Interrupts, events and flags management functions. More...

Functions

ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
Checks whether the last I2Cx Event is equal to the one passed as parameter.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.

Detailed Description

Interrupts, events and flags management functions.

 ===============================================================================
        ##### Interrupts, events and flags management functions #####
 ===============================================================================
    [..] This section provides functions allowing to configure the I2C Interrupts
         sources and check or clear the flags or pending bits status.
         The user should identify which mode will be used in his application to manage
         the communication: Polling mode, Interrupt mode or DMA mode.

                ##### I2C State Monitoring Functions #####
 ===============================================================================
    [..]This I2C driver provides three different ways for I2C state monitoring
        depending on the application requirements and constraints:

     ***. Basic state monitoring (Using I2C_CheckEvent() function) ***
     -----------------------------------------------------------------
    [..]It compares the status registers (SR1 and SR2) content to a given event
        (can be the combination of one or more flags).
        It returns SUCCESS if the current status includes the given flags
        and returns ERROR if one or more flags are missing in the current status.

    (+) When to use
        (++) This function is suitable for most applications as well as for
             startup activity since the events are fully described in the product
             reference manual (RM0038).
        (++) It is also suitable for users who need to define their own events.
    (+) Limitations
        (++) If an error occurs (ie. error flags are set besides to the monitored
             flags), the I2C_CheckEvent() function may return SUCCESS despite
             the communication hold or corrupted real state.
             In this case, it is advised to use error interrupts to monitor
             the error events and handle them in the interrupt IRQ handler.
        -@@- For error management, it is advised to use the following functions:
             (+@@) I2C_ITConfig() to configure and enable the error interrupts
                   (I2C_IT_ERR).
             (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
                   Where x is the peripheral instance (I2C1, I2C2 ...).
             (+@@) I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the
                   I2Cx_ER_IRQHandler() function in order to determine which error occurred.
             (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
                   and/or I2C_GenerateStop() in order to clear the error flag and source
                   and return to correct  communication status.

     *** Advanced state monitoring (Using the function I2C_GetLastEvent()) ***
     -------------------------------------------------------------------------
    [..] Using the function I2C_GetLastEvent() which returns the image of both status
        registers in a single word (uint32_t) (Status Register 2 value is shifted left
        by 16 bits and concatenated to Status Register 1).

    (+) When to use
       (++) This function is suitable for the same applications above but it
            allows to overcome the mentioned limitation of I2C_GetFlagStatus()
            function.
       (++) The returned value could be compared to events already defined in
            the library (stm32l1xx_i2c.h) or to custom values defined by user.
            This function is suitable when multiple flags are monitored at the
            same time.
       (++) At the opposite of I2C_CheckEvent() function, this function allows
            user to choose when an event is accepted (when all events flags are
            set and no other flags are set or just when the needed flags are set
            like I2C_CheckEvent() function.

     (+) Limitations
         (++) User may need to define his own events.
         (++) Same remark concerning the error management is applicable for this
              function if user decides to check only regular communication flags
              (and ignores error flags).

    *** Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ***
    ----------------------------------------------------------------------------
    [..] Using the function I2C_GetFlagStatus() which simply returns the status of
         one single flag (ie. I2C_FLAG_RXNE ...).
         (+) When to use
             (++) This function could be used for specific applications or in debug
                  phase.
             (++) It is suitable when only one flag checking is needed (most I2C
                  events are monitored through multiple flags).
         (+) Limitations:
             (++) When calling this function, the Status register is accessed.
                  Some flags are cleared when the status register is accessed.
                  So checking the status of one Flag, may clear other ones.
             (++) Function may need to be called twice or more in order to monitor
                  one single event.

    [..] For detailed description of Events, please refer to section I2C_Events in
         stm32l1xx_i2c.h file.

Function Documentation

ErrorStatus I2C_CheckEvent | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_EVENT
 | ) |  |

Checks whether the last I2Cx Event is equal to the one passed as parameter.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED: EV4
  • I2C_EVENT_MASTER_MODE_SELECT: EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
Note:
For detailed description of Events, please refer to section I2C_Events in stm32l1xx_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 1055 of file stm32l1xx_i2c.c.

References ERROR, FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_EVENT, I2C_TypeDef::SR1, I2C_TypeDef::SR2, and SUCCESS.

void I2C_ClearFlag | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Clears the I2Cx's pending flags.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Note:
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1235 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_FLAG, and I2C_TypeDef::SR1.

void I2C_ClearITPendingBit | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Clears the I2Cx's interrupt pending bits.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_IT_SMBALERT: SMBus Alert interrupt
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
  • I2C_IT_PECERR: PEC error in reception interrupt
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
  • I2C_IT_AF: Acknowledge failure interrupt
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
  • I2C_IT_BERR: Bus error interrupt
Note:
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1330 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_IT, and I2C_TypeDef::SR1.

FlagStatus I2C_GetFlagStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Checks whether the specified I2C flag is set or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_DUALF: Dual flag (Slave mode)
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_FLAG_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 1158 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_GET_FLAG, RESET, and SET.

ITStatus I2C_GetITStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_IT_SMBALERT: SMBus Alert flag
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
  • I2C_IT_PECERR: PEC error in reception flag
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_IT_AF: Acknowledge failure flag
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
  • I2C_IT_BERR: Bus error flag
  • I2C_IT_TXE: Data register empty flag (Transmitter)
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
  • I2C_IT_BTF: Byte transfer finished flag
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_IT_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_IT (SET or RESET).

Definition at line 1269 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_GET_IT, ITEN_MASK, RESET, SET, and I2C_TypeDef::SR1.

uint32_t I2C_GetLastEvent ( I2C_TypeDef * I2Cx )

Returns the last I2Cx Event.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Note:
For detailed description of Events, please refer to section I2C_Events in stm32l1xx_i2c.h file.
Return values:
The last event

Definition at line 1103 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, I2C_TypeDef::SR1, and I2C_TypeDef::SR2.

void I2C_ITConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupts.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • I2C_IT_BUF: Buffer interrupt mask
  • I2C_IT_EVT: Event interrupt mask
  • I2C_IT_ERR: Error interrupt mask
NewState,: new state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 998 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and IS_I2C_CONFIG_IT.

uint16_t I2C_ReadRegister | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | I2C_Register
 | ) |  |

Reads the specified I2C register and returns its value.

Parameters:
I2C_Register,: specifies the register to read. This parameter can be one of the following values:

  • I2C_Register_CR1: CR1 register.
  • I2C_Register_CR2: CR2 register.
  • I2C_Register_OAR1: OAR1 register.
  • I2C_Register_OAR2: OAR2 register.
  • I2C_Register_DR: DR register.
  • I2C_Register_SR1: SR1 register.
  • I2C_Register_SR2: SR2 register.
  • I2C_Register_CCR: CCR register.
  • I2C_Register_TRISE: TRISE register.
Return values:
The value of the read register.

Definition at line 971 of file stm32l1xx_i2c.c.

References IS_I2C_ALL_PERIPH, and IS_I2C_REGISTER.


STM32L1xx Standard Peripherals Firmware Library: I2C

Data Structures | Modules | Defines | Functions

I2C

STM32L1xx_StdPeriph_Driver

I2C driver modules. More...

Data Structures

struct | I2C_InitTypeDef
I2C Init structure definition. More...

Modules

I2C_Exported_Constants
I2C_Private_Functions

Defines

#define | CR1_CLEAR_MASK ((uint16_t)0xFBF5)
#define | FLAG_MASK ((uint32_t)0x00FFFFFF)
#define | ITEN_MASK ((uint32_t)0x07000000)

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
Checks whether the last I2Cx Event is equal to the one passed as parameter.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

I2C driver modules.

Define Documentation

#define CR1_CLEAR_MASK ((uint16_t)0xFBF5)

Definition at line 91 of file stm32l1xx_i2c.c.

Referenced by I2C_Init().

#define FLAG_MASK ((uint32_t)0x00FFFFFF)

Definition at line 92 of file stm32l1xx_i2c.c.

Referenced by I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_GetFlagStatus(), I2C_GetITStatus(), and I2C_GetLastEvent().

#define ITEN_MASK ((uint32_t)0x07000000)

Definition at line 93 of file stm32l1xx_i2c.c.

Referenced by I2C_GetITStatus().

Function Documentation

void I2C_AcknowledgeConfig | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C acknowledge feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 357 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ACK, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_ARPCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C ARP.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 505 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENARP, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_CalculatePEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the PEC value calculation of the transferred bytes.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENPEC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

ErrorStatus I2C_CheckEvent | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_EVENT
 | ) |  |

Checks whether the last I2Cx Event is equal to the one passed as parameter.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED: EV4
  • I2C_EVENT_MASTER_MODE_SELECT: EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
Note:
For detailed description of Events, please refer to section I2C_Events in stm32l1xx_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 1055 of file stm32l1xx_i2c.c.

References ERROR, FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_EVENT, I2C_TypeDef::SR1, I2C_TypeDef::SR2, and SUCCESS.

void I2C_ClearFlag | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Clears the I2Cx's pending flags.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Note:
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1235 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_FLAG, and I2C_TypeDef::SR1.

void I2C_ClearITPendingBit | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Clears the I2Cx's interrupt pending bits.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_IT_SMBALERT: SMBus Alert interrupt
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
  • I2C_IT_PECERR: PEC error in reception interrupt
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
  • I2C_IT_AF: Acknowledge failure interrupt
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
  • I2C_IT_BERR: Bus error interrupt
Note:
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1330 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_IT, and I2C_TypeDef::SR1.

void I2C_Cmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 285 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_PE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_DeInit ( I2C_TypeDef * I2Cx )

Deinitializes the I2Cx peripheral registers to their default reset values.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 121 of file stm32l1xx_i2c.c.

References DISABLE, ENABLE, I2C1, IS_I2C_ALL_PERIPH, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, and RCC_APB1PeriphResetCmd().

void I2C_DMACmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C DMA requests.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 814 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, I2C_CR2_DMAEN, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_DMALastTransferCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Specifies that the next DMA transfer is the last one.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 838 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, I2C_CR2_LAST, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_DualAddressCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C dual addressing mode.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 407 of file stm32l1xx_i2c.c.

References DISABLE, I2C_OAR2_ENDUAL, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and I2C_TypeDef::OAR2.

void I2C_FastModeDutyCycleConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_DutyCycle
 | ) |  |

Selects the specified I2C fast mode duty cycle.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_DutyCycle,: specifies the fast mode duty cycle. This parameter can be one of the following values:

  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
Return values:
None

Definition at line 555 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CCR, I2C_DutyCycle_16_9, I2C_DutyCycle_2, IS_I2C_ALL_PERIPH, and IS_I2C_DUTY_CYCLE.

void I2C_GeneralCallCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C general call feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C General call. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 431 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_ENGC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTART | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication START condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 309 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_START, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTOP | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication STOP condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 333 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_STOP, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

FlagStatus I2C_GetFlagStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Checks whether the specified I2C flag is set or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_DUALF: Dual flag (Slave mode)
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_FLAG_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 1158 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_GET_FLAG, RESET, and SET.

ITStatus I2C_GetITStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_IT_SMBALERT: SMBus Alert flag
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
  • I2C_IT_PECERR: PEC error in reception flag
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_IT_AF: Acknowledge failure flag
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
  • I2C_IT_BERR: Bus error flag
  • I2C_IT_TXE: Data register empty flag (Transmitter)
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
  • I2C_IT_BTF: Byte transfer finished flag
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_IT_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_IT (SET or RESET).

Definition at line 1269 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, FLAG_MASK, IS_I2C_ALL_PERIPH, IS_I2C_GET_IT, ITEN_MASK, RESET, SET, and I2C_TypeDef::SR1.

uint32_t I2C_GetLastEvent ( I2C_TypeDef * I2Cx )

Returns the last I2Cx Event.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Note:
For detailed description of Events, please refer to section I2C_Events in stm32l1xx_i2c.h file.
Return values:
The last event

Definition at line 1103 of file stm32l1xx_i2c.c.

References FLAG_MASK, IS_I2C_ALL_PERIPH, I2C_TypeDef::SR1, and I2C_TypeDef::SR2.

uint8_t I2C_GetPEC ( I2C_TypeDef * I2Cx )

Returns the PEC value for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The PEC value.

Definition at line 782 of file stm32l1xx_i2c.c.

References IS_I2C_ALL_PERIPH, and I2C_TypeDef::SR2.

void I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

Note:
To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz.
Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_InitStruct,: pointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
Return values:
None

Definition at line 152 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CCR, I2C_TypeDef::CR1, CR1_CLEAR_MASK, I2C_TypeDef::CR2, I2C_InitTypeDef::I2C_Ack, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_CCR_CCR, I2C_CCR_FS, I2C_InitTypeDef::I2C_ClockSpeed, I2C_CR1_PE, I2C_CR2_FREQ, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_16_9, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_InitTypeDef::I2C_OwnAddress1, IS_I2C_ACK_STATE, IS_I2C_ACKNOWLEDGE_ADDRESS, IS_I2C_ALL_PERIPH, IS_I2C_CLOCK_SPEED, IS_I2C_DUTY_CYCLE, IS_I2C_MODE, IS_I2C_OWN_ADDRESS1, I2C_TypeDef::OAR1, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_GetClocksFreq(), and I2C_TypeDef::TRISE.

void I2C_ITConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupts.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • I2C_IT_BUF: Buffer interrupt mask
  • I2C_IT_EVT: Event interrupt mask
  • I2C_IT_ERR: Error interrupt mask
NewState,: new state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 998 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and IS_I2C_CONFIG_IT.

void I2C_NACKPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_NACKPosition
 | ) |  |

Selects the specified I2C NACK position in master receiver mode.

This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_NACKPosition,: specifies the NACK position. This parameter can be one of the following values:

  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
Note:
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
Return values:
None

Definition at line 665 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_NACKPosition_Current, I2C_NACKPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_NACK_POSITION.

void I2C_OwnAddress2Config | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address
 | ) |  |

Configures the specified I2C own address2.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the 7bit I2C own address2.
Return values:
None.

Definition at line 380 of file stm32l1xx_i2c.c.

References I2C_OAR2_ADD2, IS_I2C_ALL_PERIPH, and I2C_TypeDef::OAR2.

void I2C_PECPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_PECPosition
 | ) |  |

Selects the specified I2C PEC position.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_PECPosition,: specifies the PEC position. This parameter can be one of the following values:

  • I2C_PECPosition_Next: indicates that the next byte is PEC
  • I2C_PECPosition_Current: indicates that current byte is PEC
Note:
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
Return values:
None

Definition at line 736 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_PECPosition_Current, I2C_PECPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_PEC_POSITION.

uint16_t I2C_ReadRegister | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | I2C_Register
 | ) |  |

Reads the specified I2C register and returns its value.

Parameters:
I2C_Register,: specifies the register to read. This parameter can be one of the following values:

  • I2C_Register_CR1: CR1 register.
  • I2C_Register_CR2: CR2 register.
  • I2C_Register_OAR1: OAR1 register.
  • I2C_Register_OAR2: OAR2 register.
  • I2C_Register_DR: DR register.
  • I2C_Register_SR1: SR1 register.
  • I2C_Register_SR2: SR2 register.
  • I2C_Register_CCR: CCR register.
  • I2C_Register_TRISE: TRISE register.
Return values:
The value of the read register.

Definition at line 971 of file stm32l1xx_i2c.c.

References IS_I2C_ALL_PERIPH, and IS_I2C_REGISTER.

uint8_t I2C_ReceiveData ( I2C_TypeDef * I2Cx )

Returns the most recent received data by the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The value of the received data.

Definition at line 637 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

void I2C_Send7bitAddress | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address,
 |  | uint8_t | I2C_Direction
 | ) |  |

Transmits the address byte to select the slave device.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the slave address which will be transmitted.
I2C_Direction,: specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values:

  • I2C_Direction_Transmitter: Transmitter mode
  • I2C_Direction_Receiver: Receiver mode
Return values:
None.

Definition at line 582 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, I2C_Direction_Transmitter, I2C_OAR1_ADD0, IS_I2C_ALL_PERIPH, and IS_I2C_DIRECTION.

void I2C_SendData | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Sends a data byte through the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Data,: Byte to be transmitted.
Return values:
None

Definition at line 624 of file stm32l1xx_i2c.c.

References I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

void I2C_SMBusAlertConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_SMBusAlert
 | ) |  |

Drives the SMBusAlert pin high or low for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_SMBusAlert,: specifies SMBAlert pin level. This parameter can be one of the following values:

  • I2C_SMBusAlert_Low: SMBAlert pin driven low
  • I2C_SMBusAlert_High: SMBAlert pin driven high
Return values:
None

Definition at line 481 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, I2C_SMBusAlert_High, I2C_SMBusAlert_Low, IS_I2C_ALL_PERIPH, and IS_I2C_SMBUS_ALERT.

void I2C_SoftwareResetCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C software reset.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 455 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_SWRST, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StretchClockCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C Clock stretching.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 529 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_NOSTRETCH, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StructInit ( I2C_InitTypeDef * I2C_InitStruct )

Fills each I2C_InitStruct member with its default value.

Parameters:
I2C_InitStruct,: pointer to an I2C_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 261 of file stm32l1xx_i2c.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Disable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, and I2C_InitTypeDef::I2C_OwnAddress1.

void I2C_TransmitPEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C PEC transfer.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 707 of file stm32l1xx_i2c.c.

References I2C_TypeDef::CR1, DISABLE, I2C_CR1_PEC, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: I2C_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2C_InitTypeDef Struct Reference
I2C

I2C Init structure definition. More...

#include <stm32l1xx_i2c.h>

Data Fields

uint16_t | I2C_Ack
uint16_t | I2C_AcknowledgedAddress
uint32_t | I2C_ClockSpeed
uint16_t | I2C_DutyCycle
uint16_t | I2C_Mode
uint16_t | I2C_OwnAddress1

Detailed Description

I2C Init structure definition.

Definition at line 51 of file stm32l1xx_i2c.h.

Field Documentation

uint16_t I2C_InitTypeDef::I2C_Ack

Enables or disables the acknowledgement. This parameter can be a value of I2C_acknowledgement

Definition at line 65 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

uint16_t I2C_InitTypeDef::I2C_AcknowledgedAddress

Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of I2C_acknowledged_address

Definition at line 68 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

uint32_t I2C_InitTypeDef::I2C_ClockSpeed

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz

Definition at line 53 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

uint16_t I2C_InitTypeDef::I2C_DutyCycle

Specifies the I2C fast mode duty cycle. This parameter can be a value of I2C_duty_cycle_in_fast_mode

Definition at line 59 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

uint16_t I2C_InitTypeDef::I2C_Mode

Specifies the I2C mode. This parameter can be a value of I2C_mode

Definition at line 56 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

uint16_t I2C_InitTypeDef::I2C_OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 62 of file stm32l1xx_i2c.h.

Referenced by I2C_Init(), and I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_i2c.h


STM32L1xx Standard Peripherals Firmware Library: IWDG_WriteAccess

Defines

IWDG_WriteAccess

IWDG_Exported_Constants

Defines

#define | IS_IWDG_WRITE_ACCESS(ACCESS)
#define | IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define | IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Define Documentation

#define IS_IWDG_WRITE_ACCESS ( ACCESS )
Value:
(((ACCESS) == IWDG_WriteAccess_Enable) || \
                                      ((ACCESS) == IWDG_WriteAccess_Disable))

Definition at line 58 of file stm32l1xx_iwdg.h.

Referenced by IWDG_WriteAccessCmd().

#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)

Definition at line 57 of file stm32l1xx_iwdg.h.

#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Definition at line 56 of file stm32l1xx_iwdg.h.


STM32L1xx Standard Peripherals Firmware Library: IWDG_prescaler

Defines

IWDG_prescaler

IWDG_Exported_Constants

Defines

#define | IS_IWDG_PRESCALER(PRESCALER)
#define | IWDG_Prescaler_128 ((uint8_t)0x05)
#define | IWDG_Prescaler_16 ((uint8_t)0x02)
#define | IWDG_Prescaler_256 ((uint8_t)0x06)
#define | IWDG_Prescaler_32 ((uint8_t)0x03)
#define | IWDG_Prescaler_4 ((uint8_t)0x00)
#define | IWDG_Prescaler_64 ((uint8_t)0x04)
#define | IWDG_Prescaler_8 ((uint8_t)0x01)

Define Documentation

#define IS_IWDG_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == IWDG_Prescaler_4)  || \
                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
                                      ((PRESCALER) == IWDG_Prescaler_16) || \
                                      ((PRESCALER) == IWDG_Prescaler_32) || \
                                      ((PRESCALER) == IWDG_Prescaler_64) || \
                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
                                      ((PRESCALER) == IWDG_Prescaler_256))

Definition at line 75 of file stm32l1xx_iwdg.h.

Referenced by IWDG_SetPrescaler().

#define IWDG_Prescaler_128 ((uint8_t)0x05)

Definition at line 73 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_16 ((uint8_t)0x02)

Definition at line 70 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_256 ((uint8_t)0x06)

Definition at line 74 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_32 ((uint8_t)0x03)

Definition at line 71 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_4 ((uint8_t)0x00)

Definition at line 68 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_64 ((uint8_t)0x04)

Definition at line 72 of file stm32l1xx_iwdg.h.

#define IWDG_Prescaler_8 ((uint8_t)0x01)

Definition at line 69 of file stm32l1xx_iwdg.h.


STM32L1xx Standard Peripherals Firmware Library: IWDG_Flag

Defines

IWDG_Flag

IWDG_Exported_Constants

Defines

#define | IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define | IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
#define | IWDG_FLAG_PVU ((uint16_t)0x0001)
#define | IWDG_FLAG_RVU ((uint16_t)0x0002)

Define Documentation

#define IS_IWDG_FLAG ( FLAG ) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))

Definition at line 92 of file stm32l1xx_iwdg.h.

Referenced by IWDG_GetFlagStatus().

#define IS_IWDG_RELOAD ( RELOAD ) ((RELOAD) <= 0xFFF)

Definition at line 93 of file stm32l1xx_iwdg.h.

Referenced by IWDG_SetReload().

#define IWDG_FLAG_PVU ((uint16_t)0x0001)

Definition at line 90 of file stm32l1xx_iwdg.h.

#define IWDG_FLAG_RVU ((uint16_t)0x0002)

Definition at line 91 of file stm32l1xx_iwdg.h.


STM32L1xx Standard Peripherals Firmware Library: Prescaler and Counter configuration functions

Functions

Prescaler and Counter configuration functions

IWDG_Private_Functions

Prescaler and Counter configuration functions. More...

Functions

void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

Prescaler and Counter configuration functions.

  ==============================================================================
            ##### Prescaler and Counter configuration functions #####
  ==============================================================================

Function Documentation

void IWDG_ReloadCounter ( void )

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 175 of file stm32l1xx_iwdg.c.

References IWDG, and KR_KEY_RELOAD.

void IWDG_SetPrescaler ( uint8_t IWDG_Prescaler )

Sets IWDG Prescaler value.

Parameters:
IWDG_Prescaler,: specifies the IWDG Prescaler value. This parameter can be one of the following values:

  • IWDG_Prescaler_4: IWDG prescaler set to 4
  • IWDG_Prescaler_8: IWDG prescaler set to 8
  • IWDG_Prescaler_16: IWDG prescaler set to 16
  • IWDG_Prescaler_32: IWDG prescaler set to 32
  • IWDG_Prescaler_64: IWDG prescaler set to 64
  • IWDG_Prescaler_128: IWDG prescaler set to 128
  • IWDG_Prescaler_256: IWDG prescaler set to 256
Return values:
None

Definition at line 149 of file stm32l1xx_iwdg.c.

References IS_IWDG_PRESCALER, and IWDG.

void IWDG_SetReload ( uint16_t Reload )

Sets IWDG Reload value.

Parameters:
Reload,: specifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
Return values:
None

Definition at line 162 of file stm32l1xx_iwdg.c.

References IS_IWDG_RELOAD, and IWDG.

void IWDG_WriteAccessCmd ( uint16_t IWDG_WriteAccess )

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
IWDG_WriteAccess,: new state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:

  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
Return values:
None

Definition at line 129 of file stm32l1xx_iwdg.c.

References IS_IWDG_WRITE_ACCESS, and IWDG.


STM32L1xx Standard Peripherals Firmware Library: IWDG activation function

Functions

IWDG activation function

IWDG_Private_Functions

IWDG activation function. More...

Functions

void IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

Detailed Description

IWDG activation function.

  ==============================================================================
                          ##### IWDG activation function #####
  ==============================================================================

Function Documentation

void IWDG_Enable ( void )

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None.
Return values:
None.

Definition at line 201 of file stm32l1xx_iwdg.c.

References IWDG, and KR_KEY_ENABLE.


STM32L1xx Standard Peripherals Firmware Library: Flag management function

Functions

Flag management function

IWDG_Private_Functions

Flag management function. More...

Functions

FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.

Detailed Description

Flag management function.

 ===============================================================================
                      ##### Flag management function #####
 ===============================================================================

Function Documentation

FlagStatus IWDG_GetFlagStatus ( uint16_t IWDG_FLAG )

Checks whether the specified IWDG flag is set or not.

Parameters:
IWDG_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • IWDG_FLAG_PVU: Prescaler Value Update on going
  • IWDG_FLAG_RVU: Reload Value Update on going
Return values:
The new state of IWDG_FLAG (SET or RESET).

Definition at line 230 of file stm32l1xx_iwdg.c.

References IS_IWDG_FLAG, IWDG, RESET, and SET.


STM32L1xx Standard Peripherals Firmware Library: IWDG

Modules | Defines | Functions

IWDG

STM32L1xx_StdPeriph_Driver

IWDG driver modules. More...

Modules

IWDG_Exported_Constants
IWDG_Private_Functions

Defines

#define | KR_KEY_ENABLE ((uint16_t)0xCCCC)
#define | KR_KEY_RELOAD ((uint16_t)0xAAAA)

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

IWDG driver modules.

Define Documentation

#define KR_KEY_ENABLE ((uint16_t)0xCCCC)

Definition at line 98 of file stm32l1xx_iwdg.c.

Referenced by IWDG_Enable().

#define KR_KEY_RELOAD ((uint16_t)0xAAAA)

Definition at line 97 of file stm32l1xx_iwdg.c.

Referenced by IWDG_ReloadCounter().

Function Documentation

void IWDG_Enable ( void )

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None.
Return values:
None.

Definition at line 201 of file stm32l1xx_iwdg.c.

References IWDG, and KR_KEY_ENABLE.

FlagStatus IWDG_GetFlagStatus ( uint16_t IWDG_FLAG )

Checks whether the specified IWDG flag is set or not.

Parameters:
IWDG_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • IWDG_FLAG_PVU: Prescaler Value Update on going
  • IWDG_FLAG_RVU: Reload Value Update on going
Return values:
The new state of IWDG_FLAG (SET or RESET).

Definition at line 230 of file stm32l1xx_iwdg.c.

References IS_IWDG_FLAG, IWDG, RESET, and SET.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 175 of file stm32l1xx_iwdg.c.

References IWDG, and KR_KEY_RELOAD.

void IWDG_SetPrescaler ( uint8_t IWDG_Prescaler )

Sets IWDG Prescaler value.

Parameters:
IWDG_Prescaler,: specifies the IWDG Prescaler value. This parameter can be one of the following values:

  • IWDG_Prescaler_4: IWDG prescaler set to 4
  • IWDG_Prescaler_8: IWDG prescaler set to 8
  • IWDG_Prescaler_16: IWDG prescaler set to 16
  • IWDG_Prescaler_32: IWDG prescaler set to 32
  • IWDG_Prescaler_64: IWDG prescaler set to 64
  • IWDG_Prescaler_128: IWDG prescaler set to 128
  • IWDG_Prescaler_256: IWDG prescaler set to 256
Return values:
None

Definition at line 149 of file stm32l1xx_iwdg.c.

References IS_IWDG_PRESCALER, and IWDG.

void IWDG_SetReload ( uint16_t Reload )

Sets IWDG Reload value.

Parameters:
Reload,: specifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
Return values:
None

Definition at line 162 of file stm32l1xx_iwdg.c.

References IS_IWDG_RELOAD, and IWDG.

void IWDG_WriteAccessCmd ( uint16_t IWDG_WriteAccess )

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
IWDG_WriteAccess,: new state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:

  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
Return values:
None

Definition at line 129 of file stm32l1xx_iwdg.c.

References IS_IWDG_WRITE_ACCESS, and IWDG.


STM32L1xx Standard Peripherals Firmware Library: LCD_Prescaler

Defines

LCD_Prescaler

LCD_Exported_Constants

Defines

#define | IS_LCD_PRESCALER(PRESCALER)
#define | LCD_Prescaler_1 ((uint32_t)0x00000000)
#define | LCD_Prescaler_1024 ((uint32_t)0x02800000)
#define | LCD_Prescaler_128 ((uint32_t)0x01C00000)
#define | LCD_Prescaler_16 ((uint32_t)0x01000000)
#define | LCD_Prescaler_16384 ((uint32_t)0x03800000)
#define | LCD_Prescaler_2 ((uint32_t)0x00400000)
#define | LCD_Prescaler_2048 ((uint32_t)0x02C00000)
#define | LCD_Prescaler_256 ((uint32_t)0x02000000)
#define | LCD_Prescaler_32 ((uint32_t)0x01400000)
#define | LCD_Prescaler_32768 ((uint32_t)0x03C00000)
#define | LCD_Prescaler_4 ((uint32_t)0x00800000)
#define | LCD_Prescaler_4096 ((uint32_t)0x03000000)
#define | LCD_Prescaler_512 ((uint32_t)0x02400000)
#define | LCD_Prescaler_64 ((uint32_t)0x01800000)
#define | LCD_Prescaler_8 ((uint32_t)0x00C00000)
#define | LCD_Prescaler_8192 ((uint32_t)0x03400000)

Define Documentation

#define IS_LCD_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == LCD_Prescaler_1) || \
                                        ((PRESCALER) == LCD_Prescaler_2) || \
                                        ((PRESCALER) == LCD_Prescaler_4) || \
                                        ((PRESCALER) == LCD_Prescaler_8) || \
                                        ((PRESCALER) == LCD_Prescaler_16) || \
                                        ((PRESCALER) == LCD_Prescaler_32) || \
                                        ((PRESCALER) == LCD_Prescaler_64) || \
                                        ((PRESCALER) == LCD_Prescaler_128) || \
                                        ((PRESCALER) == LCD_Prescaler_256) || \
                                        ((PRESCALER) == LCD_Prescaler_512) || \
                                        ((PRESCALER) == LCD_Prescaler_1024) || \
                                        ((PRESCALER) == LCD_Prescaler_2048) || \
                                        ((PRESCALER) == LCD_Prescaler_4096) || \
                                        ((PRESCALER) == LCD_Prescaler_8192) || \
                                        ((PRESCALER) == LCD_Prescaler_16384) || \
                                        ((PRESCALER) == LCD_Prescaler_32768))

Definition at line 93 of file stm32l1xx_lcd.h.

Referenced by LCD_Init().

#define LCD_Prescaler_1 ((uint32_t)0x00000000)

CLKPS = LCDCLK

Definition at line 76 of file stm32l1xx_lcd.h.

Referenced by LCD_StructInit().

#define LCD_Prescaler_1024 ((uint32_t)0x02800000)

CLKPS = LCDCLK/1024

Definition at line 86 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_128 ((uint32_t)0x01C00000)

CLKPS = LCDCLK/128

Definition at line 83 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_16 ((uint32_t)0x01000000)

CLKPS = LCDCLK/16

Definition at line 80 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_16384 ((uint32_t)0x03800000)

CLKPS = LCDCLK/16384

Definition at line 90 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_2 ((uint32_t)0x00400000)

CLKPS = LCDCLK/2

Definition at line 77 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_2048 ((uint32_t)0x02C00000)

CLKPS = LCDCLK/2048

Definition at line 87 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_256 ((uint32_t)0x02000000)

CLKPS = LCDCLK/256

Definition at line 84 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_32 ((uint32_t)0x01400000)

CLKPS = LCDCLK/32

Definition at line 81 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_32768 ((uint32_t)0x03C00000)

CLKPS = LCDCLK/32768

Definition at line 91 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_4 ((uint32_t)0x00800000)

CLKPS = LCDCLK/4

Definition at line 78 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_4096 ((uint32_t)0x03000000)

CLKPS = LCDCLK/4096

Definition at line 88 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_512 ((uint32_t)0x02400000)

CLKPS = LCDCLK/512

Definition at line 85 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_64 ((uint32_t)0x01800000)

CLKPS = LCDCLK/64

Definition at line 82 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_8 ((uint32_t)0x00C00000)

CLKPS = LCDCLK/8

Definition at line 79 of file stm32l1xx_lcd.h.

#define LCD_Prescaler_8192 ((uint32_t)0x03400000)

CLKPS = LCDCLK/8192

Definition at line 89 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_Divider

Defines

LCD_Divider

LCD_Exported_Constants

Defines

#define | IS_LCD_DIVIDER(DIVIDER)
#define | LCD_Divider_16 ((uint32_t)0x00000000)
#define | LCD_Divider_17 ((uint32_t)0x00040000)
#define | LCD_Divider_18 ((uint32_t)0x00080000)
#define | LCD_Divider_19 ((uint32_t)0x000C0000)
#define | LCD_Divider_20 ((uint32_t)0x00100000)
#define | LCD_Divider_21 ((uint32_t)0x00140000)
#define | LCD_Divider_22 ((uint32_t)0x00180000)
#define | LCD_Divider_23 ((uint32_t)0x001C0000)
#define | LCD_Divider_24 ((uint32_t)0x00200000)
#define | LCD_Divider_25 ((uint32_t)0x00240000)
#define | LCD_Divider_26 ((uint32_t)0x00280000)
#define | LCD_Divider_27 ((uint32_t)0x002C0000)
#define | LCD_Divider_28 ((uint32_t)0x00300000)
#define | LCD_Divider_29 ((uint32_t)0x00340000)
#define | LCD_Divider_30 ((uint32_t)0x00380000)
#define | LCD_Divider_31 ((uint32_t)0x003C0000)

Define Documentation

#define IS_LCD_DIVIDER ( DIVIDER )
Value:
(((DIVIDER) == LCD_Divider_16) || \
                                    ((DIVIDER) == LCD_Divider_17) || \
                                    ((DIVIDER) == LCD_Divider_18) || \
                                    ((DIVIDER) == LCD_Divider_19) || \
                                    ((DIVIDER) == LCD_Divider_20) || \
                                    ((DIVIDER) == LCD_Divider_21) || \
                                    ((DIVIDER) == LCD_Divider_22) || \
                                    ((DIVIDER) == LCD_Divider_23) || \
                                    ((DIVIDER) == LCD_Divider_24) || \
                                    ((DIVIDER) == LCD_Divider_25) || \
                                    ((DIVIDER) == LCD_Divider_26) || \
                                    ((DIVIDER) == LCD_Divider_27) || \
                                    ((DIVIDER) == LCD_Divider_28) || \
                                    ((DIVIDER) == LCD_Divider_29) || \
                                    ((DIVIDER) == LCD_Divider_30) || \
                                    ((DIVIDER) == LCD_Divider_31))

Definition at line 135 of file stm32l1xx_lcd.h.

Referenced by LCD_Init().

#define LCD_Divider_16 ((uint32_t)0x00000000)

LCD frequency = CLKPS/16

Definition at line 118 of file stm32l1xx_lcd.h.

Referenced by LCD_StructInit().

#define LCD_Divider_17 ((uint32_t)0x00040000)

LCD frequency = CLKPS/17

Definition at line 119 of file stm32l1xx_lcd.h.

#define LCD_Divider_18 ((uint32_t)0x00080000)

LCD frequency = CLKPS/18

Definition at line 120 of file stm32l1xx_lcd.h.

#define LCD_Divider_19 ((uint32_t)0x000C0000)

LCD frequency = CLKPS/19

Definition at line 121 of file stm32l1xx_lcd.h.

#define LCD_Divider_20 ((uint32_t)0x00100000)

LCD frequency = CLKPS/20

Definition at line 122 of file stm32l1xx_lcd.h.

#define LCD_Divider_21 ((uint32_t)0x00140000)

LCD frequency = CLKPS/21

Definition at line 123 of file stm32l1xx_lcd.h.

#define LCD_Divider_22 ((uint32_t)0x00180000)

LCD frequency = CLKPS/22

Definition at line 124 of file stm32l1xx_lcd.h.

#define LCD_Divider_23 ((uint32_t)0x001C0000)

LCD frequency = CLKPS/23

Definition at line 125 of file stm32l1xx_lcd.h.

#define LCD_Divider_24 ((uint32_t)0x00200000)

LCD frequency = CLKPS/24

Definition at line 126 of file stm32l1xx_lcd.h.

#define LCD_Divider_25 ((uint32_t)0x00240000)

LCD frequency = CLKPS/25

Definition at line 127 of file stm32l1xx_lcd.h.

#define LCD_Divider_26 ((uint32_t)0x00280000)

LCD frequency = CLKPS/26

Definition at line 128 of file stm32l1xx_lcd.h.

#define LCD_Divider_27 ((uint32_t)0x002C0000)

LCD frequency = CLKPS/27

Definition at line 129 of file stm32l1xx_lcd.h.

#define LCD_Divider_28 ((uint32_t)0x00300000)

LCD frequency = CLKPS/28

Definition at line 130 of file stm32l1xx_lcd.h.

#define LCD_Divider_29 ((uint32_t)0x00340000)

LCD frequency = CLKPS/29

Definition at line 131 of file stm32l1xx_lcd.h.

#define LCD_Divider_30 ((uint32_t)0x00380000)

LCD frequency = CLKPS/30

Definition at line 132 of file stm32l1xx_lcd.h.

#define LCD_Divider_31 ((uint32_t)0x003C0000)

LCD frequency = CLKPS/31

Definition at line 133 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_Duty

Defines

LCD_Duty

LCD_Exported_Constants

Defines

#define | IS_LCD_DUTY(DUTY)
#define | LCD_Duty_1_2 ((uint32_t)0x00000004)
#define | LCD_Duty_1_3 ((uint32_t)0x00000008)
#define | LCD_Duty_1_4 ((uint32_t)0x0000000C)
#define | LCD_Duty_1_8 ((uint32_t)0x00000010)
#define | LCD_Duty_Static ((uint32_t)0x00000000)

Define Documentation

#define IS_LCD_DUTY ( DUTY )
Value:
(((DUTY) == LCD_Duty_Static) || \
                           ((DUTY) == LCD_Duty_1_2) || \
                           ((DUTY) == LCD_Duty_1_3) || \
                           ((DUTY) == LCD_Duty_1_4) || \
                           ((DUTY) == LCD_Duty_1_8))

Definition at line 167 of file stm32l1xx_lcd.h.

Referenced by LCD_Init().

#define LCD_Duty_1_2 ((uint32_t)0x00000004)

1/2 duty

Definition at line 162 of file stm32l1xx_lcd.h.

#define LCD_Duty_1_3 ((uint32_t)0x00000008)

1/3 duty

Definition at line 163 of file stm32l1xx_lcd.h.

#define LCD_Duty_1_4 ((uint32_t)0x0000000C)

1/4 duty

Definition at line 164 of file stm32l1xx_lcd.h.

#define LCD_Duty_1_8 ((uint32_t)0x00000010)

1/4 duty

Definition at line 165 of file stm32l1xx_lcd.h.

#define LCD_Duty_Static ((uint32_t)0x00000000)

Static duty

Definition at line 161 of file stm32l1xx_lcd.h.

Referenced by LCD_StructInit().


STM32L1xx Standard Peripherals Firmware Library: LCD_Bias

Defines

LCD_Bias

LCD_Exported_Constants

Defines

#define | IS_LCD_BIAS(BIAS)
#define | LCD_Bias_1_2 LCD_CR_BIAS_0
#define | LCD_Bias_1_3 LCD_CR_BIAS_1
#define | LCD_Bias_1_4 ((uint32_t)0x00000000)

Define Documentation

#define IS_LCD_BIAS ( BIAS )
Value:
(((BIAS) == LCD_Bias_1_4) || \
                           ((BIAS) == LCD_Bias_1_2) || \
                           ((BIAS) == LCD_Bias_1_3))

Definition at line 186 of file stm32l1xx_lcd.h.

Referenced by LCD_Init().

#define LCD_Bias_1_2 LCD_CR_BIAS_0

1/2 Bias

Definition at line 183 of file stm32l1xx_lcd.h.

#define LCD_Bias_1_3 LCD_CR_BIAS_1

1/3 Bias

Definition at line 184 of file stm32l1xx_lcd.h.

#define LCD_Bias_1_4 ((uint32_t)0x00000000)

1/4 Bias

Definition at line 182 of file stm32l1xx_lcd.h.

Referenced by LCD_StructInit().


STM32L1xx Standard Peripherals Firmware Library: LCD_Voltage_Source

Defines

LCD_Voltage_Source

LCD_Exported_Constants

Defines

#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | LCD_VoltageSource_External LCD_CR_VSEL
#define | LCD_VoltageSource_Internal ((uint32_t)0x00000000)

Define Documentation

#define IS_LCD_VOLTAGE_SOURCE ( SOURCE )
Value:
(((SOURCE) == LCD_VoltageSource_Internal) || \
                                       ((SOURCE) == LCD_VoltageSource_External))

Definition at line 200 of file stm32l1xx_lcd.h.

Referenced by LCD_Init().

#define LCD_VoltageSource_External LCD_CR_VSEL

External voltage source for the LCD

Definition at line 198 of file stm32l1xx_lcd.h.

#define LCD_VoltageSource_Internal ((uint32_t)0x00000000)

Internal voltage source for the LCD

Definition at line 197 of file stm32l1xx_lcd.h.

Referenced by LCD_StructInit().


STM32L1xx Standard Peripherals Firmware Library: LCD_Interrupts

Defines

LCD_Interrupts

LCD_Exported_Constants

Defines

#define | IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))
#define | IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))
#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE

Define Documentation

#define IS_LCD_GET_IT ( IT ) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))

Definition at line 215 of file stm32l1xx_lcd.h.

Referenced by LCD_GetITStatus().

#define IS_LCD_IT ( IT ) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))

Definition at line 213 of file stm32l1xx_lcd.h.

Referenced by LCD_ClearITPendingBit(), and LCD_ITConfig().

#define LCD_IT_SOF LCD_FCR_SOFIE

Definition at line 210 of file stm32l1xx_lcd.h.

#define LCD_IT_UDD LCD_FCR_UDDIE

Definition at line 211 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_PulseOnDuration

Defines

LCD_PulseOnDuration

LCD_Exported_Constants

Defines

#define | IS_LCD_PULSE_ON_DURATION(DURATION)
#define | LCD_PulseOnDuration_0 ((uint32_t)0x00000000)
#define | LCD_PulseOnDuration_1 ((uint32_t)0x00000010)
#define | LCD_PulseOnDuration_2 ((uint32_t)0x00000020)
#define | LCD_PulseOnDuration_3 ((uint32_t)0x00000030)
#define | LCD_PulseOnDuration_4 ((uint32_t)0x00000040)
#define | LCD_PulseOnDuration_5 ((uint32_t)0x00000050)
#define | LCD_PulseOnDuration_6 ((uint32_t)0x00000060)
#define | LCD_PulseOnDuration_7 ((uint32_t)0x00000070)

Define Documentation

#define IS_LCD_PULSE_ON_DURATION ( DURATION )
Value:
(((DURATION) == LCD_PulseOnDuration_0) || \
                                            ((DURATION) == LCD_PulseOnDuration_1) || \
                                            ((DURATION) == LCD_PulseOnDuration_2) || \
                                            ((DURATION) == LCD_PulseOnDuration_3) || \
                                            ((DURATION) == LCD_PulseOnDuration_4) || \
                                            ((DURATION) == LCD_PulseOnDuration_5) || \
                                            ((DURATION) == LCD_PulseOnDuration_6) || \
                                            ((DURATION) == LCD_PulseOnDuration_7))

Definition at line 234 of file stm32l1xx_lcd.h.

Referenced by LCD_PulseOnDurationConfig().

#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000)

Pulse ON duration = 0 pulse

Definition at line 225 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010)

Pulse ON duration = 1/CK_PS

Definition at line 226 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020)

Pulse ON duration = 2/CK_PS

Definition at line 227 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030)

Pulse ON duration = 3/CK_PS

Definition at line 228 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040)

Pulse ON duration = 4/CK_PS

Definition at line 229 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050)

Pulse ON duration = 5/CK_PS

Definition at line 230 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060)

Pulse ON duration = 6/CK_PS

Definition at line 231 of file stm32l1xx_lcd.h.

#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070)

Pulse ON duration = 7/CK_PS

Definition at line 232 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_DeadTime

Defines

LCD_DeadTime

LCD_Exported_Constants

Defines

#define | IS_LCD_DEAD_TIME(TIME)
#define | LCD_DeadTime_0 ((uint32_t)0x00000000)
#define | LCD_DeadTime_1 ((uint32_t)0x00000080)
#define | LCD_DeadTime_2 ((uint32_t)0x00000100)
#define | LCD_DeadTime_3 ((uint32_t)0x00000180)
#define | LCD_DeadTime_4 ((uint32_t)0x00000200)
#define | LCD_DeadTime_5 ((uint32_t)0x00000280)
#define | LCD_DeadTime_6 ((uint32_t)0x00000300)
#define | LCD_DeadTime_7 ((uint32_t)0x00000380)

Define Documentation

#define IS_LCD_DEAD_TIME ( TIME )
Value:
(((TIME) == LCD_DeadTime_0) || \
                                ((TIME) == LCD_DeadTime_1) || \
                                ((TIME) == LCD_DeadTime_2) || \
                                ((TIME) == LCD_DeadTime_3) || \
                                ((TIME) == LCD_DeadTime_4) || \
                                ((TIME) == LCD_DeadTime_5) || \
                                ((TIME) == LCD_DeadTime_6) || \
                                ((TIME) == LCD_DeadTime_7))

Definition at line 260 of file stm32l1xx_lcd.h.

Referenced by LCD_DeadTimeConfig().

#define LCD_DeadTime_0 ((uint32_t)0x00000000)

No dead Time

Definition at line 251 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_1 ((uint32_t)0x00000080)

One Phase between different couple of Frame

Definition at line 252 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_2 ((uint32_t)0x00000100)

Two Phase between different couple of Frame

Definition at line 253 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_3 ((uint32_t)0x00000180)

Three Phase between different couple of Frame

Definition at line 254 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_4 ((uint32_t)0x00000200)

Four Phase between different couple of Frame

Definition at line 255 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_5 ((uint32_t)0x00000280)

Five Phase between different couple of Frame

Definition at line 256 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_6 ((uint32_t)0x00000300)

Six Phase between different couple of Frame

Definition at line 257 of file stm32l1xx_lcd.h.

#define LCD_DeadTime_7 ((uint32_t)0x00000380)

Seven Phase between different couple of Frame

Definition at line 258 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_BlinkMode

Defines

LCD_BlinkMode

LCD_Exported_Constants

Defines

#define | IS_LCD_BLINK_MODE(MODE)
#define | LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000)
#define | LCD_BlinkMode_Off ((uint32_t)0x00000000)
#define | LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000)
#define | LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000)

Define Documentation

#define IS_LCD_BLINK_MODE ( MODE )
Value:
(((MODE) == LCD_BlinkMode_Off) || \
                                 ((MODE) == LCD_BlinkMode_SEG0_COM0) || \
                                 ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \
                                 ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))

Definition at line 282 of file stm32l1xx_lcd.h.

Referenced by LCD_BlinkConfig().

#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000)

Blink enabled on all SEG and all COM (all pixels)

Definition at line 280 of file stm32l1xx_lcd.h.

#define LCD_BlinkMode_Off ((uint32_t)0x00000000)

Blink disabled

Definition at line 276 of file stm32l1xx_lcd.h.

#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000)

Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)

Definition at line 278 of file stm32l1xx_lcd.h.

#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000)

Blink enabled on SEG[0], COM[0] (1 pixel)

Definition at line 277 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_BlinkFrequency

Defines

LCD_BlinkFrequency

LCD_Exported_Constants

Defines

#define | IS_LCD_BLINK_FREQUENCY(FREQUENCY)
#define | LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000)
#define | LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000)
#define | LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000)
#define | LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000)
#define | LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000)
#define | LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000)
#define | LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000)
#define | LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000)

Define Documentation

#define IS_LCD_BLINK_FREQUENCY ( FREQUENCY )
Value:
(((FREQUENCY) == LCD_BlinkFrequency_Div8) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \
                                           ((FREQUENCY) == LCD_BlinkFrequency_Div1024))

Definition at line 303 of file stm32l1xx_lcd.h.

Referenced by LCD_BlinkConfig().

#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000)

The Blink frequency = fLCD/1024

Definition at line 301 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000)

The Blink frequency = fLCD/128

Definition at line 298 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000)

The Blink frequency = fLCD/16

Definition at line 295 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000)

The Blink frequency = fLCD/256

Definition at line 299 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000)

The Blink frequency = fLCD/32

Definition at line 296 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000)

The Blink frequency = fLCD/512

Definition at line 300 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000)

The Blink frequency = fLCD/64

Definition at line 297 of file stm32l1xx_lcd.h.

#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000)

The Blink frequency = fLCD/8

Definition at line 294 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_Contrast

Defines

LCD_Contrast

LCD_Exported_Constants

Defines

#define | IS_LCD_CONTRAST(CONTRAST)
#define | LCD_Contrast_Level_0 ((uint32_t)0x00000000)
#define | LCD_Contrast_Level_1 ((uint32_t)0x00000400)
#define | LCD_Contrast_Level_2 ((uint32_t)0x00000800)
#define | LCD_Contrast_Level_3 ((uint32_t)0x00000C00)
#define | LCD_Contrast_Level_4 ((uint32_t)0x00001000)
#define | LCD_Contrast_Level_5 ((uint32_t)0x00001400)
#define | LCD_Contrast_Level_6 ((uint32_t)0x00001800)
#define | LCD_Contrast_Level_7 ((uint32_t)0x00001C00)

Define Documentation

#define IS_LCD_CONTRAST ( CONTRAST )
Value:
(((CONTRAST) == LCD_Contrast_Level_0) || \
                                   ((CONTRAST) == LCD_Contrast_Level_1) || \
                                   ((CONTRAST) == LCD_Contrast_Level_2) || \
                                   ((CONTRAST) == LCD_Contrast_Level_3) || \
                                   ((CONTRAST) == LCD_Contrast_Level_4) || \
                                   ((CONTRAST) == LCD_Contrast_Level_5) || \
                                   ((CONTRAST) == LCD_Contrast_Level_6) || \
                                   ((CONTRAST) == LCD_Contrast_Level_7))

Definition at line 328 of file stm32l1xx_lcd.h.

Referenced by LCD_ContrastConfig().

#define LCD_Contrast_Level_0 ((uint32_t)0x00000000)

Maximum Voltage = 2.60V

Definition at line 319 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_1 ((uint32_t)0x00000400)

Maximum Voltage = 2.73V

Definition at line 320 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_2 ((uint32_t)0x00000800)

Maximum Voltage = 2.86V

Definition at line 321 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00)

Maximum Voltage = 2.99V

Definition at line 322 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_4 ((uint32_t)0x00001000)

Maximum Voltage = 3.12V

Definition at line 323 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_5 ((uint32_t)0x00001400)

Maximum Voltage = 3.25V

Definition at line 324 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_6 ((uint32_t)0x00001800)

Maximum Voltage = 3.38V

Definition at line 325 of file stm32l1xx_lcd.h.

#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00)

Maximum Voltage = 3.51V

Definition at line 326 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_Flag

Defines

LCD_Flag

LCD_Exported_Constants

Defines

#define | IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))
#define | IS_LCD_GET_FLAG(FLAG)
#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_UDR LCD_SR_UDR

Define Documentation

#define IS_LCD_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))

Definition at line 355 of file stm32l1xx_lcd.h.

Referenced by LCD_ClearFlag().

#define IS_LCD_GET_FLAG ( FLAG )
Value:
(((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \
                               ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \
                               ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))

Definition at line 351 of file stm32l1xx_lcd.h.

Referenced by LCD_GetFlagStatus().

#define LCD_FLAG_ENS LCD_SR_ENS

Definition at line 344 of file stm32l1xx_lcd.h.

#define LCD_FLAG_FCRSF LCD_SR_FCRSR

Definition at line 349 of file stm32l1xx_lcd.h.

Referenced by LCD_WaitForSynchro().

#define LCD_FLAG_RDY LCD_SR_RDY

Definition at line 348 of file stm32l1xx_lcd.h.

#define LCD_FLAG_SOF LCD_SR_SOF

Definition at line 345 of file stm32l1xx_lcd.h.

#define LCD_FLAG_UDD LCD_SR_UDD

Definition at line 347 of file stm32l1xx_lcd.h.

#define LCD_FLAG_UDR LCD_SR_UDR

Definition at line 346 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: LCD_RAMRegister

Defines

LCD_RAMRegister

LCD_Exported_Constants

Defines

#define | IS_LCD_RAM_REGISTER(REGISTER)
#define | LCD_RAMRegister_0 ((uint32_t)0x00000000)
#define | LCD_RAMRegister_1 ((uint32_t)0x00000001)
#define | LCD_RAMRegister_10 ((uint32_t)0x0000000A)
#define | LCD_RAMRegister_11 ((uint32_t)0x0000000B)
#define | LCD_RAMRegister_12 ((uint32_t)0x0000000C)
#define | LCD_RAMRegister_13 ((uint32_t)0x0000000D)
#define | LCD_RAMRegister_14 ((uint32_t)0x0000000E)
#define | LCD_RAMRegister_15 ((uint32_t)0x0000000F)
#define | LCD_RAMRegister_2 ((uint32_t)0x00000002)
#define | LCD_RAMRegister_3 ((uint32_t)0x00000003)
#define | LCD_RAMRegister_4 ((uint32_t)0x00000004)
#define | LCD_RAMRegister_5 ((uint32_t)0x00000005)
#define | LCD_RAMRegister_6 ((uint32_t)0x00000006)
#define | LCD_RAMRegister_7 ((uint32_t)0x00000007)
#define | LCD_RAMRegister_8 ((uint32_t)0x00000008)
#define | LCD_RAMRegister_9 ((uint32_t)0x00000009)

Define Documentation

#define IS_LCD_RAM_REGISTER ( REGISTER )
Value:
(((REGISTER) == LCD_RAMRegister_0) || \
                                       ((REGISTER) == LCD_RAMRegister_1) || \
                                       ((REGISTER) == LCD_RAMRegister_2) || \
                                       ((REGISTER) == LCD_RAMRegister_3) || \
                                       ((REGISTER) == LCD_RAMRegister_4) || \
                                       ((REGISTER) == LCD_RAMRegister_5) || \
                                       ((REGISTER) == LCD_RAMRegister_6) || \
                                       ((REGISTER) == LCD_RAMRegister_7) || \
                                       ((REGISTER) == LCD_RAMRegister_8) || \
                                       ((REGISTER) == LCD_RAMRegister_9) || \
                                       ((REGISTER) == LCD_RAMRegister_10) || \
                                       ((REGISTER) == LCD_RAMRegister_11) || \
                                       ((REGISTER) == LCD_RAMRegister_12) || \
                                       ((REGISTER) == LCD_RAMRegister_13) || \
                                       ((REGISTER) == LCD_RAMRegister_14) || \
                                       ((REGISTER) == LCD_RAMRegister_15))

Definition at line 381 of file stm32l1xx_lcd.h.

Referenced by LCD_Write().

#define LCD_RAMRegister_0 ((uint32_t)0x00000000)

LCD RAM Register 0

Definition at line 364 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_1 ((uint32_t)0x00000001)

LCD RAM Register 1

Definition at line 365 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_10 ((uint32_t)0x0000000A)

LCD RAM Register 10

Definition at line 374 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_11 ((uint32_t)0x0000000B)

LCD RAM Register 11

Definition at line 375 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_12 ((uint32_t)0x0000000C)

LCD RAM Register 12

Definition at line 376 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_13 ((uint32_t)0x0000000D)

LCD RAM Register 13

Definition at line 377 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_14 ((uint32_t)0x0000000E)

LCD RAM Register 14

Definition at line 378 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_15 ((uint32_t)0x0000000F)

LCD RAM Register 15

Definition at line 379 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_2 ((uint32_t)0x00000002)

LCD RAM Register 2

Definition at line 366 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_3 ((uint32_t)0x00000003)

LCD RAM Register 3

Definition at line 367 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_4 ((uint32_t)0x00000004)

LCD RAM Register 4

Definition at line 368 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_5 ((uint32_t)0x00000005)

LCD RAM Register 5

Definition at line 369 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_6 ((uint32_t)0x00000006)

LCD RAM Register 6

Definition at line 370 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_7 ((uint32_t)0x00000007)

LCD RAM Register 7

Definition at line 371 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_8 ((uint32_t)0x00000008)

LCD RAM Register 8

Definition at line 372 of file stm32l1xx_lcd.h.

#define LCD_RAMRegister_9 ((uint32_t)0x00000009)

LCD RAM Register 9

Definition at line 373 of file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

LCD_Private_Functions

Initialization and Configuration functions. More...

Functions

void | LCD_BlinkConfig (uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
Configures the LCD Blink mode and Blink frequency.
void | LCD_Cmd (FunctionalState NewState)
Enables or disables the LCD Controller.
void | LCD_ContrastConfig (uint32_t LCD_Contrast)
Configures the LCD Contrast.
void | LCD_DeadTimeConfig (uint32_t LCD_DeadTime)
Configures the LCD dead time.
void | LCD_DeInit (void)
Deinitializes the LCD peripheral registers to their default reset values.
void | LCD_HighDriveCmd (FunctionalState NewState)
Enables or disables the low resistance divider.
void | LCD_Init (LCD_InitTypeDef *LCD_InitStruct)
Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.
void | LCD_MuxSegmentCmd (FunctionalState NewState)
Enables or disables the Mux Segment.
void | LCD_PulseOnDurationConfig (uint32_t LCD_PulseOnDuration)
Configures the LCD pulses on duration.
void | LCD_StructInit (LCD_InitTypeDef *LCD_InitStruct)
Fills each LCD_InitStruct member with its default value.
void | LCD_WaitForSynchro (void)
Waits until the LCD FCR register is synchronized in the LCDCLK domain.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================

Function Documentation

void LCD_BlinkConfig | ( | uint32_t | LCD_BlinkMode,
 |  | uint32_t | LCD_BlinkFrequency
 | ) |  |

Configures the LCD Blink mode and Blink frequency.

Parameters:
LCD_BlinkMode,: specifies the LCD blink mode. This parameter can be one of the following values:

  • LCD_BlinkMode_Off: Blink disabled
  • LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
  • LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
  • LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM (all pixels)
LCD_BlinkFrequency,: specifies the LCD blink frequency. This parameter can be one of the following values:

  • LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8
  • LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16
  • LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32
  • LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64
  • LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128
  • LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256
  • LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512
  • LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
Return values:
None

Definition at line 345 of file stm32l1xx_lcd.c.

References BLINK_MASK, IS_LCD_BLINK_FREQUENCY, IS_LCD_BLINK_MODE, and LCD.

void LCD_Cmd ( FunctionalState NewState )

Enables or disables the LCD Controller.

Parameters:
NewState,: new state of the LCD peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 218 of file stm32l1xx_lcd.c.

References CR_LCDEN_BB, and IS_FUNCTIONAL_STATE.

void LCD_ContrastConfig ( uint32_t LCD_Contrast )

Configures the LCD Contrast.

Parameters:
LCD_Contrast,: specifies the LCD Contrast. This parameter can be one of the following values:

  • LCD_Contrast_Level_0: Maximum Voltage = 2.60V
  • LCD_Contrast_Level_1: Maximum Voltage = 2.73V
  • LCD_Contrast_Level_2: Maximum Voltage = 2.86V
  • LCD_Contrast_Level_3: Maximum Voltage = 2.99V
  • LCD_Contrast_Level_4: Maximum Voltage = 3.12V
  • LCD_Contrast_Level_5: Maximum Voltage = 3.25V
  • LCD_Contrast_Level_6: Maximum Voltage = 3.38V
  • LCD_Contrast_Level_7: Maximum Voltage = 3.51V
Return values:
None

Definition at line 369 of file stm32l1xx_lcd.c.

References CONTRAST_MASK, IS_LCD_CONTRAST, and LCD.

void LCD_DeadTimeConfig ( uint32_t LCD_DeadTime )

Configures the LCD dead time.

Parameters:
LCD_DeadTime,: specifies the LCD dead time. This parameter can be one of the following values:

  • LCD_DeadTime_0: No dead Time
  • LCD_DeadTime_1: One Phase between different couple of Frame
  • LCD_DeadTime_2: Two Phase between different couple of Frame
  • LCD_DeadTime_3: Three Phase between different couple of Frame
  • LCD_DeadTime_4: Four Phase between different couple of Frame
  • LCD_DeadTime_5: Five Phase between different couple of Frame
  • LCD_DeadTime_6: Six Phase between different couple of Frame
  • LCD_DeadTime_7: Seven Phase between different couple of Frame
Return values:
None

Definition at line 314 of file stm32l1xx_lcd.c.

References DEAD_MASK, IS_LCD_DEAD_TIME, and LCD.

void LCD_DeInit ( void )

Deinitializes the LCD peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 156 of file stm32l1xx_lcd.c.

References DISABLE, ENABLE, RCC_APB1Periph_LCD, and RCC_APB1PeriphResetCmd().

void LCD_HighDriveCmd ( FunctionalState NewState )

Enables or disables the low resistance divider.

Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This function is useful in this case if some additional power consumption can be tolerated.

Note:
When this mode is enabled, the PulseOn Duration (PON) have to be programmed to 1/CK_PS (LCD_PulseOnDuration_1).
Parameters:
NewState,: new state of the low resistance divider. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 253 of file stm32l1xx_lcd.c.

References FCR_HD_BB, and IS_FUNCTIONAL_STATE.

void LCD_Init ( LCD_InitTypeDef * LCD_InitStruct )

Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.

Note:
This function can be used only when the LCD is disabled.
Parameters:
LCD_InitStruct,: pointer to a LCD_InitTypeDef structure that contains the configuration information for the specified LCD peripheral.
Return values:
None

Definition at line 172 of file stm32l1xx_lcd.c.

References CR_MASK, FCR_MASK, IS_LCD_BIAS, IS_LCD_DIVIDER, IS_LCD_DUTY, IS_LCD_PRESCALER, IS_LCD_VOLTAGE_SOURCE, LCD, LCD_InitTypeDef::LCD_Bias, LCD_InitTypeDef::LCD_Divider, LCD_InitTypeDef::LCD_Duty, LCD_InitTypeDef::LCD_Prescaler, LCD_InitTypeDef::LCD_VoltageSource, and LCD_WaitForSynchro().

void LCD_MuxSegmentCmd ( FunctionalState NewState )

Enables or disables the Mux Segment.

Note:
This function can be used only when the LCD is disabled.
Parameters:
NewState,: new state of the Mux Segment. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 268 of file stm32l1xx_lcd.c.

References CR_MUX_SEG_BB, and IS_FUNCTIONAL_STATE.

void LCD_PulseOnDurationConfig ( uint32_t LCD_PulseOnDuration )

Configures the LCD pulses on duration.

Parameters:
LCD_PulseOnDuration,: specifies the LCD pulse on duration in terms of CK_PS (prescaled LCD clock period) pulses. This parameter can be one of the following values:

  • LCD_PulseOnDuration_0: 0 pulse
  • LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS
  • LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS
  • LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS
  • LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS
  • LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS
  • LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS
  • LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS
Return values:
None

Definition at line 291 of file stm32l1xx_lcd.c.

References IS_LCD_PULSE_ON_DURATION, LCD, and PON_MASK.

void LCD_StructInit ( LCD_InitTypeDef * LCD_InitStruct )

Fills each LCD_InitStruct member with its default value.

Parameters:
LCD_InitStruct,: pointer to a LCD_InitTypeDef structure which will be initialized.
Return values:
None

< Initialize the LCD_Prescaler member

< Initialize the LCD_Divider member

< Initialize the LCD_Duty member

< Initialize the LCD_Bias member

< Initialize the LCD_VoltageSource member

Definition at line 198 of file stm32l1xx_lcd.c.

References LCD_InitTypeDef::LCD_Bias, LCD_Bias_1_4, LCD_InitTypeDef::LCD_Divider, LCD_Divider_16, LCD_InitTypeDef::LCD_Duty, LCD_Duty_Static, LCD_InitTypeDef::LCD_Prescaler, LCD_Prescaler_1, LCD_InitTypeDef::LCD_VoltageSource, and LCD_VoltageSource_Internal.

void LCD_WaitForSynchro ( void )

Waits until the LCD FCR register is synchronized in the LCDCLK domain.

This function must be called after any write operation to LCD_FCR register.

Parameters:
None
Return values:
None

Definition at line 234 of file stm32l1xx_lcd.c.

References LCD, LCD_FLAG_FCRSF, and RESET.

Referenced by LCD_Init().


STM32L1xx Standard Peripherals Firmware Library: LCD RAM memory write functions

Functions

LCD RAM memory write functions

LCD_Private_Functions

LCD RAM memory write functions. More...

Functions

void | LCD_UpdateDisplayRequest (void)
Enables the Update Display Request.
void | LCD_Write (uint32_t LCD_RAMRegister, uint32_t LCD_Data)
Writes a word in the specific LCD RAM.

Detailed Description

LCD RAM memory write functions.

 ===============================================================================
                  ##### LCD RAM memory write functions #####
 ===============================================================================
    [..] Using its double buffer memory the LCD controller ensures the coherency
         of the displayed information without having to use interrupts to control
         LCD_RAM modification.

    [..] The application software can access the first buffer level (LCD_RAM) through
         the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag
         in the LCD_SR register using the LCD_UpdateDisplayRequest() function.

    [..] This UDR flag (update display request) requests the updated information
         to be moved into the second buffer level (LCD_DISPLAY).

    [..] This operation is done synchronously with the frame (at the beginning of
         the next frame), until the update is completed, the LCD_RAM is write
         protected and the UDR flag stays high.

    [..] Once the update is completed another flag (UDD - Update Display Done) is
         set and generates an interrupt if the UDDIE bit in the LCD_FCR register
        is set.

    [..] The time it takes to update LCD_DISPLAY is, in the worst case, one odd
         and one even frame.

    [..] The update will not occur (UDR = 1 and UDD = 0) until the display is
         enabled (LCDEN = 1).

Function Documentation

void LCD_UpdateDisplayRequest ( void )

Enables the Update Display Request.

Note:
Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
Parameters:
None
Return values:
None

Definition at line 464 of file stm32l1xx_lcd.c.

References SR_UDR_BB.

void LCD_Write | ( | uint32_t | LCD_RAMRegister,
 |  | uint32_t | LCD_Data
 | ) |  |

Writes a word in the specific LCD RAM.

Parameters:
LCD_RAMRegister,: specifies the LCD Contrast. This parameter can be one of the following values:

  • LCD_RAMRegister_0: LCD RAM Register 0
  • LCD_RAMRegister_1: LCD RAM Register 1
  • LCD_RAMRegister_2: LCD RAM Register 2
  • LCD_RAMRegister_3: LCD RAM Register 3
  • LCD_RAMRegister_4: LCD RAM Register 4
  • LCD_RAMRegister_5: LCD RAM Register 5
  • LCD_RAMRegister_6: LCD RAM Register 6
  • LCD_RAMRegister_7: LCD RAM Register 7
  • LCD_RAMRegister_8: LCD RAM Register 8
  • LCD_RAMRegister_9: LCD RAM Register 9
  • LCD_RAMRegister_10: LCD RAM Register 10
  • LCD_RAMRegister_11: LCD RAM Register 11
  • LCD_RAMRegister_12: LCD RAM Register 12
  • LCD_RAMRegister_13: LCD RAM Register 13
  • LCD_RAMRegister_14: LCD RAM Register 14
  • LCD_RAMRegister_15: LCD RAM Register 15
LCD_Data,: specifies LCD Data Value to be written.
Return values:
None

Definition at line 441 of file stm32l1xx_lcd.c.

References IS_LCD_RAM_REGISTER, and LCD.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

LCD_Private_Functions

Interrupts and flags management functions. More...

Functions

void | LCD_ClearFlag (uint32_t LCD_FLAG)
Clears the LCD's pending flags.
void | LCD_ClearITPendingBit (uint32_t LCD_IT)
Clears the LCD's interrupt pending bits.
FlagStatus | LCD_GetFlagStatus (uint32_t LCD_FLAG)
Checks whether the specified LCD flag is set or not.
ITStatus | LCD_GetITStatus (uint32_t LCD_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | LCD_ITConfig (uint32_t LCD_IT, FunctionalState NewState)
Enables or disables the specified LCD interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
            ##### Interrupts and flags management functions #####
 ===============================================================================

Function Documentation

void LCD_ClearFlag ( uint32_t LCD_FLAG )

Clears the LCD's pending flags.

Parameters:
LCD_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • LCD_FLAG_SOF: Start of Frame Interrupt
  • LCD_FLAG_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 557 of file stm32l1xx_lcd.c.

References IS_LCD_CLEAR_FLAG, and LCD.

void LCD_ClearITPendingBit ( uint32_t LCD_IT )

Clears the LCD's interrupt pending bits.

Parameters:
LCD_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 612 of file stm32l1xx_lcd.c.

References IS_LCD_IT, and LCD.

FlagStatus LCD_GetFlagStatus ( uint32_t LCD_FLAG )

Checks whether the specified LCD flag is set or not.

Parameters:
LCD_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
Note:
The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.
  • LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at the beginning of a new frame, at the same time as the display data is updated.
  • LCD_FLAG_UDR: Update Display Request flag.
  • LCD_FLAG_UDD: Update Display Done flag.
  • LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status of the step-up converter.
  • LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. This flag is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain.
Return values:
The new state of LCD_FLAG (SET or RESET).

Definition at line 531 of file stm32l1xx_lcd.c.

References IS_LCD_GET_FLAG, LCD, RESET, and SET.

ITStatus LCD_GetITStatus ( uint32_t LCD_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
LCD_IT,: specifies the LCD interrupts sources to check. This parameter can be one of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt.
Note:
If the device is in STOP mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt will never occur.
Return values:
The new state of the LCD_IT (SET or RESET).

Definition at line 577 of file stm32l1xx_lcd.c.

References IS_LCD_GET_IT, LCD, RESET, and SET.

void LCD_ITConfig | ( | uint32_t | LCD_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified LCD interrupts.

Parameters:
LCD_IT,: specifies the LCD interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
NewState,: new state of the specified LCD interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 495 of file stm32l1xx_lcd.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_LCD_IT, and LCD.


STM32L1xx Standard Peripherals Firmware Library: LCD

Data Structures | Modules | Defines | Functions

LCD

STM32L1xx_StdPeriph_Driver

LCD driver modules. More...

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...

Modules

LCD_Exported_Constants
LCD_Private_Functions

Defines

#define | BLINK_MASK ((uint32_t)0xFFFC1FFF)
#define | CONTRAST_MASK ((uint32_t)0xFFFFE3FF)
#define | CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))
#define | CR_MASK ((uint32_t)0xFFFFFF81)
#define | CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))
#define | CR_OFFSET (LCD_OFFSET + 0x00)
#define | DEAD_MASK ((uint32_t)0xFFFFFC7F)
#define | FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))
#define | FCR_MASK ((uint32_t)0xFC03FFFF)
#define | FCR_OFFSET (LCD_OFFSET + 0x04)
#define | HD_BitNumber 0x00
#define | LCD_OFFSET (LCD_BASE - PERIPH_BASE)
#define | LCDEN_BitNumber 0x00
#define | MUX_SEG_BitNumber 0x07
#define | PON_MASK ((uint32_t)0xFFFFFF8F)
#define | SR_OFFSET (LCD_OFFSET + 0x08)
#define | SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))
#define | UDR_BitNumber 0x02

Functions

void | LCD_BlinkConfig (uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
Configures the LCD Blink mode and Blink frequency.
void | LCD_ClearFlag (uint32_t LCD_FLAG)
Clears the LCD's pending flags.
void | LCD_ClearITPendingBit (uint32_t LCD_IT)
Clears the LCD's interrupt pending bits.
void | LCD_Cmd (FunctionalState NewState)
Enables or disables the LCD Controller.
void | LCD_ContrastConfig (uint32_t LCD_Contrast)
Configures the LCD Contrast.
void | LCD_DeadTimeConfig (uint32_t LCD_DeadTime)
Configures the LCD dead time.
void | LCD_DeInit (void)
Deinitializes the LCD peripheral registers to their default reset values.
FlagStatus | LCD_GetFlagStatus (uint32_t LCD_FLAG)
Checks whether the specified LCD flag is set or not.
ITStatus | LCD_GetITStatus (uint32_t LCD_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | LCD_HighDriveCmd (FunctionalState NewState)
Enables or disables the low resistance divider.
void | LCD_Init (LCD_InitTypeDef *LCD_InitStruct)
Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.
void | LCD_ITConfig (uint32_t LCD_IT, FunctionalState NewState)
Enables or disables the specified LCD interrupts.
void | LCD_MuxSegmentCmd (FunctionalState NewState)
Enables or disables the Mux Segment.
void | LCD_PulseOnDurationConfig (uint32_t LCD_PulseOnDuration)
Configures the LCD pulses on duration.
void | LCD_StructInit (LCD_InitTypeDef *LCD_InitStruct)
Fills each LCD_InitStruct member with its default value.
void | LCD_UpdateDisplayRequest (void)
Enables the Update Display Request.
void | LCD_WaitForSynchro (void)
Waits until the LCD FCR register is synchronized in the LCDCLK domain.
void | LCD_Write (uint32_t LCD_RAMRegister, uint32_t LCD_Data)
Writes a word in the specific LCD RAM.

Detailed Description

LCD driver modules.

Define Documentation

#define BLINK_MASK ((uint32_t)0xFFFC1FFF)

Definition at line 126 of file stm32l1xx_lcd.c.

Referenced by LCD_BlinkConfig().

#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF)

Definition at line 127 of file stm32l1xx_lcd.c.

Referenced by LCD_ContrastConfig().

#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))

Definition at line 101 of file stm32l1xx_lcd.c.

Referenced by LCD_Cmd().

#define CR_MASK ((uint32_t)0xFFFFFF81)

Definition at line 123 of file stm32l1xx_lcd.c.

Referenced by LCD_Init().

#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))

Definition at line 105 of file stm32l1xx_lcd.c.

Referenced by LCD_MuxSegmentCmd().

#define CR_OFFSET (LCD_OFFSET + 0x00)

Definition at line 99 of file stm32l1xx_lcd.c.

#define DEAD_MASK ((uint32_t)0xFFFFFC7F)

Definition at line 125 of file stm32l1xx_lcd.c.

Referenced by LCD_DeadTimeConfig().

#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))

Definition at line 113 of file stm32l1xx_lcd.c.

Referenced by LCD_HighDriveCmd().

#define FCR_MASK ((uint32_t)0xFC03FFFF)

Definition at line 122 of file stm32l1xx_lcd.c.

Referenced by LCD_Init().

#define FCR_OFFSET (LCD_OFFSET + 0x04)

Definition at line 111 of file stm32l1xx_lcd.c.

#define HD_BitNumber 0x00

Definition at line 112 of file stm32l1xx_lcd.c.

#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)

Definition at line 94 of file stm32l1xx_lcd.c.

#define LCDEN_BitNumber 0x00

Definition at line 100 of file stm32l1xx_lcd.c.

#define MUX_SEG_BitNumber 0x07

Definition at line 104 of file stm32l1xx_lcd.c.

#define PON_MASK ((uint32_t)0xFFFFFF8F)

Definition at line 124 of file stm32l1xx_lcd.c.

Referenced by LCD_PulseOnDurationConfig().

#define SR_OFFSET (LCD_OFFSET + 0x08)

Definition at line 118 of file stm32l1xx_lcd.c.

#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))

Definition at line 120 of file stm32l1xx_lcd.c.

Referenced by LCD_UpdateDisplayRequest().

#define UDR_BitNumber 0x02

Definition at line 119 of file stm32l1xx_lcd.c.

Function Documentation

void LCD_BlinkConfig | ( | uint32_t | LCD_BlinkMode,
 |  | uint32_t | LCD_BlinkFrequency
 | ) |  |

Configures the LCD Blink mode and Blink frequency.

Parameters:
LCD_BlinkMode,: specifies the LCD blink mode. This parameter can be one of the following values:

  • LCD_BlinkMode_Off: Blink disabled
  • LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
  • LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
  • LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM (all pixels)
LCD_BlinkFrequency,: specifies the LCD blink frequency. This parameter can be one of the following values:

  • LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8
  • LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16
  • LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32
  • LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64
  • LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128
  • LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256
  • LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512
  • LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
Return values:
None

Definition at line 345 of file stm32l1xx_lcd.c.

References BLINK_MASK, IS_LCD_BLINK_FREQUENCY, IS_LCD_BLINK_MODE, and LCD.

void LCD_ClearFlag ( uint32_t LCD_FLAG )

Clears the LCD's pending flags.

Parameters:
LCD_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • LCD_FLAG_SOF: Start of Frame Interrupt
  • LCD_FLAG_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 557 of file stm32l1xx_lcd.c.

References IS_LCD_CLEAR_FLAG, and LCD.

void LCD_ClearITPendingBit ( uint32_t LCD_IT )

Clears the LCD's interrupt pending bits.

Parameters:
LCD_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 612 of file stm32l1xx_lcd.c.

References IS_LCD_IT, and LCD.

void LCD_Cmd ( FunctionalState NewState )

Enables or disables the LCD Controller.

Parameters:
NewState,: new state of the LCD peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 218 of file stm32l1xx_lcd.c.

References CR_LCDEN_BB, and IS_FUNCTIONAL_STATE.

void LCD_ContrastConfig ( uint32_t LCD_Contrast )

Configures the LCD Contrast.

Parameters:
LCD_Contrast,: specifies the LCD Contrast. This parameter can be one of the following values:

  • LCD_Contrast_Level_0: Maximum Voltage = 2.60V
  • LCD_Contrast_Level_1: Maximum Voltage = 2.73V
  • LCD_Contrast_Level_2: Maximum Voltage = 2.86V
  • LCD_Contrast_Level_3: Maximum Voltage = 2.99V
  • LCD_Contrast_Level_4: Maximum Voltage = 3.12V
  • LCD_Contrast_Level_5: Maximum Voltage = 3.25V
  • LCD_Contrast_Level_6: Maximum Voltage = 3.38V
  • LCD_Contrast_Level_7: Maximum Voltage = 3.51V
Return values:
None

Definition at line 369 of file stm32l1xx_lcd.c.

References CONTRAST_MASK, IS_LCD_CONTRAST, and LCD.

void LCD_DeadTimeConfig ( uint32_t LCD_DeadTime )

Configures the LCD dead time.

Parameters:
LCD_DeadTime,: specifies the LCD dead time. This parameter can be one of the following values:

  • LCD_DeadTime_0: No dead Time
  • LCD_DeadTime_1: One Phase between different couple of Frame
  • LCD_DeadTime_2: Two Phase between different couple of Frame
  • LCD_DeadTime_3: Three Phase between different couple of Frame
  • LCD_DeadTime_4: Four Phase between different couple of Frame
  • LCD_DeadTime_5: Five Phase between different couple of Frame
  • LCD_DeadTime_6: Six Phase between different couple of Frame
  • LCD_DeadTime_7: Seven Phase between different couple of Frame
Return values:
None

Definition at line 314 of file stm32l1xx_lcd.c.

References DEAD_MASK, IS_LCD_DEAD_TIME, and LCD.

void LCD_DeInit ( void )

Deinitializes the LCD peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 156 of file stm32l1xx_lcd.c.

References DISABLE, ENABLE, RCC_APB1Periph_LCD, and RCC_APB1PeriphResetCmd().

FlagStatus LCD_GetFlagStatus ( uint32_t LCD_FLAG )

Checks whether the specified LCD flag is set or not.

Parameters:
LCD_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
Note:
The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.
  • LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at the beginning of a new frame, at the same time as the display data is updated.
  • LCD_FLAG_UDR: Update Display Request flag.
  • LCD_FLAG_UDD: Update Display Done flag.
  • LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status of the step-up converter.
  • LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. This flag is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain.
Return values:
The new state of LCD_FLAG (SET or RESET).

Definition at line 531 of file stm32l1xx_lcd.c.

References IS_LCD_GET_FLAG, LCD, RESET, and SET.

ITStatus LCD_GetITStatus ( uint32_t LCD_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
LCD_IT,: specifies the LCD interrupts sources to check. This parameter can be one of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt.
Note:
If the device is in STOP mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt will never occur.
Return values:
The new state of the LCD_IT (SET or RESET).

Definition at line 577 of file stm32l1xx_lcd.c.

References IS_LCD_GET_IT, LCD, RESET, and SET.

void LCD_HighDriveCmd ( FunctionalState NewState )

Enables or disables the low resistance divider.

Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This function is useful in this case if some additional power consumption can be tolerated.

Note:
When this mode is enabled, the PulseOn Duration (PON) have to be programmed to 1/CK_PS (LCD_PulseOnDuration_1).
Parameters:
NewState,: new state of the low resistance divider. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 253 of file stm32l1xx_lcd.c.

References FCR_HD_BB, and IS_FUNCTIONAL_STATE.

void LCD_Init ( LCD_InitTypeDef * LCD_InitStruct )

Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.

Note:
This function can be used only when the LCD is disabled.
Parameters:
LCD_InitStruct,: pointer to a LCD_InitTypeDef structure that contains the configuration information for the specified LCD peripheral.
Return values:
None

Definition at line 172 of file stm32l1xx_lcd.c.

References CR_MASK, FCR_MASK, IS_LCD_BIAS, IS_LCD_DIVIDER, IS_LCD_DUTY, IS_LCD_PRESCALER, IS_LCD_VOLTAGE_SOURCE, LCD, LCD_InitTypeDef::LCD_Bias, LCD_InitTypeDef::LCD_Divider, LCD_InitTypeDef::LCD_Duty, LCD_InitTypeDef::LCD_Prescaler, LCD_InitTypeDef::LCD_VoltageSource, and LCD_WaitForSynchro().

void LCD_ITConfig | ( | uint32_t | LCD_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified LCD interrupts.

Parameters:
LCD_IT,: specifies the LCD interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
NewState,: new state of the specified LCD interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 495 of file stm32l1xx_lcd.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_LCD_IT, and LCD.

void LCD_MuxSegmentCmd ( FunctionalState NewState )

Enables or disables the Mux Segment.

Note:
This function can be used only when the LCD is disabled.
Parameters:
NewState,: new state of the Mux Segment. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 268 of file stm32l1xx_lcd.c.

References CR_MUX_SEG_BB, and IS_FUNCTIONAL_STATE.

void LCD_PulseOnDurationConfig ( uint32_t LCD_PulseOnDuration )

Configures the LCD pulses on duration.

Parameters:
LCD_PulseOnDuration,: specifies the LCD pulse on duration in terms of CK_PS (prescaled LCD clock period) pulses. This parameter can be one of the following values:

  • LCD_PulseOnDuration_0: 0 pulse
  • LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS
  • LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS
  • LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS
  • LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS
  • LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS
  • LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS
  • LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS
Return values:
None

Definition at line 291 of file stm32l1xx_lcd.c.

References IS_LCD_PULSE_ON_DURATION, LCD, and PON_MASK.

void LCD_StructInit ( LCD_InitTypeDef * LCD_InitStruct )

Fills each LCD_InitStruct member with its default value.

Parameters:
LCD_InitStruct,: pointer to a LCD_InitTypeDef structure which will be initialized.
Return values:
None

< Initialize the LCD_Prescaler member

< Initialize the LCD_Divider member

< Initialize the LCD_Duty member

< Initialize the LCD_Bias member

< Initialize the LCD_VoltageSource member

Definition at line 198 of file stm32l1xx_lcd.c.

References LCD_InitTypeDef::LCD_Bias, LCD_Bias_1_4, LCD_InitTypeDef::LCD_Divider, LCD_Divider_16, LCD_InitTypeDef::LCD_Duty, LCD_Duty_Static, LCD_InitTypeDef::LCD_Prescaler, LCD_Prescaler_1, LCD_InitTypeDef::LCD_VoltageSource, and LCD_VoltageSource_Internal.

void LCD_UpdateDisplayRequest ( void )

Enables the Update Display Request.

Note:
Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
Parameters:
None
Return values:
None

Definition at line 464 of file stm32l1xx_lcd.c.

References SR_UDR_BB.

void LCD_WaitForSynchro ( void )

Waits until the LCD FCR register is synchronized in the LCDCLK domain.

This function must be called after any write operation to LCD_FCR register.

Parameters:
None
Return values:
None

Definition at line 234 of file stm32l1xx_lcd.c.

References LCD, LCD_FLAG_FCRSF, and RESET.

Referenced by LCD_Init().

void LCD_Write | ( | uint32_t | LCD_RAMRegister,
 |  | uint32_t | LCD_Data
 | ) |  |

Writes a word in the specific LCD RAM.

Parameters:
LCD_RAMRegister,: specifies the LCD Contrast. This parameter can be one of the following values:

  • LCD_RAMRegister_0: LCD RAM Register 0
  • LCD_RAMRegister_1: LCD RAM Register 1
  • LCD_RAMRegister_2: LCD RAM Register 2
  • LCD_RAMRegister_3: LCD RAM Register 3
  • LCD_RAMRegister_4: LCD RAM Register 4
  • LCD_RAMRegister_5: LCD RAM Register 5
  • LCD_RAMRegister_6: LCD RAM Register 6
  • LCD_RAMRegister_7: LCD RAM Register 7
  • LCD_RAMRegister_8: LCD RAM Register 8
  • LCD_RAMRegister_9: LCD RAM Register 9
  • LCD_RAMRegister_10: LCD RAM Register 10
  • LCD_RAMRegister_11: LCD RAM Register 11
  • LCD_RAMRegister_12: LCD RAM Register 12
  • LCD_RAMRegister_13: LCD RAM Register 13
  • LCD_RAMRegister_14: LCD RAM Register 14
  • LCD_RAMRegister_15: LCD RAM Register 15
LCD_Data,: specifies LCD Data Value to be written.
Return values:
None

Definition at line 441 of file stm32l1xx_lcd.c.

References IS_LCD_RAM_REGISTER, and LCD.


STM32L1xx Standard Peripherals Firmware Library: LCD_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

LCD_InitTypeDef Struct Reference
LCD

LCD Init structure definition. More...

#include <stm32l1xx_lcd.h>

Data Fields

uint32_t | LCD_Bias
uint32_t | LCD_Divider
uint32_t | LCD_Duty
uint32_t | LCD_Prescaler
uint32_t | LCD_VoltageSource

Detailed Description

LCD Init structure definition.

Definition at line 51 of file stm32l1xx_lcd.h.

Field Documentation

uint32_t LCD_InitTypeDef::LCD_Bias

Configures the LCD Bias. This parameter can be one value of LCD_Bias

Definition at line 59 of file stm32l1xx_lcd.h.

Referenced by LCD_Init(), and LCD_StructInit().

uint32_t LCD_InitTypeDef::LCD_Divider

Configures the LCD Divider. This parameter can be one value of LCD_Divider

Definition at line 55 of file stm32l1xx_lcd.h.

Referenced by LCD_Init(), and LCD_StructInit().

uint32_t LCD_InitTypeDef::LCD_Duty

Configures the LCD Duty. This parameter can be one value of LCD_Duty

Definition at line 57 of file stm32l1xx_lcd.h.

Referenced by LCD_Init(), and LCD_StructInit().

uint32_t LCD_InitTypeDef::LCD_Prescaler

Configures the LCD Prescaler. This parameter can be one value of LCD_Prescaler

Definition at line 53 of file stm32l1xx_lcd.h.

Referenced by LCD_Init(), and LCD_StructInit().

uint32_t LCD_InitTypeDef::LCD_VoltageSource

Selects the LCD Voltage source. This parameter can be one value of LCD_Voltage_Source

Definition at line 61 of file stm32l1xx_lcd.h.

Referenced by LCD_Init(), and LCD_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_lcd.h


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Selection

Defines

OPAMP_Selection

OPAMP_Exported_Constants

Defines

#define | IS_OPAMP_ALL_PERIPH(PERIPH)
#define | OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD
#define | OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD
#define | OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD

Define Documentation

#define IS_OPAMP_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == OPAMP_Selection_OPAMP1) || \
                                     ((PERIPH) == OPAMP_Selection_OPAMP2) || \
                                     ((PERIPH) == OPAMP_Selection_OPAMP3))

Definition at line 60 of file stm32l1xx_opamp.h.

Referenced by OPAMP_Cmd(), OPAMP_GetFlagStatus(), OPAMP_LowPowerCmd(), OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD

Definition at line 56 of file stm32l1xx_opamp.h.

Referenced by OPAMP_GetFlagStatus(), OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD

Definition at line 57 of file stm32l1xx_opamp.h.

Referenced by OPAMP_GetFlagStatus(), OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD

Definition at line 58 of file stm32l1xx_opamp.h.


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Switches

Defines

OPAMP_Switches

OPAMP_Exported_Constants

Defines

#define | IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
#define | OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1
#define | OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1
#define | OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1
#define | OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1
#define | OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1
#define | OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2
#define | OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2
#define | OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2
#define | OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2
#define | OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2
#define | OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2
#define | OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3
#define | OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3
#define | OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3
#define | OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3
#define | OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3

Define Documentation

#define IS_OPAMP_SWITCH ( SWITCH ) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))

Definition at line 94 of file stm32l1xx_opamp.h.

Referenced by OPAMP_SwitchCmd().

#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1

OPAMP1 Switch 3

Definition at line 73 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1

OPAMP1 Switch 4

Definition at line 74 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1

OPAMP1 Switch 5

Definition at line 75 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1

OPAMP1 Switch 6

Definition at line 76 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1

OPAMP1 Switch ANA

Definition at line 77 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2

OPAMP2 Switch 3

Definition at line 80 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2

OPAMP2 Switch 4

Definition at line 81 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2

OPAMP2 Switch 5

Definition at line 82 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2

OPAMP2 Switch 6

Definition at line 83 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2

OPAMP2 Switch 7

Definition at line 84 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2

OPAMP2 Switch ANA

Definition at line 85 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3

OPAMP3 Switch 3

Definition at line 88 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3

OPAMP3 Switch 4

Definition at line 89 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3

OPAMP3 Switch 5

Definition at line 90 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3

OPAMP3 Switch 6

Definition at line 91 of file stm32l1xx_opamp.h.

#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3

OPAMP3 Switch ANA

Definition at line 92 of file stm32l1xx_opamp.h.


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Trimming

Defines

OPAMP_Trimming

OPAMP_Exported_Constants

Defines

#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | OPAMP_Trimming_Factory ((uint32_t)0x00000000)
#define | OPAMP_Trimming_User OPAMP_OTR_OT_USER

Define Documentation

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_Trimming_Factory) || \
                                     ((TRIMMING) == OPAMP_Trimming_User))

Definition at line 107 of file stm32l1xx_opamp.h.

Referenced by OPAMP_OffsetTrimmingModeSelect().

#define OPAMP_Trimming_Factory ((uint32_t)0x00000000)

Factory trimming

Definition at line 104 of file stm32l1xx_opamp.h.

#define OPAMP_Trimming_User OPAMP_OTR_OT_USER

User trimming

Definition at line 105 of file stm32l1xx_opamp.h.


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Input

Defines

OPAMP_Input

OPAMP_Exported_Constants

Defines

#define | IS_OPAMP_INPUT(INPUT)
#define | OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H
#define | OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L

Define Documentation

#define IS_OPAMP_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_Input_NMOS) || \
                               ((INPUT) == OPAMP_Input_PMOS))

Definition at line 121 of file stm32l1xx_opamp.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().

#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H

NMOS input

Definition at line 118 of file stm32l1xx_opamp.h.

#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L

PMOS input

Definition at line 119 of file stm32l1xx_opamp.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().


STM32L1xx Standard Peripherals Firmware Library: OPAMP_TrimValue

Defines

OPAMP_TrimValue

OPAMP_Exported_Constants

Defines

#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F)

Define Documentation

#define IS_OPAMP_TRIMMINGVALUE ( VALUE ) ((VALUE) <= 0x0000001F)

Trimming value

Definition at line 132 of file stm32l1xx_opamp.h.

Referenced by OPAMP_OffsetTrimConfig(), and OPAMP_OffsetTrimLowPowerConfig().


STM32L1xx Standard Peripherals Firmware Library: OPAMP_PowerRange

Defines

OPAMP_PowerRange

OPAMP_Exported_Constants

Defines

#define | IS_OPAMP_RANGE(RANGE)
#define | OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE
#define | OPAMP_PowerRange_Low ((uint32_t)0x00000000)

Define Documentation

#define IS_OPAMP_RANGE ( RANGE )
Value:
(((RANGE) == OPAMP_PowerRange_Low) || \
                               ((RANGE) == OPAMP_PowerRange_High))

Definition at line 145 of file stm32l1xx_opamp.h.

Referenced by OPAMP_PowerRangeSelect().

#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE

High power range is selected (VDDA is higher than 2.4V)

Definition at line 143 of file stm32l1xx_opamp.h.

#define OPAMP_PowerRange_Low ((uint32_t)0x00000000)

Low power range is selected (VDDA is lower than 2.4V)

Definition at line 142 of file stm32l1xx_opamp.h.


STM32L1xx Standard Peripherals Firmware Library: Initialization and configuration

Functions

Initialization and configuration

OPAMP_Private_Functions

Initialization and configuration. More...

Functions

void | OPAMP_Cmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the OPAMP peripheral.
void | OPAMP_DeInit (void)
Deinitialize the OPAMPs register to its default reset value.
void | OPAMP_LowPowerCmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the low power mode for OPAMP peripheral.
void | OPAMP_PowerRangeSelect (uint32_t OPAMP_PowerRange)
Select the OPAMP power range.
void | OPAMP_SwitchCmd (uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
Close or Open the OPAMP switches.

Detailed Description

Initialization and configuration.

 ===============================================================================
                            ##### Initialization and configuration #####
 ===============================================================================

Function Documentation

void OPAMP_Cmd | ( | uint32_t | OPAMP_Selection,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable the OPAMP peripheral.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected
NewState,: new state of the selected OPAMP peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 173 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_ALL_PERIPH, and OPAMP.

void OPAMP_DeInit ( void )

Deinitialize the OPAMPs register to its default reset value.

Note:
At startup, OTR and LPOTR registers are set to factory programmed values.
Parameters:
None.
Return values:
None.

< Set OPAMP_CSR register to reset value

< Set OPAMP_OTR register to reset value

< Set OPAMP_LPOTR register to reset value

Definition at line 103 of file stm32l1xx_opamp.c.

References FLASH_R_BASE, and OPAMP.

void OPAMP_LowPowerCmd | ( | uint32_t | OPAMP_Selection,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable the low power mode for OPAMP peripheral.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 selected
  • OPAMP_Selection_OPAMP2: OPAMP2 selected
  • OPAMP_Selection_OPAMP3: OPAMP3 selected
NewState,: new low power state of the selected OPAMP peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 202 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_ALL_PERIPH, and OPAMP.

void OPAMP_PowerRangeSelect ( uint32_t OPAMP_PowerRange )

Select the OPAMP power range.

Note:
The OPAMP power range selection must be performed while OPAMPs are powered down.
Parameters:
OPAMP_Range,: the selected OPAMP power range. This parameter can be one of the following values:

  • OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
  • OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
Return values:
None

Definition at line 229 of file stm32l1xx_opamp.c.

References IS_OPAMP_RANGE, OPAMP, and OPAMP_CSR_AOP_RANGE.

void OPAMP_SwitchCmd | ( | uint32_t | OPAMP_OPAMPxSwitchy,
 |  | FunctionalState | NewState
 | ) |  |

Close or Open the OPAMP switches.

Parameters:
OPAMP_OPAMPxSwitchy,: selects the OPAMPx switch. This parameter can be any combinations of the following values:

  • OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to OPAMP1 negative input (internal follower)
  • OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
  • OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
  • OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
  • OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
  • OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to OPAMP2 negative input (internal follower)
  • OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
  • OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
  • OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
  • OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
  • OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
  • OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to OPAMP3 negative input (internal follower)
  • OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
  • OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
  • OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
  • OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
NewState,: New state of the OPAMP switch. This parameter can be: ENABLE to close the OPAMP switch or DISABLE to open the OPAMP switch
Note:
OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
Return values:
None

Definition at line 144 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_SWITCH, and OPAMP.


STM32L1xx Standard Peripherals Firmware Library: Calibration functions

Functions

Calibration functions

OPAMP_Private_Functions

Calibration functions. More...

Functions

FlagStatus | OPAMP_GetFlagStatus (uint32_t OPAMP_Selection)
Checks whether the specified OPAMP calibration flag is set or not.
void | OPAMP_OffsetTrimConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in normal mode.
void | OPAMP_OffsetTrimLowPowerConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in low power mode.
void | OPAMP_OffsetTrimmingModeSelect (uint32_t OPAMP_Trimming)
Select the trimming mode.

Detailed Description

Calibration functions.

 ===============================================================================
                            ##### Calibration functions #####
 ===============================================================================

Function Documentation

FlagStatus OPAMP_GetFlagStatus ( uint32_t OPAMP_Selection )

Checks whether the specified OPAMP calibration flag is set or not.

Note:
User should wait until calibration flag change the value when changing the trimming value.
Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected.
Return values:
The new state of the OPAMP calibration flag (SET or RESET).

Definition at line 490 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, OPAMP, OPAMP_CSR_OPA1CALOUT, OPAMP_CSR_OPA2CALOUT, OPAMP_CSR_OPA3CALOUT, OPAMP_Selection_OPAMP1, OPAMP_Selection_OPAMP2, RESET, and SET.

void OPAMP_OffsetTrimConfig | ( | uint32_t | OPAMP_Selection,
 |  | uint32_t | OPAMP_Input,
 |  | uint32_t | OPAMP_TrimValue
 | ) |  |

Configure the trimming value of OPAMPs in normal mode.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
OPAMP_Input,: the selected OPAMP input. This parameter can be one of the following values:

  • OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
  • OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
OPAMP_TrimValue,: the trimming value. This parameter can be any value lower or equal to 0x0000001F.
Return values:
None

Definition at line 298 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, IS_OPAMP_INPUT, IS_OPAMP_TRIMMINGVALUE, OPAMP, OPAMP_CSR_OPA1CAL_H, OPAMP_CSR_OPA1CAL_L, OPAMP_CSR_OPA2CAL_H, OPAMP_CSR_OPA2CAL_L, OPAMP_CSR_OPA3CAL_H, OPAMP_CSR_OPA3CAL_L, OPAMP_Input_PMOS, OPAMP_Selection_OPAMP1, and OPAMP_Selection_OPAMP2.

void OPAMP_OffsetTrimLowPowerConfig | ( | uint32_t | OPAMP_Selection,
 |  | uint32_t | OPAMP_Input,
 |  | uint32_t | OPAMP_TrimValue
 | ) |  |

Configure the trimming value of OPAMPs in low power mode.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
OPAMP_Input,: the selected OPAMP input. This parameter can be one of the following values:

  • OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
  • OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
OPAMP_TrimValue,: the trimming value. This parameter can be any value lower or equal to 0x0000001F.
Return values:
None

Definition at line 396 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, IS_OPAMP_INPUT, IS_OPAMP_TRIMMINGVALUE, OPAMP, OPAMP_CSR_OPA1CAL_H, OPAMP_CSR_OPA1CAL_L, OPAMP_CSR_OPA2CAL_H, OPAMP_CSR_OPA2CAL_L, OPAMP_CSR_OPA3CAL_H, OPAMP_CSR_OPA3CAL_L, OPAMP_Input_PMOS, OPAMP_Selection_OPAMP1, and OPAMP_Selection_OPAMP2.

void OPAMP_OffsetTrimmingModeSelect ( uint32_t OPAMP_Trimming )

Select the trimming mode.

Parameters:
OffsetTrimming,: the selected offset trimming mode. This parameter can be one of the following values:

  • OffsetTrimming_Factory: factory trimming values are used for offset calibration.
  • OffsetTrimming_User: user trimming values are used for offset calibration.
Note:
When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig() function or OPAMP_OffsetTrimLowPowerConfig() function to adjust trimming value.
Return values:
None

Definition at line 270 of file stm32l1xx_opamp.c.

References IS_OPAMP_TRIMMING, OPAMP, and OPAMP_OTR_OT_USER.


STM32L1xx Standard Peripherals Firmware Library: OPAMP

Modules | Functions

OPAMP

STM32L1xx_StdPeriph_Driver

OPAMP driver modules. More...

Modules

OPAMP_Exported_Constants
OPAMP_Private_Functions

Functions

void | OPAMP_Cmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the OPAMP peripheral.
void | OPAMP_DeInit (void)
Deinitialize the OPAMPs register to its default reset value.
FlagStatus | OPAMP_GetFlagStatus (uint32_t OPAMP_Selection)
Checks whether the specified OPAMP calibration flag is set or not.
void | OPAMP_LowPowerCmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the low power mode for OPAMP peripheral.
void | OPAMP_OffsetTrimConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in normal mode.
void | OPAMP_OffsetTrimLowPowerConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in low power mode.
void | OPAMP_OffsetTrimmingModeSelect (uint32_t OPAMP_Trimming)
Select the trimming mode.
void | OPAMP_PowerRangeSelect (uint32_t OPAMP_PowerRange)
Select the OPAMP power range.
void | OPAMP_SwitchCmd (uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
Close or Open the OPAMP switches.

Detailed Description

OPAMP driver modules.

Function Documentation

void OPAMP_Cmd | ( | uint32_t | OPAMP_Selection,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable the OPAMP peripheral.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected
NewState,: new state of the selected OPAMP peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 173 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_ALL_PERIPH, and OPAMP.

void OPAMP_DeInit ( void )

Deinitialize the OPAMPs register to its default reset value.

Note:
At startup, OTR and LPOTR registers are set to factory programmed values.
Parameters:
None.
Return values:
None.

< Set OPAMP_CSR register to reset value

< Set OPAMP_OTR register to reset value

< Set OPAMP_LPOTR register to reset value

Definition at line 103 of file stm32l1xx_opamp.c.

References FLASH_R_BASE, and OPAMP.

FlagStatus OPAMP_GetFlagStatus ( uint32_t OPAMP_Selection )

Checks whether the specified OPAMP calibration flag is set or not.

Note:
User should wait until calibration flag change the value when changing the trimming value.
Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected.
Return values:
The new state of the OPAMP calibration flag (SET or RESET).

Definition at line 490 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, OPAMP, OPAMP_CSR_OPA1CALOUT, OPAMP_CSR_OPA2CALOUT, OPAMP_CSR_OPA3CALOUT, OPAMP_Selection_OPAMP1, OPAMP_Selection_OPAMP2, RESET, and SET.

void OPAMP_LowPowerCmd | ( | uint32_t | OPAMP_Selection,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable the low power mode for OPAMP peripheral.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 selected
  • OPAMP_Selection_OPAMP2: OPAMP2 selected
  • OPAMP_Selection_OPAMP3: OPAMP3 selected
NewState,: new low power state of the selected OPAMP peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 202 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_ALL_PERIPH, and OPAMP.

void OPAMP_OffsetTrimConfig | ( | uint32_t | OPAMP_Selection,
 |  | uint32_t | OPAMP_Input,
 |  | uint32_t | OPAMP_TrimValue
 | ) |  |

Configure the trimming value of OPAMPs in normal mode.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
OPAMP_Input,: the selected OPAMP input. This parameter can be one of the following values:

  • OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
  • OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
OPAMP_TrimValue,: the trimming value. This parameter can be any value lower or equal to 0x0000001F.
Return values:
None

Definition at line 298 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, IS_OPAMP_INPUT, IS_OPAMP_TRIMMINGVALUE, OPAMP, OPAMP_CSR_OPA1CAL_H, OPAMP_CSR_OPA1CAL_L, OPAMP_CSR_OPA2CAL_H, OPAMP_CSR_OPA2CAL_L, OPAMP_CSR_OPA3CAL_H, OPAMP_CSR_OPA3CAL_L, OPAMP_Input_PMOS, OPAMP_Selection_OPAMP1, and OPAMP_Selection_OPAMP2.

void OPAMP_OffsetTrimLowPowerConfig | ( | uint32_t | OPAMP_Selection,
 |  | uint32_t | OPAMP_Input,
 |  | uint32_t | OPAMP_TrimValue
 | ) |  |

Configure the trimming value of OPAMPs in low power mode.

Parameters:
OPAMP_Selection,: the selected OPAMP. This parameter can be one of the following values:

  • OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
  • OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
OPAMP_Input,: the selected OPAMP input. This parameter can be one of the following values:

  • OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
  • OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
OPAMP_TrimValue,: the trimming value. This parameter can be any value lower or equal to 0x0000001F.
Return values:
None

Definition at line 396 of file stm32l1xx_opamp.c.

References IS_OPAMP_ALL_PERIPH, IS_OPAMP_INPUT, IS_OPAMP_TRIMMINGVALUE, OPAMP, OPAMP_CSR_OPA1CAL_H, OPAMP_CSR_OPA1CAL_L, OPAMP_CSR_OPA2CAL_H, OPAMP_CSR_OPA2CAL_L, OPAMP_CSR_OPA3CAL_H, OPAMP_CSR_OPA3CAL_L, OPAMP_Input_PMOS, OPAMP_Selection_OPAMP1, and OPAMP_Selection_OPAMP2.

void OPAMP_OffsetTrimmingModeSelect ( uint32_t OPAMP_Trimming )

Select the trimming mode.

Parameters:
OffsetTrimming,: the selected offset trimming mode. This parameter can be one of the following values:

  • OffsetTrimming_Factory: factory trimming values are used for offset calibration.
  • OffsetTrimming_User: user trimming values are used for offset calibration.
Note:
When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig() function or OPAMP_OffsetTrimLowPowerConfig() function to adjust trimming value.
Return values:
None

Definition at line 270 of file stm32l1xx_opamp.c.

References IS_OPAMP_TRIMMING, OPAMP, and OPAMP_OTR_OT_USER.

void OPAMP_PowerRangeSelect ( uint32_t OPAMP_PowerRange )

Select the OPAMP power range.

Note:
The OPAMP power range selection must be performed while OPAMPs are powered down.
Parameters:
OPAMP_Range,: the selected OPAMP power range. This parameter can be one of the following values:

  • OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
  • OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
Return values:
None

Definition at line 229 of file stm32l1xx_opamp.c.

References IS_OPAMP_RANGE, OPAMP, and OPAMP_CSR_AOP_RANGE.

void OPAMP_SwitchCmd | ( | uint32_t | OPAMP_OPAMPxSwitchy,
 |  | FunctionalState | NewState
 | ) |  |

Close or Open the OPAMP switches.

Parameters:
OPAMP_OPAMPxSwitchy,: selects the OPAMPx switch. This parameter can be any combinations of the following values:

  • OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to OPAMP1 negative input (internal follower)
  • OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
  • OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
  • OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
  • OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
  • OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to OPAMP2 negative input (internal follower)
  • OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
  • OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
  • OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
  • OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
  • OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
  • OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to OPAMP3 negative input (internal follower)
  • OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
  • OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
  • OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
  • OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
NewState,: New state of the OPAMP switch. This parameter can be: ENABLE to close the OPAMP switch or DISABLE to open the OPAMP switch
Note:
OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
Return values:
None

Definition at line 144 of file stm32l1xx_opamp.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_OPAMP_SWITCH, and OPAMP.


STM32L1xx Standard Peripherals Firmware Library: PWR_PVD_detection_level

Defines

PWR_PVD_detection_level

PWR_Exported_Constants

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLevel_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLevel_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLevel_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLevel_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLevel_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLevel_7 PWR_CR_PLS_LEV7

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))

Definition at line 65 of file stm32l1xx_pwr.h.

Referenced by PWR_PVDLevelConfig().

#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0

Definition at line 56 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1

Definition at line 57 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2

Definition at line 58 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3

Definition at line 59 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4

Definition at line 60 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5

Definition at line 61 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6

Definition at line 62 of file stm32l1xx_pwr.h.

#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7

Definition at line 63 of file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: PWR_WakeUp_Pins

Defines

PWR_WakeUp_Pins

PWR_Exported_Constants

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | PWR_WakeUpPin_1 ((uint32_t)0x00000000)
#define | PWR_WakeUpPin_2 ((uint32_t)0x00000004)
#define | PWR_WakeUpPin_3 ((uint32_t)0x00000008)

Define Documentation

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WakeUpPin_1) || \
                                ((PIN) == PWR_WakeUpPin_2) || \
                                ((PIN) == PWR_WakeUpPin_3))

Definition at line 80 of file stm32l1xx_pwr.h.

Referenced by PWR_WakeUpPinCmd().

#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)

Definition at line 77 of file stm32l1xx_pwr.h.

#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)

Definition at line 78 of file stm32l1xx_pwr.h.

#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)

Definition at line 79 of file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: PWR_Voltage_Scaling_Ranges

Defines

PWR_Voltage_Scaling_Ranges

PWR_Exported_Constants

Defines

#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | PWR_VoltageScaling_Range1 PWR_CR_VOS_0
#define | PWR_VoltageScaling_Range2 PWR_CR_VOS_1
#define | PWR_VoltageScaling_Range3 PWR_CR_VOS

Define Documentation

#define IS_PWR_VOLTAGE_SCALING_RANGE ( RANGE )
Value:
(((RANGE) == PWR_VoltageScaling_Range1) || \
                                             ((RANGE) == PWR_VoltageScaling_Range2) || \
                                             ((RANGE) == PWR_VoltageScaling_Range3))

Definition at line 96 of file stm32l1xx_pwr.h.

Referenced by PWR_VoltageScalingConfig().

#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0

Definition at line 92 of file stm32l1xx_pwr.h.

#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1

Definition at line 93 of file stm32l1xx_pwr.h.

#define PWR_VoltageScaling_Range3 PWR_CR_VOS

Definition at line 94 of file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: PWR_Regulator_state_is_Sleep_STOP_mode

Defines

PWR_Regulator_state_is_Sleep_STOP_mode

PWR_Exported_Constants

Defines

#define | IS_PWR_REGULATOR(REGULATOR)
#define | PWR_Regulator_LowPower PWR_CR_LPSDSR
#define | PWR_Regulator_ON ((uint32_t)0x00000000)

Define Documentation

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_Regulator_ON) || \
                                     ((REGULATOR) == PWR_Regulator_LowPower))

Definition at line 109 of file stm32l1xx_pwr.h.

Referenced by PWR_EnterSleepMode(), and PWR_EnterSTOPMode().

#define PWR_Regulator_LowPower PWR_CR_LPSDSR

Definition at line 108 of file stm32l1xx_pwr.h.

#define PWR_Regulator_ON ((uint32_t)0x00000000)

Definition at line 107 of file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: PWR_SLEEP_mode_entry

Defines

PWR_SLEEP_mode_entry

PWR_Exported_Constants

Defines

#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
#define | PWR_SLEEPEntry_WFE ((uint8_t)0x02)
#define | PWR_SLEEPEntry_WFI ((uint8_t)0x01)

Define Documentation

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))

Definition at line 121 of file stm32l1xx_pwr.h.

Referenced by PWR_EnterSleepMode().

#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)

Definition at line 120 of file stm32l1xx_pwr.h.

#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)

Definition at line 119 of file stm32l1xx_pwr.h.

Referenced by PWR_EnterSleepMode().


STM32L1xx Standard Peripherals Firmware Library: PWR_STOP_mode_entry

Defines

PWR_STOP_mode_entry

PWR_Exported_Constants

Defines

#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
#define | PWR_STOPEntry_WFE ((uint8_t)0x02)
#define | PWR_STOPEntry_WFI ((uint8_t)0x01)

Define Documentation

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))

Definition at line 133 of file stm32l1xx_pwr.h.

Referenced by PWR_EnterSTOPMode().

#define PWR_STOPEntry_WFE ((uint8_t)0x02)

Definition at line 132 of file stm32l1xx_pwr.h.

#define PWR_STOPEntry_WFI ((uint8_t)0x01)

Definition at line 131 of file stm32l1xx_pwr.h.

Referenced by PWR_EnterSTOPMode().


STM32L1xx Standard Peripherals Firmware Library: PWR_Flag

Defines

PWR_Flag

PWR_Exported_Constants

Defines

#define | IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
#define | IS_PWR_GET_FLAG(FLAG)
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_REGLP PWR_CSR_REGLPF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_VOS PWR_CSR_VOSF
#define | PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#define | PWR_FLAG_WU PWR_CSR_WUF

Define Documentation

#define IS_PWR_CLEAR_FLAG ( FLAG ) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))

Definition at line 154 of file stm32l1xx_pwr.h.

Referenced by PWR_ClearFlag().

#define IS_PWR_GET_FLAG ( FLAG )
Value:
(((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
                               ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))

Definition at line 150 of file stm32l1xx_pwr.h.

Referenced by PWR_GetFlagStatus().

#define PWR_FLAG_PVDO PWR_CSR_PVDO

Definition at line 145 of file stm32l1xx_pwr.h.

#define PWR_FLAG_REGLP PWR_CSR_REGLPF

Definition at line 148 of file stm32l1xx_pwr.h.

#define PWR_FLAG_SB PWR_CSR_SBF

Definition at line 144 of file stm32l1xx_pwr.h.

#define PWR_FLAG_VOS PWR_CSR_VOSF

Definition at line 147 of file stm32l1xx_pwr.h.

#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF

Definition at line 146 of file stm32l1xx_pwr.h.

#define PWR_FLAG_WU PWR_CSR_WUF

Definition at line 143 of file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: RTC Domain Access function

Functions

RTC Domain Access function

PWR_Private_Functions

RTC Domain Access function. More...

Functions

void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_RTCAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.

Detailed Description

RTC Domain Access function.

  ==============================================================================
                     ##### RTC Domain Access function #####
  ==============================================================================

    [..] After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup
         registers) are protected against possible stray write accesses.
    [..] To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.

Function Documentation

void PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Note:
Before calling this function, the VOS[1:0] bits should be configured to "10" and the system frequency has to be configured accordingly. To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() function.
ULP and FWU bits are not reset by this function.
Parameters:
None
Return values:
None

Definition at line 120 of file stm32l1xx_pwr.c.

References DISABLE, ENABLE, RCC_APB1Periph_PWR, and RCC_APB1PeriphResetCmd().

void PWR_RTCAccessCmd ( FunctionalState NewState )

Enables or disables access to the RTC and backup registers.

Note:
If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the RTC Domain Access should be kept enabled.
Parameters:
NewState,: new state of the access to the RTC and backup registers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 134 of file stm32l1xx_pwr.c.

References CR_DBP_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: PVD configuration functions

Functions

PVD configuration functions

PWR_Private_Functions

PVD configuration functions. More...

Functions

void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Detailed Description

PVD configuration functions.

  ==============================================================================
                    ##### PVD configuration functions #####
  ==============================================================================
  [..]
  (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
      selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
  (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
      internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
      when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
  (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
      PVD threshold. This event is internally connected to the EXTI line16
      and can generate an interrupt if enabled through the EXTI registers.
  (+) The PVD is stopped in Standby mode.

Function Documentation

void PWR_PVDCmd ( FunctionalState NewState )

Enables or disables the Power Voltage Detector(PVD).

Parameters:
NewState,: new state of the PVD. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 207 of file stm32l1xx_pwr.c.

References CR_PVDE_BB, and IS_FUNCTIONAL_STATE.

void PWR_PVDLevelConfig ( uint32_t PWR_PVDLevel )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
PWR_PVDLevel,: specifies the PVD detection level. This parameter can be one of the following values:

  • PWR_PVDLevel_0: PVD detection level set to 1.9V.
  • PWR_PVDLevel_1: PVD detection level set to 2.1V.
  • PWR_PVDLevel_2: PVD detection level set to 2.3V.
  • PWR_PVDLevel_3: PVD detection level set to 2.5V.
  • PWR_PVDLevel_4: PVD detection level set to 2.7V.
  • PWR_PVDLevel_5: PVD detection level set to 2.9V.
  • PWR_PVDLevel_6: PVD detection level set to 3.1V.
  • PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).
Return values:
None

Definition at line 182 of file stm32l1xx_pwr.c.

References CR_PLS_MASK, IS_PWR_PVD_LEVEL, and PWR.


STM32L1xx Standard Peripherals Firmware Library: WakeUp pins configuration functions

Functions

WakeUp pins configuration functions

PWR_Private_Functions

WakeUp pins configuration functions. More...

Functions

void PWR_WakeUpPinCmd (uint32_t PWR_WakeUpPin, FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

WakeUp pins configuration functions.

  ==============================================================================
               ##### WakeUp pin configuration functions #####
  ==============================================================================

  (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
      forced in input pull down configuration and are active on rising edges.
  (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
      WakeUp Pin 3 on PE.06.

Function Documentation

void PWR_WakeUpPinCmd | ( | uint32_t | PWR_WakeUpPin,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the WakeUp Pin functionality.

Parameters:
PWR_WakeUpPin,: specifies the WakeUpPin. This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
NewState,: new state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 244 of file stm32l1xx_pwr.c.

References CSR_EWUP_BB, IS_FUNCTIONAL_STATE, and IS_PWR_WAKEUP_PIN.


STM32L1xx Standard Peripherals Firmware Library: Ultra Low Power mode configuration functions

Functions

Ultra Low Power mode configuration functions

PWR_Private_Functions

Ultra Low Power mode configuration functions. More...

Functions

void | PWR_FastWakeUpCmd (FunctionalState NewState)
Enables or disables the Fast WakeUp from Ultra Low Power mode.
void | PWR_UltraLowPowerCmd (FunctionalState NewState)
Enables or disables the Ultra Low Power mode.

Detailed Description

Ultra Low Power mode configuration functions.

  ==============================================================================
             ##### Ultra Low Power mode configuration functions #####
  ==============================================================================
  [..]
  (+) The internal voltage reference consumption is not negligible, in particular
      in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()
      function (ULP bit (Ultra low power) in the PWR_CR register) to disable the
      internal voltage reference. However, in this case, when exiting from the
      Stop/Standby mode, the functions managed through the internal voltage reference
      are not reliable during the internal voltage reference startup time (up to 3 ms).
      To reduce the wakeup time, the device can exit from Stop/Standby mode without
      waiting for the internal voltage reference startup time. This is performed
      by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
      wakeup) in the PWR_CR register) before entering Stop/Standby mode.

Function Documentation

void PWR_FastWakeUpCmd ( FunctionalState NewState )

Enables or disables the Fast WakeUp from Ultra Low Power mode.

Parameters:
NewState,: new state of the Fast WakeUp functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 291 of file stm32l1xx_pwr.c.

References CR_FWU_BB, and IS_FUNCTIONAL_STATE.

void PWR_UltraLowPowerCmd ( FunctionalState NewState )

Enables or disables the Ultra Low Power mode.

Parameters:
NewState,: new state of the Ultra Low Power mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 305 of file stm32l1xx_pwr.c.

References CR_ULP_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Voltage Scaling configuration functions

Functions

Voltage Scaling configuration functions

PWR_Private_Functions

Voltage Scaling configuration functions. More...

Functions

void PWR_VoltageScalingConfig (uint32_t PWR_VoltageScaling)
Configures the voltage scaling range.

Detailed Description

Voltage Scaling configuration functions.

  ==============================================================================
              ##### Voltage Scaling configuration functions #####
  ==============================================================================

    (+) The dynamic voltage scaling is a power management technique which consists in
        increasing or decreasing the voltage used for the digital peripherals (VCORE),
        according to the circumstances.

   [..] Depending on the device voltage range, the maximum frequency and FLASH wait
        state should be adapted accordingly:
   [..]
        +------------------------------------------------------------------+
        |   Wait states   |                HCLK clock frequency (MHz)      |
        |                 |------------------------------------------------|
        |    (Latency)    |            voltage range       | voltage range |
        |                 |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
        |                 |----------------|---------------|---------------|
        |                 |     Range 3    |    Range 2    |    Range 1    |
        |                 |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
        |---------------- |----------------|---------------|---------------|
        | 0WS(1CPU cycle) |0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
        |-----------------|----------------|---------------|---------------|
        | 1WS(2CPU cycle) |2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
        |-----------------|----------------|---------------|---------------|
        | CPU Performance |      Low       |     Medium    |     High      |
        |-----__----------|----------------|---------------|---------------|
        |Power Performance|      High      |     Medium    |      Low      |
        +------------------------------------------------------------------+

    (+) To modify the Product voltage range, user application has to:
        (++) Check VDD to identify which ranges are allowed (see table above).
        (++) Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus()
             function and wait until it is  reset.
        (++) Configure the Voltage range using the PWR_VoltageScalingConfig() function.

    (+) When VCORE range 1 is selected and VDD drops below 2.0 V, the application must
        reconfigure the system:
        (++) Detect that VDD drops below 2.0 V using the PVD Level 1.
        (++) Adapt the clock frequency to the voltage range that will be selected at next step.
        (++) Select the required voltage range.
        (++) When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system
             reconfiguration is required.

    (+) When VDD is above 2.0 V, any of the 3 voltage ranges can be selected.
        (++) When the voltage range is above the targeted voltage range (e.g. from range
             1 to 2).
        (++) Adapt the clock frequency to the lower voltage range that will be selected
             at next step.
        (++) Select the required voltage range.
        (++) When the voltage range is below the targeted voltage range (e.g. from range
             3 to 1).
        (++) Select the required voltage range.
        (++) Tune the clock frequency if needed.

    (+) When VDD is below 2.0 V, only range 2 and 3 can be selected:
        (++) From range 2 to range 3.
             (+++) Adapt the clock frequency to voltage range 3.
             (+++) Select voltage range 3.
        (++) From range 3 to range 2.
             (+++) Select the voltage range 2.
             (+++) Tune the clock frequency if needed.

Function Documentation

void PWR_VoltageScalingConfig ( uint32_t PWR_VoltageScaling )

Configures the voltage scaling range.

Note:
During voltage scaling configuration, the system clock is stopped until the regulator is stabilized (VOSF = 0). This must be taken into account during application developement, in case a critical reaction time to interrupt is needed, and depending on peripheral used (timer, communication,...).
Parameters:
PWR_VoltageScaling,: specifies the voltage scaling range. This parameter can be:

  • PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).
  • PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).
  • PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V)
Return values:
None

Definition at line 402 of file stm32l1xx_pwr.c.

References CR_VOS_MASK, IS_PWR_VOLTAGE_SCALING_RANGE, and PWR.


STM32L1xx Standard Peripherals Firmware Library: Low Power modes configuration functions

Functions

Low Power modes configuration functions

PWR_Private_Functions

Low Power modes configuration functions. More...

Functions

void | PWR_EnterLowPowerRunMode (FunctionalState NewState)
Enters/Exits the Low Power Run mode.
void | PWR_EnterSleepMode (uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
Enters Sleep mode.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.

Detailed Description

Low Power modes configuration functions.

  ==============================================================================
              ##### Low Power modes configuration functions #####
  ==============================================================================

    [..] The devices feature five low-power modes:
    (+) Low power run mode: regulator in low power mode, limited clock frequency,
        limited number of peripherals running.
    (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
    (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
        limited number of peripherals running, regulator in low power mode.
    (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode.
    (+) Standby mode: VCORE domain powered off.

  *** Low power run mode (LP run) ***
  ===================================
      [..]
    (+) Entry:
        (++) Decrease the system frequency.
        (++) The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()
             function.
    (+) Exit:
        (++) The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()
             function.
        (++) Increase the system frequency if needed.

  *** Sleep mode ***
  ==================
  [..]
    (+) Entry:
        (++) The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,)
             function with regulator ON.
    (+) Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) can wake up the device from Sleep mode.

  *** Low power sleep mode (LP sleep) ***
  =======================================
  [..]
    (+) Entry:
        (++) The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()
             function.
        (++) Decrease the system frequency.
        (++) The regulator is forced in low power mode and the WFI or WFE instructions
             are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function
             with regulator in LowPower.
    (+) Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) can wake up the device from Sleep LP mode.

  *** Stop mode ***
  =================
  [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
       the HSI and the HSE RC oscillators are disabled. Internal SRAM and register
       contents are preserved.
       The voltage regulator can be configured either in normal or low-power mode.
       To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
       sensor can be switched off before entering the Stop mode. They can be switched
       on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()
       function.

    (+) Entry:
        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
             function with regulator in LowPower or with Regulator ON.
    (+) Exit:
        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

  *** Standby mode ***
  ====================
  [..] The Standby mode allows to achieve the lowest power consumption. It is based
       on the Cortex-M3 deepsleep mode, with the voltage regulator disabled.
       The VCORE domain is consequently powered off. The PLL, the MSI, the HSI
       oscillator and the HSE oscillator are also switched off. SRAM and register
       contents are lost except for the RTC registers, RTC backup registers and
       Standby circuitry.

  [..] The voltage regulator is OFF.

  [..] To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
       sensor can be switched off before entering the Standby mode. They can be switched
       on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()
       function.

    (+) Entry:
        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
    (+) Exit:
        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
            tamper event, time-stamp event, external reset in NRST pin, IWDG reset.

  *** Auto-wakeup (AWU) from low-power mode ***
  =============================================
  [..]The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event, a time-stamp event, or a comparator event,
      without depending on an external interrupt (Auto-wakeup mode).

    (+) RTC auto-wakeup (AWU) from the Stop mode
        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
                   or Event modes) using the EXTI_Init() function.
             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
                   and RTC_AlarmCmd() functions.
        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to:
             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
                   or Event modes) using the EXTI_Init() function.
             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
                   function.
             (+++) Configure the RTC to detect the tamper or time stamp event using the
                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
                   functions.
        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
             (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
                   or Event modes) using the EXTI_Init() function.
             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.

    (+) RTC auto-wakeup (AWU) from the Standby mode
        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
                   and RTC_AlarmCmd() functions.
        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
             is necessary to:
             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
                   function.
             (+++) Configure the RTC to detect the tamper or time stamp event using the
                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
                   functions.
        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.

    (+) Comparator auto-wakeup (AWU) from the Stop mode
        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
             event, it is necessary to:
             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
                   to be sensitive to to the selected edges (falling, rising or falling
                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
             (+++) Configure the comparator to generate the event.

Function Documentation

void PWR_EnterLowPowerRunMode ( FunctionalState NewState )

Enters/Exits the Low Power Run mode.

Note:
Low power run mode can only be entered when VCORE is in range 2. In addition, the dynamic voltage scaling must not be used when Low power run mode is selected. Only Stop and Sleep modes with regulator configured in Low power mode is allowed when Low power run mode is selected.
In Low power run mode, all I/O pins keep the same state as in Run mode.
Parameters:
NewState,: new state of the Low Power Run mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 584 of file stm32l1xx_pwr.c.

References DISABLE, IS_FUNCTIONAL_STATE, PWR, PWR_CR_LPRUN, and PWR_CR_LPSDSR.

void PWR_EnterSleepMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
PWR_Regulator,: specifies the regulator state in Sleep mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: Sleep mode with regulator ON
  • PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
Note:
Low power sleep mode can only be entered when VCORE is in range 2.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Low power sleep mode.
Parameters:
PWR_SLEEPEntry,: specifies if SLEEP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 617 of file stm32l1xx_pwr.c.

References CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR, PWR_SLEEPEntry_WFI, and SCB_SCR_SLEEPDEEP.

void PWR_EnterSTANDBYMode ( void )

Enters STANDBY mode.

Note:
In Standby mode, all I/O pins are high impedance except for: Reset pad (still available) RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, time-stamp, RTC Alarm out, or RTC clock calibration out. WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
Parameters:
None
Return values:
None

Definition at line 720 of file stm32l1xx_pwr.c.

References PWR, PWR_CR_CWUF, PWR_CR_PDDS, and SCB_SCR_SLEEPDEEP.

void PWR_EnterSTOPMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_STOPEntry
 | ) |  |

Enters STOP mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
PWR_Regulator,: specifies the regulator state in STOP mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: STOP mode with regulator ON.
  • PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
PWR_STOPEntry,: specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.
Return values:
None

Definition at line 673 of file stm32l1xx_pwr.c.

References CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR, PWR_STOPEntry_WFI, and SCB_SCR_SLEEPDEEP.


STM32L1xx Standard Peripherals Firmware Library: Flags management functions

Functions

Flags management functions

PWR_Private_Functions

Flags management functions. More...

Functions

void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.

Detailed Description

Flags management functions.

  ==============================================================================
                       ##### Flags management functions #####
  ==============================================================================

Function Documentation

void PWR_ClearFlag ( uint32_t PWR_FLAG )

Clears the PWR's pending flags.

Parameters:
PWR_FLAG,: specifies the flag to clear. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
Return values:
None

Definition at line 806 of file stm32l1xx_pwr.c.

References IS_PWR_CLEAR_FLAG, and PWR.

FlagStatus PWR_GetFlagStatus ( uint32_t PWR_FLAG )

Checks whether the specified PWR flag is set or not.

Parameters:
PWR_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the PWR_PVDCmd() function.
  • PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This flag indicates the state of the internal voltage reference, VREFINT.
  • PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for the internal regulator to be ready after the voltage range is changed. The VOSF flag indicates that the regulator has reached the voltage level defined with bits VOS[1:0] of PWR_CR register.
  • PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware when the MCU is in Low power run mode. When the MCU exits from Low power run mode, this flag stays SET until the regulator is ready in main mode. A polling on this flag is recommended to wait for the regulator main mode. This flag is RESET by hardware when the regulator is ready.
Return values:
The new state of PWR_FLAG (SET or RESET).

Definition at line 780 of file stm32l1xx_pwr.c.

References IS_PWR_GET_FLAG, PWR, RESET, and SET.


STM32L1xx Standard Peripherals Firmware Library: PWR

Modules | Defines | Functions

PWR

STM32L1xx_StdPeriph_Driver

PWR driver modules. More...

Modules

PWR_Exported_Constants
PWR_Private_Functions

Defines

#define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
#define | CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define | CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
#define | CR_OFFSET (PWR_OFFSET + 0x00)
#define | CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
#define | CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
#define | CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
#define | CSR_OFFSET (PWR_OFFSET + 0x04)
#define | DBP_BitNumber 0x08
#define | EWUP_BitNumber 0x08
#define | FWU_BitNumber 0x0A
#define | PVDE_BitNumber 0x04
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | ULP_BitNumber 0x09

Functions

void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterLowPowerRunMode (FunctionalState NewState)
Enters/Exits the Low Power Run mode.
void | PWR_EnterSleepMode (uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
Enters Sleep mode.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
void | PWR_FastWakeUpCmd (FunctionalState NewState)
Enables or disables the Fast WakeUp from Ultra Low Power mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_RTCAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_UltraLowPowerCmd (FunctionalState NewState)
Enables or disables the Ultra Low Power mode.
void | PWR_VoltageScalingConfig (uint32_t PWR_VoltageScaling)
Configures the voltage scaling range.
void | PWR_WakeUpPinCmd (uint32_t PWR_WakeUpPin, FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

PWR driver modules.

Define Documentation

#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))

Definition at line 57 of file stm32l1xx_pwr.c.

Referenced by PWR_RTCAccessCmd().

#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)

Definition at line 81 of file stm32l1xx_pwr.c.

Referenced by PWR_EnterSleepMode(), and PWR_EnterSTOPMode().

#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))

Definition at line 69 of file stm32l1xx_pwr.c.

Referenced by PWR_FastWakeUpCmd().

#define CR_OFFSET (PWR_OFFSET + 0x00)

Definition at line 55 of file stm32l1xx_pwr.c.

#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)

Definition at line 82 of file stm32l1xx_pwr.c.

Referenced by PWR_PVDLevelConfig().

#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))

Definition at line 61 of file stm32l1xx_pwr.c.

Referenced by PWR_PVDCmd().

#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))

Definition at line 65 of file stm32l1xx_pwr.c.

Referenced by PWR_UltraLowPowerCmd().

#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)

Definition at line 83 of file stm32l1xx_pwr.c.

Referenced by PWR_VoltageScalingConfig().

#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))

Definition at line 76 of file stm32l1xx_pwr.c.

Referenced by PWR_WakeUpPinCmd().

#define CSR_OFFSET (PWR_OFFSET + 0x04)

Definition at line 74 of file stm32l1xx_pwr.c.

#define DBP_BitNumber 0x08

Definition at line 56 of file stm32l1xx_pwr.c.

#define EWUP_BitNumber 0x08

Definition at line 75 of file stm32l1xx_pwr.c.

#define FWU_BitNumber 0x0A

Definition at line 68 of file stm32l1xx_pwr.c.

#define PVDE_BitNumber 0x04

Definition at line 60 of file stm32l1xx_pwr.c.

#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Definition at line 50 of file stm32l1xx_pwr.c.

#define ULP_BitNumber 0x09

Definition at line 64 of file stm32l1xx_pwr.c.

Function Documentation

void PWR_ClearFlag ( uint32_t PWR_FLAG )

Clears the PWR's pending flags.

Parameters:
PWR_FLAG,: specifies the flag to clear. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
Return values:
None

Definition at line 806 of file stm32l1xx_pwr.c.

References IS_PWR_CLEAR_FLAG, and PWR.

void PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Note:
Before calling this function, the VOS[1:0] bits should be configured to "10" and the system frequency has to be configured accordingly. To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() function.
ULP and FWU bits are not reset by this function.
Parameters:
None
Return values:
None

Definition at line 120 of file stm32l1xx_pwr.c.

References DISABLE, ENABLE, RCC_APB1Periph_PWR, and RCC_APB1PeriphResetCmd().

void PWR_EnterLowPowerRunMode ( FunctionalState NewState )

Enters/Exits the Low Power Run mode.

Note:
Low power run mode can only be entered when VCORE is in range 2. In addition, the dynamic voltage scaling must not be used when Low power run mode is selected. Only Stop and Sleep modes with regulator configured in Low power mode is allowed when Low power run mode is selected.
In Low power run mode, all I/O pins keep the same state as in Run mode.
Parameters:
NewState,: new state of the Low Power Run mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 584 of file stm32l1xx_pwr.c.

References DISABLE, IS_FUNCTIONAL_STATE, PWR, PWR_CR_LPRUN, and PWR_CR_LPSDSR.

void PWR_EnterSleepMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
PWR_Regulator,: specifies the regulator state in Sleep mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: Sleep mode with regulator ON
  • PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
Note:
Low power sleep mode can only be entered when VCORE is in range 2.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Low power sleep mode.
Parameters:
PWR_SLEEPEntry,: specifies if SLEEP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 617 of file stm32l1xx_pwr.c.

References CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR, PWR_SLEEPEntry_WFI, and SCB_SCR_SLEEPDEEP.

void PWR_EnterSTANDBYMode ( void )

Enters STANDBY mode.

Note:
In Standby mode, all I/O pins are high impedance except for: Reset pad (still available) RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, time-stamp, RTC Alarm out, or RTC clock calibration out. WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
Parameters:
None
Return values:
None

Definition at line 720 of file stm32l1xx_pwr.c.

References PWR, PWR_CR_CWUF, PWR_CR_PDDS, and SCB_SCR_SLEEPDEEP.

void PWR_EnterSTOPMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_STOPEntry
 | ) |  |

Enters STOP mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
PWR_Regulator,: specifies the regulator state in STOP mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: STOP mode with regulator ON.
  • PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
PWR_STOPEntry,: specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.
Return values:
None

Definition at line 673 of file stm32l1xx_pwr.c.

References CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR, PWR_STOPEntry_WFI, and SCB_SCR_SLEEPDEEP.

void PWR_FastWakeUpCmd ( FunctionalState NewState )

Enables or disables the Fast WakeUp from Ultra Low Power mode.

Parameters:
NewState,: new state of the Fast WakeUp functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 291 of file stm32l1xx_pwr.c.

References CR_FWU_BB, and IS_FUNCTIONAL_STATE.

FlagStatus PWR_GetFlagStatus ( uint32_t PWR_FLAG )

Checks whether the specified PWR flag is set or not.

Parameters:
PWR_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the PWR_PVDCmd() function.
  • PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This flag indicates the state of the internal voltage reference, VREFINT.
  • PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for the internal regulator to be ready after the voltage range is changed. The VOSF flag indicates that the regulator has reached the voltage level defined with bits VOS[1:0] of PWR_CR register.
  • PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware when the MCU is in Low power run mode. When the MCU exits from Low power run mode, this flag stays SET until the regulator is ready in main mode. A polling on this flag is recommended to wait for the regulator main mode. This flag is RESET by hardware when the regulator is ready.
Return values:
The new state of PWR_FLAG (SET or RESET).

Definition at line 780 of file stm32l1xx_pwr.c.

References IS_PWR_GET_FLAG, PWR, RESET, and SET.

void PWR_PVDCmd ( FunctionalState NewState )

Enables or disables the Power Voltage Detector(PVD).

Parameters:
NewState,: new state of the PVD. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 207 of file stm32l1xx_pwr.c.

References CR_PVDE_BB, and IS_FUNCTIONAL_STATE.

void PWR_PVDLevelConfig ( uint32_t PWR_PVDLevel )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
PWR_PVDLevel,: specifies the PVD detection level. This parameter can be one of the following values:

  • PWR_PVDLevel_0: PVD detection level set to 1.9V.
  • PWR_PVDLevel_1: PVD detection level set to 2.1V.
  • PWR_PVDLevel_2: PVD detection level set to 2.3V.
  • PWR_PVDLevel_3: PVD detection level set to 2.5V.
  • PWR_PVDLevel_4: PVD detection level set to 2.7V.
  • PWR_PVDLevel_5: PVD detection level set to 2.9V.
  • PWR_PVDLevel_6: PVD detection level set to 3.1V.
  • PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).
Return values:
None

Definition at line 182 of file stm32l1xx_pwr.c.

References CR_PLS_MASK, IS_PWR_PVD_LEVEL, and PWR.

void PWR_RTCAccessCmd ( FunctionalState NewState )

Enables or disables access to the RTC and backup registers.

Note:
If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the RTC Domain Access should be kept enabled.
Parameters:
NewState,: new state of the access to the RTC and backup registers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 134 of file stm32l1xx_pwr.c.

References CR_DBP_BB, and IS_FUNCTIONAL_STATE.

void PWR_UltraLowPowerCmd ( FunctionalState NewState )

Enables or disables the Ultra Low Power mode.

Parameters:
NewState,: new state of the Ultra Low Power mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 305 of file stm32l1xx_pwr.c.

References CR_ULP_BB, and IS_FUNCTIONAL_STATE.

void PWR_VoltageScalingConfig ( uint32_t PWR_VoltageScaling )

Configures the voltage scaling range.

Note:
During voltage scaling configuration, the system clock is stopped until the regulator is stabilized (VOSF = 0). This must be taken into account during application developement, in case a critical reaction time to interrupt is needed, and depending on peripheral used (timer, communication,...).
Parameters:
PWR_VoltageScaling,: specifies the voltage scaling range. This parameter can be:

  • PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).
  • PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).
  • PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V)
Return values:
None

Definition at line 402 of file stm32l1xx_pwr.c.

References CR_VOS_MASK, IS_PWR_VOLTAGE_SCALING_RANGE, and PWR.

void PWR_WakeUpPinCmd | ( | uint32_t | PWR_WakeUpPin,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the WakeUp Pin functionality.

Parameters:
PWR_WakeUpPin,: specifies the WakeUpPin. This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
NewState,: new state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 244 of file stm32l1xx_pwr.c.

References CSR_EWUP_BB, IS_FUNCTIONAL_STATE, and IS_PWR_WAKEUP_PIN.


STM32L1xx Standard Peripherals Firmware Library: RCC_HSE_configuration

Defines

RCC_HSE_configuration

RCC_Exported_Constants

Defines

#define | IS_RCC_HSE(HSE)
#define | RCC_HSE_Bypass ((uint8_t)0x05)
#define | RCC_HSE_OFF ((uint8_t)0x00)
#define | RCC_HSE_ON ((uint8_t)0x01)

Define Documentation

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))

Definition at line 68 of file stm32l1xx_rcc.h.

Referenced by RCC_HSEConfig().

#define RCC_HSE_Bypass ((uint8_t)0x05)

Definition at line 67 of file stm32l1xx_rcc.h.

#define RCC_HSE_OFF ((uint8_t)0x00)

Definition at line 65 of file stm32l1xx_rcc.h.

Referenced by RCC_HSEConfig().

#define RCC_HSE_ON ((uint8_t)0x01)

Definition at line 66 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_MSI_Clock_Range

Defines

RCC_MSI_Clock_Range

RCC_Exported_Constants

Defines

#define | IS_RCC_MSI_CLOCK_RANGE(RANGE)
#define | RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0
#define | RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1
#define | RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2
#define | RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3
#define | RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4
#define | RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5
#define | RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6

Define Documentation

#define IS_RCC_MSI_CLOCK_RANGE ( RANGE )
Value:
(((RANGE) == RCC_MSIRange_0) || \
                                       ((RANGE) == RCC_MSIRange_1) || \
                                       ((RANGE) == RCC_MSIRange_2) || \
                                       ((RANGE) == RCC_MSIRange_3) || \
                                       ((RANGE) == RCC_MSIRange_4) || \
                                       ((RANGE) == RCC_MSIRange_5) || \
                                       ((RANGE) == RCC_MSIRange_6))

Definition at line 87 of file stm32l1xx_rcc.h.

Referenced by RCC_MSIRangeConfig().

#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0

MSI = 65.536 KHz

Definition at line 79 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1

MSI = 131.072 KHz

Definition at line 80 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2

MSI = 262.144 KHz

Definition at line 81 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3

MSI = 524.288 KHz

Definition at line 82 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4

MSI = 1.048 MHz

Definition at line 83 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5

MSI = 2.097 MHz

Definition at line 84 of file stm32l1xx_rcc.h.

#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6

MSI = 4.194 MHz

Definition at line 85 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_PLL_Clock_Source

Defines

RCC_PLL_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_PLL_SOURCE(SOURCE)
#define | RCC_PLLSource_HSE ((uint8_t)0x01)
#define | RCC_PLLSource_HSI ((uint8_t)0x00)

Define Documentation

#define IS_RCC_PLL_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSource_HSI) || \
                                   ((SOURCE) == RCC_PLLSource_HSE))

Definition at line 106 of file stm32l1xx_rcc.h.

Referenced by RCC_PLLConfig().

#define RCC_PLLSource_HSE ((uint8_t)0x01)

Definition at line 104 of file stm32l1xx_rcc.h.

#define RCC_PLLSource_HSI ((uint8_t)0x00)

Definition at line 103 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_PLL_Multiplication_Factor

Defines

RCC_PLL_Multiplication_Factor

RCC_Exported_Constants

Defines

#define | IS_RCC_PLL_MUL(MUL)
#define | RCC_PLLMul_12 ((uint8_t)0x10)
#define | RCC_PLLMul_16 ((uint8_t)0x14)
#define | RCC_PLLMul_24 ((uint8_t)0x18)
#define | RCC_PLLMul_3 ((uint8_t)0x00)
#define | RCC_PLLMul_32 ((uint8_t)0x1C)
#define | RCC_PLLMul_4 ((uint8_t)0x04)
#define | RCC_PLLMul_48 ((uint8_t)0x20)
#define | RCC_PLLMul_6 ((uint8_t)0x08)
#define | RCC_PLLMul_8 ((uint8_t)0x0C)

Define Documentation

#define IS_RCC_PLL_MUL ( MUL )
Value:
(((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
                             ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
                             ((MUL) == RCC_PLLMul_48))

Definition at line 127 of file stm32l1xx_rcc.h.

Referenced by RCC_PLLConfig().

#define RCC_PLLMul_12 ((uint8_t)0x10)

Definition at line 120 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_16 ((uint8_t)0x14)

Definition at line 121 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_24 ((uint8_t)0x18)

Definition at line 122 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_3 ((uint8_t)0x00)

Definition at line 116 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_32 ((uint8_t)0x1C)

Definition at line 123 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_4 ((uint8_t)0x04)

Definition at line 117 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_48 ((uint8_t)0x20)

Definition at line 124 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_6 ((uint8_t)0x08)

Definition at line 118 of file stm32l1xx_rcc.h.

#define RCC_PLLMul_8 ((uint8_t)0x0C)

Definition at line 119 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_PLL_Divider_Factor

Defines

RCC_PLL_Divider_Factor

RCC_Exported_Constants

Defines

#define | IS_RCC_PLL_DIV(DIV)
#define | RCC_PLLDiv_2 ((uint8_t)0x40)
#define | RCC_PLLDiv_3 ((uint8_t)0x80)
#define | RCC_PLLDiv_4 ((uint8_t)0xC0)

Define Documentation

#define IS_RCC_PLL_DIV ( DIV )
Value:
(((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
                             ((DIV) == RCC_PLLDiv_4))

Definition at line 145 of file stm32l1xx_rcc.h.

Referenced by RCC_PLLConfig().

#define RCC_PLLDiv_2 ((uint8_t)0x40)

Definition at line 140 of file stm32l1xx_rcc.h.

#define RCC_PLLDiv_3 ((uint8_t)0x80)

Definition at line 141 of file stm32l1xx_rcc.h.

#define RCC_PLLDiv_4 ((uint8_t)0xC0)

Definition at line 142 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_System_Clock_Source

Defines

RCC_System_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_SYSCLK_SOURCE(SOURCE)
#define | RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
#define | RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define IS_RCC_SYSCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSource_MSI) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))

Definition at line 159 of file stm32l1xx_rcc.h.

Referenced by RCC_SYSCLKConfig().

#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE

Definition at line 157 of file stm32l1xx_rcc.h.

#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI

Definition at line 156 of file stm32l1xx_rcc.h.

#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI

Definition at line 155 of file stm32l1xx_rcc.h.

#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL

Definition at line 158 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_AHB_Clock_Source

Defines

RCC_AHB_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_HCLK(HCLK)
#define | RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
#define | RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8

Define Documentation

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))

Definition at line 180 of file stm32l1xx_rcc.h.

Referenced by RCC_HCLKConfig().

#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1

Definition at line 171 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128

Definition at line 177 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16

Definition at line 175 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2

Definition at line 172 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256

Definition at line 178 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4

Definition at line 173 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512

Definition at line 179 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64

Definition at line 176 of file stm32l1xx_rcc.h.

#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8

Definition at line 174 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_APB1_APB2_Clock_Source

Defines

RCC_APB1_APB2_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_PCLK(PCLK)
#define | RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
#define | RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8

Define Documentation

#define IS_RCC_PCLK ( PCLK )
Value:
(((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))

Definition at line 198 of file stm32l1xx_rcc.h.

Referenced by RCC_PCLK1Config(), and RCC_PCLK2Config().

#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1

Definition at line 193 of file stm32l1xx_rcc.h.

#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16

Definition at line 197 of file stm32l1xx_rcc.h.

#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2

Definition at line 194 of file stm32l1xx_rcc.h.

#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4

Definition at line 195 of file stm32l1xx_rcc.h.

#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8

Definition at line 196 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_Interrupt_Source

Defines

RCC_Interrupt_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_GET_IT(IT)
#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define | RCC_IT_CSS ((uint8_t)0x80)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_LSECSS ((uint8_t)0x40)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_MSIRDY ((uint8_t)0x20)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)

Define Documentation

#define IS_RCC_CLEAR_IT ( IT ) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))

Definition at line 226 of file stm32l1xx_rcc.h.

Referenced by RCC_ClearITPendingBit().

#define IS_RCC_GET_IT ( IT )
Value:
(((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
                           ((IT) == RCC_IT_CSS)  || ((IT) == RCC_IT_LSECSS))

Definition at line 221 of file stm32l1xx_rcc.h.

Referenced by RCC_GetITStatus().

#define IS_RCC_IT ( IT ) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))

Definition at line 219 of file stm32l1xx_rcc.h.

Referenced by RCC_ITConfig().

#define RCC_IT_CSS ((uint8_t)0x80)

Definition at line 217 of file stm32l1xx_rcc.h.

#define RCC_IT_HSERDY ((uint8_t)0x08)

Definition at line 213 of file stm32l1xx_rcc.h.

#define RCC_IT_HSIRDY ((uint8_t)0x04)

Definition at line 212 of file stm32l1xx_rcc.h.

#define RCC_IT_LSECSS ((uint8_t)0x40)

Definition at line 216 of file stm32l1xx_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)0x02)

Definition at line 211 of file stm32l1xx_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)0x01)

Definition at line 210 of file stm32l1xx_rcc.h.

#define RCC_IT_MSIRDY ((uint8_t)0x20)

Definition at line 215 of file stm32l1xx_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)0x10)

Definition at line 214 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_LSE_Configuration

Defines

RCC_LSE_Configuration

RCC_Exported_Constants

Defines

#define | IS_RCC_LSE(LSE)
#define | RCC_LSE_Bypass ((uint8_t)0x05)
#define | RCC_LSE_OFF ((uint8_t)0x00)
#define | RCC_LSE_ON ((uint8_t)0x01)

Define Documentation

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))

Definition at line 239 of file stm32l1xx_rcc.h.

Referenced by RCC_LSEConfig().

#define RCC_LSE_Bypass ((uint8_t)0x05)

Definition at line 238 of file stm32l1xx_rcc.h.

#define RCC_LSE_OFF ((uint8_t)0x00)

Definition at line 236 of file stm32l1xx_rcc.h.

Referenced by RCC_LSEConfig().

#define RCC_LSE_ON ((uint8_t)0x01)

Definition at line 237 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_RTC_Clock_Source

Defines

RCC_RTC_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_RTCCLK_SOURCE(SOURCE)
#define | RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
#define | RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
#define | RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
#define | RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
#define | RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
#define | RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI

Define Documentation

#define IS_RCC_RTCCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_RTCCLKSource_LSE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))

Definition at line 255 of file stm32l1xx_rcc.h.

Referenced by RCC_RTCCLKConfig().

#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)

Definition at line 254 of file stm32l1xx_rcc.h.

#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE

Definition at line 251 of file stm32l1xx_rcc.h.

#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)

Definition at line 252 of file stm32l1xx_rcc.h.

#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)

Definition at line 253 of file stm32l1xx_rcc.h.

#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE

Definition at line 249 of file stm32l1xx_rcc.h.

#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI

Definition at line 250 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_AHB_Peripherals

Defines

RCC_AHB_Peripherals

RCC_Exported_Constants

Defines

#define | IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_AHBPeriph_AES RCC_AHBENR_AESEN
#define | RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
#define | RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
#define | RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
#define | RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
#define | RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN
#define | RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
#define | RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
#define | RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
#define | RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
#define | RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
#define | RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
#define | RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
#define | RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
#define | RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN

Define Documentation

#define IS_RCC_AHB_LPMODE_PERIPH ( PERIPH ) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))

Definition at line 286 of file stm32l1xx_rcc.h.

Referenced by RCC_AHBPeriphClockLPModeCmd().

#define IS_RCC_AHB_PERIPH ( PERIPH ) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))

Definition at line 285 of file stm32l1xx_rcc.h.

Referenced by RCC_AHBPeriphClockCmd(), and RCC_AHBPeriphResetCmd().

#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN

Definition at line 282 of file stm32l1xx_rcc.h.

Referenced by AES_DeInit().

#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN

Definition at line 277 of file stm32l1xx_rcc.h.

#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN

Definition at line 280 of file stm32l1xx_rcc.h.

#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN

Definition at line 281 of file stm32l1xx_rcc.h.

#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN

Definition at line 278 of file stm32l1xx_rcc.h.

#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN

Definition at line 283 of file stm32l1xx_rcc.h.

#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN

Definition at line 269 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN

Definition at line 270 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN

Definition at line 271 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN

Definition at line 272 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN

Definition at line 273 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN

Definition at line 275 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN

Definition at line 276 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN

Definition at line 274 of file stm32l1xx_rcc.h.

Referenced by GPIO_DeInit().

#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN

Definition at line 279 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_APB2_Peripherals

Defines

RCC_APB2_Peripherals

RCC_Exported_Constants

Defines

#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
#define | RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN
#define | RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
#define | RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
#define | RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
#define | RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
#define | RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN

Define Documentation

#define IS_RCC_APB2_PERIPH ( PERIPH ) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))

Definition at line 305 of file stm32l1xx_rcc.h.

Referenced by RCC_APB2PeriphClockCmd(), RCC_APB2PeriphClockLPModeCmd(), and RCC_APB2PeriphResetCmd().

#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN

Definition at line 300 of file stm32l1xx_rcc.h.

Referenced by ADC_DeInit().

#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN

Definition at line 301 of file stm32l1xx_rcc.h.

Referenced by SDIO_DeInit().

#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 302 of file stm32l1xx_rcc.h.

Referenced by SPI_I2S_DeInit().

#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN

Definition at line 296 of file stm32l1xx_rcc.h.

Referenced by SYSCFG_DeInit().

#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN

Definition at line 298 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN

Definition at line 299 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN

Definition at line 297 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN

Definition at line 303 of file stm32l1xx_rcc.h.

Referenced by USART_DeInit().


STM32L1xx Standard Peripherals Firmware Library: RCC_APB1_Peripherals

Defines

RCC_APB1_Peripherals

RCC_Exported_Constants

Defines

#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
#define | RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
#define | RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
#define | RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
#define | RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
#define | RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
#define | RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
#define | RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
#define | RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
#define | RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
#define | RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
#define | RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
#define | RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
#define | RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
#define | RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
#define | RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
#define | RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
#define | RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
#define | RCC_APB1Periph_USB RCC_APB1ENR_USBEN
#define | RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN

Define Documentation

#define IS_RCC_APB1_PERIPH ( PERIPH ) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))

Definition at line 336 of file stm32l1xx_rcc.h.

Referenced by RCC_APB1PeriphClockCmd(), RCC_APB1PeriphClockLPModeCmd(), and RCC_APB1PeriphResetCmd().

#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN

Definition at line 333 of file stm32l1xx_rcc.h.

#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN

Definition at line 332 of file stm32l1xx_rcc.h.

Referenced by DAC_DeInit().

#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN

Definition at line 328 of file stm32l1xx_rcc.h.

Referenced by I2C_DeInit().

#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN

Definition at line 329 of file stm32l1xx_rcc.h.

Referenced by I2C_DeInit().

#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN

Definition at line 320 of file stm32l1xx_rcc.h.

Referenced by LCD_DeInit().

#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN

Definition at line 331 of file stm32l1xx_rcc.h.

Referenced by PWR_DeInit().

#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN

Definition at line 322 of file stm32l1xx_rcc.h.

Referenced by SPI_I2S_DeInit().

#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN

Definition at line 323 of file stm32l1xx_rcc.h.

Referenced by SPI_I2S_DeInit().

#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN

Definition at line 314 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN

Definition at line 315 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN

Definition at line 316 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN

Definition at line 317 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN

Definition at line 318 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN

Definition at line 319 of file stm32l1xx_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN

Definition at line 326 of file stm32l1xx_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN

Definition at line 327 of file stm32l1xx_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN

Definition at line 324 of file stm32l1xx_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN

Definition at line 325 of file stm32l1xx_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN

Definition at line 330 of file stm32l1xx_rcc.h.

#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN

Definition at line 321 of file stm32l1xx_rcc.h.

Referenced by WWDG_DeInit().


STM32L1xx Standard Peripherals Firmware Library: RCC_MCO_Clock_Source

Defines

RCC_MCO_Clock_Source

RCC_Exported_Constants

Defines

#define | IS_RCC_MCO_SOURCE(SOURCE)
#define | RCC_MCOSource_HSE ((uint8_t)0x04)
#define | RCC_MCOSource_HSI ((uint8_t)0x02)
#define | RCC_MCOSource_LSE ((uint8_t)0x07)
#define | RCC_MCOSource_LSI ((uint8_t)0x06)
#define | RCC_MCOSource_MSI ((uint8_t)0x03)
#define | RCC_MCOSource_NoClock ((uint8_t)0x00)
#define | RCC_MCOSource_PLLCLK ((uint8_t)0x05)
#define | RCC_MCOSource_SYSCLK ((uint8_t)0x01)

Define Documentation

#define IS_RCC_MCO_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
                                   ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_MSI) || \
                                   ((SOURCE) == RCC_MCOSource_HSE)  || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
                                   ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))

Definition at line 354 of file stm32l1xx_rcc.h.

Referenced by RCC_MCOConfig().

#define RCC_MCOSource_HSE ((uint8_t)0x04)

Definition at line 349 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_HSI ((uint8_t)0x02)

Definition at line 347 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_LSE ((uint8_t)0x07)

Definition at line 352 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_LSI ((uint8_t)0x06)

Definition at line 351 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_MSI ((uint8_t)0x03)

Definition at line 348 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_NoClock ((uint8_t)0x00)

Definition at line 345 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)

Definition at line 350 of file stm32l1xx_rcc.h.

#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)

Definition at line 346 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_MCO_Output_Divider

Defines

RCC_MCO_Output_Divider

RCC_Exported_Constants

Defines

#define | IS_RCC_MCO_DIV(DIV)
#define | RCC_MCODiv_1 ((uint8_t)0x00)
#define | RCC_MCODiv_16 ((uint8_t)0x40)
#define | RCC_MCODiv_2 ((uint8_t)0x10)
#define | RCC_MCODiv_4 ((uint8_t)0x20)
#define | RCC_MCODiv_8 ((uint8_t)0x30)

Define Documentation

#define IS_RCC_MCO_DIV ( DIV )
Value:
(((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
                             ((DIV) == RCC_MCODiv_4)  || ((DIV) == RCC_MCODiv_8) || \
                             ((DIV) == RCC_MCODiv_16))

Definition at line 372 of file stm32l1xx_rcc.h.

Referenced by RCC_MCOConfig().

#define RCC_MCODiv_1 ((uint8_t)0x00)

Definition at line 366 of file stm32l1xx_rcc.h.

#define RCC_MCODiv_16 ((uint8_t)0x40)

Definition at line 370 of file stm32l1xx_rcc.h.

#define RCC_MCODiv_2 ((uint8_t)0x10)

Definition at line 367 of file stm32l1xx_rcc.h.

#define RCC_MCODiv_4 ((uint8_t)0x20)

Definition at line 368 of file stm32l1xx_rcc.h.

#define RCC_MCODiv_8 ((uint8_t)0x30)

Definition at line 369 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: RCC_Flag

Defines

RCC_Flag

RCC_Exported_Constants

Defines

#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x5D)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x5F)
#define | RCC_FLAG_LSECSS ((uint8_t)0x4A)
#define | RCC_FLAG_LSERDY ((uint8_t)0x49)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x41)
#define | RCC_FLAG_MSIRDY ((uint8_t)0x29)
#define | RCC_FLAG_OBLRST ((uint8_t)0x59)
#define | RCC_FLAG_PINRST ((uint8_t)0x5A)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PORRST ((uint8_t)0x5B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x5C)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x5E)

Define Documentation

#define IS_RCC_FLAG ( FLAG )
Value:
(((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
                           ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
                           ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LSECSS))

Definition at line 398 of file stm32l1xx_rcc.h.

Referenced by RCC_GetFlagStatus().

#define IS_RCC_HSI_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 406 of file stm32l1xx_rcc.h.

Referenced by RCC_AdjustHSICalibrationValue().

#define IS_RCC_MSI_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x3F)

Definition at line 407 of file stm32l1xx_rcc.h.

Referenced by RCC_AdjustMSICalibrationValue().

#define RCC_FLAG_HSERDY ((uint8_t)0x31)

Definition at line 385 of file stm32l1xx_rcc.h.

Referenced by RCC_WaitForHSEStartUp().

#define RCC_FLAG_HSIRDY ((uint8_t)0x21)

Definition at line 383 of file stm32l1xx_rcc.h.

#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)

Definition at line 394 of file stm32l1xx_rcc.h.

#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)

Definition at line 396 of file stm32l1xx_rcc.h.

#define RCC_FLAG_LSECSS ((uint8_t)0x4A)

Definition at line 388 of file stm32l1xx_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x49)

Definition at line 387 of file stm32l1xx_rcc.h.

#define RCC_FLAG_LSIRDY ((uint8_t)0x41)

Definition at line 389 of file stm32l1xx_rcc.h.

#define RCC_FLAG_MSIRDY ((uint8_t)0x29)

Definition at line 384 of file stm32l1xx_rcc.h.

#define RCC_FLAG_OBLRST ((uint8_t)0x59)

Definition at line 390 of file stm32l1xx_rcc.h.

#define RCC_FLAG_PINRST ((uint8_t)0x5A)

Definition at line 391 of file stm32l1xx_rcc.h.

#define RCC_FLAG_PLLRDY ((uint8_t)0x39)

Definition at line 386 of file stm32l1xx_rcc.h.

#define RCC_FLAG_PORRST ((uint8_t)0x5B)

Definition at line 392 of file stm32l1xx_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)0x5C)

Definition at line 393 of file stm32l1xx_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)

Definition at line 395 of file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: Internal and external clocks, PLL, CSS and MCO configuration functions

Functions

Internal and external clocks, PLL, CSS and MCO configuration functions

RCC_Private_Functions

Internal and external clocks, PLL, CSS and MCO configuration functions. More...

Functions

void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_HSEConfig (uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_LSEClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the LSE Clock Security System.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
Selects the clock source to output on MCO pin (PA8).
void | RCC_MSICmd (FunctionalState NewState)
Enables or disables the Internal Multi Speed oscillator (MSI).
void | RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
Configures the Internal Multi Speed oscillator (MSI) clock range.
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
Configures the PLL clock source and multiplication factor.
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Detailed Description

Internal and external clocks, PLL, CSS and MCO configuration functions.

 ===============================================================================
 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the internal/external
         clocks, PLL, CSS and MCO.
         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
             or through the PLL as System clock source.
         (#) MSI (multi-speed internal), multispeed low power RC
             (65.536 KHz to 4.194 MHz) MHz used as System clock source.
         (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
             and/or RTC clock source.
         (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
             directly or through the PLL as System clock source. Can be used
             also as RTC clock source.
         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
         (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
         (#) CSS (Clock security system), once enable and if a HSE clock failure
             occurs (HSE used directly or through PLL as System clock source),
             the System clock is automatically switched to MSI and an interrupt
             is generated if enabled.
             The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
             exception vector.
         (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
             HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
             PA8 pin.

Function Documentation

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the HSI.
Parameters:
HSICalibrationValue,: specifies the HSI calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None

Definition at line 383 of file stm32l1xx_rcc.c.

References IS_RCC_HSI_CALIBRATION_VALUE, RCC, and RCC_ICSCR_HSITRIM.

void RCC_AdjustMSICalibrationValue ( uint8_t MSICalibrationValue )

Adjusts the Internal Multi Speed oscillator (MSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.
Parameters:
MSICalibrationValue,: specifies the MSI calibration trimming value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 300 of file stm32l1xx_rcc.c.

References ICSCR_BYTE4_ADDRESS, and IS_RCC_MSI_CALIBRATION_VALUE.

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Parameters:
NewState,: new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 553 of file stm32l1xx_rcc.c.

References CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
MSI ON and used as system clock source (MSI range is not modified by this function, it keep the value configured by user application)
HSI, HSE and PLL OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS and MCO OFF
All interrupts disabled
However, this function doesn't modify the configuration of the
Peripheral clocks
LSI, LSE and RTC clocks
Parameters:
None
Return values:
None

Definition at line 199 of file stm32l1xx_rcc.c.

References RCC.

void RCC_HSEConfig ( uint8_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note:
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
RCC_HSE,: specifies the new state of the HSE. This parameter can be one of the following values:

  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values:
None

Definition at line 241 of file stm32l1xx_rcc.c.

References CR_BYTE3_ADDRESS, IS_RCC_HSE, and RCC_HSE_OFF.

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note:
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.
HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.
The HSI is stopped by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 417 of file stm32l1xx_rcc.c.

References CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_LSEClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the LSE Clock Security System.

Parameters:
NewState,: new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 567 of file stm32l1xx_rcc.c.

References CSR_LSECSSON_BB, and IS_FUNCTIONAL_STATE.

void RCC_LSEConfig ( uint8_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Note:
As the LSE is in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
RCC_LSE,: specifies the new state of the LSE. This parameter can be one of the following values:

  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None

Definition at line 442 of file stm32l1xx_rcc.c.

References CSR_BYTE2_ADDRESS, IS_RCC_LSE, and RCC_LSE_OFF.

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Note:
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

Definition at line 466 of file stm32l1xx_rcc.c.

References CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_MCOConfig | ( | uint8_t | RCC_MCOSource,
 |  | uint8_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO pin (PA8).

Note:
PA8 should be configured in alternate function mode.
Parameters:
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:

  • RCC_MCOSource_NoClock: No clock selected
  • RCC_MCOSource_SYSCLK: System clock selected
  • RCC_MCOSource_HSI: HSI oscillator clock selected
  • RCC_MCOSource_MSI: MSI oscillator clock selected
  • RCC_MCOSource_HSE: HSE oscillator clock selected
  • RCC_MCOSource_PLLCLK: PLL clock selected
  • RCC_MCOSource_LSI: LSI clock selected
  • RCC_MCOSource_LSE: LSE clock selected
RCC_MCODiv,: specifies the MCO prescaler. This parameter can be one of the following values:

  • RCC_MCODiv_1: no division applied to MCO clock
  • RCC_MCODiv_2: division by 2 applied to MCO clock
  • RCC_MCODiv_4: division by 4 applied to MCO clock
  • RCC_MCODiv_8: division by 8 applied to MCO clock
  • RCC_MCODiv_16: division by 16 applied to MCO clock
Return values:
None

Definition at line 597 of file stm32l1xx_rcc.c.

References CFGR_BYTE4_ADDRESS, IS_RCC_MCO_DIV, and IS_RCC_MCO_SOURCE.

void RCC_MSICmd ( FunctionalState NewState )

Enables or disables the Internal Multi Speed oscillator (MSI).

Note:
The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.
After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.
Parameters:
NewState,: new state of the MSI. This parameter can be: ENABLE or DISABLE.
Note:
When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.
Return values:
None

Definition at line 365 of file stm32l1xx_rcc.c.

References CR_MSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_MSIRangeConfig ( uint32_t RCC_MSIRange )

Configures the Internal Multi Speed oscillator (MSI) clock range.

Note:
After restart from Reset or wakeup from STANDBY, the MSI clock is around 2.097 MHz. The MSI clock does not change after wake-up from STOP mode.
The MSI clock range can be modified on the fly.
Parameters:
RCC_MSIRange,: specifies the MSI Clock range. This parameter must be one of the following values:

  • RCC_MSIRange_0: MSI clock is around 65.536 KHz
  • RCC_MSIRange_1: MSI clock is around 131.072 KHz
  • RCC_MSIRange_2: MSI clock is around 262.144 KHz
  • RCC_MSIRange_3: MSI clock is around 524.288 KHz
  • RCC_MSIRange_4: MSI clock is around 1.048 MHz
  • RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
  • RCC_MSIRange_6: MSI clock is around 4.194 MHz
Return values:
None

Definition at line 327 of file stm32l1xx_rcc.c.

References IS_RCC_MSI_CLOCK_RANGE, RCC, and RCC_ICSCR_MSIRANGE.

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the PLL.

Note:
After enabling the PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The PLL can not be disabled if it is used as system clock source
The PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 534 of file stm32l1xx_rcc.c.

References CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

void RCC_PLLConfig | ( | uint8_t | RCC_PLLSource,
 |  | uint8_t | RCC_PLLMul,
 |  | uint8_t | RCC_PLLDiv
 | ) |  |

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,: specifies the PLL entry clock source. This parameter can be one of the following values:

  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
Note:
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
Parameters:
RCC_PLLMul,: specifies the PLL multiplication factor, which drive the PLLVCO clock This parameter can be:

  • RCC_PLLMul_3: PLL clock source multiplied by 3
  • RCC_PLLMul_4: PLL clock source multiplied by 4
  • RCC_PLLMul_6: PLL clock source multiplied by 6
  • RCC_PLLMul_8: PLL clock source multiplied by 8
  • RCC_PLLMul_12: PLL clock source multiplied by 12
  • RCC_PLLMul_16: PLL clock source multiplied by 16
  • RCC_PLLMul_24: PLL clock source multiplied by 24
  • RCC_PLLMul_32: PLL clock source multiplied by 32
  • RCC_PLLMul_48: PLL clock source multiplied by 48
Note:
The application software must set correctly the PLL multiplication factor to avoid exceeding:
  • 96 MHz as PLLVCO when the product is in range 1
  • 48 MHz as PLLVCO when the product is in range 2
  • 24 MHz when the product is in range 3
When using the USB the PLLVCO should be 96MHz
Parameters:
RCC_PLLDiv,: specifies the PLL division factor. This parameter can be:

  • RCC_PLLDiv_2: PLL Clock output divided by 2
  • RCC_PLLDiv_3: PLL Clock output divided by 3
  • RCC_PLLDiv_4: PLL Clock output divided by 4
Note:
The application software must set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
Return values:
None

Definition at line 513 of file stm32l1xx_rcc.c.

References CFGR_BYTE3_ADDRESS, IS_RCC_PLL_DIV, IS_RCC_PLL_MUL, and IS_RCC_PLL_SOURCE.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Note:
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

Definition at line 266 of file stm32l1xx_rcc.c.

References ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, and SUCCESS.


STM32L1xx Standard Peripherals Firmware Library: System AHB and APB busses clocks configuration functions

Functions

System AHB and APB busses clocks configuration functions

RCC_Private_Functions

System, AHB and APB busses clocks configuration functions. More...

Functions

void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of the System, AHB and APB busses clocks.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).

Detailed Description

System, AHB and APB busses clocks configuration functions.

 ===============================================================================
     ##### System, AHB and APB busses clocks configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the System, AHB,
         APB1 and APB2 busses clocks.
         (#) Several clock sources can be used to drive the System clock (SYSCLK):
             MSI, HSI, HSE and PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are
             derived from AHB clock through configurable prescalers and used to
             clock the peripherals mapped on these busses. You can use
             "RCC_GetClocksFreq()" function to retrieve the frequencies of these
             clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK)
             except:
             (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
             (+@) The ADC clock which is always the HSI clock. A divider by 1, 2
                  or 4 allows to adapt the clock frequency to the device operating
                  conditions.
             (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz
                  HSE_RTC (HSE divided by a programmable prescaler).
                  The System clock (SYSCLK) frequency must be higher or equal to
                  the RTC/LCD clock frequency.
             (+@) IWDG clock which is always the LSI clock.

         (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly:

        +----------------------------------------------------------------+
        |  Wait states  |                HCLK clock frequency (MHz)      |
        |               |------------------------------------------------|
        |   (Latency)   |            voltage range       | voltage range |
        |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
        |               |----------------|---------------|---------------|
        |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
        |-------------- |----------------|---------------|---------------|
        |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
        |---------------|----------------|---------------|---------------|
        |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
        +----------------------------------------------------------------+

         (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS,
             Flash 32-bit access is enabled and prefetch is disabled.
    [..] It is recommended to use the following software sequences to tune the
         number of wait states needed to access the Flash memory with the CPU
         frequency (HCLK).
         (+) Increasing the CPU frequency (in the same voltage range)
         (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)"
             function
         (+) Check that 64-bit access is taken into account by reading FLASH_ACR
         (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)"
             function
         (+) Check that the new number of WS is taken into account by reading
             FLASH_ACR
         (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
         (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
             function
         (+) Check that the new CPU clock source is taken into account by reading
           the clock source status, using "RCC_GetSYSCLKSource()" function
         (+) Decreasing the CPU frequency (in the same voltage range)
         (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
         (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
             function
         (+) Check that the new CPU clock source is taken into account by reading
           the clock source status, using "RCC_GetSYSCLKSource()" function
         (+) Program the new number of WS, using "FLASH_SetLatency()" function
         (+) Check that the new number of WS is taken into account by reading
             FLASH_ACR
         (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)"
             function
         (+) Check that 32-bit access is taken into account by reading FLASH_ACR

Function Documentation

void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks )

Returns the frequencies of the System, AHB and APB busses clocks.

Note:
The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig():
If SYSCLK source is MSI, function returns values based on MSI Value as defined by the MSI range, refer to RCC_MSIRangeConfig()
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().

(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
Parameters:
RCC_Clocks,: pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values:
None

Definition at line 888 of file stm32l1xx_rcc.c.

References APBAHBPrescTable, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, PLLMulTable, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLDIV, RCC_CFGR_PLLMUL, RCC_CFGR_PLLSRC, RCC_CFGR_PPRE1, RCC_CFGR_PPRE2, RCC_CFGR_SWS, RCC_ICSCR_MSIRANGE, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by I2C_Init(), I2S_Init(), and USART_Init().

uint8_t RCC_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
The clock source used as system clock. The returned value can be one of the following values:

  • 0x00: MSI used as system clock
  • 0x04: HSI used as system clock
  • 0x08: HSE used as system clock
  • 0x0C: PLL used as system clock

Definition at line 743 of file stm32l1xx_rcc.c.

References RCC, and RCC_CFGR_SWS.

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Configures the AHB clock (HCLK).

Note:
Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
Parameters:
RCC_SYSCLK,: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None

Definition at line 768 of file stm32l1xx_rcc.c.

References IS_RCC_HCLK, RCC, and RCC_CFGR_HPRE.

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None

Definition at line 799 of file stm32l1xx_rcc.c.

References IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE1.

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,: defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None

Definition at line 830 of file stm32l1xx_rcc.c.

References IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE2.

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Configures the system clock (SYSCLK).

Note:
The MSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
Parameters:
RCC_SYSCLKSource,: specifies the clock source used as system clock source This parameter can be one of the following values:

  • RCC_SYSCLKSource_MSI: MSI selected as system clock source
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values:
None

Definition at line 714 of file stm32l1xx_rcc.c.

References IS_RCC_SYSCLK_SOURCE, RCC, and RCC_CFGR_SW.


STM32L1xx Standard Peripherals Firmware Library: Peripheral clocks configuration functions

Functions

Peripheral clocks configuration functions

RCC_Private_Functions

Peripheral clocks configuration functions. More...

Functions

void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock during SLEEP mode.
void | RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during SLEEP mode.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during SLEEP mode.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC and LCD clock (RTCCLK / LCDCLK).
void | RCC_RTCResetCmd (FunctionalState NewState)
Forces or releases the RTC peripheral and associated resources reset.

Detailed Description

Peripheral clocks configuration functions.

 ===============================================================================
             ##### Peripheral clocks configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the Peripheral clocks.
         (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
         (HSE divided by a programmable prescaler).
         (#) After restart from Reset or wakeup from STANDBY, all peripherals are
             off except internal SRAM, Flash and JTAG. Before to start using a
             peripheral you have to enable its interface clock. You can do this
             using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and
             RCC_APB1PeriphClockCmd() functions.

         (#) To reset the peripherals configuration (to the default state after
             device reset) you can use RCC_AHBPeriphResetCmd(),
             RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.
         (#) To further reduce power consumption in SLEEP mode the peripheral
             clocks can be disabled prior to executing the WFI or WFE instructions.
             You can do this using RCC_AHBPeriphClockLPModeCmd(),
             RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd()
             functions.

Function Documentation

void RCC_AHBPeriphClockCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1102 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

void RCC_AHBPeriphClockLPModeCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
  • After wakeup from SLEEP mode, the peripheral clock is enabled again.
  • By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_SRAM: SRAM clock
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1341 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_LPMODE_PERIPH, and RCC.

void RCC_AHBPeriphResetCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases AHB peripheral reset.

Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to reset. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1222 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

Referenced by AES_DeInit(), and GPIO_DeInit().

void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP COMP clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1184 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB1PeriphClockLPModeCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the APB1 peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP: COMP clock
NewState,: new state
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1426 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1298 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by DAC_DeInit(), I2C_DeInit(), LCD_DeInit(), PWR_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), USART_DeInit(), and WWDG_DeInit().

void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
  • RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
  • RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
  • RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
  • RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
  • RCC_APB2Periph_SDIO: SDIO APB2 Clock.
  • RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
  • RCC_APB2Periph_USART1: USART1 APB2 Clock.
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1137 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

void RCC_APB2PeriphClockLPModeCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the APB2 peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_USART1: USART1 clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1377 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_USART1: USART1 clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1254 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by ADC_DeInit(), SDIO_DeInit(), SPI_I2S_DeInit(), SYSCFG_DeInit(), TIM_DeInit(), and USART_DeInit().

void RCC_RTCCLKCmd ( FunctionalState NewState )

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1053 of file stm32l1xx_rcc.c.

References CSR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Configures the RTC and LCD clock (RTCCLK / LCDCLK).

Note:
As the RTC clock configuration bits are in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
Parameters:
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 1017 of file stm32l1xx_rcc.c.

References IS_RCC_RTCCLK_SOURCE, RCC, RCC_CR_RTCPRE, RCC_CSR_RTCSEL, and RCC_CSR_RTCSEL_HSE.

void RCC_RTCResetCmd ( FunctionalState NewState )

Forces or releases the RTC peripheral and associated resources reset.

Note:
This function resets the RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers.
Parameters:
NewState,: new state of the RTC reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1069 of file stm32l1xx_rcc.c.

References CSR_RTCRST_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

RCC_Private_Functions

Interrupts and flags management functions. More...

Functions

void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
             ##### Interrupts and flags management functions #####
 ===============================================================================

Function Documentation

void RCC_ClearFlag ( void )

Clears the RCC reset flags.

The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Parameters:
None
Return values:
None

Definition at line 1560 of file stm32l1xx_rcc.c.

References RCC, and RCC_CSR_RMVF.

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Clears the RCC's interrupt pending bits.

Parameters:
RCC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
None

Definition at line 1613 of file stm32l1xx_rcc.c.

References CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_MSIRDY: MSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
The new state of RCC_FLAG (SET or RESET).

Definition at line 1517 of file stm32l1xx_rcc.c.

References FLAG_MASK, IS_RCC_FLAG, RCC, RESET, and SET.

Referenced by RCC_WaitForHSEStartUp().

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,: specifies the RCC interrupt source to check. This parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of RCC_IT (SET or RESET).

Definition at line 1580 of file stm32l1xx_rcc.c.

References IS_RCC_GET_IT, RCC, RESET, and SET.

void RCC_ITConfig | ( | uint8_t | RCC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RCC interrupts.

Note:
The CSS interrupt doesn't have an enable bit; once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely, and since NMI has higher priority than any other IRQ (and main program) the application will be stacked in the NMI ISR unless the CSS interrupt pending bit is cleared.
Parameters:
RCC_IT,: specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
NewState,: new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1479 of file stm32l1xx_rcc.c.

References CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.


STM32L1xx Standard Peripherals Firmware Library: RCC

Data Structures | Modules | Defines | Functions | Variables

RCC

STM32L1xx_StdPeriph_Driver

RCC driver modules. More...

Data Structures

struct | RCC_ClocksTypeDef

Modules

RCC_Exported_Constants
RCC_Private_Functions

Defines

#define | CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
#define | CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
#define | CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
#define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
#define | CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
#define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define | CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
#define | CR_OFFSET (RCC_OFFSET + 0x00)
#define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define | CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
#define | CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))
#define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define | CSR_OFFSET (RCC_OFFSET + 0x34)
#define | CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define | CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
#define | CSSON_BitNumber 0x1C
#define | FLAG_MASK ((uint8_t)0x1F)
#define | HSION_BitNumber 0x00
#define | ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
#define | LSECSSON_BitNumber 0x0B
#define | LSION_BitNumber 0x00
#define | MSION_BitNumber 0x08
#define | PLLON_BitNumber 0x18
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RTCEN_BitNumber 0x16
#define | RTCRST_BitNumber 0x17

Functions

void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock during SLEEP mode.
void | RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during SLEEP mode.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during SLEEP mode.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of the System, AHB and APB busses clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the LSE Clock Security System.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
Selects the clock source to output on MCO pin (PA8).
void | RCC_MSICmd (FunctionalState NewState)
Enables or disables the Internal Multi Speed oscillator (MSI).
void | RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
Configures the Internal Multi Speed oscillator (MSI) clock range.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC and LCD clock (RTCCLK / LCDCLK).
void | RCC_RTCResetCmd (FunctionalState NewState)
Forces or releases the RTC peripheral and associated resources reset.
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Variables

static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}
static __I uint8_t | PLLMulTable [9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}

Detailed Description

RCC driver modules.

Define Documentation

#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)

Definition at line 123 of file stm32l1xx_rcc.c.

Referenced by RCC_PLLConfig().

#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)

Definition at line 126 of file stm32l1xx_rcc.c.

Referenced by RCC_MCOConfig().

#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)

Definition at line 129 of file stm32l1xx_rcc.c.

Referenced by RCC_ITConfig().

#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)

Definition at line 132 of file stm32l1xx_rcc.c.

Referenced by RCC_ClearITPendingBit().

#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)

Definition at line 117 of file stm32l1xx_rcc.c.

Referenced by RCC_HSEConfig().

#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))

Definition at line 90 of file stm32l1xx_rcc.c.

Referenced by RCC_ClockSecuritySystemCmd().

#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))

Definition at line 78 of file stm32l1xx_rcc.c.

Referenced by RCC_HSICmd().

#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))

Definition at line 82 of file stm32l1xx_rcc.c.

Referenced by RCC_MSICmd().

#define CR_OFFSET (RCC_OFFSET + 0x00)

Definition at line 76 of file stm32l1xx_rcc.c.

#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

Definition at line 86 of file stm32l1xx_rcc.c.

Referenced by RCC_PLLCmd().

#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)

Definition at line 135 of file stm32l1xx_rcc.c.

Referenced by RCC_LSEConfig().

#define CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))

Definition at line 101 of file stm32l1xx_rcc.c.

Referenced by RCC_LSEClockSecuritySystemCmd().

#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

Definition at line 97 of file stm32l1xx_rcc.c.

Referenced by RCC_LSICmd().

#define CSR_OFFSET (RCC_OFFSET + 0x34)

Definition at line 95 of file stm32l1xx_rcc.c.

#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))

Definition at line 105 of file stm32l1xx_rcc.c.

Referenced by RCC_RTCCLKCmd().

#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))

Definition at line 109 of file stm32l1xx_rcc.c.

Referenced by RCC_RTCResetCmd().

#define CSSON_BitNumber 0x1C

Definition at line 89 of file stm32l1xx_rcc.c.

#define FLAG_MASK ((uint8_t)0x1F)

Definition at line 114 of file stm32l1xx_rcc.c.

Referenced by RCC_GetFlagStatus().

#define HSION_BitNumber 0x00

Definition at line 77 of file stm32l1xx_rcc.c.

#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)

Definition at line 120 of file stm32l1xx_rcc.c.

Referenced by RCC_AdjustMSICalibrationValue().

#define LSECSSON_BitNumber 0x0B

Definition at line 100 of file stm32l1xx_rcc.c.

#define LSION_BitNumber 0x00

Definition at line 96 of file stm32l1xx_rcc.c.

#define MSION_BitNumber 0x08

Definition at line 81 of file stm32l1xx_rcc.c.

#define PLLON_BitNumber 0x18

Definition at line 85 of file stm32l1xx_rcc.c.

#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

Definition at line 71 of file stm32l1xx_rcc.c.

#define RTCEN_BitNumber 0x16

Definition at line 104 of file stm32l1xx_rcc.c.

#define RTCRST_BitNumber 0x17

Definition at line 108 of file stm32l1xx_rcc.c.

Function Documentation

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the HSI.
Parameters:
HSICalibrationValue,: specifies the HSI calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None

Definition at line 383 of file stm32l1xx_rcc.c.

References IS_RCC_HSI_CALIBRATION_VALUE, RCC, and RCC_ICSCR_HSITRIM.

void RCC_AdjustMSICalibrationValue ( uint8_t MSICalibrationValue )

Adjusts the Internal Multi Speed oscillator (MSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.
Parameters:
MSICalibrationValue,: specifies the MSI calibration trimming value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 300 of file stm32l1xx_rcc.c.

References ICSCR_BYTE4_ADDRESS, and IS_RCC_MSI_CALIBRATION_VALUE.

void RCC_AHBPeriphClockCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1102 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

void RCC_AHBPeriphClockLPModeCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
  • After wakeup from SLEEP mode, the peripheral clock is enabled again.
  • By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_SRAM: SRAM clock
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1341 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_LPMODE_PERIPH, and RCC.

void RCC_AHBPeriphResetCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases AHB peripheral reset.

Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to reset. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA: GPIOA clock
  • RCC_AHBPeriph_GPIOB: GPIOB clock
  • RCC_AHBPeriph_GPIOC: GPIOC clock
  • RCC_AHBPeriph_GPIOD: GPIOD clock
  • RCC_AHBPeriph_GPIOE: GPIOE clock
  • RCC_AHBPeriph_GPIOH: GPIOH clock
  • RCC_AHBPeriph_GPIOF: GPIOF clock
  • RCC_AHBPeriph_GPIOG: GPIOG clock
  • RCC_AHBPeriph_CRC: CRC clock
  • RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1: DMA1 clock
  • RCC_AHBPeriph_DMA2: DMA2 clock
  • RCC_AHBPeriph_AES: AES clock
  • RCC_AHBPeriph_FSMC: FSMC clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1222 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

Referenced by AES_DeInit(), and GPIO_DeInit().

void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP COMP clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1184 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB1PeriphClockLPModeCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the APB1 peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP: COMP clock
NewState,: new state
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1426 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_LCD: LCD clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_USB: USB clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
  • RCC_APB1Periph_COMP
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1298 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by DAC_DeInit(), I2C_DeInit(), LCD_DeInit(), PWR_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), USART_DeInit(), and WWDG_DeInit().

void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
  • RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
  • RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
  • RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
  • RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
  • RCC_APB2Periph_SDIO: SDIO APB2 Clock.
  • RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
  • RCC_APB2Periph_USART1: USART1 APB2 Clock.
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1137 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

void RCC_APB2PeriphClockLPModeCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the APB2 peripheral clock during SLEEP mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_USART1: USART1 clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1377 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_USART1: USART1 clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1254 of file stm32l1xx_rcc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by ADC_DeInit(), SDIO_DeInit(), SPI_I2S_DeInit(), SYSCFG_DeInit(), TIM_DeInit(), and USART_DeInit().

void RCC_ClearFlag ( void )

Clears the RCC reset flags.

The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Parameters:
None
Return values:
None

Definition at line 1560 of file stm32l1xx_rcc.c.

References RCC, and RCC_CSR_RMVF.

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Clears the RCC's interrupt pending bits.

Parameters:
RCC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
None

Definition at line 1613 of file stm32l1xx_rcc.c.

References CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Parameters:
NewState,: new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 553 of file stm32l1xx_rcc.c.

References CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
MSI ON and used as system clock source (MSI range is not modified by this function, it keep the value configured by user application)
HSI, HSE and PLL OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS and MCO OFF
All interrupts disabled
However, this function doesn't modify the configuration of the
Peripheral clocks
LSI, LSE and RTC clocks
Parameters:
None
Return values:
None

Definition at line 199 of file stm32l1xx_rcc.c.

References RCC.

void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks )

Returns the frequencies of the System, AHB and APB busses clocks.

Note:
The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig():
If SYSCLK source is MSI, function returns values based on MSI Value as defined by the MSI range, refer to RCC_MSIRangeConfig()
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().

(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
Parameters:
RCC_Clocks,: pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values:
None

Definition at line 888 of file stm32l1xx_rcc.c.

References APBAHBPrescTable, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, PLLMulTable, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLDIV, RCC_CFGR_PLLMUL, RCC_CFGR_PLLSRC, RCC_CFGR_PPRE1, RCC_CFGR_PPRE2, RCC_CFGR_SWS, RCC_ICSCR_MSIRANGE, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by I2C_Init(), I2S_Init(), and USART_Init().

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_MSIRDY: MSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
The new state of RCC_FLAG (SET or RESET).

Definition at line 1517 of file stm32l1xx_rcc.c.

References FLAG_MASK, IS_RCC_FLAG, RCC, RESET, and SET.

Referenced by RCC_WaitForHSEStartUp().

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,: specifies the RCC interrupt source to check. This parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of RCC_IT (SET or RESET).

Definition at line 1580 of file stm32l1xx_rcc.c.

References IS_RCC_GET_IT, RCC, RESET, and SET.

uint8_t RCC_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
The clock source used as system clock. The returned value can be one of the following values:

  • 0x00: MSI used as system clock
  • 0x04: HSI used as system clock
  • 0x08: HSE used as system clock
  • 0x0C: PLL used as system clock

Definition at line 743 of file stm32l1xx_rcc.c.

References RCC, and RCC_CFGR_SWS.

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Configures the AHB clock (HCLK).

Note:
Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
Parameters:
RCC_SYSCLK,: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None

Definition at line 768 of file stm32l1xx_rcc.c.

References IS_RCC_HCLK, RCC, and RCC_CFGR_HPRE.

void RCC_HSEConfig ( uint8_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note:
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
RCC_HSE,: specifies the new state of the HSE. This parameter can be one of the following values:

  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values:
None

Definition at line 241 of file stm32l1xx_rcc.c.

References CR_BYTE3_ADDRESS, IS_RCC_HSE, and RCC_HSE_OFF.

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note:
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.
HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.
The HSI is stopped by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 417 of file stm32l1xx_rcc.c.

References CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_ITConfig | ( | uint8_t | RCC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RCC interrupts.

Note:
The CSS interrupt doesn't have an enable bit; once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely, and since NMI has higher priority than any other IRQ (and main program) the application will be stacked in the NMI ISR unless the CSS interrupt pending bit is cleared.
Parameters:
RCC_IT,: specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_LSECSS: LSE CSS interrupt
NewState,: new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1479 of file stm32l1xx_rcc.c.

References CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.

void RCC_LSEClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the LSE Clock Security System.

Parameters:
NewState,: new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 567 of file stm32l1xx_rcc.c.

References CSR_LSECSSON_BB, and IS_FUNCTIONAL_STATE.

void RCC_LSEConfig ( uint8_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Note:
As the LSE is in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
RCC_LSE,: specifies the new state of the LSE. This parameter can be one of the following values:

  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None

Definition at line 442 of file stm32l1xx_rcc.c.

References CSR_BYTE2_ADDRESS, IS_RCC_LSE, and RCC_LSE_OFF.

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Note:
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

Definition at line 466 of file stm32l1xx_rcc.c.

References CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_MCOConfig | ( | uint8_t | RCC_MCOSource,
 |  | uint8_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO pin (PA8).

Note:
PA8 should be configured in alternate function mode.
Parameters:
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:

  • RCC_MCOSource_NoClock: No clock selected
  • RCC_MCOSource_SYSCLK: System clock selected
  • RCC_MCOSource_HSI: HSI oscillator clock selected
  • RCC_MCOSource_MSI: MSI oscillator clock selected
  • RCC_MCOSource_HSE: HSE oscillator clock selected
  • RCC_MCOSource_PLLCLK: PLL clock selected
  • RCC_MCOSource_LSI: LSI clock selected
  • RCC_MCOSource_LSE: LSE clock selected
RCC_MCODiv,: specifies the MCO prescaler. This parameter can be one of the following values:

  • RCC_MCODiv_1: no division applied to MCO clock
  • RCC_MCODiv_2: division by 2 applied to MCO clock
  • RCC_MCODiv_4: division by 4 applied to MCO clock
  • RCC_MCODiv_8: division by 8 applied to MCO clock
  • RCC_MCODiv_16: division by 16 applied to MCO clock
Return values:
None

Definition at line 597 of file stm32l1xx_rcc.c.

References CFGR_BYTE4_ADDRESS, IS_RCC_MCO_DIV, and IS_RCC_MCO_SOURCE.

void RCC_MSICmd ( FunctionalState NewState )

Enables or disables the Internal Multi Speed oscillator (MSI).

Note:
The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.
After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.
Parameters:
NewState,: new state of the MSI. This parameter can be: ENABLE or DISABLE.
Note:
When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.
Return values:
None

Definition at line 365 of file stm32l1xx_rcc.c.

References CR_MSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_MSIRangeConfig ( uint32_t RCC_MSIRange )

Configures the Internal Multi Speed oscillator (MSI) clock range.

Note:
After restart from Reset or wakeup from STANDBY, the MSI clock is around 2.097 MHz. The MSI clock does not change after wake-up from STOP mode.
The MSI clock range can be modified on the fly.
Parameters:
RCC_MSIRange,: specifies the MSI Clock range. This parameter must be one of the following values:

  • RCC_MSIRange_0: MSI clock is around 65.536 KHz
  • RCC_MSIRange_1: MSI clock is around 131.072 KHz
  • RCC_MSIRange_2: MSI clock is around 262.144 KHz
  • RCC_MSIRange_3: MSI clock is around 524.288 KHz
  • RCC_MSIRange_4: MSI clock is around 1.048 MHz
  • RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
  • RCC_MSIRange_6: MSI clock is around 4.194 MHz
Return values:
None

Definition at line 327 of file stm32l1xx_rcc.c.

References IS_RCC_MSI_CLOCK_RANGE, RCC, and RCC_ICSCR_MSIRANGE.

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None

Definition at line 799 of file stm32l1xx_rcc.c.

References IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE1.

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,: defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None

Definition at line 830 of file stm32l1xx_rcc.c.

References IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE2.

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the PLL.

Note:
After enabling the PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The PLL can not be disabled if it is used as system clock source
The PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 534 of file stm32l1xx_rcc.c.

References CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

void RCC_PLLConfig | ( | uint8_t | RCC_PLLSource,
 |  | uint8_t | RCC_PLLMul,
 |  | uint8_t | RCC_PLLDiv
 | ) |  |

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,: specifies the PLL entry clock source. This parameter can be one of the following values:

  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
Note:
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
Parameters:
RCC_PLLMul,: specifies the PLL multiplication factor, which drive the PLLVCO clock This parameter can be:

  • RCC_PLLMul_3: PLL clock source multiplied by 3
  • RCC_PLLMul_4: PLL clock source multiplied by 4
  • RCC_PLLMul_6: PLL clock source multiplied by 6
  • RCC_PLLMul_8: PLL clock source multiplied by 8
  • RCC_PLLMul_12: PLL clock source multiplied by 12
  • RCC_PLLMul_16: PLL clock source multiplied by 16
  • RCC_PLLMul_24: PLL clock source multiplied by 24
  • RCC_PLLMul_32: PLL clock source multiplied by 32
  • RCC_PLLMul_48: PLL clock source multiplied by 48
Note:
The application software must set correctly the PLL multiplication factor to avoid exceeding:
  • 96 MHz as PLLVCO when the product is in range 1
  • 48 MHz as PLLVCO when the product is in range 2
  • 24 MHz when the product is in range 3
When using the USB the PLLVCO should be 96MHz
Parameters:
RCC_PLLDiv,: specifies the PLL division factor. This parameter can be:

  • RCC_PLLDiv_2: PLL Clock output divided by 2
  • RCC_PLLDiv_3: PLL Clock output divided by 3
  • RCC_PLLDiv_4: PLL Clock output divided by 4
Note:
The application software must set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
Return values:
None

Definition at line 513 of file stm32l1xx_rcc.c.

References CFGR_BYTE3_ADDRESS, IS_RCC_PLL_DIV, IS_RCC_PLL_MUL, and IS_RCC_PLL_SOURCE.

void RCC_RTCCLKCmd ( FunctionalState NewState )

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1053 of file stm32l1xx_rcc.c.

References CSR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Configures the RTC and LCD clock (RTCCLK / LCDCLK).

Note:
As the RTC clock configuration bits are in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
Parameters:
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 1017 of file stm32l1xx_rcc.c.

References IS_RCC_RTCCLK_SOURCE, RCC, RCC_CR_RTCPRE, RCC_CSR_RTCSEL, and RCC_CSR_RTCSEL_HSE.

void RCC_RTCResetCmd ( FunctionalState NewState )

Forces or releases the RTC peripheral and associated resources reset.

Note:
This function resets the RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers.
Parameters:
NewState,: new state of the RTC reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1069 of file stm32l1xx_rcc.c.

References CSR_RTCRST_BB, and IS_FUNCTIONAL_STATE.

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Configures the system clock (SYSCLK).

Note:
The MSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
Parameters:
RCC_SYSCLKSource,: specifies the clock source used as system clock source This parameter can be one of the following values:

  • RCC_SYSCLKSource_MSI: MSI selected as system clock source
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values:
None

Definition at line 714 of file stm32l1xx_rcc.c.

References IS_RCC_SYSCLK_SOURCE, RCC, and RCC_CFGR_SW.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Note:
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

Definition at line 266 of file stm32l1xx_rcc.c.

References ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, and SUCCESS.

Variable Documentation

__I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} [static]

Definition at line 141 of file stm32l1xx_rcc.c.

Referenced by RCC_GetClocksFreq().

__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48} [static]

Definition at line 140 of file stm32l1xx_rcc.c.


STM32L1xx Standard Peripherals Firmware Library: RCC_ClocksTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RCC_ClocksTypeDef Struct Reference
RCC

#include <stm32l1xx_rcc.h>

Data Fields

uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency
uint32_t | SYSCLK_Frequency

Detailed Description

Definition at line 47 of file stm32l1xx_rcc.h.

Field Documentation

uint32_t RCC_ClocksTypeDef::HCLK_Frequency

Definition at line 50 of file stm32l1xx_rcc.h.

Referenced by RCC_GetClocksFreq().

uint32_t RCC_ClocksTypeDef::PCLK1_Frequency

Definition at line 51 of file stm32l1xx_rcc.h.

Referenced by I2C_Init(), RCC_GetClocksFreq(), and USART_Init().

uint32_t RCC_ClocksTypeDef::PCLK2_Frequency

Definition at line 52 of file stm32l1xx_rcc.h.

Referenced by RCC_GetClocksFreq(), and USART_Init().

uint32_t RCC_ClocksTypeDef::SYSCLK_Frequency

Definition at line 49 of file stm32l1xx_rcc.h.

Referenced by I2S_Init(), and RCC_GetClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32l1xx_rcc.h


STM32L1xx Standard Peripherals Firmware Library: RTC_Hour_Formats

Defines

RTC_Hour_Formats

RTC_Exported_Constants

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | RTC_HourFormat_12 ((uint32_t)0x00000040)
#define | RTC_HourFormat_24 ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HourFormat_12) || \
                                        ((FORMAT) == RTC_HourFormat_24))

Definition at line 132 of file stm32l1xx_rtc.h.

Referenced by RTC_Init().

#define RTC_HourFormat_12 ((uint32_t)0x00000040)

Definition at line 131 of file stm32l1xx_rtc.h.

#define RTC_HourFormat_24 ((uint32_t)0x00000000)

Definition at line 130 of file stm32l1xx_rtc.h.

Referenced by RTC_StructInit().


STM32L1xx Standard Peripherals Firmware Library: RTC_Asynchronous_Predivider

Defines

RTC_Asynchronous_Predivider

RTC_Exported_Constants

Defines

#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)

Define Documentation

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7F)

Definition at line 141 of file stm32l1xx_rtc.h.

Referenced by RTC_Init().


STM32L1xx Standard Peripherals Firmware Library: RTC_Synchronous_Predivider

Defines

RTC_Synchronous_Predivider

RTC_Exported_Constants

Defines

#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)

Define Documentation

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7FFF)

Definition at line 151 of file stm32l1xx_rtc.h.

Referenced by RTC_Init().


STM32L1xx Standard Peripherals Firmware Library: RTC_Time_Definitions

Defines

RTC_Time_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)

Define Documentation

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > 0) && ((HOUR) <= 12))

Definition at line 160 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm(), and RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23)

Definition at line 161 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm(), and RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59)

Definition at line 162 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm(), and RTC_SetTime().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59)

Definition at line 163 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm(), and RTC_SetTime().


STM32L1xx Standard Peripherals Firmware Library: RTC_AM_PM_Definitions

Defines

RTC_AM_PM_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
#define | RTC_H12_AM ((uint8_t)0x00)
#define | RTC_H12_PM ((uint8_t)0x40)

Define Documentation

#define IS_RTC_H12 ( PM ) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))

Definition at line 174 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm(), and RTC_SetTime().

#define RTC_H12_AM ((uint8_t)0x00)

Definition at line 172 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), and RTC_TimeStructInit().

#define RTC_H12_PM ((uint8_t)0x40)

Definition at line 173 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Year_Date_Definitions

Defines

RTC_Year_Date_Definitions

RTC_Exported_Constants

Defines

#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)

Define Documentation

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99)

Definition at line 183 of file stm32l1xx_rtc.h.

Referenced by RTC_SetDate().


STM32L1xx Standard Peripherals Firmware Library: RTC_Month_Date_Definitions

Defines

RTC_Month_Date_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
#define | RTC_Month_April ((uint8_t)0x04)
#define | RTC_Month_August ((uint8_t)0x08)
#define | RTC_Month_December ((uint8_t)0x12)
#define | RTC_Month_February ((uint8_t)0x02)
#define | RTC_Month_January ((uint8_t)0x01)
#define | RTC_Month_July ((uint8_t)0x07)
#define | RTC_Month_June ((uint8_t)0x06)
#define | RTC_Month_March ((uint8_t)0x03)
#define | RTC_Month_May ((uint8_t)0x05)
#define | RTC_Month_November ((uint8_t)0x11)
#define | RTC_Month_October ((uint8_t)0x10)
#define | RTC_Month_September ((uint8_t)0x09)

Define Documentation

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1) && ((DATE) <= 31))

Definition at line 207 of file stm32l1xx_rtc.h.

Referenced by RTC_SetDate().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1) && ((MONTH) <= 12))

Definition at line 206 of file stm32l1xx_rtc.h.

Referenced by RTC_SetDate().

#define RTC_Month_April ((uint8_t)0x04)

Definition at line 197 of file stm32l1xx_rtc.h.

#define RTC_Month_August ((uint8_t)0x08)

Definition at line 201 of file stm32l1xx_rtc.h.

#define RTC_Month_December ((uint8_t)0x12)

Definition at line 205 of file stm32l1xx_rtc.h.

#define RTC_Month_February ((uint8_t)0x02)

Definition at line 195 of file stm32l1xx_rtc.h.

#define RTC_Month_January ((uint8_t)0x01)

Definition at line 194 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit().

#define RTC_Month_July ((uint8_t)0x07)

Definition at line 200 of file stm32l1xx_rtc.h.

#define RTC_Month_June ((uint8_t)0x06)

Definition at line 199 of file stm32l1xx_rtc.h.

#define RTC_Month_March ((uint8_t)0x03)

Definition at line 196 of file stm32l1xx_rtc.h.

#define RTC_Month_May ((uint8_t)0x05)

Definition at line 198 of file stm32l1xx_rtc.h.

#define RTC_Month_November ((uint8_t)0x11)

Definition at line 204 of file stm32l1xx_rtc.h.

#define RTC_Month_October ((uint8_t)0x10)

Definition at line 203 of file stm32l1xx_rtc.h.

#define RTC_Month_September ((uint8_t)0x09)

Definition at line 202 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_WeekDay_Definitions

Defines

RTC_WeekDay_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | RTC_Weekday_Friday ((uint8_t)0x05)
#define | RTC_Weekday_Monday ((uint8_t)0x01)
#define | RTC_Weekday_Saturday ((uint8_t)0x06)
#define | RTC_Weekday_Sunday ((uint8_t)0x07)
#define | RTC_Weekday_Thursday ((uint8_t)0x04)
#define | RTC_Weekday_Tuesday ((uint8_t)0x02)
#define | RTC_Weekday_Wednesday ((uint8_t)0x03)

Define Documentation

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_Weekday_Monday) || \
                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
                                 ((WEEKDAY) == RTC_Weekday_Sunday))

Definition at line 224 of file stm32l1xx_rtc.h.

Referenced by RTC_SetDate().

#define RTC_Weekday_Friday ((uint8_t)0x05)

Definition at line 221 of file stm32l1xx_rtc.h.

#define RTC_Weekday_Monday ((uint8_t)0x01)

Definition at line 217 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit().

#define RTC_Weekday_Saturday ((uint8_t)0x06)

Definition at line 222 of file stm32l1xx_rtc.h.

#define RTC_Weekday_Sunday ((uint8_t)0x07)

Definition at line 223 of file stm32l1xx_rtc.h.

#define RTC_Weekday_Thursday ((uint8_t)0x04)

Definition at line 220 of file stm32l1xx_rtc.h.

#define RTC_Weekday_Tuesday ((uint8_t)0x02)

Definition at line 218 of file stm32l1xx_rtc.h.

#define RTC_Weekday_Wednesday ((uint8_t)0x03)

Definition at line 219 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Alarm_Definitions

Defines

RTC_Alarm_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)

Define Documentation

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) > 0) && ((DATE) <= 31))

Definition at line 239 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_Weekday_Monday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
                                                    ((WEEKDAY) == RTC_Weekday_Sunday))

Definition at line 240 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm().


STM32L1xx Standard Peripherals Firmware Library: RTC_AlarmDateWeekDay_Definitions

Defines

RTC_AlarmDateWeekDay_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
#define | RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)

Define Documentation

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))

Definition at line 259 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm().

#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)

Definition at line 256 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), and RTC_SetAlarm().

#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)

Definition at line 257 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_AlarmMask_Definitions

Defines

RTC_AlarmMask_Definitions

RTC_Exported_Constants

Defines

#define | IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | RTC_AlarmMask_All ((uint32_t)0x80808080)
#define | RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
#define | RTC_AlarmMask_Hours ((uint32_t)0x00800000)
#define | RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
#define | RTC_AlarmMask_None ((uint32_t)0x00000000)
#define | RTC_AlarmMask_Seconds ((uint32_t)0x00000080)

Define Documentation

#define IS_ALARM_MASK ( MASK ) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)

Definition at line 276 of file stm32l1xx_rtc.h.

Referenced by RTC_SetAlarm().

#define RTC_AlarmMask_All ((uint32_t)0x80808080)

Definition at line 275 of file stm32l1xx_rtc.h.

Referenced by RTC_GetAlarm().

#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)

Definition at line 271 of file stm32l1xx_rtc.h.

#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)

Definition at line 272 of file stm32l1xx_rtc.h.

#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)

Definition at line 273 of file stm32l1xx_rtc.h.

#define RTC_AlarmMask_None ((uint32_t)0x00000000)

Definition at line 270 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit().

#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)

Definition at line 274 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Alarms_Definitions

Defines

RTC_Alarms_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
#define | IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
#define | RTC_Alarm_A ((uint32_t)0x00000100)
#define | RTC_Alarm_B ((uint32_t)0x00000200)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))

Definition at line 287 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmSubSecondConfig(), RTC_GetAlarm(), and RTC_SetAlarm().

#define IS_RTC_CMD_ALARM ( ALARM ) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)

Definition at line 288 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmCmd().

#define RTC_Alarm_A ((uint32_t)0x00000100)

Definition at line 285 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmSubSecondConfig(), RTC_GetAlarm(), RTC_GetAlarmSubSecond(), and RTC_SetAlarm().

#define RTC_Alarm_B ((uint32_t)0x00000200)

Definition at line 286 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Alarm_Sub_Seconds_Masks_Definitions

Defines

RTC_Alarm_Sub_Seconds_Masks_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000)
#define | RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000)
#define | RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000)
#define | RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000)
#define | RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000)
#define | RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000)
#define | RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000)
#define | RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000)
#define | RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000)
#define | RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000)
#define | RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000)
#define | RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000)

Define Documentation

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_AlarmSubSecondMask_All) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
                                              ((MASK) == RTC_AlarmSubSecondMask_None))

Definition at line 330 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmSubSecondConfig().

#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 297 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000)

SS[14:0] are compared and must match to activate alarm.

Definition at line 328 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000)

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 326 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000)

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 300 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 318 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 320 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000)

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

Definition at line 322 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 324 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000)

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 302 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000)

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 304 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 306 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000)

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 308 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 310 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

Definition at line 312 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 314 of file stm32l1xx_rtc.h.

#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000)

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 316 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Alarm_Sub_Seconds_Value

Defines

RTC_Alarm_Sub_Seconds_Value

RTC_Exported_Constants

Defines

#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)

Define Documentation

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= 0x00007FFF)

Definition at line 354 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmSubSecondConfig().


STM32L1xx Standard Peripherals Firmware Library: RTC_Wakeup_Timer_Definitions

Defines

RTC_Wakeup_Timer_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
#define | RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
#define | RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
#define | RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
#define | RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
#define | RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)

Define Documentation

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))

Definition at line 369 of file stm32l1xx_rtc.h.

Referenced by RTC_WakeUpClockConfig().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= 0xFFFF)

Definition at line 375 of file stm32l1xx_rtc.h.

Referenced by RTC_SetWakeUpCounter().

#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)

Definition at line 367 of file stm32l1xx_rtc.h.

#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)

Definition at line 368 of file stm32l1xx_rtc.h.

#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)

Definition at line 363 of file stm32l1xx_rtc.h.

#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)

Definition at line 366 of file stm32l1xx_rtc.h.

#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)

Definition at line 365 of file stm32l1xx_rtc.h.

#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)

Definition at line 364 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Time_Stamp_Edges_definitions

Defines

RTC_Time_Stamp_Edges_definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TIMESTAMP_EDGE(EDGE)
#define | RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
#define | RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TimeStampEdge_Rising) || \
                                     ((EDGE) == RTC_TimeStampEdge_Falling))

Definition at line 385 of file stm32l1xx_rtc.h.

Referenced by RTC_TimeStampCmd().

#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)

Definition at line 384 of file stm32l1xx_rtc.h.

#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)

Definition at line 383 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Output_selection_Definitions

Defines

RTC_Output_selection_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | RTC_Output_AlarmA ((uint32_t)0x00200000)
#define | RTC_Output_AlarmB ((uint32_t)0x00400000)
#define | RTC_Output_Disable ((uint32_t)0x00000000)
#define | RTC_Output_WakeUp ((uint32_t)0x00600000)

Define Documentation

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_Output_Disable) || \
                               ((OUTPUT) == RTC_Output_AlarmA) || \
                               ((OUTPUT) == RTC_Output_AlarmB) || \
                               ((OUTPUT) == RTC_Output_WakeUp))

Definition at line 399 of file stm32l1xx_rtc.h.

Referenced by RTC_OutputConfig().

#define RTC_Output_AlarmA ((uint32_t)0x00200000)

Definition at line 395 of file stm32l1xx_rtc.h.

#define RTC_Output_AlarmB ((uint32_t)0x00400000)

Definition at line 396 of file stm32l1xx_rtc.h.

#define RTC_Output_Disable ((uint32_t)0x00000000)

Definition at line 394 of file stm32l1xx_rtc.h.

#define RTC_Output_WakeUp ((uint32_t)0x00600000)

Definition at line 397 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Output_Polarity_Definitions

Defines

RTC_Output_Polarity_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_OUTPUT_POL(POL)
#define | RTC_OutputPolarity_High ((uint32_t)0x00000000)
#define | RTC_OutputPolarity_Low ((uint32_t)0x00100000)

Define Documentation

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OutputPolarity_High) || \
                                ((POL) == RTC_OutputPolarity_Low))

Definition at line 413 of file stm32l1xx_rtc.h.

Referenced by RTC_OutputConfig().

#define RTC_OutputPolarity_High ((uint32_t)0x00000000)

Definition at line 411 of file stm32l1xx_rtc.h.

#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)

Definition at line 412 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Coarse_Calibration_Definitions

Defines

RTC_Coarse_Calibration_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_CALIB_SIGN(SIGN)
#define | IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
#define | RTC_CalibSign_Negative ((uint32_t)0x00000080)
#define | RTC_CalibSign_Positive ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_CALIB_SIGN ( SIGN )
Value:
(((SIGN) == RTC_CalibSign_Positive) || \
                                 ((SIGN) == RTC_CalibSign_Negative))

Definition at line 424 of file stm32l1xx_rtc.h.

Referenced by RTC_CoarseCalibConfig().

#define IS_RTC_CALIB_VALUE ( VALUE ) ((VALUE) < 0x20)

Definition at line 426 of file stm32l1xx_rtc.h.

Referenced by RTC_CoarseCalibConfig().

#define RTC_CalibSign_Negative ((uint32_t)0x00000080)

Definition at line 423 of file stm32l1xx_rtc.h.

#define RTC_CalibSign_Positive ((uint32_t)0x00000000)

Definition at line 422 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Calib_Output_selection_Definitions

Defines

RTC_Calib_Output_selection_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_CALIB_OUTPUT(OUTPUT)
#define | RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
#define | RTC_CalibOutput_512Hz ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CalibOutput_512Hz) || \
                                      ((OUTPUT) == RTC_CalibOutput_1Hz))

Definition at line 437 of file stm32l1xx_rtc.h.

Referenced by RTC_CalibOutputConfig().

#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)

Definition at line 436 of file stm32l1xx_rtc.h.

#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)

Definition at line 435 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Smooth_calib_period_Definitions

Defines

RTC_Smooth_calib_period_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000)
#define | RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000)
#define | RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000)

Define Documentation

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))

Definition at line 452 of file stm32l1xx_rtc.h.

Referenced by RTC_SmoothCalibConfig().

#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000)

if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds

Definition at line 448 of file stm32l1xx_rtc.h.

#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000)

if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds

Definition at line 446 of file stm32l1xx_rtc.h.

#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000)

if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds

Definition at line 450 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Smooth_calib_Plus_pulses_Definitions

Defines

RTC_Smooth_calib_Plus_pulses_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000)
#define | RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000)

Define Documentation

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))

Definition at line 468 of file stm32l1xx_rtc.h.

Referenced by RTC_SmoothCalibConfig().

#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0].

Definition at line 466 of file stm32l1xx_rtc.h.

#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000)

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0]. with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 463 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Smooth_calib_Minus_pulses_Definitions

Defines

RTC_Smooth_calib_Minus_pulses_Definitions

RTC_Exported_Constants

Defines

#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)

Define Documentation

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= 0x000001FF)

Definition at line 478 of file stm32l1xx_rtc.h.

Referenced by RTC_SmoothCalibConfig().


STM32L1xx Standard Peripherals Firmware Library: RTC_DayLightSaving_Definitions

Defines

RTC_DayLightSaving_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
#define | RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
#define | RTC_StoreOperation_Reset ((uint32_t)0x00000000)
#define | RTC_StoreOperation_Set ((uint32_t)0x00040000)

Define Documentation

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DayLightSaving_SUB1H) || \
                                      ((SAVE) == RTC_DayLightSaving_ADD1H))

Definition at line 489 of file stm32l1xx_rtc.h.

Referenced by RTC_DayLightSavingConfig().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_StoreOperation_Reset) || \
                                           ((OPERATION) == RTC_StoreOperation_Set))

Definition at line 494 of file stm32l1xx_rtc.h.

Referenced by RTC_DayLightSavingConfig().

#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)

Definition at line 488 of file stm32l1xx_rtc.h.

#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)

Definition at line 487 of file stm32l1xx_rtc.h.

#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)

Definition at line 492 of file stm32l1xx_rtc.h.

#define RTC_StoreOperation_Set ((uint32_t)0x00040000)

Definition at line 493 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Tamper_Trigger_Definitions

Defines

RTC_Tamper_Trigger_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
#define | RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
#define | RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
#define | RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel))

Definition at line 507 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperTriggerConfig().

#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)

Definition at line 504 of file stm32l1xx_rtc.h.

#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)

Definition at line 506 of file stm32l1xx_rtc.h.

#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)

Definition at line 505 of file stm32l1xx_rtc.h.

#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)

Definition at line 503 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperTriggerConfig().


STM32L1xx Standard Peripherals Firmware Library: RTC_Tamper_Filter_Definitions

Defines

RTC_Tamper_Filter_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | RTC_TamperFilter_2Sample ((uint32_t)0x00000800)
#define | RTC_TamperFilter_4Sample ((uint32_t)0x00001000)
#define | RTC_TamperFilter_8Sample ((uint32_t)0x00001800)
#define | RTC_TamperFilter_Disable ((uint32_t)0x00000000)

Define Documentation

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TamperFilter_Disable) || \
                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
                                      ((FILTER) == RTC_TamperFilter_8Sample))

Definition at line 527 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperFilterConfig().

#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800)

Tamper is activated after 2 consecutive samples at the active level

Definition at line 521 of file stm32l1xx_rtc.h.

#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000)

Tamper is activated after 4 consecutive samples at the active level

Definition at line 523 of file stm32l1xx_rtc.h.

#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800)

Tamper is activated after 8 consecutive samples at the active leve.

Definition at line 525 of file stm32l1xx_rtc.h.

#define RTC_TamperFilter_Disable ((uint32_t)0x00000000)

Tamper filter is disabled

Definition at line 519 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Tamper_Sampling_Frequencies_Definitions

Defines

RTC_Tamper_Sampling_Frequencies_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500)
#define | RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100)
#define | RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400)
#define | RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700)
#define | RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000)
#define | RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300)
#define | RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600)
#define | RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200)

Define Documentation

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))

Definition at line 554 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperSamplingFreqConfig().

#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 548 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 540 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 546 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 552 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 538 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 544 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 550 of file stm32l1xx_rtc.h.

#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 542 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Tamper_Pin_Precharge_Duration_Definitions

Defines

RTC_Tamper_Pin_Precharge_Duration_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)

Define Documentation

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))

Definition at line 579 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperPinsPrechargeDuration().

#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 570 of file stm32l1xx_rtc.h.

#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 572 of file stm32l1xx_rtc.h.

#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 574 of file stm32l1xx_rtc.h.

#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 576 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Tamper_Pins_Definitions

Defines

RTC_Tamper_Pins_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
#define | RTC_Tamper_1 RTC_TAFCR_TAMP1E
#define | RTC_Tamper_2 RTC_TAFCR_TAMP2E
#define | RTC_Tamper_3 RTC_TAFCR_TAMP3E

Define Documentation

#define IS_RTC_TAMPER ( TAMPER ) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))

Definition at line 597 of file stm32l1xx_rtc.h.

Referenced by RTC_TamperCmd(), and RTC_TamperTriggerConfig().

#define RTC_Tamper_1 RTC_TAFCR_TAMP1E

Tamper detection enable for input tamper 1

Definition at line 590 of file stm32l1xx_rtc.h.

#define RTC_Tamper_2 RTC_TAFCR_TAMP2E

Tamper detection enable for input tamper 2

Definition at line 592 of file stm32l1xx_rtc.h.

#define RTC_Tamper_3 RTC_TAFCR_TAMP3E

Tamper detection enable for input tamper 3

Definition at line 594 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Output_Type_ALARM_OUT

Defines

RTC_Output_Type_ALARM_OUT

RTC_Exported_Constants

Defines

#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
#define | RTC_OutputType_PushPull ((uint32_t)0x00040000)

Define Documentation

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OutputType_OpenDrain) || \
                                  ((TYPE) == RTC_OutputType_PushPull))

Definition at line 609 of file stm32l1xx_rtc.h.

Referenced by RTC_OutputTypeConfig().

#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)

Definition at line 607 of file stm32l1xx_rtc.h.

#define RTC_OutputType_PushPull ((uint32_t)0x00040000)

Definition at line 608 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Add_1_Second_Parameter_Definitions

Defines

RTC_Add_1_Second_Parameter_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
#define | RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)

Define Documentation

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_ShiftAdd1S_Reset) || \
                                 ((SEL) == RTC_ShiftAdd1S_Set))

Definition at line 621 of file stm32l1xx_rtc.h.

Referenced by RTC_SynchroShiftConfig().

#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)

Definition at line 619 of file stm32l1xx_rtc.h.

#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)

Definition at line 620 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Substract_Fraction_Of_Second_Value

Defines

RTC_Substract_Fraction_Of_Second_Value

RTC_Exported_Constants

Defines

#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)

Define Documentation

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= 0x00007FFF)

Definition at line 630 of file stm32l1xx_rtc.h.

Referenced by RTC_SynchroShiftConfig().


STM32L1xx Standard Peripherals Firmware Library: RTC_Backup_Registers_Definitions

Defines

RTC_Backup_Registers_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_BKP(BKP)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)

Define Documentation

#define IS_RTC_BKP ( BKP )

Definition at line 672 of file stm32l1xx_rtc.h.

Referenced by RTC_ReadBackupRegister(), and RTC_WriteBackupRegister().

#define RTC_BKP_DR0 ((uint32_t)0x00000000)

Definition at line 640 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001)

Definition at line 641 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000A)

Definition at line 650 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000B)

Definition at line 651 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000C)

Definition at line 652 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000D)

Definition at line 653 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000E)

Definition at line 654 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000F)

Definition at line 655 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010)

Definition at line 656 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011)

Definition at line 657 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012)

Definition at line 658 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013)

Definition at line 659 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002)

Definition at line 642 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR20 ((uint32_t)0x00000014)

Definition at line 660 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR21 ((uint32_t)0x00000015)

Definition at line 661 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR22 ((uint32_t)0x00000016)

Definition at line 662 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR23 ((uint32_t)0x00000017)

Definition at line 663 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR24 ((uint32_t)0x00000018)

Definition at line 664 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR25 ((uint32_t)0x00000019)

Definition at line 665 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR26 ((uint32_t)0x0000001A)

Definition at line 666 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR27 ((uint32_t)0x0000001B)

Definition at line 667 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR28 ((uint32_t)0x0000001C)

Definition at line 668 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR29 ((uint32_t)0x0000001D)

Definition at line 669 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003)

Definition at line 643 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR30 ((uint32_t)0x0000001E)

Definition at line 670 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR31 ((uint32_t)0x0000001F)

Definition at line 671 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004)

Definition at line 644 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005)

Definition at line 645 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006)

Definition at line 646 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007)

Definition at line 647 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008)

Definition at line 648 of file stm32l1xx_rtc.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009)

Definition at line 649 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Input_parameter_format_definitions

Defines

RTC_Input_parameter_format_definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
#define | RTC_Format_BCD ((uint32_t)0x000000001)
#define | RTC_Format_BIN ((uint32_t)0x000000000)

Define Documentation

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))

Definition at line 713 of file stm32l1xx_rtc.h.

Referenced by RTC_GetAlarm(), RTC_GetDate(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetDate(), and RTC_SetTime().

#define RTC_Format_BCD ((uint32_t)0x000000001)

Definition at line 712 of file stm32l1xx_rtc.h.

#define RTC_Format_BIN ((uint32_t)0x000000000)

Definition at line 711 of file stm32l1xx_rtc.h.

Referenced by RTC_GetAlarm(), RTC_GetDate(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetDate(), and RTC_SetTime().


STM32L1xx Standard Peripherals Firmware Library: RTC_Flags_Definitions

Defines

RTC_Flags_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
#define | IS_RTC_GET_FLAG(FLAG)
#define | RTC_FLAG_ALRAF ((uint32_t)0x00000100)
#define | RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
#define | RTC_FLAG_ALRBF ((uint32_t)0x00000200)
#define | RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
#define | RTC_FLAG_INITF ((uint32_t)0x00000040)
#define | RTC_FLAG_INITS ((uint32_t)0x00000010)
#define | RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define | RTC_FLAG_RSF ((uint32_t)0x00000020)
#define | RTC_FLAG_SHPF ((uint32_t)0x00000008)
#define | RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
#define | RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
#define | RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
#define | RTC_FLAG_TSF ((uint32_t)0x00000800)
#define | RTC_FLAG_TSOVF ((uint32_t)0x00001000)
#define | RTC_FLAG_WUTF ((uint32_t)0x00000400)
#define | RTC_FLAG_WUTWF ((uint32_t)0x00000004)

Define Documentation

#define IS_RTC_CLEAR_FLAG ( FLAG ) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))

Definition at line 746 of file stm32l1xx_rtc.h.

Referenced by RTC_ClearFlag().

#define IS_RTC_GET_FLAG ( FLAG )
Value:
(((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
                                ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
                                ((FLAG) == RTC_FLAG_SHPF))

Definition at line 738 of file stm32l1xx_rtc.h.

Referenced by RTC_GetFlagStatus().

#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)

Definition at line 730 of file stm32l1xx_rtc.h.

#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)

Definition at line 737 of file stm32l1xx_rtc.h.

#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)

Definition at line 729 of file stm32l1xx_rtc.h.

#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)

Definition at line 736 of file stm32l1xx_rtc.h.

#define RTC_FLAG_INITF ((uint32_t)0x00000040)

Definition at line 731 of file stm32l1xx_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)0x00000010)

Definition at line 733 of file stm32l1xx_rtc.h.

#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)

Definition at line 722 of file stm32l1xx_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)0x00000020)

Definition at line 732 of file stm32l1xx_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)0x00000008)

Definition at line 734 of file stm32l1xx_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)

Definition at line 725 of file stm32l1xx_rtc.h.

#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)

Definition at line 724 of file stm32l1xx_rtc.h.

#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)

Definition at line 723 of file stm32l1xx_rtc.h.

#define RTC_FLAG_TSF ((uint32_t)0x00000800)

Definition at line 727 of file stm32l1xx_rtc.h.

#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)

Definition at line 726 of file stm32l1xx_rtc.h.

#define RTC_FLAG_WUTF ((uint32_t)0x00000400)

Definition at line 728 of file stm32l1xx_rtc.h.

#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)

Definition at line 735 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Interrupts_Definitions

Defines

RTC_Interrupts_Definitions

RTC_Exported_Constants

Defines

#define | IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
#define | IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
#define | IS_RTC_GET_IT(IT)
#define | RTC_IT_ALRA ((uint32_t)0x00001000)
#define | RTC_IT_ALRB ((uint32_t)0x00002000)
#define | RTC_IT_TAMP ((uint32_t)0x00000004)
#define | RTC_IT_TAMP1 ((uint32_t)0x00020000)
#define | RTC_IT_TAMP2 ((uint32_t)0x00040000)
#define | RTC_IT_TAMP3 ((uint32_t)0x00080000)
#define | RTC_IT_TS ((uint32_t)0x00008000)
#define | RTC_IT_WUT ((uint32_t)0x00004000)

Define Documentation

#define IS_RTC_CLEAR_IT ( IT ) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))

Definition at line 770 of file stm32l1xx_rtc.h.

Referenced by RTC_ClearITPendingBit().

#define IS_RTC_CONFIG_IT ( IT ) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))

Definition at line 765 of file stm32l1xx_rtc.h.

Referenced by RTC_ITConfig().

#define IS_RTC_GET_IT ( IT )
Value:
(((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_WUT) || \
                           ((IT) == RTC_IT_ALRB)  || ((IT) == RTC_IT_ALRA) || \
                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
                           ((IT) == RTC_IT_TAMP3))

Definition at line 766 of file stm32l1xx_rtc.h.

Referenced by RTC_GetITStatus().

#define RTC_IT_ALRA ((uint32_t)0x00001000)

Definition at line 758 of file stm32l1xx_rtc.h.

#define RTC_IT_ALRB ((uint32_t)0x00002000)

Definition at line 757 of file stm32l1xx_rtc.h.

#define RTC_IT_TAMP ((uint32_t)0x00000004)

Definition at line 759 of file stm32l1xx_rtc.h.

#define RTC_IT_TAMP1 ((uint32_t)0x00020000)

Definition at line 760 of file stm32l1xx_rtc.h.

#define RTC_IT_TAMP2 ((uint32_t)0x00040000)

Definition at line 761 of file stm32l1xx_rtc.h.

#define RTC_IT_TAMP3 ((uint32_t)0x00080000)

Definition at line 762 of file stm32l1xx_rtc.h.

#define RTC_IT_TS ((uint32_t)0x00008000)

Definition at line 755 of file stm32l1xx_rtc.h.

#define RTC_IT_WUT ((uint32_t)0x00004000)

Definition at line 756 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: RTC_Legacy

Defines

RTC_Legacy

RTC_Exported_Constants

Defines

#define | RTC_DigitalCalibCmd RTC_CoarseCalibCmd
#define | RTC_DigitalCalibConfig RTC_CoarseCalibConfig

Define Documentation

#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd

Definition at line 780 of file stm32l1xx_rtc.h.

#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig

Definition at line 779 of file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

RTC_Private_Functions

Initialization and Configuration functions. More...

Functions

void | RTC_BypassShadowCmd (FunctionalState NewState)
Enables or Disables the Bypass Shadow feature.
ErrorStatus | RTC_DeInit (void)
Deinitializes the RTC registers to their default reset values.
ErrorStatus | RTC_EnterInitMode (void)
Enters the RTC Initialization mode.
void | RTC_ExitInitMode (void)
Exits the RTC Initialization mode.
ErrorStatus | RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
ErrorStatus | RTC_RefClockCmd (FunctionalState NewState)
Enables or disables the RTC reference clock detection.
void | RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
Fills each RTC_InitStruct member with its default value.
ErrorStatus | RTC_WaitForSynchro (void)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
void | RTC_WriteProtectionCmd (FunctionalState NewState)
Enables or disables the RTC registers write protection.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To Configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

void RTC_BypassShadowCmd ( FunctionalState NewState )

Enables or Disables the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
NewState,: new state of the Bypass Shadow feature. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 646 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_CR_BYPSHAD.

ErrorStatus RTC_DeInit ( void )

Deinitializes the RTC registers to their default reset values.

Note:
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are deinitialized
  • ERROR: RTC registers are not deinitialized

Definition at line 309 of file stm32l1xx_rtc.c.

References ERROR, INITMODE_TIMEOUT, RESET, RTC, RTC_EnterInitMode(), RTC_ISR_WUTWF, RTC_WaitForSynchro(), and SUCCESS.

ErrorStatus RTC_EnterInitMode ( void )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 488 of file stm32l1xx_rtc.c.

References ERROR, INITMODE_TIMEOUT, RESET, RTC, RTC_INIT_MASK, RTC_ISR_INITF, and SUCCESS.

Referenced by RTC_CoarseCalibCmd(), RTC_CoarseCalibConfig(), RTC_DeInit(), RTC_Init(), RTC_RefClockCmd(), RTC_SetDate(), and RTC_SetTime().

void RTC_ExitInitMode ( void )

Exits the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
Parameters:
None
Return values:
None

Definition at line 533 of file stm32l1xx_rtc.c.

References RTC, and RTC_ISR_INIT.

Referenced by RTC_CoarseCalibCmd(), RTC_CoarseCalibConfig(), RTC_Init(), RTC_RefClockCmd(), RTC_SetDate(), and RTC_SetTime().

ErrorStatus RTC_Init ( RTC_InitTypeDef * RTC_InitStruct )

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTC_InitStruct,: pointer to a RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 393 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_SYNCH_PREDIV, RTC, RTC_InitTypeDef::RTC_AsynchPrediv, RTC_CR_FMT, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_InitTypeDef::RTC_HourFormat, RTC_InitTypeDef::RTC_SynchPrediv, and SUCCESS.

ErrorStatus RTC_RefClockCmd ( FunctionalState NewState )

Enables or disables the RTC reference clock detection.

Parameters:
NewState,: new state of the RTC reference clock. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC reference clock detection is enabled
  • ERROR: RTC reference clock detection is disabled

Definition at line 598 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, IS_FUNCTIONAL_STATE, RTC, RTC_CR_REFCKON, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

void RTC_StructInit ( RTC_InitTypeDef * RTC_InitStruct )

Fills each RTC_InitStruct member with its default value.

Parameters:
RTC_InitStruct,: pointer to a RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 439 of file stm32l1xx_rtc.c.

References RTC_InitTypeDef::RTC_AsynchPrediv, RTC_InitTypeDef::RTC_HourFormat, RTC_HourFormat_24, and RTC_InitTypeDef::RTC_SynchPrediv.

ErrorStatus RTC_WaitForSynchro ( void )

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 555 of file stm32l1xx_rtc.c.

References ERROR, RESET, RTC, RTC_ISR_RSF, RTC_RSF_MASK, SUCCESS, and SYNCHRO_TIMEOUT.

Referenced by RTC_DeInit(), RTC_SetDate(), RTC_SetTime(), and RTC_SynchroShiftConfig().

void RTC_WriteProtectionCmd ( FunctionalState NewState )

Enables or disables the RTC registers write protection.

Note:
All the RTC registers are write protected except for RTC_ISR[13:8], RTC_TAFCR and RTC_BKPxR.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Parameters:
NewState,: new state of the write protection. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 461 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, and RTC.


STM32L1xx Standard Peripherals Firmware Library: Time and Date configuration functions

Functions

Time and Date configuration functions

RTC_Private_Functions

Time and Date configuration functions. More...

Functions

void | RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).
void | RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Get the RTC current date.
uint32_t | RTC_GetSubSecond (void)
Gets the RTC current Calendar Subseconds value.
void | RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Get the RTC current Time.
ErrorStatus | RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
ErrorStatus | RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).

Detailed Description

Time and Date configuration functions.

 ===============================================================================
               ##### Time and Date configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to program and read the RTC
         Calendar (Time and Date).

Function Documentation

void RTC_DateStructInit ( RTC_DateTypeDef * RTC_DateStruct )

Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).

Parameters:
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 972 of file stm32l1xx_rtc.c.

References RTC_DateTypeDef::RTC_Date, RTC_DateTypeDef::RTC_Month, RTC_Month_January, RTC_DateTypeDef::RTC_WeekDay, RTC_Weekday_Monday, and RTC_DateTypeDef::RTC_Year.

void RTC_GetDate | ( | uint32_t | RTC_Format,
 |  | RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Get the RTC current date.

Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that will contain the returned current date configuration.
Return values:
None

Definition at line 991 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_DateTypeDef::RTC_Date, RTC_DR_DT, RTC_DR_DU, RTC_DR_MT, RTC_DR_MU, RTC_DR_RESERVED_MASK, RTC_DR_WDU, RTC_DR_YT, RTC_DR_YU, RTC_Format_BIN, RTC_DateTypeDef::RTC_Month, RTC_DateTypeDef::RTC_WeekDay, and RTC_DateTypeDef::RTC_Year.

uint32_t RTC_GetSubSecond ( void )

Gets the RTC current Calendar Subseconds value.

Note:
This function freeze the Time and Date registers after reading the SSR register.
Parameters:
None
Return values:
RTC current Calendar Subseconds value.

Definition at line 856 of file stm32l1xx_rtc.c.

References RTC.

void RTC_GetTime | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Get the RTC current Time.

Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure that will contain the returned current time configuration.
Return values:
None

Definition at line 823 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_HT, RTC_TR_HU, RTC_TR_MNT, RTC_TR_MNU, RTC_TR_PM, RTC_TR_RESERVED_MASK, RTC_TR_ST, and RTC_TR_SU.

ErrorStatus RTC_SetDate | ( | uint32_t | RTC_Format,
 |  | RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTC_Format,: specifies the format of the entered parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Date register is configured
  • ERROR: RTC Date register is not configured

Definition at line 881 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RESET, RTC, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_BYPSHAD, RTC_DateTypeDef::RTC_Date, RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_Format_BIN, RTC_DateTypeDef::RTC_Month, RTC_WaitForSynchro(), RTC_DateTypeDef::RTC_WeekDay, RTC_DateTypeDef::RTC_Year, and SUCCESS.

ErrorStatus RTC_SetTime | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTC_Format,: specifies the format of the entered parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 700 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_FORMAT, IS_RTC_H12, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RESET, RTC, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_BYPSHAD, RTC_CR_FMT, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_RESERVED_MASK, RTC_WaitForSynchro(), and SUCCESS.

void RTC_TimeStructInit ( RTC_TimeTypeDef * RTC_TimeStruct )

Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 804 of file stm32l1xx_rtc.c.

References RTC_TimeTypeDef::RTC_H12, RTC_H12_AM, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.


STM32L1xx Standard Peripherals Firmware Library: Alarms configuration functions

Functions

Alarms configuration functions

RTC_Private_Functions

Alarms (Alarm A and Alarm B) configuration functions. More...

Functions

ErrorStatus | RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
Enables or disables the specified RTC Alarm.
void | RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).
void | RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
Configure the RTC AlarmA/B Subseconds value and mask.
void | RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Get the RTC Alarm value and masks.
uint32_t | RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
Gets the RTC Alarm Subseconds value.
void | RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the specified RTC Alarm.

Detailed Description

Alarms (Alarm A and Alarm B) configuration functions.

 ===============================================================================
         ##### Alarms (Alarm A and Alarm B) configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to program and read the RTC
         Alarms.

Function Documentation

ErrorStatus RTC_AlarmCmd | ( | uint32_t | RTC_Alarm,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC Alarm.

Parameters:
RTC_Alarm,: specifies the alarm to be configured. This parameter can be any combination of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
NewState,: new state of the specified alarm. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Alarm is enabled/disabled
  • ERROR: RTC Alarm is not enabled/disabled

Definition at line 1246 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, INITMODE_TIMEOUT, IS_FUNCTIONAL_STATE, IS_RTC_CMD_ALARM, RESET, RTC, and SUCCESS.

void RTC_AlarmStructInit ( RTC_AlarmTypeDef * RTC_AlarmStruct )

Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 1162 of file stm32l1xx_rtc.c.

References RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmDateWeekDaySel_Date, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmMask_None, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_TimeTypeDef::RTC_H12, RTC_H12_AM, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

void RTC_AlarmSubSecondConfig | ( | uint32_t | RTC_Alarm,
 |  | uint32_t | RTC_AlarmSubSecondValue,
 |  | uint32_t | RTC_AlarmSubSecondMask
 | ) |  |

Configure the RTC AlarmA/B Subseconds value and mask.

*

Note:
This function is performed only when the Alarm is disabled.
Parameters:
RTC_Alarm,: specifies the alarm to be configured. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmSubSecondValue,: specifies the Subseconds value. This parameter can be a value from 0 to 0x00007FFF.
RTC_AlarmSubSecondMask,: specifies the Subseconds Mask. This parameter can be any combination of the following values:

  • RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm.
  • RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared
  • RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared
  • RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared
  • RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared
  • RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared.
  • RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared.
  • RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm.
Return values:
None

Definition at line 1340 of file stm32l1xx_rtc.c.

References IS_RTC_ALARM, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, RTC, and RTC_Alarm_A.

void RTC_GetAlarm | ( | uint32_t | RTC_Format,
 |  | uint32_t | RTC_Alarm,
 |  | RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
RTC_Format,: specifies the format of the output parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_Alarm,: specifies the alarm to be read. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure that will contains the output alarm configuration values.
Return values:
None

Definition at line 1192 of file stm32l1xx_rtc.c.

References IS_RTC_ALARM, IS_RTC_FORMAT, RTC, RTC_Alarm_A, RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmMask_All, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_ALRMAR_DT, RTC_ALRMAR_DU, RTC_ALRMAR_HT, RTC_ALRMAR_HU, RTC_ALRMAR_MNT, RTC_ALRMAR_MNU, RTC_ALRMAR_PM, RTC_ALRMAR_ST, RTC_ALRMAR_SU, RTC_ALRMAR_WDSEL, RTC_Bcd2ToByte(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

uint32_t RTC_GetAlarmSubSecond ( uint32_t RTC_Alarm )

Gets the RTC Alarm Subseconds value.

Parameters:
RTC_Alarm,: specifies the alarm to be read. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
None
Return values:
RTC Alarm Subseconds value.

Definition at line 1381 of file stm32l1xx_rtc.c.

References RTC, RTC_Alarm_A, RTC_ALRMASSR_SS, and RTC_ALRMBSSR_SS.

void RTC_SetAlarm | ( | uint32_t | RTC_Format,
 |  | uint32_t | RTC_Alarm,
 |  | RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the specified RTC Alarm.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the RTC_AlarmCmd(DISABLE)).
Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_Alarm,: specifies the alarm to be configured. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
None

Definition at line 1051 of file stm32l1xx_rtc.c.

References IS_ALARM_MASK, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_FORMAT, IS_RTC_H12, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RESET, RTC, RTC_Alarm_A, RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmDateWeekDaySel_Date, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_FMT, RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.


STM32L1xx Standard Peripherals Firmware Library: WakeUp Timer configuration functions

Functions

WakeUp Timer configuration functions

RTC_Private_Functions

WakeUp Timer configuration functions. More...

Functions

uint32_t | RTC_GetWakeUpCounter (void)
Returns the RTC WakeUp timer counter value.
void | RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
Configures the RTC Wakeup counter.
void | RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
Configures the RTC Wakeup clock source.
ErrorStatus | RTC_WakeUpCmd (FunctionalState NewState)
Enables or Disables the RTC WakeUp timer.

Detailed Description

WakeUp Timer configuration functions.

 ===============================================================================
               ##### WakeUp Timer configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to program and read the RTC WakeUp.

Function Documentation

uint32_t RTC_GetWakeUpCounter ( void )

Returns the RTC WakeUp timer counter value.

Parameters:
None
Return values:
The RTC WakeUp Counter value.

Definition at line 1477 of file stm32l1xx_rtc.c.

References RTC, and RTC_WUTR_WUT.

void RTC_SetWakeUpCounter ( uint32_t RTC_WakeUpCounter )

Configures the RTC Wakeup counter.

Note:
The RTC WakeUp counter can only be written when the RTC WakeUp. is disabled (Use the RTC_WakeUpCmd(DISABLE)).
Parameters:
RTC_WakeUpCounter,: specifies the WakeUp counter. This parameter can be a value from 0x0000 to 0xFFFF.
Return values:
None

Definition at line 1456 of file stm32l1xx_rtc.c.

References IS_RTC_WAKEUP_COUNTER, and RTC.

void RTC_WakeUpClockConfig ( uint32_t RTC_WakeUpClock )

Configures the RTC Wakeup clock source.

Note:
The WakeUp Clock source can only be changed when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
Parameters:
RTC_WakeUpClock,: Wakeup Clock source. This parameter can be one of the following values:

  • RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16.
  • RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8.
  • RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4.
  • RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2.
  • RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE.
  • RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE.
Return values:
None

Definition at line 1429 of file stm32l1xx_rtc.c.

References IS_RTC_WAKEUP_CLOCK, RTC, and RTC_CR_WUCKSEL.

ErrorStatus RTC_WakeUpCmd ( FunctionalState NewState )

Enables or Disables the RTC WakeUp timer.

Parameters:
NewState,: new state of the WakeUp timer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1489 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, INITMODE_TIMEOUT, IS_FUNCTIONAL_STATE, RESET, RTC, RTC_CR_WUTE, RTC_ISR_WUTWF, and SUCCESS.


STM32L1xx Standard Peripherals Firmware Library: Daylight Saving configuration functions

Functions

Daylight Saving configuration functions

RTC_Private_Functions

Daylight Saving configuration functions. More...

Functions

void | RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
Adds or substract one hour from the current time.
uint32_t | RTC_GetStoreOperation (void)
Returns the RTC Day Light Saving stored operation.

Detailed Description

Daylight Saving configuration functions.

 ===============================================================================
              ##### Daylight Saving configuration functions #####
 ===============================================================================
    [..] This section provide functions allowing to configure the RTC DayLight Saving.

Function Documentation

void RTC_DayLightSavingConfig | ( | uint32_t | RTC_DayLightSaving,
 |  | uint32_t | RTC_StoreOperation
 | ) |  |

Adds or substract one hour from the current time.

Parameters:
RTC_DayLightSaveOperation,: the value of hour adjustment. This parameter can be one of the following values:

  • RTC_DayLightSaving_SUB1H: Substract one hour (winter time).
  • RTC_DayLightSaving_ADD1H: Add one hour (summer time).
RTC_StoreOperation,: Specifies the value to be written in the BCK bit in CR register to store the operation. This parameter can be one of the following values:

  • RTC_StoreOperation_Reset: BCK Bit Reset.
  • RTC_StoreOperation_Set: BCK Bit Set.
Return values:
None

Definition at line 1565 of file stm32l1xx_rtc.c.

References IS_RTC_DAYLIGHT_SAVING, IS_RTC_STORE_OPERATION, RTC, and RTC_CR_BCK.

uint32_t RTC_GetStoreOperation ( void )

Returns the RTC Day Light Saving stored operation.

Parameters:
None
Return values:
RTC Day Light Saving stored operation.

  • RTC_StoreOperation_Reset
  • RTC_StoreOperation_Set

Definition at line 1592 of file stm32l1xx_rtc.c.

References RTC, and RTC_CR_BCK.


STM32L1xx Standard Peripherals Firmware Library: Output pin Configuration function

Functions

Output pin Configuration function

RTC_Private_Functions

Output pin Configuration function. More...

Functions

void RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
Configures the RTC output source (AFO_ALARM).

Detailed Description

Output pin Configuration function.

 ===============================================================================
                  ##### Output pin Configuration function #####
 ===============================================================================
    [..] This section provide functions allowing to configure the RTC Output source.

Function Documentation

void RTC_OutputConfig | ( | uint32_t | RTC_Output,
 |  | uint32_t | RTC_OutputPolarity
 | ) |  |

Configures the RTC output source (AFO_ALARM).

Parameters:
RTC_Output,: Specifies which signal will be routed to the RTC output. This parameter can be one of the following values:

  • RTC_Output_Disable: No output selected
  • RTC_Output_AlarmA: signal of AlarmA mapped to output.
  • RTC_Output_AlarmB: signal of AlarmB mapped to output.
  • RTC_Output_WakeUp: signal of WakeUp mapped to output.
RTC_OutputPolarity,: Specifies the polarity of the output signal. This parameter can be one of the following:

  • RTC_OutputPolarity_High: The output pin is high when the ALRAF/ALRBF/WUTF is high (depending on OSEL).
  • RTC_OutputPolarity_Low: The output pin is low when the ALRAF/ALRBF/WUTF is high (depending on OSEL).
Return values:
None

Definition at line 1630 of file stm32l1xx_rtc.c.

References IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, RTC, RTC_CR_OSEL, and RTC_CR_POL.


STM32L1xx Standard Peripherals Firmware Library: Coarse and Smooth Calibrations configuration functions

Functions

Coarse and Smooth Calibrations configuration functions

RTC_Private_Functions

Coarse and Smooth Calibrations configuration functions. More...

Functions

void | RTC_CalibOutputCmd (FunctionalState NewState)
Enables or disables the RTC clock to be output through the relative pin.
void | RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
ErrorStatus | RTC_CoarseCalibCmd (FunctionalState NewState)
Enables or disables the Coarse calibration process.
ErrorStatus | RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
Configures the Coarse Calibration parameters.
ErrorStatus | RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
Configures the Smooth Calibration Settings.

Detailed Description

Coarse and Smooth Calibrations configuration functions.

 ===============================================================================
        ##### Coarse and Smooth Calibrations configuration functions #####
 ===============================================================================

Function Documentation

void RTC_CalibOutputCmd ( FunctionalState NewState )

Enables or disables the RTC clock to be output through the relative pin.

Parameters:
NewState,: new state of the coarse calibration Output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1769 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_CR_COE.

void RTC_CalibOutputConfig ( uint32_t RTC_CalibOutput )

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
RTC_CalibOutput : Select the Calibration output Selection . This parameter can be one of the following values:

  • RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
  • RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
Return values:
None

Definition at line 1801 of file stm32l1xx_rtc.c.

References IS_RTC_CALIB_OUTPUT, RTC, and RTC_CR_COSEL.

ErrorStatus RTC_CoarseCalibCmd ( FunctionalState NewState )

Enables or disables the Coarse calibration process.

Parameters:
NewState,: new state of the Coarse calibration. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Coarse calibration are enabled/disabled
  • ERROR: RTC Coarse calibration are not enabled/disabled

Definition at line 1722 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, IS_FUNCTIONAL_STATE, RTC, RTC_CR_DCE, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

ErrorStatus RTC_CoarseCalibConfig | ( | uint32_t | RTC_CalibSign,
 |  | uint32_t | Value
 | ) |  |

Configures the Coarse Calibration parameters.

Parameters:
RTC_CalibSign,: specifies the sign of the calibration value. This parameter can be one of the following values:

  • RTC_CalibSign_Positive: The value sign is positive.
  • RTC_CalibSign_Negative: The value sign is negative.
Value,: value of calibration expressed in ppm (coded on 5 bits) This value should be between 0 and 63 when using negative sign with a 2-ppm step. This value should be between 0 and 126 when using positive sign with a 4-ppm step.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Coarse calibration are initialized
  • ERROR: RTC Coarse calibration are not initialized

Definition at line 1681 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_CALIB_SIGN, IS_RTC_CALIB_VALUE, RTC, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

ErrorStatus RTC_SmoothCalibConfig | ( | uint32_t | RTC_SmoothCalibPeriod,
 |  | uint32_t | RTC_SmoothCalibPlusPulses,
 |  | uint32_t | RTC_SmouthCalibMinusPulsesValue
 | ) |  |

Configures the Smooth Calibration Settings.

Parameters:
RTC_SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values:

  • RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
  • RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
  • RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
RTC_SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:

  • RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
  • RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
RTC_SmouthCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Calib registers are configured
  • ERROR: RTC Calib registers are not configured

Definition at line 1837 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RECALPF_TIMEOUT, RESET, RTC, RTC_ISR_RECALPF, and SUCCESS.


STM32L1xx Standard Peripherals Firmware Library: TimeStamp configuration functions

Functions

TimeStamp configuration functions

RTC_Private_Functions

TimeStamp configuration functions. More...

Functions

void | RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
Get the RTC TimeStamp value and masks.
uint32_t | RTC_GetTimeStampSubSecond (void)
Get the RTC timestamp Subseconds value.
void | RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.

Detailed Description

TimeStamp configuration functions.

 ===============================================================================
                 ##### TimeStamp configuration functions #####
 ===============================================================================

Function Documentation

void RTC_GetTimeStamp | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_StampTimeStruct,
 |  | RTC_DateTypeDef * | RTC_StampDateStruct
 | ) |  |

Get the RTC TimeStamp value and masks.

Parameters:
RTC_Format,: specifies the format of the output parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format
  • RTC_Format_BCD: BCD data format
RTC_StampTimeStruct,: pointer to a RTC_TimeTypeDef structure that will contains the TimeStamp time values.
RTC_StampDateStruct,: pointer to a RTC_DateTypeDef structure that will contains the TimeStamp date values.
Return values:
None

Definition at line 1957 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_DateTypeDef::RTC_Date, RTC_DR_DT, RTC_DR_DU, RTC_DR_MT, RTC_DR_MU, RTC_DR_RESERVED_MASK, RTC_DR_WDU, RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_DateTypeDef::RTC_Month, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_HT, RTC_TR_HU, RTC_TR_MNT, RTC_TR_MNU, RTC_TR_PM, RTC_TR_RESERVED_MASK, RTC_TR_ST, RTC_TR_SU, RTC_DateTypeDef::RTC_WeekDay, and RTC_DateTypeDef::RTC_Year.

uint32_t RTC_GetTimeStampSubSecond ( void )

Get the RTC timestamp Subseconds value.

Parameters:
None
Return values:
RTC current timestamp Subseconds value.

Definition at line 2001 of file stm32l1xx_rtc.c.

References RTC.

void RTC_TimeStampCmd | ( | uint32_t | RTC_TimeStampEdge,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.

Parameters:
RTC_TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following:

  • RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TimeStampEdge_Falling: the Time stamp event occurs on the falling edge of the related pin.
NewState,: new state of the TimeStamp. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1913 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_TIMESTAMP_EDGE, RTC, RTC_CR_TSE, and RTC_CR_TSEDGE.


STM32L1xx Standard Peripherals Firmware Library: Tampers configuration functions

Functions

Tampers configuration functions

RTC_Private_Functions

Tampers configuration functions. More...

Functions

void | RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
Enables or Disables the Tamper detection.
void | RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
Configures the Tampers Filter.
void | RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
Configures the Tampers Pins input Precharge Duration.
void | RTC_TamperPullUpCmd (FunctionalState NewState)
Enables or Disables the Precharge of Tamper pin.
void | RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
Configures the Tampers Sampling Frequency.
void | RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
Configures the select Tamper pin edge.
void | RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
Enables or Disables the TimeStamp on Tamper Detection Event.

Detailed Description

Tampers configuration functions.

 ===============================================================================
                 ##### Tampers configuration functions #####
 ===============================================================================

Function Documentation

void RTC_TamperCmd | ( | uint32_t | RTC_Tamper,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the Tamper detection.

Parameters:
RTC_Tamper,: Selected tamper pin. This parameter can be any combination of the following values:

  • RTC_Tamper_1: Select Tamper 1.
  • RTC_Tamper_2: Select Tamper 2.
  • RTC_Tamper_3: Select Tamper 3.
NewState,: new state of the tamper pin. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2069 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_TAMPER, and RTC.

void RTC_TamperFilterConfig ( uint32_t RTC_TamperFilter )

Configures the Tampers Filter.

Parameters:
RTC_TamperFilter,: Specifies the tampers filter. This parameter can be one of the following values:

  • RTC_TamperFilter_Disable: Tamper filter is disabled.
  • RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive samples at the active level.
  • RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive samples at the active level.
  • RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive samples at the active level.
Return values:
None

Definition at line 2100 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_FILTER, RTC, and RTC_TAFCR_TAMPFLT.

void RTC_TamperPinsPrechargeDuration ( uint32_t RTC_TamperPrechargeDuration )

Configures the Tampers Pins input Precharge Duration.

Parameters:
RTC_TamperPrechargeDuration,: Specifies the Tampers Pins input Precharge Duration. This parameter can be one of the following values:

  • RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
Return values:
None

Definition at line 2157 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_PRECHARGE_DURATION, RTC, and RTC_TAFCR_TAMPPRCH.

void RTC_TamperPullUpCmd ( FunctionalState NewState )

Enables or Disables the Precharge of Tamper pin.

Parameters:
NewState,: new state of tamper pull up. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2200 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_TAFCR_TAMPPUDIS.

void RTC_TamperSamplingFreqConfig ( uint32_t RTC_TamperSamplingFreq )

Configures the Tampers Sampling Frequency.

Parameters:
RTC_TamperSamplingFreq,: Specifies the tampers Sampling Frequency. This parameter can be one of the following values:

  • RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768
  • RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384
  • RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192
  • RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096
  • RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048
  • RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024
  • RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled with a frequency = RTCCLK / 512
  • RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled with a frequency = RTCCLK / 256
Return values:
None

Definition at line 2134 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_SAMPLING_FREQ, RTC, and RTC_TAFCR_TAMPFREQ.

void RTC_TamperTriggerConfig | ( | uint32_t | RTC_Tamper,
 |  | uint32_t | RTC_TamperTrigger
 | ) |  |

Configures the select Tamper pin edge.

Parameters:
RTC_Tamper,: Selected tamper pin. This parameter can be any combination of the following values:

  • RTC_Tamper_1: Select Tamper 1.
  • RTC_Tamper_2: Select Tamper 2.
  • RTC_Tamper_3: Select Tamper 3.
RTC_TamperTrigger,: Specifies the trigger on the tamper pin that stimulates tamper event. This parameter can be one of the following values:

  • RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
  • RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
  • RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
  • RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
Return values:
None

Definition at line 2039 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER, IS_RTC_TAMPER_TRIGGER, RTC, and RTC_TamperTrigger_RisingEdge.

void RTC_TimeStampOnTamperDetectionCmd ( FunctionalState NewState )

Enables or Disables the TimeStamp on Tamper Detection Event.

Note:
The timestamp is valid even the TSE bit in tamper control register is reset.
Parameters:
NewState,: new state of the timestamp on tamper event. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2177 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_TAFCR_TAMPTS.


STM32L1xx Standard Peripherals Firmware Library: Backup Data Registers configuration functions

Functions

Backup Data Registers configuration functions

RTC_Private_Functions

Backup Data Registers configuration functions. More...

Functions

uint32_t | RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
Reads data from the specified RTC Backup data Register.
void | RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
Writes a data in a specified RTC Backup data register.

Detailed Description

Backup Data Registers configuration functions.

 ===============================================================================
          ##### Backup Data Registers configuration functions #####
 ===============================================================================

Function Documentation

uint32_t RTC_ReadBackupRegister ( uint32_t RTC_BKP_DR )

Reads data from the specified RTC Backup data Register.

Parameters:
RTC_BKP_DR,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
None

Definition at line 2262 of file stm32l1xx_rtc.c.

References IS_RTC_BKP, and RTC_BASE.

void RTC_WriteBackupRegister | ( | uint32_t | RTC_BKP_DR,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
RTC_BKP_DR,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 2241 of file stm32l1xx_rtc.c.

References IS_RTC_BKP, and RTC_BASE.


STM32L1xx Standard Peripherals Firmware Library: Output Type Config configuration functions

Functions

Output Type Config configuration functions

RTC_Private_Functions

Output Type Config configuration functions. More...

Functions

void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
Configures the RTC Output Pin mode.

Detailed Description

Output Type Config configuration functions.

 ===============================================================================
             ##### Output Type Config configuration functions #####
 ===============================================================================

Function Documentation

void RTC_OutputTypeConfig ( uint32_t RTC_OutputType )

Configures the RTC Output Pin mode.

Parameters:
RTC_OutputType,: specifies the RTC Output (PC13) pin mode. This parameter can be one of the following values:

  • RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in Open Drain mode.
  • RTC_OutputType_PushPull: RTC Output (PC13) is configured in Push Pull mode.
Return values:
None

Definition at line 2302 of file stm32l1xx_rtc.c.

References IS_RTC_OUTPUT_TYPE, RTC, and RTC_TAFCR_ALARMOUTTYPE.


STM32L1xx Standard Peripherals Firmware Library: Shift control synchronisation functions

Functions

Shift control synchronisation functions

RTC_Private_Functions

Shift control synchronisation functions. More...

Functions

ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
Configures the Synchronization Shift Control Settings.

Detailed Description

Shift control synchronisation functions.

 ===============================================================================
            ##### Shift control synchronisation functions #####
 ===============================================================================

Function Documentation

ErrorStatus RTC_SynchroShiftConfig | ( | uint32_t | RTC_ShiftAdd1S,
 |  | uint32_t | RTC_ShiftSubFS
 | ) |  |

Configures the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register
Parameters:
RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. This parameter can be one of the following values :

  • RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
  • RTC_ShiftAdd1S_Reset: No effect.
RTC_ShiftSubFS,: Select the number of Second Fractions to Substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Shift registers are configured
  • ERROR: RTC Shift registers are not configured

Definition at line 2340 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RESET, RTC, RTC_CR_REFCKON, RTC_ISR_SHPF, RTC_WaitForSynchro(), SHPF_TIMEOUT, and SUCCESS.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

RTC_Private_Functions

Interrupts and flags management functions. More...

Functions

void | RTC_ClearFlag (uint32_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint32_t RTC_IT)
Clears the RTC's interrupt pending bits.
FlagStatus | RTC_GetFlagStatus (uint32_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint32_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
            ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] All RTC interrupts are connected to the EXTI controller.
         (+) To enable the RTC Alarm interrupt, the following sequence is required:
         (+) Configure and enable the EXTI Line 17 in interrupt mode and select
             the rising edge sensitivity using the EXTI_Init() function.
         (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
             the NVIC_Init() function.
         (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
             using the RTC_SetAlarm() and RTC_AlarmCmd() functions.

         (+) To enable the RTC Wakeup interrupt, the following sequence is required:
         (+) Configure and enable the EXTI Line 20 in interrupt mode and select
             the rising edge sensitivity using the EXTI_Init() function.
         (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
             NVIC_Init() function.
         (+) Configure the RTC to generate the RTC wakeup timer event using the
             RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
             functions.

         (+) To enable the RTC Tamper interrupt, the following sequence is required:
         (+) Configure and enable the EXTI Line 19 in interrupt mode and select
             the rising edge sensitivity using the EXTI_Init() function.
         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
             the NVIC_Init() function.
         (+) Configure the RTC to detect the RTC tamper event using the
             RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.

         (+) To enable the RTC TimeStamp interrupt, the following sequence is
             required:
         (+) Configure and enable the EXTI Line 19 in interrupt mode and select
             the rising edge sensitivity using the EXTI_Init() function.
         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
             the NVIC_Init() function.
         (+) Configure the RTC to detect the RTC time-stamp event using the
             RTC_TimeStampCmd() functions.

Function Documentation

void RTC_ClearFlag ( uint32_t RTC_FLAG )

Clears the RTC's pending flags.

Parameters:
RTC_FLAG,: specifies the RTC flag to clear. This parameter can be any combination of the following values:

  • RTC_FLAG_TAMP3F: Tamper 3 event flag.
  • RTC_FLAG_TAMP2F: Tamper 2 event flag.
  • RTC_FLAG_TAMP1F: Tamper 1 event flag.
  • RTC_FLAG_TSOVF: Time Stamp Overflow flag.
  • RTC_FLAG_TSF: Time Stamp event flag.
  • RTC_FLAG_WUTF: WakeUp Timer flag.
  • RTC_FLAG_ALRBF: Alarm B flag.
  • RTC_FLAG_ALRAF: Alarm A flag.
  • RTC_FLAG_RSF: Registers Synchronized flag.
Return values:
None

Definition at line 2548 of file stm32l1xx_rtc.c.

References IS_RTC_CLEAR_FLAG, RTC, and RTC_ISR_INIT.

void RTC_ClearITPendingBit ( uint32_t RTC_IT )

Clears the RTC's interrupt pending bits.

Parameters:
RTC_IT,: specifies the RTC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RTC_IT_TS: Time Stamp interrupt
  • RTC_IT_WUT: WakeUp Timer interrupt
  • RTC_IT_ALRB: Alarm B interrupt
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_TAMP1: Tamper1 event interrupt
  • RTC_IT_TAMP2: Tamper2 event interrupt
  • RTC_IT_TAMP3: Tamper3 event interrupt
Return values:
None

Definition at line 2612 of file stm32l1xx_rtc.c.

References IS_RTC_CLEAR_IT, RTC, and RTC_ISR_INIT.

FlagStatus RTC_GetFlagStatus ( uint32_t RTC_FLAG )

Checks whether the specified RTC flag is set or not.

Parameters:
RTC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • RTC_FLAG_RECALPF: RECALPF event flag.
  • RTC_FLAG_TAMP3F: Tamper 3 event flag.
  • RTC_FLAG_TAMP2F: Tamper 2 event flag.
  • RTC_FLAG_TAMP1F: Tamper 1 event flag.
  • RTC_FLAG_TSOVF: Time Stamp OverFlow flag.
  • RTC_FLAG_TSF: Time Stamp event flag.
  • RTC_FLAG_WUTF: WakeUp Timer flag.
  • RTC_FLAG_ALRBF: Alarm B flag.
  • RTC_FLAG_ALRAF: Alarm A flag.
  • RTC_FLAG_INITF: Initialization mode flag.
  • RTC_FLAG_RSF: Registers Synchronized flag.
  • RTC_FLAG_INITS: Registers Configured flag. : Shift operation pending flag.
  • RTC_FLAG_WUTWF: WakeUp Timer Write flag.
  • RTC_FLAG_ALRBWF: Alarm B Write flag.
  • RTC_FLAG_ALRAWF: Alarm A write flag.
Return values:
The new state of RTC_FLAG (SET or RESET).

Definition at line 2510 of file stm32l1xx_rtc.c.

References IS_RTC_GET_FLAG, RESET, RTC, RTC_FLAGS_MASK, and SET.

ITStatus RTC_GetITStatus ( uint32_t RTC_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
RTC_IT,: specifies the RTC interrupt source to check. This parameter can be one of the following values:

  • RTC_IT_TS: Time Stamp interrupt.
  • RTC_IT_WUT: WakeUp Timer interrupt.
  • RTC_IT_ALRB: Alarm B interrupt.
  • RTC_IT_ALRA: Alarm A interrupt.
  • RTC_IT_TAMP1: Tamper1 event interrupt.
  • RTC_IT_TAMP2: Tamper2 event interrupt.
  • RTC_IT_TAMP3: Tamper3 event interrupt.
Return values:
The new state of RTC_IT (SET or RESET).

Definition at line 2570 of file stm32l1xx_rtc.c.

References IS_RTC_GET_IT, RESET, RTC, RTC_TAFCR_TAMPIE, and SET.

void RTC_ITConfig | ( | uint32_t | RTC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC interrupts.

Parameters:
RTC_IT,: specifies the RTC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RTC_IT_TS: Time Stamp interrupt mask.
  • RTC_IT_WUT: WakeUp Timer interrupt mask.
  • RTC_IT_ALRB: Alarm B interrupt mask.
  • RTC_IT_ALRA: Alarm A interrupt mask.
  • RTC_IT_TAMP: Tamper event interrupt mask.
NewState,: new state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2460 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_CONFIG_IT, RTC, and RTC_TAFCR_TAMPIE.


STM32L1xx Standard Peripherals Firmware Library: RTC_Private_Functions

Modules | Functions

RTC_Private_Functions

RTC

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Time and Date configuration functions

Time and Date configuration functions.

Alarms configuration functions

Alarms (Alarm A and Alarm B) configuration functions.

WakeUp Timer configuration functions

WakeUp Timer configuration functions.

Daylight Saving configuration functions

Daylight Saving configuration functions.

Output pin Configuration function

Output pin Configuration function.

Coarse and Smooth Calibrations configuration functions

Coarse and Smooth Calibrations configuration functions.

TimeStamp configuration functions

TimeStamp configuration functions.

Tampers configuration functions

Tampers configuration functions.

Backup Data Registers configuration functions

Backup Data Registers configuration functions.

Output Type Config configuration functions

Output Type Config configuration functions.

Shift control synchronisation functions

Shift control synchronisation functions.

Interrupts and flags management functions

Interrupts and flags management functions.

Functions

static uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
static uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.

Function Documentation

static uint8_t RTC_Bcd2ToByte ( uint8_t Value ) [static]

Convert from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted.
Return values:
Converted word

Definition at line 2653 of file stm32l1xx_rtc.c.

Referenced by RTC_GetAlarm(), RTC_GetDate(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetDate(), and RTC_SetTime().

static uint8_t RTC_ByteToBcd2 ( uint8_t Value ) [static]

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted.
Return values:
Converted byte

Definition at line 2635 of file stm32l1xx_rtc.c.

Referenced by RTC_SetAlarm(), RTC_SetDate(), and RTC_SetTime().


STM32L1xx Standard Peripherals Firmware Library: RTC

Data Structures | Modules | Defines | Functions

RTC

STM32L1xx_StdPeriph_Driver

RTC driver modules. More...

Data Structures

struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_InitTypeDef
RTC Init structures definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...

Modules

RTC_Exported_Constants
RTC_Private_Functions

Defines

#define | INITMODE_TIMEOUT ((uint32_t) 0x00002000)
#define | RECALPF_TIMEOUT ((uint32_t) 0x00001000)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_FLAGS_MASK
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | SHPF_TIMEOUT ((uint32_t) 0x00002000)
#define | SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)

Functions

ErrorStatus | RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
Enables or disables the specified RTC Alarm.
void | RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).
void | RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
Configure the RTC AlarmA/B Subseconds value and mask.
void | RTC_BypassShadowCmd (FunctionalState NewState)
Enables or Disables the Bypass Shadow feature.
void | RTC_CalibOutputCmd (FunctionalState NewState)
Enables or disables the RTC clock to be output through the relative pin.
void | RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
void | RTC_ClearFlag (uint32_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint32_t RTC_IT)
Clears the RTC's interrupt pending bits.
ErrorStatus | RTC_CoarseCalibCmd (FunctionalState NewState)
Enables or disables the Coarse calibration process.
ErrorStatus | RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
Configures the Coarse Calibration parameters.
void | RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).
void | RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
Adds or substract one hour from the current time.
ErrorStatus | RTC_DeInit (void)
Deinitializes the RTC registers to their default reset values.
ErrorStatus | RTC_EnterInitMode (void)
Enters the RTC Initialization mode.
void | RTC_ExitInitMode (void)
Exits the RTC Initialization mode.
void | RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Get the RTC Alarm value and masks.
uint32_t | RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
Gets the RTC Alarm Subseconds value.
void | RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Get the RTC current date.
FlagStatus | RTC_GetFlagStatus (uint32_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint32_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
uint32_t | RTC_GetStoreOperation (void)
Returns the RTC Day Light Saving stored operation.
uint32_t | RTC_GetSubSecond (void)
Gets the RTC current Calendar Subseconds value.
void | RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Get the RTC current Time.
void | RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
Get the RTC TimeStamp value and masks.
uint32_t | RTC_GetTimeStampSubSecond (void)
Get the RTC timestamp Subseconds value.
uint32_t | RTC_GetWakeUpCounter (void)
Returns the RTC WakeUp timer counter value.
ErrorStatus | RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
Configures the RTC output source (AFO_ALARM).
void | RTC_OutputTypeConfig (uint32_t RTC_OutputType)
Configures the RTC Output Pin mode.
uint32_t | RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
Reads data from the specified RTC Backup data Register.
ErrorStatus | RTC_RefClockCmd (FunctionalState NewState)
Enables or disables the RTC reference clock detection.
void | RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the specified RTC Alarm.
ErrorStatus | RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
ErrorStatus | RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
Configures the RTC Wakeup counter.
ErrorStatus | RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
Configures the Smooth Calibration Settings.
void | RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
Fills each RTC_InitStruct member with its default value.
ErrorStatus | RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
Configures the Synchronization Shift Control Settings.
void | RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
Enables or Disables the Tamper detection.
void | RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
Configures the Tampers Filter.
void | RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
Configures the Tampers Pins input Precharge Duration.
void | RTC_TamperPullUpCmd (FunctionalState NewState)
Enables or Disables the Precharge of Tamper pin.
void | RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
Configures the Tampers Sampling Frequency.
void | RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
Configures the select Tamper pin edge.
void | RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.
void | RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
Enables or Disables the TimeStamp on Tamper Detection Event.
void | RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).
ErrorStatus | RTC_WaitForSynchro (void)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
void | RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
Configures the RTC Wakeup clock source.
ErrorStatus | RTC_WakeUpCmd (FunctionalState NewState)
Enables or Disables the RTC WakeUp timer.
void | RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
Writes a data in a specified RTC Backup data register.
void | RTC_WriteProtectionCmd (FunctionalState NewState)
Enables or disables the RTC registers write protection.

Detailed Description

RTC driver modules.

Define Documentation

#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)

Definition at line 249 of file stm32l1xx_rtc.c.

Referenced by RTC_AlarmCmd(), RTC_DeInit(), RTC_EnterInitMode(), and RTC_WakeUpCmd().

#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)

Definition at line 251 of file stm32l1xx_rtc.c.

Referenced by RTC_SmoothCalibConfig().

#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)

Definition at line 239 of file stm32l1xx_rtc.c.

Referenced by RTC_GetDate(), RTC_GetTimeStamp(), and RTC_SetDate().

#define RTC_FLAGS_MASK
Value:
((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
                                            RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
                                            RTC_FLAG_SHPF))

Definition at line 242 of file stm32l1xx_rtc.c.

Referenced by RTC_GetFlagStatus().

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)

Definition at line 240 of file stm32l1xx_rtc.c.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)

Definition at line 241 of file stm32l1xx_rtc.c.

Referenced by RTC_WaitForSynchro().

#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)

Definition at line 238 of file stm32l1xx_rtc.c.

Referenced by RTC_GetTime(), RTC_GetTimeStamp(), and RTC_SetTime().

#define SHPF_TIMEOUT ((uint32_t) 0x00002000)

Definition at line 252 of file stm32l1xx_rtc.c.

Referenced by RTC_SynchroShiftConfig().

#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)

Definition at line 250 of file stm32l1xx_rtc.c.

Referenced by RTC_WaitForSynchro().

Function Documentation

ErrorStatus RTC_AlarmCmd | ( | uint32_t | RTC_Alarm,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC Alarm.

Parameters:
RTC_Alarm,: specifies the alarm to be configured. This parameter can be any combination of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
NewState,: new state of the specified alarm. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Alarm is enabled/disabled
  • ERROR: RTC Alarm is not enabled/disabled

Definition at line 1246 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, INITMODE_TIMEOUT, IS_FUNCTIONAL_STATE, IS_RTC_CMD_ALARM, RESET, RTC, and SUCCESS.

void RTC_AlarmStructInit ( RTC_AlarmTypeDef * RTC_AlarmStruct )

Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 1162 of file stm32l1xx_rtc.c.

References RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmDateWeekDaySel_Date, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmMask_None, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_TimeTypeDef::RTC_H12, RTC_H12_AM, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

void RTC_AlarmSubSecondConfig | ( | uint32_t | RTC_Alarm,
 |  | uint32_t | RTC_AlarmSubSecondValue,
 |  | uint32_t | RTC_AlarmSubSecondMask
 | ) |  |

Configure the RTC AlarmA/B Subseconds value and mask.

*

Note:
This function is performed only when the Alarm is disabled.
Parameters:
RTC_Alarm,: specifies the alarm to be configured. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmSubSecondValue,: specifies the Subseconds value. This parameter can be a value from 0 to 0x00007FFF.
RTC_AlarmSubSecondMask,: specifies the Subseconds Mask. This parameter can be any combination of the following values:

  • RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm.
  • RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared
  • RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared
  • RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared
  • RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared
  • RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared.
  • RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared.
  • RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared.
  • RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm.
Return values:
None

Definition at line 1340 of file stm32l1xx_rtc.c.

References IS_RTC_ALARM, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, RTC, and RTC_Alarm_A.

void RTC_BypassShadowCmd ( FunctionalState NewState )

Enables or Disables the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
NewState,: new state of the Bypass Shadow feature. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 646 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_CR_BYPSHAD.

void RTC_CalibOutputCmd ( FunctionalState NewState )

Enables or disables the RTC clock to be output through the relative pin.

Parameters:
NewState,: new state of the coarse calibration Output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1769 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_CR_COE.

void RTC_CalibOutputConfig ( uint32_t RTC_CalibOutput )

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
RTC_CalibOutput : Select the Calibration output Selection . This parameter can be one of the following values:

  • RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
  • RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
Return values:
None

Definition at line 1801 of file stm32l1xx_rtc.c.

References IS_RTC_CALIB_OUTPUT, RTC, and RTC_CR_COSEL.

void RTC_ClearFlag ( uint32_t RTC_FLAG )

Clears the RTC's pending flags.

Parameters:
RTC_FLAG,: specifies the RTC flag to clear. This parameter can be any combination of the following values:

  • RTC_FLAG_TAMP3F: Tamper 3 event flag.
  • RTC_FLAG_TAMP2F: Tamper 2 event flag.
  • RTC_FLAG_TAMP1F: Tamper 1 event flag.
  • RTC_FLAG_TSOVF: Time Stamp Overflow flag.
  • RTC_FLAG_TSF: Time Stamp event flag.
  • RTC_FLAG_WUTF: WakeUp Timer flag.
  • RTC_FLAG_ALRBF: Alarm B flag.
  • RTC_FLAG_ALRAF: Alarm A flag.
  • RTC_FLAG_RSF: Registers Synchronized flag.
Return values:
None

Definition at line 2548 of file stm32l1xx_rtc.c.

References IS_RTC_CLEAR_FLAG, RTC, and RTC_ISR_INIT.

void RTC_ClearITPendingBit ( uint32_t RTC_IT )

Clears the RTC's interrupt pending bits.

Parameters:
RTC_IT,: specifies the RTC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RTC_IT_TS: Time Stamp interrupt
  • RTC_IT_WUT: WakeUp Timer interrupt
  • RTC_IT_ALRB: Alarm B interrupt
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_TAMP1: Tamper1 event interrupt
  • RTC_IT_TAMP2: Tamper2 event interrupt
  • RTC_IT_TAMP3: Tamper3 event interrupt
Return values:
None

Definition at line 2612 of file stm32l1xx_rtc.c.

References IS_RTC_CLEAR_IT, RTC, and RTC_ISR_INIT.

ErrorStatus RTC_CoarseCalibCmd ( FunctionalState NewState )

Enables or disables the Coarse calibration process.

Parameters:
NewState,: new state of the Coarse calibration. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Coarse calibration are enabled/disabled
  • ERROR: RTC Coarse calibration are not enabled/disabled

Definition at line 1722 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, IS_FUNCTIONAL_STATE, RTC, RTC_CR_DCE, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

ErrorStatus RTC_CoarseCalibConfig | ( | uint32_t | RTC_CalibSign,
 |  | uint32_t | Value
 | ) |  |

Configures the Coarse Calibration parameters.

Parameters:
RTC_CalibSign,: specifies the sign of the calibration value. This parameter can be one of the following values:

  • RTC_CalibSign_Positive: The value sign is positive.
  • RTC_CalibSign_Negative: The value sign is negative.
Value,: value of calibration expressed in ppm (coded on 5 bits) This value should be between 0 and 63 when using negative sign with a 2-ppm step. This value should be between 0 and 126 when using positive sign with a 4-ppm step.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Coarse calibration are initialized
  • ERROR: RTC Coarse calibration are not initialized

Definition at line 1681 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_CALIB_SIGN, IS_RTC_CALIB_VALUE, RTC, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

void RTC_DateStructInit ( RTC_DateTypeDef * RTC_DateStruct )

Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).

Parameters:
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 972 of file stm32l1xx_rtc.c.

References RTC_DateTypeDef::RTC_Date, RTC_DateTypeDef::RTC_Month, RTC_Month_January, RTC_DateTypeDef::RTC_WeekDay, RTC_Weekday_Monday, and RTC_DateTypeDef::RTC_Year.

void RTC_DayLightSavingConfig | ( | uint32_t | RTC_DayLightSaving,
 |  | uint32_t | RTC_StoreOperation
 | ) |  |

Adds or substract one hour from the current time.

Parameters:
RTC_DayLightSaveOperation,: the value of hour adjustment. This parameter can be one of the following values:

  • RTC_DayLightSaving_SUB1H: Substract one hour (winter time).
  • RTC_DayLightSaving_ADD1H: Add one hour (summer time).
RTC_StoreOperation,: Specifies the value to be written in the BCK bit in CR register to store the operation. This parameter can be one of the following values:

  • RTC_StoreOperation_Reset: BCK Bit Reset.
  • RTC_StoreOperation_Set: BCK Bit Set.
Return values:
None

Definition at line 1565 of file stm32l1xx_rtc.c.

References IS_RTC_DAYLIGHT_SAVING, IS_RTC_STORE_OPERATION, RTC, and RTC_CR_BCK.

ErrorStatus RTC_DeInit ( void )

Deinitializes the RTC registers to their default reset values.

Note:
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are deinitialized
  • ERROR: RTC registers are not deinitialized

Definition at line 309 of file stm32l1xx_rtc.c.

References ERROR, INITMODE_TIMEOUT, RESET, RTC, RTC_EnterInitMode(), RTC_ISR_WUTWF, RTC_WaitForSynchro(), and SUCCESS.

ErrorStatus RTC_EnterInitMode ( void )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 488 of file stm32l1xx_rtc.c.

References ERROR, INITMODE_TIMEOUT, RESET, RTC, RTC_INIT_MASK, RTC_ISR_INITF, and SUCCESS.

Referenced by RTC_CoarseCalibCmd(), RTC_CoarseCalibConfig(), RTC_DeInit(), RTC_Init(), RTC_RefClockCmd(), RTC_SetDate(), and RTC_SetTime().

void RTC_ExitInitMode ( void )

Exits the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
Parameters:
None
Return values:
None

Definition at line 533 of file stm32l1xx_rtc.c.

References RTC, and RTC_ISR_INIT.

Referenced by RTC_CoarseCalibCmd(), RTC_CoarseCalibConfig(), RTC_Init(), RTC_RefClockCmd(), RTC_SetDate(), and RTC_SetTime().

void RTC_GetAlarm | ( | uint32_t | RTC_Format,
 |  | uint32_t | RTC_Alarm,
 |  | RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
RTC_Format,: specifies the format of the output parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_Alarm,: specifies the alarm to be read. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure that will contains the output alarm configuration values.
Return values:
None

Definition at line 1192 of file stm32l1xx_rtc.c.

References IS_RTC_ALARM, IS_RTC_FORMAT, RTC, RTC_Alarm_A, RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmMask_All, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_ALRMAR_DT, RTC_ALRMAR_DU, RTC_ALRMAR_HT, RTC_ALRMAR_HU, RTC_ALRMAR_MNT, RTC_ALRMAR_MNU, RTC_ALRMAR_PM, RTC_ALRMAR_ST, RTC_ALRMAR_SU, RTC_ALRMAR_WDSEL, RTC_Bcd2ToByte(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

uint32_t RTC_GetAlarmSubSecond ( uint32_t RTC_Alarm )

Gets the RTC Alarm Subseconds value.

Parameters:
RTC_Alarm,: specifies the alarm to be read. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
None
Return values:
RTC Alarm Subseconds value.

Definition at line 1381 of file stm32l1xx_rtc.c.

References RTC, RTC_Alarm_A, RTC_ALRMASSR_SS, and RTC_ALRMBSSR_SS.

void RTC_GetDate | ( | uint32_t | RTC_Format,
 |  | RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Get the RTC current date.

Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that will contain the returned current date configuration.
Return values:
None

Definition at line 991 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_DateTypeDef::RTC_Date, RTC_DR_DT, RTC_DR_DU, RTC_DR_MT, RTC_DR_MU, RTC_DR_RESERVED_MASK, RTC_DR_WDU, RTC_DR_YT, RTC_DR_YU, RTC_Format_BIN, RTC_DateTypeDef::RTC_Month, RTC_DateTypeDef::RTC_WeekDay, and RTC_DateTypeDef::RTC_Year.

FlagStatus RTC_GetFlagStatus ( uint32_t RTC_FLAG )

Checks whether the specified RTC flag is set or not.

Parameters:
RTC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • RTC_FLAG_RECALPF: RECALPF event flag.
  • RTC_FLAG_TAMP3F: Tamper 3 event flag.
  • RTC_FLAG_TAMP2F: Tamper 2 event flag.
  • RTC_FLAG_TAMP1F: Tamper 1 event flag.
  • RTC_FLAG_TSOVF: Time Stamp OverFlow flag.
  • RTC_FLAG_TSF: Time Stamp event flag.
  • RTC_FLAG_WUTF: WakeUp Timer flag.
  • RTC_FLAG_ALRBF: Alarm B flag.
  • RTC_FLAG_ALRAF: Alarm A flag.
  • RTC_FLAG_INITF: Initialization mode flag.
  • RTC_FLAG_RSF: Registers Synchronized flag.
  • RTC_FLAG_INITS: Registers Configured flag. : Shift operation pending flag.
  • RTC_FLAG_WUTWF: WakeUp Timer Write flag.
  • RTC_FLAG_ALRBWF: Alarm B Write flag.
  • RTC_FLAG_ALRAWF: Alarm A write flag.
Return values:
The new state of RTC_FLAG (SET or RESET).

Definition at line 2510 of file stm32l1xx_rtc.c.

References IS_RTC_GET_FLAG, RESET, RTC, RTC_FLAGS_MASK, and SET.

ITStatus RTC_GetITStatus ( uint32_t RTC_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
RTC_IT,: specifies the RTC interrupt source to check. This parameter can be one of the following values:

  • RTC_IT_TS: Time Stamp interrupt.
  • RTC_IT_WUT: WakeUp Timer interrupt.
  • RTC_IT_ALRB: Alarm B interrupt.
  • RTC_IT_ALRA: Alarm A interrupt.
  • RTC_IT_TAMP1: Tamper1 event interrupt.
  • RTC_IT_TAMP2: Tamper2 event interrupt.
  • RTC_IT_TAMP3: Tamper3 event interrupt.
Return values:
The new state of RTC_IT (SET or RESET).

Definition at line 2570 of file stm32l1xx_rtc.c.

References IS_RTC_GET_IT, RESET, RTC, RTC_TAFCR_TAMPIE, and SET.

uint32_t RTC_GetStoreOperation ( void )

Returns the RTC Day Light Saving stored operation.

Parameters:
None
Return values:
RTC Day Light Saving stored operation.

  • RTC_StoreOperation_Reset
  • RTC_StoreOperation_Set

Definition at line 1592 of file stm32l1xx_rtc.c.

References RTC, and RTC_CR_BCK.

uint32_t RTC_GetSubSecond ( void )

Gets the RTC current Calendar Subseconds value.

Note:
This function freeze the Time and Date registers after reading the SSR register.
Parameters:
None
Return values:
RTC current Calendar Subseconds value.

Definition at line 856 of file stm32l1xx_rtc.c.

References RTC.

void RTC_GetTime | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Get the RTC current Time.

Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure that will contain the returned current time configuration.
Return values:
None

Definition at line 823 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_HT, RTC_TR_HU, RTC_TR_MNT, RTC_TR_MNU, RTC_TR_PM, RTC_TR_RESERVED_MASK, RTC_TR_ST, and RTC_TR_SU.

void RTC_GetTimeStamp | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_StampTimeStruct,
 |  | RTC_DateTypeDef * | RTC_StampDateStruct
 | ) |  |

Get the RTC TimeStamp value and masks.

Parameters:
RTC_Format,: specifies the format of the output parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format
  • RTC_Format_BCD: BCD data format
RTC_StampTimeStruct,: pointer to a RTC_TimeTypeDef structure that will contains the TimeStamp time values.
RTC_StampDateStruct,: pointer to a RTC_DateTypeDef structure that will contains the TimeStamp date values.
Return values:
None

Definition at line 1957 of file stm32l1xx_rtc.c.

References IS_RTC_FORMAT, RTC, RTC_Bcd2ToByte(), RTC_DateTypeDef::RTC_Date, RTC_DR_DT, RTC_DR_DU, RTC_DR_MT, RTC_DR_MU, RTC_DR_RESERVED_MASK, RTC_DR_WDU, RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_DateTypeDef::RTC_Month, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_HT, RTC_TR_HU, RTC_TR_MNT, RTC_TR_MNU, RTC_TR_PM, RTC_TR_RESERVED_MASK, RTC_TR_ST, RTC_TR_SU, RTC_DateTypeDef::RTC_WeekDay, and RTC_DateTypeDef::RTC_Year.

uint32_t RTC_GetTimeStampSubSecond ( void )

Get the RTC timestamp Subseconds value.

Parameters:
None
Return values:
RTC current timestamp Subseconds value.

Definition at line 2001 of file stm32l1xx_rtc.c.

References RTC.

uint32_t RTC_GetWakeUpCounter ( void )

Returns the RTC WakeUp timer counter value.

Parameters:
None
Return values:
The RTC WakeUp Counter value.

Definition at line 1477 of file stm32l1xx_rtc.c.

References RTC, and RTC_WUTR_WUT.

ErrorStatus RTC_Init ( RTC_InitTypeDef * RTC_InitStruct )

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTC_InitStruct,: pointer to a RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 393 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_SYNCH_PREDIV, RTC, RTC_InitTypeDef::RTC_AsynchPrediv, RTC_CR_FMT, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_InitTypeDef::RTC_HourFormat, RTC_InitTypeDef::RTC_SynchPrediv, and SUCCESS.

void RTC_ITConfig | ( | uint32_t | RTC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC interrupts.

Parameters:
RTC_IT,: specifies the RTC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RTC_IT_TS: Time Stamp interrupt mask.
  • RTC_IT_WUT: WakeUp Timer interrupt mask.
  • RTC_IT_ALRB: Alarm B interrupt mask.
  • RTC_IT_ALRA: Alarm A interrupt mask.
  • RTC_IT_TAMP: Tamper event interrupt mask.
NewState,: new state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2460 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_CONFIG_IT, RTC, and RTC_TAFCR_TAMPIE.

void RTC_OutputConfig | ( | uint32_t | RTC_Output,
 |  | uint32_t | RTC_OutputPolarity
 | ) |  |

Configures the RTC output source (AFO_ALARM).

Parameters:
RTC_Output,: Specifies which signal will be routed to the RTC output. This parameter can be one of the following values:

  • RTC_Output_Disable: No output selected
  • RTC_Output_AlarmA: signal of AlarmA mapped to output.
  • RTC_Output_AlarmB: signal of AlarmB mapped to output.
  • RTC_Output_WakeUp: signal of WakeUp mapped to output.
RTC_OutputPolarity,: Specifies the polarity of the output signal. This parameter can be one of the following:

  • RTC_OutputPolarity_High: The output pin is high when the ALRAF/ALRBF/WUTF is high (depending on OSEL).
  • RTC_OutputPolarity_Low: The output pin is low when the ALRAF/ALRBF/WUTF is high (depending on OSEL).
Return values:
None

Definition at line 1630 of file stm32l1xx_rtc.c.

References IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, RTC, RTC_CR_OSEL, and RTC_CR_POL.

void RTC_OutputTypeConfig ( uint32_t RTC_OutputType )

Configures the RTC Output Pin mode.

Parameters:
RTC_OutputType,: specifies the RTC Output (PC13) pin mode. This parameter can be one of the following values:

  • RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in Open Drain mode.
  • RTC_OutputType_PushPull: RTC Output (PC13) is configured in Push Pull mode.
Return values:
None

Definition at line 2302 of file stm32l1xx_rtc.c.

References IS_RTC_OUTPUT_TYPE, RTC, and RTC_TAFCR_ALARMOUTTYPE.

uint32_t RTC_ReadBackupRegister ( uint32_t RTC_BKP_DR )

Reads data from the specified RTC Backup data Register.

Parameters:
RTC_BKP_DR,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
None

Definition at line 2262 of file stm32l1xx_rtc.c.

References IS_RTC_BKP, and RTC_BASE.

ErrorStatus RTC_RefClockCmd ( FunctionalState NewState )

Enables or disables the RTC reference clock detection.

Parameters:
NewState,: new state of the RTC reference clock. This parameter can be: ENABLE or DISABLE.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC reference clock detection is enabled
  • ERROR: RTC reference clock detection is disabled

Definition at line 598 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, IS_FUNCTIONAL_STATE, RTC, RTC_CR_REFCKON, RTC_EnterInitMode(), RTC_ExitInitMode(), and SUCCESS.

void RTC_SetAlarm | ( | uint32_t | RTC_Format,
 |  | uint32_t | RTC_Alarm,
 |  | RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the specified RTC Alarm.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the RTC_AlarmCmd(DISABLE)).
Parameters:
RTC_Format,: specifies the format of the returned parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_Alarm,: specifies the alarm to be configured. This parameter can be one of the following values:

  • RTC_Alarm_A: to select Alarm A.
  • RTC_Alarm_B: to select Alarm B.
RTC_AlarmStruct,: pointer to a RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
None

Definition at line 1051 of file stm32l1xx_rtc.c.

References IS_ALARM_MASK, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_FORMAT, IS_RTC_H12, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RESET, RTC, RTC_Alarm_A, RTC_AlarmTypeDef::RTC_AlarmDateWeekDay, RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel, RTC_AlarmDateWeekDaySel_Date, RTC_AlarmTypeDef::RTC_AlarmMask, RTC_AlarmTypeDef::RTC_AlarmTime, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_FMT, RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

ErrorStatus RTC_SetDate | ( | uint32_t | RTC_Format,
 |  | RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTC_Format,: specifies the format of the entered parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Date register is configured
  • ERROR: RTC Date register is not configured

Definition at line 881 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RESET, RTC, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_BYPSHAD, RTC_DateTypeDef::RTC_Date, RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_Format_BIN, RTC_DateTypeDef::RTC_Month, RTC_WaitForSynchro(), RTC_DateTypeDef::RTC_WeekDay, RTC_DateTypeDef::RTC_Year, and SUCCESS.

ErrorStatus RTC_SetTime | ( | uint32_t | RTC_Format,
 |  | RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTC_Format,: specifies the format of the entered parameters. This parameter can be one of the following values:

  • RTC_Format_BIN: Binary data format.
  • RTC_Format_BCD: BCD data format.
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 700 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_FORMAT, IS_RTC_H12, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RESET, RTC, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CR_BYPSHAD, RTC_CR_FMT, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_Format_BIN, RTC_TimeTypeDef::RTC_H12, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, RTC_TimeTypeDef::RTC_Seconds, RTC_TR_RESERVED_MASK, RTC_WaitForSynchro(), and SUCCESS.

void RTC_SetWakeUpCounter ( uint32_t RTC_WakeUpCounter )

Configures the RTC Wakeup counter.

Note:
The RTC WakeUp counter can only be written when the RTC WakeUp. is disabled (Use the RTC_WakeUpCmd(DISABLE)).
Parameters:
RTC_WakeUpCounter,: specifies the WakeUp counter. This parameter can be a value from 0x0000 to 0xFFFF.
Return values:
None

Definition at line 1456 of file stm32l1xx_rtc.c.

References IS_RTC_WAKEUP_COUNTER, and RTC.

ErrorStatus RTC_SmoothCalibConfig | ( | uint32_t | RTC_SmoothCalibPeriod,
 |  | uint32_t | RTC_SmoothCalibPlusPulses,
 |  | uint32_t | RTC_SmouthCalibMinusPulsesValue
 | ) |  |

Configures the Smooth Calibration Settings.

Parameters:
RTC_SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values:

  • RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
  • RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
  • RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
RTC_SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:

  • RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
  • RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
RTC_SmouthCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Calib registers are configured
  • ERROR: RTC Calib registers are not configured

Definition at line 1837 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RECALPF_TIMEOUT, RESET, RTC, RTC_ISR_RECALPF, and SUCCESS.

void RTC_StructInit ( RTC_InitTypeDef * RTC_InitStruct )

Fills each RTC_InitStruct member with its default value.

Parameters:
RTC_InitStruct,: pointer to a RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 439 of file stm32l1xx_rtc.c.

References RTC_InitTypeDef::RTC_AsynchPrediv, RTC_InitTypeDef::RTC_HourFormat, RTC_HourFormat_24, and RTC_InitTypeDef::RTC_SynchPrediv.

ErrorStatus RTC_SynchroShiftConfig | ( | uint32_t | RTC_ShiftAdd1S,
 |  | uint32_t | RTC_ShiftSubFS
 | ) |  |

Configures the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register
Parameters:
RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. This parameter can be one of the following values :

  • RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
  • RTC_ShiftAdd1S_Reset: No effect.
RTC_ShiftSubFS,: Select the number of Second Fractions to Substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC Shift registers are configured
  • ERROR: RTC Shift registers are not configured

Definition at line 2340 of file stm32l1xx_rtc.c.

References ERROR, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RESET, RTC, RTC_CR_REFCKON, RTC_ISR_SHPF, RTC_WaitForSynchro(), SHPF_TIMEOUT, and SUCCESS.

void RTC_TamperCmd | ( | uint32_t | RTC_Tamper,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the Tamper detection.

Parameters:
RTC_Tamper,: Selected tamper pin. This parameter can be any combination of the following values:

  • RTC_Tamper_1: Select Tamper 1.
  • RTC_Tamper_2: Select Tamper 2.
  • RTC_Tamper_3: Select Tamper 3.
NewState,: new state of the tamper pin. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2069 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_TAMPER, and RTC.

void RTC_TamperFilterConfig ( uint32_t RTC_TamperFilter )

Configures the Tampers Filter.

Parameters:
RTC_TamperFilter,: Specifies the tampers filter. This parameter can be one of the following values:

  • RTC_TamperFilter_Disable: Tamper filter is disabled.
  • RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive samples at the active level.
  • RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive samples at the active level.
  • RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive samples at the active level.
Return values:
None

Definition at line 2100 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_FILTER, RTC, and RTC_TAFCR_TAMPFLT.

void RTC_TamperPinsPrechargeDuration ( uint32_t RTC_TamperPrechargeDuration )

Configures the Tampers Pins input Precharge Duration.

Parameters:
RTC_TamperPrechargeDuration,: Specifies the Tampers Pins input Precharge Duration. This parameter can be one of the following values:

  • RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
  • RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
Return values:
None

Definition at line 2157 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_PRECHARGE_DURATION, RTC, and RTC_TAFCR_TAMPPRCH.

void RTC_TamperPullUpCmd ( FunctionalState NewState )

Enables or Disables the Precharge of Tamper pin.

Parameters:
NewState,: new state of tamper pull up. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2200 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_TAFCR_TAMPPUDIS.

void RTC_TamperSamplingFreqConfig ( uint32_t RTC_TamperSamplingFreq )

Configures the Tampers Sampling Frequency.

Parameters:
RTC_TamperSamplingFreq,: Specifies the tampers Sampling Frequency. This parameter can be one of the following values:

  • RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768
  • RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384
  • RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192
  • RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096
  • RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048
  • RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024
  • RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled with a frequency = RTCCLK / 512
  • RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled with a frequency = RTCCLK / 256
Return values:
None

Definition at line 2134 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER_SAMPLING_FREQ, RTC, and RTC_TAFCR_TAMPFREQ.

void RTC_TamperTriggerConfig | ( | uint32_t | RTC_Tamper,
 |  | uint32_t | RTC_TamperTrigger
 | ) |  |

Configures the select Tamper pin edge.

Parameters:
RTC_Tamper,: Selected tamper pin. This parameter can be any combination of the following values:

  • RTC_Tamper_1: Select Tamper 1.
  • RTC_Tamper_2: Select Tamper 2.
  • RTC_Tamper_3: Select Tamper 3.
RTC_TamperTrigger,: Specifies the trigger on the tamper pin that stimulates tamper event. This parameter can be one of the following values:

  • RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
  • RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
  • RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
  • RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
Return values:
None

Definition at line 2039 of file stm32l1xx_rtc.c.

References IS_RTC_TAMPER, IS_RTC_TAMPER_TRIGGER, RTC, and RTC_TamperTrigger_RisingEdge.

void RTC_TimeStampCmd | ( | uint32_t | RTC_TimeStampEdge,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.

Parameters:
RTC_TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following:

  • RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TimeStampEdge_Falling: the Time stamp event occurs on the falling edge of the related pin.
NewState,: new state of the TimeStamp. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1913 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_TIMESTAMP_EDGE, RTC, RTC_CR_TSE, and RTC_CR_TSEDGE.

void RTC_TimeStampOnTamperDetectionCmd ( FunctionalState NewState )

Enables or Disables the TimeStamp on Tamper Detection Event.

Note:
The timestamp is valid even the TSE bit in tamper control register is reset.
Parameters:
NewState,: new state of the timestamp on tamper event. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2177 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, RTC, and RTC_TAFCR_TAMPTS.

void RTC_TimeStructInit ( RTC_TimeTypeDef * RTC_TimeStruct )

Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct,: pointer to a RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 804 of file stm32l1xx_rtc.c.

References RTC_TimeTypeDef::RTC_H12, RTC_H12_AM, RTC_TimeTypeDef::RTC_Hours, RTC_TimeTypeDef::RTC_Minutes, and RTC_TimeTypeDef::RTC_Seconds.

ErrorStatus RTC_WaitForSynchro ( void )

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
None
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 555 of file stm32l1xx_rtc.c.

References ERROR, RESET, RTC, RTC_ISR_RSF, RTC_RSF_MASK, SUCCESS, and SYNCHRO_TIMEOUT.

Referenced by RTC_DeInit(), RTC_SetDate(), RTC_SetTime(), and RTC_SynchroShiftConfig().

void RTC_WakeUpClockConfig ( uint32_t RTC_WakeUpClock )

Configures the RTC Wakeup clock source.

Note:
The WakeUp Clock source can only be changed when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
Parameters:
RTC_WakeUpClock,: Wakeup Clock source. This parameter can be one of the following values:

  • RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16.
  • RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8.
  • RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4.
  • RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2.
  • RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE.
  • RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE.
Return values:
None

Definition at line 1429 of file stm32l1xx_rtc.c.

References IS_RTC_WAKEUP_CLOCK, RTC, and RTC_CR_WUCKSEL.

ErrorStatus RTC_WakeUpCmd ( FunctionalState NewState )

Enables or Disables the RTC WakeUp timer.

Parameters:
NewState,: new state of the WakeUp timer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1489 of file stm32l1xx_rtc.c.

References DISABLE, ERROR, INITMODE_TIMEOUT, IS_FUNCTIONAL_STATE, RESET, RTC, RTC_CR_WUTE, RTC_ISR_WUTWF, and SUCCESS.

void RTC_WriteBackupRegister | ( | uint32_t | RTC_BKP_DR,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
RTC_BKP_DR,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 2241 of file stm32l1xx_rtc.c.

References IS_RTC_BKP, and RTC_BASE.

void RTC_WriteProtectionCmd ( FunctionalState NewState )

Enables or disables the RTC registers write protection.

Note:
All the RTC registers are write protected except for RTC_ISR[13:8], RTC_TAFCR and RTC_BKPxR.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Parameters:
NewState,: new state of the write protection. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 461 of file stm32l1xx_rtc.c.

References DISABLE, IS_FUNCTIONAL_STATE, and RTC.


STM32L1xx Standard Peripherals Firmware Library: RTC_AlarmTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_AlarmTypeDef Struct Reference
RTC

RTC Alarm structure definition. More...

#include <stm32l1xx_rtc.h>

Data Fields

uint8_t | RTC_AlarmDateWeekDay
uint32_t | RTC_AlarmDateWeekDaySel
uint32_t | RTC_AlarmMask
RTC_TimeTypeDef RTC_AlarmTime

Detailed Description

RTC Alarm structure definition.

Definition at line 103 of file stm32l1xx_rtc.h.

Field Documentation

uint8_t RTC_AlarmTypeDef::RTC_AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC_WeekDay_Definitions

Definition at line 113 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), and RTC_SetAlarm().

uint32_t RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC_AlarmDateWeekDay_Definitions

Definition at line 110 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), and RTC_SetAlarm().

uint32_t RTC_AlarmTypeDef::RTC_AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC_AlarmMask_Definitions

Definition at line 107 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), and RTC_SetAlarm().

RTC_TimeTypeDef RTC_AlarmTypeDef::RTC_AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 105 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), and RTC_SetAlarm().

The documentation for this struct was generated from the following file:
  • stm32l1xx_rtc.h


STM32L1xx Standard Peripherals Firmware Library: RTC_DateTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_DateTypeDef Struct Reference
RTC

RTC Date structure definition. More...

#include <stm32l1xx_rtc.h>

Data Fields

uint8_t | RTC_Date
uint8_t | RTC_Month
uint8_t | RTC_WeekDay
uint8_t | RTC_Year

Detailed Description

RTC Date structure definition.

Definition at line 85 of file stm32l1xx_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::RTC_Date

Specifies the RTC Date. This parameter must be set to a value in the 1-31 range.

Definition at line 93 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit(), RTC_GetDate(), RTC_GetTimeStamp(), and RTC_SetDate().

uint8_t RTC_DateTypeDef::RTC_Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC_Month_Date_Definitions

Definition at line 90 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit(), RTC_GetDate(), RTC_GetTimeStamp(), and RTC_SetDate().

uint8_t RTC_DateTypeDef::RTC_WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC_WeekDay_Definitions

Definition at line 87 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit(), RTC_GetDate(), RTC_GetTimeStamp(), and RTC_SetDate().

uint8_t RTC_DateTypeDef::RTC_Year

Specifies the RTC Date Year. This parameter must be set to a value in the 0-99 range.

Definition at line 96 of file stm32l1xx_rtc.h.

Referenced by RTC_DateStructInit(), RTC_GetDate(), RTC_GetTimeStamp(), and RTC_SetDate().

The documentation for this struct was generated from the following file:
  • stm32l1xx_rtc.h


STM32L1xx Standard Peripherals Firmware Library: RTC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_InitTypeDef Struct Reference
RTC

RTC Init structures definition. More...

#include <stm32l1xx_rtc.h>

Data Fields

uint32_t | RTC_AsynchPrediv
uint32_t | RTC_HourFormat
uint32_t | RTC_SynchPrediv

Detailed Description

RTC Init structures definition.

Definition at line 50 of file stm32l1xx_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::RTC_AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be set to a value lower than 0x7F

Definition at line 55 of file stm32l1xx_rtc.h.

Referenced by RTC_Init(), and RTC_StructInit().

uint32_t RTC_InitTypeDef::RTC_HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC_Hour_Formats

Definition at line 52 of file stm32l1xx_rtc.h.

Referenced by RTC_Init(), and RTC_StructInit().

uint32_t RTC_InitTypeDef::RTC_SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be set to a value lower than 0x7FFF

Definition at line 58 of file stm32l1xx_rtc.h.

Referenced by RTC_Init(), and RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_rtc.h


STM32L1xx Standard Peripherals Firmware Library: RTC_TimeTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_TimeTypeDef Struct Reference
RTC

RTC Time structure definition. More...

#include <stm32l1xx_rtc.h>

Data Fields

uint8_t | RTC_H12
uint8_t | RTC_Hours
uint8_t | RTC_Minutes
uint8_t | RTC_Seconds

Detailed Description

RTC Time structure definition.

Definition at line 65 of file stm32l1xx_rtc.h.

Field Documentation

uint8_t RTC_TimeTypeDef::RTC_H12

Specifies the RTC AM/PM Time. This parameter can be a value of RTC_AM_PM_Definitions

Definition at line 78 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetTime(), and RTC_TimeStructInit().

uint8_t RTC_TimeTypeDef::RTC_Hours

Specifies the RTC Time Hour. This parameter must be set to a value in the 0-12 range if the RTC_HourFormat_12 is selected or 0-23 range if the RTC_HourFormat_24 is selected.

Definition at line 67 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetTime(), and RTC_TimeStructInit().

uint8_t RTC_TimeTypeDef::RTC_Minutes

Specifies the RTC Time Minutes. This parameter must be set to a value in the 0-59 range.

Definition at line 72 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetTime(), and RTC_TimeStructInit().

uint8_t RTC_TimeTypeDef::RTC_Seconds

Specifies the RTC Time Seconds. This parameter must be set to a value in the 0-59 range.

Definition at line 75 of file stm32l1xx_rtc.h.

Referenced by RTC_AlarmStructInit(), RTC_GetAlarm(), RTC_GetTime(), RTC_GetTimeStamp(), RTC_SetAlarm(), RTC_SetTime(), and RTC_TimeStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_rtc.h


STM32L1xx Standard Peripherals Firmware Library: SDIO_Clock_Edge

Defines

SDIO_Clock_Edge

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_EDGE(EDGE)
#define | SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define | SDIO_ClockEdge_Rising ((uint32_t)0x00000000)

Define Documentation

#define IS_SDIO_CLOCK_EDGE ( EDGE )
Value:
(((EDGE) == SDIO_ClockEdge_Rising) || \
                                  ((EDGE) == SDIO_ClockEdge_Falling))

Definition at line 124 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)

Definition at line 123 of file stm32l1xx_sdio.h.

#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)

Definition at line 122 of file stm32l1xx_sdio.h.

Referenced by SDIO_StructInit().


STM32L1xx Standard Peripherals Firmware Library: SDIO_Clock_Bypass

Defines

SDIO_Clock_Bypass

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_BYPASS(BYPASS)
#define | SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockBypass_Enable ((uint32_t)0x00000400)

Define Documentation

#define IS_SDIO_CLOCK_BYPASS ( BYPASS )
Value:
(((BYPASS) == SDIO_ClockBypass_Disable) || \
                                     ((BYPASS) == SDIO_ClockBypass_Enable))

Definition at line 136 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)

Definition at line 134 of file stm32l1xx_sdio.h.

Referenced by SDIO_StructInit().

#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)

Definition at line 135 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Clock_Power_Save

Defines

SDIO_Clock_Power_Save

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_POWER_SAVE(SAVE)
#define | SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)

Define Documentation

#define IS_SDIO_CLOCK_POWER_SAVE ( SAVE )
Value:
(((SAVE) == SDIO_ClockPowerSave_Disable) || \
                                        ((SAVE) == SDIO_ClockPowerSave_Enable))

Definition at line 148 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)

Definition at line 146 of file stm32l1xx_sdio.h.

Referenced by SDIO_StructInit().

#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)

Definition at line 147 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Bus_Wide

Defines

SDIO_Bus_Wide

SDIO_Exported_Constants

Defines

#define | IS_SDIO_BUS_WIDE(WIDE)
#define | SDIO_BusWide_1b ((uint32_t)0x00000000)
#define | SDIO_BusWide_4b ((uint32_t)0x00000800)
#define | SDIO_BusWide_8b ((uint32_t)0x00001000)

Define Documentation

#define IS_SDIO_BUS_WIDE ( WIDE )
Value:
(((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
                                ((WIDE) == SDIO_BusWide_8b))

Definition at line 161 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init().

#define SDIO_BusWide_1b ((uint32_t)0x00000000)

Definition at line 158 of file stm32l1xx_sdio.h.

Referenced by SDIO_StructInit().

#define SDIO_BusWide_4b ((uint32_t)0x00000800)

Definition at line 159 of file stm32l1xx_sdio.h.

#define SDIO_BusWide_8b ((uint32_t)0x00001000)

Definition at line 160 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Hardware_Flow_Control

Defines

SDIO_Hardware_Flow_Control

SDIO_Exported_Constants

Defines

#define | IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
#define | SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define | SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)

Define Documentation

#define IS_SDIO_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))

Definition at line 174 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init().

#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)

Definition at line 172 of file stm32l1xx_sdio.h.

Referenced by SDIO_StructInit().

#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)

Definition at line 173 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Power_State

Defines

SDIO_Power_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
#define | SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define | SDIO_PowerState_ON ((uint32_t)0x00000003)

Define Documentation

#define IS_SDIO_POWER_STATE ( STATE ) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))

Definition at line 186 of file stm32l1xx_sdio.h.

Referenced by SDIO_SetPowerState().

#define SDIO_PowerState_OFF ((uint32_t)0x00000000)

Definition at line 184 of file stm32l1xx_sdio.h.

#define SDIO_PowerState_ON ((uint32_t)0x00000003)

Definition at line 185 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Interrupt_soucres

Defines

SDIO_Interrupt_soucres

SDIO_Exported_Constants

Defines

#define | IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
#define | SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define | SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define | SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define | SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_IT_RXACT ((uint32_t)0x00002000)
#define | SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define | SDIO_IT_TXACT ((uint32_t)0x00001000)
#define | SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_IT_TXUNDERR ((uint32_t)0x00000010)

Define Documentation

#define IS_SDIO_IT ( IT ) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))

Definition at line 220 of file stm32l1xx_sdio.h.

Referenced by SDIO_ITConfig().

#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)

Definition at line 196 of file stm32l1xx_sdio.h.

#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)

Definition at line 219 of file stm32l1xx_sdio.h.

#define SDIO_IT_CMDACT ((uint32_t)0x00000800)

Definition at line 207 of file stm32l1xx_sdio.h.

#define SDIO_IT_CMDREND ((uint32_t)0x00000040)

Definition at line 202 of file stm32l1xx_sdio.h.

#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)

Definition at line 203 of file stm32l1xx_sdio.h.

#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)

Definition at line 198 of file stm32l1xx_sdio.h.

#define SDIO_IT_DATAEND ((uint32_t)0x00000100)

Definition at line 204 of file stm32l1xx_sdio.h.

#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)

Definition at line 206 of file stm32l1xx_sdio.h.

#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)

Definition at line 197 of file stm32l1xx_sdio.h.

#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)

Definition at line 199 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXACT ((uint32_t)0x00002000)

Definition at line 209 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)

Definition at line 217 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)

Definition at line 215 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)

Definition at line 213 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)

Definition at line 211 of file stm32l1xx_sdio.h.

#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)

Definition at line 201 of file stm32l1xx_sdio.h.

#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)

Definition at line 218 of file stm32l1xx_sdio.h.

#define SDIO_IT_STBITERR ((uint32_t)0x00000200)

Definition at line 205 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXACT ((uint32_t)0x00001000)

Definition at line 208 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)

Definition at line 216 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)

Definition at line 214 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)

Definition at line 212 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)

Definition at line 210 of file stm32l1xx_sdio.h.

#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)

Definition at line 200 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Command_Index

Defines

SDIO_Command_Index

SDIO_Exported_Constants

Defines

#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)

Define Documentation

#define IS_SDIO_CMD_INDEX ( INDEX ) ((INDEX) < 0x40)

Definition at line 229 of file stm32l1xx_sdio.h.

Referenced by SDIO_SendCommand().


STM32L1xx Standard Peripherals Firmware Library: SDIO_Response_Type

Defines

SDIO_Response_Type

SDIO_Exported_Constants

Defines

#define | IS_SDIO_RESPONSE(RESPONSE)
#define | SDIO_Response_Long ((uint32_t)0x000000C0)
#define | SDIO_Response_No ((uint32_t)0x00000000)
#define | SDIO_Response_Short ((uint32_t)0x00000040)

Define Documentation

#define IS_SDIO_RESPONSE ( RESPONSE )
Value:
(((RESPONSE) == SDIO_Response_No) || \
                                    ((RESPONSE) == SDIO_Response_Short) || \
                                    ((RESPONSE) == SDIO_Response_Long))

Definition at line 241 of file stm32l1xx_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_Response_Long ((uint32_t)0x000000C0)

Definition at line 240 of file stm32l1xx_sdio.h.

#define SDIO_Response_No ((uint32_t)0x00000000)

Definition at line 238 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit().

#define SDIO_Response_Short ((uint32_t)0x00000040)

Definition at line 239 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Wait_Interrupt_State

Defines

SDIO_Wait_Interrupt_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_WAIT(WAIT)
#define | SDIO_Wait_IT ((uint32_t)0x00000100)
#define | SDIO_Wait_No ((uint32_t)0x00000000)
#define | SDIO_Wait_Pend ((uint32_t)0x00000200)

Define Documentation

#define IS_SDIO_WAIT ( WAIT )
Value:
(((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
                            ((WAIT) == SDIO_Wait_Pend))

Definition at line 255 of file stm32l1xx_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_Wait_IT ((uint32_t)0x00000100)

SDIO Wait Interrupt Request

Definition at line 253 of file stm32l1xx_sdio.h.

#define SDIO_Wait_No ((uint32_t)0x00000000)

SDIO No Wait, TimeOut is enabled

Definition at line 252 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit().

#define SDIO_Wait_Pend ((uint32_t)0x00000200)

SDIO Wait End of transfer

Definition at line 254 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_CPSM_State

Defines

SDIO_CPSM_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
#define | SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_CPSM_Enable ((uint32_t)0x00000400)

Define Documentation

#define IS_SDIO_CPSM ( CPSM ) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))

Definition at line 267 of file stm32l1xx_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_CPSM_Disable ((uint32_t)0x00000000)

Definition at line 265 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit().

#define SDIO_CPSM_Enable ((uint32_t)0x00000400)

Definition at line 266 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Response_Registers

Defines

SDIO_Response_Registers

SDIO_Exported_Constants

Defines

#define | IS_SDIO_RESP(RESP)
#define | SDIO_RESP1 ((uint32_t)0x00000000)
#define | SDIO_RESP2 ((uint32_t)0x00000004)
#define | SDIO_RESP3 ((uint32_t)0x00000008)
#define | SDIO_RESP4 ((uint32_t)0x0000000C)

Define Documentation

#define IS_SDIO_RESP ( RESP )
Value:
(((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))

Definition at line 280 of file stm32l1xx_sdio.h.

Referenced by SDIO_GetResponse().

#define SDIO_RESP1 ((uint32_t)0x00000000)

Definition at line 276 of file stm32l1xx_sdio.h.

#define SDIO_RESP2 ((uint32_t)0x00000004)

Definition at line 277 of file stm32l1xx_sdio.h.

#define SDIO_RESP3 ((uint32_t)0x00000008)

Definition at line 278 of file stm32l1xx_sdio.h.

#define SDIO_RESP4 ((uint32_t)0x0000000C)

Definition at line 279 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Data_Length

Defines

SDIO_Data_Length

SDIO_Exported_Constants

Defines

#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)

Define Documentation

#define IS_SDIO_DATA_LENGTH ( LENGTH ) ((LENGTH) <= 0x01FFFFFF)

Definition at line 290 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig().


STM32L1xx Standard Peripherals Firmware Library: SDIO_Data_Block_Size

Defines

SDIO_Data_Block_Size

SDIO_Exported_Constants

Defines

#define | IS_SDIO_BLOCK_SIZE(SIZE)
#define | SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define | SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define | SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define | SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define | SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define | SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define | SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define | SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define | SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define | SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define | SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define | SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define | SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define | SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define | SDIO_DataBlockSize_8b ((uint32_t)0x00000030)

Define Documentation

#define IS_SDIO_BLOCK_SIZE ( SIZE )
Value:
(((SIZE) == SDIO_DataBlockSize_1b) || \
                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
                                  ((SIZE) == SDIO_DataBlockSize_16384b))

Definition at line 314 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)

Definition at line 309 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)

Definition at line 306 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)

Definition at line 313 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)

Definition at line 303 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)

Definition at line 299 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)

Definition at line 310 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)

Definition at line 307 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)

Definition at line 300 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)

Definition at line 304 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)

Definition at line 311 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)

Definition at line 301 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)

Definition at line 308 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)

Definition at line 305 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)

Definition at line 312 of file stm32l1xx_sdio.h.

#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)

Definition at line 302 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Transfer_Direction

Defines

SDIO_Transfer_Direction

SDIO_Exported_Constants

Defines

#define | IS_SDIO_TRANSFER_DIR(DIR)
#define | SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define | SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)

Define Documentation

#define IS_SDIO_TRANSFER_DIR ( DIR )
Value:
(((DIR) == SDIO_TransferDir_ToCard) || \
                                   ((DIR) == SDIO_TransferDir_ToSDIO))

Definition at line 339 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)

Definition at line 337 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)

Definition at line 338 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Transfer_Type

Defines

SDIO_Transfer_Type

SDIO_Exported_Constants

Defines

#define | IS_SDIO_TRANSFER_MODE(MODE)
#define | SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define | SDIO_TransferMode_Stream ((uint32_t)0x00000004)

Define Documentation

#define IS_SDIO_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SDIO_TransferMode_Stream) || \
                                     ((MODE) == SDIO_TransferMode_Block))

Definition at line 351 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_TransferMode_Block ((uint32_t)0x00000000)

Definition at line 349 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)

Definition at line 350 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_DPSM_State

Defines

SDIO_DPSM_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
#define | SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_DPSM_Enable ((uint32_t)0x00000001)

Define Documentation

#define IS_SDIO_DPSM ( DPSM ) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))

Definition at line 363 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_DPSM_Disable ((uint32_t)0x00000000)

Definition at line 361 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_DPSM_Enable ((uint32_t)0x00000001)

Definition at line 362 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Flags

Defines

SDIO_Flags

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define | IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_FLAG(FLAG)
#define | IS_SDIO_GET_IT(IT)
#define | SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define | SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define | SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define | SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define | SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define | SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define | SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)

Define Documentation

#define IS_SDIO_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))

Definition at line 421 of file stm32l1xx_sdio.h.

Referenced by SDIO_ClearFlag().

#define IS_SDIO_CLEAR_IT ( IT ) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))

Definition at line 448 of file stm32l1xx_sdio.h.

Referenced by SDIO_ClearITPendingBit().

#define IS_SDIO_FLAG ( FLAG )
Value:
(((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
                            ((FLAG)  == SDIO_FLAG_TXACT) || \
                            ((FLAG)  == SDIO_FLAG_RXACT) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
                            ((FLAG)  == SDIO_FLAG_CEATAEND))

Definition at line 396 of file stm32l1xx_sdio.h.

Referenced by SDIO_GetFlagStatus().

#define IS_SDIO_GET_IT ( IT )
Value:
(((IT)  == SDIO_IT_CCRCFAIL) || \
                            ((IT)  == SDIO_IT_DCRCFAIL) || \
                            ((IT)  == SDIO_IT_CTIMEOUT) || \
                            ((IT)  == SDIO_IT_DTIMEOUT) || \
                            ((IT)  == SDIO_IT_TXUNDERR) || \
                            ((IT)  == SDIO_IT_RXOVERR) || \
                            ((IT)  == SDIO_IT_CMDREND) || \
                            ((IT)  == SDIO_IT_CMDSENT) || \
                            ((IT)  == SDIO_IT_DATAEND) || \
                            ((IT)  == SDIO_IT_STBITERR) || \
                            ((IT)  == SDIO_IT_DBCKEND) || \
                            ((IT)  == SDIO_IT_CMDACT) || \
                            ((IT)  == SDIO_IT_TXACT) || \
                            ((IT)  == SDIO_IT_RXACT) || \
                            ((IT)  == SDIO_IT_TXFIFOHE) || \
                            ((IT)  == SDIO_IT_RXFIFOHF) || \
                            ((IT)  == SDIO_IT_TXFIFOF) || \
                            ((IT)  == SDIO_IT_RXFIFOF) || \
                            ((IT)  == SDIO_IT_TXFIFOE) || \
                            ((IT)  == SDIO_IT_RXFIFOE) || \
                            ((IT)  == SDIO_IT_TXDAVL) || \
                            ((IT)  == SDIO_IT_RXDAVL) || \
                            ((IT)  == SDIO_IT_SDIOIT) || \
                            ((IT)  == SDIO_IT_CEATAEND))

Definition at line 423 of file stm32l1xx_sdio.h.

Referenced by SDIO_GetITStatus().

#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)

Definition at line 372 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)

Definition at line 395 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)

Definition at line 383 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)

Definition at line 378 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)

Definition at line 379 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)

Definition at line 374 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)

Definition at line 380 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)

Definition at line 382 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)

Definition at line 373 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)

Definition at line 375 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)

Definition at line 385 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)

Definition at line 393 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)

Definition at line 391 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)

Definition at line 389 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)

Definition at line 387 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)

Definition at line 377 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)

Definition at line 394 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)

Definition at line 381 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)

Definition at line 384 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)

Definition at line 392 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)

Definition at line 390 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)

Definition at line 388 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)

Definition at line 386 of file stm32l1xx_sdio.h.

#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)

Definition at line 376 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: SDIO_Read_Wait_Mode

Defines

SDIO_Read_Wait_Mode

SDIO_Exported_Constants

Defines

#define | IS_SDIO_READWAIT_MODE(MODE)
#define | SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define | SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)

Define Documentation

#define IS_SDIO_READWAIT_MODE ( MODE )
Value:
(((MODE) == SDIO_ReadWaitMode_CLK) || \
                                     ((MODE) == SDIO_ReadWaitMode_DATA2))

Definition at line 460 of file stm32l1xx_sdio.h.

Referenced by SDIO_SetSDIOReadWaitMode().

#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)

Definition at line 458 of file stm32l1xx_sdio.h.

#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)

Definition at line 459 of file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

SDIO_Private_Functions

Initialization and Configuration functions. More...

Functions

void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================

Function Documentation

void SDIO_ClockCmd ( FunctionalState NewState )

Enables or disables the SDIO Clock.

Parameters:
NewState,: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 312 of file stm32l1xx_sdio.c.

References CLKCR_CLKEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_DeInit ( void )

Deinitializes the SDIO peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 245 of file stm32l1xx_sdio.c.

References DISABLE, ENABLE, RCC_APB2Periph_SDIO, and RCC_APB2PeriphResetCmd().

uint32_t SDIO_GetPowerState ( void )

Gets the power status of the controller.

Parameters:
None
Return values:
Power status of the controller. The returned value can be one of the following:

  • 0x00: Power OFF
  • 0x02: Power UP
  • 0x03: Power ON

Definition at line 345 of file stm32l1xx_sdio.c.

References PWR_PWRCTRL_MASK, and SDIO.

void SDIO_Init ( SDIO_InitTypeDef * SDIO_InitStruct )

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

Parameters:
SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
Return values:
None

Definition at line 258 of file stm32l1xx_sdio.c.

References CLKCR_CLEAR_MASK, IS_SDIO_BUS_WIDE, IS_SDIO_CLOCK_BYPASS, IS_SDIO_CLOCK_EDGE, IS_SDIO_CLOCK_POWER_SAVE, IS_SDIO_HARDWARE_FLOW_CONTROL, SDIO, SDIO_InitTypeDef::SDIO_BusWide, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_InitTypeDef::SDIO_ClockPowerSave, and SDIO_InitTypeDef::SDIO_HardwareFlowControl.

void SDIO_SetPowerState ( uint32_t SDIO_PowerState )

Sets the power status of the controller.

Parameters:
SDIO_PowerState,: new state of the Power state. This parameter can be one of the following values:

  • SDIO_PowerState_OFF: SDIO Power OFF.
  • SDIO_PowerState_ON: SDIO Power ON.
Return values:
None

Definition at line 328 of file stm32l1xx_sdio.c.

References IS_SDIO_POWER_STATE, and SDIO.

void SDIO_StructInit ( SDIO_InitTypeDef * SDIO_InitStruct )

Fills each SDIO_InitStruct member with its default value.

Parameters:
SDIO_InitStruct,: pointer to an SDIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 296 of file stm32l1xx_sdio.c.

References SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, and SDIO_HardwareFlowControl_Disable.


STM32L1xx Standard Peripherals Firmware Library: DMA transfers management functions

Functions

DMA transfers management functions

SDIO_Private_Functions

DMA transfers management functions. More...

Functions

void SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.

Detailed Description

DMA transfers management functions.

  ==============================================================================
                  ##### DMA transfers management functions #####
  ==============================================================================
    [..] This section provide functions allowing to program SDIO DMA transfer.

Function Documentation

void SDIO_DMACmd ( FunctionalState NewState )

Enables or disables the SDIO DMA request.

Parameters:
NewState,: new state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 373 of file stm32l1xx_sdio.c.

References DCTRL_DMAEN_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Command path state machine (CPSM) management functions

Functions

Command path state machine (CPSM) management functions

SDIO_Private_Functions

Command path state machine (CPSM) management functions. More...

Functions

void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

Detailed Description

Command path state machine (CPSM) management functions.

  ==============================================================================
       ##### Command path state machine (CPSM) management functions #####
  ==============================================================================
  [..] This section provide functions allowing to program and read the Command
       path state machine (CPSM).

Function Documentation

void SDIO_CmdStructInit ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Fills each SDIO_CmdInitStruct member with its default value.

Parameters:
SDIO_CmdInitStruct,: pointer to an SDIO_CmdInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 442 of file stm32l1xx_sdio.c.

References SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Disable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

uint8_t SDIO_GetCommandResponse ( void )

Returns command index of last command for which response received.

Parameters:
None
Return values:
Returns the command index of the last command response received.

Definition at line 457 of file stm32l1xx_sdio.c.

References SDIO.

uint32_t SDIO_GetResponse ( uint32_t SDIO_RESP )

Returns response received from the card for the last command.

Parameters:
SDIO_RESP,: Specifies the SDIO response register. This parameter can be one of the following values:

  • SDIO_RESP1: Response Register 1.
  • SDIO_RESP2: Response Register 2.
  • SDIO_RESP3: Response Register 3.
  • SDIO_RESP4: Response Register 4.
Return values:
The Corresponding response register value.

Definition at line 472 of file stm32l1xx_sdio.c.

References IS_SDIO_RESP, and SDIO_RESP_ADDR.

void SDIO_SendCommand ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

Parameters:
SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 406 of file stm32l1xx_sdio.c.

References CMD_CLEAR_MASK, IS_SDIO_CMD_INDEX, IS_SDIO_CPSM, IS_SDIO_RESPONSE, IS_SDIO_WAIT, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CmdInitTypeDef::SDIO_Response, and SDIO_CmdInitTypeDef::SDIO_Wait.


STM32L1xx Standard Peripherals Firmware Library: Data path state machine (DPSM) management functions

Functions

Data path state machine (DPSM) management functions

SDIO_Private_Functions

Data path state machine (DPSM) management functions. More...

Functions

void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

Data path state machine (DPSM) management functions.

  ==============================================================================
        ##### Data path state machine (DPSM) management functions #####
  ==============================================================================
  [..] This section provide functions allowing to program and read the Data path
       state machine (DPSM).

Function Documentation

void SDIO_DataConfig ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

Parameters:
SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 509 of file stm32l1xx_sdio.c.

References DCTRL_CLEAR_MASK, IS_SDIO_BLOCK_SIZE, IS_SDIO_DATA_LENGTH, IS_SDIO_DPSM, IS_SDIO_TRANSFER_DIR, IS_SDIO_TRANSFER_MODE, SDIO, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DataInitTypeDef::SDIO_TransferDir, and SDIO_DataInitTypeDef::SDIO_TransferMode.

void SDIO_DataStructInit ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Fills each SDIO_DataInitStruct member with its default value.

Parameters:
SDIO_DataInitStruct,: pointer to an SDIO_DataInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 550 of file stm32l1xx_sdio.c.

References SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_1b, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Disable, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, and SDIO_TransferMode_Block.

uint32_t SDIO_GetDataCounter ( void )

Returns number of remaining data bytes to be transferred.

Parameters:
None
Return values:
Number of remaining data bytes to be transferred

Definition at line 566 of file stm32l1xx_sdio.c.

References SDIO.

uint32_t SDIO_GetFIFOCount ( void )

Returns the number of words left to be written to or read from FIFO.

Parameters:
None
Return values:
Remaining number of words.

Definition at line 596 of file stm32l1xx_sdio.c.

References SDIO.

uint32_t SDIO_ReadData ( void )

Read one data word from Rx FIFO.

Parameters:
None
Return values:
Data received

Definition at line 576 of file stm32l1xx_sdio.c.

References SDIO.

void SDIO_WriteData ( uint32_t Data )

Write one data word to Tx FIFO.

Parameters:
Data,: 32-bit data word to write.
Return values:
None

Definition at line 586 of file stm32l1xx_sdio.c.

References SDIO.


STM32L1xx Standard Peripherals Firmware Library: SDIO IO Cards mode management functions

Functions

SDIO IO Cards mode management functions

SDIO_Private_Functions

SDIO IO Cards mode management functions. More...

Functions

void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.

Detailed Description

SDIO IO Cards mode management functions.

  ==============================================================================
              ##### SDIO IO Cards mode management functions #####
  ==============================================================================
  [..] This section provide functions allowing to program and read the SDIO IO
       Cards.

Function Documentation

void SDIO_SendSDIOSuspendCmd ( FunctionalState NewState )

Enables or disables the SD I/O Mode suspend command sending.

Parameters:
NewState,: new state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 683 of file stm32l1xx_sdio.c.

References CMD_SDIOSUSPEND_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetSDIOOperation ( FunctionalState NewState )

Enables or disables the SD I/O Mode Operation.

Parameters:
NewState,: new state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 669 of file stm32l1xx_sdio.c.

References DCTRL_SDIOEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetSDIOReadWaitMode ( uint32_t SDIO_ReadWaitMode )

Sets one of the two options of inserting read wait interval.

Parameters:
SDIO_ReadWaitMode,: SD I/O Read Wait operation mode. This parametre can be:

  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.
Return values:
None

Definition at line 655 of file stm32l1xx_sdio.c.

References DCTRL_RWMOD_BB, and IS_SDIO_READWAIT_MODE.

void SDIO_StartSDIOReadWait ( FunctionalState NewState )

Starts the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 625 of file stm32l1xx_sdio.c.

References DCTRL_RWSTART_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StopSDIOReadWait ( FunctionalState NewState )

Stops the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 639 of file stm32l1xx_sdio.c.

References DCTRL_RWSTOP_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: CE-ATA mode management functions

Functions

CE-ATA mode management functions

SDIO_Private_Functions

CE-ATA mode management functions. More...

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).

Detailed Description

CE-ATA mode management functions.

  ==============================================================================
                    ##### CE-ATA mode management functions #####
  ==============================================================================
  [..] This section provide functions allowing to program and read the CE-ATA
       card.

Function Documentation

void SDIO_CEATAITCmd ( FunctionalState NewState )

Enables or disables the CE-ATA interrupt.

Parameters:
NewState,: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 728 of file stm32l1xx_sdio.c.

References CMD_NIEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_CommandCompletionCmd ( FunctionalState NewState )

Enables or disables the command completion signal.

Parameters:
NewState,: new state of command completion signal. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 715 of file stm32l1xx_sdio.c.

References CMD_ENCMDCOMPL_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SendCEATACmd ( FunctionalState NewState )

Sends CE-ATA command (CMD61).

Parameters:
NewState,: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 741 of file stm32l1xx_sdio.c.

References CMD_ATACMD_BB, and IS_FUNCTIONAL_STATE.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

SDIO_Private_Functions

Interrupts and flags management functions. More...

Functions

void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.

Detailed Description

Interrupts and flags management functions.

  ==============================================================================
              ##### Interrupts and flags management functions #####
  ==============================================================================

Function Documentation

void SDIO_ClearFlag ( uint32_t SDIO_FLAG )

Clears the SDIO's pending flags.

Parameters:
SDIO_FLAG,: specifies the flag to clear. This parameter can be one or a combination of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
  • SDIO_FLAG_CTIMEOUT: Command response timeout.
  • SDIO_FLAG_DTIMEOUT: Data timeout.
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error.
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed).
  • SDIO_FLAG_CMDSENT: Command sent (no response required).
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received.
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
None

Definition at line 886 of file stm32l1xx_sdio.c.

References IS_SDIO_CLEAR_FLAG, and SDIO.

void SDIO_ClearITPendingBit ( uint32_t SDIO_IT )

Clears the SDIO's interrupt pending bits.

Parameters:
SDIO_IT,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
None

Definition at line 961 of file stm32l1xx_sdio.c.

References IS_SDIO_CLEAR_IT, and SDIO.

FlagStatus SDIO_GetFlagStatus ( uint32_t SDIO_FLAG )

Checks whether the specified SDIO flag is set or not.

Parameters:
SDIO_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
  • SDIO_FLAG_CTIMEOUT: Command response timeout.
  • SDIO_FLAG_DTIMEOUT: Data timeout.
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error.
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed).
  • SDIO_FLAG_CMDSENT: Command sent (no response required).
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
  • SDIO_FLAG_CMDACT: Command transfer in progress.
  • SDIO_FLAG_TXACT: Data transmit in progress.
  • SDIO_FLAG_RXACT: Data receive in progress.
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full.
  • SDIO_FLAG_RXFIFOF: Receive FIFO full.
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty.
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty.
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO.
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO.
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received.
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
The new state of SDIO_FLAG (SET or RESET).

Definition at line 848 of file stm32l1xx_sdio.c.

References IS_SDIO_FLAG, RESET, SDIO, and SET.

ITStatus SDIO_GetITStatus ( uint32_t SDIO_IT )

Checks whether the specified SDIO interrupt has occurred or not.

Parameters:
SDIO_IT,: specifies the SDIO interrupt source to check. This parameter can be one of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
  • SDIO_IT_CMDACT: Command transfer in progress interrupt.
  • SDIO_IT_TXACT: Data transmit in progress interrupt.
  • SDIO_IT_RXACT: Data receive in progress interrupt.
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
Return values:
The new state of SDIO_IT (SET or RESET).

Definition at line 925 of file stm32l1xx_sdio.c.

References IS_SDIO_GET_IT, RESET, SDIO, and SET.

void SDIO_ITConfig | ( | uint32_t | SDIO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SDIO interrupts.

Parameters:
SDIO_IT,: specifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
  • SDIO_IT_CMDACT: Command transfer in progress interrupt.
  • SDIO_IT_TXACT: Data transmit in progress interrupt.
  • SDIO_IT_RXACT: Data receive in progress interrupt.
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
NewState,: new state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 799 of file stm32l1xx_sdio.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_SDIO_IT, and SDIO.


STM32L1xx Standard Peripherals Firmware Library: SDIO

Data Structures | Modules | Defines | Functions

SDIO

STM32L1xx_StdPeriph_Driver

SDIO driver modules. More...

Data Structures

struct | SDIO_CmdInitTypeDef
struct | SDIO_DataInitTypeDef
struct | SDIO_InitTypeDef

Modules

SDIO_Exported_Constants
SDIO_Private_Functions

Defines

#define | ATACMD_BitNumber 0x0E
#define | CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
#define | CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
#define | CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define | CLKEN_BitNumber 0x08
#define | CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
#define | CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
#define | CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
#define | CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
#define | CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define | CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
#define | DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
#define | DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
#define | DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define | DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
#define | DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
#define | DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
#define | DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
#define | DMAEN_BitNumber 0x03
#define | ENCMDCOMPL_BitNumber 0x0C
#define | NIEN_BitNumber 0x0D
#define | PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
#define | RWMOD_BitNumber 0x0A
#define | RWSTART_BitNumber 0x08
#define | RWSTOP_BitNumber 0x09
#define | SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
#define | SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
#define | SDIOEN_BitNumber 0x0B
#define | SDIOSUSPEND_BitNumber 0x0B

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

SDIO driver modules.

Define Documentation

#define ATACMD_BitNumber 0x0E

Definition at line 168 of file stm32l1xx_sdio.c.

#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)

Definition at line 199 of file stm32l1xx_sdio.c.

Referenced by SDIO_Init().

#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))

Definition at line 150 of file stm32l1xx_sdio.c.

Referenced by SDIO_ClockCmd().

#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)

Definition at line 148 of file stm32l1xx_sdio.c.

#define CLKEN_BitNumber 0x08

Definition at line 149 of file stm32l1xx_sdio.c.

#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))

Definition at line 169 of file stm32l1xx_sdio.c.

Referenced by SDIO_SendCEATACmd().

#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)

Definition at line 214 of file stm32l1xx_sdio.c.

Referenced by SDIO_SendCommand().

#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))

Definition at line 161 of file stm32l1xx_sdio.c.

Referenced by SDIO_CommandCompletionCmd().

#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))

Definition at line 165 of file stm32l1xx_sdio.c.

Referenced by SDIO_CEATAITCmd().

#define CMD_OFFSET (SDIO_OFFSET + 0x0C)

Definition at line 155 of file stm32l1xx_sdio.c.

#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))

Definition at line 157 of file stm32l1xx_sdio.c.

Referenced by SDIO_SendSDIOSuspendCmd().

#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)

Definition at line 209 of file stm32l1xx_sdio.c.

Referenced by SDIO_DataConfig().

#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))

Definition at line 176 of file stm32l1xx_sdio.c.

Referenced by SDIO_DMACmd().

#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)

Definition at line 174 of file stm32l1xx_sdio.c.

#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))

Definition at line 188 of file stm32l1xx_sdio.c.

Referenced by SDIO_SetSDIOReadWaitMode().

#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))

Definition at line 180 of file stm32l1xx_sdio.c.

Referenced by SDIO_StartSDIOReadWait().

#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))

Definition at line 184 of file stm32l1xx_sdio.c.

Referenced by SDIO_StopSDIOReadWait().

#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))

Definition at line 192 of file stm32l1xx_sdio.c.

Referenced by SDIO_SetSDIOOperation().

#define DMAEN_BitNumber 0x03

Definition at line 175 of file stm32l1xx_sdio.c.

#define ENCMDCOMPL_BitNumber 0x0C

Definition at line 160 of file stm32l1xx_sdio.c.

#define NIEN_BitNumber 0x0D

Definition at line 164 of file stm32l1xx_sdio.c.

#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)

Definition at line 204 of file stm32l1xx_sdio.c.

Referenced by SDIO_GetPowerState().

#define RWMOD_BitNumber 0x0A

Definition at line 187 of file stm32l1xx_sdio.c.

#define RWSTART_BitNumber 0x08

Definition at line 179 of file stm32l1xx_sdio.c.

#define RWSTOP_BitNumber 0x09

Definition at line 183 of file stm32l1xx_sdio.c.

#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)

Definition at line 143 of file stm32l1xx_sdio.c.

#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))

Definition at line 217 of file stm32l1xx_sdio.c.

Referenced by SDIO_GetResponse().

#define SDIOEN_BitNumber 0x0B

Definition at line 191 of file stm32l1xx_sdio.c.

#define SDIOSUSPEND_BitNumber 0x0B

Definition at line 156 of file stm32l1xx_sdio.c.

Function Documentation

void SDIO_CEATAITCmd ( FunctionalState NewState )

Enables or disables the CE-ATA interrupt.

Parameters:
NewState,: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 728 of file stm32l1xx_sdio.c.

References CMD_NIEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_ClearFlag ( uint32_t SDIO_FLAG )

Clears the SDIO's pending flags.

Parameters:
SDIO_FLAG,: specifies the flag to clear. This parameter can be one or a combination of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
  • SDIO_FLAG_CTIMEOUT: Command response timeout.
  • SDIO_FLAG_DTIMEOUT: Data timeout.
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error.
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed).
  • SDIO_FLAG_CMDSENT: Command sent (no response required).
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received.
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
None

Definition at line 886 of file stm32l1xx_sdio.c.

References IS_SDIO_CLEAR_FLAG, and SDIO.

void SDIO_ClearITPendingBit ( uint32_t SDIO_IT )

Clears the SDIO's interrupt pending bits.

Parameters:
SDIO_IT,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
None

Definition at line 961 of file stm32l1xx_sdio.c.

References IS_SDIO_CLEAR_IT, and SDIO.

void SDIO_ClockCmd ( FunctionalState NewState )

Enables or disables the SDIO Clock.

Parameters:
NewState,: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 312 of file stm32l1xx_sdio.c.

References CLKCR_CLKEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_CmdStructInit ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Fills each SDIO_CmdInitStruct member with its default value.

Parameters:
SDIO_CmdInitStruct,: pointer to an SDIO_CmdInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 442 of file stm32l1xx_sdio.c.

References SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Disable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

void SDIO_CommandCompletionCmd ( FunctionalState NewState )

Enables or disables the command completion signal.

Parameters:
NewState,: new state of command completion signal. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 715 of file stm32l1xx_sdio.c.

References CMD_ENCMDCOMPL_BB, and IS_FUNCTIONAL_STATE.

void SDIO_DataConfig ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

Parameters:
SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 509 of file stm32l1xx_sdio.c.

References DCTRL_CLEAR_MASK, IS_SDIO_BLOCK_SIZE, IS_SDIO_DATA_LENGTH, IS_SDIO_DPSM, IS_SDIO_TRANSFER_DIR, IS_SDIO_TRANSFER_MODE, SDIO, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DataInitTypeDef::SDIO_TransferDir, and SDIO_DataInitTypeDef::SDIO_TransferMode.

void SDIO_DataStructInit ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Fills each SDIO_DataInitStruct member with its default value.

Parameters:
SDIO_DataInitStruct,: pointer to an SDIO_DataInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 550 of file stm32l1xx_sdio.c.

References SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_1b, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Disable, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, and SDIO_TransferMode_Block.

void SDIO_DeInit ( void )

Deinitializes the SDIO peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 245 of file stm32l1xx_sdio.c.

References DISABLE, ENABLE, RCC_APB2Periph_SDIO, and RCC_APB2PeriphResetCmd().

void SDIO_DMACmd ( FunctionalState NewState )

Enables or disables the SDIO DMA request.

Parameters:
NewState,: new state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 373 of file stm32l1xx_sdio.c.

References DCTRL_DMAEN_BB, and IS_FUNCTIONAL_STATE.

uint8_t SDIO_GetCommandResponse ( void )

Returns command index of last command for which response received.

Parameters:
None
Return values:
Returns the command index of the last command response received.

Definition at line 457 of file stm32l1xx_sdio.c.

References SDIO.

uint32_t SDIO_GetDataCounter ( void )

Returns number of remaining data bytes to be transferred.

Parameters:
None
Return values:
Number of remaining data bytes to be transferred

Definition at line 566 of file stm32l1xx_sdio.c.

References SDIO.

uint32_t SDIO_GetFIFOCount ( void )

Returns the number of words left to be written to or read from FIFO.

Parameters:
None
Return values:
Remaining number of words.

Definition at line 596 of file stm32l1xx_sdio.c.

References SDIO.

FlagStatus SDIO_GetFlagStatus ( uint32_t SDIO_FLAG )

Checks whether the specified SDIO flag is set or not.

Parameters:
SDIO_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
  • SDIO_FLAG_CTIMEOUT: Command response timeout.
  • SDIO_FLAG_DTIMEOUT: Data timeout.
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error.
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed).
  • SDIO_FLAG_CMDSENT: Command sent (no response required).
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
  • SDIO_FLAG_CMDACT: Command transfer in progress.
  • SDIO_FLAG_TXACT: Data transmit in progress.
  • SDIO_FLAG_RXACT: Data receive in progress.
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full.
  • SDIO_FLAG_RXFIFOF: Receive FIFO full.
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty.
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty.
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO.
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO.
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received.
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
Return values:
The new state of SDIO_FLAG (SET or RESET).

Definition at line 848 of file stm32l1xx_sdio.c.

References IS_SDIO_FLAG, RESET, SDIO, and SET.

ITStatus SDIO_GetITStatus ( uint32_t SDIO_IT )

Checks whether the specified SDIO interrupt has occurred or not.

Parameters:
SDIO_IT,: specifies the SDIO interrupt source to check. This parameter can be one of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
  • SDIO_IT_CMDACT: Command transfer in progress interrupt.
  • SDIO_IT_TXACT: Data transmit in progress interrupt.
  • SDIO_IT_RXACT: Data receive in progress interrupt.
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
Return values:
The new state of SDIO_IT (SET or RESET).

Definition at line 925 of file stm32l1xx_sdio.c.

References IS_SDIO_GET_IT, RESET, SDIO, and SET.

uint32_t SDIO_GetPowerState ( void )

Gets the power status of the controller.

Parameters:
None
Return values:
Power status of the controller. The returned value can be one of the following:

  • 0x00: Power OFF
  • 0x02: Power UP
  • 0x03: Power ON

Definition at line 345 of file stm32l1xx_sdio.c.

References PWR_PWRCTRL_MASK, and SDIO.

uint32_t SDIO_GetResponse ( uint32_t SDIO_RESP )

Returns response received from the card for the last command.

Parameters:
SDIO_RESP,: Specifies the SDIO response register. This parameter can be one of the following values:

  • SDIO_RESP1: Response Register 1.
  • SDIO_RESP2: Response Register 2.
  • SDIO_RESP3: Response Register 3.
  • SDIO_RESP4: Response Register 4.
Return values:
The Corresponding response register value.

Definition at line 472 of file stm32l1xx_sdio.c.

References IS_SDIO_RESP, and SDIO_RESP_ADDR.

void SDIO_Init ( SDIO_InitTypeDef * SDIO_InitStruct )

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

Parameters:
SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
Return values:
None

Definition at line 258 of file stm32l1xx_sdio.c.

References CLKCR_CLEAR_MASK, IS_SDIO_BUS_WIDE, IS_SDIO_CLOCK_BYPASS, IS_SDIO_CLOCK_EDGE, IS_SDIO_CLOCK_POWER_SAVE, IS_SDIO_HARDWARE_FLOW_CONTROL, SDIO, SDIO_InitTypeDef::SDIO_BusWide, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_InitTypeDef::SDIO_ClockPowerSave, and SDIO_InitTypeDef::SDIO_HardwareFlowControl.

void SDIO_ITConfig | ( | uint32_t | SDIO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SDIO interrupts.

Parameters:
SDIO_IT,: specifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt.
  • SDIO_IT_DTIMEOUT: Data timeout interrupt.
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt.
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
  • SDIO_IT_CMDACT: Command transfer in progress interrupt.
  • SDIO_IT_TXACT: Data transmit in progress interrupt.
  • SDIO_IT_RXACT: Data receive in progress interrupt.
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
NewState,: new state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 799 of file stm32l1xx_sdio.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_SDIO_IT, and SDIO.

uint32_t SDIO_ReadData ( void )

Read one data word from Rx FIFO.

Parameters:
None
Return values:
Data received

Definition at line 576 of file stm32l1xx_sdio.c.

References SDIO.

void SDIO_SendCEATACmd ( FunctionalState NewState )

Sends CE-ATA command (CMD61).

Parameters:
NewState,: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 741 of file stm32l1xx_sdio.c.

References CMD_ATACMD_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SendCommand ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

Parameters:
SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 406 of file stm32l1xx_sdio.c.

References CMD_CLEAR_MASK, IS_SDIO_CMD_INDEX, IS_SDIO_CPSM, IS_SDIO_RESPONSE, IS_SDIO_WAIT, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CmdInitTypeDef::SDIO_Response, and SDIO_CmdInitTypeDef::SDIO_Wait.

void SDIO_SendSDIOSuspendCmd ( FunctionalState NewState )

Enables or disables the SD I/O Mode suspend command sending.

Parameters:
NewState,: new state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 683 of file stm32l1xx_sdio.c.

References CMD_SDIOSUSPEND_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetPowerState ( uint32_t SDIO_PowerState )

Sets the power status of the controller.

Parameters:
SDIO_PowerState,: new state of the Power state. This parameter can be one of the following values:

  • SDIO_PowerState_OFF: SDIO Power OFF.
  • SDIO_PowerState_ON: SDIO Power ON.
Return values:
None

Definition at line 328 of file stm32l1xx_sdio.c.

References IS_SDIO_POWER_STATE, and SDIO.

void SDIO_SetSDIOOperation ( FunctionalState NewState )

Enables or disables the SD I/O Mode Operation.

Parameters:
NewState,: new state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 669 of file stm32l1xx_sdio.c.

References DCTRL_SDIOEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetSDIOReadWaitMode ( uint32_t SDIO_ReadWaitMode )

Sets one of the two options of inserting read wait interval.

Parameters:
SDIO_ReadWaitMode,: SD I/O Read Wait operation mode. This parametre can be:

  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.
Return values:
None

Definition at line 655 of file stm32l1xx_sdio.c.

References DCTRL_RWMOD_BB, and IS_SDIO_READWAIT_MODE.

void SDIO_StartSDIOReadWait ( FunctionalState NewState )

Starts the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 625 of file stm32l1xx_sdio.c.

References DCTRL_RWSTART_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StopSDIOReadWait ( FunctionalState NewState )

Stops the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 639 of file stm32l1xx_sdio.c.

References DCTRL_RWSTOP_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StructInit ( SDIO_InitTypeDef * SDIO_InitStruct )

Fills each SDIO_InitStruct member with its default value.

Parameters:
SDIO_InitStruct,: pointer to an SDIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 296 of file stm32l1xx_sdio.c.

References SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, and SDIO_HardwareFlowControl_Disable.

void SDIO_WriteData ( uint32_t Data )

Write one data word to Tx FIFO.

Parameters:
Data,: 32-bit data word to write.
Return values:
None

Definition at line 586 of file stm32l1xx_sdio.c.

References SDIO.


STM32L1xx Standard Peripherals Firmware Library: SDIO_CmdInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_CmdInitTypeDef Struct Reference
SDIO

#include <stm32l1xx_sdio.h>

Data Fields

uint32_t | SDIO_Argument
uint32_t | SDIO_CmdIndex
uint32_t | SDIO_CPSM
uint32_t | SDIO_Response
uint32_t | SDIO_Wait

Detailed Description

Definition at line 71 of file stm32l1xx_sdio.h.

Field Documentation

uint32_t SDIO_CmdInitTypeDef::SDIO_Argument

Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register

Definition at line 73 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_CmdIndex

Specifies the SDIO command index. It must be lower than 0x40.

Definition at line 78 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_CPSM

Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of SDIO_CPSM_State

Definition at line 86 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_Response

Specifies the SDIO response type. This parameter can be a value of SDIO_Response_Type

Definition at line 80 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_Wait

Specifies whether SDIO wait-for-interrupt request is enabled or disabled. This parameter can be a value of SDIO_Wait_Interrupt_State

Definition at line 83 of file stm32l1xx_sdio.h.

Referenced by SDIO_CmdStructInit(), and SDIO_SendCommand().

The documentation for this struct was generated from the following file:
  • stm32l1xx_sdio.h


STM32L1xx Standard Peripherals Firmware Library: SDIO_DataInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_DataInitTypeDef Struct Reference
SDIO

#include <stm32l1xx_sdio.h>

Data Fields

uint32_t | SDIO_DataBlockSize
uint32_t | SDIO_DataLength
uint32_t | SDIO_DataTimeOut
uint32_t | SDIO_DPSM
uint32_t | SDIO_TransferDir
uint32_t | SDIO_TransferMode

Detailed Description

Definition at line 91 of file stm32l1xx_sdio.h.

Field Documentation

uint32_t SDIO_DataInitTypeDef::SDIO_DataBlockSize

Specifies the data block size for block transfer. This parameter can be a value of SDIO_Data_Block_Size

Definition at line 97 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DataLength

Specifies the number of data bytes to be transferred.

Definition at line 95 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DataTimeOut

Specifies the data timeout period in card bus clock periods.

Definition at line 93 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DPSM

Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of SDIO_DPSM_State

Definition at line 107 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_TransferDir

Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of SDIO_Transfer_Direction

Definition at line 100 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_TransferMode

Specifies whether data transfer is in stream or block mode. This parameter can be a value of SDIO_Transfer_Type

Definition at line 104 of file stm32l1xx_sdio.h.

Referenced by SDIO_DataConfig(), and SDIO_DataStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_sdio.h


STM32L1xx Standard Peripherals Firmware Library: SDIO_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_InitTypeDef Struct Reference
SDIO

#include <stm32l1xx_sdio.h>

Data Fields

uint32_t | SDIO_BusWide
uint32_t | SDIO_ClockBypass
uint8_t | SDIO_ClockDiv
uint32_t | SDIO_ClockEdge
uint32_t | SDIO_ClockPowerSave
uint32_t | SDIO_HardwareFlowControl

Detailed Description

Definition at line 47 of file stm32l1xx_sdio.h.

Field Documentation

uint32_t SDIO_InitTypeDef::SDIO_BusWide

Specifies the SDIO bus width. This parameter can be a value of SDIO_Bus_Wide

Definition at line 60 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockBypass

Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of SDIO_Clock_Bypass

Definition at line 52 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

uint8_t SDIO_InitTypeDef::SDIO_ClockDiv

Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF.

Definition at line 66 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockEdge

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SDIO_Clock_Edge

Definition at line 49 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockPowerSave

Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of SDIO_Clock_Power_Save

Definition at line 56 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_HardwareFlowControl

Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of SDIO_Hardware_Flow_Control

Definition at line 63 of file stm32l1xx_sdio.h.

Referenced by SDIO_Init(), and SDIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_sdio.h


STM32L1xx Standard Peripherals Firmware Library: SPI_data_direction

Defines

SPI_data_direction

SPI_Exported_Constants

Defines

#define | IS_SPI_DIRECTION_MODE(MODE)
#define | SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define | SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define | SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define | SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)

Define Documentation

#define IS_SPI_DIRECTION_MODE ( MODE )
Value:
(((MODE) == SPI_Direction_2Lines_FullDuplex) || \
                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
                                     ((MODE) == SPI_Direction_1Line_Rx) || \
                                     ((MODE) == SPI_Direction_1Line_Tx))

Definition at line 130 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)

Definition at line 128 of file stm32l1xx_spi.h.

#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)

Definition at line 129 of file stm32l1xx_spi.h.

#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)

Definition at line 126 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().

#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)

Definition at line 127 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_mode

Defines

SPI_mode

SPI_Exported_Constants

Defines

#define | IS_SPI_MODE(MODE)
#define | SPI_Mode_Master ((uint16_t)0x0104)
#define | SPI_Mode_Slave ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_Mode_Master) || \
                           ((MODE) == SPI_Mode_Slave))

Definition at line 144 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_Mode_Master ((uint16_t)0x0104)

Definition at line 142 of file stm32l1xx_spi.h.

#define SPI_Mode_Slave ((uint16_t)0x0000)

Definition at line 143 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().


STM32L1xx Standard Peripherals Firmware Library: SPI_data_size

Defines

SPI_data_size

SPI_Exported_Constants

Defines

#define | IS_SPI_DATASIZE(DATASIZE)
#define | SPI_DataSize_16b ((uint16_t)0x0800)
#define | SPI_DataSize_8b ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DataSize_16b) || \
                                   ((DATASIZE) == SPI_DataSize_8b))

Definition at line 156 of file stm32l1xx_spi.h.

Referenced by SPI_DataSizeConfig(), and SPI_Init().

#define SPI_DataSize_16b ((uint16_t)0x0800)

Definition at line 154 of file stm32l1xx_spi.h.

Referenced by SPI_DataSizeConfig().

#define SPI_DataSize_8b ((uint16_t)0x0000)

Definition at line 155 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().


STM32L1xx Standard Peripherals Firmware Library: SPI_Clock_Polarity

Defines

SPI_Clock_Polarity

SPI_Exported_Constants

Defines

#define | IS_SPI_CPOL(CPOL)
#define | SPI_CPOL_High ((uint16_t)0x0002)
#define | SPI_CPOL_Low ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_CPOL_Low) || \
                           ((CPOL) == SPI_CPOL_High))

Definition at line 168 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_CPOL_High ((uint16_t)0x0002)

Definition at line 167 of file stm32l1xx_spi.h.

#define SPI_CPOL_Low ((uint16_t)0x0000)

Definition at line 166 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().


STM32L1xx Standard Peripherals Firmware Library: SPI_Clock_Phase

Defines

SPI_Clock_Phase

SPI_Exported_Constants

Defines

#define | IS_SPI_CPHA(CPHA)
#define | SPI_CPHA_1Edge ((uint16_t)0x0000)
#define | SPI_CPHA_2Edge ((uint16_t)0x0001)

Define Documentation

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_CPHA_1Edge) || \
                           ((CPHA) == SPI_CPHA_2Edge))

Definition at line 180 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_CPHA_1Edge ((uint16_t)0x0000)

Definition at line 178 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().

#define SPI_CPHA_2Edge ((uint16_t)0x0001)

Definition at line 179 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_Slave_Select_management

Defines

SPI_Slave_Select_management

SPI_Exported_Constants

Defines

#define | IS_SPI_NSS(NSS)
#define | SPI_NSS_Hard ((uint16_t)0x0000)
#define | SPI_NSS_Soft ((uint16_t)0x0200)

Define Documentation

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_Soft) || \
                         ((NSS) == SPI_NSS_Hard))

Definition at line 192 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_NSS_Hard ((uint16_t)0x0000)

Definition at line 191 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().

#define SPI_NSS_Soft ((uint16_t)0x0200)

Definition at line 190 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_BaudRate_Prescaler

Defines

SPI_BaudRate_Prescaler

SPI_Exported_Constants

Defines

#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define | SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define | SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define | SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define | SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define | SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define | SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define | SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BaudRatePrescaler_2) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))

Definition at line 210 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)

Definition at line 208 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)

Definition at line 205 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)

Definition at line 202 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().

#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)

Definition at line 209 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)

Definition at line 206 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)

Definition at line 203 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)

Definition at line 207 of file stm32l1xx_spi.h.

#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)

Definition at line 204 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_MSB_LSB_transmission

Defines

SPI_MSB_LSB_transmission

SPI_Exported_Constants

Defines

#define | IS_SPI_FIRST_BIT(BIT)
#define | SPI_FirstBit_LSB ((uint16_t)0x0080)
#define | SPI_FirstBit_MSB ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FirstBit_MSB) || \
                               ((BIT) == SPI_FirstBit_LSB))

Definition at line 228 of file stm32l1xx_spi.h.

Referenced by SPI_Init().

#define SPI_FirstBit_LSB ((uint16_t)0x0080)

Definition at line 227 of file stm32l1xx_spi.h.

#define SPI_FirstBit_MSB ((uint16_t)0x0000)

Definition at line 226 of file stm32l1xx_spi.h.

Referenced by SPI_StructInit().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Mode

Defines

SPI_I2S_Mode

SPI_Exported_Constants

Defines

#define | I2S_Mode_MasterRx ((uint16_t)0x0300)
#define | I2S_Mode_MasterTx ((uint16_t)0x0200)
#define | I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define | I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define | IS_I2S_MODE(MODE)

Define Documentation

#define I2S_Mode_MasterRx ((uint16_t)0x0300)

Definition at line 241 of file stm32l1xx_spi.h.

#define I2S_Mode_MasterTx ((uint16_t)0x0200)

Definition at line 240 of file stm32l1xx_spi.h.

#define I2S_Mode_SlaveRx ((uint16_t)0x0100)

Definition at line 239 of file stm32l1xx_spi.h.

#define I2S_Mode_SlaveTx ((uint16_t)0x0000)

Definition at line 238 of file stm32l1xx_spi.h.

Referenced by I2S_StructInit().

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_Mode_SlaveTx) || \
                           ((MODE) == I2S_Mode_SlaveRx) || \
                           ((MODE) == I2S_Mode_MasterTx)|| \
                           ((MODE) == I2S_Mode_MasterRx))

Definition at line 242 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Standard

Defines

SPI_I2S_Standard

SPI_Exported_Constants

Defines

#define | I2S_Standard_LSB ((uint16_t)0x0020)
#define | I2S_Standard_MSB ((uint16_t)0x0010)
#define | I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define | I2S_Standard_PCMShort ((uint16_t)0x0030)
#define | I2S_Standard_Phillips ((uint16_t)0x0000)
#define | IS_I2S_STANDARD(STANDARD)

Define Documentation

#define I2S_Standard_LSB ((uint16_t)0x0020)

Definition at line 257 of file stm32l1xx_spi.h.

#define I2S_Standard_MSB ((uint16_t)0x0010)

Definition at line 256 of file stm32l1xx_spi.h.

#define I2S_Standard_PCMLong ((uint16_t)0x00B0)

Definition at line 259 of file stm32l1xx_spi.h.

#define I2S_Standard_PCMShort ((uint16_t)0x0030)

Definition at line 258 of file stm32l1xx_spi.h.

#define I2S_Standard_Phillips ((uint16_t)0x0000)

Definition at line 255 of file stm32l1xx_spi.h.

Referenced by I2S_StructInit().

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_Standard_Phillips) || \
                                   ((STANDARD) == I2S_Standard_MSB) || \
                                   ((STANDARD) == I2S_Standard_LSB) || \
                                   ((STANDARD) == I2S_Standard_PCMShort) || \
                                   ((STANDARD) == I2S_Standard_PCMLong))

Definition at line 260 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Data_Format

Defines

SPI_I2S_Data_Format

SPI_Exported_Constants

Defines

#define | I2S_DataFormat_16b ((uint16_t)0x0000)
#define | I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define | I2S_DataFormat_24b ((uint16_t)0x0003)
#define | I2S_DataFormat_32b ((uint16_t)0x0005)
#define | IS_I2S_DATA_FORMAT(FORMAT)

Define Documentation

#define I2S_DataFormat_16b ((uint16_t)0x0000)

Definition at line 273 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

#define I2S_DataFormat_16bextended ((uint16_t)0x0001)

Definition at line 274 of file stm32l1xx_spi.h.

#define I2S_DataFormat_24b ((uint16_t)0x0003)

Definition at line 275 of file stm32l1xx_spi.h.

#define I2S_DataFormat_32b ((uint16_t)0x0005)

Definition at line 276 of file stm32l1xx_spi.h.

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DataFormat_16b) || \
                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
                                    ((FORMAT) == I2S_DataFormat_24b) || \
                                    ((FORMAT) == I2S_DataFormat_32b))

Definition at line 277 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_MCLK_Output

Defines

SPI_I2S_MCLK_Output

SPI_Exported_Constants

Defines

#define | I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define | I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)

Define Documentation

#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)

Definition at line 290 of file stm32l1xx_spi.h.

Referenced by I2S_StructInit().

#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)

Definition at line 289 of file stm32l1xx_spi.h.

Referenced by I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOutput_Enable) || \
                                    ((OUTPUT) == I2S_MCLKOutput_Disable))

Definition at line 291 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Audio_Frequency

Defines

SPI_I2S_Audio_Frequency

SPI_Exported_Constants

Defines

#define | I2S_AudioFreq_11k ((uint32_t)11025)
#define | I2S_AudioFreq_16k ((uint32_t)16000)
#define | I2S_AudioFreq_192k ((uint32_t)192000)
#define | I2S_AudioFreq_22k ((uint32_t)22050)
#define | I2S_AudioFreq_32k ((uint32_t)32000)
#define | I2S_AudioFreq_44k ((uint32_t)44100)
#define | I2S_AudioFreq_48k ((uint32_t)48000)
#define | I2S_AudioFreq_8k ((uint32_t)8000)
#define | I2S_AudioFreq_96k ((uint32_t)96000)
#define | I2S_AudioFreq_Default ((uint32_t)2)
#define | IS_I2S_AUDIO_FREQ(FREQ)

Define Documentation

#define I2S_AudioFreq_11k ((uint32_t)11025)

Definition at line 308 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_16k ((uint32_t)16000)

Definition at line 307 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_192k ((uint32_t)192000)

Definition at line 301 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_22k ((uint32_t)22050)

Definition at line 306 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_32k ((uint32_t)32000)

Definition at line 305 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_44k ((uint32_t)44100)

Definition at line 304 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_48k ((uint32_t)48000)

Definition at line 303 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_8k ((uint32_t)8000)

Definition at line 309 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_96k ((uint32_t)96000)

Definition at line 302 of file stm32l1xx_spi.h.

#define I2S_AudioFreq_Default ((uint32_t)2)

Definition at line 310 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AudioFreq_8k) && \
                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
                                 ((FREQ) == I2S_AudioFreq_Default))

Definition at line 312 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Clock_Polarity

Defines

SPI_I2S_Clock_Polarity

SPI_Exported_Constants

Defines

#define | I2S_CPOL_High ((uint16_t)0x0008)
#define | I2S_CPOL_Low ((uint16_t)0x0000)
#define | IS_I2S_CPOL(CPOL)

Define Documentation

#define I2S_CPOL_High ((uint16_t)0x0008)

Definition at line 324 of file stm32l1xx_spi.h.

#define I2S_CPOL_Low ((uint16_t)0x0000)

Definition at line 323 of file stm32l1xx_spi.h.

Referenced by I2S_StructInit().

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_Low) || \
                           ((CPOL) == I2S_CPOL_High))

Definition at line 325 of file stm32l1xx_spi.h.

Referenced by I2S_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_DMA_transfer_requests

Defines

SPI_I2S_DMA_transfer_requests

SPI_Exported_Constants

Defines

#define | IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
#define | SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define | SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)

Define Documentation

#define IS_SPI_I2S_DMAREQ ( DMAREQ ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))

Definition at line 337 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_DMACmd().

#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)

Definition at line 336 of file stm32l1xx_spi.h.

#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)

Definition at line 335 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_NSS_internal_software_management

Defines

SPI_NSS_internal_software_management

SPI_Exported_Constants

Defines

#define | IS_SPI_NSS_INTERNAL(INTERNAL)
#define | SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define | SPI_NSSInternalSoft_Set ((uint16_t)0x0100)

Define Documentation

#define IS_SPI_NSS_INTERNAL ( INTERNAL )
Value:
(((INTERNAL) == SPI_NSSInternalSoft_Set) || \
                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))

Definition at line 348 of file stm32l1xx_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().

#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)

Definition at line 347 of file stm32l1xx_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().

#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)

Definition at line 346 of file stm32l1xx_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().


STM32L1xx Standard Peripherals Firmware Library: SPI_CRC_Transmit_Receive

Defines

SPI_CRC_Transmit_Receive

SPI_Exported_Constants

Defines

#define | IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
#define | SPI_CRC_Rx ((uint8_t)0x01)
#define | SPI_CRC_Tx ((uint8_t)0x00)

Define Documentation

#define IS_SPI_CRC ( CRC ) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))

Definition at line 360 of file stm32l1xx_spi.h.

Referenced by SPI_GetCRC().

#define SPI_CRC_Rx ((uint8_t)0x01)

Definition at line 359 of file stm32l1xx_spi.h.

Referenced by SPI_GetCRC().

#define SPI_CRC_Tx ((uint8_t)0x00)

Definition at line 358 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_direction_transmit_receive

Defines

SPI_direction_transmit_receive

SPI_Exported_Constants

Defines

#define | IS_SPI_DIRECTION(DIRECTION)
#define | SPI_Direction_Rx ((uint16_t)0xBFFF)
#define | SPI_Direction_Tx ((uint16_t)0x4000)

Define Documentation

#define IS_SPI_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == SPI_Direction_Rx) || \
                                     ((DIRECTION) == SPI_Direction_Tx))

Definition at line 371 of file stm32l1xx_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_Direction_Rx ((uint16_t)0xBFFF)

Definition at line 369 of file stm32l1xx_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_Direction_Tx ((uint16_t)0x4000)

Definition at line 370 of file stm32l1xx_spi.h.

Referenced by SPI_BiDirectionalLineConfig().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_interrupts_definition

Defines

SPI_I2S_interrupts_definition

SPI_Exported_Constants

Defines

#define | I2S_IT_UDR ((uint8_t)0x53)
#define | IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define | IS_SPI_I2S_CONFIG_IT(IT)
#define | IS_SPI_I2S_GET_IT(IT)
#define | SPI_I2S_IT_ERR ((uint8_t)0x50)
#define | SPI_I2S_IT_FRE ((uint8_t)0x58)
#define | SPI_I2S_IT_OVR ((uint8_t)0x56)
#define | SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define | SPI_I2S_IT_TXE ((uint8_t)0x71)
#define | SPI_IT_CRCERR ((uint8_t)0x54)
#define | SPI_IT_MODF ((uint8_t)0x55)

Define Documentation

#define I2S_IT_UDR ((uint8_t)0x53)

Definition at line 384 of file stm32l1xx_spi.h.

#define IS_SPI_I2S_CLEAR_IT ( IT ) (((IT) == SPI_IT_CRCERR))

Definition at line 395 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_ClearITPendingBit().

#define IS_SPI_I2S_CONFIG_IT ( IT )
Value:
(((IT) == SPI_I2S_IT_TXE) || \
                                  ((IT) == SPI_I2S_IT_RXNE) || \
                                  ((IT) == SPI_I2S_IT_ERR))

Definition at line 387 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_ITConfig().

#define IS_SPI_I2S_GET_IT ( IT )
Value:
(((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
                               ((IT) == SPI_IT_CRCERR)   || ((IT) == SPI_IT_MODF) || \
                               ((IT) == SPI_I2S_IT_OVR)  || ((IT) == I2S_IT_UDR) ||\
                               ((IT) == SPI_I2S_IT_FRE))

Definition at line 397 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_GetITStatus().

#define SPI_I2S_IT_ERR ((uint8_t)0x50)

Definition at line 383 of file stm32l1xx_spi.h.

#define SPI_I2S_IT_FRE ((uint8_t)0x58)

Definition at line 385 of file stm32l1xx_spi.h.

#define SPI_I2S_IT_OVR ((uint8_t)0x56)

Definition at line 391 of file stm32l1xx_spi.h.

#define SPI_I2S_IT_RXNE ((uint8_t)0x60)

Definition at line 382 of file stm32l1xx_spi.h.

#define SPI_I2S_IT_TXE ((uint8_t)0x71)

Definition at line 381 of file stm32l1xx_spi.h.

#define SPI_IT_CRCERR ((uint8_t)0x54)

Definition at line 393 of file stm32l1xx_spi.h.

#define SPI_IT_MODF ((uint8_t)0x55)

Definition at line 392 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_flags_definition

Defines

SPI_I2S_flags_definition

SPI_Exported_Constants

Defines

#define | I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define | I2S_FLAG_UDR ((uint16_t)0x0008)
#define | IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define | IS_SPI_I2S_GET_FLAG(FLAG)
#define | SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define | SPI_FLAG_MODF ((uint16_t)0x0020)
#define | SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define | SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
#define | SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define | SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define | SPI_I2S_FLAG_TXE ((uint16_t)0x0002)

Define Documentation

#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)

Definition at line 411 of file stm32l1xx_spi.h.

#define I2S_FLAG_UDR ((uint16_t)0x0008)

Definition at line 412 of file stm32l1xx_spi.h.

#define IS_SPI_I2S_CLEAR_FLAG ( FLAG ) (((FLAG) == SPI_FLAG_CRCERR))

Definition at line 419 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_ClearFlag().

#define IS_SPI_I2S_GET_FLAG ( FLAG )
Value:
(((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
                                   ((FLAG) == SPI_I2S_FLAG_FRE))

Definition at line 420 of file stm32l1xx_spi.h.

Referenced by SPI_I2S_GetFlagStatus().

#define SPI_FLAG_CRCERR ((uint16_t)0x0010)

Definition at line 413 of file stm32l1xx_spi.h.

#define SPI_FLAG_MODF ((uint16_t)0x0020)

Definition at line 414 of file stm32l1xx_spi.h.

#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)

Definition at line 416 of file stm32l1xx_spi.h.

#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)

Definition at line 417 of file stm32l1xx_spi.h.

#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)

Definition at line 415 of file stm32l1xx_spi.h.

#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)

Definition at line 409 of file stm32l1xx_spi.h.

#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)

Definition at line 410 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_CRC_polynomial

Defines

SPI_CRC_polynomial

SPI_Exported_Constants

Defines

#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)

Define Documentation

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) ((POLYNOMIAL) >= 0x1)

Definition at line 433 of file stm32l1xx_spi.h.

Referenced by SPI_Init().


STM32L1xx Standard Peripherals Firmware Library: SPI_I2S_Legacy

Defines

SPI_I2S_Legacy

SPI_Exported_Constants

Defines

#define | SPI_ClearFlag SPI_I2S_ClearFlag
#define | SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
#define | SPI_DeInit SPI_I2S_DeInit
#define | SPI_DMACmd SPI_I2S_DMACmd
#define | SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
#define | SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
#define | SPI_FLAG_BSY SPI_I2S_FLAG_BSY
#define | SPI_FLAG_OVR SPI_I2S_FLAG_OVR
#define | SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
#define | SPI_FLAG_TXE SPI_I2S_FLAG_TXE
#define | SPI_GetFlagStatus SPI_I2S_GetFlagStatus
#define | SPI_GetITStatus SPI_I2S_GetITStatus
#define | SPI_IT_ERR SPI_I2S_IT_ERR
#define | SPI_IT_OVR SPI_I2S_IT_OVR
#define | SPI_IT_RXNE SPI_I2S_IT_RXNE
#define | SPI_IT_TXE SPI_I2S_IT_TXE
#define | SPI_ITConfig SPI_I2S_ITConfig
#define | SPI_ReceiveData SPI_I2S_ReceiveData
#define | SPI_SendData SPI_I2S_SendData

Define Documentation

#define SPI_ClearFlag SPI_I2S_ClearFlag

Definition at line 458 of file stm32l1xx_spi.h.

#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit

Definition at line 460 of file stm32l1xx_spi.h.

#define SPI_DeInit SPI_I2S_DeInit

Definition at line 452 of file stm32l1xx_spi.h.

#define SPI_DMACmd SPI_I2S_DMACmd

Definition at line 454 of file stm32l1xx_spi.h.

#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx

Definition at line 443 of file stm32l1xx_spi.h.

#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx

Definition at line 442 of file stm32l1xx_spi.h.

#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY

Definition at line 451 of file stm32l1xx_spi.h.

#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR

Definition at line 450 of file stm32l1xx_spi.h.

#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE

Definition at line 448 of file stm32l1xx_spi.h.

#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE

Definition at line 449 of file stm32l1xx_spi.h.

#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus

Definition at line 457 of file stm32l1xx_spi.h.

#define SPI_GetITStatus SPI_I2S_GetITStatus

Definition at line 459 of file stm32l1xx_spi.h.

#define SPI_IT_ERR SPI_I2S_IT_ERR

Definition at line 446 of file stm32l1xx_spi.h.

#define SPI_IT_OVR SPI_I2S_IT_OVR

Definition at line 447 of file stm32l1xx_spi.h.

#define SPI_IT_RXNE SPI_I2S_IT_RXNE

Definition at line 445 of file stm32l1xx_spi.h.

#define SPI_IT_TXE SPI_I2S_IT_TXE

Definition at line 444 of file stm32l1xx_spi.h.

#define SPI_ITConfig SPI_I2S_ITConfig

Definition at line 453 of file stm32l1xx_spi.h.

#define SPI_ReceiveData SPI_I2S_ReceiveData

Definition at line 456 of file stm32l1xx_spi.h.

#define SPI_SendData SPI_I2S_SendData

Definition at line 455 of file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: SPI_Exported_Constants

Modules | Defines

SPI_Exported_Constants

SPI

Modules

SPI_data_direction
SPI_mode
SPI_data_size
SPI_Clock_Polarity
SPI_Clock_Phase
SPI_Slave_Select_management
SPI_BaudRate_Prescaler
SPI_MSB_LSB_transmission
SPI_I2S_Mode
SPI_I2S_Standard
SPI_I2S_Data_Format
SPI_I2S_MCLK_Output
SPI_I2S_Audio_Frequency
SPI_I2S_Clock_Polarity
SPI_I2S_DMA_transfer_requests
SPI_NSS_internal_software_management
SPI_CRC_Transmit_Receive
SPI_direction_transmit_receive
SPI_I2S_interrupts_definition
SPI_I2S_flags_definition
SPI_CRC_polynomial
SPI_I2S_Legacy

Defines

#define | IS_SPI_23_PERIPH(PERIPH)
#define | IS_SPI_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_SPI_23_PERIPH ( PERIPH )
Value:
(((PERIPH) == SPI2) || \
                                   ((PERIPH) == SPI3))

Definition at line 119 of file stm32l1xx_spi.h.

Referenced by I2S_Cmd(), and I2S_Init().

#define IS_SPI_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == SPI1) || \
                                   ((PERIPH) == SPI2) || \
                                   ((PERIPH) == SPI3))

Definition at line 116 of file stm32l1xx_spi.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRC(), SPI_Cmd(), SPI_DataSizeConfig(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_I2S_ClearFlag(), SPI_I2S_ClearITPendingBit(), SPI_I2S_DeInit(), SPI_I2S_DMACmd(), SPI_I2S_GetFlagStatus(), SPI_I2S_GetITStatus(), SPI_I2S_ITConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_NSSInternalSoftwareConfig(), SPI_SSOutputCmd(), and SPI_TransmitCRC().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

SPI_Private_Functions

Initialization and Configuration functions. More...

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and Configuration functions #####
 ===============================================================================
    [..] This section provides a set of functions allowing to initialize the SPI
         Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
         Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
    [..] The SPI_Init() function follows the SPI configuration procedures for
         Master mode and Slave mode (details for these procedures are available
         in reference manual (RM0038)).

Function Documentation

void I2S_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral (in I2S mode).

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 426 of file stm32l1xx_spi.c.

References DISABLE, SPI_TypeDef::I2SCFGR, IS_FUNCTIONAL_STATE, IS_SPI_23_PERIPH, and SPI_I2SCFGR_I2SE.

void I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStruct,: pointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
Note:
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead.
Return values:
None

Definition at line 244 of file stm32l1xx_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Enable, I2S_InitTypeDef::I2S_Mode, I2S_InitTypeDef::I2S_Standard, SPI_TypeDef::I2SCFGR, I2SCFGR_CLEAR_Mask, SPI_TypeDef::I2SPR, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, IS_SPI_23_PERIPH, RCC_GetClocksFreq(), SPI_I2SCFGR_I2SMOD, and RCC_ClocksTypeDef::SYSCLK_Frequency.

void I2S_StructInit ( I2S_InitTypeDef * I2S_InitStruct )

Fills each I2S_InitStruct member with its default value.

Parameters:
I2S_InitStruct,: pointer to a I2S_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 373 of file stm32l1xx_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_SlaveTx, I2S_InitTypeDef::I2S_Standard, and I2S_Standard_Phillips.

void SPI_BiDirectionalLineConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_Direction
 | ) |  |

Selects the data transfer direction in bidirectional mode for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_Direction,: specifies the data transfer direction in bidirectional mode. This parameter can be one of the following values:

  • SPI_Direction_Tx: Selects Tx transmission direction.
  • SPI_Direction_Rx: Selects Rx receive direction.
Return values:
None

Definition at line 473 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DIRECTION, SPI_Direction_Rx, and SPI_Direction_Tx.

void SPI_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 402 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR1_SPE.

void SPI_DataSizeConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_DataSize
 | ) |  |

Configures the data size for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_DataSize,: specifies the SPI data size. This parameter can be one of the following values:

  • SPI_DataSize_16b: Set data frame format to 16bit.
  • SPI_DataSize_8b: Set data frame format to 8bit.
Return values:
None.

Definition at line 453 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DATASIZE, and SPI_DataSize_16b.

void SPI_I2S_DeInit ( SPI_TypeDef * SPIx )

Deinitializes the SPIx peripheral registers to their default reset values.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Return values:
None

Definition at line 145 of file stm32l1xx_spi.c.

References DISABLE, ENABLE, IS_SPI_ALL_PERIPH, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_SPI1, RCC_APB2PeriphResetCmd(), SPI1, SPI2, and SPI3.

void SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
Return values:
None

Definition at line 184 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, CR1_CLEAR_MASK, SPI_TypeDef::CRCPR, SPI_TypeDef::I2SCFGR, IS_SPI_ALL_PERIPH, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION_MODE, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_InitTypeDef::SPI_CPHA, SPI_InitTypeDef::SPI_CPOL, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_InitTypeDef::SPI_Direction, SPI_InitTypeDef::SPI_FirstBit, SPI_I2SCFGR_I2SMOD, SPI_InitTypeDef::SPI_Mode, and SPI_InitTypeDef::SPI_NSS.

void SPI_NSSInternalSoftwareConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_NSSInternalSoft
 | ) |  |

Configures internally by software the NSS pin for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_NSSInternalSoft,: specifies the SPI NSS internal state. This parameter can be one of the following values:

  • SPI_NSSInternalSoft_Set: Set NSS pin internally.
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally.
Return values:
None

Definition at line 499 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_NSS_INTERNAL, SPI_NSSInternalSoft_Reset, and SPI_NSSInternalSoft_Set.

void SPI_SSOutputCmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SS output for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 523 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR2_SSOE.

void SPI_StructInit ( SPI_InitTypeDef * SPI_InitStruct )

Fills each SPI_InitStruct member with its default value.

Parameters:
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 345 of file stm32l1xx_spi.c.

References SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Hard.


STM32L1xx Standard Peripherals Firmware Library: Data transfers functions

Functions

Data transfers functions

SPI_Private_Functions

Data transfers functions. More...

Functions

uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.

Detailed Description

Data transfers functions.

 ===============================================================================
                    ##### Data transfers functions #####
 ===============================================================================
....[..] This section provides a set of functions allowing to manage the SPI data
         transfers.
....[..] In reception, data are received and then stored into an internal Rx buffer
         while In transmission, data are first stored into an internal Tx buffer
         before being transmitted.
....[..] The read access of the SPI_DR register can be done using the
         SPI_I2S_ReceiveData() function and returns the Rx buffered value.
         Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData()
         function and stores the written data into Tx buffer.

Function Documentation

uint16_t SPI_I2S_ReceiveData ( SPI_TypeDef * SPIx )

Returns the most recent received data by the SPIx/I2Sx peripheral.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Return values:
The value of the received data.

Definition at line 571 of file stm32l1xx_spi.c.

References SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

void SPI_I2S_SendData | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | Data
 | ) |  |

Transmits a Data through the SPIx/I2Sx peripheral.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Data,: Data to be transmitted.
Return values:
None

Definition at line 587 of file stm32l1xx_spi.c.

References SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Hardware CRC Calculation functions

Functions

Hardware CRC Calculation functions

SPI_Private_Functions

Hardware CRC Calculation functions. More...

Functions

void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

Hardware CRC Calculation functions.

 ===============================================================================
                ##### Hardware CRC Calculation functions #####
 ===============================================================================
    [..] This section provides a set of functions allowing to manage the SPI CRC
         hardware calculation SPI communication using CRC is possible through
         the following procedure:
         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate
             Prescaler, Slave Management, Peripheral Mode and CRC Polynomial
             values using the SPI_Init() function.
         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
         (#) Enable the SPI using the SPI_Cmd() function.
         (#) Before writing the last data to the TX buffer, set the CRCNext bit
             using the SPI_TransmitCRC() function to indicate that after
             transmission of the last data, the CRC should be transmitted.
         (#) After transmitting the last data, the SPI transmits the CRC.
             The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and
             compared against the SPI_RXCRCR value.
             If the value does not match, the SPI_FLAG_CRCERR flag is set and an
             interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
    -@-
       (+@) It is advised to don't read the calculate CRC values during the communication.
       (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
       when the clock is stable, that is, when the clock is in the steady state.
       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
       to the SCK slave input clock as soon as CRCEN is set, and this, whatever
       the value of the SPE bit.
       (+@) With high bitrate frequencies, be careful when transmitting the CRC.
       As the number of used CPU cycles has to be as low as possible in the CRC
       transfer phase, it is forbidden to call software functions in the CRC
       transmission sequence to avoid errors in the last data and CRC reception.
       In fact, CRCNEXT bit has to be written before the end of the transmission/
       reception of the last data.
       (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
       degradation of the SPI speed performance due to CPU accesses impacting the
       SPI bandwidth.
       (+@) When the STM32L15xxx are configured as slaves and the NSS hardware mode is
       used, the NSS pin needs to be kept low between the data phase and the CRC
       phase.
       (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
       calculation takes place even if a high level is applied on the NSS pin.
       This may happen for example in case of a multislave environment where the
       communication master addresses slaves alternately.
       (+@) Between a slave deselection (high level on NSS) and a new slave selection
       (low level on NSS), the CRC value should be cleared on both master and slave
       sides in order to resynchronize the master and slave for their respective
       CRC calculation.
    -@- To clear the CRC, follow the procedure below:
       (#@) Disable SPI using the SPI_Cmd() function
       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
       (#@) Enable SPI using the SPI_Cmd() function.

Function Documentation

void SPI_CalculateCRC | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 667 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR1_CRCEN.

uint16_t SPI_GetCRC | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_CRC
 | ) |  |

Returns the transmit or the receive CRC register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_CRC,: specifies the CRC register to be read. This parameter can be one of the following values:

  • SPI_CRC_Tx: Selects Tx CRC register.
  • SPI_CRC_Rx: Selects Rx CRC register.
Return values:
The selected CRC register value.

Definition at line 707 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_CRC, SPI_TypeDef::RXCRCR, SPI_CRC_Rx, and SPI_TypeDef::TXCRCR.

uint16_t SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Returns the CRC Polynomial register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
The CRC Polynomial register value.

Definition at line 732 of file stm32l1xx_spi.c.

References SPI_TypeDef::CRCPR, and IS_SPI_ALL_PERIPH.

void SPI_TransmitCRC ( SPI_TypeDef * SPIx )

Transmit the SPIx CRC value.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 689 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, and SPI_CR1_CRCNEXT.


STM32L1xx Standard Peripherals Firmware Library: DMA transfers management functions

Functions

DMA transfers management functions

SPI_Private_Functions

DMA transfers management functions. More...

Functions

void SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.

Detailed Description

DMA transfers management functions.

 ===============================================================================
                ##### DMA transfers management functions #####
 ===============================================================================

Function Documentation

void SPI_I2S_DMACmd | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SPIx/I2Sx DMA interface.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_DMAReq,: specifies the SPI DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:

  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.
NewState,: new state of the selected SPI DMA transfer request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 769 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_DMAREQ.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

SPI_Private_Functions

Interrupts and flags management functions. More...

Functions

void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
             ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] This section provides a set of functions allowing to configure the SPI
         Interrupts sources and check or clear the flags or pending bits status.
         The user should identify which mode will be used in his application to
         manage the communication: Polling mode, Interrupt mode or DMA mode.
  *** Polling Mode ***
  ====================
    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
        (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer
             register.
        (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer
             register.
        (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer
             of the SPI.
        (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
        (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
        (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
        (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
        (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
        (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
    -@- Do not use the BSY flag to handle each data transmission or reception.
        It is better to use the TXE and RXNE flags instead.
    [..] In this Mode it is advised to use the following functions:
         (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).
         (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).

  *** Interrupt Mode ***
  ======================
    [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt
         sources and 7 pending bits:
    [..] Pending Bits:
        (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
        (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
        (#) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur.
        (#) SPI_IT_MODF : to indicate if a Mode Fault error occur.
        (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
        (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
        (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
    [..] Interrupt Source:
        (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
            interrupt.
        (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
            empty interrupt.
        (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
    [..] In this Mode it is advised to use the following functions:
         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT,
             FunctionalState NewState).
         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).
         (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).

  *** DMA Mode ***
  ================
    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel
         requests:
        (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
        (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.

    [..] In this Mode it is advised to use the following function:
         (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq,
             FunctionalState NewState).

Function Documentation

void SPI_I2S_ClearFlag | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Clears the SPIx CRC Error (CRCERR) flag.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_FLAG,: specifies the SPI flag to clear. This function clears only CRCERR flag.
Note:
OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 962 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_FLAG, and SPI_TypeDef::SR.

void SPI_I2S_ClearITPendingBit | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.

OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).

Note:
UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 1043 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_IT, and SPI_TypeDef::SR.

FlagStatus SPI_I2S_GetFlagStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Checks whether the specified SPIx/I2Sx flag is set or not.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_FLAG,: specifies the SPI flag to check. This parameter can be one of the following values:

  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
  • SPI_I2S_FLAG_BSY: Busy flag.
  • SPI_I2S_FLAG_OVR: Overrun flag.
  • SPI_FLAG_MODF: Mode Fault flag.
  • SPI_FLAG_CRCERR: CRC Error flag.
  • SPI_I2S_FLAG_FRE: Format Error.
  • I2S_FLAG_UDR: Underrun Error flag.
  • I2S_FLAG_CHSIDE: Channel Side flag.
Return values:
The new state of SPI_I2S_FLAG (SET or RESET).

Definition at line 922 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_FLAG, RESET, SET, and SPI_TypeDef::SR.

ITStatus SPI_I2S_GetITStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Checks whether the specified SPIx/I2Sx interrupt has occurred or not.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt source to check. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
  • SPI_I2S_IT_OVR: Overrun interrupt.
  • SPI_IT_MODF: Mode Fault interrupt.
  • SPI_IT_CRCERR: CRC Error interrupt.
  • I2S_IT_UDR: Underrun interrupt.
  • SPI_I2S_IT_FRE: Format Error interrupt.
Return values:
The new state of SPI_I2S_IT (SET or RESET).

Definition at line 988 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_IT, RESET, SET, and SPI_TypeDef::SR.

void SPI_I2S_ITConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI/I2S interrupts.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt source to be enabled or disabled. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.
  • SPI_I2S_IT_ERR: Error interrupt mask.
NewState,: new state of the specified SPI interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 877 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_CONFIG_IT.


STM32L1xx Standard Peripherals Firmware Library: SPI

Data Structures | Modules | Defines | Functions

SPI

STM32L1xx_StdPeriph_Driver

SPI driver modules. More...

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | SPI_InitTypeDef
SPI Init structure definition. More...

Modules

SPI_Exported_Constants
SPI_Private_Functions

Defines

#define | CR1_CLEAR_MASK ((uint16_t)0x3040)
#define | I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values.
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

SPI driver modules.

Define Documentation

#define CR1_CLEAR_MASK ((uint16_t)0x3040)

Definition at line 108 of file stm32l1xx_spi.c.

Referenced by SPI_Init().

#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)

Definition at line 109 of file stm32l1xx_spi.c.

Referenced by I2S_Init().

Function Documentation

void I2S_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral (in I2S mode).

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 426 of file stm32l1xx_spi.c.

References DISABLE, SPI_TypeDef::I2SCFGR, IS_FUNCTIONAL_STATE, IS_SPI_23_PERIPH, and SPI_I2SCFGR_I2SE.

void I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStruct,: pointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
Note:
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead.
Return values:
None

Definition at line 244 of file stm32l1xx_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Enable, I2S_InitTypeDef::I2S_Mode, I2S_InitTypeDef::I2S_Standard, SPI_TypeDef::I2SCFGR, I2SCFGR_CLEAR_Mask, SPI_TypeDef::I2SPR, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, IS_SPI_23_PERIPH, RCC_GetClocksFreq(), SPI_I2SCFGR_I2SMOD, and RCC_ClocksTypeDef::SYSCLK_Frequency.

void I2S_StructInit ( I2S_InitTypeDef * I2S_InitStruct )

Fills each I2S_InitStruct member with its default value.

Parameters:
I2S_InitStruct,: pointer to a I2S_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 373 of file stm32l1xx_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_SlaveTx, I2S_InitTypeDef::I2S_Standard, and I2S_Standard_Phillips.

void SPI_BiDirectionalLineConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_Direction
 | ) |  |

Selects the data transfer direction in bidirectional mode for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_Direction,: specifies the data transfer direction in bidirectional mode. This parameter can be one of the following values:

  • SPI_Direction_Tx: Selects Tx transmission direction.
  • SPI_Direction_Rx: Selects Rx receive direction.
Return values:
None

Definition at line 473 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DIRECTION, SPI_Direction_Rx, and SPI_Direction_Tx.

void SPI_CalculateCRC | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 667 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR1_CRCEN.

void SPI_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 402 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR1_SPE.

void SPI_DataSizeConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_DataSize
 | ) |  |

Configures the data size for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_DataSize,: specifies the SPI data size. This parameter can be one of the following values:

  • SPI_DataSize_16b: Set data frame format to 16bit.
  • SPI_DataSize_8b: Set data frame format to 8bit.
Return values:
None.

Definition at line 453 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DATASIZE, and SPI_DataSize_16b.

uint16_t SPI_GetCRC | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_CRC
 | ) |  |

Returns the transmit or the receive CRC register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_CRC,: specifies the CRC register to be read. This parameter can be one of the following values:

  • SPI_CRC_Tx: Selects Tx CRC register.
  • SPI_CRC_Rx: Selects Rx CRC register.
Return values:
The selected CRC register value.

Definition at line 707 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_CRC, SPI_TypeDef::RXCRCR, SPI_CRC_Rx, and SPI_TypeDef::TXCRCR.

uint16_t SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Returns the CRC Polynomial register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
The CRC Polynomial register value.

Definition at line 732 of file stm32l1xx_spi.c.

References SPI_TypeDef::CRCPR, and IS_SPI_ALL_PERIPH.

void SPI_I2S_ClearFlag | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Clears the SPIx CRC Error (CRCERR) flag.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_FLAG,: specifies the SPI flag to clear. This function clears only CRCERR flag.
Note:
OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 962 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_FLAG, and SPI_TypeDef::SR.

void SPI_I2S_ClearITPendingBit | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.

OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).

Note:
UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 1043 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_IT, and SPI_TypeDef::SR.

void SPI_I2S_DeInit ( SPI_TypeDef * SPIx )

Deinitializes the SPIx peripheral registers to their default reset values.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Return values:
None

Definition at line 145 of file stm32l1xx_spi.c.

References DISABLE, ENABLE, IS_SPI_ALL_PERIPH, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_SPI1, RCC_APB2PeriphResetCmd(), SPI1, SPI2, and SPI3.

void SPI_I2S_DMACmd | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SPIx/I2Sx DMA interface.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_DMAReq,: specifies the SPI DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:

  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.
NewState,: new state of the selected SPI DMA transfer request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 769 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_DMAREQ.

FlagStatus SPI_I2S_GetFlagStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Checks whether the specified SPIx/I2Sx flag is set or not.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_FLAG,: specifies the SPI flag to check. This parameter can be one of the following values:

  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
  • SPI_I2S_FLAG_BSY: Busy flag.
  • SPI_I2S_FLAG_OVR: Overrun flag.
  • SPI_FLAG_MODF: Mode Fault flag.
  • SPI_FLAG_CRCERR: CRC Error flag.
  • SPI_I2S_FLAG_FRE: Format Error.
  • I2S_FLAG_UDR: Underrun Error flag.
  • I2S_FLAG_CHSIDE: Channel Side flag.
Return values:
The new state of SPI_I2S_FLAG (SET or RESET).

Definition at line 922 of file stm32l1xx_spi.c.

References IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_FLAG, RESET, SET, and SPI_TypeDef::SR.

ITStatus SPI_I2S_GetITStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Checks whether the specified SPIx/I2Sx interrupt has occurred or not.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt source to check. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
  • SPI_I2S_IT_OVR: Overrun interrupt.
  • SPI_IT_MODF: Mode Fault interrupt.
  • SPI_IT_CRCERR: CRC Error interrupt.
  • I2S_IT_UDR: Underrun interrupt.
  • SPI_I2S_IT_FRE: Format Error interrupt.
Return values:
The new state of SPI_I2S_IT (SET or RESET).

Definition at line 988 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_IT, RESET, SET, and SPI_TypeDef::SR.

void SPI_I2S_ITConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI/I2S interrupts.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
SPI_I2S_IT,: specifies the SPI interrupt source to be enabled or disabled. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.
  • SPI_I2S_IT_ERR: Error interrupt mask.
NewState,: new state of the specified SPI interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 877 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_CONFIG_IT.

uint16_t SPI_I2S_ReceiveData ( SPI_TypeDef * SPIx )

Returns the most recent received data by the SPIx/I2Sx peripheral.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Return values:
The value of the received data.

Definition at line 571 of file stm32l1xx_spi.c.

References SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

void SPI_I2S_SendData | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | Data
 | ) |  |

Transmits a Data through the SPIx/I2Sx peripheral.

Parameters:
SPIx,: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 in SPI mode or 2 or 3 in I2S mode.
Data,: Data to be transmitted.
Return values:
None

Definition at line 587 of file stm32l1xx_spi.c.

References SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

void SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
Return values:
None

Definition at line 184 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, CR1_CLEAR_MASK, SPI_TypeDef::CRCPR, SPI_TypeDef::I2SCFGR, IS_SPI_ALL_PERIPH, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION_MODE, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_InitTypeDef::SPI_CPHA, SPI_InitTypeDef::SPI_CPOL, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_InitTypeDef::SPI_Direction, SPI_InitTypeDef::SPI_FirstBit, SPI_I2SCFGR_I2SMOD, SPI_InitTypeDef::SPI_Mode, and SPI_InitTypeDef::SPI_NSS.

void SPI_NSSInternalSoftwareConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_NSSInternalSoft
 | ) |  |

Configures internally by software the NSS pin for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_NSSInternalSoft,: specifies the SPI NSS internal state. This parameter can be one of the following values:

  • SPI_NSSInternalSoft_Set: Set NSS pin internally.
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally.
Return values:
None

Definition at line 499 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_NSS_INTERNAL, SPI_NSSInternalSoft_Reset, and SPI_NSSInternalSoft_Set.

void SPI_SSOutputCmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SS output for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 523 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and SPI_CR2_SSOE.

void SPI_StructInit ( SPI_InitTypeDef * SPI_InitStruct )

Fills each SPI_InitStruct member with its default value.

Parameters:
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 345 of file stm32l1xx_spi.c.

References SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Hard.

void SPI_TransmitCRC ( SPI_TypeDef * SPIx )

Transmit the SPIx CRC value.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 689 of file stm32l1xx_spi.c.

References SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, and SPI_CR1_CRCNEXT.


STM32L1xx Standard Peripherals Firmware Library: I2S_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2S_InitTypeDef Struct Reference
SPI

I2S Init structure definition. More...

#include <stm32l1xx_spi.h>

Data Fields

uint32_t | I2S_AudioFreq
uint16_t | I2S_CPOL
uint16_t | I2S_DataFormat
uint16_t | I2S_MCLKOutput
uint16_t | I2S_Mode
uint16_t | I2S_Standard

Detailed Description

I2S Init structure definition.

Definition at line 88 of file stm32l1xx_spi.h.

Field Documentation

uint32_t I2S_InitTypeDef::I2S_AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of SPI_I2S_Audio_Frequency

Definition at line 103 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

uint16_t I2S_InitTypeDef::I2S_CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of SPI_I2S_Clock_Polarity

Definition at line 106 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

uint16_t I2S_InitTypeDef::I2S_DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of SPI_I2S_Data_Format

Definition at line 97 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

uint16_t I2S_InitTypeDef::I2S_MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of SPI_I2S_MCLK_Output

Definition at line 100 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

uint16_t I2S_InitTypeDef::I2S_Mode

Specifies the I2S operating mode. This parameter can be a value of SPI_I2S_Mode

Definition at line 91 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

uint16_t I2S_InitTypeDef::I2S_Standard

Specifies the standard used for the I2S communication. This parameter can be a value of SPI_I2S_Standard

Definition at line 94 of file stm32l1xx_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_spi.h


STM32L1xx Standard Peripherals Firmware Library: SPI_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SPI_InitTypeDef Struct Reference
SPI

SPI Init structure definition. More...

#include <stm32l1xx_spi.h>

Data Fields

uint16_t | SPI_BaudRatePrescaler
uint16_t | SPI_CPHA
uint16_t | SPI_CPOL
uint16_t | SPI_CRCPolynomial
uint16_t | SPI_DataSize
uint16_t | SPI_Direction
uint16_t | SPI_FirstBit
uint16_t | SPI_Mode
uint16_t | SPI_NSS

Detailed Description

SPI Init structure definition.

Definition at line 51 of file stm32l1xx_spi.h.

Field Documentation

uint16_t SPI_InitTypeDef::SPI_BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI_BaudRate_Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 72 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CPHA

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI_Clock_Phase

Definition at line 65 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CPOL

Specifies the serial clock steady state. This parameter can be a value of SPI_Clock_Polarity

Definition at line 62 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CRCPolynomial

Specifies the polynomial used for the CRC calculation.

Definition at line 81 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_DataSize

Specifies the SPI data size. This parameter can be a value of SPI_data_size

Definition at line 59 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_Direction

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of SPI_data_direction

Definition at line 53 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI_MSB_LSB_transmission

Definition at line 78 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_Mode

Specifies the SPI operating mode. This parameter can be a value of SPI_mode

Definition at line 56 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI_Slave_Select_management

Definition at line 68 of file stm32l1xx_spi.h.

Referenced by SPI_Init(), and SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_spi.h


STM32L1xx Standard Peripherals Firmware Library: EXTI_Port_Sources

Defines

EXTI_Port_Sources

SYSCFG_Exported_Constants

Defines

#define | EXTI_PortSourceGPIOA ((uint8_t)0x00)
#define | EXTI_PortSourceGPIOB ((uint8_t)0x01)
#define | EXTI_PortSourceGPIOC ((uint8_t)0x02)
#define | EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define | EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define | EXTI_PortSourceGPIOF ((uint8_t)0x06)
#define | EXTI_PortSourceGPIOG ((uint8_t)0x07)
#define | EXTI_PortSourceGPIOH ((uint8_t)0x05)
#define | IS_EXTI_PORT_SOURCE(PORTSOURCE)

Define Documentation

#define EXTI_PortSourceGPIOA ((uint8_t)0x00)

Definition at line 55 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOB ((uint8_t)0x01)

Definition at line 56 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOC ((uint8_t)0x02)

Definition at line 57 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOD ((uint8_t)0x03)

Definition at line 58 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOE ((uint8_t)0x04)

Definition at line 59 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOF ((uint8_t)0x06)

Definition at line 61 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOG ((uint8_t)0x07)

Definition at line 62 of file stm32l1xx_syscfg.h.

#define EXTI_PortSourceGPIOH ((uint8_t)0x05)

Definition at line 60 of file stm32l1xx_syscfg.h.

#define IS_EXTI_PORT_SOURCE ( PORTSOURCE )
Value:
(((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
                                         ((PORTSOURCE) == EXTI_PortSourceGPIOH))

Definition at line 64 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_EXTILineConfig().


STM32L1xx Standard Peripherals Firmware Library: EXTI_Pin_sources

Defines

EXTI_Pin_sources

SYSCFG_Exported_Constants

Defines

#define | EXTI_PinSource0 ((uint8_t)0x00)
#define | EXTI_PinSource1 ((uint8_t)0x01)
#define | EXTI_PinSource10 ((uint8_t)0x0A)
#define | EXTI_PinSource11 ((uint8_t)0x0B)
#define | EXTI_PinSource12 ((uint8_t)0x0C)
#define | EXTI_PinSource13 ((uint8_t)0x0D)
#define | EXTI_PinSource14 ((uint8_t)0x0E)
#define | EXTI_PinSource15 ((uint8_t)0x0F)
#define | EXTI_PinSource2 ((uint8_t)0x02)
#define | EXTI_PinSource3 ((uint8_t)0x03)
#define | EXTI_PinSource4 ((uint8_t)0x04)
#define | EXTI_PinSource5 ((uint8_t)0x05)
#define | EXTI_PinSource6 ((uint8_t)0x06)
#define | EXTI_PinSource7 ((uint8_t)0x07)
#define | EXTI_PinSource8 ((uint8_t)0x08)
#define | EXTI_PinSource9 ((uint8_t)0x09)
#define | IS_EXTI_PIN_SOURCE(PINSOURCE)

Define Documentation

#define EXTI_PinSource0 ((uint8_t)0x00)

Definition at line 79 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource1 ((uint8_t)0x01)

Definition at line 80 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource10 ((uint8_t)0x0A)

Definition at line 89 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource11 ((uint8_t)0x0B)

Definition at line 90 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource12 ((uint8_t)0x0C)

Definition at line 91 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource13 ((uint8_t)0x0D)

Definition at line 92 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource14 ((uint8_t)0x0E)

Definition at line 93 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource15 ((uint8_t)0x0F)

Definition at line 94 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource2 ((uint8_t)0x02)

Definition at line 81 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource3 ((uint8_t)0x03)

Definition at line 82 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource4 ((uint8_t)0x04)

Definition at line 83 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource5 ((uint8_t)0x05)

Definition at line 84 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource6 ((uint8_t)0x06)

Definition at line 85 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource7 ((uint8_t)0x07)

Definition at line 86 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource8 ((uint8_t)0x08)

Definition at line 87 of file stm32l1xx_syscfg.h.

#define EXTI_PinSource9 ((uint8_t)0x09)

Definition at line 88 of file stm32l1xx_syscfg.h.

#define IS_EXTI_PIN_SOURCE ( PINSOURCE )
Value:
(((PINSOURCE) == EXTI_PinSource0) || \
                                       ((PINSOURCE) == EXTI_PinSource1) || \
                                       ((PINSOURCE) == EXTI_PinSource2) || \
                                       ((PINSOURCE) == EXTI_PinSource3) || \
                                       ((PINSOURCE) == EXTI_PinSource4) || \
                                       ((PINSOURCE) == EXTI_PinSource5) || \
                                       ((PINSOURCE) == EXTI_PinSource6) || \
                                       ((PINSOURCE) == EXTI_PinSource7) || \
                                       ((PINSOURCE) == EXTI_PinSource8) || \
                                       ((PINSOURCE) == EXTI_PinSource9) || \
                                       ((PINSOURCE) == EXTI_PinSource10) || \
                                       ((PINSOURCE) == EXTI_PinSource11) || \
                                       ((PINSOURCE) == EXTI_PinSource12) || \
                                       ((PINSOURCE) == EXTI_PinSource13) || \
                                       ((PINSOURCE) == EXTI_PinSource14) || \
                                       ((PINSOURCE) == EXTI_PinSource15))

Definition at line 95 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_EXTILineConfig().


STM32L1xx Standard Peripherals Firmware Library: SYSCFG_Memory_Remap_Config

Defines

SYSCFG_Memory_Remap_Config

SYSCFG_Exported_Constants

Defines

#define | IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP)
#define | SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define | SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#define | SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define | SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)

Define Documentation

#define IS_SYSCFG_MEMORY_REMAP_CONFING ( REMAP )
Value:
(((REMAP) == SYSCFG_MemoryRemap_Flash) || \
                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
                                               ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \
                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM))

Definition at line 123 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_MemoryRemapConfig().

#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)

Definition at line 118 of file stm32l1xx_syscfg.h.

#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)

Definition at line 120 of file stm32l1xx_syscfg.h.

#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)

Definition at line 121 of file stm32l1xx_syscfg.h.

#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)

Definition at line 119 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_Resistor

Defines

RI_Resistor

SYSCFG_Exported_Constants

Defines

#define | IS_RI_RESISTOR(RESISTOR)
#define | RI_Resistor_10KPD COMP_CSR_10KPD
#define | RI_Resistor_10KPU COMP_CSR_10KPU
#define | RI_Resistor_400KPD COMP_CSR_400KPD
#define | RI_Resistor_400KPU COMP_CSR_400KPU

Define Documentation

#define IS_RI_RESISTOR ( RESISTOR )
Value:
(((RESISTOR) == COMP_CSR_10KPU) || \
                                   ((RESISTOR) == COMP_CSR_400KPU) || \
                                   ((RESISTOR) == COMP_CSR_10KPD) || \
                                   ((RESISTOR) == COMP_CSR_400KPD))

Definition at line 141 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIResistorConfig().

#define RI_Resistor_10KPD COMP_CSR_10KPD

Definition at line 138 of file stm32l1xx_syscfg.h.

#define RI_Resistor_10KPU COMP_CSR_10KPU

Definition at line 136 of file stm32l1xx_syscfg.h.

#define RI_Resistor_400KPD COMP_CSR_400KPD

Definition at line 139 of file stm32l1xx_syscfg.h.

#define RI_Resistor_400KPU COMP_CSR_400KPU

Definition at line 137 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_Channel

Defines

RI_Channel

SYSCFG_Exported_Constants

Defines

#define | IS_RI_CHANNEL(CHANNEL)
#define | RI_Channel_13 ((uint32_t)0x10000000)
#define | RI_Channel_3 ((uint32_t)0x04000000)
#define | RI_Channel_8 ((uint32_t)0x08000000)

Define Documentation

#define IS_RI_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == RI_Channel_3) || \
                                 ((CHANNEL) == RI_Channel_8) || \
                                 ((CHANNEL) == RI_Channel_13))

Definition at line 158 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIChannelSpeedConfig().

#define RI_Channel_13 ((uint32_t)0x10000000)

Definition at line 156 of file stm32l1xx_syscfg.h.

#define RI_Channel_3 ((uint32_t)0x04000000)

Definition at line 154 of file stm32l1xx_syscfg.h.

#define RI_Channel_8 ((uint32_t)0x08000000)

Definition at line 155 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_ChannelSpeed

Defines

RI_ChannelSpeed

SYSCFG_Exported_Constants

Defines

#define | IS_RI_CHANNELSPEED(SPEED)
#define | RI_ChannelSpeed_Fast ((uint32_t)0x00000000)
#define | RI_ChannelSpeed_Slow ((uint32_t)0x00000001)

Define Documentation

#define IS_RI_CHANNELSPEED ( SPEED )
Value:
(((SPEED) == RI_ChannelSpeed_Fast) || \
                                    ((SPEED) == RI_ChannelSpeed_Slow))

Definition at line 173 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIChannelSpeedConfig().

#define RI_ChannelSpeed_Fast ((uint32_t)0x00000000)

Definition at line 170 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIChannelSpeedConfig().

#define RI_ChannelSpeed_Slow ((uint32_t)0x00000001)

Definition at line 171 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_InputCapture

Defines

RI_InputCapture

SYSCFG_Exported_Constants

Defines

#define | IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
#define | RI_InputCapture_IC1 RI_ICR_IC1
#define | RI_InputCapture_IC2 RI_ICR_IC2
#define | RI_InputCapture_IC3 RI_ICR_IC3
#define | RI_InputCapture_IC4 RI_ICR_IC4

Define Documentation

#define IS_RI_INPUTCAPTURE ( INPUTCAPTURE ) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))

Definition at line 189 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define RI_InputCapture_IC1 RI_ICR_IC1

Input Capture 1

Definition at line 184 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define RI_InputCapture_IC2 RI_ICR_IC2

Input Capture 2

Definition at line 185 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define RI_InputCapture_IC3 RI_ICR_IC3

Input Capture 3

Definition at line 186 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define RI_InputCapture_IC4 RI_ICR_IC4

Input Capture 4

Definition at line 187 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().


STM32L1xx Standard Peripherals Firmware Library: TIM_Select

Defines

TIM_Select

SYSCFG_Exported_Constants

Defines

#define | IS_RI_TIM(TIM)
#define | TIM_Select_None ((uint32_t)0x00000000)
#define | TIM_Select_TIM2 ((uint32_t)0x00010000)
#define | TIM_Select_TIM3 ((uint32_t)0x00020000)
#define | TIM_Select_TIM4 ((uint32_t)0x00030000)

Define Documentation

#define IS_RI_TIM ( TIM )
Value:
(((TIM) == TIM_Select_None) || \
                        ((TIM) == TIM_Select_TIM2) || \
                        ((TIM) == TIM_Select_TIM3) || \
                        ((TIM) == TIM_Select_TIM4))

Definition at line 203 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMSelect().

#define TIM_Select_None ((uint32_t)0x00000000)

None selected

Definition at line 198 of file stm32l1xx_syscfg.h.

#define TIM_Select_TIM2 ((uint32_t)0x00010000)

Timer 2 selected

Definition at line 199 of file stm32l1xx_syscfg.h.

#define TIM_Select_TIM3 ((uint32_t)0x00020000)

Timer 3 selected

Definition at line 200 of file stm32l1xx_syscfg.h.

#define TIM_Select_TIM4 ((uint32_t)0x00030000)

Timer 4 selected

Definition at line 201 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_InputCaptureRouting

Defines

RI_InputCaptureRouting

SYSCFG_Exported_Constants

Defines

#define | IS_RI_INPUTCAPTURE_ROUTING(ROUTING)
#define | RI_InputCaptureRouting_0 ((uint32_t)0x00000000)
#define | RI_InputCaptureRouting_1 ((uint32_t)0x00000001)
#define | RI_InputCaptureRouting_10 ((uint32_t)0x0000000A)
#define | RI_InputCaptureRouting_11 ((uint32_t)0x0000000B)
#define | RI_InputCaptureRouting_12 ((uint32_t)0x0000000C)
#define | RI_InputCaptureRouting_13 ((uint32_t)0x0000000D)
#define | RI_InputCaptureRouting_14 ((uint32_t)0x0000000E)
#define | RI_InputCaptureRouting_15 ((uint32_t)0x0000000F)
#define | RI_InputCaptureRouting_2 ((uint32_t)0x00000002)
#define | RI_InputCaptureRouting_3 ((uint32_t)0x00000003)
#define | RI_InputCaptureRouting_4 ((uint32_t)0x00000004)
#define | RI_InputCaptureRouting_5 ((uint32_t)0x00000005)
#define | RI_InputCaptureRouting_6 ((uint32_t)0x00000006)
#define | RI_InputCaptureRouting_7 ((uint32_t)0x00000007)
#define | RI_InputCaptureRouting_8 ((uint32_t)0x00000008)
#define | RI_InputCaptureRouting_9 ((uint32_t)0x00000009)

Define Documentation

#define IS_RI_INPUTCAPTURE_ROUTING ( ROUTING )
Value:
(((ROUTING) == RI_InputCaptureRouting_0) || \
                                             ((ROUTING) == RI_InputCaptureRouting_1) || \
                                             ((ROUTING) == RI_InputCaptureRouting_2) || \
                                             ((ROUTING) == RI_InputCaptureRouting_3) || \
                                             ((ROUTING) == RI_InputCaptureRouting_4) || \
                                             ((ROUTING) == RI_InputCaptureRouting_5) || \
                                             ((ROUTING) == RI_InputCaptureRouting_6) || \
                                             ((ROUTING) == RI_InputCaptureRouting_7) || \
                                             ((ROUTING) == RI_InputCaptureRouting_8) || \
                                             ((ROUTING) == RI_InputCaptureRouting_9) || \
                                             ((ROUTING) == RI_InputCaptureRouting_10) || \
                                             ((ROUTING) == RI_InputCaptureRouting_11) || \
                                             ((ROUTING) == RI_InputCaptureRouting_12) || \
                                             ((ROUTING) == RI_InputCaptureRouting_13) || \
                                             ((ROUTING) == RI_InputCaptureRouting_14) || \
                                             ((ROUTING) == RI_InputCaptureRouting_15))

Definition at line 233 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000)

Definition at line 216 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001)

Definition at line 217 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A)

Definition at line 226 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B)

Definition at line 227 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C)

Definition at line 228 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D)

Definition at line 229 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E)

Definition at line 230 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F)

Definition at line 231 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002)

Definition at line 218 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003)

Definition at line 219 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004)

Definition at line 220 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005)

Definition at line 221 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006)

Definition at line 222 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007)

Definition at line 223 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008)

Definition at line 224 of file stm32l1xx_syscfg.h.

#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009)

Definition at line 225 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_IOSwitch

Defines

RI_IOSwitch

SYSCFG_Exported_Constants

Defines

#define | IS_RI_IOSWITCH(IOSWITCH)
#define | RI_IOSwitch_CH0 ((uint32_t)0x80000001)
#define | RI_IOSwitch_CH0b ((uint32_t)0x00010000)
#define | RI_IOSwitch_CH1 ((uint32_t)0x80000002)
#define | RI_IOSwitch_CH10 ((uint32_t)0x80000400)
#define | RI_IOSwitch_CH10b ((uint32_t)0x01000000)
#define | RI_IOSwitch_CH11 ((uint32_t)0x80000800)
#define | RI_IOSwitch_CH11b ((uint32_t)0x02000000)
#define | RI_IOSwitch_CH12 ((uint32_t)0x80001000)
#define | RI_IOSwitch_CH12b ((uint32_t)0x04000000)
#define | RI_IOSwitch_CH13 ((uint32_t)0x80002000)
#define | RI_IOSwitch_CH14 ((uint32_t)0x80004000)
#define | RI_IOSwitch_CH15 ((uint32_t)0x80008000)
#define | RI_IOSwitch_CH18 ((uint32_t)0x80040000)
#define | RI_IOSwitch_CH19 ((uint32_t)0x80080000)
#define | RI_IOSwitch_CH1b ((uint32_t)0x00020000)
#define | RI_IOSwitch_CH2 ((uint32_t)0x80000004)
#define | RI_IOSwitch_CH20 ((uint32_t)0x80100000)
#define | RI_IOSwitch_CH21 ((uint32_t)0x80200000)
#define | RI_IOSwitch_CH22 ((uint32_t)0x80400000)
#define | RI_IOSwitch_CH23 ((uint32_t)0x80800000)
#define | RI_IOSwitch_CH24 ((uint32_t)0x81000000)
#define | RI_IOSwitch_CH25 ((uint32_t)0x82000000)
#define | RI_IOSwitch_CH27 ((uint32_t)0x88000000)
#define | RI_IOSwitch_CH28 ((uint32_t)0x90000000)
#define | RI_IOSwitch_CH29 ((uint32_t)0xA0000000)
#define | RI_IOSwitch_CH2b ((uint32_t)0x00040000)
#define | RI_IOSwitch_CH3 ((uint32_t)0x80000008)
#define | RI_IOSwitch_CH30 ((uint32_t)0xC0000000)
#define | RI_IOSwitch_CH31 ((uint32_t)0x80010000)
#define | RI_IOSwitch_CH3b ((uint32_t)0x00080000)
#define | RI_IOSwitch_CH4 ((uint32_t)0x80000010)
#define | RI_IOSwitch_CH5 ((uint32_t)0x80000020)
#define | RI_IOSwitch_CH6 ((uint32_t)0x80000040)
#define | RI_IOSwitch_CH6b ((uint32_t)0x00100000)
#define | RI_IOSwitch_CH7 ((uint32_t)0x80000080)
#define | RI_IOSwitch_CH7b ((uint32_t)0x00200000)
#define | RI_IOSwitch_CH8 ((uint32_t)0x80000100)
#define | RI_IOSwitch_CH8b ((uint32_t)0x00400000)
#define | RI_IOSwitch_CH9 ((uint32_t)0x80000200)
#define | RI_IOSwitch_CH9b ((uint32_t)0x00800000)
#define | RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
#define | RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
#define | RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
#define | RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
#define | RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
#define | RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
#define | RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
#define | RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)
#define | RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
#define | RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
#define | RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
#define | RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)
#define | RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
#define | RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
#define | RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)
#define | RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)
#define | RI_IOSwitch_VCOMP ((uint32_t)0x84000000)

Define Documentation

#define IS_RI_IOSWITCH ( IOSWITCH )

Definition at line 321 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIIOSwitchConfig().

#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)

Definition at line 259 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH0b ((uint32_t)0x00010000)

Definition at line 305 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)

Definition at line 260 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)

Definition at line 269 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH10b ((uint32_t)0x01000000)

Definition at line 313 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)

Definition at line 270 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH11b ((uint32_t)0x02000000)

Definition at line 314 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)

Definition at line 271 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH12b ((uint32_t)0x04000000)

Definition at line 315 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)

Definition at line 272 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)

Definition at line 273 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)

Definition at line 274 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)

Definition at line 276 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)

Definition at line 277 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH1b ((uint32_t)0x00020000)

Definition at line 306 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)

Definition at line 261 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)

Definition at line 278 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)

Definition at line 279 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)

Definition at line 280 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)

Definition at line 281 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)

Definition at line 282 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)

Definition at line 283 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH27 ((uint32_t)0x88000000)

Definition at line 286 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH28 ((uint32_t)0x90000000)

Definition at line 287 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH29 ((uint32_t)0xA0000000)

Definition at line 288 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH2b ((uint32_t)0x00040000)

Definition at line 307 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)

Definition at line 262 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH30 ((uint32_t)0xC0000000)

Definition at line 289 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH31 ((uint32_t)0x80010000)

Definition at line 275 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH3b ((uint32_t)0x00080000)

Definition at line 308 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)

Definition at line 263 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)

Definition at line 264 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)

Definition at line 265 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH6b ((uint32_t)0x00100000)

Definition at line 309 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)

Definition at line 266 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH7b ((uint32_t)0x00200000)

Definition at line 310 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)

Definition at line 267 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH8b ((uint32_t)0x00400000)

Definition at line 311 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)

Definition at line 268 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_CH9b ((uint32_t)0x00800000)

Definition at line 312 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)

Definition at line 292 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)

Definition at line 293 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)

Definition at line 294 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)

Definition at line 295 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)

Definition at line 301 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)

Definition at line 302 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)

Definition at line 303 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)

Definition at line 304 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)

Definition at line 298 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)

Definition at line 299 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)

Definition at line 300 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)

Definition at line 318 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)

Definition at line 296 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)

Definition at line 297 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)

Definition at line 316 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)

Definition at line 317 of file stm32l1xx_syscfg.h.

#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000)

Definition at line 284 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: RI_Port

Defines

RI_Port

SYSCFG_Exported_Constants

Defines

#define | IS_RI_PORT(PORT)
#define | RI_PortA ((uint8_t)0x01)
#define | RI_PortB ((uint8_t)0x02)
#define | RI_PortC ((uint8_t)0x03)
#define | RI_PortD ((uint8_t)0x04)
#define | RI_PortE ((uint8_t)0x05)
#define | RI_PortF ((uint8_t)0x06)
#define | RI_PortG ((uint8_t)0x07)

Define Documentation

#define IS_RI_PORT ( PORT )
Value:
(((PORT) == RI_PortA) || \
                          ((PORT) == RI_PortB) || \
                          ((PORT) == RI_PortC) || \
                          ((PORT) == RI_PortD) || \
                          ((PORT) == RI_PortE) || \
                          ((PORT) == RI_PortF) || \
                          ((PORT) == RI_PortG))

Definition at line 395 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortA ((uint8_t)0x01)

GPIOA selected

Definition at line 387 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortB ((uint8_t)0x02)

GPIOB selected

Definition at line 388 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortC ((uint8_t)0x03)

GPIOC selected

Definition at line 389 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortD ((uint8_t)0x04)

GPIOD selected

Definition at line 390 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortE ((uint8_t)0x05)

GPIOE selected

Definition at line 391 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortF ((uint8_t)0x06)

GPIOF selected

Definition at line 392 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_PortG ((uint8_t)0x07)

GPIOG selected

Definition at line 393 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: define

Defines

define

SYSCFG_Exported_Constants

Defines

#define | IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define | RI_Pin_0 ((uint16_t)0x0001)
#define | RI_Pin_1 ((uint16_t)0x0002)
#define | RI_Pin_10 ((uint16_t)0x0400)
#define | RI_Pin_11 ((uint16_t)0x0800)
#define | RI_Pin_12 ((uint16_t)0x1000)
#define | RI_Pin_13 ((uint16_t)0x2000)
#define | RI_Pin_14 ((uint16_t)0x4000)
#define | RI_Pin_15 ((uint16_t)0x8000)
#define | RI_Pin_2 ((uint16_t)0x0004)
#define | RI_Pin_3 ((uint16_t)0x0008)
#define | RI_Pin_4 ((uint16_t)0x0010)
#define | RI_Pin_5 ((uint16_t)0x0020)
#define | RI_Pin_6 ((uint16_t)0x0040)
#define | RI_Pin_7 ((uint16_t)0x0080)
#define | RI_Pin_8 ((uint16_t)0x0100)
#define | RI_Pin_9 ((uint16_t)0x0200)
#define | RI_Pin_All ((uint16_t)0xFFFF)

Define Documentation

#define IS_RI_PIN ( PIN ) ((PIN) != (uint16_t)0x00)

Definition at line 427 of file stm32l1xx_syscfg.h.

Referenced by SYSCFG_RIHysteresisConfig().

#define RI_Pin_0 ((uint16_t)0x0001)

Pin 0 selected

Definition at line 409 of file stm32l1xx_syscfg.h.

#define RI_Pin_1 ((uint16_t)0x0002)

Pin 1 selected

Definition at line 410 of file stm32l1xx_syscfg.h.

#define RI_Pin_10 ((uint16_t)0x0400)

Pin 10 selected

Definition at line 419 of file stm32l1xx_syscfg.h.

#define RI_Pin_11 ((uint16_t)0x0800)

Pin 11 selected

Definition at line 420 of file stm32l1xx_syscfg.h.

#define RI_Pin_12 ((uint16_t)0x1000)

Pin 12 selected

Definition at line 421 of file stm32l1xx_syscfg.h.

#define RI_Pin_13 ((uint16_t)0x2000)

Pin 13 selected

Definition at line 422 of file stm32l1xx_syscfg.h.

#define RI_Pin_14 ((uint16_t)0x4000)

Pin 14 selected

Definition at line 423 of file stm32l1xx_syscfg.h.

#define RI_Pin_15 ((uint16_t)0x8000)

Pin 15 selected

Definition at line 424 of file stm32l1xx_syscfg.h.

#define RI_Pin_2 ((uint16_t)0x0004)

Pin 2 selected

Definition at line 411 of file stm32l1xx_syscfg.h.

#define RI_Pin_3 ((uint16_t)0x0008)

Pin 3 selected

Definition at line 412 of file stm32l1xx_syscfg.h.

#define RI_Pin_4 ((uint16_t)0x0010)

Pin 4 selected

Definition at line 413 of file stm32l1xx_syscfg.h.

#define RI_Pin_5 ((uint16_t)0x0020)

Pin 5 selected

Definition at line 414 of file stm32l1xx_syscfg.h.

#define RI_Pin_6 ((uint16_t)0x0040)

Pin 6 selected

Definition at line 415 of file stm32l1xx_syscfg.h.

#define RI_Pin_7 ((uint16_t)0x0080)

Pin 7 selected

Definition at line 416 of file stm32l1xx_syscfg.h.

#define RI_Pin_8 ((uint16_t)0x0100)

Pin 8 selected

Definition at line 417 of file stm32l1xx_syscfg.h.

#define RI_Pin_9 ((uint16_t)0x0200)

Pin 9 selected

Definition at line 418 of file stm32l1xx_syscfg.h.

#define RI_Pin_All ((uint16_t)0xFFFF)

All pins selected

Definition at line 425 of file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: SYSCFG Initialization and Configuration functions

Functions

SYSCFG Initialization and Configuration functions

SYSCFG_Private_Functions

SYSCFG Initialization and Configuration functions. More...

Functions

void | SYSCFG_DeInit (void)
Deinitializes the SYSCFG registers to their default reset values.
void | SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
uint32_t | SYSCFG_GetBootMode (void)
Returns the boot mode as configured by user.
void | SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
Changes the mapping of the specified memory.
void | SYSCFG_RIDeInit (void)
Deinitializes the RI registers to their default reset values.
void | SYSCFG_USBPuCmd (FunctionalState NewState)
Control the internal pull-up on USB DP line.

Detailed Description

SYSCFG Initialization and Configuration functions.

 ===============================================================================
        ##### SYSCFG Initialization and Configuration functions #####
 ===============================================================================

Function Documentation

void SYSCFG_DeInit ( void )

Deinitializes the SYSCFG registers to their default reset values.

Parameters:
None.
Return values:
None. : MEMRMP bits are not reset by APB2 reset.

Definition at line 111 of file stm32l1xx_syscfg.c.

References DISABLE, ENABLE, RCC_APB2Periph_SYSCFG, and RCC_APB2PeriphResetCmd().

void SYSCFG_EXTILineConfig | ( | uint8_t | EXTI_PortSourceGPIOx,
 |  | uint8_t | EXTI_PinSourcex
 | ) |  |

Selects the GPIO pin used as EXTI Line.

Parameters:
EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for EXTI lines where x can be (A, B, C, D, E, F, G or H).
EXTI_PinSourcex,: specifies the EXTI line to be configured. This parameter can be EXTI_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 197 of file stm32l1xx_syscfg.c.

References IS_EXTI_PIN_SOURCE, IS_EXTI_PORT_SOURCE, and SYSCFG.

uint32_t SYSCFG_GetBootMode ( void )

Returns the boot mode as configured by user.

Parameters:
None.
Return values:
The boot mode as configured by user. The returned value can be one of the following values:

  • 0x00000000: Boot is configured in Main Flash memory
  • 0x00000100: Boot is configured in System Flash memory
  • 0x00000200: Boot is configured in FSMC memory
  • 0x00000300: Boot is configured in Embedded SRAM memory

Definition at line 160 of file stm32l1xx_syscfg.c.

References SYSCFG, and SYSCFG_MEMRMP_BOOT_MODE.

void SYSCFG_MemoryRemapConfig ( uint8_t SYSCFG_MemoryRemap )

Changes the mapping of the specified memory.

Parameters:
SYSCFG_Memory,: selects the memory remapping. This parameter can be one of the following values:

  • SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
Return values:
None

Definition at line 143 of file stm32l1xx_syscfg.c.

References IS_SYSCFG_MEMORY_REMAP_CONFING, and SYSCFG.

void SYSCFG_RIDeInit ( void )

Deinitializes the RI registers to their default reset values.

Parameters:
None.
Return values:
None.

< Set RI->ICR to reset value

< Set RI->ASCR1 to reset value

< Set RI->ASCR2 to reset value

< Set RI->HYSCR1 to reset value

< Set RI->HYSCR2 to reset value

< Set RI->HYSCR3 to reset value

< Set RI->HYSCR4 to reset value

Definition at line 122 of file stm32l1xx_syscfg.c.

References RI.

void SYSCFG_USBPuCmd ( FunctionalState NewState )

Control the internal pull-up on USB DP line.

Parameters:
NewState,: New state of the internal pull-up on USB DP line. This parameter can be ENABLE: Connect internal pull-up on USB DP line. or DISABLE: Disconnect internal pull-up on USB DP line.
Return values:
None

Definition at line 172 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, SYSCFG, and SYSCFG_PMC_USB_PU.


STM32L1xx Standard Peripherals Firmware Library: RI Initialization and Configuration functions

Functions

RI Initialization and Configuration functions

SYSCFG_Private_Functions

RI Initialization and Configuration functions. More...

Functions

void | SYSCFG_RIChannelSpeedConfig (uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
Configures the ADC channels speed.
void | SYSCFG_RIHysteresisConfig (uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState)
Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.
void | SYSCFG_RIIOSwitchConfig (uint32_t RI_IOSwitch, FunctionalState NewState)
Close or Open the routing interface Input Output switches.
void | SYSCFG_RIResistorConfig (uint32_t RI_Resistor, FunctionalState NewState)
Configures the Pull-up and Pull-down Resistors.
void | SYSCFG_RISwitchControlModeCmd (FunctionalState NewState)
Enable or disable the switch control mode.
void | SYSCFG_RITIMInputCaptureConfig (uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.
void | SYSCFG_RITIMSelect (uint32_t TIM_Select)
Configures the routing interface to select which Timer to be routed.

Detailed Description

RI Initialization and Configuration functions.

 ===============================================================================
        ##### RI Initialization and Configuration functions #####
 ===============================================================================

Function Documentation

void SYSCFG_RIChannelSpeedConfig | ( | uint32_t | RI_Channel,
 |  | uint32_t | RI_ChannelSpeed
 | ) |  |

Configures the ADC channels speed.

Parameters:
RI_Channel selects the channel. This parameter can be one of the following values:

  • RI_Channel_3: Channel 3 is selected.
  • RI_Channel_8: Channel 8 is selected.
  • RI_Channel_13: Channel 13 is selected.
RI_ChannelSpeed,: The speed of the selected ADC channel This parameter can be: RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.
Return values:
None

Definition at line 385 of file stm32l1xx_syscfg.c.

References COMP, IS_RI_CHANNEL, IS_RI_CHANNELSPEED, and RI_ChannelSpeed_Fast.

void SYSCFG_RIHysteresisConfig | ( | uint8_t | RI_Port,
 |  | uint16_t | RI_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.

When hysteresis is disabled, it is possible to read the corresponding port with a trigger level of VDDIO/2.

Parameters:
RI_Port,: selects the GPIO Port. This parameter can be one of the following values:

  • RI_PortA: Port A is selected
  • RI_PortB: Port B is selected
  • RI_PortC: Port C is selected
  • RI_PortD: Port D is selected
  • RI_PortE: Port E is selected
  • RI_PortF: Port F is selected
  • RI_PortG: Port G is selected
RI_Pin | : Selects the pin(s) on which to enable or disable hysteresis. This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
NewState | new state of the Hysteresis. This parameter can be: ENABLE so the Hysteresis is on or DISABLE so the Hysteresis is off
Return values:
None

Definition at line 528 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RI_PIN, IS_RI_PORT, RI, RI_PortA, RI_PortB, RI_PortC, RI_PortD, RI_PortE, and RI_PortF.

void SYSCFG_RIIOSwitchConfig | ( | uint32_t | RI_IOSwitch,
 |  | FunctionalState | NewState
 | ) |  |

Close or Open the routing interface Input Output switches.

Parameters:
RI_IOSwitch,: selects the I/O analog switch number. This parameter can be one of the following values:
RI_IOSwitch_CH0 | --> RI_IOSwitch_CH15.
RI_IOSwitch_CH18 | --> RI_IOSwitch_CH25.
RI_IOSwitch_GR10_1 | --> RI_IOSwitch_GR10_4.
RI_IOSwitch_GR6_1 | --> RI_IOSwitch_GR6_2.
RI_IOSwitch_GR5_1 | --> RI_IOSwitch_GR5_3.
RI_IOSwitch_GR4_1 | --> RI_IOSwitch_GR4_3.
RI_IOSwitch_VCOMP | RI_IOSwitch_CH27
RI_IOSwitch_CH28 | --> RI_IOSwitch_CH30
RI_IOSwitch_GR10_1 | --> RI_IOSwitch_GR10_4
RI_IOSwitch_GR6_1
RI_IOSwitch_GR6_2
RI_IOSwitch_GR5_1 | --> RI_IOSwitch_GR5_3
RI_IOSwitch_GR4_1 | --> RI_IOSwitch_GR4_4
RI_IOSwitch_CH0b | --> RI_IOSwitch_CH3b
RI_IOSwitch_CH6b | --> RI_IOSwitch_CH12b
RI_IOSwitch_GR6_3
RI_IOSwitch_GR6_4
RI_IOSwitch_GR5_4
NewState,: New state of the analog switch. This parameter can be ENABLE so the Input Output switch is closed or DISABLE so the Input Output switch is open.
Return values:
None

Definition at line 433 of file stm32l1xx_syscfg.c.

References DISABLE, IS_RI_IOSWITCH, and RI.

void SYSCFG_RIResistorConfig | ( | uint32_t | RI_Resistor,
 |  | FunctionalState | NewState
 | ) |  |

Configures the Pull-up and Pull-down Resistors.

Parameters:
RI_Resistor selects the resistor to connect. This parameter can be one of the following values:

  • RI_Resistor_10KPU: 10K pull-up resistor.
  • RI_Resistor_400KPU: 400K pull-up resistor.
  • RI_Resistor_10KPD: 10K pull-down resistor.
  • RI_Resistor_400KPD: 400K pull-down resistor.
NewState,: New state of the analog switch associated to the selected resistor. This parameter can be: ENABLE so the selected resistor is connected or DISABLE so the selected resistor is disconnected.
Note:
To avoid extra power consumption, only one resistor should be enabled at a time.
Return values:
None

Definition at line 354 of file stm32l1xx_syscfg.c.

References COMP, DISABLE, IS_FUNCTIONAL_STATE, and IS_RI_RESISTOR.

void SYSCFG_RISwitchControlModeCmd ( FunctionalState NewState )

Enable or disable the switch control mode.

Parameters:
NewState,: New state of the switch control mode. This parameter can be ENABLE: ADC analog switches closed if the corresponding I/O switch is also closed. When using COMP1, switch control mode must be enabled. or DISABLE: ADC analog switches open or controlled by the ADC interface. When using the ADC for acquisition, switch control mode must be disabled.
Note:
COMP1 comparator and ADC cannot be used at the same time since they share the ADC switch matrix.
Return values:
None

Definition at line 488 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, RI, and RI_ASCR1_SCM.

void SYSCFG_RITIMInputCaptureConfig | ( | uint32_t | RI_InputCapture,
 |  | uint32_t | RI_InputCaptureRouting
 | ) |  |

Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.

Parameters:
RI_InputCapture selects which input capture to be routed. This parameter can be one (or combination) of the following parameters:

  • RI_InputCapture_IC1: Input capture 1 is selected.
  • RI_InputCapture_IC2: Input capture 2 is selected.
  • RI_InputCapture_IC3: Input capture 3 is selected.
  • RI_InputCapture_IC4: Input capture 4 is selected.
RI_InputCaptureRouting,: selects which pin to be routed to Input Capture. This parameter can be one of the following values:
RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15 e.g. SYSCFG_RITIMSelect(TIM_Select_TIM2) SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1) allows routing of Input capture IC1 of TIM2 to PA4. For details about correspondence between RI_InputCaptureRouting_x and I/O pins refer to the parameters' description in the header file or refer to the product reference manual.
Note:
Input capture selection bits are not reset by this function. To reset input capture selection bits, use SYSCFG_RIDeInit() function.
The I/O should be configured in alternate function mode (AF14) using GPIO_PinAFConfig() function.
Return values:
None.

Definition at line 283 of file stm32l1xx_syscfg.c.

References IC_ROUTING_MASK, IS_RI_INPUTCAPTURE, IS_RI_INPUTCAPTURE_ROUTING, RI, RI_InputCapture_IC1, RI_InputCapture_IC2, RI_InputCapture_IC3, and RI_InputCapture_IC4.

void SYSCFG_RITIMSelect ( uint32_t TIM_Select )

Configures the routing interface to select which Timer to be routed.

Note:
Routing capability can be applied only on one of the three timers (TIM2, TIM3 or TIM4) at a time.
Parameters:
TIM_Select,: Timer select. This parameter can be one of the following values:

  • TIM_Select_None: No timer selected and default Timer mapping is enabled.
  • TIM_Select_TIM2: Timer 2 Input Captures to be routed.
  • TIM_Select_TIM3: Timer 3 Input Captures to be routed.
  • TIM_Select_TIM4: Timer 4 Input Captures to be routed.
Return values:
None.

Definition at line 238 of file stm32l1xx_syscfg.c.

References IS_RI_TIM, RI, and TIM_SELECT_MASK.


STM32L1xx Standard Peripherals Firmware Library: SYSCFG

Modules | Defines | Functions

SYSCFG

STM32L1xx_StdPeriph_Driver

SYSCFG driver modules. More...

Modules

SYSCFG_Exported_Constants
SYSCFG_Private_Functions

Defines

#define | IC_ROUTING_MASK ((uint32_t)0x0000000F)
#define | TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF)

Functions

void | SYSCFG_DeInit (void)
Deinitializes the SYSCFG registers to their default reset values.
void | SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
uint32_t | SYSCFG_GetBootMode (void)
Returns the boot mode as configured by user.
void | SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
Changes the mapping of the specified memory.
void | SYSCFG_RIChannelSpeedConfig (uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
Configures the ADC channels speed.
void | SYSCFG_RIDeInit (void)
Deinitializes the RI registers to their default reset values.
void | SYSCFG_RIHysteresisConfig (uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState)
Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.
void | SYSCFG_RIIOSwitchConfig (uint32_t RI_IOSwitch, FunctionalState NewState)
Close or Open the routing interface Input Output switches.
void | SYSCFG_RIResistorConfig (uint32_t RI_Resistor, FunctionalState NewState)
Configures the Pull-up and Pull-down Resistors.
void | SYSCFG_RISwitchControlModeCmd (FunctionalState NewState)
Enable or disable the switch control mode.
void | SYSCFG_RITIMInputCaptureConfig (uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.
void | SYSCFG_RITIMSelect (uint32_t TIM_Select)
Configures the routing interface to select which Timer to be routed.
void | SYSCFG_USBPuCmd (FunctionalState NewState)
Control the internal pull-up on USB DP line.

Detailed Description

SYSCFG driver modules.

Define Documentation

#define IC_ROUTING_MASK ((uint32_t)0x0000000F)

Input Capture routing mask

Definition at line 82 of file stm32l1xx_syscfg.c.

Referenced by SYSCFG_RITIMInputCaptureConfig().

#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF)

TIM select mask

Definition at line 81 of file stm32l1xx_syscfg.c.

Referenced by SYSCFG_RITIMSelect().

Function Documentation

void SYSCFG_DeInit ( void )

Deinitializes the SYSCFG registers to their default reset values.

Parameters:
None.
Return values:
None. : MEMRMP bits are not reset by APB2 reset.

Definition at line 111 of file stm32l1xx_syscfg.c.

References DISABLE, ENABLE, RCC_APB2Periph_SYSCFG, and RCC_APB2PeriphResetCmd().

void SYSCFG_EXTILineConfig | ( | uint8_t | EXTI_PortSourceGPIOx,
 |  | uint8_t | EXTI_PinSourcex
 | ) |  |

Selects the GPIO pin used as EXTI Line.

Parameters:
EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for EXTI lines where x can be (A, B, C, D, E, F, G or H).
EXTI_PinSourcex,: specifies the EXTI line to be configured. This parameter can be EXTI_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 197 of file stm32l1xx_syscfg.c.

References IS_EXTI_PIN_SOURCE, IS_EXTI_PORT_SOURCE, and SYSCFG.

uint32_t SYSCFG_GetBootMode ( void )

Returns the boot mode as configured by user.

Parameters:
None.
Return values:
The boot mode as configured by user. The returned value can be one of the following values:

  • 0x00000000: Boot is configured in Main Flash memory
  • 0x00000100: Boot is configured in System Flash memory
  • 0x00000200: Boot is configured in FSMC memory
  • 0x00000300: Boot is configured in Embedded SRAM memory

Definition at line 160 of file stm32l1xx_syscfg.c.

References SYSCFG, and SYSCFG_MEMRMP_BOOT_MODE.

void SYSCFG_MemoryRemapConfig ( uint8_t SYSCFG_MemoryRemap )

Changes the mapping of the specified memory.

Parameters:
SYSCFG_Memory,: selects the memory remapping. This parameter can be one of the following values:

  • SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000
  • SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
Return values:
None

Definition at line 143 of file stm32l1xx_syscfg.c.

References IS_SYSCFG_MEMORY_REMAP_CONFING, and SYSCFG.

void SYSCFG_RIChannelSpeedConfig | ( | uint32_t | RI_Channel,
 |  | uint32_t | RI_ChannelSpeed
 | ) |  |

Configures the ADC channels speed.

Parameters:
RI_Channel selects the channel. This parameter can be one of the following values:

  • RI_Channel_3: Channel 3 is selected.
  • RI_Channel_8: Channel 8 is selected.
  • RI_Channel_13: Channel 13 is selected.
RI_ChannelSpeed,: The speed of the selected ADC channel This parameter can be: RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.
Return values:
None

Definition at line 385 of file stm32l1xx_syscfg.c.

References COMP, IS_RI_CHANNEL, IS_RI_CHANNELSPEED, and RI_ChannelSpeed_Fast.

void SYSCFG_RIDeInit ( void )

Deinitializes the RI registers to their default reset values.

Parameters:
None.
Return values:
None.

< Set RI->ICR to reset value

< Set RI->ASCR1 to reset value

< Set RI->ASCR2 to reset value

< Set RI->HYSCR1 to reset value

< Set RI->HYSCR2 to reset value

< Set RI->HYSCR3 to reset value

< Set RI->HYSCR4 to reset value

Definition at line 122 of file stm32l1xx_syscfg.c.

References RI.

void SYSCFG_RIHysteresisConfig | ( | uint8_t | RI_Port,
 |  | uint16_t | RI_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.

When hysteresis is disabled, it is possible to read the corresponding port with a trigger level of VDDIO/2.

Parameters:
RI_Port,: selects the GPIO Port. This parameter can be one of the following values:

  • RI_PortA: Port A is selected
  • RI_PortB: Port B is selected
  • RI_PortC: Port C is selected
  • RI_PortD: Port D is selected
  • RI_PortE: Port E is selected
  • RI_PortF: Port F is selected
  • RI_PortG: Port G is selected
RI_Pin | : Selects the pin(s) on which to enable or disable hysteresis. This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
NewState | new state of the Hysteresis. This parameter can be: ENABLE so the Hysteresis is on or DISABLE so the Hysteresis is off
Return values:
None

Definition at line 528 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_RI_PIN, IS_RI_PORT, RI, RI_PortA, RI_PortB, RI_PortC, RI_PortD, RI_PortE, and RI_PortF.

void SYSCFG_RIIOSwitchConfig | ( | uint32_t | RI_IOSwitch,
 |  | FunctionalState | NewState
 | ) |  |

Close or Open the routing interface Input Output switches.

Parameters:
RI_IOSwitch,: selects the I/O analog switch number. This parameter can be one of the following values:
RI_IOSwitch_CH0 | --> RI_IOSwitch_CH15.
RI_IOSwitch_CH18 | --> RI_IOSwitch_CH25.
RI_IOSwitch_GR10_1 | --> RI_IOSwitch_GR10_4.
RI_IOSwitch_GR6_1 | --> RI_IOSwitch_GR6_2.
RI_IOSwitch_GR5_1 | --> RI_IOSwitch_GR5_3.
RI_IOSwitch_GR4_1 | --> RI_IOSwitch_GR4_3.
RI_IOSwitch_VCOMP | RI_IOSwitch_CH27
RI_IOSwitch_CH28 | --> RI_IOSwitch_CH30
RI_IOSwitch_GR10_1 | --> RI_IOSwitch_GR10_4
RI_IOSwitch_GR6_1
RI_IOSwitch_GR6_2
RI_IOSwitch_GR5_1 | --> RI_IOSwitch_GR5_3
RI_IOSwitch_GR4_1 | --> RI_IOSwitch_GR4_4
RI_IOSwitch_CH0b | --> RI_IOSwitch_CH3b
RI_IOSwitch_CH6b | --> RI_IOSwitch_CH12b
RI_IOSwitch_GR6_3
RI_IOSwitch_GR6_4
RI_IOSwitch_GR5_4
NewState,: New state of the analog switch. This parameter can be ENABLE so the Input Output switch is closed or DISABLE so the Input Output switch is open.
Return values:
None

Definition at line 433 of file stm32l1xx_syscfg.c.

References DISABLE, IS_RI_IOSWITCH, and RI.

void SYSCFG_RIResistorConfig | ( | uint32_t | RI_Resistor,
 |  | FunctionalState | NewState
 | ) |  |

Configures the Pull-up and Pull-down Resistors.

Parameters:
RI_Resistor selects the resistor to connect. This parameter can be one of the following values:

  • RI_Resistor_10KPU: 10K pull-up resistor.
  • RI_Resistor_400KPU: 400K pull-up resistor.
  • RI_Resistor_10KPD: 10K pull-down resistor.
  • RI_Resistor_400KPD: 400K pull-down resistor.
NewState,: New state of the analog switch associated to the selected resistor. This parameter can be: ENABLE so the selected resistor is connected or DISABLE so the selected resistor is disconnected.
Note:
To avoid extra power consumption, only one resistor should be enabled at a time.
Return values:
None

Definition at line 354 of file stm32l1xx_syscfg.c.

References COMP, DISABLE, IS_FUNCTIONAL_STATE, and IS_RI_RESISTOR.

void SYSCFG_RISwitchControlModeCmd ( FunctionalState NewState )

Enable or disable the switch control mode.

Parameters:
NewState,: New state of the switch control mode. This parameter can be ENABLE: ADC analog switches closed if the corresponding I/O switch is also closed. When using COMP1, switch control mode must be enabled. or DISABLE: ADC analog switches open or controlled by the ADC interface. When using the ADC for acquisition, switch control mode must be disabled.
Note:
COMP1 comparator and ADC cannot be used at the same time since they share the ADC switch matrix.
Return values:
None

Definition at line 488 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, RI, and RI_ASCR1_SCM.

void SYSCFG_RITIMInputCaptureConfig | ( | uint32_t | RI_InputCapture,
 |  | uint32_t | RI_InputCaptureRouting
 | ) |  |

Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.

Parameters:
RI_InputCapture selects which input capture to be routed. This parameter can be one (or combination) of the following parameters:

  • RI_InputCapture_IC1: Input capture 1 is selected.
  • RI_InputCapture_IC2: Input capture 2 is selected.
  • RI_InputCapture_IC3: Input capture 3 is selected.
  • RI_InputCapture_IC4: Input capture 4 is selected.
RI_InputCaptureRouting,: selects which pin to be routed to Input Capture. This parameter can be one of the following values:
RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15 e.g. SYSCFG_RITIMSelect(TIM_Select_TIM2) SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1) allows routing of Input capture IC1 of TIM2 to PA4. For details about correspondence between RI_InputCaptureRouting_x and I/O pins refer to the parameters' description in the header file or refer to the product reference manual.
Note:
Input capture selection bits are not reset by this function. To reset input capture selection bits, use SYSCFG_RIDeInit() function.
The I/O should be configured in alternate function mode (AF14) using GPIO_PinAFConfig() function.
Return values:
None.

Definition at line 283 of file stm32l1xx_syscfg.c.

References IC_ROUTING_MASK, IS_RI_INPUTCAPTURE, IS_RI_INPUTCAPTURE_ROUTING, RI, RI_InputCapture_IC1, RI_InputCapture_IC2, RI_InputCapture_IC3, and RI_InputCapture_IC4.

void SYSCFG_RITIMSelect ( uint32_t TIM_Select )

Configures the routing interface to select which Timer to be routed.

Note:
Routing capability can be applied only on one of the three timers (TIM2, TIM3 or TIM4) at a time.
Parameters:
TIM_Select,: Timer select. This parameter can be one of the following values:

  • TIM_Select_None: No timer selected and default Timer mapping is enabled.
  • TIM_Select_TIM2: Timer 2 Input Captures to be routed.
  • TIM_Select_TIM3: Timer 3 Input Captures to be routed.
  • TIM_Select_TIM4: Timer 4 Input Captures to be routed.
Return values:
None.

Definition at line 238 of file stm32l1xx_syscfg.c.

References IS_RI_TIM, RI, and TIM_SELECT_MASK.

void SYSCFG_USBPuCmd ( FunctionalState NewState )

Control the internal pull-up on USB DP line.

Parameters:
NewState,: New state of the internal pull-up on USB DP line. This parameter can be ENABLE: Connect internal pull-up on USB DP line. or DISABLE: Disconnect internal pull-up on USB DP line.
Return values:
None

Definition at line 172 of file stm32l1xx_syscfg.c.

References DISABLE, IS_FUNCTIONAL_STATE, SYSCFG, and SYSCFG_PMC_USB_PU.


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_and_PWM_modes

Defines

TIM_Output_Compare_and_PWM_modes

TIM_Exported_constants

Defines

#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_OCM(MODE)
#define | TIM_OCMode_Active ((uint16_t)0x0010)
#define | TIM_OCMode_Inactive ((uint16_t)0x0020)
#define | TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define | TIM_OCMode_PWM2 ((uint16_t)0x0070)
#define | TIM_OCMode_Timing ((uint16_t)0x0000)
#define | TIM_OCMode_Toggle ((uint16_t)0x0030)

Define Documentation

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMode_Timing) || \
                              ((MODE) == TIM_OCMode_Active) || \
                              ((MODE) == TIM_OCMode_Inactive) || \
                              ((MODE) == TIM_OCMode_Toggle)|| \
                              ((MODE) == TIM_OCMode_PWM1) || \
                              ((MODE) == TIM_OCMode_PWM2))

Definition at line 187 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OC4Init().

#define IS_TIM_OCM ( MODE )
Value:
(((MODE) == TIM_OCMode_Timing) || \
                          ((MODE) == TIM_OCMode_Active) || \
                          ((MODE) == TIM_OCMode_Inactive) || \
                          ((MODE) == TIM_OCMode_Toggle)|| \
                          ((MODE) == TIM_OCMode_PWM1) || \
                          ((MODE) == TIM_OCMode_PWM2) ||        \
                          ((MODE) == TIM_ForcedAction_Active) || \
                          ((MODE) == TIM_ForcedAction_InActive))

Definition at line 193 of file stm32l1xx_tim.h.

Referenced by TIM_SelectOCxM().

#define TIM_OCMode_Active ((uint16_t)0x0010)

Definition at line 182 of file stm32l1xx_tim.h.

#define TIM_OCMode_Inactive ((uint16_t)0x0020)

Definition at line 183 of file stm32l1xx_tim.h.

#define TIM_OCMode_PWM1 ((uint16_t)0x0060)

Definition at line 185 of file stm32l1xx_tim.h.

#define TIM_OCMode_PWM2 ((uint16_t)0x0070)

Definition at line 186 of file stm32l1xx_tim.h.

#define TIM_OCMode_Timing ((uint16_t)0x0000)

Definition at line 181 of file stm32l1xx_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OCMode_Toggle ((uint16_t)0x0030)

Definition at line 184 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_One_Pulse_Mode

Defines

TIM_One_Pulse_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_OPM_MODE(MODE)
#define | TIM_OPMode_Repetitive ((uint16_t)0x0000)
#define | TIM_OPMode_Single ((uint16_t)0x0008)

Define Documentation

#define IS_TIM_OPM_MODE ( MODE )
Value:
(((MODE) == TIM_OPMode_Single) || \
                               ((MODE) == TIM_OPMode_Repetitive))

Definition at line 211 of file stm32l1xx_tim.h.

Referenced by TIM_SelectOnePulseMode().

#define TIM_OPMode_Repetitive ((uint16_t)0x0000)

Definition at line 210 of file stm32l1xx_tim.h.

#define TIM_OPMode_Single ((uint16_t)0x0008)

Definition at line 209 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Channel

Defines

TIM_Channel

TIM_Exported_constants

Defines

#define | IS_TIM_CHANNEL(CHANNEL)
#define | IS_TIM_PWMI_CHANNEL(CHANNEL)
#define | TIM_Channel_1 ((uint16_t)0x0000)
#define | TIM_Channel_2 ((uint16_t)0x0004)
#define | TIM_Channel_3 ((uint16_t)0x0008)
#define | TIM_Channel_4 ((uint16_t)0x000C)

Define Documentation

#define IS_TIM_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == TIM_Channel_1) || \
                                 ((CHANNEL) == TIM_Channel_2) || \
                                 ((CHANNEL) == TIM_Channel_3) || \
                                 ((CHANNEL) == TIM_Channel_4))

Definition at line 226 of file stm32l1xx_tim.h.

#define IS_TIM_PWMI_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == TIM_Channel_1) || \
                                      ((CHANNEL) == TIM_Channel_2))

Definition at line 231 of file stm32l1xx_tim.h.

#define TIM_Channel_1 ((uint16_t)0x0000)

Definition at line 221 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), TIM_PWMIConfig(), and TIM_SelectOCxM().

#define TIM_Channel_2 ((uint16_t)0x0004)

Definition at line 222 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit().

#define TIM_Channel_3 ((uint16_t)0x0008)

Definition at line 223 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), and TIM_SelectOCxM().

#define TIM_Channel_4 ((uint16_t)0x000C)

Definition at line 224 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Clock_Division_CKD

Defines

TIM_Clock_Division_CKD

TIM_Exported_constants

Defines

#define | IS_TIM_CKD_DIV(DIV)
#define | TIM_CKD_DIV1 ((uint16_t)0x0000)
#define | TIM_CKD_DIV2 ((uint16_t)0x0100)
#define | TIM_CKD_DIV4 ((uint16_t)0x0200)

Define Documentation

#define IS_TIM_CKD_DIV ( DIV )
Value:
(((DIV) == TIM_CKD_DIV1) || \
                             ((DIV) == TIM_CKD_DIV2) || \
                             ((DIV) == TIM_CKD_DIV4))

Definition at line 245 of file stm32l1xx_tim.h.

Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().

#define TIM_CKD_DIV1 ((uint16_t)0x0000)

Definition at line 242 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseStructInit().

#define TIM_CKD_DIV2 ((uint16_t)0x0100)

Definition at line 243 of file stm32l1xx_tim.h.

#define TIM_CKD_DIV4 ((uint16_t)0x0200)

Definition at line 244 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Counter_Mode

Defines

TIM_Counter_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_COUNTER_MODE(MODE)
#define | TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define | TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define | TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
#define | TIM_CounterMode_Down ((uint16_t)0x0010)
#define | TIM_CounterMode_Up ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_COUNTER_MODE ( MODE )
Value:
(((MODE) == TIM_CounterMode_Up) ||  \
                                   ((MODE) == TIM_CounterMode_Down) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned3))

Definition at line 261 of file stm32l1xx_tim.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)

Definition at line 258 of file stm32l1xx_tim.h.

#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)

Definition at line 259 of file stm32l1xx_tim.h.

#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)

Definition at line 260 of file stm32l1xx_tim.h.

#define TIM_CounterMode_Down ((uint16_t)0x0010)

Definition at line 257 of file stm32l1xx_tim.h.

#define TIM_CounterMode_Up ((uint16_t)0x0000)

Definition at line 256 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseStructInit().


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_Polarity

Defines

TIM_Output_Compare_Polarity

TIM_Exported_constants

Defines

#define | IS_TIM_OC_POLARITY(POLARITY)
#define | TIM_OCPolarity_High ((uint16_t)0x0000)
#define | TIM_OCPolarity_Low ((uint16_t)0x0002)

Define Documentation

#define IS_TIM_OC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCPolarity_High) || \
                                      ((POLARITY) == TIM_OCPolarity_Low))

Definition at line 276 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC1PolarityConfig(), TIM_OC2Init(), TIM_OC2PolarityConfig(), TIM_OC3Init(), TIM_OC3PolarityConfig(), TIM_OC4Init(), and TIM_OC4PolarityConfig().

#define TIM_OCPolarity_High ((uint16_t)0x0000)

Definition at line 274 of file stm32l1xx_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OCPolarity_Low ((uint16_t)0x0002)

Definition at line 275 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_state

Defines

TIM_Output_Compare_state

TIM_Exported_constants

Defines

#define | IS_TIM_OUTPUT_STATE(STATE)
#define | TIM_OutputState_Disable ((uint16_t)0x0000)
#define | TIM_OutputState_Enable ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_OutputState_Disable) || \
                                    ((STATE) == TIM_OutputState_Enable))

Definition at line 289 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OC4Init().

#define TIM_OutputState_Disable ((uint16_t)0x0000)

Definition at line 287 of file stm32l1xx_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OutputState_Enable ((uint16_t)0x0001)

Definition at line 288 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Capture_Compare_state

Defines

TIM_Capture_Compare_state

TIM_Exported_constants

Defines

#define | IS_TIM_CCX(CCX)
#define | TIM_CCx_Disable ((uint16_t)0x0000)
#define | TIM_CCx_Enable ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_CCX ( CCX )
Value:
(((CCX) == TIM_CCx_Enable) || \
                         ((CCX) == TIM_CCx_Disable))

Definition at line 302 of file stm32l1xx_tim.h.

Referenced by TIM_CCxCmd().

#define TIM_CCx_Disable ((uint16_t)0x0000)

Definition at line 301 of file stm32l1xx_tim.h.

#define TIM_CCx_Enable ((uint16_t)0x0001)

Definition at line 300 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Input_Capture_Polarity

Defines

TIM_Input_Capture_Polarity

TIM_Exported_constants

Defines

#define | IS_TIM_IC_POLARITY(POLARITY)
#define | TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define | TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define | TIM_ICPolarity_Rising ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_IC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ICPolarity_Rising) || \
                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
                                      ((POLARITY) == TIM_ICPolarity_BothEdge))

Definition at line 315 of file stm32l1xx_tim.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ICInit(), and TIM_TIxExternalClockConfig().

#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)

Definition at line 314 of file stm32l1xx_tim.h.

#define TIM_ICPolarity_Falling ((uint16_t)0x0002)

Definition at line 313 of file stm32l1xx_tim.h.

Referenced by TIM_PWMIConfig().

#define TIM_ICPolarity_Rising ((uint16_t)0x0000)

Definition at line 312 of file stm32l1xx_tim.h.

Referenced by TIM_ICStructInit(), and TIM_PWMIConfig().


STM32L1xx Standard Peripherals Firmware Library: TIM_Input_Capture_Selection

Defines

TIM_Input_Capture_Selection

TIM_Exported_constants

Defines

#define | IS_TIM_IC_SELECTION(SELECTION)
#define | TIM_ICSelection_DirectTI ((uint16_t)0x0001)
#define | TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
#define | TIM_ICSelection_TRC ((uint16_t)0x0003)

Define Documentation

#define IS_TIM_IC_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_ICSelection_DirectTI) || \
                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
                                        ((SELECTION) == TIM_ICSelection_TRC))

Definition at line 331 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit().

#define TIM_ICSelection_DirectTI ((uint16_t)0x0001)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 326 of file stm32l1xx_tim.h.

Referenced by TIM_ICStructInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively.

Definition at line 328 of file stm32l1xx_tim.h.

Referenced by TIM_PWMIConfig().

#define TIM_ICSelection_TRC ((uint16_t)0x0003)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC.

Definition at line 330 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Input_Capture_Prescaler

Defines

TIM_Input_Capture_Prescaler

TIM_Exported_constants

Defines

#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | TIM_ICPSC_DIV1 ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV2 ((uint16_t)0x0004)
#define | TIM_ICPSC_DIV4 ((uint16_t)0x0008)
#define | TIM_ICPSC_DIV8 ((uint16_t)0x000C)

Define Documentation

#define IS_TIM_IC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV8))

Definition at line 346 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

#define TIM_ICPSC_DIV1 ((uint16_t)0x0000)

Capture performed each time an edge is detected on the capture input.

Definition at line 342 of file stm32l1xx_tim.h.

Referenced by TIM_ICStructInit().

#define TIM_ICPSC_DIV2 ((uint16_t)0x0004)

Capture performed once every 2 events.

Definition at line 343 of file stm32l1xx_tim.h.

#define TIM_ICPSC_DIV4 ((uint16_t)0x0008)

Capture performed once every 4 events.

Definition at line 344 of file stm32l1xx_tim.h.

#define TIM_ICPSC_DIV8 ((uint16_t)0x000C)

Capture performed once every 8 events.

Definition at line 345 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_interrupt_sources

Defines

TIM_interrupt_sources

TIM_Exported_constants

Defines

#define | IS_TIM_GET_IT(IT)
#define | IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
#define | TIM_IT_CC1 ((uint16_t)0x0002)
#define | TIM_IT_CC2 ((uint16_t)0x0004)
#define | TIM_IT_CC3 ((uint16_t)0x0008)
#define | TIM_IT_CC4 ((uint16_t)0x0010)
#define | TIM_IT_Trigger ((uint16_t)0x0040)
#define | TIM_IT_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_GET_IT ( IT )
Value:
(((IT) == TIM_IT_Update) || \
                           ((IT) == TIM_IT_CC1) || \
                           ((IT) == TIM_IT_CC2) || \
                           ((IT) == TIM_IT_CC3) || \
                           ((IT) == TIM_IT_CC4) || \
                           ((IT) == TIM_IT_Trigger))

Definition at line 366 of file stm32l1xx_tim.h.

Referenced by TIM_GetITStatus().

#define IS_TIM_IT ( IT ) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))

Definition at line 364 of file stm32l1xx_tim.h.

Referenced by TIM_ClearITPendingBit(), and TIM_ITConfig().

#define TIM_IT_CC1 ((uint16_t)0x0002)

Definition at line 359 of file stm32l1xx_tim.h.

#define TIM_IT_CC2 ((uint16_t)0x0004)

Definition at line 360 of file stm32l1xx_tim.h.

#define TIM_IT_CC3 ((uint16_t)0x0008)

Definition at line 361 of file stm32l1xx_tim.h.

#define TIM_IT_CC4 ((uint16_t)0x0010)

Definition at line 362 of file stm32l1xx_tim.h.

#define TIM_IT_Trigger ((uint16_t)0x0040)

Definition at line 363 of file stm32l1xx_tim.h.

#define TIM_IT_Update ((uint16_t)0x0001)

Definition at line 358 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_DMA_Base_address

Defines

TIM_DMA_Base_address

TIM_Exported_constants

Defines

#define | IS_TIM_DMA_BASE(BASE)
#define | TIM_DMABase_ARR ((uint16_t)0x000B)
#define | TIM_DMABase_CCER ((uint16_t)0x0008)
#define | TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define | TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define | TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define | TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define | TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define | TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define | TIM_DMABase_CNT ((uint16_t)0x0009)
#define | TIM_DMABase_CR1 ((uint16_t)0x0000)
#define | TIM_DMABase_CR2 ((uint16_t)0x0001)
#define | TIM_DMABase_DCR ((uint16_t)0x0012)
#define | TIM_DMABase_DIER ((uint16_t)0x0003)
#define | TIM_DMABase_EGR ((uint16_t)0x0005)
#define | TIM_DMABase_OR ((uint16_t)0x0013)
#define | TIM_DMABase_PSC ((uint16_t)0x000A)
#define | TIM_DMABase_SMCR ((uint16_t)0x0002)
#define | TIM_DMABase_SR ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_DMA_BASE ( BASE )
Value:
(((BASE) == TIM_DMABase_CR1) || \
                               ((BASE) == TIM_DMABase_CR2) || \
                               ((BASE) == TIM_DMABase_SMCR) || \
                               ((BASE) == TIM_DMABase_DIER) || \
                               ((BASE) == TIM_DMABase_SR) || \
                               ((BASE) == TIM_DMABase_EGR) || \
                               ((BASE) == TIM_DMABase_CCMR1) || \
                               ((BASE) == TIM_DMABase_CCMR2) || \
                               ((BASE) == TIM_DMABase_CCER) || \
                               ((BASE) == TIM_DMABase_CNT) || \
                               ((BASE) == TIM_DMABase_PSC) || \
                               ((BASE) == TIM_DMABase_ARR) || \
                               ((BASE) == TIM_DMABase_CCR1) || \
                               ((BASE) == TIM_DMABase_CCR2) || \
                               ((BASE) == TIM_DMABase_CCR3) || \
                               ((BASE) == TIM_DMABase_CCR4) || \
                               ((BASE) == TIM_DMABase_DCR) || \
                               ((BASE) == TIM_DMABase_OR))

Definition at line 398 of file stm32l1xx_tim.h.

Referenced by TIM_DMAConfig().

#define TIM_DMABase_ARR ((uint16_t)0x000B)

Definition at line 391 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCER ((uint16_t)0x0008)

Definition at line 388 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)

Definition at line 386 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)

Definition at line 387 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCR1 ((uint16_t)0x000D)

Definition at line 392 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCR2 ((uint16_t)0x000E)

Definition at line 393 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCR3 ((uint16_t)0x000F)

Definition at line 394 of file stm32l1xx_tim.h.

#define TIM_DMABase_CCR4 ((uint16_t)0x0010)

Definition at line 395 of file stm32l1xx_tim.h.

#define TIM_DMABase_CNT ((uint16_t)0x0009)

Definition at line 389 of file stm32l1xx_tim.h.

#define TIM_DMABase_CR1 ((uint16_t)0x0000)

Definition at line 380 of file stm32l1xx_tim.h.

#define TIM_DMABase_CR2 ((uint16_t)0x0001)

Definition at line 381 of file stm32l1xx_tim.h.

#define TIM_DMABase_DCR ((uint16_t)0x0012)

Definition at line 396 of file stm32l1xx_tim.h.

#define TIM_DMABase_DIER ((uint16_t)0x0003)

Definition at line 383 of file stm32l1xx_tim.h.

#define TIM_DMABase_EGR ((uint16_t)0x0005)

Definition at line 385 of file stm32l1xx_tim.h.

#define TIM_DMABase_OR ((uint16_t)0x0013)

Definition at line 397 of file stm32l1xx_tim.h.

#define TIM_DMABase_PSC ((uint16_t)0x000A)

Definition at line 390 of file stm32l1xx_tim.h.

#define TIM_DMABase_SMCR ((uint16_t)0x0002)

Definition at line 382 of file stm32l1xx_tim.h.

#define TIM_DMABase_SR ((uint16_t)0x0004)

Definition at line 384 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_DMA_Burst_Length

Defines

TIM_DMA_Burst_Length

TIM_Exported_constants

Defines

#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define | TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define | TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define | TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define | TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define | TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define | TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define | TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define | TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
#define | TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define | TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define | TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define | TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define | TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define | TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define | TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define | TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define | TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)

Define Documentation

#define IS_TIM_DMA_LENGTH ( LENGTH )
Value:
(((LENGTH) == TIM_DMABurstLength_1Transfer) || \
                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))

Definition at line 442 of file stm32l1xx_tim.h.

Referenced by TIM_DMAConfig().

#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)

Definition at line 433 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)

Definition at line 434 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)

Definition at line 435 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)

Definition at line 436 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)

Definition at line 437 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)

Definition at line 438 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)

Definition at line 439 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)

Definition at line 440 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)

Definition at line 441 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)

Definition at line 424 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)

Definition at line 425 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)

Definition at line 426 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)

Definition at line 427 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)

Definition at line 428 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)

Definition at line 429 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)

Definition at line 430 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)

Definition at line 431 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)

Definition at line 432 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_DMA_sources

Defines

TIM_DMA_sources

TIM_Exported_constants

Defines

#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
#define | TIM_DMA_CC1 ((uint16_t)0x0200)
#define | TIM_DMA_CC2 ((uint16_t)0x0400)
#define | TIM_DMA_CC3 ((uint16_t)0x0800)
#define | TIM_DMA_CC4 ((uint16_t)0x1000)
#define | TIM_DMA_Trigger ((uint16_t)0x4000)
#define | TIM_DMA_Update ((uint16_t)0x0100)

Define Documentation

#define IS_TIM_DMA_SOURCE ( SOURCE ) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))

Definition at line 474 of file stm32l1xx_tim.h.

Referenced by TIM_DMACmd().

#define TIM_DMA_CC1 ((uint16_t)0x0200)

Definition at line 469 of file stm32l1xx_tim.h.

#define TIM_DMA_CC2 ((uint16_t)0x0400)

Definition at line 470 of file stm32l1xx_tim.h.

#define TIM_DMA_CC3 ((uint16_t)0x0800)

Definition at line 471 of file stm32l1xx_tim.h.

#define TIM_DMA_CC4 ((uint16_t)0x1000)

Definition at line 472 of file stm32l1xx_tim.h.

#define TIM_DMA_Trigger ((uint16_t)0x4000)

Definition at line 473 of file stm32l1xx_tim.h.

#define TIM_DMA_Update ((uint16_t)0x0100)

Definition at line 468 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_External_Trigger_Prescaler

Defines

TIM_External_Trigger_Prescaler

TIM_Exported_constants

Defines

#define | IS_TIM_EXT_PRESCALER(PRESCALER)
#define | TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define | TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define | TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
#define | TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_EXT_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))

Definition at line 488 of file stm32l1xx_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().

#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)

Definition at line 485 of file stm32l1xx_tim.h.

#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)

Definition at line 486 of file stm32l1xx_tim.h.

#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)

Definition at line 487 of file stm32l1xx_tim.h.

#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)

Definition at line 484 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Internal_Trigger_Selection

Defines

TIM_Internal_Trigger_Selection

TIM_Exported_constants

Defines

#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | TIM_TS_ETRF ((uint16_t)0x0070)
#define | TIM_TS_ITR0 ((uint16_t)0x0000)
#define | TIM_TS_ITR1 ((uint16_t)0x0010)
#define | TIM_TS_ITR2 ((uint16_t)0x0020)
#define | TIM_TS_ITR3 ((uint16_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint16_t)0x0060)

Define Documentation

#define IS_TIM_INTERNAL_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                      ((SELECTION) == TIM_TS_ITR1) || \
                                                      ((SELECTION) == TIM_TS_ITR2) || \
                                                      ((SELECTION) == TIM_TS_ITR3))

Definition at line 516 of file stm32l1xx_tim.h.

Referenced by TIM_ITRxExternalClockConfig().

#define IS_TIM_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                             ((SELECTION) == TIM_TS_ITR1) || \
                                             ((SELECTION) == TIM_TS_ITR2) || \
                                             ((SELECTION) == TIM_TS_ITR3) || \
                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
                                             ((SELECTION) == TIM_TS_TI1FP1) || \
                                             ((SELECTION) == TIM_TS_TI2FP2) || \
                                             ((SELECTION) == TIM_TS_ETRF))

Definition at line 508 of file stm32l1xx_tim.h.

Referenced by TIM_SelectInputTrigger().

#define TIM_TS_ETRF ((uint16_t)0x0070)

Definition at line 507 of file stm32l1xx_tim.h.

Referenced by TIM_ETRClockMode1Config().

#define TIM_TS_ITR0 ((uint16_t)0x0000)

Definition at line 500 of file stm32l1xx_tim.h.

#define TIM_TS_ITR1 ((uint16_t)0x0010)

Definition at line 501 of file stm32l1xx_tim.h.

#define TIM_TS_ITR2 ((uint16_t)0x0020)

Definition at line 502 of file stm32l1xx_tim.h.

#define TIM_TS_ITR3 ((uint16_t)0x0030)

Definition at line 503 of file stm32l1xx_tim.h.

#define TIM_TS_TI1F_ED ((uint16_t)0x0040)

Definition at line 504 of file stm32l1xx_tim.h.

#define TIM_TS_TI1FP1 ((uint16_t)0x0050)

Definition at line 505 of file stm32l1xx_tim.h.

#define TIM_TS_TI2FP2 ((uint16_t)0x0060)

Definition at line 506 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_TIx_External_Clock_Source

Defines

TIM_TIx_External_Clock_Source

TIM_Exported_constants

Defines

#define | TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define | TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
#define | TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)

Define Documentation

#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)

Definition at line 528 of file stm32l1xx_tim.h.

#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)

Definition at line 530 of file stm32l1xx_tim.h.

#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)

Definition at line 529 of file stm32l1xx_tim.h.

Referenced by TIM_TIxExternalClockConfig().


STM32L1xx Standard Peripherals Firmware Library: TIM_External_Trigger_Polarity

Defines

TIM_External_Trigger_Polarity

TIM_Exported_constants

Defines

#define | IS_TIM_EXT_POLARITY(POLARITY)
#define | TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define | TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_EXT_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))

Definition at line 541 of file stm32l1xx_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().

#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)

Definition at line 539 of file stm32l1xx_tim.h.

#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)

Definition at line 540 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Prescaler_Reload_Mode

Defines

TIM_Prescaler_Reload_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_PRESCALER_RELOAD(RELOAD)
#define | TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Update ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_PRESCALER_RELOAD ( RELOAD )
Value:
(((RELOAD) == TIM_PSCReloadMode_Update) || \
                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))

Definition at line 553 of file stm32l1xx_tim.h.

Referenced by TIM_PrescalerConfig().

#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)

Definition at line 552 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseInit().

#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)

Definition at line 551 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Forced_Action

Defines

TIM_Forced_Action

TIM_Exported_constants

Defines

#define | IS_TIM_FORCED_ACTION(ACTION)
#define | TIM_ForcedAction_Active ((uint16_t)0x0050)
#define | TIM_ForcedAction_InActive ((uint16_t)0x0040)

Define Documentation

#define IS_TIM_FORCED_ACTION ( ACTION )
Value:
(((ACTION) == TIM_ForcedAction_Active) || \
                                      ((ACTION) == TIM_ForcedAction_InActive))

Definition at line 565 of file stm32l1xx_tim.h.

Referenced by TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_ForcedOC3Config(), and TIM_ForcedOC4Config().

#define TIM_ForcedAction_Active ((uint16_t)0x0050)

Definition at line 563 of file stm32l1xx_tim.h.

#define TIM_ForcedAction_InActive ((uint16_t)0x0040)

Definition at line 564 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Encoder_Mode

Defines

TIM_Encoder_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_ENCODER_MODE(MODE)
#define | TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define | TIM_EncoderMode_TI12 ((uint16_t)0x0003)
#define | TIM_EncoderMode_TI2 ((uint16_t)0x0002)

Define Documentation

#define IS_TIM_ENCODER_MODE ( MODE )
Value:
(((MODE) == TIM_EncoderMode_TI1) || \
                                   ((MODE) == TIM_EncoderMode_TI2) || \
                                   ((MODE) == TIM_EncoderMode_TI12))

Definition at line 578 of file stm32l1xx_tim.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)

Definition at line 575 of file stm32l1xx_tim.h.

#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)

Definition at line 577 of file stm32l1xx_tim.h.

#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)

Definition at line 576 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Event_Source

Defines

TIM_Event_Source

TIM_Exported_constants

Defines

#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
#define | TIM_EventSource_CC1 ((uint16_t)0x0002)
#define | TIM_EventSource_CC2 ((uint16_t)0x0004)
#define | TIM_EventSource_CC3 ((uint16_t)0x0008)
#define | TIM_EventSource_CC4 ((uint16_t)0x0010)
#define | TIM_EventSource_Trigger ((uint16_t)0x0040)
#define | TIM_EventSource_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_EVENT_SOURCE ( SOURCE ) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))

Definition at line 596 of file stm32l1xx_tim.h.

Referenced by TIM_GenerateEvent().

#define TIM_EventSource_CC1 ((uint16_t)0x0002)

Definition at line 591 of file stm32l1xx_tim.h.

#define TIM_EventSource_CC2 ((uint16_t)0x0004)

Definition at line 592 of file stm32l1xx_tim.h.

#define TIM_EventSource_CC3 ((uint16_t)0x0008)

Definition at line 593 of file stm32l1xx_tim.h.

#define TIM_EventSource_CC4 ((uint16_t)0x0010)

Definition at line 594 of file stm32l1xx_tim.h.

#define TIM_EventSource_Trigger ((uint16_t)0x0040)

Definition at line 595 of file stm32l1xx_tim.h.

#define TIM_EventSource_Update ((uint16_t)0x0001)

Definition at line 590 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Update_Source

Defines

TIM_Update_Source

TIM_Exported_constants

Defines

#define | IS_TIM_UPDATE_SOURCE(SOURCE)
#define | TIM_UpdateSource_Global ((uint16_t)0x0000)
#define | TIM_UpdateSource_Regular ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_UPDATE_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_UpdateSource_Global) || \
                                      ((SOURCE) == TIM_UpdateSource_Regular))

Definition at line 610 of file stm32l1xx_tim.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_UpdateSource_Global ((uint16_t)0x0000)

Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.

Definition at line 606 of file stm32l1xx_tim.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_UpdateSource_Regular ((uint16_t)0x0001)

Source of update is counter overflow/underflow.

Definition at line 609 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_Preload_State

Defines

TIM_Output_Compare_Preload_State

TIM_Exported_constants

Defines

#define | IS_TIM_OCPRELOAD_STATE(STATE)
#define | TIM_OCPreload_Disable ((uint16_t)0x0000)
#define | TIM_OCPreload_Enable ((uint16_t)0x0008)

Define Documentation

#define IS_TIM_OCPRELOAD_STATE ( STATE )
Value:
(((STATE) == TIM_OCPreload_Enable) || \
                                       ((STATE) == TIM_OCPreload_Disable))

Definition at line 622 of file stm32l1xx_tim.h.

Referenced by TIM_OC1PreloadConfig(), TIM_OC2PreloadConfig(), TIM_OC3PreloadConfig(), and TIM_OC4PreloadConfig().

#define TIM_OCPreload_Disable ((uint16_t)0x0000)

Definition at line 621 of file stm32l1xx_tim.h.

#define TIM_OCPreload_Enable ((uint16_t)0x0008)

Definition at line 620 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_Fast_State

Defines

TIM_Output_Compare_Fast_State

TIM_Exported_constants

Defines

#define | IS_TIM_OCFAST_STATE(STATE)
#define | TIM_OCFast_Disable ((uint16_t)0x0000)
#define | TIM_OCFast_Enable ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_OCFAST_STATE ( STATE )
Value:
(((STATE) == TIM_OCFast_Enable) || \
                                    ((STATE) == TIM_OCFast_Disable))

Definition at line 634 of file stm32l1xx_tim.h.

Referenced by TIM_OC1FastConfig(), TIM_OC2FastConfig(), TIM_OC3FastConfig(), and TIM_OC4FastConfig().

#define TIM_OCFast_Disable ((uint16_t)0x0000)

Definition at line 633 of file stm32l1xx_tim.h.

#define TIM_OCFast_Enable ((uint16_t)0x0004)

Definition at line 632 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Output_Compare_Clear_State

Defines

TIM_Output_Compare_Clear_State

TIM_Exported_constants

Defines

#define | IS_TIM_OCCLEAR_STATE(STATE)
#define | TIM_OCClear_Disable ((uint16_t)0x0000)
#define | TIM_OCClear_Enable ((uint16_t)0x0080)

Define Documentation

#define IS_TIM_OCCLEAR_STATE ( STATE )
Value:
(((STATE) == TIM_OCClear_Enable) || \
                                     ((STATE) == TIM_OCClear_Disable))

Definition at line 647 of file stm32l1xx_tim.h.

Referenced by TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_ClearOC3Ref(), and TIM_ClearOC4Ref().

#define TIM_OCClear_Disable ((uint16_t)0x0000)

Definition at line 646 of file stm32l1xx_tim.h.

#define TIM_OCClear_Enable ((uint16_t)0x0080)

Definition at line 645 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Trigger_Output_Source

Defines

TIM_Trigger_Output_Source

TIM_Exported_constants

Defines

#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define | TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define | TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define | TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define | TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define | TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
#define | TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define | TIM_TRGOSource_Update ((uint16_t)0x0020)

Define Documentation

#define IS_TIM_TRGO_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGOSource_Reset) || \
                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
                                    ((SOURCE) == TIM_TRGOSource_Update) || \
                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))

Definition at line 665 of file stm32l1xx_tim.h.

Referenced by TIM_SelectOutputTrigger().

#define TIM_TRGOSource_Enable ((uint16_t)0x0010)

Definition at line 658 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)

Definition at line 660 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)

Definition at line 661 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)

Definition at line 662 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)

Definition at line 663 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)

Definition at line 664 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_Reset ((uint16_t)0x0000)

Definition at line 657 of file stm32l1xx_tim.h.

#define TIM_TRGOSource_Update ((uint16_t)0x0020)

Definition at line 659 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Slave_Mode

Defines

TIM_Slave_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_SLAVE_MODE(MODE)
#define | TIM_SlaveMode_External1 ((uint16_t)0x0007)
#define | TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define | TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define | TIM_SlaveMode_Trigger ((uint16_t)0x0006)

Define Documentation

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SlaveMode_Reset) || \
                                 ((MODE) == TIM_SlaveMode_Gated) || \
                                 ((MODE) == TIM_SlaveMode_Trigger) || \
                                 ((MODE) == TIM_SlaveMode_External1))

Definition at line 685 of file stm32l1xx_tim.h.

Referenced by TIM_SelectSlaveMode().

#define TIM_SlaveMode_External1 ((uint16_t)0x0007)

Definition at line 684 of file stm32l1xx_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

#define TIM_SlaveMode_Gated ((uint16_t)0x0005)

Definition at line 682 of file stm32l1xx_tim.h.

#define TIM_SlaveMode_Reset ((uint16_t)0x0004)

Definition at line 681 of file stm32l1xx_tim.h.

#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)

Definition at line 683 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Master_Slave_Mode

Defines

TIM_Master_Slave_Mode

TIM_Exported_constants

Defines

#define | IS_TIM_MSM_STATE(STATE)
#define | TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
#define | TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)

Define Documentation

#define IS_TIM_MSM_STATE ( STATE )
Value:
(((STATE) == TIM_MasterSlaveMode_Enable) || \
                                 ((STATE) == TIM_MasterSlaveMode_Disable))

Definition at line 699 of file stm32l1xx_tim.h.

Referenced by TIM_SelectMasterSlaveMode().

#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)

Definition at line 698 of file stm32l1xx_tim.h.

#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)

Definition at line 697 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Flags

Defines

TIM_Flags

TIM_Exported_constants

Defines

#define | IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
#define | IS_TIM_GET_FLAG(FLAG)
#define | TIM_FLAG_CC1 ((uint16_t)0x0002)
#define | TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define | TIM_FLAG_CC2 ((uint16_t)0x0004)
#define | TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define | TIM_FLAG_CC3 ((uint16_t)0x0008)
#define | TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define | TIM_FLAG_CC4 ((uint16_t)0x0010)
#define | TIM_FLAG_CC4OF ((uint16_t)0x1000)
#define | TIM_FLAG_Trigger ((uint16_t)0x0040)
#define | TIM_FLAG_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_CLEAR_FLAG ( TIM_FLAG ) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))

Definition at line 729 of file stm32l1xx_tim.h.

Referenced by TIM_ClearFlag().

#define IS_TIM_GET_FLAG ( FLAG )
Value:
(((FLAG) == TIM_FLAG_Update) || \
                               ((FLAG) == TIM_FLAG_CC1) || \
                               ((FLAG) == TIM_FLAG_CC2) || \
                               ((FLAG) == TIM_FLAG_CC3) || \
                               ((FLAG) == TIM_FLAG_CC4) || \
                               ((FLAG) == TIM_FLAG_Trigger) || \
                               ((FLAG) == TIM_FLAG_CC1OF) || \
                               ((FLAG) == TIM_FLAG_CC2OF) || \
                               ((FLAG) == TIM_FLAG_CC3OF) || \
                               ((FLAG) == TIM_FLAG_CC4OF))

Definition at line 719 of file stm32l1xx_tim.h.

Referenced by TIM_GetFlagStatus().

#define TIM_FLAG_CC1 ((uint16_t)0x0002)

Definition at line 710 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC1OF ((uint16_t)0x0200)

Definition at line 715 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC2 ((uint16_t)0x0004)

Definition at line 711 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC2OF ((uint16_t)0x0400)

Definition at line 716 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC3 ((uint16_t)0x0008)

Definition at line 712 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC3OF ((uint16_t)0x0800)

Definition at line 717 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC4 ((uint16_t)0x0010)

Definition at line 713 of file stm32l1xx_tim.h.

#define TIM_FLAG_CC4OF ((uint16_t)0x1000)

Definition at line 718 of file stm32l1xx_tim.h.

#define TIM_FLAG_Trigger ((uint16_t)0x0040)

Definition at line 714 of file stm32l1xx_tim.h.

#define TIM_FLAG_Update ((uint16_t)0x0001)

Definition at line 709 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Input_Capture_Filer_Value

Defines

TIM_Input_Capture_Filer_Value

TIM_Exported_constants

Defines

#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)

Define Documentation

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0xF)

Definition at line 739 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), and TIM_TIxExternalClockConfig().


STM32L1xx Standard Peripherals Firmware Library: TIM_External_Trigger_Filter

Defines

TIM_External_Trigger_Filter

TIM_Exported_constants

Defines

#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)

Define Documentation

#define IS_TIM_EXT_FILTER ( EXTFILTER ) ((EXTFILTER) <= 0xF)

Definition at line 748 of file stm32l1xx_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().


STM32L1xx Standard Peripherals Firmware Library: TIM_OCReferenceClear

Defines

TIM_OCReferenceClear

TIM_Exported_constants

Defines

#define | TIM_OCREFERENCECECLEAR_SOURCE(SOURCE)
#define | TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
#define | TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)

Define Documentation

#define TIM_OCREFERENCECECLEAR_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_OCReferenceClear_ETRF) || \
                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))

Definition at line 758 of file stm32l1xx_tim.h.

Referenced by TIM_SelectOCREFClear().

#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)

Definition at line 756 of file stm32l1xx_tim.h.

#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)

Definition at line 757 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Remap

Defines

TIM_Remap

TIM_Exported_constants

Defines

#define | IS_TIM_REMAP(TIM_REMAP)
#define | TIM10_ETR_LSE ((uint32_t)0xFFFB0000)
#define | TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
#define | TIM10_GPIO ((uint32_t)0xFFF40000)
#define | TIM10_LSE ((uint32_t)0xFFF40002)
#define | TIM10_LSI ((uint32_t)0xFFF40001)
#define | TIM10_RI ((uint32_t)0xFFF40008)
#define | TIM10_RTC ((uint32_t)0xFFF40003)
#define | TIM11_ETR_LSE ((uint32_t)0xFFFB0000)
#define | TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
#define | TIM11_GPIO ((uint32_t)0xFFF40000)
#define | TIM11_HSE_RTC ((uint32_t)0xFFF40002)
#define | TIM11_MSI ((uint32_t)0xFFF40001)
#define | TIM11_RI ((uint32_t)0xFFF40008)
#define | TIM2_TIM10_OC ((uint32_t)0xFFFE0000)
#define | TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)
#define | TIM3_TIM11_OC ((uint32_t)0xFFFE0000)
#define | TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)
#define | TIM9_GPIO ((uint32_t)0xFFFC0000)
#define | TIM9_LSE ((uint32_t)0xFFFC0001)
#define | TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)
#define | TIM9_TS_IO ((uint32_t)0xFFFB0004)

Define Documentation

#define IS_TIM_REMAP ( TIM_REMAP )
Value:
(((TIM_REMAP) == TIM2_TIM10_OC)|| \
                                  ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \
                                  ((TIM_REMAP) == TIM3_TIM11_OC)|| \
                                  ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \
                                  ((TIM_REMAP) == TIM9_GPIO)|| \
                                  ((TIM_REMAP) == TIM9_LSE)|| \
                                  ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \
                                  ((TIM_REMAP) == TIM9_TS_IO)|| \
                                  ((TIM_REMAP) == TIM10_GPIO)|| \
                                  ((TIM_REMAP) == TIM10_LSI)|| \
                                  ((TIM_REMAP) == TIM10_LSE)|| \
                                  ((TIM_REMAP) == TIM10_RTC)|| \
                                  ((TIM_REMAP) == TIM10_RI)|| \
                                  ((TIM_REMAP) == TIM10_ETR_LSE)|| \
                                  ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \
                                  ((TIM_REMAP) == TIM11_GPIO)|| \
                                  ((TIM_REMAP) == TIM11_MSI)|| \
                                  ((TIM_REMAP) == TIM11_HSE_RTC)|| \
                                  ((TIM_REMAP) == TIM11_RI)|| \
                                  ((TIM_REMAP) == TIM11_ETR_LSE)|| \
                                  ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))

Definition at line 798 of file stm32l1xx_tim.h.

Referenced by TIM_RemapConfig().

#define TIM10_ETR_LSE ((uint32_t)0xFFFB0000)

Definition at line 787 of file stm32l1xx_tim.h.

#define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)

Definition at line 788 of file stm32l1xx_tim.h.

#define TIM10_GPIO ((uint32_t)0xFFF40000)

Definition at line 781 of file stm32l1xx_tim.h.

#define TIM10_LSE ((uint32_t)0xFFF40002)

Definition at line 783 of file stm32l1xx_tim.h.

#define TIM10_LSI ((uint32_t)0xFFF40001)

Definition at line 782 of file stm32l1xx_tim.h.

#define TIM10_RI ((uint32_t)0xFFF40008)

Definition at line 785 of file stm32l1xx_tim.h.

#define TIM10_RTC ((uint32_t)0xFFF40003)

Definition at line 784 of file stm32l1xx_tim.h.

#define TIM11_ETR_LSE ((uint32_t)0xFFFB0000)

Definition at line 795 of file stm32l1xx_tim.h.

#define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)

Definition at line 796 of file stm32l1xx_tim.h.

#define TIM11_GPIO ((uint32_t)0xFFF40000)

Definition at line 790 of file stm32l1xx_tim.h.

#define TIM11_HSE_RTC ((uint32_t)0xFFF40002)

Definition at line 792 of file stm32l1xx_tim.h.

#define TIM11_MSI ((uint32_t)0xFFF40001)

Definition at line 791 of file stm32l1xx_tim.h.

#define TIM11_RI ((uint32_t)0xFFF40008)

Definition at line 793 of file stm32l1xx_tim.h.

#define TIM2_TIM10_OC ((uint32_t)0xFFFE0000)

Definition at line 769 of file stm32l1xx_tim.h.

#define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)

Definition at line 770 of file stm32l1xx_tim.h.

#define TIM3_TIM11_OC ((uint32_t)0xFFFE0000)

Definition at line 772 of file stm32l1xx_tim.h.

#define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)

Definition at line 773 of file stm32l1xx_tim.h.

#define TIM9_GPIO ((uint32_t)0xFFFC0000)

Definition at line 775 of file stm32l1xx_tim.h.

#define TIM9_LSE ((uint32_t)0xFFFC0001)

Definition at line 776 of file stm32l1xx_tim.h.

#define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)

Definition at line 778 of file stm32l1xx_tim.h.

#define TIM9_TS_IO ((uint32_t)0xFFFB0004)

Definition at line 779 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Legacy

Defines

TIM_Legacy

TIM_Exported_constants

Defines

#define | TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define | TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define | TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define | TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define | TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define | TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define | TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define | TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define | TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
#define | TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define | TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define | TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define | TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define | TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define | TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define | TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define | TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define | TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers

Define Documentation

#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers

Definition at line 837 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers

Definition at line 838 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers

Definition at line 839 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers

Definition at line 840 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers

Definition at line 841 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers

Definition at line 842 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers

Definition at line 843 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers

Definition at line 844 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers

Definition at line 845 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer

Definition at line 828 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers

Definition at line 829 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers

Definition at line 830 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers

Definition at line 831 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers

Definition at line 832 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers

Definition at line 833 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers

Definition at line 834 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers

Definition at line 835 of file stm32l1xx_tim.h.

#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers

Definition at line 836 of file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: TIM_Exported_constants

Modules | Defines

TIM_Exported_constants

TIM

Modules

TIM_Output_Compare_and_PWM_modes
TIM_One_Pulse_Mode
TIM_Channel
TIM_Clock_Division_CKD
TIM_Counter_Mode
TIM_Output_Compare_Polarity
TIM_Output_Compare_state
TIM_Capture_Compare_state
TIM_Input_Capture_Polarity
TIM_Input_Capture_Selection
TIM_Input_Capture_Prescaler
TIM_interrupt_sources
TIM_DMA_Base_address
TIM_DMA_Burst_Length
TIM_DMA_sources
TIM_External_Trigger_Prescaler
TIM_Internal_Trigger_Selection
TIM_TIx_External_Clock_Source
TIM_External_Trigger_Polarity
TIM_Prescaler_Reload_Mode
TIM_Forced_Action
TIM_Encoder_Mode
TIM_Event_Source
TIM_Update_Source
TIM_Output_Compare_Preload_State
TIM_Output_Compare_Fast_State
TIM_Output_Compare_Clear_State
TIM_Trigger_Output_Source
TIM_Slave_Mode
TIM_Master_Slave_Mode
TIM_Flags
TIM_Input_Capture_Filer_Value
TIM_External_Trigger_Filter
TIM_OCReferenceClear
TIM_Remap
TIM_Legacy

Defines

#define | IS_TIM_ALL_PERIPH(PERIPH)
#define | IS_TIM_LIST1_PERIPH(PERIPH)
#define | IS_TIM_LIST2_PERIPH(PERIPH)
#define | IS_TIM_LIST3_PERIPH(PERIPH)
#define | IS_TIM_LIST4_PERIPH(PERIPH)
#define | IS_TIM_LIST5_PERIPH(PERIPH)
#define | IS_TIM_LIST6_PERIPH(PERIPH)

Define Documentation

#define IS_TIM_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                   ((PERIPH) == TIM3) || \
                                   ((PERIPH) == TIM4) || \
                                   ((PERIPH) == TIM5) || \
                                   ((PERIPH) == TIM6) || \
                                   ((PERIPH) == TIM7) || \
                                   ((PERIPH) == TIM9) || \
                                   ((PERIPH) == TIM10) || \
                                   ((PERIPH) == TIM11))

Definition at line 119 of file stm32l1xx_tim.h.

Referenced by TIM_ARRPreloadConfig(), TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_Cmd(), TIM_DeInit(), TIM_GenerateEvent(), TIM_GetCounter(), TIM_GetFlagStatus(), TIM_GetITStatus(), TIM_GetPrescaler(), TIM_ITConfig(), TIM_PrescalerConfig(), TIM_SelectOnePulseMode(), TIM_SetAutoreload(), TIM_SetCounter(), TIM_TimeBaseInit(), TIM_UpdateDisableConfig(), and TIM_UpdateRequestConfig().

#define IS_TIM_LIST1_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) || \
                                     ((PERIPH) == TIM9) || \
                                     ((PERIPH) == TIM10) || \
                                     ((PERIPH) == TIM11))

Definition at line 130 of file stm32l1xx_tim.h.

Referenced by TIM_CCxCmd(), TIM_ClearOC1Ref(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_ForcedOC1Config(), TIM_GetCapture1(), TIM_ICInit(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1PolarityConfig(), TIM_OC1PreloadConfig(), TIM_SelectInputTrigger(), TIM_SelectOCxM(), TIM_SetClockDivision(), TIM_SetCompare1(), and TIM_SetIC1Prescaler().

#define IS_TIM_LIST2_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) || \
                                     ((PERIPH) == TIM9))

Definition at line 145 of file stm32l1xx_tim.h.

Referenced by TIM_ClearOC2Ref(), TIM_ETRClockMode1Config(), TIM_ForcedOC2Config(), TIM_GetCapture2(), TIM_ICInit(), TIM_InternalClockConfig(), TIM_ITRxExternalClockConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2PolarityConfig(), TIM_OC2PreloadConfig(), TIM_PWMIConfig(), TIM_SelectMasterSlaveMode(), TIM_SelectSlaveMode(), TIM_SetCompare2(), TIM_SetIC2Prescaler(), and TIM_TIxExternalClockConfig().

#define IS_TIM_LIST3_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5))

Definition at line 139 of file stm32l1xx_tim.h.

Referenced by TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_CounterModeConfig(), TIM_DMAConfig(), TIM_EncoderInterfaceConfig(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_GetCapture3(), TIM_GetCapture4(), TIM_ICInit(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3PolarityConfig(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), TIM_OC4PreloadConfig(), TIM_SelectCCDMA(), TIM_SelectHallSensor(), TIM_SelectOCREFClear(), TIM_SetCompare3(), TIM_SetCompare4(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

#define IS_TIM_LIST4_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) ||\
                                     ((PERIPH) == TIM6) || \
                                     ((PERIPH) == TIM7))

Definition at line 161 of file stm32l1xx_tim.h.

Referenced by TIM_DMACmd().

#define IS_TIM_LIST5_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) ||\
                                     ((PERIPH) == TIM6) || \
                                     ((PERIPH) == TIM7) ||\
                                     ((PERIPH) == TIM9))

Definition at line 152 of file stm32l1xx_tim.h.

Referenced by TIM_SelectOutputTrigger().

#define IS_TIM_LIST6_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM9) || \
                                     ((PERIPH) == TIM10) || \
                                     ((PERIPH) == TIM11))

Definition at line 169 of file stm32l1xx_tim.h.

Referenced by TIM_RemapConfig().


STM32L1xx Standard Peripherals Firmware Library: TimeBase management functions

Functions

TimeBase management functions

TIM_Private_Functions

TimeBase management functions. More...

Functions

void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
uint32_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

TimeBase management functions.

 ===============================================================================
                 ##### TimeBase management functions #####
 ===============================================================================

        *** TIM Driver: how to use it in Timing(Time base) Mode ***
 ===============================================================================
    [..] To use the Timer in Timing(Time base) mode, the following steps are
         mandatory:
         (#) Enable TIM clock using
             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
         (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
         (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
             the Time Base unit with the corresponding configuration.
         (#) Enable the NVIC if you need to generate the update interrupt.
         (#) Enable the corresponding interrupt using the function
             TIM_ITConfig(TIMx, TIM_IT_Update).
         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
    [..]
        (@) All other functions can be used seperatly to modify, if needed,
            a specific feature of the Timer.

Function Documentation

void TIM_ARRPreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables TIMx peripheral Preload register on ARR.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
NewState,: new state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 468 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_ARPE.

void TIM_Cmd | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM peripheral.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIMx peripheral.
NewState,: new state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 538 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_CEN.

void TIM_CounterModeConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CounterMode
 | ) |  |

Specifies the TIMx Counter Mode to be used.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_CounterMode,: specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM_CounterMode_Up: TIM Up Counting Mode.
  • TIM_CounterMode_Down: TIM Down Counting Mode.
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1.
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2.
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3.
Return values:
None

Definition at line 332 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_COUNTER_MODE, IS_TIM_LIST3_PERIPH, TIM_CR1_CMS, and TIM_CR1_DIR.

void TIM_DeInit ( TIM_TypeDef * TIMx )

Deinitializes the TIMx peripheral registers to their default reset values.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
None

Definition at line 180 of file stm32l1xx_tim.c.

References DISABLE, ENABLE, IS_TIM_ALL_PERIPH, RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11, RCC_APB2Periph_TIM9, RCC_APB2PeriphResetCmd(), TIM10, TIM11, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM9.

uint32_t TIM_GetCounter ( TIM_TypeDef * TIMx )

Gets the TIMx Counter value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
Counter Register value.

Definition at line 384 of file stm32l1xx_tim.c.

References TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

uint16_t TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Gets the TIMx Prescaler value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
Prescaler Register value.

Definition at line 398 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, and TIM_TypeDef::PSC.

void TIM_PrescalerConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Prescaler,
 |  | uint16_t | TIM_PSCReloadMode
 | ) |  |

Configures the TIMx Prescaler.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Prescaler,: specifies the Prescaler Register value.
TIM_PSCReloadMode,: specifies the TIM Prescaler Reload mode This parameter can be one of the following values:

  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
Return values:
None

Definition at line 308 of file stm32l1xx_tim.c.

References TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_PRESCALER_RELOAD, and TIM_TypeDef::PSC.

void TIM_SelectOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OPMode
 | ) |  |

Selects the TIMx's One Pulse Mode.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_OPMode,: specifies the OPM Mode to be used. This parameter can be one of the following values:

  • TIM_OPMode_Single:: TIM One Pulse Single Mode (Counter stops counting at the next update event (clearing the bit CEN)).
  • TIM_OPMode_Repetitive: TIM One Pulse Repetitive Mode (Counter is not stopped at update event).
Return values:
None

Definition at line 497 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_OPM_MODE, and TIM_CR1_OPM.

void TIM_SetAutoreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Autoreload
 | ) |  |

Sets the TIMx Autoreload Register value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Autoreload,: specifies the Autoreload register new value.
Return values:
None

Definition at line 370 of file stm32l1xx_tim.c.

References TIM_TypeDef::ARR, and IS_TIM_ALL_PERIPH.

void TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CKD
 | ) |  |

Sets the TIMx Clock Division value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_CKD,: specifies the clock division value. This parameter can be one of the following value:

  • TIM_CKD_DIV1: TDTS = Tck_tim.
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim.
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim.
Return values:
None

Definition at line 519 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_CKD_DIV, IS_TIM_LIST1_PERIPH, and TIM_CR1_CKD.

void TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Sets the TIMx Counter Register value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Counter,: specifies the Counter register new value.
Return values:
None

Definition at line 355 of file stm32l1xx_tim.c.

References TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

void TIM_TimeBaseInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_TimeBaseInitTypeDef * | TIM_TimeBaseInitStruct
 | ) |  |

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_TimeBaseInitStruct,: pointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 246 of file stm32l1xx_tim.c.

References TIM_TypeDef::ARR, TIM_TypeDef::CR1, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_CKD_DIV, IS_TIM_COUNTER_MODE, TIM_TypeDef::PSC, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CR1_CKD, TIM_CR1_CMS, TIM_CR1_DIR, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, and TIM_PSCReloadMode_Immediate.

void TIM_TimeBaseStructInit ( TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct )

Fills each TIM_TimeBaseInitStruct member with its default value.

Parameters:
TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 289 of file stm32l1xx_tim.c.

References TIM_CKD_DIV1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, and TIM_TimeBaseInitTypeDef::TIM_Prescaler.

void TIM_UpdateDisableConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the TIMx Update event.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
NewState,: new state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 414 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_UDIS.

void TIM_UpdateRequestConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_UpdateSource
 | ) |  |

Configures the TIMx Update Request Interrupt source.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_UpdateSource,: specifies the Update source. This parameter can be one of the following values:

  • TIM_UpdateSource_Global: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
  • TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
Return values:
None

Definition at line 443 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_UPDATE_SOURCE, TIM_CR1_URS, and TIM_UpdateSource_Global.


STM32L1xx Standard Peripherals Firmware Library: Output Compare management functions

Functions

Output Compare management functions

TIM_Private_Functions

Output Compare management functions. More...

Functions

void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_SelectOCREFClear (TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.

Detailed Description

Output Compare management functions.

 ===============================================================================
                ##### Output Compare management functions #####
 ===============================================================================
        *** TIM Driver: how to use it in Output Compare Mode ***
 ===============================================================================
    [..] To use the Timer in Output Compare mode, the following steps are mandatory:
         (#) Enable TIM clock using
             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
         (#) Configure the TIM pins by configuring the corresponding GPIO pins
         (#) Configure the Time base unit as described in the first part of this
             driver, if needed, else the Timer will run with the default
             configuration:
             (++) Autoreload value = 0xFFFF.
             (++) Prescaler value = 0x0000.
             (++) Counter mode = Up counting.
             (++) Clock Division = TIM_CKD_DIV1.
         (#) Fill the TIM_OCInitStruct with the desired parameters including:
             (++) The TIM Output Compare mode: TIM_OCMode.
             (++) TIM Output State: TIM_OutputState.
             (++) TIM Pulse value: TIM_Pulse.
             (++) TIM Output Compare Polarity : TIM_OCPolarity.
         (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
             channel with the corresponding configuration.
         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
    [..]
        (@) All other functions can be used separately to modify, if needed,
          a specific feature of the Timer.
        (@) In case of PWM mode, this function is mandatory:
            TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
        (@) If the corresponding interrupt or DMA request are needed, the user should:
            (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
            (#@) Enable the corresponding interrupt (or DMA request) using the function
                 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).

Function Documentation

void TIM_CCxCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCx
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel. This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1.
  • TIM_Channel_2: TIM Channel 2.
  • TIM_Channel_3: TIM Channel 3.
  • TIM_Channel_4: TIM Channel 4.
TIM_CCx,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
Return values:
None

Definition at line 1497 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, CCER_CCE_SET, IS_TIM_CCX, and IS_TIM_LIST1_PERIPH.

void TIM_ClearOC1Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF1 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1268 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC1CE.

void TIM_ClearOC2Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF2 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit.

This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable .
    Return values:
    None

Definition at line 1295 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC2CE.

void TIM_ClearOC3Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF3 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1321 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC3CE.

void TIM_ClearOC4Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF4 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1347 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC4CE.

void TIM_ForcedOC1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 1 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC1REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
Return values:
None

Definition at line 956 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST1_PERIPH, and TIM_CCMR1_OC1M.

void TIM_ForcedOC2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 2 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC2REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
Return values:
None

Definition at line 981 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST2_PERIPH, and TIM_CCMR1_OC2M.

void TIM_ForcedOC3Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 3 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC3REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
Return values:
None

Definition at line 1007 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC3M.

void TIM_ForcedOC4Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 4 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC4REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
Return values:
None

Definition at line 1033 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC4M.

void TIM_OC1FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 1 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1160 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC1FE.

void TIM_OC1Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 611 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR1, IS_TIM_LIST1_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC1E, TIM_CCER_CC1P, TIM_CCMR1_CC1S, TIM_CCMR1_OC1M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC1PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 1 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1373 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC1P.

void TIM_OC1PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR1.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1058 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC1PE.

void TIM_OC2FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 2 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1187 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC2FE.

void TIM_OC2Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 663 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR2, IS_TIM_LIST2_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC2E, TIM_CCER_CC2P, TIM_CCMR1_OC2M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC2PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 2 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1398 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST2_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC2P.

void TIM_OC2PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR2.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1083 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC2PE.

void TIM_OC3FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 3 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1214 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC3FE.

void TIM_OC3Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 714 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR3, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC3E, TIM_CCER_CC3P, TIM_CCMR2_OC3M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC3PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 3 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1423 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC3P.

void TIM_OC3PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR3.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1108 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC3PE.

void TIM_OC4FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 4 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1241 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC4FE.

void TIM_OC4Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 766 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR4, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC4E, TIM_CCER_CC4P, TIM_CCMR2_OC4M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC4PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 4 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC4 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1448 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC4P.

void TIM_OC4PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR4.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1134 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC4PE.

void TIM_OCStructInit ( TIM_OCInitTypeDef * TIM_OCInitStruct )

Fills each TIM_OCInitStruct member with its default value.

Parameters:
TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 815 of file stm32l1xx_tim.c.

References TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Disable, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_SelectOCREFClear | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCReferenceClear
 | ) |  |

Selects the OCReference Clear source.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCReferenceClear,: specifies the OCReference Clear source. This parameter can be one of the following values:

  • TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
  • TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
Return values:
None

Definition at line 1473 of file stm32l1xx_tim.c.

References IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_OCREFERENCECECLEAR_SOURCE, and TIM_SMCR_OCCS.

void TIM_SelectOCxM | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_OCMode
 | ) |  |

Selects the TIM Output Compare Mode.

Note:
This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel. This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1.
  • TIM_Channel_2: TIM Channel 2.
  • TIM_Channel_3: TIM Channel 3.
  • TIM_Channel_4: TIM Channel 4.
TIM_OCMode,: specifies the TIM Output Compare Mode. This parameter can be one of the following values:

  • TIM_OCMode_Timing: TIM Output Compare Timing mode.
  • TIM_OCMode_Active: TIM Output Compare Active mode.
  • TIM_OCMode_Inactive: TIM Output Compare Inactive mode.
  • TIM_OCMode_Toggle: TIM Output Compare Toggle mode.
  • TIM_OCMode_PWM1: TIM Output Compare PWM1 mode.
  • TIM_OCMode_PWM2: TIM Output Compare PWM2 mode.
  • TIM_ForcedAction_Active: TIM Forced Action Active mode.
  • TIM_ForcedAction_InActive: TIM Forced Action Inactive mode.
Return values:
None

Definition at line 848 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, CCER_CCE_SET, CCMR_OFFSET, IS_TIM_LIST1_PERIPH, IS_TIM_OCM, TIM_CCMR1_OC1M, TIM_CCMR1_OC2M, TIM_Channel_1, and TIM_Channel_3.

void TIM_SetCompare1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare1
 | ) |  |

Sets the TIMx Capture Compare1 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
Compare1,: specifies the Capture Compare1 register new value.
Return values:
None

Definition at line 893 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR1, and IS_TIM_LIST1_PERIPH.

void TIM_SetCompare2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare2
 | ) |  |

Sets the TIMx Capture Compare2 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Compare2,: specifies the Capture Compare2 register new value.
Return values:
None

Definition at line 908 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR2, and IS_TIM_LIST2_PERIPH.

void TIM_SetCompare3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare3
 | ) |  |

Sets the TIMx Capture Compare3 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Compare3,: specifies the Capture Compare3 register new value.
Return values:
None

Definition at line 923 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

void TIM_SetCompare4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare4
 | ) |  |

Sets the TIMx Capture Compare4 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Compare4,: specifies the Capture Compare4 register new value.
Return values:
None

Definition at line 938 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.


STM32L1xx Standard Peripherals Firmware Library: Input Capture management functions

Functions

Input Capture management functions

TIM_Private_Functions

Input Capture management functions. More...

Functions

uint32_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint32_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint32_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint32_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.

Detailed Description

Input Capture management functions.

 ===============================================================================
               ##### Input Capture management functions #####
 ===============================================================================

          *** TIM Driver: how to use it in Input Capture Mode ***
 ===============================================================================
    [..] To use the Timer in Input Capture mode, the following steps are mandatory:
         (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
             function.
         (#) Configure the TIM pins by configuring the corresponding GPIO pins.
         (#) Configure the Time base unit as described in the first part of this
             driver, if needed, else the Timer will run with the default configuration:
             (++) Autoreload value = 0xFFFF.
             (++) Prescaler value = 0x0000.
             (++) Counter mode = Up counting.
             (++) Clock Division = TIM_CKD_DIV1.
         (#) Fill the TIM_ICInitStruct with the desired parameters including:
             (++) TIM Channel: TIM_Channel.
             (++) TIM Input Capture polarity: TIM_ICPolarity.
             (++) TIM Input Capture selection: TIM_ICSelection.
             (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
             (++) TIM Input CApture filter value: TIM_ICFilter.
         (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired
             channel with the corresponding configuration and to measure only
             frequency or duty cycle of the input signal,or, Call
             TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired
             channels with the corresponding configuration and to measure the
             frequency and the duty cycle of the input signal.
         (#) Enable the NVIC or the DMA to read the measured frequency.
         (#) Enable the corresponding interrupt (or DMA request) to read
             the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
             (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
         (#) Use TIM_GetCapturex(TIMx); to read the captured value.
    [..]
        (@) All other functions can be used separately to modify, if needed,
            a specific feature of the Timer.

Function Documentation

uint32_t TIM_GetCapture1 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 1 value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
Return values:
Capture Compare 1 Register value.

Definition at line 1703 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR1, and IS_TIM_LIST1_PERIPH.

uint32_t TIM_GetCapture2 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 2 value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Return values:
Capture Compare 2 Register value.

Definition at line 1717 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR2, and IS_TIM_LIST2_PERIPH.

uint32_t TIM_GetCapture3 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 3 value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Return values:
Capture Compare 3 Register value.

Definition at line 1731 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

uint32_t TIM_GetCapture4 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 4 value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Return values:
Capture Compare 4 Register value.

Definition at line 1745 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

void TIM_ICInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 1573 of file stm32l1xx_tim.c.

References IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_LIST1_PERIPH, IS_TIM_LIST2_PERIPH, IS_TIM_LIST3_PERIPH, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

void TIM_ICStructInit ( TIM_ICInitTypeDef * TIM_ICInitStruct )

Fills each TIM_ICInitStruct member with its default value.

Parameters:
TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 1629 of file stm32l1xx_tim.c.

References TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, and TIM_ICSelection_DirectTI.

void TIM_PWMIConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 1648 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, TI1_Config(), TI2_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Falling, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_ICSelection_IndirectTI, TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

void TIM_SetIC1Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 1 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture1 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1765 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST1_PERIPH, and TIM_CCMR1_IC1PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC2Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 2 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture2 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1788 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST2_PERIPH, and TIM_CCMR1_IC2PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC3Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 3 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture3 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1811 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC3PSC.

Referenced by TIM_ICInit().

void TIM_SetIC4Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 4 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1834 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC4PSC.

Referenced by TIM_ICInit().


STM32L1xx Standard Peripherals Firmware Library: Interrupts DMA and flags management functions

Functions

Interrupts DMA and flags management functions

TIM_Private_Functions

Interrupts, DMA and flags management functions. More...

Functions

void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.

Detailed Description

Interrupts, DMA and flags management functions.

 ===============================================================================
          ##### Interrupts, DMA and flags management functions #####
 ===============================================================================

Function Documentation

void TIM_ClearFlag | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Clears the TIMx's pending flags.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_FLAG,: specifies the flag bit to clear. This parameter can be any combination of the following values:

  • TIM_FLAG_Update: TIM update Flag.
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
  • TIM_FLAG_Trigger: TIM Trigger Flag.
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
Note:
TIM6 and TIM7 can have only one update flag.
TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
Return values:
None

Definition at line 1988 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_CLEAR_FLAG, and TIM_TypeDef::SR.

void TIM_ClearITPendingBit | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Clears the TIMx's interrupt pending bits.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_IT,: specifies the pending bit to clear. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can generate only an update interrupt.
TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2, and TIM_IT_Trigger interrupt.
TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1 interrupt
Return values:
None

Definition at line 2059 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_IT, and TIM_TypeDef::SR.

void TIM_DMACmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMASource,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's DMA Requests.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 6 or 7 to select the TIM peripheral.
TIM_DMASource,: specifies the DMA Request sources. This parameter can be any combination of the following values:

  • TIM_DMA_Update: TIM update Interrupt source.
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source.
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source.
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source.
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source.
  • TIM_DMA_Trigger: TIM Trigger DMA source.
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2122 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_DMA_SOURCE, and IS_TIM_LIST4_PERIPH.

void TIM_DMAConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMABase,
 |  | uint16_t | TIM_DMABurstLength
 | ) |  |

Configures the TIMx's DMA interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_DMABase,: DMA Base address. This parameter can be one of the following values:

  • TIM_DMABase_CR1: TIM CR1 register as TIM DMA Base.
  • TIM_DMABase_CR2: TIM CR2 register as TIM DMA Base.
  • TIM_DMABase_SMCR: TIM SMCR register as TIM DMA Base.
  • TIM_DMABase_DIER: TIM DIER register as TIM DMA Base.
  • TIM_DMABase_SR: TIM SR register as TIM DMA Base.
  • TIM_DMABase_EGR: TIM EGR register as TIM DMA Base.
  • TIM_DMABase_CCMR1: TIM CCMR1 register as TIM DMA Base.
  • TIM_DMABase_CCMR2: TIM CCMR2 register as TIM DMA Base.
  • TIM_DMABase_CCER: TIM CCER register as TIM DMA Base.
  • TIM_DMABase_CNT: TIM CNT register as TIM DMA Base.
  • TIM_DMABase_PSC: TIM PSC register as TIM DMA Base.
  • TIM_DMABase_ARR: TIM ARR register as TIM DMA Base.
  • TIM_DMABase_CCR1: TIM CCR1 register as TIM DMA Base.
  • TIM_DMABase_CCR2: TIM CCR2 register as TIM DMA Base.
  • TIM_DMABase_CCR3: TIM CCR3 register as TIM DMA Base.
  • TIM_DMABase_CCR4: TIM CCR4 register as TIM DMA Base.
  • TIM_DMABase_DCR: TIM DCR register as TIM DMA Base.
  • TIM_DMABase_OR: TIM OR register as TIM DMA Base.
TIM_DMABurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
None

Definition at line 2097 of file stm32l1xx_tim.c.

References TIM_TypeDef::DCR, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, and IS_TIM_LIST3_PERIPH.

void TIM_GenerateEvent | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EventSource
 | ) |  |

Configures the TIMx event to be generate by software.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_EventSource,: specifies the event source. This parameter can be one or more of the following values:

  • TIM_EventSource_Update: Timer update Event source.
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source.
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source.
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source.
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source.
  • TIM_EventSource_Trigger: Timer Trigger Event source.
Note:
TIM6 and TIM7 can only generate an update event.
TIM9 can only generate an update event, Capture Compare 1 event, Capture Compare 2 event and TIM_EventSource_Trigger.
TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
Return values:
None

Definition at line 1916 of file stm32l1xx_tim.c.

References TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, and IS_TIM_EVENT_SOURCE.

FlagStatus TIM_GetFlagStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Checks whether the specified TIM flag is set or not.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • TIM_FLAG_Update: TIM update Flag.
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
  • TIM_FLAG_Trigger: TIM Trigger Flag.
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
Note:
TIM6 and TIM7 can have only one update flag.
TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger, TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
Return values:
The new state of TIM_FLAG (SET or RESET).

Definition at line 1947 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_GET_FLAG, RESET, SET, and TIM_TypeDef::SR.

ITStatus TIM_GetITStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Checks whether the TIM interrupt has occurred or not.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_IT,: specifies the TIM interrupt source to check. This parameter can be one of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can generate only an update interrupt.
TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2, interrupt and TIM_IT_Trigger interrupt.
TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1 interrupt
Return values:
The new state of the TIM_IT(SET or RESET).

Definition at line 2017 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, IS_TIM_ALL_PERIPH, IS_TIM_GET_IT, RESET, SET, and TIM_TypeDef::SR.

void TIM_ITConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM interrupts.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIMx peripheral.
TIM_IT,: specifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can only generate an update interrupt.
TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11.
TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
Parameters:
NewState,: new state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1880 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and IS_TIM_IT.

void TIM_SelectCCDMA | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIMx peripheral Capture Compare DMA source.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
NewState,: new state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2148 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST3_PERIPH, and TIM_CR2_CCDS.


STM32L1xx Standard Peripherals Firmware Library: Clocks management functions

Functions

Clocks management functions

TIM_Private_Functions

Clocks management functions. More...

Functions

void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.

Detailed Description

Clocks management functions.

 ===============================================================================
                     ##### Clocks management functions #####
 ===============================================================================

Function Documentation

void TIM_ETRClockMode1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode1.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2273 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), TIM_SlaveMode_External1, TIM_SMCR_SMS, TIM_SMCR_TS, and TIM_TS_ETRF.

void TIM_ETRClockMode2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode2.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2317 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST1_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), and TIM_SMCR_ECE.

void TIM_InternalClockConfig ( TIM_TypeDef * TIMx )

Configures the TIMx internal Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Return values:
None

Definition at line 2187 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

void TIM_ITRxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Configures the TIMx Internal Trigger as External Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ITRSource,: Trigger source. This parameter can be one of the following values:
TIM_TS_ITR0,: Internal Trigger 0.
TIM_TS_ITR1,: Internal Trigger 1.
TIM_TS_ITR2,: Internal Trigger 2.
TIM_TS_ITR3,: Internal Trigger 3.
Return values:
None

Definition at line 2206 of file stm32l1xx_tim.c.

References IS_TIM_INTERNAL_TRIGGER_SELECTION, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TIM_SelectInputTrigger(), and TIM_SlaveMode_External1.

void TIM_TIxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TIxExternalCLKSource,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | ICFilter
 | ) |  |

Configures the TIMx Trigger as External Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_TIxExternalCLKSource,: Trigger source. This parameter can be one of the following values:

  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector.
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1.
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2.
TIM_ICPolarity,: specifies the TIx Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising:
  • TIM_ICPolarity_Falling:
ICFilter : specifies the filter value. This parameter must be a value between 0x0 and 0xF.
Return values:
None

Definition at line 2233 of file stm32l1xx_tim.c.

References IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TI1_Config(), TI2_Config(), TIM_ICSelection_DirectTI, TIM_SelectInputTrigger(), TIM_SlaveMode_External1, and TIM_TIxExternalCLK1Source_TI2.


STM32L1xx Standard Peripherals Firmware Library: Synchronization management functions

Functions

Synchronization management functions

TIM_Private_Functions

Synchronization management functions. More...

Functions

void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.

Detailed Description

Synchronization management functions.

 ===============================================================================
               ##### Synchronization management functions #####
 ===============================================================================
        *** TIM Driver: how to use it in synchronization Mode ***
 ===============================================================================
    [..] Case of two/several Timers
         (#) Configure the Master Timers using the following functions:
             (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
                  uint16_t TIM_TRGOSource).
             (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
                  uint16_t TIM_MasterSlaveMode);
         (#) Configure the Slave Timers using the following functions:
             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
                  uint16_t TIM_InputTriggerSource);
             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
    [..] Case of Timers and external trigger(ETR pin)
         (#) Configure the Etrenal trigger using this function:
             (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
                  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
         (#) Configure the Slave Timers using the following functions:
             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
                  uint16_t TIM_InputTriggerSource);
             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);

Function Documentation

void TIM_ETRConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2502 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST1_PERIPH, TIM_TypeDef::SMCR, and SMCR_ETR_MASK.

Referenced by TIM_ETRClockMode1Config(), and TIM_ETRClockMode2Config().

void TIM_SelectInputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Selects the Input Trigger source.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, or 9 to select the TIM peripheral.
TIM_InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:

  • TIM_TS_ITR0: Internal Trigger 0.
  • TIM_TS_ITR1: Internal Trigger 1.
  • TIM_TS_ITR2: Internal Trigger 2.
  • TIM_TS_ITR3: Internal Trigger 3.
  • TIM_TS_TI1F_ED: TI1 Edge Detector.
  • TIM_TS_TI1FP1: Filtered Timer Input 1.
  • TIM_TS_TI2FP2: Filtered Timer Input 2.
  • TIM_TS_ETRF: External Trigger input.
Return values:
None

Definition at line 2383 of file stm32l1xx_tim.c.

References IS_TIM_LIST1_PERIPH, IS_TIM_TRIGGER_SELECTION, TIM_TypeDef::SMCR, and TIM_SMCR_TS.

Referenced by TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

void TIM_SelectMasterSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_MasterSlaveMode
 | ) |  |

Sets or Resets the TIMx Master/Slave Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_MasterSlaveMode,: specifies the Timer Master Slave Mode. This paramter can be one of the following values:

  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO).
  • TIM_MasterSlaveMode_Disable: No action
Return values:
None

Definition at line 2472 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, IS_TIM_MSM_STATE, TIM_TypeDef::SMCR, and TIM_SMCR_MSM.

void TIM_SelectOutputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TRGOSource
 | ) |  |

Selects the TIMx Trigger Output Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 6, 7 or 9 to select the TIM peripheral.
TIM_TRGOSource,: specifies the Trigger Output source. This paramter can be one of the following values:
For all TIMx

  • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
  • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
  • TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
For all TIMx except TIM6 and TIM7

  • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
  • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
For all TIMx except TIM6, TIM7, TIM10 and TIM11

  • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
For TIM2, TIM3 and TIM4

  • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
  • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
Return values:
None

Definition at line 2426 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, IS_TIM_LIST5_PERIPH, IS_TIM_TRGO_SOURCE, and TIM_CR2_MMS.

void TIM_SelectSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_SlaveMode
 | ) |  |

Selects the TIMx Slave Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_SlaveMode,: specifies the Timer Slave Mode. This paramter can be one of the following values:

  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes the counter and triggers an update of the registers.
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
Return values:
None

Definition at line 2450 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, IS_TIM_SLAVE_MODE, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.


STM32L1xx Standard Peripherals Firmware Library: Specific interface management functions

Functions

Specific interface management functions

TIM_Private_Functions

Specific interface management functions. More...

Functions

void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.

Detailed Description

Specific interface management functions.

 ===============================================================================
             ##### Specific interface management functions #####
 ===============================================================================

Function Documentation

void TIM_EncoderInterfaceConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EncoderMode,
 |  | uint16_t | TIM_IC1Polarity,
 |  | uint16_t | TIM_IC2Polarity
 | ) |  |

Configures the TIMx Encoder Interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_EncoderMode,: specifies the TIMx Encoder Mode. This parameter can be one of the following values:

  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM_IC1Polarity,: specifies the IC1 Polarity. This parmeter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
TIM_IC2Polarity,: specifies the IC2 Polarity This parmeter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
Return values:
None

Definition at line 2557 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, IS_TIM_ENCODER_MODE, IS_TIM_IC_POLARITY, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_CCER_CC1P, TIM_CCER_CC2P, TIM_CCMR1_CC1S, TIM_CCMR1_CC1S_0, TIM_CCMR1_CC2S, TIM_CCMR1_CC2S_0, and TIM_SMCR_SMS.

void TIM_SelectHallSensor | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's Hall sensor interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
NewState,: new state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2600 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST3_PERIPH, and TIM_CR2_TI1S.


STM32L1xx Standard Peripherals Firmware Library: Specific remapping management function

Functions

Specific remapping management function

TIM_Private_Functions

Specific remapping management function. More...

Functions

void TIM_RemapConfig (TIM_TypeDef *TIMx, uint32_t TIM_Remap)
Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.

Detailed Description

Specific remapping management function.

 ===============================================================================
               ##### Specific remapping management function #####
 ===============================================================================

Function Documentation

void TIM_RemapConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_Remap
 | ) |  |

Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.

Parameters:
TIMx,: where x can be 2, 3, 9, 10 or 11 to select the TIM peripheral.
TIM_Remap,: specifies the TIM input remapping source. This parameter can be one of the following values:

  • TIM2_TIM10_OC: TIM2 ITR1 is connected to TIM10 output compare(default).
  • TIM2_TIM5_TRGO: TIM2 ITR1 is connected to TIM5 Trigger output.
  • TIM3_TIM11_OC: TIM3 ITR2 is connected to TIM11 output compare(default).
  • TIM3_TIM5_TRGO: TIM3 ITR2 is connected to TIM5 Trigger output.
  • TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default).
  • TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
  • TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO.
  • TIM9_TS_IO: TIM9 ITR1 is connected to Touch Sense IO.
  • TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default).
  • TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
  • TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
  • TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
  • TIM10_RI: TIM10 Channel 1 is connected to Routing Interface (RI).
  • TIM10_ETR_LSE: TIM10 ETR input is connected to LSE Clock.
  • TIM10_ETR_TIM9_TRGO: TIM10 ETR input is connected to TIM9 Trigger Output.
  • TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default).
  • TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
  • TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
  • TIM11_RI: TIM11 Channel 1 is connected to Routing Interface (RI).
  • TIM11_ETR_LSE: TIM11 ETR input is connected to LSE Clock.
  • TIM11_ETR_TIM9_TRGO: TIM11 ETR input is connected to TIM9 Trigger Output.
Return values:
None

Definition at line 2663 of file stm32l1xx_tim.c.

References IS_TIM_LIST6_PERIPH, IS_TIM_REMAP, and TIM_TypeDef::OR.


STM32L1xx Standard Peripherals Firmware Library: TIM_Private_Functions

Modules | Functions

TIM_Private_Functions

TIM

Modules

TimeBase management functions

TimeBase management functions.

Output Compare management functions

Output Compare management functions.

Input Capture management functions

Input Capture management functions.

Interrupts DMA and flags management functions

Interrupts, DMA and flags management functions.

Clocks management functions

Clocks management functions.

Synchronization management functions

Synchronization management functions.

Specific interface management functions

Specific interface management functions.

Specific remapping management function

Specific remapping management function.

Functions

static void | TI1_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.

Function Documentation

static void TI1_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIMx,: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising: IC Rising edge.
  • TIM_ICPolarity_Falling: IC Falling edge.
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2694 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_CCER_CC1E, TIM_CCER_CC1NP, TIM_CCER_CC1P, TIM_CCMR1_CC1S, and TIM_CCMR1_IC1F.

Referenced by TIM_ICInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

static void TI2_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx,: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising: IC Rising edge.
  • TIM_ICPolarity_Falling: IC Falling edge.
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2730 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_CCER_CC2E, TIM_CCER_CC2NP, TIM_CCER_CC2P, TIM_CCMR1_CC2S, and TIM_CCMR1_IC2F.

Referenced by TIM_ICInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

static void TI3_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx,: where x can be 2, 3 or 4 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising: IC Rising edge.
  • TIM_ICPolarity_Falling: IC Falling edge.
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2768 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_CCER_CC3E, TIM_CCER_CC3NP, TIM_CCER_CC3P, TIM_CCMR2_CC3S, and TIM_CCMR2_IC3F.

Referenced by TIM_ICInit().

static void TI4_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx,: where x can be 2, 3 or 4 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising: IC Rising edge.
  • TIM_ICPolarity_Falling: IC Falling edge.
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2805 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_CCER_CC4E, TIM_CCER_CC4NP, TIM_CCER_CC4P, TIM_CCMR2_CC4S, and TIM_CCMR2_IC4F.

Referenced by TIM_ICInit().


STM32L1xx Standard Peripherals Firmware Library: TIM

Data Structures | Modules | Defines | Functions

TIM

STM32L1xx_StdPeriph_Driver

TIM driver modules. More...

Data Structures

struct | TIM_ICInitTypeDef
TIM Input Capture Init structure definition. More...
struct | TIM_OCInitTypeDef
TIM Output Compare Init structure definition. More...
struct | TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition. More...

Modules

TIM_Exported_constants
TIM_Private_Functions

Defines

#define | CCER_CCE_SET ((uint16_t)0x0001)
#define | CCMR_OFFSET ((uint16_t)0x0018)
#define | SMCR_ETR_MASK ((uint16_t)0x00FF)

Functions

void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint32_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint32_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint32_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint32_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint32_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_RemapConfig (TIM_TypeDef *TIMx, uint32_t TIM_Remap)
Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCREFClear (TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

TIM driver modules.

Define Documentation

#define CCER_CCE_SET ((uint16_t)0x0001)

Definition at line 125 of file stm32l1xx_tim.c.

Referenced by TIM_CCxCmd(), and TIM_SelectOCxM().

#define CCMR_OFFSET ((uint16_t)0x0018)

Definition at line 124 of file stm32l1xx_tim.c.

Referenced by TIM_SelectOCxM().

#define SMCR_ETR_MASK ((uint16_t)0x00FF)

Definition at line 123 of file stm32l1xx_tim.c.

Referenced by TIM_ETRConfig().

Function Documentation

void TIM_ARRPreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables TIMx peripheral Preload register on ARR.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
NewState,: new state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 468 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_ARPE.

void TIM_CCxCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCx
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel. This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1.
  • TIM_Channel_2: TIM Channel 2.
  • TIM_Channel_3: TIM Channel 3.
  • TIM_Channel_4: TIM Channel 4.
TIM_CCx,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
Return values:
None

Definition at line 1497 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, CCER_CCE_SET, IS_TIM_CCX, and IS_TIM_LIST1_PERIPH.

void TIM_ClearFlag | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Clears the TIMx's pending flags.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_FLAG,: specifies the flag bit to clear. This parameter can be any combination of the following values:

  • TIM_FLAG_Update: TIM update Flag.
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
  • TIM_FLAG_Trigger: TIM Trigger Flag.
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
Note:
TIM6 and TIM7 can have only one update flag.
TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
Return values:
None

Definition at line 1988 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_CLEAR_FLAG, and TIM_TypeDef::SR.

void TIM_ClearITPendingBit | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Clears the TIMx's interrupt pending bits.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_IT,: specifies the pending bit to clear. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can generate only an update interrupt.
TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2, and TIM_IT_Trigger interrupt.
TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1 interrupt
Return values:
None

Definition at line 2059 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_IT, and TIM_TypeDef::SR.

void TIM_ClearOC1Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF1 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1268 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC1CE.

void TIM_ClearOC2Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF2 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit.

This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable .
    Return values:
    None

Definition at line 1295 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC2CE.

void TIM_ClearOC3Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF3 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1321 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC3CE.

void TIM_ClearOC4Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF4 signal on an external event.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable.
  • TIM_OCClear_Disable: TIM Output clear disable.
Return values:
None

Definition at line 1347 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC4CE.

void TIM_Cmd | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM peripheral.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIMx peripheral.
NewState,: new state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 538 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_CEN.

void TIM_CounterModeConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CounterMode
 | ) |  |

Specifies the TIMx Counter Mode to be used.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_CounterMode,: specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM_CounterMode_Up: TIM Up Counting Mode.
  • TIM_CounterMode_Down: TIM Down Counting Mode.
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1.
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2.
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3.
Return values:
None

Definition at line 332 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_COUNTER_MODE, IS_TIM_LIST3_PERIPH, TIM_CR1_CMS, and TIM_CR1_DIR.

void TIM_DeInit ( TIM_TypeDef * TIMx )

Deinitializes the TIMx peripheral registers to their default reset values.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
None

Definition at line 180 of file stm32l1xx_tim.c.

References DISABLE, ENABLE, IS_TIM_ALL_PERIPH, RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11, RCC_APB2Periph_TIM9, RCC_APB2PeriphResetCmd(), TIM10, TIM11, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM9.

void TIM_DMACmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMASource,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's DMA Requests.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 6 or 7 to select the TIM peripheral.
TIM_DMASource,: specifies the DMA Request sources. This parameter can be any combination of the following values:

  • TIM_DMA_Update: TIM update Interrupt source.
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source.
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source.
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source.
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source.
  • TIM_DMA_Trigger: TIM Trigger DMA source.
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2122 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_DMA_SOURCE, and IS_TIM_LIST4_PERIPH.

void TIM_DMAConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMABase,
 |  | uint16_t | TIM_DMABurstLength
 | ) |  |

Configures the TIMx's DMA interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_DMABase,: DMA Base address. This parameter can be one of the following values:

  • TIM_DMABase_CR1: TIM CR1 register as TIM DMA Base.
  • TIM_DMABase_CR2: TIM CR2 register as TIM DMA Base.
  • TIM_DMABase_SMCR: TIM SMCR register as TIM DMA Base.
  • TIM_DMABase_DIER: TIM DIER register as TIM DMA Base.
  • TIM_DMABase_SR: TIM SR register as TIM DMA Base.
  • TIM_DMABase_EGR: TIM EGR register as TIM DMA Base.
  • TIM_DMABase_CCMR1: TIM CCMR1 register as TIM DMA Base.
  • TIM_DMABase_CCMR2: TIM CCMR2 register as TIM DMA Base.
  • TIM_DMABase_CCER: TIM CCER register as TIM DMA Base.
  • TIM_DMABase_CNT: TIM CNT register as TIM DMA Base.
  • TIM_DMABase_PSC: TIM PSC register as TIM DMA Base.
  • TIM_DMABase_ARR: TIM ARR register as TIM DMA Base.
  • TIM_DMABase_CCR1: TIM CCR1 register as TIM DMA Base.
  • TIM_DMABase_CCR2: TIM CCR2 register as TIM DMA Base.
  • TIM_DMABase_CCR3: TIM CCR3 register as TIM DMA Base.
  • TIM_DMABase_CCR4: TIM CCR4 register as TIM DMA Base.
  • TIM_DMABase_DCR: TIM DCR register as TIM DMA Base.
  • TIM_DMABase_OR: TIM OR register as TIM DMA Base.
TIM_DMABurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
None

Definition at line 2097 of file stm32l1xx_tim.c.

References TIM_TypeDef::DCR, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, and IS_TIM_LIST3_PERIPH.

void TIM_EncoderInterfaceConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EncoderMode,
 |  | uint16_t | TIM_IC1Polarity,
 |  | uint16_t | TIM_IC2Polarity
 | ) |  |

Configures the TIMx Encoder Interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_EncoderMode,: specifies the TIMx Encoder Mode. This parameter can be one of the following values:

  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM_IC1Polarity,: specifies the IC1 Polarity. This parmeter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
TIM_IC2Polarity,: specifies the IC2 Polarity This parmeter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
Return values:
None

Definition at line 2557 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, IS_TIM_ENCODER_MODE, IS_TIM_IC_POLARITY, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_CCER_CC1P, TIM_CCER_CC2P, TIM_CCMR1_CC1S, TIM_CCMR1_CC1S_0, TIM_CCMR1_CC2S, TIM_CCMR1_CC2S_0, and TIM_SMCR_SMS.

void TIM_ETRClockMode1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode1.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2273 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), TIM_SlaveMode_External1, TIM_SMCR_SMS, TIM_SMCR_TS, and TIM_TS_ETRF.

void TIM_ETRClockMode2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode2.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2317 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST1_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), and TIM_SMCR_ECE.

void TIM_ETRConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 2502 of file stm32l1xx_tim.c.

References IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST1_PERIPH, TIM_TypeDef::SMCR, and SMCR_ETR_MASK.

Referenced by TIM_ETRClockMode1Config(), and TIM_ETRClockMode2Config().

void TIM_ForcedOC1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 1 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC1REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
Return values:
None

Definition at line 956 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST1_PERIPH, and TIM_CCMR1_OC1M.

void TIM_ForcedOC2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 2 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC2REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
Return values:
None

Definition at line 981 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST2_PERIPH, and TIM_CCMR1_OC2M.

void TIM_ForcedOC3Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 3 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC3REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
Return values:
None

Definition at line 1007 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC3M.

void TIM_ForcedOC4Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 4 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC4REF.
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
Return values:
None

Definition at line 1033 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC4M.

void TIM_GenerateEvent | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EventSource
 | ) |  |

Configures the TIMx event to be generate by software.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_EventSource,: specifies the event source. This parameter can be one or more of the following values:

  • TIM_EventSource_Update: Timer update Event source.
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source.
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source.
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source.
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source.
  • TIM_EventSource_Trigger: Timer Trigger Event source.
Note:
TIM6 and TIM7 can only generate an update event.
TIM9 can only generate an update event, Capture Compare 1 event, Capture Compare 2 event and TIM_EventSource_Trigger.
TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
Return values:
None

Definition at line 1916 of file stm32l1xx_tim.c.

References TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, and IS_TIM_EVENT_SOURCE.

uint32_t TIM_GetCapture1 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 1 value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
Return values:
Capture Compare 1 Register value.

Definition at line 1703 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR1, and IS_TIM_LIST1_PERIPH.

uint32_t TIM_GetCapture2 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 2 value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Return values:
Capture Compare 2 Register value.

Definition at line 1717 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR2, and IS_TIM_LIST2_PERIPH.

uint32_t TIM_GetCapture3 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 3 value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Return values:
Capture Compare 3 Register value.

Definition at line 1731 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

uint32_t TIM_GetCapture4 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 4 value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Return values:
Capture Compare 4 Register value.

Definition at line 1745 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

uint32_t TIM_GetCounter ( TIM_TypeDef * TIMx )

Gets the TIMx Counter value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
Counter Register value.

Definition at line 384 of file stm32l1xx_tim.c.

References TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

FlagStatus TIM_GetFlagStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Checks whether the specified TIM flag is set or not.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • TIM_FLAG_Update: TIM update Flag.
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
  • TIM_FLAG_Trigger: TIM Trigger Flag.
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
Note:
TIM6 and TIM7 can have only one update flag.
TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger, TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
Return values:
The new state of TIM_FLAG (SET or RESET).

Definition at line 1947 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, IS_TIM_GET_FLAG, RESET, SET, and TIM_TypeDef::SR.

ITStatus TIM_GetITStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Checks whether the TIM interrupt has occurred or not.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_IT,: specifies the TIM interrupt source to check. This parameter can be one of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can generate only an update interrupt.
TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2, interrupt and TIM_IT_Trigger interrupt.
TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1 interrupt
Return values:
The new state of the TIM_IT(SET or RESET).

Definition at line 2017 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, IS_TIM_ALL_PERIPH, IS_TIM_GET_IT, RESET, SET, and TIM_TypeDef::SR.

uint16_t TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Gets the TIMx Prescaler value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Return values:
Prescaler Register value.

Definition at line 398 of file stm32l1xx_tim.c.

References IS_TIM_ALL_PERIPH, and TIM_TypeDef::PSC.

void TIM_ICInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 1573 of file stm32l1xx_tim.c.

References IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_LIST1_PERIPH, IS_TIM_LIST2_PERIPH, IS_TIM_LIST3_PERIPH, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

void TIM_ICStructInit ( TIM_ICInitTypeDef * TIM_ICInitStruct )

Fills each TIM_ICInitStruct member with its default value.

Parameters:
TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 1629 of file stm32l1xx_tim.c.

References TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, and TIM_ICSelection_DirectTI.

void TIM_InternalClockConfig ( TIM_TypeDef * TIMx )

Configures the TIMx internal Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Return values:
None

Definition at line 2187 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

void TIM_ITConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM interrupts.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIMx peripheral.
TIM_IT,: specifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source.
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
  • TIM_IT_Trigger: TIM Trigger Interrupt source.
Note:
TIM6 and TIM7 can only generate an update interrupt.
TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11.
TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
Parameters:
NewState,: new state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1880 of file stm32l1xx_tim.c.

References TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and IS_TIM_IT.

void TIM_ITRxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Configures the TIMx Internal Trigger as External Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ITRSource,: Trigger source. This parameter can be one of the following values:
TIM_TS_ITR0,: Internal Trigger 0.
TIM_TS_ITR1,: Internal Trigger 1.
TIM_TS_ITR2,: Internal Trigger 2.
TIM_TS_ITR3,: Internal Trigger 3.
Return values:
None

Definition at line 2206 of file stm32l1xx_tim.c.

References IS_TIM_INTERNAL_TRIGGER_SELECTION, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TIM_SelectInputTrigger(), and TIM_SlaveMode_External1.

void TIM_OC1FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 1 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1160 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC1FE.

void TIM_OC1Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 611 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR1, IS_TIM_LIST1_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC1E, TIM_CCER_CC1P, TIM_CCMR1_CC1S, TIM_CCMR1_OC1M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC1PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 1 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1373 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC1P.

void TIM_OC1PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR1.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1058 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST1_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC1PE.

void TIM_OC2FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 2 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1187 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC2FE.

void TIM_OC2Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 663 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR2, IS_TIM_LIST2_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC2E, TIM_CCER_CC2P, TIM_CCMR1_OC2M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC2PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 2 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1398 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST2_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC2P.

void TIM_OC2PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR2.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1083 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_LIST2_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC2PE.

void TIM_OC3FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 3 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1214 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC3FE.

void TIM_OC3Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 714 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR3, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC3E, TIM_CCER_CC3P, TIM_CCMR2_OC3M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC3PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 3 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1423 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC3P.

void TIM_OC3PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR3.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1108 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC3PE.

void TIM_OC4FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 4 Fast feature.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable.
  • TIM_OCFast_Disable: TIM output compare fast disable.
Return values:
None

Definition at line 1241 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC4FE.

void TIM_OC4Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 766 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR4, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OUTPUT_STATE, TIM_CCER_CC4E, TIM_CCER_CC4P, TIM_CCMR2_OC4M, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_OC4PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 4 polarity.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC4 Polarity. This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high.
  • TIM_OCPolarity_Low: Output Compare active low.
Return values:
None

Definition at line 1448 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC4P.

void TIM_OC4PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR4.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register. This parameter can be one of the following values:

  • TIM_OCPreload_Enable: Enable TIM output compare Preload
  • TIM_OCPreload_Disable: Disable TIM output compare Preload
Return values:
None

Definition at line 1134 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC4PE.

void TIM_OCStructInit ( TIM_OCInitTypeDef * TIM_OCInitStruct )

Fills each TIM_OCInitStruct member with its default value.

Parameters:
TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 815 of file stm32l1xx_tim.c.

References TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Disable, and TIM_OCInitTypeDef::TIM_Pulse.

void TIM_PrescalerConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Prescaler,
 |  | uint16_t | TIM_PSCReloadMode
 | ) |  |

Configures the TIMx Prescaler.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Prescaler,: specifies the Prescaler Register value.
TIM_PSCReloadMode,: specifies the TIM Prescaler Reload mode This parameter can be one of the following values:

  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
Return values:
None

Definition at line 308 of file stm32l1xx_tim.c.

References TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_PRESCALER_RELOAD, and TIM_TypeDef::PSC.

void TIM_PWMIConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 1648 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, TI1_Config(), TI2_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Falling, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_ICSelection_IndirectTI, TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

void TIM_RemapConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_Remap
 | ) |  |

Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.

Parameters:
TIMx,: where x can be 2, 3, 9, 10 or 11 to select the TIM peripheral.
TIM_Remap,: specifies the TIM input remapping source. This parameter can be one of the following values:

  • TIM2_TIM10_OC: TIM2 ITR1 is connected to TIM10 output compare(default).
  • TIM2_TIM5_TRGO: TIM2 ITR1 is connected to TIM5 Trigger output.
  • TIM3_TIM11_OC: TIM3 ITR2 is connected to TIM11 output compare(default).
  • TIM3_TIM5_TRGO: TIM3 ITR2 is connected to TIM5 Trigger output.
  • TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default).
  • TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
  • TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO.
  • TIM9_TS_IO: TIM9 ITR1 is connected to Touch Sense IO.
  • TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default).
  • TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
  • TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
  • TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
  • TIM10_RI: TIM10 Channel 1 is connected to Routing Interface (RI).
  • TIM10_ETR_LSE: TIM10 ETR input is connected to LSE Clock.
  • TIM10_ETR_TIM9_TRGO: TIM10 ETR input is connected to TIM9 Trigger Output.
  • TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default).
  • TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
  • TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
  • TIM11_RI: TIM11 Channel 1 is connected to Routing Interface (RI).
  • TIM11_ETR_LSE: TIM11 ETR input is connected to LSE Clock.
  • TIM11_ETR_TIM9_TRGO: TIM11 ETR input is connected to TIM9 Trigger Output.
Return values:
None

Definition at line 2663 of file stm32l1xx_tim.c.

References IS_TIM_LIST6_PERIPH, IS_TIM_REMAP, and TIM_TypeDef::OR.

void TIM_SelectCCDMA | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIMx peripheral Capture Compare DMA source.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
NewState,: new state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2148 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST3_PERIPH, and TIM_CR2_CCDS.

void TIM_SelectHallSensor | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's Hall sensor interface.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
NewState,: new state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2600 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST3_PERIPH, and TIM_CR2_TI1S.

void TIM_SelectInputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Selects the Input Trigger source.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, or 9 to select the TIM peripheral.
TIM_InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:

  • TIM_TS_ITR0: Internal Trigger 0.
  • TIM_TS_ITR1: Internal Trigger 1.
  • TIM_TS_ITR2: Internal Trigger 2.
  • TIM_TS_ITR3: Internal Trigger 3.
  • TIM_TS_TI1F_ED: TI1 Edge Detector.
  • TIM_TS_TI1FP1: Filtered Timer Input 1.
  • TIM_TS_TI2FP2: Filtered Timer Input 2.
  • TIM_TS_ETRF: External Trigger input.
Return values:
None

Definition at line 2383 of file stm32l1xx_tim.c.

References IS_TIM_LIST1_PERIPH, IS_TIM_TRIGGER_SELECTION, TIM_TypeDef::SMCR, and TIM_SMCR_TS.

Referenced by TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

void TIM_SelectMasterSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_MasterSlaveMode
 | ) |  |

Sets or Resets the TIMx Master/Slave Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_MasterSlaveMode,: specifies the Timer Master Slave Mode. This paramter can be one of the following values:

  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO).
  • TIM_MasterSlaveMode_Disable: No action
Return values:
None

Definition at line 2472 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, IS_TIM_MSM_STATE, TIM_TypeDef::SMCR, and TIM_SMCR_MSM.

void TIM_SelectOCREFClear | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCReferenceClear
 | ) |  |

Selects the OCReference Clear source.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_OCReferenceClear,: specifies the OCReference Clear source. This parameter can be one of the following values:

  • TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
  • TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
Return values:
None

Definition at line 1473 of file stm32l1xx_tim.c.

References IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_OCREFERENCECECLEAR_SOURCE, and TIM_SMCR_OCCS.

void TIM_SelectOCxM | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_OCMode
 | ) |  |

Selects the TIM Output Compare Mode.

Note:
This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel. This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1.
  • TIM_Channel_2: TIM Channel 2.
  • TIM_Channel_3: TIM Channel 3.
  • TIM_Channel_4: TIM Channel 4.
TIM_OCMode,: specifies the TIM Output Compare Mode. This parameter can be one of the following values:

  • TIM_OCMode_Timing: TIM Output Compare Timing mode.
  • TIM_OCMode_Active: TIM Output Compare Active mode.
  • TIM_OCMode_Inactive: TIM Output Compare Inactive mode.
  • TIM_OCMode_Toggle: TIM Output Compare Toggle mode.
  • TIM_OCMode_PWM1: TIM Output Compare PWM1 mode.
  • TIM_OCMode_PWM2: TIM Output Compare PWM2 mode.
  • TIM_ForcedAction_Active: TIM Forced Action Active mode.
  • TIM_ForcedAction_InActive: TIM Forced Action Inactive mode.
Return values:
None

Definition at line 848 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCER, CCER_CCE_SET, CCMR_OFFSET, IS_TIM_LIST1_PERIPH, IS_TIM_OCM, TIM_CCMR1_OC1M, TIM_CCMR1_OC2M, TIM_Channel_1, and TIM_Channel_3.

void TIM_SelectOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OPMode
 | ) |  |

Selects the TIMx's One Pulse Mode.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_OPMode,: specifies the OPM Mode to be used. This parameter can be one of the following values:

  • TIM_OPMode_Single:: TIM One Pulse Single Mode (Counter stops counting at the next update event (clearing the bit CEN)).
  • TIM_OPMode_Repetitive: TIM One Pulse Repetitive Mode (Counter is not stopped at update event).
Return values:
None

Definition at line 497 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_OPM_MODE, and TIM_CR1_OPM.

void TIM_SelectOutputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TRGOSource
 | ) |  |

Selects the TIMx Trigger Output Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 6, 7 or 9 to select the TIM peripheral.
TIM_TRGOSource,: specifies the Trigger Output source. This paramter can be one of the following values:
For all TIMx

  • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
  • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
  • TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
For all TIMx except TIM6 and TIM7

  • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
  • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
For all TIMx except TIM6, TIM7, TIM10 and TIM11

  • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
For TIM2, TIM3 and TIM4

  • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
  • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
Return values:
None

Definition at line 2426 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR2, IS_TIM_LIST5_PERIPH, IS_TIM_TRGO_SOURCE, and TIM_CR2_MMS.

void TIM_SelectSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_SlaveMode
 | ) |  |

Selects the TIMx Slave Mode.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_SlaveMode,: specifies the Timer Slave Mode. This paramter can be one of the following values:

  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes the counter and triggers an update of the registers.
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
Return values:
None

Definition at line 2450 of file stm32l1xx_tim.c.

References IS_TIM_LIST2_PERIPH, IS_TIM_SLAVE_MODE, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

void TIM_SetAutoreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Autoreload
 | ) |  |

Sets the TIMx Autoreload Register value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Autoreload,: specifies the Autoreload register new value.
Return values:
None

Definition at line 370 of file stm32l1xx_tim.c.

References TIM_TypeDef::ARR, and IS_TIM_ALL_PERIPH.

void TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CKD
 | ) |  |

Sets the TIMx Clock Division value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_CKD,: specifies the clock division value. This parameter can be one of the following value:

  • TIM_CKD_DIV1: TDTS = Tck_tim.
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim.
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim.
Return values:
None

Definition at line 519 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_CKD_DIV, IS_TIM_LIST1_PERIPH, and TIM_CR1_CKD.

void TIM_SetCompare1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare1
 | ) |  |

Sets the TIMx Capture Compare1 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
Compare1,: specifies the Capture Compare1 register new value.
Return values:
None

Definition at line 893 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR1, and IS_TIM_LIST1_PERIPH.

void TIM_SetCompare2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare2
 | ) |  |

Sets the TIMx Capture Compare2 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
Compare2,: specifies the Capture Compare2 register new value.
Return values:
None

Definition at line 908 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR2, and IS_TIM_LIST2_PERIPH.

void TIM_SetCompare3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare3
 | ) |  |

Sets the TIMx Capture Compare3 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Compare3,: specifies the Capture Compare3 register new value.
Return values:
None

Definition at line 923 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

void TIM_SetCompare4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Compare4
 | ) |  |

Sets the TIMx Capture Compare4 Register value.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
Compare4,: specifies the Capture Compare4 register new value.
Return values:
None

Definition at line 938 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

void TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Sets the TIMx Counter Register value.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
Counter,: specifies the Counter register new value.
Return values:
None

Definition at line 355 of file stm32l1xx_tim.c.

References TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

void TIM_SetIC1Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 1 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture1 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1765 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST1_PERIPH, and TIM_CCMR1_IC1PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC2Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 2 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture2 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1788 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST2_PERIPH, and TIM_CCMR1_IC2PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC3Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 3 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture3 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1811 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC3PSC.

Referenced by TIM_ICInit().

void TIM_SetIC4Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 4 prescaler.

Parameters:
TIMx,: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler.
  • TIM_ICPSC_DIV2: capture is done once every 2 events.
  • TIM_ICPSC_DIV4: capture is done once every 4 events.
  • TIM_ICPSC_DIV8: capture is done once every 8 events.
Return values:
None

Definition at line 1834 of file stm32l1xx_tim.c.

References TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC4PSC.

Referenced by TIM_ICInit().

void TIM_TimeBaseInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_TimeBaseInitTypeDef * | TIM_TimeBaseInitStruct
 | ) |  |

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_TimeBaseInitStruct,: pointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 246 of file stm32l1xx_tim.c.

References TIM_TypeDef::ARR, TIM_TypeDef::CR1, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_CKD_DIV, IS_TIM_COUNTER_MODE, TIM_TypeDef::PSC, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CR1_CKD, TIM_CR1_CMS, TIM_CR1_DIR, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, and TIM_PSCReloadMode_Immediate.

void TIM_TimeBaseStructInit ( TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct )

Fills each TIM_TimeBaseInitStruct member with its default value.

Parameters:
TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 289 of file stm32l1xx_tim.c.

References TIM_CKD_DIV1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, and TIM_TimeBaseInitTypeDef::TIM_Prescaler.

void TIM_TIxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TIxExternalCLKSource,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | ICFilter
 | ) |  |

Configures the TIMx Trigger as External Clock.

Parameters:
TIMx,: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
TIM_TIxExternalCLKSource,: Trigger source. This parameter can be one of the following values:

  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector.
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1.
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2.
TIM_ICPolarity,: specifies the TIx Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising:
  • TIM_ICPolarity_Falling:
ICFilter : specifies the filter value. This parameter must be a value between 0x0 and 0xF.
Return values:
None

Definition at line 2233 of file stm32l1xx_tim.c.

References IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_LIST2_PERIPH, TIM_TypeDef::SMCR, TI1_Config(), TI2_Config(), TIM_ICSelection_DirectTI, TIM_SelectInputTrigger(), TIM_SlaveMode_External1, and TIM_TIxExternalCLK1Source_TI2.

void TIM_UpdateDisableConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the TIMx Update event.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
NewState,: new state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 414 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_UDIS.

void TIM_UpdateRequestConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_UpdateSource
 | ) |  |

Configures the TIMx Update Request Interrupt source.

Parameters:
TIMx,: where x can be 2 to 11 to select the TIM peripheral.
TIM_UpdateSource,: specifies the Update source. This parameter can be one of the following values:

  • TIM_UpdateSource_Global: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
  • TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
Return values:
None

Definition at line 443 of file stm32l1xx_tim.c.

References TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_UPDATE_SOURCE, TIM_CR1_URS, and TIM_UpdateSource_Global.


STM32L1xx Standard Peripherals Firmware Library: TIM_ICInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_ICInitTypeDef Struct Reference
TIM

TIM Input Capture Init structure definition. More...

#include <stm32l1xx_tim.h>

Data Fields

uint16_t | TIM_Channel
uint16_t | TIM_ICFilter
uint16_t | TIM_ICPolarity
uint16_t | TIM_ICPrescaler
uint16_t | TIM_ICSelection

Detailed Description

TIM Input Capture Init structure definition.

Definition at line 93 of file stm32l1xx_tim.h.

Field Documentation

uint16_t TIM_ICInitTypeDef::TIM_Channel

Specifies the TIM channel. This parameter can be a value of TIM_Channel

Definition at line 96 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICFilter

Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF

Definition at line 108 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM_Input_Capture_Polarity

Definition at line 99 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM_Input_Capture_Prescaler

Definition at line 105 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICSelection

Specifies the input. This parameter can be a value of TIM_Input_Capture_Selection

Definition at line 102 of file stm32l1xx_tim.h.

Referenced by TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

The documentation for this struct was generated from the following file:
  • stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: TIM_OCInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_OCInitTypeDef Struct Reference
TIM

TIM Output Compare Init structure definition. More...

#include <stm32l1xx_tim.h>

Data Fields

uint16_t | TIM_OCMode
uint16_t | TIM_OCPolarity
uint16_t | TIM_OutputState
uint32_t | TIM_Pulse

Detailed Description

TIM Output Compare Init structure definition.

Definition at line 73 of file stm32l1xx_tim.h.

Field Documentation

uint16_t TIM_OCInitTypeDef::TIM_OCMode

Specifies the TIM mode. This parameter can be a value of TIM_Output_Compare_and_PWM_modes

Definition at line 75 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OCPolarity

Specifies the output polarity. This parameter can be a value of TIM_Output_Compare_Polarity

Definition at line 84 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OutputState

Specifies the TIM Output Compare state. This parameter can be a value of TIM_Output_Compare_state

Definition at line 78 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint32_t TIM_OCInitTypeDef::TIM_Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF

Definition at line 81 of file stm32l1xx_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: TIM_TimeBaseInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_TimeBaseInitTypeDef Struct Reference
TIM

TIM Time Base Init structure definition. More...

#include <stm32l1xx_tim.h>

Data Fields

uint16_t | TIM_ClockDivision
uint16_t | TIM_CounterMode
uint32_t | TIM_Period
uint16_t | TIM_Prescaler

Detailed Description

TIM Time Base Init structure definition.

Note:
This structure is used with all TIMx except for TIM6 and TIM7.

Definition at line 52 of file stm32l1xx_tim.h.

Field Documentation

uint16_t TIM_TimeBaseInitTypeDef::TIM_ClockDivision

Specifies the clock division. This parameter can be a value of TIM_Clock_Division_CKD

Definition at line 64 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint16_t TIM_TimeBaseInitTypeDef::TIM_CounterMode

Specifies the counter mode. This parameter can be a value of TIM_Counter_Mode

Definition at line 57 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint32_t TIM_TimeBaseInitTypeDef::TIM_Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF.

Definition at line 60 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint16_t TIM_TimeBaseInitTypeDef::TIM_Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF

Definition at line 54 of file stm32l1xx_tim.h.

Referenced by TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: USART_Word_Length

Defines

USART_Word_Length

USART_Exported_Constants

Defines

#define | IS_USART_WORD_LENGTH(LENGTH)
#define | USART_WordLength_8b ((uint16_t)0x0000)
#define | USART_WordLength_9b ((uint16_t)0x1000)

Define Documentation

#define IS_USART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_WordLength_8b) || \
                                      ((LENGTH) == USART_WordLength_9b))

Definition at line 124 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define USART_WordLength_8b ((uint16_t)0x0000)

Definition at line 121 of file stm32l1xx_usart.h.

Referenced by USART_StructInit().

#define USART_WordLength_9b ((uint16_t)0x1000)

Definition at line 122 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Stop_Bits

Defines

USART_Stop_Bits

USART_Exported_Constants

Defines

#define | IS_USART_STOPBITS(STOPBITS)
#define | USART_StopBits_0_5 ((uint16_t)0x1000)
#define | USART_StopBits_1 ((uint16_t)0x0000)
#define | USART_StopBits_1_5 ((uint16_t)0x3000)
#define | USART_StopBits_2 ((uint16_t)0x2000)

Define Documentation

#define IS_USART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == USART_StopBits_1) || \
                                     ((STOPBITS) == USART_StopBits_0_5) || \
                                     ((STOPBITS) == USART_StopBits_2) || \
                                     ((STOPBITS) == USART_StopBits_1_5))

Definition at line 138 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define USART_StopBits_0_5 ((uint16_t)0x1000)

Definition at line 135 of file stm32l1xx_usart.h.

#define USART_StopBits_1 ((uint16_t)0x0000)

Definition at line 134 of file stm32l1xx_usart.h.

Referenced by USART_StructInit().

#define USART_StopBits_1_5 ((uint16_t)0x3000)

Definition at line 137 of file stm32l1xx_usart.h.

#define USART_StopBits_2 ((uint16_t)0x2000)

Definition at line 136 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Parity

Defines

USART_Parity

USART_Exported_Constants

Defines

#define | IS_USART_PARITY(PARITY)
#define | USART_Parity_Even ((uint16_t)0x0400)
#define | USART_Parity_No ((uint16_t)0x0000)
#define | USART_Parity_Odd ((uint16_t)0x0600)

Define Documentation

#define IS_USART_PARITY ( PARITY )
Value:
(((PARITY) == USART_Parity_No) || \
                                 ((PARITY) == USART_Parity_Even) || \
                                 ((PARITY) == USART_Parity_Odd))

Definition at line 153 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define USART_Parity_Even ((uint16_t)0x0400)

Definition at line 151 of file stm32l1xx_usart.h.

#define USART_Parity_No ((uint16_t)0x0000)

Definition at line 150 of file stm32l1xx_usart.h.

Referenced by USART_StructInit().

#define USART_Parity_Odd ((uint16_t)0x0600)

Definition at line 152 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Mode

Defines

USART_Mode

USART_Exported_Constants

Defines

#define | IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
#define | USART_Mode_Rx ((uint16_t)0x0004)
#define | USART_Mode_Tx ((uint16_t)0x0008)

Define Documentation

#define IS_USART_MODE ( MODE ) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))

Definition at line 166 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define USART_Mode_Rx ((uint16_t)0x0004)

Definition at line 164 of file stm32l1xx_usart.h.

Referenced by USART_StructInit().

#define USART_Mode_Tx ((uint16_t)0x0008)

Definition at line 165 of file stm32l1xx_usart.h.

Referenced by USART_StructInit().


STM32L1xx Standard Peripherals Firmware Library: USART_Hardware_Flow_Control

Defines

USART_Hardware_Flow_Control

USART_Exported_Constants

Defines

#define | IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define | USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define | USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define | USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)

Define Documentation

#define IS_USART_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == USART_HardwareFlowControl_None) || \
                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))

Definition at line 178 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)

Definition at line 176 of file stm32l1xx_usart.h.

#define USART_HardwareFlowControl_None ((uint16_t)0x0000)

Definition at line 174 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)

Definition at line 175 of file stm32l1xx_usart.h.

#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)

Definition at line 177 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Clock

Defines

USART_Clock

USART_Exported_Constants

Defines

#define | IS_USART_CLOCK(CLOCK)
#define | USART_Clock_Disable ((uint16_t)0x0000)
#define | USART_Clock_Enable ((uint16_t)0x0800)

Define Documentation

#define IS_USART_CLOCK ( CLOCK )
Value:
(((CLOCK) == USART_Clock_Disable) || \
                               ((CLOCK) == USART_Clock_Enable))

Definition at line 192 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit().

#define USART_Clock_Disable ((uint16_t)0x0000)

Definition at line 190 of file stm32l1xx_usart.h.

Referenced by USART_ClockStructInit().

#define USART_Clock_Enable ((uint16_t)0x0800)

Definition at line 191 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Clock_Polarity

Defines

USART_Clock_Polarity

USART_Exported_Constants

Defines

#define | IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
#define | USART_CPOL_High ((uint16_t)0x0400)
#define | USART_CPOL_Low ((uint16_t)0x0000)

Define Documentation

#define IS_USART_CPOL ( CPOL ) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))

Definition at line 204 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit().

#define USART_CPOL_High ((uint16_t)0x0400)

Definition at line 203 of file stm32l1xx_usart.h.

#define USART_CPOL_Low ((uint16_t)0x0000)

Definition at line 202 of file stm32l1xx_usart.h.

Referenced by USART_ClockStructInit().


STM32L1xx Standard Peripherals Firmware Library: USART_Clock_Phase

Defines

USART_Clock_Phase

USART_Exported_Constants

Defines

#define | IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
#define | USART_CPHA_1Edge ((uint16_t)0x0000)
#define | USART_CPHA_2Edge ((uint16_t)0x0200)

Define Documentation

#define IS_USART_CPHA ( CPHA ) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))

Definition at line 216 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit().

#define USART_CPHA_1Edge ((uint16_t)0x0000)

Definition at line 214 of file stm32l1xx_usart.h.

Referenced by USART_ClockStructInit().

#define USART_CPHA_2Edge ((uint16_t)0x0200)

Definition at line 215 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Last_Bit

Defines

USART_Last_Bit

USART_Exported_Constants

Defines

#define | IS_USART_LASTBIT(LASTBIT)
#define | USART_LastBit_Disable ((uint16_t)0x0000)
#define | USART_LastBit_Enable ((uint16_t)0x0100)

Define Documentation

#define IS_USART_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == USART_LastBit_Disable) || \
                                   ((LASTBIT) == USART_LastBit_Enable))

Definition at line 228 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit().

#define USART_LastBit_Disable ((uint16_t)0x0000)

Definition at line 226 of file stm32l1xx_usart.h.

Referenced by USART_ClockStructInit().

#define USART_LastBit_Enable ((uint16_t)0x0100)

Definition at line 227 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Legacy

Defines

USART_Legacy

USART_Interrupt_definition

Defines

#define USART_IT_ORE USART_IT_ORE_ER

Define Documentation

#define USART_IT_ORE USART_IT_ORE_ER

Definition at line 254 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Interrupt_definition

Modules | Defines

USART_Interrupt_definition

USART_Exported_Constants

Modules

USART_Legacy

Defines

#define | IS_USART_CLEAR_IT(IT)
#define | IS_USART_CONFIG_IT(IT)
#define | IS_USART_GET_IT(IT)
#define | USART_IT_CTS ((uint16_t)0x096A)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_FE ((uint16_t)0x0160)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_LBD ((uint16_t)0x0846)
#define | USART_IT_NE ((uint16_t)0x0260)
#define | USART_IT_ORE_ER ((uint16_t)0x0360)
#define | USART_IT_ORE_RX ((uint16_t)0x0325)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_TXE ((uint16_t)0x0727)

Define Documentation

#define IS_USART_CLEAR_IT ( IT )
Value:
(((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))

Definition at line 269 of file stm32l1xx_usart.h.

Referenced by USART_ClearITPendingBit().

#define IS_USART_CONFIG_IT ( IT )
Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))

Definition at line 259 of file stm32l1xx_usart.h.

Referenced by USART_ITConfig().

#define IS_USART_GET_IT ( IT )
Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
                             ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
                             ((IT) == USART_IT_FE))

Definition at line 263 of file stm32l1xx_usart.h.

Referenced by USART_GetITStatus().

#define USART_IT_CTS ((uint16_t)0x096A)

Definition at line 245 of file stm32l1xx_usart.h.

Referenced by USART_ClearITPendingBit(), USART_GetITStatus(), and USART_ITConfig().

#define USART_IT_ERR ((uint16_t)0x0060)

Definition at line 246 of file stm32l1xx_usart.h.

#define USART_IT_FE ((uint16_t)0x0160)

Definition at line 249 of file stm32l1xx_usart.h.

#define USART_IT_IDLE ((uint16_t)0x0424)

Definition at line 242 of file stm32l1xx_usart.h.

#define USART_IT_LBD ((uint16_t)0x0846)

Definition at line 243 of file stm32l1xx_usart.h.

#define USART_IT_NE ((uint16_t)0x0260)

Definition at line 248 of file stm32l1xx_usart.h.

#define USART_IT_ORE_ER ((uint16_t)0x0360)

Definition at line 247 of file stm32l1xx_usart.h.

#define USART_IT_ORE_RX ((uint16_t)0x0325)

Definition at line 244 of file stm32l1xx_usart.h.

#define USART_IT_PE ((uint16_t)0x0028)

Definition at line 238 of file stm32l1xx_usart.h.

#define USART_IT_RXNE ((uint16_t)0x0525)

Definition at line 241 of file stm32l1xx_usart.h.

#define USART_IT_TC ((uint16_t)0x0626)

Definition at line 240 of file stm32l1xx_usart.h.

#define USART_IT_TXE ((uint16_t)0x0727)

Definition at line 239 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_DMA_Requests

Defines

USART_DMA_Requests

USART_Exported_Constants

Defines

#define | IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
#define | USART_DMAReq_Rx ((uint16_t)0x0040)
#define | USART_DMAReq_Tx ((uint16_t)0x0080)

Define Documentation

#define IS_USART_DMAREQ ( DMAREQ ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))

Definition at line 281 of file stm32l1xx_usart.h.

Referenced by USART_DMACmd().

#define USART_DMAReq_Rx ((uint16_t)0x0040)

Definition at line 280 of file stm32l1xx_usart.h.

#define USART_DMAReq_Tx ((uint16_t)0x0080)

Definition at line 279 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_WakeUp_methods

Defines

USART_WakeUp_methods

USART_Exported_Constants

Defines

#define | IS_USART_WAKEUP(WAKEUP)
#define | USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define | USART_WakeUp_IdleLine ((uint16_t)0x0000)

Define Documentation

#define IS_USART_WAKEUP ( WAKEUP )
Value:
(((WAKEUP) == USART_WakeUp_IdleLine) || \
                                 ((WAKEUP) == USART_WakeUp_AddressMark))

Definition at line 293 of file stm32l1xx_usart.h.

Referenced by USART_WakeUpConfig().

#define USART_WakeUp_AddressMark ((uint16_t)0x0800)

Definition at line 292 of file stm32l1xx_usart.h.

#define USART_WakeUp_IdleLine ((uint16_t)0x0000)

Definition at line 291 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_LIN_Break_Detection_Length

Defines

USART_LIN_Break_Detection_Length

USART_Exported_Constants

Defines

#define | IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define | USART_LINBreakDetectLength_11b ((uint16_t)0x0020)

Define Documentation

#define IS_USART_LIN_BREAK_DETECT_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
                                ((LENGTH) == USART_LINBreakDetectLength_11b))

Definition at line 305 of file stm32l1xx_usart.h.

Referenced by USART_LINBreakDetectLengthConfig().

#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)

Definition at line 303 of file stm32l1xx_usart.h.

#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)

Definition at line 304 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_IrDA_Low_Power

Defines

USART_IrDA_Low_Power

USART_Exported_Constants

Defines

#define | IS_USART_IRDA_MODE(MODE)
#define | USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define | USART_IrDAMode_Normal ((uint16_t)0x0000)

Define Documentation

#define IS_USART_IRDA_MODE ( MODE )
Value:
(((MODE) == USART_IrDAMode_LowPower) || \
                                  ((MODE) == USART_IrDAMode_Normal))

Definition at line 318 of file stm32l1xx_usart.h.

Referenced by USART_IrDAConfig().

#define USART_IrDAMode_LowPower ((uint16_t)0x0004)

Definition at line 316 of file stm32l1xx_usart.h.

#define USART_IrDAMode_Normal ((uint16_t)0x0000)

Definition at line 317 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Flags

Defines

USART_Flags

USART_Exported_Constants

Defines

#define | IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define | IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
#define | IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
#define | IS_USART_FLAG(FLAG)
#define | USART_FLAG_CTS ((uint16_t)0x0200)
#define | USART_FLAG_FE ((uint16_t)0x0002)
#define | USART_FLAG_IDLE ((uint16_t)0x0010)
#define | USART_FLAG_LBD ((uint16_t)0x0100)
#define | USART_FLAG_NE ((uint16_t)0x0004)
#define | USART_FLAG_ORE ((uint16_t)0x0008)
#define | USART_FLAG_PE ((uint16_t)0x0001)
#define | USART_FLAG_RXNE ((uint16_t)0x0020)
#define | USART_FLAG_TC ((uint16_t)0x0040)
#define | USART_FLAG_TXE ((uint16_t)0x0080)

Define Documentation

#define IS_USART_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0xF)

Definition at line 347 of file stm32l1xx_usart.h.

Referenced by USART_SetAddress().

#define IS_USART_BAUDRATE ( BAUDRATE ) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))

Definition at line 346 of file stm32l1xx_usart.h.

Referenced by USART_Init().

#define IS_USART_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))

Definition at line 344 of file stm32l1xx_usart.h.

Referenced by USART_ClearFlag().

#define IS_USART_DATA ( DATA ) ((DATA) <= 0x1FF)

Definition at line 348 of file stm32l1xx_usart.h.

Referenced by USART_SendData().

#define IS_USART_FLAG ( FLAG )
Value:
(((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))

Definition at line 338 of file stm32l1xx_usart.h.

Referenced by USART_GetFlagStatus().

#define USART_FLAG_CTS ((uint16_t)0x0200)

Definition at line 328 of file stm32l1xx_usart.h.

Referenced by USART_ClearFlag(), and USART_GetFlagStatus().

#define USART_FLAG_FE ((uint16_t)0x0002)

Definition at line 336 of file stm32l1xx_usart.h.

#define USART_FLAG_IDLE ((uint16_t)0x0010)

Definition at line 333 of file stm32l1xx_usart.h.

#define USART_FLAG_LBD ((uint16_t)0x0100)

Definition at line 329 of file stm32l1xx_usart.h.

#define USART_FLAG_NE ((uint16_t)0x0004)

Definition at line 335 of file stm32l1xx_usart.h.

#define USART_FLAG_ORE ((uint16_t)0x0008)

Definition at line 334 of file stm32l1xx_usart.h.

#define USART_FLAG_PE ((uint16_t)0x0001)

Definition at line 337 of file stm32l1xx_usart.h.

#define USART_FLAG_RXNE ((uint16_t)0x0020)

Definition at line 332 of file stm32l1xx_usart.h.

#define USART_FLAG_TC ((uint16_t)0x0040)

Definition at line 331 of file stm32l1xx_usart.h.

#define USART_FLAG_TXE ((uint16_t)0x0080)

Definition at line 330 of file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: USART_Exported_Constants

Modules | Defines

USART_Exported_Constants

USART

Modules

USART_Word_Length
USART_Stop_Bits
USART_Parity
USART_Mode
USART_Hardware_Flow_Control
USART_Clock
USART_Clock_Polarity
USART_Clock_Phase
USART_Last_Bit
USART_Interrupt_definition
USART_DMA_Requests
USART_WakeUp_methods
USART_LIN_Break_Detection_Length
USART_IrDA_Low_Power
USART_Flags

Defines

#define | IS_USART_123_PERIPH(PERIPH)
#define | IS_USART_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_USART_123_PERIPH ( PERIPH )
Value:
(((PERIPH) == USART1) || \
                                     ((PERIPH) == USART2) || \
                                     ((PERIPH) == USART3))

Definition at line 113 of file stm32l1xx_usart.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_ClockInit(), USART_GetFlagStatus(), USART_GetITStatus(), USART_Init(), USART_ITConfig(), USART_SetGuardTime(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

#define IS_USART_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == USART1) || \
                                     ((PERIPH) == USART2) || \
                                     ((PERIPH) == USART3) || \
                                     ((PERIPH) == UART4) || \
                                     ((PERIPH) == UART5))

Definition at line 107 of file stm32l1xx_usart.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_Cmd(), USART_DeInit(), USART_DMACmd(), USART_GetFlagStatus(), USART_GetITStatus(), USART_HalfDuplexCmd(), USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_ITConfig(), USART_LINBreakDetectLengthConfig(), USART_LINCmd(), USART_OneBitMethodCmd(), USART_OverSampling8Cmd(), USART_ReceiveData(), USART_ReceiverWakeUpCmd(), USART_SendBreak(), USART_SendData(), USART_SetAddress(), USART_SetPrescaler(), and USART_WakeUpConfig().


STM32L1xx Standard Peripherals Firmware Library: Initialization and Configuration functions

Functions

Initialization and Configuration functions

USART_Private_Functions

Initialization and Configuration functions. More...

Functions

void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
        This subsection provides a set of functions allowing to initialize the USART
        in asynchronous and in synchronous modes.
        (+) For the asynchronous mode only these parameters can be configured:
        (+) Baud Rate.
        (+) Word Length.
        (+) Stop Bit.
        (+) Parity: If the parity is enabled, then the MSB bit of the data written
          in the data register is transmitted but is changed by the parity bit.
          Depending on the frame length defined by the M bit (8-bits or 9-bits),
          the possible USART frame formats are as listed in the following table:
    [..]
   +-------------------------------------------------------------+
   |   M bit |  PCE bit  |            USART frame                |
   |---------------------|---------------------------------------|
   |    0    |    0      |    | SB | 8 bit data | STB |          |
   |---------|-----------|---------------------------------------|
   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
   |---------|-----------|---------------------------------------|
   |    1    |    0      |    | SB | 9 bit data | STB |          |
   |---------|-----------|---------------------------------------|
   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
   +-------------------------------------------------------------+
    [..]
        (+) Hardware flow control.
        (+) Receiver/transmitter modes.
    [..] The USART_Init() function follows the USART  asynchronous configuration
         procedure(details for the procedure are available in reference manual
         (RM0038)).
        (+) For the synchronous mode in addition to the asynchronous mode parameters
            these parameters should be also configured:
            (++) USART Clock Enabled.
            (++) USART polarity.
            (++) USART phase.
            (++) USART LastBit.
    [..] These parameters can be configured using the USART_ClockInit() function.

Function Documentation

void USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.

Parameters:
USARTx,: where x can be 1, 2, 3 to select the USART peripheral.
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
Note:
The Smart Card and Synchronous modes are not available for UART4 and UART5.
Return values:
None.

Definition at line 345 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, CR2_CLOCK_CLEAR_MASK, IS_USART_123_PERIPH, IS_USART_CLOCK, IS_USART_CPHA, IS_USART_CPOL, IS_USART_LASTBIT, USART_ClockInitTypeDef::USART_Clock, USART_ClockInitTypeDef::USART_CPHA, USART_ClockInitTypeDef::USART_CPOL, and USART_ClockInitTypeDef::USART_LastBit.

void USART_ClockStructInit ( USART_ClockInitTypeDef * USART_ClockInitStruct )

Fills each USART_ClockInitStruct member with its default value.

Parameters:
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 376 of file stm32l1xx_usart.c.

References USART_ClockInitTypeDef::USART_Clock, USART_Clock_Disable, USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_1Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_Low, USART_ClockInitTypeDef::USART_LastBit, and USART_LastBit_Disable.

void USART_Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 394 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_UE.

void USART_DeInit ( USART_TypeDef * USARTx )

Deinitializes the USARTx peripheral registers to their default reset values.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None.

Definition at line 170 of file stm32l1xx_usart.c.

References DISABLE, ENABLE, IS_USART_ALL_PERIPH, RCC_APB1Periph_UART4, RCC_APB1Periph_UART5, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_USART1, RCC_APB2PeriphResetCmd(), UART4, UART5, USART1, USART2, and USART3.

void USART_Init | ( | USART_TypeDef * | USARTx,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None.

Definition at line 215 of file stm32l1xx_usart.c.

References USART_TypeDef::BRR, USART_TypeDef::CR1, CR1_CLEAR_MASK, USART_TypeDef::CR2, USART_TypeDef::CR3, CR3_CLEAR_MASK, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_BAUDRATE, IS_USART_HARDWARE_FLOW_CONTROL, IS_USART_MODE, IS_USART_PARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetClocksFreq(), USART1, USART_InitTypeDef::USART_BaudRate, USART_CR1_OVER8, USART_CR2_STOP, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_InitTypeDef::USART_Parity, USART_InitTypeDef::USART_StopBits, and USART_InitTypeDef::USART_WordLength.

void USART_OneBitMethodCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's one bit sampling method.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 472 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_ONEBIT.

void USART_OverSampling8Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's 8x oversampling mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART 8x oversampling mode. This parameter can be: ENABLE or DISABLE.
Note:
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
Return values:
None

Definition at line 445 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_OVER8.

void USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Prescaler
 | ) |  |

Sets the system clock prescaler.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Prescaler,: specifies the prescaler clock.
Note:
The function is used for IrDA mode with UART4 and UART5.
Return values:
None.

Definition at line 421 of file stm32l1xx_usart.c.

References USART_TypeDef::GTPR, IS_USART_ALL_PERIPH, and USART_GTPR_GT.

void USART_StructInit ( USART_InitTypeDef * USART_InitStruct )

Fills each USART_InitStruct member with its default value.

Parameters:
USART_InitStruct,: pointer to a USART_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 324 of file stm32l1xx_usart.c.

References USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.


STM32L1xx Standard Peripherals Firmware Library: Data transfers functions

Functions

Data transfers functions

USART_Private_Functions

Data transfers functions. More...

Functions

uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.

Detailed Description

Data transfers functions.

 ===============================================================================
                    ##### Data transfers functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage
         the USART data transfers.
    [..] During an USART reception, data shifts in least significant bit first
         through the RX pin. In this mode, the USART_DR register consists of
         a buffer (RDR) between the internal bus and the received shift register.
         When a transmission is taking place, a write instruction to
         the USART_DR register stores the data in the TDR register and which is
         copied in the shift register at the end of the current transmission.
    [..] The read access of the USART_DR register can be done using
         the USART_ReceiveData() function and returns the RDR buffered value.
        Whereas a write access to the USART_DR can be done using USART_SendData()
        function and stores the written data into TDR buffer.

Function Documentation

uint16_t USART_ReceiveData ( USART_TypeDef * USARTx )

Returns the most recent received data by the USARTx peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
The received data.

Definition at line 543 of file stm32l1xx_usart.c.

References USART_TypeDef::DR, and IS_USART_ALL_PERIPH.

void USART_SendData | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Data
 | ) |  |

Transmits single data through the USARTx peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Data,: the data to transmit.
Return values:
None.

Definition at line 526 of file stm32l1xx_usart.c.

References USART_TypeDef::DR, IS_USART_ALL_PERIPH, and IS_USART_DATA.


STM32L1xx Standard Peripherals Firmware Library: MultiProcessor Communication functions

Functions

MultiProcessor Communication functions

USART_Private_Functions

Multi-Processor Communication functions. More...

Functions

void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

Multi-Processor Communication functions.

 ===============================================================================
             ##### Multi-Processor Communication functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART
         multiprocessor communication.
    [..] For instance one of the USARTs can be the master, its TX output is
         connected to the RX input of the other USART. The others are slaves,
         their respective TX outputs are logically ANDed together and connected
         to the RX input of the master. USART multiprocessor communication is
         possible through the following procedure:
         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
             Mode transmitter or Mode receiver and hardware flow control values
             using the USART_Init() function.
         (#) Configures the USART address using the USART_SetAddress() function.
         (#) Configures the wake up methode (USART_WakeUp_IdleLine or
             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
             for the slaves.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
             function.

    [..] The USART Slave exit from mute mode when receive the wake up condition.

Function Documentation

void USART_ReceiverWakeUpCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Determines if the USART is in mute mode or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 616 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_RWU.

void USART_SetAddress | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Address
 | ) |  |

Sets the address of the USART node.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Address,: Indicates the address of the USART node.
Return values:
None

Definition at line 595 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, IS_USART_ADDRESS, IS_USART_ALL_PERIPH, and USART_CR2_ADD.

void USART_WakeUpConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_WakeUp
 | ) |  |

Selects the USART WakeUp method.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_WakeUp,: specifies the USART wakeup method. This parameter can be one of the following values:

  • USART_WakeUp_IdleLine: WakeUp by an idle line detection.
  • USART_WakeUp_AddressMark: WakeUp by an address mark.
Return values:
None.

Definition at line 644 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, IS_USART_ALL_PERIPH, IS_USART_WAKEUP, and USART_CR1_WAKE.


STM32L1xx Standard Peripherals Firmware Library: LIN mode functions

Functions

LIN mode functions

USART_Private_Functions

LIN mode functions. More...

Functions

void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's LIN mode.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.

Detailed Description

LIN mode functions.

 ===============================================================================
                       ##### LIN mode functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART
         LIN Mode communication.
    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
         with the LIN standard.
    [..] Only this LIN Feature is supported by the USART IP:
         (+) LIN Master Synchronous Break send capability and LIN slave break
             detection capability :  13-bit break generation and 10/11 bit break
             detection.
    [..] USART LIN Master transmitter communication is possible through the
         following procedure:
         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
             Mode transmitter or Mode receiver and hardware flow control values
             using the USART_Init() function.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Enable the LIN mode using the USART_LINCmd() function.
         (#) Send the break character using USART_SendBreak() function.
    [..] USART LIN Master receiver communication is possible through the
         following procedure:
         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
             Mode transmitter or Mode receiver and hardware flow control values
            using the USART_Init() function.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Configures the break detection length
             using the USART_LINBreakDetectLengthConfig() function.
         (#) Enable the LIN mode using the USART_LINCmd() function.
         -@- In LIN mode, the following bits must be kept cleared:
             (+@) CLKEN in the USART_CR2 register.
             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.

Function Documentation

void USART_LINBreakDetectLengthConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_LINBreakDetectLength
 | ) |  |

Sets the USART LIN Break detection length.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_LINBreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:

  • USART_LINBreakDetectLength_10b: 10-bit break detection.
  • USART_LINBreakDetectLength_11b: 11-bit break detection.
Return values:
None.

Definition at line 709 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, IS_USART_ALL_PERIPH, IS_USART_LIN_BREAK_DETECT_LENGTH, and USART_CR2_LBDL.

void USART_LINCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's LIN mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 728 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR2_LINEN.

void USART_SendBreak ( USART_TypeDef * USARTx )

Transmits break characters.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None.

Definition at line 753 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, IS_USART_ALL_PERIPH, and USART_CR1_SBK.


STM32L1xx Standard Peripherals Firmware Library: Halfduplex mode function

Functions

Halfduplex mode function

USART_Private_Functions

Half-duplex mode function. More...

Functions

void USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Half Duplex communication.

Detailed Description

Half-duplex mode function.

 ===============================================================================
                   ##### Half-duplex mode function #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART
         Half-duplex communication.
    [..] The USART can be configured to follow a single-wire half-duplex protocol
         where the TX and RX lines are internally connected.
    [..] USART Half duplex communication is possible through the following procedure:
         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
             or Mode receiver and hardware flow control values using the USART_Init()
            function.
         (#) Configures the USART address using the USART_SetAddress() function.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
         -@- The RX pin is no longer used.
         -@- In Half-duplex mode the following bits must be kept cleared:
             (+@) LINEN and CLKEN bits in the USART_CR2 register.
             (+@) SCEN and IREN bits in the USART_CR3 register.

Function Documentation

void USART_HalfDuplexCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's Half Duplex communication.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 802 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_HDSEL.


STM32L1xx Standard Peripherals Firmware Library: Smartcard mode functions

Functions

Smartcard mode functions

USART_Private_Functions

Smartcard mode functions. More...

Functions

void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.

Detailed Description

Smartcard mode functions.

 ===============================================================================
                     ##### Smartcard mode functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART
         Smartcard communication.
    [..] The Smartcard interface is designed to support asynchronous protocol
         Smartcards as defined in the ISO 7816-3 standard. The USART can provide
         a clock to the smartcard through the SCLK output. In smartcard mode,
         SCLK is not associated to the communication but is simply derived from
         the internal peripheral input clock through a 5-bit prescaler.
    [..] Smartcard communication is possible through the following procedure:
         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
             function.
         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
             function.
         (#) Program the USART clock using the USART_ClockInit() function as following:
             (++) USART Clock enabled.
             (++) USART CPOL Low.
             (++) USART CPHA on first edge.
             (++) USART Last Bit Clock Enabled.
         (#) Program the Smartcard interface using the USART_Init() function as
             following:
             (++) Word Length = 9 Bits.
             (++) 1.5 Stop Bit.
             (++) Even parity.
             (++) BaudRate = 12096 baud.
             (++) Hardware flow control disabled (RTS and CTS signals).
             (++) Tx and Rx enabled
         (#) Optionally you can enable the parity error interrupt using
             the USART_ITConfig() function.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
    [..]
  Please refer to the ISO 7816-3 specification for more details.
    [..]
         (@) It is also possible to choose 0.5 stop bit for receiving but it is
             recommended to use 1.5 stop bits for both transmitting and receiving
             to avoid switching between the two configurations.
         (@) In smartcard mode, the following bits must be kept cleared:
             (+@) LINEN bit in the USART_CR2 register.
             (+@) HDSEL and IREN bits in the USART_CR3 register.

Function Documentation

void USART_SetGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_GuardTime
 | ) |  |

Sets the specified USART guard time.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
USART_GuardTime,: specifies the guard time.
Return values:
None.

Definition at line 884 of file stm32l1xx_usart.c.

References USART_TypeDef::GTPR, IS_USART_123_PERIPH, and USART_GTPR_PSC.

void USART_SmartCardCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's Smart Card mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 904 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, and USART_CR3_SCEN.

void USART_SmartCardNACKCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables NACK transmission.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
NewState,: new state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 930 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, and USART_CR3_NACK.


STM32L1xx Standard Peripherals Firmware Library: IrDA mode functions

Functions

IrDA mode functions

USART_Private_Functions

IrDA mode functions. More...

Functions

void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.

Detailed Description

IrDA mode functions.

 ===============================================================================
                        ##### IrDA mode functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART
         IrDA communication.
    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
         any data on the IrDA receive line will be ignored by the IrDA decoder
         and if the Receiver is busy, data on the TX from the USART to IrDA will
         not be encoded by IrDA. While receiving data, transmission should be
         avoided as the data to be transmitted could be corrupted.

    [..] IrDA communication is possible through the following procedure:
         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
             Transmitter/Receiver modes and hardware flow control values using
             the USART_Init() function.
         (#) Enable the USART using the USART_Cmd() function.
         (#) Configures the IrDA pulse width by configuring the prescaler using
             the USART_SetPrescaler() function.
         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal
             mode using the USART_IrDAConfig() function.
         (#) Enable the IrDA using the USART_IrDACmd() function.

    [..]
    (@) A pulse of width less than two and greater than one PSC period(s) may or
        may not be rejected.
    (@) The receiver set up time should be managed by software. The IrDA physical
        layer specification specifies a minimum of 10 ms delay between
        transmission and reception (IrDA is a half duplex protocol).
    (@) In IrDA mode, the following bits must be kept cleared:
        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
        (+@) SCEN and HDSEL bits in the USART_CR3 register.

Function Documentation

void USART_IrDACmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's IrDA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1021 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_IREN.

void USART_IrDAConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IrDAMode
 | ) |  |

Configures the USART's IrDA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IrDAMode,: specifies the IrDA mode. This parameter can be one of the following values:

  • USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.
  • USART_IrDAMode_Normal: USART IrDA Normal mode selected.
Return values:
None

Definition at line 1002 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, IS_USART_ALL_PERIPH, IS_USART_IRDA_MODE, and USART_CR3_IRLP.


STM32L1xx Standard Peripherals Firmware Library: DMA transfers management functions

Functions

DMA transfers management functions

USART_Private_Functions

DMA transfers management functions. More...

Functions

void USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART's DMA interface.

Detailed Description

DMA transfers management functions.

 ===============================================================================
               ##### DMA transfers management functions #####
 ===============================================================================

Function Documentation

void USART_DMACmd | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's DMA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_DMAReq,: specifies the DMA request. This parameter can be any combination of the following values:

  • USART_DMAReq_Tx: USART DMA transmit request.
  • USART_DMAReq_Rx: USART DMA receive request.
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1068 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and IS_USART_DMAREQ.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

USART_Private_Functions

Interrupts and flags management functions. More...

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.

Detailed Description

Interrupts and flags management functions.

 ===============================================================================
            ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to configure the
         USART Interrupts sources, DMA channels requests and check or clear the
         flags or pending bits status. The user should identify which mode will
         be used in his application to manage the communication: Polling mode,
         Interrupt mode or DMA mode.
 *** Polling Mode ***
 ====================
    [..] In Polling Mode, the SPI communication can be managed by 10 flags:
         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
         (#) USART_FLAG_NE: to indicate if a noise error occur.
         (#) USART_FLAG_FE: to indicate if a frame error occur.
         (#) USART_FLAG_PE: to indicate if a parity error occur.
         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
    [..] In this Mode it is advised to use the following functions:
         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).

 *** Interrupt Mode ***
 ======================
    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
         sources and 10 pending bits:
         (+) Pending Bits:
             (##) USART_IT_TXE: to indicate the status of the transmit buffer
                  register.
             (##) USART_IT_RXNE: to indicate the status of the receive buffer
                  register.
             (##) USART_IT_TC: to indicate the status of the transmit operation.
             (##) USART_IT_IDLE: to indicate the status of the Idle Line.
             (##) USART_IT_CTS: to indicate the status of the nCTS input.
             (##) USART_IT_LBD: to indicate the status of the LIN break detection.
             (##) USART_IT_NE: to indicate if a noise error occur.
             (##) USART_IT_FE: to indicate if a frame error occur.
             (##) USART_IT_PE: to indicate if a parity error occur.
             (##) USART_IT_ORE: to indicate if an Overrun error occur
                  (if the RXNEIE or EIE bits are set).

         (+) Interrupt Source:
             (##) USART_IT_TXE: specifies the interrupt source for the Tx buffer
                  empty interrupt.
             (##) USART_IT_RXNE: specifies the interrupt source for the Rx buffer
                  not empty interrupt.
             (##) USART_IT_TC: specifies the interrupt source for the Transmit
                  complete interrupt.
             (##) USART_IT_IDLE: specifies the interrupt source for the Idle Line
                  interrupt.
             (##) USART_IT_CTS: specifies the interrupt source for the CTS interrupt.
             (##) USART_IT_LBD: specifies the interrupt source for the LIN break
                  detection interrupt.
             (##) USART_IT_PE: specifies the interrupt source for theparity error
                  interrupt.
             (##) USART_IT_ERR:  specifies the interrupt source for the errors
                  interrupt.
             -@@- Some parameters are coded in order to use them as interrupt
                 source or as pending bits.
    [..] In this Mode it is advised to use the following functions:
         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT,
             FunctionalState NewState).
         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).

 *** DMA Mode ***
 ================
    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
         requests:
         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
    [..] In this Mode it is advised to use the following function:
         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
             FunctionalState NewState).

Function Documentation

void USART_ClearFlag | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Clears the USARTx's pending flags.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1312 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_FLAG, USART_TypeDef::SR, and USART_FLAG_CTS.

void USART_ClearITPendingBit | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Clears the USARTx's interrupt pending bits.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1422 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_IT, USART_TypeDef::SR, and USART_IT_CTS.

FlagStatus USART_GetFlagStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Checks whether the specified USART flag is set or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TXE: Transmit data register empty flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
  • USART_FLAG_IDLE: Idle Line detection flag.
  • USART_FLAG_ORE: OverRun Error flag.
  • USART_FLAG_NE: Noise Error flag.
  • USART_FLAG_FE: Framing Error flag.
  • USART_FLAG_PE: Parity Error flag.
Return values:
The new state of USART_FLAG (SET or RESET).

Definition at line 1262 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_FLAG, RESET, SET, USART_TypeDef::SR, and USART_FLAG_CTS.

ITStatus USART_GetITStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Checks whether the specified USART interrupt has occurred or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt source to check. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Tansmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.
  • USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set.
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of USART_IT (SET or RESET).

Definition at line 1347 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, USART_TypeDef::CR2, USART_TypeDef::CR3, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_GET_IT, IT_MASK, RESET, SET, USART_TypeDef::SR, and USART_IT_CTS.

void USART_ITConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt.
  • USART_IT_LBD: LIN Break detection interrupt.
  • USART_IT_TXE: Tansmit Data Register empty interrupt.
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
  • USART_IT_IDLE: Idle line detection interrupt.
  • USART_IT_PE: Parity Error interrupt.
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error).
NewState,: new state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 1197 of file stm32l1xx_usart.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CONFIG_IT, IT_MASK, and USART_IT_CTS.


STM32L1xx Standard Peripherals Firmware Library: USART

Data Structures | Modules | Defines | Functions

USART

STM32L1xx_StdPeriph_Driver

USART driver modules. More...

Data Structures

struct | USART_ClockInitTypeDef
USART Clock Init Structure definition. More...
struct | USART_InitTypeDef
USART Init Structure definition. More...

Modules

USART_Exported_Constants
USART_Private_Functions

Defines

#define | CR1_CLEAR_MASK
#define | CR2_CLOCK_CLEAR_MASK
#define | CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | IT_MASK ((uint16_t)0x001F)

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART's DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

USART driver modules.

Define Documentation

#define CR1_CLEAR_MASK
Value:
((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
                                              USART_CR1_PS | USART_CR1_TE | \
                                              USART_CR1_RE))

< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF))

Definition at line 92 of file stm32l1xx_usart.c.

Referenced by USART_Init().

#define CR2_CLOCK_CLEAR_MASK
Value:
((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
                                              USART_CR2_CPHA | USART_CR2_LBCL))

USART CR3 register clear Mask ((~(uint16_t)0xFCFF))

Definition at line 97 of file stm32l1xx_usart.c.

Referenced by USART_ClockInit().

#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))

USART Interrupts mask

Definition at line 101 of file stm32l1xx_usart.c.

Referenced by USART_Init().

#define IT_MASK ((uint16_t)0x001F)

Definition at line 104 of file stm32l1xx_usart.c.

Referenced by USART_GetITStatus(), and USART_ITConfig().

Function Documentation

void USART_ClearFlag | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Clears the USARTx's pending flags.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1312 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_FLAG, USART_TypeDef::SR, and USART_FLAG_CTS.

void USART_ClearITPendingBit | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Clears the USARTx's interrupt pending bits.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1422 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_IT, USART_TypeDef::SR, and USART_IT_CTS.

void USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.

Parameters:
USARTx,: where x can be 1, 2, 3 to select the USART peripheral.
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
Note:
The Smart Card and Synchronous modes are not available for UART4 and UART5.
Return values:
None.

Definition at line 345 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, CR2_CLOCK_CLEAR_MASK, IS_USART_123_PERIPH, IS_USART_CLOCK, IS_USART_CPHA, IS_USART_CPOL, IS_USART_LASTBIT, USART_ClockInitTypeDef::USART_Clock, USART_ClockInitTypeDef::USART_CPHA, USART_ClockInitTypeDef::USART_CPOL, and USART_ClockInitTypeDef::USART_LastBit.

void USART_ClockStructInit ( USART_ClockInitTypeDef * USART_ClockInitStruct )

Fills each USART_ClockInitStruct member with its default value.

Parameters:
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 376 of file stm32l1xx_usart.c.

References USART_ClockInitTypeDef::USART_Clock, USART_Clock_Disable, USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_1Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_Low, USART_ClockInitTypeDef::USART_LastBit, and USART_LastBit_Disable.

void USART_Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 394 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_UE.

void USART_DeInit ( USART_TypeDef * USARTx )

Deinitializes the USARTx peripheral registers to their default reset values.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None.

Definition at line 170 of file stm32l1xx_usart.c.

References DISABLE, ENABLE, IS_USART_ALL_PERIPH, RCC_APB1Periph_UART4, RCC_APB1Periph_UART5, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_USART1, RCC_APB2PeriphResetCmd(), UART4, UART5, USART1, USART2, and USART3.

void USART_DMACmd | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's DMA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_DMAReq,: specifies the DMA request. This parameter can be any combination of the following values:

  • USART_DMAReq_Tx: USART DMA transmit request.
  • USART_DMAReq_Rx: USART DMA receive request.
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1068 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and IS_USART_DMAREQ.

FlagStatus USART_GetFlagStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Checks whether the specified USART flag is set or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TXE: Transmit data register empty flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
  • USART_FLAG_IDLE: Idle Line detection flag.
  • USART_FLAG_ORE: OverRun Error flag.
  • USART_FLAG_NE: Noise Error flag.
  • USART_FLAG_FE: Framing Error flag.
  • USART_FLAG_PE: Parity Error flag.
Return values:
The new state of USART_FLAG (SET or RESET).

Definition at line 1262 of file stm32l1xx_usart.c.

References IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_FLAG, RESET, SET, USART_TypeDef::SR, and USART_FLAG_CTS.

ITStatus USART_GetITStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Checks whether the specified USART interrupt has occurred or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt source to check. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Tansmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.
  • USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set.
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of USART_IT (SET or RESET).

Definition at line 1347 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, USART_TypeDef::CR2, USART_TypeDef::CR3, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_GET_IT, IT_MASK, RESET, SET, USART_TypeDef::SR, and USART_IT_CTS.

void USART_HalfDuplexCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's Half Duplex communication.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 802 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_HDSEL.

void USART_Init | ( | USART_TypeDef * | USARTx,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None.

Definition at line 215 of file stm32l1xx_usart.c.

References USART_TypeDef::BRR, USART_TypeDef::CR1, CR1_CLEAR_MASK, USART_TypeDef::CR2, USART_TypeDef::CR3, CR3_CLEAR_MASK, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_BAUDRATE, IS_USART_HARDWARE_FLOW_CONTROL, IS_USART_MODE, IS_USART_PARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetClocksFreq(), USART1, USART_InitTypeDef::USART_BaudRate, USART_CR1_OVER8, USART_CR2_STOP, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_InitTypeDef::USART_Parity, USART_InitTypeDef::USART_StopBits, and USART_InitTypeDef::USART_WordLength.

void USART_IrDACmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's IrDA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1021 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_IREN.

void USART_IrDAConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IrDAMode
 | ) |  |

Configures the USART's IrDA interface.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IrDAMode,: specifies the IrDA mode. This parameter can be one of the following values:

  • USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.
  • USART_IrDAMode_Normal: USART IrDA Normal mode selected.
Return values:
None

Definition at line 1002 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, IS_USART_ALL_PERIPH, IS_USART_IRDA_MODE, and USART_CR3_IRLP.

void USART_ITConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt.
  • USART_IT_LBD: LIN Break detection interrupt.
  • USART_IT_TXE: Tansmit Data Register empty interrupt.
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
  • USART_IT_IDLE: Idle line detection interrupt.
  • USART_IT_PE: Parity Error interrupt.
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error).
NewState,: new state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 1197 of file stm32l1xx_usart.c.

References DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CONFIG_IT, IT_MASK, and USART_IT_CTS.

void USART_LINBreakDetectLengthConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_LINBreakDetectLength
 | ) |  |

Sets the USART LIN Break detection length.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_LINBreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:

  • USART_LINBreakDetectLength_10b: 10-bit break detection.
  • USART_LINBreakDetectLength_11b: 11-bit break detection.
Return values:
None.

Definition at line 709 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, IS_USART_ALL_PERIPH, IS_USART_LIN_BREAK_DETECT_LENGTH, and USART_CR2_LBDL.

void USART_LINCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's LIN mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 728 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR2_LINEN.

void USART_OneBitMethodCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's one bit sampling method.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 472 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR3_ONEBIT.

void USART_OverSampling8Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's 8x oversampling mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART 8x oversampling mode. This parameter can be: ENABLE or DISABLE.
Note:
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
Return values:
None

Definition at line 445 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_OVER8.

uint16_t USART_ReceiveData ( USART_TypeDef * USARTx )

Returns the most recent received data by the USARTx peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
The received data.

Definition at line 543 of file stm32l1xx_usart.c.

References USART_TypeDef::DR, and IS_USART_ALL_PERIPH.

void USART_ReceiverWakeUpCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Determines if the USART is in mute mode or not.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 616 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and USART_CR1_RWU.

void USART_SendBreak ( USART_TypeDef * USARTx )

Transmits break characters.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None.

Definition at line 753 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, IS_USART_ALL_PERIPH, and USART_CR1_SBK.

void USART_SendData | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Data
 | ) |  |

Transmits single data through the USARTx peripheral.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Data,: the data to transmit.
Return values:
None.

Definition at line 526 of file stm32l1xx_usart.c.

References USART_TypeDef::DR, IS_USART_ALL_PERIPH, and IS_USART_DATA.

void USART_SetAddress | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Address
 | ) |  |

Sets the address of the USART node.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Address,: Indicates the address of the USART node.
Return values:
None

Definition at line 595 of file stm32l1xx_usart.c.

References USART_TypeDef::CR2, IS_USART_ADDRESS, IS_USART_ALL_PERIPH, and USART_CR2_ADD.

void USART_SetGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_GuardTime
 | ) |  |

Sets the specified USART guard time.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
USART_GuardTime,: specifies the guard time.
Return values:
None.

Definition at line 884 of file stm32l1xx_usart.c.

References USART_TypeDef::GTPR, IS_USART_123_PERIPH, and USART_GTPR_PSC.

void USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Prescaler
 | ) |  |

Sets the system clock prescaler.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Prescaler,: specifies the prescaler clock.
Note:
The function is used for IrDA mode with UART4 and UART5.
Return values:
None.

Definition at line 421 of file stm32l1xx_usart.c.

References USART_TypeDef::GTPR, IS_USART_ALL_PERIPH, and USART_GTPR_GT.

void USART_SmartCardCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's Smart Card mode.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 904 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, and USART_CR3_SCEN.

void USART_SmartCardNACKCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables NACK transmission.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2 or USART3.
NewState,: new state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 930 of file stm32l1xx_usart.c.

References USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, and USART_CR3_NACK.

void USART_StructInit ( USART_InitTypeDef * USART_InitStruct )

Fills each USART_InitStruct member with its default value.

Parameters:
USART_InitStruct,: pointer to a USART_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 324 of file stm32l1xx_usart.c.

References USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void USART_WakeUpConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_WakeUp
 | ) |  |

Selects the USART WakeUp method.

Parameters:
USARTx,: Select the USART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_WakeUp,: specifies the USART wakeup method. This parameter can be one of the following values:

  • USART_WakeUp_IdleLine: WakeUp by an idle line detection.
  • USART_WakeUp_AddressMark: WakeUp by an address mark.
Return values:
None.

Definition at line 644 of file stm32l1xx_usart.c.

References USART_TypeDef::CR1, IS_USART_ALL_PERIPH, IS_USART_WAKEUP, and USART_CR1_WAKE.


STM32L1xx Standard Peripherals Firmware Library: USART_ClockInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_ClockInitTypeDef Struct Reference
USART

USART Clock Init Structure definition. More...

#include <stm32l1xx_usart.h>

Data Fields

uint16_t | USART_Clock
uint16_t | USART_CPHA
uint16_t | USART_CPOL
uint16_t | USART_LastBit

Detailed Description

USART Clock Init Structure definition.

Definition at line 84 of file stm32l1xx_usart.h.

Field Documentation

uint16_t USART_ClockInitTypeDef::USART_Clock

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of USART_Clock

Definition at line 87 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_CPHA

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART_Clock_Phase

Definition at line 93 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_CPOL

Specifies the steady state of the serial clock. This parameter can be a value of USART_Clock_Polarity

Definition at line 90 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_LastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART_Last_Bit

Definition at line 96 of file stm32l1xx_usart.h.

Referenced by USART_ClockInit(), and USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_usart.h


STM32L1xx Standard Peripherals Firmware Library: USART_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_InitTypeDef Struct Reference
USART

USART Init Structure definition. More...

#include <stm32l1xx_usart.h>

Data Fields

uint32_t | USART_BaudRate
uint16_t | USART_HardwareFlowControl
uint16_t | USART_Mode
uint16_t | USART_Parity
uint16_t | USART_StopBits
uint16_t | USART_WordLength

Detailed Description

USART Init Structure definition.

Definition at line 51 of file stm32l1xx_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::USART_BaudRate

This member configures the USART communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register.

Definition at line 53 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_HardwareFlowControl

Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of USART_Hardware_Flow_Control

Definition at line 75 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_Mode

Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART_Mode

Definition at line 72 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_Parity

Specifies the parity mode. This parameter can be a value of USART_Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 65 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART_Stop_Bits

Definition at line 62 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USART_Word_Length

Definition at line 59 of file stm32l1xx_usart.h.

Referenced by USART_Init(), and USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l1xx_usart.h


STM32L1xx Standard Peripherals Firmware Library: WWDG_Prescaler

Defines

WWDG_Prescaler

WWDG_Exported_Constants

Defines

#define | IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
#define | IS_WWDG_PRESCALER(PRESCALER)
#define | IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define | WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define | WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define | WWDG_Prescaler_8 ((uint32_t)0x00000180)

Define Documentation

#define IS_WWDG_COUNTER ( COUNTER ) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))

Definition at line 65 of file stm32l1xx_wwdg.h.

Referenced by WWDG_Enable(), and WWDG_SetCounter().

#define IS_WWDG_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == WWDG_Prescaler_1) || \
                                      ((PRESCALER) == WWDG_Prescaler_2) || \
                                      ((PRESCALER) == WWDG_Prescaler_4) || \
                                      ((PRESCALER) == WWDG_Prescaler_8))

Definition at line 60 of file stm32l1xx_wwdg.h.

Referenced by WWDG_SetPrescaler().

#define IS_WWDG_WINDOW_VALUE ( VALUE ) ((VALUE) <= 0x7F)

Definition at line 64 of file stm32l1xx_wwdg.h.

Referenced by WWDG_SetWindowValue().

#define WWDG_Prescaler_1 ((uint32_t)0x00000000)

Definition at line 56 of file stm32l1xx_wwdg.h.

#define WWDG_Prescaler_2 ((uint32_t)0x00000080)

Definition at line 57 of file stm32l1xx_wwdg.h.

#define WWDG_Prescaler_4 ((uint32_t)0x00000100)

Definition at line 58 of file stm32l1xx_wwdg.h.

#define WWDG_Prescaler_8 ((uint32_t)0x00000180)

Definition at line 59 of file stm32l1xx_wwdg.h.


STM32L1xx Standard Peripherals Firmware Library: Prescaler, Refresh window and Counter configuration functions

Functions

Prescaler, Refresh window and Counter configuration functions

WWDG_Private_Functions

Prescaler, Refresh window and Counter configuration functions. More...

Functions

void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

Prescaler, Refresh window and Counter configuration functions.

  ==============================================================================
    ##### Prescaler, Refresh window and Counter configuration functions #####
  ==============================================================================

Function Documentation

void WWDG_DeInit ( void )

Deinitializes the WWDG peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 139 of file stm32l1xx_wwdg.c.

References DISABLE, ENABLE, RCC_APB1Periph_WWDG, and RCC_APB1PeriphResetCmd().

void WWDG_EnableIT ( void )

Enables the WWDG Early Wakeup interrupt(EWI).

Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Parameters:
None
Return values:
None

Definition at line 197 of file stm32l1xx_wwdg.c.

References CFR_EWI_BB, and ENABLE.

void WWDG_SetCounter ( uint8_t Counter )

Sets the WWDG counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset).
Return values:
None

Definition at line 209 of file stm32l1xx_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTER, and WWDG.

void WWDG_SetPrescaler ( uint32_t WWDG_Prescaler )

Sets the WWDG Prescaler.

Parameters:
WWDG_Prescaler,: specifies the WWDG Prescaler. This parameter can be one of the following values:

  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
Return values:
None

Definition at line 155 of file stm32l1xx_wwdg.c.

References CFR_WDGTB_MASK, IS_WWDG_PRESCALER, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 174 of file stm32l1xx_wwdg.c.

References BIT_MASK, CFR_W_MASK, IS_WWDG_WINDOW_VALUE, and WWDG.


STM32L1xx Standard Peripherals Firmware Library: WWDG activation functions

Functions

WWDG activation functions

WWDG_Private_Functions

WWDG activation functions. More...

Functions

void WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.

Detailed Description

WWDG activation functions.

  ==============================================================================
                     ##### WWDG activation function #####
  ==============================================================================

Function Documentation

void WWDG_Enable ( uint8_t Counter )

Enables WWDG and load the counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset).
Return values:
None

Definition at line 241 of file stm32l1xx_wwdg.c.

References IS_WWDG_COUNTER, WWDG, and WWDG_CR_WDGA.


STM32L1xx Standard Peripherals Firmware Library: Interrupts and flags management functions

Functions

Interrupts and flags management functions

WWDG_Private_Functions

Interrupts and flags management functions. More...

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.

Detailed Description

Interrupts and flags management functions.

  ==============================================================================
                ##### Interrupts and flags management functions #####
  ==============================================================================

Function Documentation

void WWDG_ClearFlag ( void )

Clears Early Wakeup interrupt flag.

Parameters:
None
Return values:
None

Definition at line 289 of file stm32l1xx_wwdg.c.

References RESET, and WWDG.

FlagStatus WWDG_GetFlagStatus ( void )

Checks whether the Early Wakeup interrupt flag is set or not.

Parameters:
None
Return values:
The new state of the Early Wakeup interrupt flag (SET or RESET).

Definition at line 269 of file stm32l1xx_wwdg.c.

References RESET, SET, and WWDG.


STM32L1xx Standard Peripherals Firmware Library: WWDG

Modules | Defines | Functions

WWDG

STM32L1xx_StdPeriph_Driver

WWDG driver modules. More...

Modules

WWDG_Exported_Constants
WWDG_Private_Functions

Defines

#define | BIT_MASK ((uint8_t)0x7F)
#define | CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
#define | CFR_OFFSET (WWDG_OFFSET + 0x04)
#define | CFR_W_MASK ((uint32_t)0xFFFFFF80)
#define | CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
#define | EWI_BitNumber 0x09
#define | WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

WWDG driver modules.

Define Documentation

#define BIT_MASK ((uint8_t)0x7F)

Definition at line 111 of file stm32l1xx_wwdg.c.

Referenced by WWDG_SetCounter(), and WWDG_SetWindowValue().

#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))

Definition at line 104 of file stm32l1xx_wwdg.c.

Referenced by WWDG_EnableIT().

#define CFR_OFFSET (WWDG_OFFSET + 0x04)

Definition at line 102 of file stm32l1xx_wwdg.c.

#define CFR_W_MASK ((uint32_t)0xFFFFFF80)

Definition at line 110 of file stm32l1xx_wwdg.c.

Referenced by WWDG_SetWindowValue().

#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)

Definition at line 109 of file stm32l1xx_wwdg.c.

Referenced by WWDG_SetPrescaler().

#define EWI_BitNumber 0x09

Definition at line 103 of file stm32l1xx_wwdg.c.

#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Definition at line 99 of file stm32l1xx_wwdg.c.

Function Documentation

void WWDG_ClearFlag ( void )

Clears Early Wakeup interrupt flag.

Parameters:
None
Return values:
None

Definition at line 289 of file stm32l1xx_wwdg.c.

References RESET, and WWDG.

void WWDG_DeInit ( void )

Deinitializes the WWDG peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 139 of file stm32l1xx_wwdg.c.

References DISABLE, ENABLE, RCC_APB1Periph_WWDG, and RCC_APB1PeriphResetCmd().

void WWDG_Enable ( uint8_t Counter )

Enables WWDG and load the counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset).
Return values:
None

Definition at line 241 of file stm32l1xx_wwdg.c.

References IS_WWDG_COUNTER, WWDG, and WWDG_CR_WDGA.

void WWDG_EnableIT ( void )

Enables the WWDG Early Wakeup interrupt(EWI).

Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Parameters:
None
Return values:
None

Definition at line 197 of file stm32l1xx_wwdg.c.

References CFR_EWI_BB, and ENABLE.

FlagStatus WWDG_GetFlagStatus ( void )

Checks whether the Early Wakeup interrupt flag is set or not.

Parameters:
None
Return values:
The new state of the Early Wakeup interrupt flag (SET or RESET).

Definition at line 269 of file stm32l1xx_wwdg.c.

References RESET, SET, and WWDG.

void WWDG_SetCounter ( uint8_t Counter )

Sets the WWDG counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset).
Return values:
None

Definition at line 209 of file stm32l1xx_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTER, and WWDG.

void WWDG_SetPrescaler ( uint32_t WWDG_Prescaler )

Sets the WWDG Prescaler.

Parameters:
WWDG_Prescaler,: specifies the WWDG Prescaler. This parameter can be one of the following values:

  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
Return values:
None

Definition at line 155 of file stm32l1xx_wwdg.c.

References CFR_WDGTB_MASK, IS_WWDG_PRESCALER, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 174 of file stm32l1xx_wwdg.c.

References BIT_MASK, CFR_W_MASK, IS_WWDG_WINDOW_VALUE, and WWDG.


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • ACR : FLASH_TypeDef
  • ADC_ContinuousConvMode : ADC_InitTypeDef
  • ADC_DataAlign : ADC_InitTypeDef
  • ADC_ExternalTrigConv : ADC_InitTypeDef
  • ADC_ExternalTrigConvEdge : ADC_InitTypeDef
  • ADC_NbrOfConversion : ADC_InitTypeDef
  • ADC_Prescaler : ADC_CommonInitTypeDef
  • ADC_Resolution : ADC_InitTypeDef
  • ADC_ScanConvMode : ADC_InitTypeDef
  • AES_Chaining : AES_InitTypeDef
  • AES_DataType : AES_InitTypeDef
  • AES_IV0 : AES_IVInitTypeDef
  • AES_IV1 : AES_IVInitTypeDef
  • AES_IV2 : AES_IVInitTypeDef
  • AES_IV3 : AES_IVInitTypeDef
  • AES_Key0 : AES_KeyInitTypeDef
  • AES_Key1 : AES_KeyInitTypeDef
  • AES_Key2 : AES_KeyInitTypeDef
  • AES_Key3 : AES_KeyInitTypeDef
  • AES_Operation : AES_InitTypeDef
  • AFR : GPIO_TypeDef
  • AHBENR : RCC_TypeDef
  • AHBLPENR : RCC_TypeDef
  • AHBRSTR : RCC_TypeDef
  • ALRMAR : RTC_TypeDef
  • ALRMASSR : RTC_TypeDef
  • ALRMBR : RTC_TypeDef
  • ALRMBSSR : RTC_TypeDef
  • APB1ENR : RCC_TypeDef
  • APB1FZ : DBGMCU_TypeDef
  • APB1LPENR : RCC_TypeDef
  • APB1RSTR : RCC_TypeDef
  • APB2ENR : RCC_TypeDef
  • APB2FZ : DBGMCU_TypeDef
  • APB2LPENR : RCC_TypeDef
  • APB2RSTR : RCC_TypeDef
  • ARG : SDIO_TypeDef
  • ARR : TIM_TypeDef
  • ASCR1 : RI_TypeDef
  • ASCR2 : RI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: misc.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

misc.c File Reference

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions). More...

#include "misc.h"

Go to the source code of this file.

Defines

#define | AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: preemption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Detailed Description

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file misc.c.


STM32L1xx Standard Peripherals Firmware Library: misc.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

misc.h File Reference

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions). More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | NVIC_InitTypeDef
NVIC Init Structure definition. More...

Defines

#define | IS_NVIC_LP(LP)
#define | IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_VECTTAB(VECTTAB)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define | NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define | NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define | NVIC_PriorityGroup_0 ((uint32_t)0x700)
#define | NVIC_PriorityGroup_1 ((uint32_t)0x600)
#define | NVIC_PriorityGroup_2 ((uint32_t)0x500)
#define | NVIC_PriorityGroup_3 ((uint32_t)0x400)
#define | NVIC_PriorityGroup_4 ((uint32_t)0x300)
#define | NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define | NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define | SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define | SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: preemption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Detailed Description

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file misc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • Include
Data Structures | Defines | Typedefs | Enumerations

stm32l1xx.h File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32L1xx High-, Medium-density and Medium-density Plus devices. More...

#include "core_cm3.h"
#include "system_stm32l1xx.h"
#include <stdint.h>

Go to the source code of this file.

Data Structures

struct | ADC_Common_TypeDef
struct | ADC_TypeDef
Analog to Digital Converter. More...
struct | AES_TypeDef
AES hardware accelerator. More...
struct | COMP_TypeDef
Comparator. More...
struct | CRC_TypeDef
CRC calculation unit. More...
struct | DAC_TypeDef
Digital to Analog Converter. More...
struct | DBGMCU_TypeDef
Debug MCU. More...
struct | DMA_Channel_TypeDef
DMA Controller. More...
struct | DMA_TypeDef
struct | EXTI_TypeDef
External Interrupt/Event Controller. More...
struct | FLASH_TypeDef
FLASH Registers. More...
struct | FSMC_Bank1_TypeDef
Flexible Static Memory Controller. More...
struct | FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E. More...
struct | GPIO_TypeDef
General Purpose IO. More...
struct | I2C_TypeDef
Inter-integrated Circuit Interface. More...
struct | IWDG_TypeDef
Independent WATCHDOG. More...
struct | LCD_TypeDef
LCD. More...
struct | OB_TypeDef
Option Bytes Registers. More...
struct | OPAMP_TypeDef
Operational Amplifier (OPAMP) More...
struct | PWR_TypeDef
Power Control. More...
struct | RCC_TypeDef
Reset and Clock Control. More...
struct | RI_TypeDef
Routing Interface. More...
struct | RTC_TypeDef
Real-Time Clock. More...
struct | SDIO_TypeDef
SD host Interface. More...
struct | SPI_TypeDef
Serial Peripheral Interface. More...
struct | SYSCFG_TypeDef
SysTem Configuration. More...
struct | TIM_TypeDef
TIM. More...
struct | USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter. More...
struct | WWDG_TypeDef
Window WATCHDOG. More...

Defines

#define | __CM3_REV 0x200
STM32L1xx Interrupt Number Definition, according to the selected device in Library_configuration_section.
#define | __MPU_PRESENT 1
#define | __NVIC_PRIO_BITS 4
#define | __STM32L1XX_STDPERIPH_VERSION
#define | __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01)
STM32L1xx Standard Peripheral Library version number V1.1.0.
#define | __STM32L1XX_STDPERIPH_VERSION_RC (0x00)
#define | __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01)
#define | __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00)
#define | __Vendor_SysTickConfig 0
#define | ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define | ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define | ADC_BASE (APB2PERIPH_BASE + 0x2700)
#define | ADC_CCR_ADCPRE ((uint32_t)0x00030000)
#define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)
#define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)
#define | ADC_CCR_TSVREFE ((uint32_t)0x00800000)
#define | ADC_CR1_AWDCH ((uint32_t)0x0000001F)
#define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
#define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
#define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
#define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
#define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
#define | ADC_CR1_AWDEN ((uint32_t)0x00800000)
#define | ADC_CR1_AWDIE ((uint32_t)0x00000040)
#define | ADC_CR1_AWDSGL ((uint32_t)0x00000200)
#define | ADC_CR1_DISCEN ((uint32_t)0x00000800)
#define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
#define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
#define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
#define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
#define | ADC_CR1_EOCIE ((uint32_t)0x00000020)
#define | ADC_CR1_JAUTO ((uint32_t)0x00000400)
#define | ADC_CR1_JAWDEN ((uint32_t)0x00400000)
#define | ADC_CR1_JDISCEN ((uint32_t)0x00001000)
#define | ADC_CR1_JEOCIE ((uint32_t)0x00000080)
#define | ADC_CR1_OVRIE ((uint32_t)0x04000000)
#define | ADC_CR1_PDD ((uint32_t)0x00010000)
#define | ADC_CR1_PDI ((uint32_t)0x00020000)
#define | ADC_CR1_RES ((uint32_t)0x03000000)
#define | ADC_CR1_RES_0 ((uint32_t)0x01000000)
#define | ADC_CR1_RES_1 ((uint32_t)0x02000000)
#define | ADC_CR1_SCAN ((uint32_t)0x00000100)
#define | ADC_CR2_ADON ((uint32_t)0x00000001)
#define | ADC_CR2_ALIGN ((uint32_t)0x00000800)
#define | ADC_CR2_CFG ((uint32_t)0x00000004)
#define | ADC_CR2_CONT ((uint32_t)0x00000002)
#define | ADC_CR2_DDS ((uint32_t)0x00000200)
#define | ADC_CR2_DELS ((uint32_t)0x00000070)
#define | ADC_CR2_DELS_0 ((uint32_t)0x00000010)
#define | ADC_CR2_DELS_1 ((uint32_t)0x00000020)
#define | ADC_CR2_DELS_2 ((uint32_t)0x00000040)
#define | ADC_CR2_DMA ((uint32_t)0x00000100)
#define | ADC_CR2_EOCS ((uint32_t)0x00000400)
#define | ADC_CR2_EXTEN ((uint32_t)0x30000000)
#define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)
#define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)
#define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000)
#define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)
#define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)
#define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)
#define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)
#define | ADC_CR2_JEXTEN ((uint32_t)0x00300000)
#define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)
#define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)
#define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)
#define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)
#define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)
#define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)
#define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)
#define | ADC_CR2_JSWSTART ((uint32_t)0x00400000)
#define | ADC_CR2_SWSTART ((uint32_t)0x40000000)
#define | ADC_CSR_ADONS1 ((uint32_t)0x00000040)
#define | ADC_CSR_AWD1 ((uint32_t)0x00000001)
#define | ADC_CSR_EOC1 ((uint32_t)0x00000002)
#define | ADC_CSR_JEOC1 ((uint32_t)0x00000004)
#define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008)
#define | ADC_CSR_OVR1 ((uint32_t)0x00000020)
#define | ADC_CSR_STRT1 ((uint32_t)0x00000010)
#define | ADC_DR_DATA ((uint32_t)0x0000FFFF)
#define | ADC_HTR_HT ((uint32_t)0x00000FFF)
#define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF)
#define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF)
#define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF)
#define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF)
#define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF)
#define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF)
#define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF)
#define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF)
#define | ADC_JSQR_JL ((uint32_t)0x00300000)
#define | ADC_JSQR_JL_0 ((uint32_t)0x00100000)
#define | ADC_JSQR_JL_1 ((uint32_t)0x00200000)
#define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
#define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
#define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
#define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
#define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
#define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
#define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
#define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
#define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
#define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
#define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
#define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
#define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
#define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
#define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
#define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
#define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
#define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
#define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
#define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
#define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
#define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
#define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
#define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
#define | ADC_LTR_LT ((uint32_t)0x00000FFF)
#define | ADC_SMPR1_SMP20 ((uint32_t)0x00000007)
#define | ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001)
#define | ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002)
#define | ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004)
#define | ADC_SMPR1_SMP21 ((uint32_t)0x00000038)
#define | ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008)
#define | ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010)
#define | ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020)
#define | ADC_SMPR1_SMP22 ((uint32_t)0x000001C0)
#define | ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040)
#define | ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080)
#define | ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100)
#define | ADC_SMPR1_SMP23 ((uint32_t)0x00000E00)
#define | ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200)
#define | ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400)
#define | ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800)
#define | ADC_SMPR1_SMP24 ((uint32_t)0x00007000)
#define | ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000)
#define | ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000)
#define | ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000)
#define | ADC_SMPR1_SMP25 ((uint32_t)0x00038000)
#define | ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000)
#define | ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000)
#define | ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000)
#define | ADC_SMPR1_SMP26 ((uint32_t)0x001C0000)
#define | ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000)
#define | ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000)
#define | ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000)
#define | ADC_SMPR1_SMP27 ((uint32_t)0x00E00000)
#define | ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000)
#define | ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000)
#define | ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000)
#define | ADC_SMPR1_SMP28 ((uint32_t)0x07000000)
#define | ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000)
#define | ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000)
#define | ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000)
#define | ADC_SMPR1_SMP29 ((uint32_t)0x38000000)
#define | ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000)
#define | ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000)
#define | ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000)
#define | ADC_SMPR2_SMP10 ((uint32_t)0x00000007)
#define | ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001)
#define | ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002)
#define | ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004)
#define | ADC_SMPR2_SMP11 ((uint32_t)0x00000038)
#define | ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008)
#define | ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010)
#define | ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020)
#define | ADC_SMPR2_SMP12 ((uint32_t)0x000001C0)
#define | ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040)
#define | ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080)
#define | ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100)
#define | ADC_SMPR2_SMP13 ((uint32_t)0x00000E00)
#define | ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200)
#define | ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400)
#define | ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800)
#define | ADC_SMPR2_SMP14 ((uint32_t)0x00007000)
#define | ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000)
#define | ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000)
#define | ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000)
#define | ADC_SMPR2_SMP15 ((uint32_t)0x00038000)
#define | ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000)
#define | ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000)
#define | ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000)
#define | ADC_SMPR2_SMP16 ((uint32_t)0x001C0000)
#define | ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000)
#define | ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000)
#define | ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000)
#define | ADC_SMPR2_SMP17 ((uint32_t)0x00E00000)
#define | ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000)
#define | ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000)
#define | ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000)
#define | ADC_SMPR2_SMP18 ((uint32_t)0x07000000)
#define | ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000)
#define | ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000)
#define | ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000)
#define | ADC_SMPR2_SMP19 ((uint32_t)0x38000000)
#define | ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000)
#define | ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000)
#define | ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000)
#define | ADC_SMPR3_SMP0 ((uint32_t)0x00000007)
#define | ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001)
#define | ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002)
#define | ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004)
#define | ADC_SMPR3_SMP1 ((uint32_t)0x00000038)
#define | ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008)
#define | ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010)
#define | ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020)
#define | ADC_SMPR3_SMP2 ((uint32_t)0x000001C0)
#define | ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040)
#define | ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080)
#define | ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100)
#define | ADC_SMPR3_SMP3 ((uint32_t)0x00000E00)
#define | ADC_SMPR3_SMP30 ((uint32_t)0x00000007)
#define | ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001)
#define | ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002)
#define | ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004)
#define | ADC_SMPR3_SMP31 ((uint32_t)0x00000038)
#define | ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008)
#define | ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010)
#define | ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020)
#define | ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200)
#define | ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400)
#define | ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800)
#define | ADC_SMPR3_SMP4 ((uint32_t)0x00007000)
#define | ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000)
#define | ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000)
#define | ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000)
#define | ADC_SMPR3_SMP5 ((uint32_t)0x00038000)
#define | ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000)
#define | ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000)
#define | ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000)
#define | ADC_SMPR3_SMP6 ((uint32_t)0x001C0000)
#define | ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000)
#define | ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000)
#define | ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000)
#define | ADC_SMPR3_SMP7 ((uint32_t)0x00E00000)
#define | ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000)
#define | ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000)
#define | ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000)
#define | ADC_SMPR3_SMP8 ((uint32_t)0x07000000)
#define | ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000)
#define | ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000)
#define | ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000)
#define | ADC_SMPR3_SMP9 ((uint32_t)0x38000000)
#define | ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000)
#define | ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000)
#define | ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000)
#define | ADC_SQR1_L ((uint32_t)0x00F00000)
#define | ADC_SQR1_L_0 ((uint32_t)0x00100000)
#define | ADC_SQR1_L_1 ((uint32_t)0x00200000)
#define | ADC_SQR1_L_2 ((uint32_t)0x00400000)
#define | ADC_SQR1_L_3 ((uint32_t)0x00800000)
#define | ADC_SQR1_SQ25 ((uint32_t)0x0000001F)
#define | ADC_SQR1_SQ25_0 ((uint32_t)0x00000001)
#define | ADC_SQR1_SQ25_1 ((uint32_t)0x00000002)
#define | ADC_SQR1_SQ25_2 ((uint32_t)0x00000004)
#define | ADC_SQR1_SQ25_3 ((uint32_t)0x00000008)
#define | ADC_SQR1_SQ25_4 ((uint32_t)0x00000010)
#define | ADC_SQR1_SQ26 ((uint32_t)0x000003E0)
#define | ADC_SQR1_SQ26_0 ((uint32_t)0x00000020)
#define | ADC_SQR1_SQ26_1 ((uint32_t)0x00000040)
#define | ADC_SQR1_SQ26_2 ((uint32_t)0x00000080)
#define | ADC_SQR1_SQ26_3 ((uint32_t)0x00000100)
#define | ADC_SQR1_SQ26_4 ((uint32_t)0x00000200)
#define | ADC_SQR1_SQ27 ((uint32_t)0x00007C00)
#define | ADC_SQR1_SQ27_0 ((uint32_t)0x00000400)
#define | ADC_SQR1_SQ27_1 ((uint32_t)0x00000800)
#define | ADC_SQR1_SQ27_2 ((uint32_t)0x00001000)
#define | ADC_SQR1_SQ27_3 ((uint32_t)0x00002000)
#define | ADC_SQR1_SQ27_4 ((uint32_t)0x00004000)
#define | ADC_SQR1_SQ28 ((uint32_t)0x000F8000)
#define | ADC_SQR1_SQ28_0 ((uint32_t)0x00008000)
#define | ADC_SQR1_SQ28_1 ((uint32_t)0x00010000)
#define | ADC_SQR1_SQ28_2 ((uint32_t)0x00020000)
#define | ADC_SQR1_SQ28_3 ((uint32_t)0x00040000)
#define | ADC_SQR1_SQ28_4 ((uint32_t)0x00080000)
#define | ADC_SQR2_SQ19 ((uint32_t)0x0000001F)
#define | ADC_SQR2_SQ19_0 ((uint32_t)0x00000001)
#define | ADC_SQR2_SQ19_1 ((uint32_t)0x00000002)
#define | ADC_SQR2_SQ19_2 ((uint32_t)0x00000004)
#define | ADC_SQR2_SQ19_3 ((uint32_t)0x00000008)
#define | ADC_SQR2_SQ19_4 ((uint32_t)0x00000010)
#define | ADC_SQR2_SQ20 ((uint32_t)0x000003E0)
#define | ADC_SQR2_SQ20_0 ((uint32_t)0x00000020)
#define | ADC_SQR2_SQ20_1 ((uint32_t)0x00000040)
#define | ADC_SQR2_SQ20_2 ((uint32_t)0x00000080)
#define | ADC_SQR2_SQ20_3 ((uint32_t)0x00000100)
#define | ADC_SQR2_SQ20_4 ((uint32_t)0x00000200)
#define | ADC_SQR2_SQ21 ((uint32_t)0x00007C00)
#define | ADC_SQR2_SQ21_0 ((uint32_t)0x00000400)
#define | ADC_SQR2_SQ21_1 ((uint32_t)0x00000800)
#define | ADC_SQR2_SQ21_2 ((uint32_t)0x00001000)
#define | ADC_SQR2_SQ21_3 ((uint32_t)0x00002000)
#define | ADC_SQR2_SQ21_4 ((uint32_t)0x00004000)
#define | ADC_SQR2_SQ22 ((uint32_t)0x000F8000)
#define | ADC_SQR2_SQ22_0 ((uint32_t)0x00008000)
#define | ADC_SQR2_SQ22_1 ((uint32_t)0x00010000)
#define | ADC_SQR2_SQ22_2 ((uint32_t)0x00020000)
#define | ADC_SQR2_SQ22_3 ((uint32_t)0x00040000)
#define | ADC_SQR2_SQ22_4 ((uint32_t)0x00080000)
#define | ADC_SQR2_SQ23 ((uint32_t)0x01F00000)
#define | ADC_SQR2_SQ23_0 ((uint32_t)0x00100000)
#define | ADC_SQR2_SQ23_1 ((uint32_t)0x00200000)
#define | ADC_SQR2_SQ23_2 ((uint32_t)0x00400000)
#define | ADC_SQR2_SQ23_3 ((uint32_t)0x00800000)
#define | ADC_SQR2_SQ23_4 ((uint32_t)0x01000000)
#define | ADC_SQR2_SQ24 ((uint32_t)0x3E000000)
#define | ADC_SQR2_SQ24_0 ((uint32_t)0x02000000)
#define | ADC_SQR2_SQ24_1 ((uint32_t)0x04000000)
#define | ADC_SQR2_SQ24_2 ((uint32_t)0x08000000)
#define | ADC_SQR2_SQ24_3 ((uint32_t)0x10000000)
#define | ADC_SQR2_SQ24_4 ((uint32_t)0x20000000)
#define | ADC_SQR3_SQ13 ((uint32_t)0x0000001F)
#define | ADC_SQR3_SQ13_0 ((uint32_t)0x00000001)
#define | ADC_SQR3_SQ13_1 ((uint32_t)0x00000002)
#define | ADC_SQR3_SQ13_2 ((uint32_t)0x00000004)
#define | ADC_SQR3_SQ13_3 ((uint32_t)0x00000008)
#define | ADC_SQR3_SQ13_4 ((uint32_t)0x00000010)
#define | ADC_SQR3_SQ14 ((uint32_t)0x000003E0)
#define | ADC_SQR3_SQ14_0 ((uint32_t)0x00000020)
#define | ADC_SQR3_SQ14_1 ((uint32_t)0x00000040)
#define | ADC_SQR3_SQ14_2 ((uint32_t)0x00000080)
#define | ADC_SQR3_SQ14_3 ((uint32_t)0x00000100)
#define | ADC_SQR3_SQ14_4 ((uint32_t)0x00000200)
#define | ADC_SQR3_SQ15 ((uint32_t)0x00007C00)
#define | ADC_SQR3_SQ15_0 ((uint32_t)0x00000400)
#define | ADC_SQR3_SQ15_1 ((uint32_t)0x00000800)
#define | ADC_SQR3_SQ15_2 ((uint32_t)0x00001000)
#define | ADC_SQR3_SQ15_3 ((uint32_t)0x00002000)
#define | ADC_SQR3_SQ15_4 ((uint32_t)0x00004000)
#define | ADC_SQR3_SQ16 ((uint32_t)0x000F8000)
#define | ADC_SQR3_SQ16_0 ((uint32_t)0x00008000)
#define | ADC_SQR3_SQ16_1 ((uint32_t)0x00010000)
#define | ADC_SQR3_SQ16_2 ((uint32_t)0x00020000)
#define | ADC_SQR3_SQ16_3 ((uint32_t)0x00040000)
#define | ADC_SQR3_SQ16_4 ((uint32_t)0x00080000)
#define | ADC_SQR3_SQ17 ((uint32_t)0x01F00000)
#define | ADC_SQR3_SQ17_0 ((uint32_t)0x00100000)
#define | ADC_SQR3_SQ17_1 ((uint32_t)0x00200000)
#define | ADC_SQR3_SQ17_2 ((uint32_t)0x00400000)
#define | ADC_SQR3_SQ17_3 ((uint32_t)0x00800000)
#define | ADC_SQR3_SQ17_4 ((uint32_t)0x01000000)
#define | ADC_SQR3_SQ18 ((uint32_t)0x3E000000)
#define | ADC_SQR3_SQ18_0 ((uint32_t)0x02000000)
#define | ADC_SQR3_SQ18_1 ((uint32_t)0x04000000)
#define | ADC_SQR3_SQ18_2 ((uint32_t)0x08000000)
#define | ADC_SQR3_SQ18_3 ((uint32_t)0x10000000)
#define | ADC_SQR3_SQ18_4 ((uint32_t)0x20000000)
#define | ADC_SQR4_SQ10 ((uint32_t)0x000F8000)
#define | ADC_SQR4_SQ10_0 ((uint32_t)0x00008000)
#define | ADC_SQR4_SQ10_1 ((uint32_t)0x00010000)
#define | ADC_SQR4_SQ10_2 ((uint32_t)0x00020000)
#define | ADC_SQR4_SQ10_3 ((uint32_t)0x00040000)
#define | ADC_SQR4_SQ10_4 ((uint32_t)0x00080000)
#define | ADC_SQR4_SQ11 ((uint32_t)0x01F00000)
#define | ADC_SQR4_SQ11_0 ((uint32_t)0x00100000)
#define | ADC_SQR4_SQ11_1 ((uint32_t)0x00200000)
#define | ADC_SQR4_SQ11_2 ((uint32_t)0x00400000)
#define | ADC_SQR4_SQ11_3 ((uint32_t)0x00800000)
#define | ADC_SQR4_SQ11_4 ((uint32_t)0x01000000)
#define | ADC_SQR4_SQ12 ((uint32_t)0x3E000000)
#define | ADC_SQR4_SQ12_0 ((uint32_t)0x02000000)
#define | ADC_SQR4_SQ12_1 ((uint32_t)0x04000000)
#define | ADC_SQR4_SQ12_2 ((uint32_t)0x08000000)
#define | ADC_SQR4_SQ12_3 ((uint32_t)0x10000000)
#define | ADC_SQR4_SQ12_4 ((uint32_t)0x20000000)
#define | ADC_SQR4_SQ7 ((uint32_t)0x0000001F)
#define | ADC_SQR4_SQ7_0 ((uint32_t)0x00000001)
#define | ADC_SQR4_SQ7_1 ((uint32_t)0x00000002)
#define | ADC_SQR4_SQ7_2 ((uint32_t)0x00000004)
#define | ADC_SQR4_SQ7_3 ((uint32_t)0x00000008)
#define | ADC_SQR4_SQ7_4 ((uint32_t)0x00000010)
#define | ADC_SQR4_SQ8 ((uint32_t)0x000003E0)
#define | ADC_SQR4_SQ8_0 ((uint32_t)0x00000020)
#define | ADC_SQR4_SQ8_1 ((uint32_t)0x00000040)
#define | ADC_SQR4_SQ8_2 ((uint32_t)0x00000080)
#define | ADC_SQR4_SQ8_3 ((uint32_t)0x00000100)
#define | ADC_SQR4_SQ8_4 ((uint32_t)0x00000200)
#define | ADC_SQR4_SQ9 ((uint32_t)0x00007C00)
#define | ADC_SQR4_SQ9_0 ((uint32_t)0x00000400)
#define | ADC_SQR4_SQ9_1 ((uint32_t)0x00000800)
#define | ADC_SQR4_SQ9_2 ((uint32_t)0x00001000)
#define | ADC_SQR4_SQ9_3 ((uint32_t)0x00002000)
#define | ADC_SQR4_SQ9_4 ((uint32_t)0x00004000)
#define | ADC_SQR5_SQ1 ((uint32_t)0x0000001F)
#define | ADC_SQR5_SQ1_0 ((uint32_t)0x00000001)
#define | ADC_SQR5_SQ1_1 ((uint32_t)0x00000002)
#define | ADC_SQR5_SQ1_2 ((uint32_t)0x00000004)
#define | ADC_SQR5_SQ1_3 ((uint32_t)0x00000008)
#define | ADC_SQR5_SQ1_4 ((uint32_t)0x00000010)
#define | ADC_SQR5_SQ2 ((uint32_t)0x000003E0)
#define | ADC_SQR5_SQ2_0 ((uint32_t)0x00000020)
#define | ADC_SQR5_SQ2_1 ((uint32_t)0x00000040)
#define | ADC_SQR5_SQ2_2 ((uint32_t)0x00000080)
#define | ADC_SQR5_SQ2_3 ((uint32_t)0x00000100)
#define | ADC_SQR5_SQ2_4 ((uint32_t)0x00000200)
#define | ADC_SQR5_SQ3 ((uint32_t)0x00007C00)
#define | ADC_SQR5_SQ3_0 ((uint32_t)0x00000400)
#define | ADC_SQR5_SQ3_1 ((uint32_t)0x00000800)
#define | ADC_SQR5_SQ3_2 ((uint32_t)0x00001000)
#define | ADC_SQR5_SQ3_3 ((uint32_t)0x00002000)
#define | ADC_SQR5_SQ3_4 ((uint32_t)0x00004000)
#define | ADC_SQR5_SQ4 ((uint32_t)0x000F8000)
#define | ADC_SQR5_SQ4_0 ((uint32_t)0x00008000)
#define | ADC_SQR5_SQ4_1 ((uint32_t)0x00010000)
#define | ADC_SQR5_SQ4_2 ((uint32_t)0x00020000)
#define | ADC_SQR5_SQ4_3 ((uint32_t)0x00040000)
#define | ADC_SQR5_SQ4_4 ((uint32_t)0x00080000)
#define | ADC_SQR5_SQ5 ((uint32_t)0x01F00000)
#define | ADC_SQR5_SQ5_0 ((uint32_t)0x00100000)
#define | ADC_SQR5_SQ5_1 ((uint32_t)0x00200000)
#define | ADC_SQR5_SQ5_2 ((uint32_t)0x00400000)
#define | ADC_SQR5_SQ5_3 ((uint32_t)0x00800000)
#define | ADC_SQR5_SQ5_4 ((uint32_t)0x01000000)
#define | ADC_SQR5_SQ6 ((uint32_t)0x3E000000)
#define | ADC_SQR5_SQ6_0 ((uint32_t)0x02000000)
#define | ADC_SQR5_SQ6_1 ((uint32_t)0x04000000)
#define | ADC_SQR5_SQ6_2 ((uint32_t)0x08000000)
#define | ADC_SQR5_SQ6_3 ((uint32_t)0x10000000)
#define | ADC_SQR5_SQ6_4 ((uint32_t)0x20000000)
#define | ADC_SR_ADONS ((uint32_t)0x00000040)
#define | ADC_SR_AWD ((uint32_t)0x00000001)
#define | ADC_SR_EOC ((uint32_t)0x00000002)
#define | ADC_SR_JCNR ((uint32_t)0x00000200)
#define | ADC_SR_JEOC ((uint32_t)0x00000004)
#define | ADC_SR_JSTRT ((uint32_t)0x00000008)
#define | ADC_SR_OVR ((uint32_t)0x00000020)
#define | ADC_SR_RCNR ((uint32_t)0x00000100)
#define | ADC_SR_STRT ((uint32_t)0x00000010)
#define | AES ((AES_TypeDef *) AES_BASE)
#define | AES_BASE ((uint32_t)0x50060000)
#define | AES_CR_CCFC ((uint32_t)0x00000080)
#define | AES_CR_CCIE ((uint32_t)0x00000200)
#define | AES_CR_CHMOD ((uint32_t)0x00000060)
#define | AES_CR_CHMOD_0 ((uint32_t)0x00000020)
#define | AES_CR_CHMOD_1 ((uint32_t)0x00000040)
#define | AES_CR_DATATYPE ((uint32_t)0x00000006)
#define | AES_CR_DATATYPE_0 ((uint32_t)0x00000002)
#define | AES_CR_DATATYPE_1 ((uint32_t)0x00000004)
#define | AES_CR_DMAINEN ((uint32_t)0x00000800)
#define | AES_CR_DMAOUTEN ((uint32_t)0x00001000)
#define | AES_CR_EN ((uint32_t)0x00000001)
#define | AES_CR_ERRC ((uint32_t)0x00000100)
#define | AES_CR_ERRIE ((uint32_t)0x00000400)
#define | AES_CR_MODE ((uint32_t)0x00000018)
#define | AES_CR_MODE_0 ((uint32_t)0x00000008)
#define | AES_CR_MODE_1 ((uint32_t)0x00000010)
#define | AES_DINR ((uint32_t)0x0000FFFF)
#define | AES_DOUTR ((uint32_t)0x0000FFFF)
#define | AES_IVR0 ((uint32_t)0x0000FFFF)
#define | AES_IVR1 ((uint32_t)0x0000FFFF)
#define | AES_IVR2 ((uint32_t)0x0000FFFF)
#define | AES_IVR3 ((uint32_t)0x0000FFFF)
#define | AES_KEYR0 ((uint32_t)0x0000FFFF)
#define | AES_KEYR1 ((uint32_t)0x0000FFFF)
#define | AES_KEYR2 ((uint32_t)0x0000FFFF)
#define | AES_KEYR3 ((uint32_t)0x0000FFFF)
#define | AES_SR_CCF ((uint32_t)0x00000001)
#define | AES_SR_RDERR ((uint32_t)0x00000002)
#define | AES_SR_WRERR ((uint32_t)0x00000004)
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define | APB1PERIPH_BASE PERIPH_BASE
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define | CLEAR_REG(REG) ((REG) = (0x0))
#define | COMP ((COMP_TypeDef *) COMP_BASE)
#define | COMP_BASE (APB1PERIPH_BASE + 0x7C00)
#define | COMP_CSR_10KPD ((uint32_t)0x00000004)
#define | COMP_CSR_10KPU ((uint32_t)0x00000001)
#define | COMP_CSR_400KPD ((uint32_t)0x00000008)
#define | COMP_CSR_400KPU ((uint32_t)0x00000002)
#define | COMP_CSR_CAIE ((uint32_t)0x20000000)
#define | COMP_CSR_CAIF ((uint32_t)0x40000000)
#define | COMP_CSR_CMP1EN ((uint32_t)0x00000010)
#define | COMP_CSR_CMP1OUT ((uint32_t)0x00000080)
#define | COMP_CSR_CMP2OUT ((uint32_t)0x00002000)
#define | COMP_CSR_FCH3 ((uint32_t)0x04000000)
#define | COMP_CSR_FCH8 ((uint32_t)0x08000000)
#define | COMP_CSR_INSEL ((uint32_t)0x001C0000)
#define | COMP_CSR_INSEL_0 ((uint32_t)0x00040000)
#define | COMP_CSR_INSEL_1 ((uint32_t)0x00080000)
#define | COMP_CSR_INSEL_2 ((uint32_t)0x00100000)
#define | COMP_CSR_OUTSEL ((uint32_t)0x00E00000)
#define | COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000)
#define | COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000)
#define | COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000)
#define | COMP_CSR_RCH13 ((uint32_t)0x10000000)
#define | COMP_CSR_SPEED ((uint32_t)0x00001000)
#define | COMP_CSR_SW1 ((uint32_t)0x00000020)
#define | COMP_CSR_TSUSP ((uint32_t)0x80000000)
#define | COMP_CSR_VREFOUTEN ((uint32_t)0x00010000)
#define | COMP_CSR_WNDWE ((uint32_t)0x00020000)
#define | CRC ((CRC_TypeDef *) CRC_BASE)
#define | CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define | CRC_CR_RESET ((uint32_t)0x00000001)
#define | CRC_DR_DR ((uint32_t)0xFFFFFFFF)
#define | CRC_IDR_IDR ((uint8_t)0xFF)
#define | DAC ((DAC_TypeDef *) DAC_BASE)
#define | DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define | DAC_CR_BOFF1 ((uint32_t)0x00000002)
#define | DAC_CR_BOFF2 ((uint32_t)0x00020000)
#define | DAC_CR_DMAEN1 ((uint32_t)0x00001000)
#define | DAC_CR_DMAEN2 ((uint32_t)0x10000000)
#define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000)
#define | DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000)
#define | DAC_CR_EN1 ((uint32_t)0x00000001)
#define | DAC_CR_EN2 ((uint32_t)0x00010000)
#define | DAC_CR_MAMP1 ((uint32_t)0x00000F00)
#define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
#define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
#define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
#define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
#define | DAC_CR_MAMP2 ((uint32_t)0x0F000000)
#define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
#define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
#define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
#define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
#define | DAC_CR_TEN1 ((uint32_t)0x00000004)
#define | DAC_CR_TEN2 ((uint32_t)0x00040000)
#define | DAC_CR_TSEL1 ((uint32_t)0x00000038)
#define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
#define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
#define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
#define | DAC_CR_TSEL2 ((uint32_t)0x00380000)
#define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
#define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
#define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
#define | DAC_CR_WAVE1 ((uint32_t)0x000000C0)
#define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
#define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
#define | DAC_CR_WAVE2 ((uint32_t)0x00C00000)
#define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
#define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
#define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
#define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
#define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
#define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
#define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
#define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
#define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
#define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
#define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
#define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
#define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
#define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
#define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
#define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
#define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
#define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
#define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
#define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
#define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
#define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
#define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
#define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
#define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
#define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
#define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
#define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
#define | DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008)
#define | DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010)
#define | DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004)
#define | DBGMCU_BASE ((uint32_t)0xE0042000)
#define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
#define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
#define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
#define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)
#define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)
#define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
#define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
#define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)
#define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)
#define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)
#define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)
#define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)
#define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)
#define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)
#define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)
#define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)
#define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)
#define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)
#define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)
#define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)
#define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)
#define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)
#define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define | DMA1_BASE (AHBPERIPH_BASE + 0x6000)
#define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define | DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
#define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define | DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
#define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define | DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
#define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define | DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
#define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define | DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
#define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define | DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
#define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define | DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define | DMA2_BASE (AHBPERIPH_BASE + 0x6400)
#define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define | DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
#define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define | DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
#define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define | DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
#define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define | DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
#define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define | DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
#define | DMA_CCR1_CIRC ((uint16_t)0x0020)
#define | DMA_CCR1_DIR ((uint16_t)0x0010)
#define | DMA_CCR1_EN ((uint16_t)0x0001)
#define | DMA_CCR1_HTIE ((uint16_t)0x0004)
#define | DMA_CCR1_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR1_MINC ((uint16_t)0x0080)
#define | DMA_CCR1_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR1_PINC ((uint16_t)0x0040)
#define | DMA_CCR1_PL ((uint16_t)0x3000)
#define | DMA_CCR1_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR1_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR1_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR1_TCIE ((uint16_t)0x0002)
#define | DMA_CCR1_TEIE ((uint16_t)0x0008)
#define | DMA_CCR2_CIRC ((uint16_t)0x0020)
#define | DMA_CCR2_DIR ((uint16_t)0x0010)
#define | DMA_CCR2_EN ((uint16_t)0x0001)
#define | DMA_CCR2_HTIE ((uint16_t)0x0004)
#define | DMA_CCR2_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR2_MINC ((uint16_t)0x0080)
#define | DMA_CCR2_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR2_PINC ((uint16_t)0x0040)
#define | DMA_CCR2_PL ((uint16_t)0x3000)
#define | DMA_CCR2_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR2_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR2_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR2_TCIE ((uint16_t)0x0002)
#define | DMA_CCR2_TEIE ((uint16_t)0x0008)
#define | DMA_CCR3_CIRC ((uint16_t)0x0020)
#define | DMA_CCR3_DIR ((uint16_t)0x0010)
#define | DMA_CCR3_EN ((uint16_t)0x0001)
#define | DMA_CCR3_HTIE ((uint16_t)0x0004)
#define | DMA_CCR3_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR3_MINC ((uint16_t)0x0080)
#define | DMA_CCR3_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR3_PINC ((uint16_t)0x0040)
#define | DMA_CCR3_PL ((uint16_t)0x3000)
#define | DMA_CCR3_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR3_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR3_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR3_TCIE ((uint16_t)0x0002)
#define | DMA_CCR3_TEIE ((uint16_t)0x0008)
#define | DMA_CCR4_CIRC ((uint16_t)0x0020)
#define | DMA_CCR4_DIR ((uint16_t)0x0010)
#define | DMA_CCR4_EN ((uint16_t)0x0001)
#define | DMA_CCR4_HTIE ((uint16_t)0x0004)
#define | DMA_CCR4_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR4_MINC ((uint16_t)0x0080)
#define | DMA_CCR4_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR4_PINC ((uint16_t)0x0040)
#define | DMA_CCR4_PL ((uint16_t)0x3000)
#define | DMA_CCR4_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR4_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR4_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR4_TCIE ((uint16_t)0x0002)
#define | DMA_CCR4_TEIE ((uint16_t)0x0008)
#define | DMA_CCR5_CIRC ((uint16_t)0x0020)
#define | DMA_CCR5_DIR ((uint16_t)0x0010)
#define | DMA_CCR5_EN ((uint16_t)0x0001)
#define | DMA_CCR5_HTIE ((uint16_t)0x0004)
#define | DMA_CCR5_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR5_MINC ((uint16_t)0x0080)
#define | DMA_CCR5_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR5_PINC ((uint16_t)0x0040)
#define | DMA_CCR5_PL ((uint16_t)0x3000)
#define | DMA_CCR5_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR5_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR5_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR5_TCIE ((uint16_t)0x0002)
#define | DMA_CCR5_TEIE ((uint16_t)0x0008)
#define | DMA_CCR6_CIRC ((uint16_t)0x0020)
#define | DMA_CCR6_DIR ((uint16_t)0x0010)
#define | DMA_CCR6_EN ((uint16_t)0x0001)
#define | DMA_CCR6_HTIE ((uint16_t)0x0004)
#define | DMA_CCR6_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR6_MINC ((uint16_t)0x0080)
#define | DMA_CCR6_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR6_PINC ((uint16_t)0x0040)
#define | DMA_CCR6_PL ((uint16_t)0x3000)
#define | DMA_CCR6_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR6_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR6_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR6_TCIE ((uint16_t)0x0002)
#define | DMA_CCR6_TEIE ((uint16_t)0x0008)
#define | DMA_CCR7_CIRC ((uint16_t)0x0020)
#define | DMA_CCR7_DIR ((uint16_t)0x0010)
#define | DMA_CCR7_EN ((uint16_t)0x0001)
#define | DMA_CCR7_HTIE ((uint16_t)0x0004)
#define | DMA_CCR7_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR7_MINC ((uint16_t)0x0080)
#define | DMA_CCR7_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR7_PINC ((uint16_t)0x0040)
#define | DMA_CCR7_PL ((uint16_t)0x3000)
#define | DMA_CCR7_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR7_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR7_PSIZE , ((uint16_t)0x0300)
#define | DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR7_TCIE ((uint16_t)0x0002)
#define | DMA_CCR7_TEIE ((uint16_t)0x0008)
#define | DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CNDTR1_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR2_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR3_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR4_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR5_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR6_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR7_NDT ((uint16_t)0xFFFF)
#define | DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001)
#define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010)
#define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100)
#define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000)
#define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000)
#define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000)
#define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000)
#define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)
#define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)
#define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)
#define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)
#define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)
#define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)
#define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)
#define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)
#define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)
#define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)
#define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)
#define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)
#define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)
#define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)
#define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)
#define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)
#define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)
#define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)
#define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)
#define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)
#define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)
#define | DMA_ISR_GIF1 ((uint32_t)0x00000001)
#define | DMA_ISR_GIF2 ((uint32_t)0x00000010)
#define | DMA_ISR_GIF3 ((uint32_t)0x00000100)
#define | DMA_ISR_GIF4 ((uint32_t)0x00001000)
#define | DMA_ISR_GIF5 ((uint32_t)0x00010000)
#define | DMA_ISR_GIF6 ((uint32_t)0x00100000)
#define | DMA_ISR_GIF7 ((uint32_t)0x01000000)
#define | DMA_ISR_HTIF1 ((uint32_t)0x00000004)
#define | DMA_ISR_HTIF2 ((uint32_t)0x00000040)
#define | DMA_ISR_HTIF3 ((uint32_t)0x00000400)
#define | DMA_ISR_HTIF4 ((uint32_t)0x00004000)
#define | DMA_ISR_HTIF5 ((uint32_t)0x00040000)
#define | DMA_ISR_HTIF6 ((uint32_t)0x00400000)
#define | DMA_ISR_HTIF7 ((uint32_t)0x04000000)
#define | DMA_ISR_TCIF1 ((uint32_t)0x00000002)
#define | DMA_ISR_TCIF2 ((uint32_t)0x00000020)
#define | DMA_ISR_TCIF3 ((uint32_t)0x00000200)
#define | DMA_ISR_TCIF4 ((uint32_t)0x00002000)
#define | DMA_ISR_TCIF5 ((uint32_t)0x00020000)
#define | DMA_ISR_TCIF6 ((uint32_t)0x00200000)
#define | DMA_ISR_TCIF7 ((uint32_t)0x02000000)
#define | DMA_ISR_TEIF1 ((uint32_t)0x00000008)
#define | DMA_ISR_TEIF2 ((uint32_t)0x00000080)
#define | DMA_ISR_TEIF3 ((uint32_t)0x00000800)
#define | DMA_ISR_TEIF4 ((uint32_t)0x00008000)
#define | DMA_ISR_TEIF5 ((uint32_t)0x00080000)
#define | DMA_ISR_TEIF6 ((uint32_t)0x00800000)
#define | DMA_ISR_TEIF7 ((uint32_t)0x08000000)
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define | EXTI_EMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_EMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_EMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_EMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_EMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_EMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_EMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_EMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_EMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_EMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_EMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_EMR_MR19 ((uint32_t)0x00080000)
#define | EXTI_EMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_EMR_MR20 ((uint32_t)0x00100000)
#define | EXTI_EMR_MR21 ((uint32_t)0x00200000)
#define | EXTI_EMR_MR22 ((uint32_t)0x00400000)
#define | EXTI_EMR_MR23 ((uint32_t)0x00800000)
#define | EXTI_EMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_EMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_EMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_EMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_EMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_EMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_EMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_FTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_FTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_FTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_FTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_FTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_FTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_FTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_FTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_FTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_FTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_FTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_FTSR_TR19 ((uint32_t)0x00080000)
#define | EXTI_FTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_FTSR_TR20 ((uint32_t)0x00100000)
#define | EXTI_FTSR_TR21 ((uint32_t)0x00200000)
#define | EXTI_FTSR_TR22 ((uint32_t)0x00400000)
#define | EXTI_FTSR_TR23 ((uint32_t)0x00800000)
#define | EXTI_FTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_FTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_FTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_FTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_FTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_FTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_FTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_IMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_IMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_IMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_IMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_IMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_IMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_IMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_IMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_IMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_IMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_IMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_IMR_MR19 ((uint32_t)0x00080000)
#define | EXTI_IMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_IMR_MR20 ((uint32_t)0x00100000)
#define | EXTI_IMR_MR21 ((uint32_t)0x00200000)
#define | EXTI_IMR_MR22 ((uint32_t)0x00400000)
#define | EXTI_IMR_MR23 ((uint32_t)0x00800000)
#define | EXTI_IMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_IMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_IMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_IMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_IMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_IMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_IMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_PR_PR0 ((uint32_t)0x00000001)
#define | EXTI_PR_PR1 ((uint32_t)0x00000002)
#define | EXTI_PR_PR10 ((uint32_t)0x00000400)
#define | EXTI_PR_PR11 ((uint32_t)0x00000800)
#define | EXTI_PR_PR12 ((uint32_t)0x00001000)
#define | EXTI_PR_PR13 ((uint32_t)0x00002000)
#define | EXTI_PR_PR14 ((uint32_t)0x00004000)
#define | EXTI_PR_PR15 ((uint32_t)0x00008000)
#define | EXTI_PR_PR16 ((uint32_t)0x00010000)
#define | EXTI_PR_PR17 ((uint32_t)0x00020000)
#define | EXTI_PR_PR18 ((uint32_t)0x00040000)
#define | EXTI_PR_PR19 ((uint32_t)0x00080000)
#define | EXTI_PR_PR2 ((uint32_t)0x00000004)
#define | EXTI_PR_PR20 ((uint32_t)0x00100000)
#define | EXTI_PR_PR21 ((uint32_t)0x00200000)
#define | EXTI_PR_PR22 ((uint32_t)0x00400000)
#define | EXTI_PR_PR23 ((uint32_t)0x00800000)
#define | EXTI_PR_PR3 ((uint32_t)0x00000008)
#define | EXTI_PR_PR4 ((uint32_t)0x00000010)
#define | EXTI_PR_PR5 ((uint32_t)0x00000020)
#define | EXTI_PR_PR6 ((uint32_t)0x00000040)
#define | EXTI_PR_PR7 ((uint32_t)0x00000080)
#define | EXTI_PR_PR8 ((uint32_t)0x00000100)
#define | EXTI_PR_PR9 ((uint32_t)0x00000200)
#define | EXTI_RTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_RTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_RTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_RTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_RTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_RTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_RTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_RTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_RTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_RTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_RTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_RTSR_TR19 ((uint32_t)0x00080000)
#define | EXTI_RTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_RTSR_TR20 ((uint32_t)0x00100000)
#define | EXTI_RTSR_TR21 ((uint32_t)0x00200000)
#define | EXTI_RTSR_TR22 ((uint32_t)0x00400000)
#define | EXTI_RTSR_TR23 ((uint32_t)0x00800000)
#define | EXTI_RTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_RTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_RTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_RTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_RTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_RTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_RTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
#define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
#define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
#define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
#define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
#define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
#define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
#define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
#define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
#define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
#define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
#define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
#define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
#define | EXTI_SWIER_SWIER20 ((uint32_t)0x00100000)
#define | EXTI_SWIER_SWIER21 ((uint32_t)0x00200000)
#define | EXTI_SWIER_SWIER22 ((uint32_t)0x00400000)
#define | EXTI_SWIER_SWIER23 ((uint32_t)0x00800000)
#define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
#define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
#define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
#define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
#define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
#define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
#define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define | FLASH_ACR_ACC64 ((uint32_t)0x00000004)
#define | FLASH_ACR_LATENCY ((uint32_t)0x00000001)
#define | FLASH_ACR_PRFTEN ((uint32_t)0x00000002)
#define | FLASH_ACR_RUN_PD ((uint32_t)0x00000010)
#define | FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008)
#define | FLASH_BASE ((uint32_t)0x08000000)
#define | FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000)
#define | FLASH_OBR_IWDG_SW ((uint32_t)0x00100000)
#define | FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000)
#define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000)
#define | FLASH_OBR_nRST_STOP ((uint32_t)0x00200000)
#define | FLASH_OBR_RDPRT ((uint16_t)0x000000AA)
#define | FLASH_OBR_USER ((uint32_t)0x00700000)
#define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_PECR_DATA ((uint32_t)0x00000010)
#define | FLASH_PECR_EOPIE ((uint32_t)0x00010000)
#define | FLASH_PECR_ERASE ((uint32_t)0x00000200)
#define | FLASH_PECR_ERRIE ((uint32_t)0x00020000)
#define | FLASH_PECR_FPRG ((uint32_t)0x00000400)
#define | FLASH_PECR_FTDW ((uint32_t)0x00000100)
#define | FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000)
#define | FLASH_PECR_OPTLOCK ((uint32_t)0x00000004)
#define | FLASH_PECR_PARALLBANK ((uint32_t)0x00008000)
#define | FLASH_PECR_PELOCK ((uint32_t)0x00000001)
#define | FLASH_PECR_PRGLOCK ((uint32_t)0x00000002)
#define | FLASH_PECR_PROG ((uint32_t)0x00000008)
#define | FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00)
#define | FLASH_SR_BSY ((uint32_t)0x00000001)
#define | FLASH_SR_ENHV ((uint32_t)0x00000004)
#define | FLASH_SR_EOP ((uint32_t)0x00000002)
#define | FLASH_SR_OPTVERR ((uint32_t)0x00000800)
#define | FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000)
#define | FLASH_SR_PGAERR ((uint32_t)0x00000200)
#define | FLASH_SR_READY ((uint32_t)0x00000008)
#define | FLASH_SR_SIZERR ((uint32_t)0x00000400)
#define | FLASH_SR_WRPERR ((uint32_t)0x00000100)
#define | FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF)
#define | FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF)
#define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)
#define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR1_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR1_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR2_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR2_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR3_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR3_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR4_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR4_WREN ((uint32_t)0x00001000)
#define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_R_BASE ((uint32_t)0xA0000000)
#define | GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)
#define | GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)
#define | GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)
#define | GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)
#define | GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)
#define | GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)
#define | GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)
#define | GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)
#define | GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
#define | GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
#define | GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
#define | GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
#define | GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
#define | GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
#define | GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
#define | GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
#define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
#define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
#define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
#define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
#define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
#define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
#define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
#define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
#define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
#define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
#define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
#define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
#define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
#define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
#define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
#define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
#define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
#define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
#define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
#define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
#define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
#define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
#define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
#define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
#define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
#define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
#define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
#define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
#define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
#define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
#define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
#define | GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
#define | GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
#define | GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
#define | GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
#define | GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
#define | GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
#define | GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
#define | GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
#define | GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
#define | GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
#define | GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
#define | GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
#define | GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
#define | GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
#define | GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
#define | GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
#define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define | GPIO_LCKR_LCKK ((uint32_t)0x00010000)
#define | GPIO_MODER_MODER0 ((uint32_t)0x00000003)
#define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
#define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
#define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
#define | GPIO_MODER_MODER10 ((uint32_t)0x00300000)
#define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
#define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
#define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
#define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
#define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
#define | GPIO_MODER_MODER12 ((uint32_t)0x03000000)
#define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
#define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
#define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
#define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
#define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
#define | GPIO_MODER_MODER14 ((uint32_t)0x30000000)
#define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
#define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
#define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
#define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
#define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
#define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
#define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
#define | GPIO_MODER_MODER2 ((uint32_t)0x00000030)
#define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
#define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
#define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
#define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
#define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
#define | GPIO_MODER_MODER4 ((uint32_t)0x00000300)
#define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
#define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
#define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
#define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
#define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
#define | GPIO_MODER_MODER6 ((uint32_t)0x00003000)
#define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
#define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
#define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
#define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
#define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
#define | GPIO_MODER_MODER8 ((uint32_t)0x00030000)
#define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
#define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
#define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
#define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
#define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
#define | GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
#define | GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
#define | GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
#define | GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
#define | GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
#define | GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
#define | GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
#define | GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
#define | GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
#define | GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
#define | GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
#define | GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
#define | GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
#define | GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
#define | GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
#define | GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
#define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
#define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
#define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
#define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
#define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
#define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
#define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
#define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
#define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
#define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
#define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
#define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
#define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
#define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
#define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
#define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
#define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
#define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
#define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
#define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
#define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
#define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
#define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
#define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
#define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
#define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
#define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
#define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
#define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
#define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
#define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
#define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
#define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
#define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
#define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
#define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
#define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
#define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
#define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
#define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
#define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
#define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
#define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
#define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
#define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
#define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
#define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
#define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
#define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
#define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
#define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
#define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
#define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
#define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
#define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
#define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
#define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
#define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
#define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
#define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
#define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
#define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
#define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
#define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
#define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
#define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
#define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
#define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
#define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
#define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
#define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
#define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
#define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
#define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
#define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
#define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
#define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
#define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
#define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
#define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
#define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
#define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
#define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
#define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
#define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
#define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
#define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
#define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
#define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
#define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
#define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
#define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
#define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
#define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
#define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
#define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
#define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
#define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
#define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
#define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
#define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
#define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
#define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
#define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
#define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
#define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
#define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
#define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
#define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
#define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
#define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
#define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
#define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
#define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
#define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
#define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
#define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
#define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
#define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
#define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
#define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
#define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
#define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
#define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
#define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
#define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
#define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
#define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
#define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
#define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
#define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
#define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
#define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
#define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
#define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
#define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
#define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
#define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
#define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
#define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
#define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
#define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
#define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
#define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define | GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
#define | GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define | GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
#define | HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.
#define | HSE_VALUE ((uint32_t)8000000)
Comment the line below if you will not use the peripherals drivers.
#define | HSI_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value.
#define | HSI_VALUE ((uint32_t)16000000)
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define | I2C_CCR_CCR ((uint16_t)0x0FFF)
#define | I2C_CCR_DUTY ((uint16_t)0x4000)
#define | I2C_CCR_FS ((uint16_t)0x8000)
#define | I2C_CR1_ACK ((uint16_t)0x0400)
#define | I2C_CR1_ALERT ((uint16_t)0x2000)
#define | I2C_CR1_ENARP ((uint16_t)0x0010)
#define | I2C_CR1_ENGC ((uint16_t)0x0040)
#define | I2C_CR1_ENPEC ((uint16_t)0x0020)
#define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080)
#define | I2C_CR1_PE ((uint16_t)0x0001)
#define | I2C_CR1_PEC ((uint16_t)0x1000)
#define | I2C_CR1_POS ((uint16_t)0x0800)
#define | I2C_CR1_SMBTYPE ((uint16_t)0x0008)
#define | I2C_CR1_SMBUS ((uint16_t)0x0002)
#define | I2C_CR1_START ((uint16_t)0x0100)
#define | I2C_CR1_STOP ((uint16_t)0x0200)
#define | I2C_CR1_SWRST ((uint16_t)0x8000)
#define | I2C_CR2_DMAEN ((uint16_t)0x0800)
#define | I2C_CR2_FREQ ((uint16_t)0x003F)
#define | I2C_CR2_FREQ_0 ((uint16_t)0x0001)
#define | I2C_CR2_FREQ_1 ((uint16_t)0x0002)
#define | I2C_CR2_FREQ_2 ((uint16_t)0x0004)
#define | I2C_CR2_FREQ_3 ((uint16_t)0x0008)
#define | I2C_CR2_FREQ_4 ((uint16_t)0x0010)
#define | I2C_CR2_FREQ_5 ((uint16_t)0x0020)
#define | I2C_CR2_ITBUFEN ((uint16_t)0x0400)
#define | I2C_CR2_ITERREN ((uint16_t)0x0100)
#define | I2C_CR2_ITEVTEN ((uint16_t)0x0200)
#define | I2C_CR2_LAST ((uint16_t)0x1000)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_OAR1_ADD0 ((uint16_t)0x0001)
#define | I2C_OAR1_ADD1 ((uint16_t)0x0002)
#define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)
#define | I2C_OAR1_ADD2 ((uint16_t)0x0004)
#define | I2C_OAR1_ADD3 ((uint16_t)0x0008)
#define | I2C_OAR1_ADD4 ((uint16_t)0x0010)
#define | I2C_OAR1_ADD5 ((uint16_t)0x0020)
#define | I2C_OAR1_ADD6 ((uint16_t)0x0040)
#define | I2C_OAR1_ADD7 ((uint16_t)0x0080)
#define | I2C_OAR1_ADD8 ((uint16_t)0x0100)
#define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
#define | I2C_OAR1_ADD9 ((uint16_t)0x0200)
#define | I2C_OAR1_ADDMODE ((uint16_t)0x8000)
#define | I2C_OAR2_ADD2 ((uint8_t)0xFE)
#define | I2C_OAR2_ENDUAL ((uint8_t)0x01)
#define | I2C_SR1_ADD10 ((uint16_t)0x0008)
#define | I2C_SR1_ADDR ((uint16_t)0x0002)
#define | I2C_SR1_AF ((uint16_t)0x0400)
#define | I2C_SR1_ARLO ((uint16_t)0x0200)
#define | I2C_SR1_BERR ((uint16_t)0x0100)
#define | I2C_SR1_BTF ((uint16_t)0x0004)
#define | I2C_SR1_OVR ((uint16_t)0x0800)
#define | I2C_SR1_PECERR ((uint16_t)0x1000)
#define | I2C_SR1_RXNE ((uint16_t)0x0040)
#define | I2C_SR1_SB ((uint16_t)0x0001)
#define | I2C_SR1_SMBALERT ((uint16_t)0x8000)
#define | I2C_SR1_STOPF ((uint16_t)0x0010)
#define | I2C_SR1_TIMEOUT ((uint16_t)0x4000)
#define | I2C_SR1_TXE ((uint16_t)0x0080)
#define | I2C_SR2_BUSY ((uint16_t)0x0002)
#define | I2C_SR2_DUALF ((uint16_t)0x0080)
#define | I2C_SR2_GENCALL ((uint16_t)0x0010)
#define | I2C_SR2_MSL ((uint16_t)0x0001)
#define | I2C_SR2_PEC ((uint16_t)0xFF00)
#define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)
#define | I2C_SR2_SMBHOST ((uint16_t)0x0040)
#define | I2C_SR2_TRA ((uint16_t)0x0004)
#define | I2C_TRISE_TRISE ((uint8_t)0x3F)
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define | IWDG_KR_KEY ((uint16_t)0xFFFF)
#define | IWDG_PR_PR ((uint8_t)0x07)
#define | IWDG_PR_PR_0 ((uint8_t)0x01)
#define | IWDG_PR_PR_1 ((uint8_t)0x02)
#define | IWDG_PR_PR_2 ((uint8_t)0x04)
#define | IWDG_RLR_RL ((uint16_t)0x0FFF)
#define | IWDG_SR_PVU ((uint8_t)0x01)
#define | IWDG_SR_RVU ((uint8_t)0x02)
#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | LCD_BASE (APB1PERIPH_BASE + 0x2400)
#define | LCD_CLR_SOFC ((uint32_t)0x00000002)
#define | LCD_CLR_UDDC ((uint32_t)0x00000008)
#define | LCD_CR_BIAS ((uint32_t)0x00000060)
#define | LCD_CR_BIAS_0 ((uint32_t)0x00000020)
#define | LCD_CR_BIAS_1 ((uint32_t)0x00000040)
#define | LCD_CR_DUTY ((uint32_t)0x0000001C)
#define | LCD_CR_DUTY_0 ((uint32_t)0x00000004)
#define | LCD_CR_DUTY_1 ((uint32_t)0x00000008)
#define | LCD_CR_DUTY_2 ((uint32_t)0x00000010)
#define | LCD_CR_LCDEN ((uint32_t)0x00000001)
#define | LCD_CR_MUX_SEG ((uint32_t)0x00000080)
#define | LCD_CR_VSEL ((uint32_t)0x00000002)
#define | LCD_FCR_BLINK ((uint32_t)0x00030000)
#define | LCD_FCR_BLINK_0 ((uint32_t)0x00010000)
#define | LCD_FCR_BLINK_1 ((uint32_t)0x00020000)
#define | LCD_FCR_BLINKF ((uint32_t)0x0000E000)
#define | LCD_FCR_BLINKF_0 ((uint32_t)0x00002000)
#define | LCD_FCR_BLINKF_1 ((uint32_t)0x00004000)
#define | LCD_FCR_BLINKF_2 ((uint32_t)0x00008000)
#define | LCD_FCR_CC ((uint32_t)0x00001C00)
#define | LCD_FCR_CC_0 ((uint32_t)0x00000400)
#define | LCD_FCR_CC_1 ((uint32_t)0x00000800)
#define | LCD_FCR_CC_2 ((uint32_t)0x00001000)
#define | LCD_FCR_DEAD ((uint32_t)0x00000380)
#define | LCD_FCR_DEAD_0 ((uint32_t)0x00000080)
#define | LCD_FCR_DEAD_1 ((uint32_t)0x00000100)
#define | LCD_FCR_DEAD_2 ((uint32_t)0x00000200)
#define | LCD_FCR_DIV ((uint32_t)0x003C0000)
#define | LCD_FCR_HD ((uint32_t)0x00000001)
#define | LCD_FCR_PON ((uint32_t)0x00000070)
#define | LCD_FCR_PON_0 ((uint32_t)0x00000010)
#define | LCD_FCR_PON_1 ((uint32_t)0x00000020)
#define | LCD_FCR_PON_2 ((uint32_t)0x00000040)
#define | LCD_FCR_PS ((uint32_t)0x03C00000)
#define | LCD_FCR_SOFIE ((uint32_t)0x00000002)
#define | LCD_FCR_UDDIE ((uint32_t)0x00000008)
#define | LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF)
#define | LCD_SR_ENS ((uint32_t)0x00000001)
#define | LCD_SR_FCRSR ((uint32_t)0x00000020)
#define | LCD_SR_RDY ((uint32_t)0x00000010)
#define | LCD_SR_SOF ((uint32_t)0x00000002)
#define | LCD_SR_UDD ((uint32_t)0x00000008)
#define | LCD_SR_UDR ((uint32_t)0x00000004)
#define | LSE_VALUE ((uint32_t)32768)
#define | LSI_VALUE ((uint32_t)37000)
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)
#define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)
#define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)
#define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)
#define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)
#define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)
#define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)
#define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)
#define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)
#define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)
#define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)
#define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)
#define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)
#define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)
#define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)
#define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)
#define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)
#define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)
#define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)
#define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)
#define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)
#define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)
#define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)
#define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)
#define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)
#define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)
#define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)
#define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)
#define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)
#define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)
#define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)
#define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)
#define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)
#define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)
#define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)
#define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)
#define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)
#define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)
#define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)
#define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)
#define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)
#define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)
#define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)
#define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)
#define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)
#define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)
#define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)
#define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)
#define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)
#define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)
#define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)
#define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)
#define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)
#define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)
#define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)
#define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)
#define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)
#define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)
#define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)
#define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)
#define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)
#define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)
#define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)
#define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)
#define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)
#define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)
#define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)
#define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)
#define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)
#define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)
#define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)
#define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)
#define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)
#define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)
#define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)
#define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)
#define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)
#define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)
#define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)
#define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)
#define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)
#define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)
#define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)
#define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)
#define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)
#define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)
#define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)
#define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)
#define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)
#define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)
#define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)
#define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)
#define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)
#define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)
#define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)
#define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)
#define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)
#define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)
#define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)
#define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)
#define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)
#define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)
#define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)
#define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)
#define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)
#define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)
#define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)
#define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)
#define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)
#define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)
#define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)
#define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)
#define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)
#define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)
#define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)
#define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)
#define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)
#define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)
#define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)
#define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)
#define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)
#define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)
#define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)
#define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)
#define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)
#define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)
#define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)
#define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)
#define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)
#define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)
#define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)
#define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)
#define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)
#define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)
#define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)
#define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)
#define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)
#define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)
#define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)
#define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)
#define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)
#define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)
#define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)
#define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)
#define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)
#define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)
#define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)
#define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)
#define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)
#define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)
#define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)
#define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)
#define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)
#define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)
#define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)
#define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)
#define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)
#define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)
#define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)
#define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)
#define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)
#define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)
#define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)
#define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)
#define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)
#define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)
#define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)
#define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)
#define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)
#define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)
#define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)
#define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)
#define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)
#define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)
#define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)
#define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)
#define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)
#define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)
#define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)
#define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)
#define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)
#define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)
#define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)
#define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)
#define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)
#define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)
#define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)
#define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)
#define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)
#define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)
#define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)
#define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)
#define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)
#define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)
#define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)
#define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)
#define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)
#define | OB ((OB_TypeDef *) OB_BASE)
#define | OB_BASE ((uint32_t)0x1FF80000)
#define | OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define | OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
#define | OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000)
#define | OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000)
#define | OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000)
#define | OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000)
#define | OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040)
#define | OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020)
#define | OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000)
#define | OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080)
#define | OPAMP_CSR_OPA1PD ((uint32_t)0x00000001)
#define | OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000)
#define | OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000)
#define | OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000)
#define | OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000)
#define | OPAMP_CSR_OPA2PD ((uint32_t)0x00000100)
#define | OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000)
#define | OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000)
#define | OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000)
#define | OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000)
#define | OPAMP_CSR_OPA3PD ((uint32_t)0x00010000)
#define | OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002)
#define | OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200)
#define | OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000)
#define | OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004)
#define | OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400)
#define | OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000)
#define | OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008)
#define | OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800)
#define | OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000)
#define | OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010)
#define | OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000)
#define | OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000)
#define | OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000)
#define | OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF)
#define | OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00)
#define | OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000)
#define | OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF)
#define | OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00)
#define | OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000)
#define | OPAMP_OTR_OT_USER ((uint32_t)0x80000000)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | PERIPH_BB_BASE ((uint32_t)0x42000000)
#define | PWR ((PWR_TypeDef *) PWR_BASE)
#define | PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define | PWR_CR_CSBF ((uint16_t)0x0008)
#define | PWR_CR_CWUF ((uint16_t)0x0004)
#define | PWR_CR_DBP ((uint16_t)0x0100)
#define | PWR_CR_FWU ((uint16_t)0x0400)
#define | PWR_CR_LPRUN ((uint16_t)0x4000)
#define | PWR_CR_LPSDSR ((uint16_t)0x0001)
#define | PWR_CR_PDDS ((uint16_t)0x0002)
#define | PWR_CR_PLS ((uint16_t)0x00E0)
#define | PWR_CR_PLS_0 ((uint16_t)0x0020)
#define | PWR_CR_PLS_1 ((uint16_t)0x0040)
#define | PWR_CR_PLS_2 ((uint16_t)0x0080)
#define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000)
#define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020)
#define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040)
#define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060)
#define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080)
#define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0)
#define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0)
#define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0)
#define | PWR_CR_PVDE ((uint16_t)0x0010)
#define | PWR_CR_ULP ((uint16_t)0x0200)
#define | PWR_CR_VOS ((uint16_t)0x1800)
#define | PWR_CR_VOS_0 ((uint16_t)0x0800)
#define | PWR_CR_VOS_1 ((uint16_t)0x1000)
#define | PWR_CSR_EWUP1 ((uint16_t)0x0100)
#define | PWR_CSR_EWUP2 ((uint16_t)0x0200)
#define | PWR_CSR_EWUP3 ((uint16_t)0x0400)
#define | PWR_CSR_PVDO ((uint16_t)0x0004)
#define | PWR_CSR_REGLPF ((uint16_t)0x0020)
#define | PWR_CSR_SBF ((uint16_t)0x0002)
#define | PWR_CSR_VOSF ((uint16_t)0x0010)
#define | PWR_CSR_VREFINTRDYF ((uint16_t)0x0008)
#define | PWR_CSR_WUF ((uint16_t)0x0001)
#define | RCC ((RCC_TypeDef *) RCC_BASE)
#define | RCC_AHBENR_AESEN ((uint32_t)0x08000000)
#define | RCC_AHBENR_CRCEN ((uint32_t)0x00001000)
#define | RCC_AHBENR_DMA1EN ((uint32_t)0x01000000)
#define | RCC_AHBENR_DMA2EN ((uint32_t)0x02000000)
#define | RCC_AHBENR_FLITFEN ((uint32_t)0x00008000)
#define | RCC_AHBENR_FSMCEN ((uint32_t)0x40000000)
#define | RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001)
#define | RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002)
#define | RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004)
#define | RCC_AHBENR_GPIODEN ((uint32_t)0x00000008)
#define | RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010)
#define | RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040)
#define | RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080)
#define | RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020)
#define | RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000)
#define | RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000)
#define | RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000)
#define | RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000)
#define | RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000)
#define | RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000)
#define | RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001)
#define | RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002)
#define | RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004)
#define | RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008)
#define | RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010)
#define | RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040)
#define | RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080)
#define | RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020)
#define | RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000)
#define | RCC_AHBRSTR_AESRST ((uint32_t)0x08000000)
#define | RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000)
#define | RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000)
#define | RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000)
#define | RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000)
#define | RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000)
#define | RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001)
#define | RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002)
#define | RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004)
#define | RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008)
#define | RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010)
#define | RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040)
#define | RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080)
#define | RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020)
#define | RCC_APB1ENR_COMPEN ((uint32_t)0x80000000)
#define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
#define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define | RCC_APB1ENR_LCDEN ((uint32_t)0x00000200)
#define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000)
#define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define | RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000)
#define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
#define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
#define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
#define | RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200)
#define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
#define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
#define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
#define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
#define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
#define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
#define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
#define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
#define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
#define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
#define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
#define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
#define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
#define | RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000)
#define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
#define | RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000)
#define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
#define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define | RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200)
#define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
#define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
#define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)
#define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
#define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
#define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
#define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001)
#define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008)
#define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010)
#define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004)
#define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
#define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200)
#define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
#define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
#define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001)
#define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008)
#define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010)
#define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004)
#define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000)
#define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)
#define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001)
#define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008)
#define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010)
#define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004)
#define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
#define | RCC_BASE (AHBPERIPH_BASE + 0x3800)
#define | RCC_CFGR_HPRE ((uint32_t)0x000000F0)
#define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
#define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
#define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
#define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
#define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
#define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
#define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
#define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
#define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
#define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
#define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
#define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
#define | RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000)
#define | RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000)
#define | RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000)
#define | RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000)
#define | RCC_CFGR_MCO_HSE ((uint32_t)0x04000000)
#define | RCC_CFGR_MCO_HSI ((uint32_t)0x02000000)
#define | RCC_CFGR_MCO_LSE ((uint32_t)0x07000000)
#define | RCC_CFGR_MCO_LSI ((uint32_t)0x06000000)
#define | RCC_CFGR_MCO_MSI ((uint32_t)0x03000000)
#define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
#define | RCC_CFGR_MCO_PLL ((uint32_t)0x05000000)
#define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000)
#define | RCC_CFGR_MCOPRE ((uint32_t)0x70000000)
#define | RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000)
#define | RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000)
#define | RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000)
#define | RCC_CFGR_MCOSEL ((uint32_t)0x07000000)
#define | RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000)
#define | RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000)
#define | RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000)
#define | RCC_CFGR_PLLDIV ((uint32_t)0x00C00000)
#define | RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000)
#define | RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000)
#define | RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000)
#define | RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000)
#define | RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000)
#define | RCC_CFGR_PLLMUL ((uint32_t)0x003C0000)
#define | RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000)
#define | RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000)
#define | RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000)
#define | RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000)
#define | RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000)
#define | RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000)
#define | RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000)
#define | RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000)
#define | RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000)
#define | RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000)
#define | RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000)
#define | RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000)
#define | RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000)
#define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000)
#define | RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)
#define | RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000)
#define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700)
#define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)
#define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)
#define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)
#define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)
#define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)
#define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)
#define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)
#define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800)
#define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)
#define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)
#define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)
#define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)
#define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)
#define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)
#define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)
#define | RCC_CFGR_SW ((uint32_t)0x00000003)
#define | RCC_CFGR_SW_0 ((uint32_t)0x00000001)
#define | RCC_CFGR_SW_1 ((uint32_t)0x00000002)
#define | RCC_CFGR_SW_HSE ((uint32_t)0x00000002)
#define | RCC_CFGR_SW_HSI ((uint32_t)0x00000001)
#define | RCC_CFGR_SW_MSI ((uint32_t)0x00000000)
#define | RCC_CFGR_SW_PLL ((uint32_t)0x00000003)
#define | RCC_CFGR_SWS ((uint32_t)0x0000000C)
#define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
#define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
#define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000008)
#define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000004)
#define | RCC_CFGR_SWS_MSI ((uint32_t)0x00000000)
#define | RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C)
#define | RCC_CIR_CSSC ((uint32_t)0x00800000)
#define | RCC_CIR_CSSF ((uint32_t)0x00000080)
#define | RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define | RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define | RCC_CIR_LSECSS ((uint32_t)0x00000040)
#define | RCC_CIR_LSECSSC ((uint32_t)0x00400000)
#define | RCC_CIR_LSECSSIE ((uint32_t)0x00004000)
#define | RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define | RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define | RCC_CIR_MSIRDYC ((uint32_t)0x00200000)
#define | RCC_CIR_MSIRDYF ((uint32_t)0x00000020)
#define | RCC_CIR_MSIRDYIE ((uint32_t)0x00002000)
#define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define | RCC_CR_CSSON ((uint32_t)0x10000000)
#define | RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define | RCC_CR_HSEON ((uint32_t)0x00010000)
#define | RCC_CR_HSERDY ((uint32_t)0x00020000)
#define | RCC_CR_HSION ((uint32_t)0x00000001)
#define | RCC_CR_HSIRDY ((uint32_t)0x00000002)
#define | RCC_CR_MSION ((uint32_t)0x00000100)
#define | RCC_CR_MSIRDY ((uint32_t)0x00000200)
#define | RCC_CR_PLLON ((uint32_t)0x01000000)
#define | RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define | RCC_CR_RTCPRE ((uint32_t)0x60000000)
#define | RCC_CR_RTCPRE_0 ((uint32_t)0x20000000)
#define | RCC_CR_RTCPRE_1 ((uint32_t)0x40000000)
#define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
#define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
#define | RCC_CSR_LSEBYP ((uint32_t)0x00000400)
#define | RCC_CSR_LSECSSD ((uint32_t)0x00001000)
#define | RCC_CSR_LSECSSON ((uint32_t)0x00000800)
#define | RCC_CSR_LSEON ((uint32_t)0x00000100)
#define | RCC_CSR_LSERDY ((uint32_t)0x00000200)
#define | RCC_CSR_LSION ((uint32_t)0x00000001)
#define | RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define | RCC_CSR_OBLRSTF ((uint32_t)0x02000000)
#define | RCC_CSR_PINRSTF ((uint32_t)0x04000000)
#define | RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define | RCC_CSR_RMVF ((uint32_t)0x01000000)
#define | RCC_CSR_RTCEN ((uint32_t)0x00400000)
#define | RCC_CSR_RTCRST ((uint32_t)0x00800000)
#define | RCC_CSR_RTCSEL ((uint32_t)0x00030000)
#define | RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000)
#define | RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000)
#define | RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000)
#define | RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000)
#define | RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000)
#define | RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)
#define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define | RCC_ICSCR_HSICAL ((uint32_t)0x000000FF)
#define | RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00)
#define | RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000)
#define | RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000)
#define | RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000)
#define | RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000)
#define | RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000)
#define | RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000)
#define | RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000)
#define | RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000)
#define | RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000)
#define | RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000)
#define | READ_BIT(REG, BIT) ((REG) & (BIT))
#define | READ_REG(REG) ((REG))
#define | RI ((RI_TypeDef *) RI_BASE)
#define | RI_ASCR1_CH ((uint32_t)0x03FCFFFF)
#define | RI_ASCR1_CH_0 ((uint32_t)0x00000001)
#define | RI_ASCR1_CH_1 ((uint32_t)0x00000002)
#define | RI_ASCR1_CH_10 ((uint32_t)0x00000400)
#define | RI_ASCR1_CH_11 ((uint32_t)0x00000800)
#define | RI_ASCR1_CH_12 ((uint32_t)0x00001000)
#define | RI_ASCR1_CH_13 ((uint32_t)0x00002000)
#define | RI_ASCR1_CH_14 ((uint32_t)0x00004000)
#define | RI_ASCR1_CH_15 ((uint32_t)0x00008000)
#define | RI_ASCR1_CH_18 ((uint32_t)0x00040000)
#define | RI_ASCR1_CH_19 ((uint32_t)0x00080000)
#define | RI_ASCR1_CH_2 ((uint32_t)0x00000004)
#define | RI_ASCR1_CH_20 ((uint32_t)0x00100000)
#define | RI_ASCR1_CH_21 ((uint32_t)0x00200000)
#define | RI_ASCR1_CH_22 ((uint32_t)0x00400000)
#define | RI_ASCR1_CH_23 ((uint32_t)0x00800000)
#define | RI_ASCR1_CH_24 ((uint32_t)0x01000000)
#define | RI_ASCR1_CH_25 ((uint32_t)0x02000000)
#define | RI_ASCR1_CH_27 ((uint32_t)0x00400000)
#define | RI_ASCR1_CH_28 ((uint32_t)0x00800000)
#define | RI_ASCR1_CH_29 ((uint32_t)0x01000000)
#define | RI_ASCR1_CH_3 ((uint32_t)0x00000008)
#define | RI_ASCR1_CH_30 ((uint32_t)0x02000000)
#define | RI_ASCR1_CH_31 ((uint32_t)0x00010000)
#define | RI_ASCR1_CH_4 ((uint32_t)0x00000010)
#define | RI_ASCR1_CH_5 ((uint32_t)0x00000020)
#define | RI_ASCR1_CH_6 ((uint32_t)0x00000040)
#define | RI_ASCR1_CH_7 ((uint32_t)0x00000080)
#define | RI_ASCR1_CH_8 ((uint32_t)0x00000100)
#define | RI_ASCR1_CH_9 ((uint32_t)0x00000200)
#define | RI_ASCR1_SCM ((uint32_t)0x80000000)
#define | RI_ASCR1_VCOMP ((uint32_t)0x04000000)
#define | RI_ASCR2_CH0b ((uint32_t)0x00010000)
#define | RI_ASCR2_CH10b ((uint32_t)0x01000000)
#define | RI_ASCR2_CH11b ((uint32_t)0x02000000)
#define | RI_ASCR2_CH12b ((uint32_t)0x04000000)
#define | RI_ASCR2_CH1b ((uint32_t)0x00020000)
#define | RI_ASCR2_CH2b ((uint32_t)0x00040000)
#define | RI_ASCR2_CH3b ((uint32_t)0x00080000)
#define | RI_ASCR2_CH6b ((uint32_t)0x00100000)
#define | RI_ASCR2_CH7b ((uint32_t)0x00200000)
#define | RI_ASCR2_CH8b ((uint32_t)0x00400000)
#define | RI_ASCR2_CH9b ((uint32_t)0x00800000)
#define | RI_ASCR2_GR10_1 ((uint32_t)0x00000001)
#define | RI_ASCR2_GR10_2 ((uint32_t)0x00000002)
#define | RI_ASCR2_GR10_3 ((uint32_t)0x00000004)
#define | RI_ASCR2_GR10_4 ((uint32_t)0x00000008)
#define | RI_ASCR2_GR4_1 ((uint32_t)0x00000200)
#define | RI_ASCR2_GR4_2 ((uint32_t)0x00000400)
#define | RI_ASCR2_GR4_3 ((uint32_t)0x00000800)
#define | RI_ASCR2_GR4_4 ((uint32_t)0x00008000)
#define | RI_ASCR2_GR5_1 ((uint32_t)0x00000040)
#define | RI_ASCR2_GR5_2 ((uint32_t)0x00000080)
#define | RI_ASCR2_GR5_3 ((uint32_t)0x00000100)
#define | RI_ASCR2_GR5_4 ((uint32_t)0x20000000)
#define | RI_ASCR2_GR6_1 ((uint32_t)0x00000010)
#define | RI_ASCR2_GR6_2 ((uint32_t)0x00000020)
#define | RI_ASCR2_GR6_3 ((uint32_t)0x08000000)
#define | RI_ASCR2_GR6_4 ((uint32_t)0x10000000)
#define | RI_BASE (APB1PERIPH_BASE + 0x7C04)
#define | RI_HYSCR1_PA ((uint32_t)0x0000FFFF)
#define | RI_HYSCR1_PA_0 ((uint32_t)0x00000001)
#define | RI_HYSCR1_PA_1 ((uint32_t)0x00000002)
#define | RI_HYSCR1_PA_10 ((uint32_t)0x00000400)
#define | RI_HYSCR1_PA_11 ((uint32_t)0x00000800)
#define | RI_HYSCR1_PA_12 ((uint32_t)0x00001000)
#define | RI_HYSCR1_PA_13 ((uint32_t)0x00002000)
#define | RI_HYSCR1_PA_14 ((uint32_t)0x00004000)
#define | RI_HYSCR1_PA_15 ((uint32_t)0x00008000)
#define | RI_HYSCR1_PA_2 ((uint32_t)0x00000004)
#define | RI_HYSCR1_PA_3 ((uint32_t)0x00000008)
#define | RI_HYSCR1_PA_4 ((uint32_t)0x00000010)
#define | RI_HYSCR1_PA_5 ((uint32_t)0x00000020)
#define | RI_HYSCR1_PA_6 ((uint32_t)0x00000040)
#define | RI_HYSCR1_PA_7 ((uint32_t)0x00000080)
#define | RI_HYSCR1_PA_8 ((uint32_t)0x00000100)
#define | RI_HYSCR1_PA_9 ((uint32_t)0x00000200)
#define | RI_HYSCR1_PB ((uint32_t)0xFFFF0000)
#define | RI_HYSCR1_PB_0 ((uint32_t)0x00010000)
#define | RI_HYSCR1_PB_1 ((uint32_t)0x00020000)
#define | RI_HYSCR1_PB_10 ((uint32_t)0x04000000)
#define | RI_HYSCR1_PB_11 ((uint32_t)0x08000000)
#define | RI_HYSCR1_PB_12 ((uint32_t)0x10000000)
#define | RI_HYSCR1_PB_13 ((uint32_t)0x20000000)
#define | RI_HYSCR1_PB_14 ((uint32_t)0x40000000)
#define | RI_HYSCR1_PB_15 ((uint32_t)0x80000000)
#define | RI_HYSCR1_PB_2 ((uint32_t)0x00040000)
#define | RI_HYSCR1_PB_3 ((uint32_t)0x00080000)
#define | RI_HYSCR1_PB_4 ((uint32_t)0x00100000)
#define | RI_HYSCR1_PB_5 ((uint32_t)0x00200000)
#define | RI_HYSCR1_PB_6 ((uint32_t)0x00400000)
#define | RI_HYSCR1_PB_7 ((uint32_t)0x00800000)
#define | RI_HYSCR1_PB_8 ((uint32_t)0x01000000)
#define | RI_HYSCR1_PB_9 ((uint32_t)0x02000000)
#define | RI_HYSCR2_PC ((uint32_t)0x0000FFFF)
#define | RI_HYSCR2_PC_0 ((uint32_t)0x00000001)
#define | RI_HYSCR2_PC_1 ((uint32_t)0x00000002)
#define | RI_HYSCR2_PC_10 ((uint32_t)0x00000400)
#define | RI_HYSCR2_PC_11 ((uint32_t)0x00000800)
#define | RI_HYSCR2_PC_12 ((uint32_t)0x00001000)
#define | RI_HYSCR2_PC_13 ((uint32_t)0x00002000)
#define | RI_HYSCR2_PC_14 ((uint32_t)0x00004000)
#define | RI_HYSCR2_PC_15 ((uint32_t)0x00008000)
#define | RI_HYSCR2_PC_2 ((uint32_t)0x00000004)
#define | RI_HYSCR2_PC_3 ((uint32_t)0x00000008)
#define | RI_HYSCR2_PC_4 ((uint32_t)0x00000010)
#define | RI_HYSCR2_PC_5 ((uint32_t)0x00000020)
#define | RI_HYSCR2_PC_6 ((uint32_t)0x00000040)
#define | RI_HYSCR2_PC_7 ((uint32_t)0x00000080)
#define | RI_HYSCR2_PC_8 ((uint32_t)0x00000100)
#define | RI_HYSCR2_PC_9 ((uint32_t)0x00000200)
#define | RI_HYSCR2_PD ((uint32_t)0xFFFF0000)
#define | RI_HYSCR2_PD_0 ((uint32_t)0x00010000)
#define | RI_HYSCR2_PD_1 ((uint32_t)0x00020000)
#define | RI_HYSCR2_PD_10 ((uint32_t)0x04000000)
#define | RI_HYSCR2_PD_11 ((uint32_t)0x08000000)
#define | RI_HYSCR2_PD_12 ((uint32_t)0x10000000)
#define | RI_HYSCR2_PD_13 ((uint32_t)0x20000000)
#define | RI_HYSCR2_PD_14 ((uint32_t)0x40000000)
#define | RI_HYSCR2_PD_15 ((uint32_t)0x80000000)
#define | RI_HYSCR2_PD_2 ((uint32_t)0x00040000)
#define | RI_HYSCR2_PD_3 ((uint32_t)0x00080000)
#define | RI_HYSCR2_PD_4 ((uint32_t)0x00100000)
#define | RI_HYSCR2_PD_5 ((uint32_t)0x00200000)
#define | RI_HYSCR2_PD_6 ((uint32_t)0x00400000)
#define | RI_HYSCR2_PD_7 ((uint32_t)0x00800000)
#define | RI_HYSCR2_PD_8 ((uint32_t)0x01000000)
#define | RI_HYSCR2_PD_9 ((uint32_t)0x02000000)
#define | RI_HYSCR2_PE ((uint32_t)0x0000FFFF)
#define | RI_HYSCR2_PE_0 ((uint32_t)0x00000001)
#define | RI_HYSCR2_PE_1 ((uint32_t)0x00000002)
#define | RI_HYSCR2_PE_10 ((uint32_t)0x00000400)
#define | RI_HYSCR2_PE_11 ((uint32_t)0x00000800)
#define | RI_HYSCR2_PE_12 ((uint32_t)0x00001000)
#define | RI_HYSCR2_PE_13 ((uint32_t)0x00002000)
#define | RI_HYSCR2_PE_14 ((uint32_t)0x00004000)
#define | RI_HYSCR2_PE_15 ((uint32_t)0x00008000)
#define | RI_HYSCR2_PE_2 ((uint32_t)0x00000004)
#define | RI_HYSCR2_PE_3 ((uint32_t)0x00000008)
#define | RI_HYSCR2_PE_4 ((uint32_t)0x00000010)
#define | RI_HYSCR2_PE_5 ((uint32_t)0x00000020)
#define | RI_HYSCR2_PE_6 ((uint32_t)0x00000040)
#define | RI_HYSCR2_PE_7 ((uint32_t)0x00000080)
#define | RI_HYSCR2_PE_8 ((uint32_t)0x00000100)
#define | RI_HYSCR2_PE_9 ((uint32_t)0x00000200)
#define | RI_HYSCR3_PF ((uint32_t)0xFFFF0000)
#define | RI_HYSCR3_PF_0 ((uint32_t)0x00010000)
#define | RI_HYSCR3_PF_1 ((uint32_t)0x00020000)
#define | RI_HYSCR3_PF_10 ((uint32_t)0x04000000)
#define | RI_HYSCR3_PF_11 ((uint32_t)0x08000000)
#define | RI_HYSCR3_PF_12 ((uint32_t)0x10000000)
#define | RI_HYSCR3_PF_13 ((uint32_t)0x20000000)
#define | RI_HYSCR3_PF_14 ((uint32_t)0x40000000)
#define | RI_HYSCR3_PF_15 ((uint32_t)0x80000000)
#define | RI_HYSCR3_PF_2 ((uint32_t)0x00040000)
#define | RI_HYSCR3_PF_3 ((uint32_t)0x00080000)
#define | RI_HYSCR3_PF_4 ((uint32_t)0x00100000)
#define | RI_HYSCR3_PF_5 ((uint32_t)0x00200000)
#define | RI_HYSCR3_PF_6 ((uint32_t)0x00400000)
#define | RI_HYSCR3_PF_7 ((uint32_t)0x00800000)
#define | RI_HYSCR3_PF_8 ((uint32_t)0x01000000)
#define | RI_HYSCR3_PF_9 ((uint32_t)0x02000000)
#define | RI_HYSCR4_PG ((uint32_t)0x0000FFFF)
#define | RI_HYSCR4_PG_0 ((uint32_t)0x00000001)
#define | RI_HYSCR4_PG_1 ((uint32_t)0x00000002)
#define | RI_HYSCR4_PG_10 ((uint32_t)0x00000400)
#define | RI_HYSCR4_PG_11 ((uint32_t)0x00000800)
#define | RI_HYSCR4_PG_12 ((uint32_t)0x00001000)
#define | RI_HYSCR4_PG_13 ((uint32_t)0x00002000)
#define | RI_HYSCR4_PG_14 ((uint32_t)0x00004000)
#define | RI_HYSCR4_PG_15 ((uint32_t)0x00008000)
#define | RI_HYSCR4_PG_2 ((uint32_t)0x00000004)
#define | RI_HYSCR4_PG_3 ((uint32_t)0x00000008)
#define | RI_HYSCR4_PG_4 ((uint32_t)0x00000010)
#define | RI_HYSCR4_PG_5 ((uint32_t)0x00000020)
#define | RI_HYSCR4_PG_6 ((uint32_t)0x00000040)
#define | RI_HYSCR4_PG_7 ((uint32_t)0x00000080)
#define | RI_HYSCR4_PG_8 ((uint32_t)0x00000100)
#define | RI_HYSCR4_PG_9 ((uint32_t)0x00000200)
#define | RI_ICR_IC1 ((uint32_t)0x00040000)
#define | RI_ICR_IC1Z ((uint32_t)0x0000000F)
#define | RI_ICR_IC1Z_0 ((uint32_t)0x00000001)
#define | RI_ICR_IC1Z_1 ((uint32_t)0x00000002)
#define | RI_ICR_IC1Z_2 ((uint32_t)0x00000004)
#define | RI_ICR_IC1Z_3 ((uint32_t)0x00000008)
#define | RI_ICR_IC2 ((uint32_t)0x00080000)
#define | RI_ICR_IC2Z ((uint32_t)0x000000F0)
#define | RI_ICR_IC2Z_0 ((uint32_t)0x00000010)
#define | RI_ICR_IC2Z_1 ((uint32_t)0x00000020)
#define | RI_ICR_IC2Z_2 ((uint32_t)0x00000040)
#define | RI_ICR_IC2Z_3 ((uint32_t)0x00000080)
#define | RI_ICR_IC3 ((uint32_t)0x00100000)
#define | RI_ICR_IC3Z ((uint32_t)0x00000F00)
#define | RI_ICR_IC3Z_0 ((uint32_t)0x00000100)
#define | RI_ICR_IC3Z_1 ((uint32_t)0x00000200)
#define | RI_ICR_IC3Z_2 ((uint32_t)0x00000400)
#define | RI_ICR_IC3Z_3 ((uint32_t)0x00000800)
#define | RI_ICR_IC4 ((uint32_t)0x00200000)
#define | RI_ICR_IC4Z ((uint32_t)0x0000F000)
#define | RI_ICR_IC4Z_0 ((uint32_t)0x00001000)
#define | RI_ICR_IC4Z_1 ((uint32_t)0x00002000)
#define | RI_ICR_IC4Z_2 ((uint32_t)0x00004000)
#define | RI_ICR_IC4Z_3 ((uint32_t)0x00008000)
#define | RI_ICR_TIM ((uint32_t)0x00030000)
#define | RI_ICR_TIM_0 ((uint32_t)0x00010000)
#define | RI_ICR_TIM_1 ((uint32_t)0x00020000)
#define | RTC ((RTC_TypeDef *) RTC_BASE)
#define | RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define | RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define | RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define | RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define | RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define | RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define | RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define | RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
#define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
#define | RTC_ALRMBR_DT ((uint32_t)0x30000000)
#define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
#define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
#define | RTC_ALRMBR_DU ((uint32_t)0x0F000000)
#define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
#define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
#define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
#define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
#define | RTC_ALRMBR_HT ((uint32_t)0x00300000)
#define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
#define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
#define | RTC_ALRMBR_HU ((uint32_t)0x000F0000)
#define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
#define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
#define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
#define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
#define | RTC_ALRMBR_MNT ((uint32_t)0x00007000)
#define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
#define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
#define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
#define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
#define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
#define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
#define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
#define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
#define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
#define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
#define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
#define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
#define | RTC_ALRMBR_PM ((uint32_t)0x00400000)
#define | RTC_ALRMBR_ST ((uint32_t)0x00000070)
#define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
#define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
#define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
#define | RTC_ALRMBR_SU ((uint32_t)0x0000000F)
#define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
#define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
#define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
#define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
#define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
#define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
#define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
#define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
#define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
#define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
#define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
#define | RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define | RTC_BKP0R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP10R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP11R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP12R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP13R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP14R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP15R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP16R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP17R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP18R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP19R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP1R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP20R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP21R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP22R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP23R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP24R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP25R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP26R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP27R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP28R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP29R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP2R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP30R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP31R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP3R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP4R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP5R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP6R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP7R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP8R ((uint32_t)0xFFFFFFFF)
#define | RTC_BKP9R ((uint32_t)0xFFFFFFFF)
#define | RTC_CALIBR_DC ((uint32_t)0x0000001F)
#define | RTC_CALIBR_DCS ((uint32_t)0x00000080)
#define | RTC_CALR_CALM ((uint32_t)0x000001FF)
#define | RTC_CALR_CALM_0 ((uint32_t)0x00000001)
#define | RTC_CALR_CALM_1 ((uint32_t)0x00000002)
#define | RTC_CALR_CALM_2 ((uint32_t)0x00000004)
#define | RTC_CALR_CALM_3 ((uint32_t)0x00000008)
#define | RTC_CALR_CALM_4 ((uint32_t)0x00000010)
#define | RTC_CALR_CALM_5 ((uint32_t)0x00000020)
#define | RTC_CALR_CALM_6 ((uint32_t)0x00000040)
#define | RTC_CALR_CALM_7 ((uint32_t)0x00000080)
#define | RTC_CALR_CALM_8 ((uint32_t)0x00000100)
#define | RTC_CALR_CALP ((uint32_t)0x00008000)
#define | RTC_CALR_CALW16 ((uint32_t)0x00002000)
#define | RTC_CALR_CALW8 ((uint32_t)0x00004000)
#define | RTC_CR_ADD1H ((uint32_t)0x00010000)
#define | RTC_CR_ALRAE ((uint32_t)0x00000100)
#define | RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define | RTC_CR_ALRBE ((uint32_t)0x00000200)
#define | RTC_CR_ALRBIE ((uint32_t)0x00002000)
#define | RTC_CR_BCK ((uint32_t)0x00040000)
#define | RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define | RTC_CR_COE ((uint32_t)0x00800000)
#define | RTC_CR_COSEL ((uint32_t)0x00080000)
#define | RTC_CR_DCE ((uint32_t)0x00000080)
#define | RTC_CR_FMT ((uint32_t)0x00000040)
#define | RTC_CR_OSEL ((uint32_t)0x00600000)
#define | RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define | RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define | RTC_CR_POL ((uint32_t)0x00100000)
#define | RTC_CR_REFCKON ((uint32_t)0x00000010)
#define | RTC_CR_SUB1H ((uint32_t)0x00020000)
#define | RTC_CR_TSE ((uint32_t)0x00000800)
#define | RTC_CR_TSEDGE ((uint32_t)0x00000008)
#define | RTC_CR_TSIE ((uint32_t)0x00008000)
#define | RTC_CR_WUCKSEL ((uint32_t)0x00000007)
#define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
#define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
#define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
#define | RTC_CR_WUTE ((uint32_t)0x00000400)
#define | RTC_CR_WUTIE ((uint32_t)0x00004000)
#define | RTC_DR_DT ((uint32_t)0x00000030)
#define | RTC_DR_DT_0 ((uint32_t)0x00000010)
#define | RTC_DR_DT_1 ((uint32_t)0x00000020)
#define | RTC_DR_DU ((uint32_t)0x0000000F)
#define | RTC_DR_DU_0 ((uint32_t)0x00000001)
#define | RTC_DR_DU_1 ((uint32_t)0x00000002)
#define | RTC_DR_DU_2 ((uint32_t)0x00000004)
#define | RTC_DR_DU_3 ((uint32_t)0x00000008)
#define | RTC_DR_MT ((uint32_t)0x00001000)
#define | RTC_DR_MU ((uint32_t)0x00000F00)
#define | RTC_DR_MU_0 ((uint32_t)0x00000100)
#define | RTC_DR_MU_1 ((uint32_t)0x00000200)
#define | RTC_DR_MU_2 ((uint32_t)0x00000400)
#define | RTC_DR_MU_3 ((uint32_t)0x00000800)
#define | RTC_DR_WDU ((uint32_t)0x0000E000)
#define | RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define | RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define | RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define | RTC_DR_YT ((uint32_t)0x00F00000)
#define | RTC_DR_YT_0 ((uint32_t)0x00100000)
#define | RTC_DR_YT_1 ((uint32_t)0x00200000)
#define | RTC_DR_YT_2 ((uint32_t)0x00400000)
#define | RTC_DR_YT_3 ((uint32_t)0x00800000)
#define | RTC_DR_YU ((uint32_t)0x000F0000)
#define | RTC_DR_YU_0 ((uint32_t)0x00010000)
#define | RTC_DR_YU_1 ((uint32_t)0x00020000)
#define | RTC_DR_YU_2 ((uint32_t)0x00040000)
#define | RTC_DR_YU_3 ((uint32_t)0x00080000)
#define | RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define | RTC_ISR_ALRAWF ((uint32_t)0x00000001)
#define | RTC_ISR_ALRBF ((uint32_t)0x00000200)
#define | RTC_ISR_ALRBWF ((uint32_t)0x00000002)
#define | RTC_ISR_INIT ((uint32_t)0x00000080)
#define | RTC_ISR_INITF ((uint32_t)0x00000040)
#define | RTC_ISR_INITS ((uint32_t)0x00000010)
#define | RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define | RTC_ISR_RSF ((uint32_t)0x00000020)
#define | RTC_ISR_SHPF ((uint32_t)0x00000008)
#define | RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define | RTC_ISR_TAMP2F ((uint32_t)0x00004000)
#define | RTC_ISR_TAMP3F ((uint32_t)0x00008000)
#define | RTC_ISR_TSF ((uint32_t)0x00000800)
#define | RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define | RTC_ISR_WUTF ((uint32_t)0x00000400)
#define | RTC_ISR_WUTWF ((uint32_t)0x00000004)
#define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define | RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
#define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
#define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define | RTC_SSR_SS ((uint32_t)0x0000FFFF)
#define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
#define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
#define | RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
#define | RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
#define | RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
#define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define | RTC_TR_HT ((uint32_t)0x00300000)
#define | RTC_TR_HT_0 ((uint32_t)0x00100000)
#define | RTC_TR_HT_1 ((uint32_t)0x00200000)
#define | RTC_TR_HU ((uint32_t)0x000F0000)
#define | RTC_TR_HU_0 ((uint32_t)0x00010000)
#define | RTC_TR_HU_1 ((uint32_t)0x00020000)
#define | RTC_TR_HU_2 ((uint32_t)0x00040000)
#define | RTC_TR_HU_3 ((uint32_t)0x00080000)
#define | RTC_TR_MNT ((uint32_t)0x00007000)
#define | RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define | RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define | RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define | RTC_TR_MNU ((uint32_t)0x00000F00)
#define | RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define | RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define | RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define | RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define | RTC_TR_PM ((uint32_t)0x00400000)
#define | RTC_TR_ST ((uint32_t)0x00000070)
#define | RTC_TR_ST_0 ((uint32_t)0x00000010)
#define | RTC_TR_ST_1 ((uint32_t)0x00000020)
#define | RTC_TR_ST_2 ((uint32_t)0x00000040)
#define | RTC_TR_SU ((uint32_t)0x0000000F)
#define | RTC_TR_SU_0 ((uint32_t)0x00000001)
#define | RTC_TR_SU_1 ((uint32_t)0x00000002)
#define | RTC_TR_SU_2 ((uint32_t)0x00000004)
#define | RTC_TR_SU_3 ((uint32_t)0x00000008)
#define | RTC_TSDR_DT ((uint32_t)0x00000030)
#define | RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define | RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define | RTC_TSDR_DU ((uint32_t)0x0000000F)
#define | RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define | RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define | RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define | RTC_TSDR_DU_3 ((uint32_t)0x00000008)
#define | RTC_TSDR_MT ((uint32_t)0x00001000)
#define | RTC_TSDR_MU ((uint32_t)0x00000F00)
#define | RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define | RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define | RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define | RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define | RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
#define | RTC_TSTR_HT ((uint32_t)0x00300000)
#define | RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define | RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define | RTC_TSTR_HU ((uint32_t)0x000F0000)
#define | RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define | RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define | RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define | RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define | RTC_TSTR_MNT ((uint32_t)0x00007000)
#define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define | RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define | RTC_TSTR_PM ((uint32_t)0x00400000)
#define | RTC_TSTR_ST ((uint32_t)0x00000070)
#define | RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define | RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define | RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define | RTC_TSTR_SU ((uint32_t)0x0000000F)
#define | RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define | RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define | RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define | RTC_TSTR_SU_3 ((uint32_t)0x00000008)
#define | RTC_WPR_KEY ((uint32_t)0x000000FF)
#define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
#define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)
#define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)
#define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)
#define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)
#define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)
#define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)
#define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)
#define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)
#define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)
#define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)
#define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)
#define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)
#define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)
#define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)
#define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)
#define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)
#define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)
#define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)
#define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
#define | SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)
#define | SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)
#define | SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)
#define | SCB_CCR_STKALIGN ((uint16_t)0x0200)
#define | SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)
#define | SCB_CCR_USERSETMPEND ((uint16_t)0x0002)
#define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000)
#define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)
#define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)
#define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)
#define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100)
#define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)
#define | SCB_CFSR_INVPC ((uint32_t)0x00040000)
#define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000)
#define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080)
#define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010)
#define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)
#define | SCB_CFSR_NOCP ((uint32_t)0x00080000)
#define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200)
#define | SCB_CFSR_STKERR ((uint32_t)0x00001000)
#define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)
#define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)
#define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)
#define | SCB_CPUID_Constant ((uint32_t)0x000F0000)
#define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)
#define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)
#define | SCB_CPUID_REVISION ((uint32_t)0x0000000F)
#define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000)
#define | SCB_DFSR_BKPT ((uint8_t)0x02)
#define | SCB_DFSR_DWTTRAP ((uint8_t)0x04)
#define | SCB_DFSR_EXTERNAL ((uint8_t)0x10)
#define | SCB_DFSR_HALTED ((uint8_t)0x01)
#define | SCB_DFSR_VCATCH ((uint8_t)0x08)
#define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)
#define | SCB_HFSR_FORCED ((uint32_t)0x40000000)
#define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002)
#define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
#define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)
#define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
#define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
#define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
#define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
#define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
#define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)
#define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)
#define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)
#define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
#define | SCB_SCR_SEVONPEND ((uint8_t)0x10)
#define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
#define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
#define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)
#define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)
#define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)
#define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)
#define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)
#define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)
#define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)
#define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)
#define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)
#define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)
#define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)
#define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)
#define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)
#define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)
#define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF)
#define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)
#define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)
#define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)
#define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000)
#define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)
#define | SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)
#define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
#define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400)
#define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)
#define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100)
#define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)
#define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)
#define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)
#define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)
#define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)
#define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)
#define | SDIO_CMD_CEATACMD ((uint16_t)0x4000)
#define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F)
#define | SDIO_CMD_CPSMEN ((uint16_t)0x0400)
#define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)
#define | SDIO_CMD_NIEN ((uint16_t)0x2000)
#define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
#define | SDIO_CMD_WAITINT ((uint16_t)0x0100)
#define | SDIO_CMD_WAITPEND ((uint16_t)0x0200)
#define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0)
#define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)
#define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)
#define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)
#define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)
#define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)
#define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)
#define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)
#define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)
#define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008)
#define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002)
#define | SDIO_DCTRL_DTEN ((uint16_t)0x0001)
#define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004)
#define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400)
#define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100)
#define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)
#define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)
#define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)
#define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)
#define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
#define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)
#define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)
#define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)
#define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)
#define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)
#define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)
#define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100)
#define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)
#define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)
#define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)
#define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)
#define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
#define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200)
#define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)
#define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)
#define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)
#define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)
#define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)
#define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)
#define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)
#define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)
#define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)
#define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)
#define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)
#define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000)
#define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)
#define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)
#define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)
#define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)
#define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)
#define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)
#define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)
#define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000)
#define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)
#define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)
#define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)
#define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)
#define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)
#define | SDIO_POWER_PWRCTRL ((uint8_t)0x03)
#define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)
#define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)
#define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)
#define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_STA_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_STA_CMDACT ((uint32_t)0x00000800)
#define | SDIO_STA_CMDREND ((uint32_t)0x00000040)
#define | SDIO_STA_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_STA_DATAEND ((uint32_t)0x00000100)
#define | SDIO_STA_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_STA_RXACT ((uint32_t)0x00002000)
#define | SDIO_STA_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_STA_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_STA_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_STA_STBITERR ((uint32_t)0x00000200)
#define | SDIO_STA_TXACT ((uint32_t)0x00001000)
#define | SDIO_STA_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010)
#define | SET_BIT(REG, BIT) ((REG) |= (BIT))
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define | SPI_CR1_BIDIMODE ((uint16_t)0x8000)
#define | SPI_CR1_BIDIOE ((uint16_t)0x4000)
#define | SPI_CR1_BR ((uint16_t)0x0038)
#define | SPI_CR1_BR_0 ((uint16_t)0x0008)
#define | SPI_CR1_BR_1 ((uint16_t)0x0010)
#define | SPI_CR1_BR_2 ((uint16_t)0x0020)
#define | SPI_CR1_CPHA ((uint16_t)0x0001)
#define | SPI_CR1_CPOL ((uint16_t)0x0002)
#define | SPI_CR1_CRCEN ((uint16_t)0x2000)
#define | SPI_CR1_CRCNEXT ((uint16_t)0x1000)
#define | SPI_CR1_DFF ((uint16_t)0x0800)
#define | SPI_CR1_LSBFIRST ((uint16_t)0x0080)
#define | SPI_CR1_MSTR ((uint16_t)0x0004)
#define | SPI_CR1_RXONLY ((uint16_t)0x0400)
#define | SPI_CR1_SPE ((uint16_t)0x0040)
#define | SPI_CR1_SSI ((uint16_t)0x0100)
#define | SPI_CR1_SSM ((uint16_t)0x0200)
#define | SPI_CR2_ERRIE ((uint8_t)0x20)
#define | SPI_CR2_FRF ((uint8_t)0x08)
#define | SPI_CR2_RXDMAEN ((uint8_t)0x01)
#define | SPI_CR2_RXNEIE ((uint8_t)0x40)
#define | SPI_CR2_SSOE ((uint8_t)0x04)
#define | SPI_CR2_TXDMAEN ((uint8_t)0x02)
#define | SPI_CR2_TXEIE ((uint8_t)0x80)
#define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)
#define | SPI_DR_DR ((uint16_t)0xFFFF)
#define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)
#define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)
#define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)
#define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)
#define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)
#define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)
#define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)
#define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
#define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400)
#define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)
#define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)
#define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)
#define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)
#define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)
#define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)
#define | SPI_I2SPR_MCKOE ((uint16_t)0x0200)
#define | SPI_I2SPR_ODD ((uint16_t)0x0100)
#define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CHSIDE ((uint8_t)0x04)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_UDR ((uint8_t)0x08)
#define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | SRAM_BB_BASE ((uint32_t)0x22000000)
#define | STM32L1XX_HD
#define | SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define | SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
#define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F)
#define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
EXTI0 configuration.
#define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
#define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
#define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
#define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
#define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006)
#define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007)
#define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005)
#define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0)
#define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
EXTI1 configuration.
#define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
#define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
#define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
#define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
#define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060)
#define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070)
#define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050)
#define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00)
#define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
EXTI2 configuration.
#define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
#define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
#define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
#define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
#define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600)
#define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700)
#define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500)
#define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000)
#define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
EXTI3 configuration.
#define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
#define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
#define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
#define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
#define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000)
#define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000)
#define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F)
#define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
EXTI4 configuration.
#define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
#define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
#define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
#define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
#define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006)
#define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007)
#define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0)
#define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
EXTI5 configuration.
#define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
#define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
#define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
#define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
#define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060)
#define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070)
#define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00)
#define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
EXTI6 configuration.
#define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
#define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
#define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
#define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
#define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600)
#define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700)
#define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000)
#define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
EXTI7 configuration.
#define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
#define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
#define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
#define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
#define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000)
#define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000)
#define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00)
#define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
EXTI10 configuration.
#define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
#define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
#define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
#define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
#define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600)
#define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700)
#define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000)
#define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
EXTI11 configuration.
#define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
#define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
#define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
#define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
#define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000)
#define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000)
#define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F)
#define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
EXTI8 configuration.
#define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
#define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
#define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
#define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
#define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006)
#define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007)
#define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0)
#define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
EXTI9 configuration.
#define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
#define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
#define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
#define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
#define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060)
#define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070)
#define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F)
#define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
EXTI12 configuration.
#define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
#define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
#define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
#define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
#define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006)
#define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007)
#define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0)
#define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
EXTI13 configuration.
#define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
#define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
#define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
#define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
#define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060)
#define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070)
#define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00)
#define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
EXTI14 configuration.
#define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
#define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
#define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
#define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
#define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600)
#define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700)
#define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)
#define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
EXTI15 configuration.
#define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
#define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
#define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
#define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
#define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000)
#define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000)
#define | SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300)
#define | SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100)
#define | SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200)
#define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003)
#define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
#define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
#define | SYSCFG_PMC_USB_PU ((uint32_t)0x00000001)
#define | SysTick_CALIB_NOREF ((uint32_t)0x80000000)
#define | SysTick_CALIB_SKEW ((uint32_t)0x40000000)
#define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)
#define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)
#define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)
#define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001)
#define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002)
#define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)
#define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)
#define | TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define | TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
#define | TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define | TIM11_BASE (APB2PERIPH_BASE + 0x1000)
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define | TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define | TIM9_BASE (APB2PERIPH_BASE + 0x0800)
#define | TIM_ARR_ARR ((uint16_t)0xFFFF)
#define | TIM_CCER_CC1E ((uint16_t)0x0001)
#define | TIM_CCER_CC1NP ((uint16_t)0x0008)
#define | TIM_CCER_CC1P ((uint16_t)0x0002)
#define | TIM_CCER_CC2E ((uint16_t)0x0010)
#define | TIM_CCER_CC2NP ((uint16_t)0x0080)
#define | TIM_CCER_CC2P ((uint16_t)0x0020)
#define | TIM_CCER_CC3E ((uint16_t)0x0100)
#define | TIM_CCER_CC3NP ((uint16_t)0x0800)
#define | TIM_CCER_CC3P ((uint16_t)0x0200)
#define | TIM_CCER_CC4E ((uint16_t)0x1000)
#define | TIM_CCER_CC4NP ((uint16_t)0x8000)
#define | TIM_CCER_CC4P ((uint16_t)0x2000)
#define | TIM_CCMR1_CC1S ((uint16_t)0x0003)
#define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
#define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
#define | TIM_CCMR1_CC2S ((uint16_t)0x0300)
#define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
#define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
#define | TIM_CCMR1_IC1F ((uint16_t)0x00F0)
#define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
#define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
#define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
#define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
#define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
#define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
#define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
#define | TIM_CCMR1_IC2F ((uint16_t)0xF000)
#define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
#define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
#define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
#define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
#define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
#define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
#define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
#define | TIM_CCMR1_OC1CE ((uint16_t)0x0080)
#define | TIM_CCMR1_OC1FE ((uint16_t)0x0004)
#define | TIM_CCMR1_OC1M ((uint16_t)0x0070)
#define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
#define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
#define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
#define | TIM_CCMR1_OC1PE ((uint16_t)0x0008)
#define | TIM_CCMR1_OC2CE ((uint16_t)0x8000)
#define | TIM_CCMR1_OC2FE ((uint16_t)0x0400)
#define | TIM_CCMR1_OC2M ((uint16_t)0x7000)
#define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
#define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
#define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
#define | TIM_CCMR1_OC2PE ((uint16_t)0x0800)
#define | TIM_CCMR2_CC3S ((uint16_t)0x0003)
#define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
#define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
#define | TIM_CCMR2_CC4S ((uint16_t)0x0300)
#define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
#define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
#define | TIM_CCMR2_IC3F ((uint16_t)0x00F0)
#define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
#define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
#define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
#define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
#define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
#define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
#define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
#define | TIM_CCMR2_IC4F ((uint16_t)0xF000)
#define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
#define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
#define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
#define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
#define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
#define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
#define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
#define | TIM_CCMR2_OC3CE ((uint16_t)0x0080)
#define | TIM_CCMR2_OC3FE ((uint16_t)0x0004)
#define | TIM_CCMR2_OC3M ((uint16_t)0x0070)
#define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
#define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
#define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
#define | TIM_CCMR2_OC3PE ((uint16_t)0x0008)
#define | TIM_CCMR2_OC4CE ((uint16_t)0x8000)
#define | TIM_CCMR2_OC4FE ((uint16_t)0x0400)
#define | TIM_CCMR2_OC4M ((uint16_t)0x7000)
#define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
#define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
#define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
#define | TIM_CCMR2_OC4PE ((uint16_t)0x0800)
#define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
#define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
#define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
#define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
#define | TIM_CNT_CNT ((uint16_t)0xFFFF)
#define | TIM_CR1_ARPE ((uint16_t)0x0080)
#define | TIM_CR1_CEN ((uint16_t)0x0001)
#define | TIM_CR1_CKD ((uint16_t)0x0300)
#define | TIM_CR1_CKD_0 ((uint16_t)0x0100)
#define | TIM_CR1_CKD_1 ((uint16_t)0x0200)
#define | TIM_CR1_CMS ((uint16_t)0x0060)
#define | TIM_CR1_CMS_0 ((uint16_t)0x0020)
#define | TIM_CR1_CMS_1 ((uint16_t)0x0040)
#define | TIM_CR1_DIR ((uint16_t)0x0010)
#define | TIM_CR1_OPM ((uint16_t)0x0008)
#define | TIM_CR1_UDIS ((uint16_t)0x0002)
#define | TIM_CR1_URS ((uint16_t)0x0004)
#define | TIM_CR2_CCDS ((uint16_t)0x0008)
#define | TIM_CR2_MMS ((uint16_t)0x0070)
#define | TIM_CR2_MMS_0 ((uint16_t)0x0010)
#define | TIM_CR2_MMS_1 ((uint16_t)0x0020)
#define | TIM_CR2_MMS_2 ((uint16_t)0x0040)
#define | TIM_CR2_TI1S ((uint16_t)0x0080)
#define | TIM_DCR_DBA ((uint16_t)0x001F)
#define | TIM_DCR_DBA_0 ((uint16_t)0x0001)
#define | TIM_DCR_DBA_1 ((uint16_t)0x0002)
#define | TIM_DCR_DBA_2 ((uint16_t)0x0004)
#define | TIM_DCR_DBA_3 ((uint16_t)0x0008)
#define | TIM_DCR_DBA_4 ((uint16_t)0x0010)
#define | TIM_DCR_DBL ((uint16_t)0x1F00)
#define | TIM_DCR_DBL_0 ((uint16_t)0x0100)
#define | TIM_DCR_DBL_1 ((uint16_t)0x0200)
#define | TIM_DCR_DBL_2 ((uint16_t)0x0400)
#define | TIM_DCR_DBL_3 ((uint16_t)0x0800)
#define | TIM_DCR_DBL_4 ((uint16_t)0x1000)
#define | TIM_DIER_CC1DE ((uint16_t)0x0200)
#define | TIM_DIER_CC1IE ((uint16_t)0x0002)
#define | TIM_DIER_CC2DE ((uint16_t)0x0400)
#define | TIM_DIER_CC2IE ((uint16_t)0x0004)
#define | TIM_DIER_CC3DE ((uint16_t)0x0800)
#define | TIM_DIER_CC3IE ((uint16_t)0x0008)
#define | TIM_DIER_CC4DE ((uint16_t)0x1000)
#define | TIM_DIER_CC4IE ((uint16_t)0x0010)
#define | TIM_DIER_TDE ((uint16_t)0x4000)
#define | TIM_DIER_TIE ((uint16_t)0x0040)
#define | TIM_DIER_UDE ((uint16_t)0x0100)
#define | TIM_DIER_UIE ((uint16_t)0x0001)
#define | TIM_DMAR_DMAB ((uint16_t)0xFFFF)
#define | TIM_EGR_CC1G ((uint8_t)0x02)
#define | TIM_EGR_CC2G ((uint8_t)0x04)
#define | TIM_EGR_CC3G ((uint8_t)0x08)
#define | TIM_EGR_CC4G ((uint8_t)0x10)
#define | TIM_EGR_TG ((uint8_t)0x40)
#define | TIM_EGR_UG ((uint8_t)0x01)
#define | TIM_OR_TI1RMP ((uint16_t)0x0003)
#define | TIM_OR_TI1RMP_0 ((uint16_t)0x0001)
#define | TIM_OR_TI1RMP_1 ((uint16_t)0x0002)
#define | TIM_PSC_PSC ((uint16_t)0xFFFF)
#define | TIM_SMCR_ECE ((uint16_t)0x4000)
#define | TIM_SMCR_ETF ((uint16_t)0x0F00)
#define | TIM_SMCR_ETF_0 ((uint16_t)0x0100)
#define | TIM_SMCR_ETF_1 ((uint16_t)0x0200)
#define | TIM_SMCR_ETF_2 ((uint16_t)0x0400)
#define | TIM_SMCR_ETF_3 ((uint16_t)0x0800)
#define | TIM_SMCR_ETP ((uint16_t)0x8000)
#define | TIM_SMCR_ETPS ((uint16_t)0x3000)
#define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
#define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
#define | TIM_SMCR_MSM ((uint16_t)0x0080)
#define | TIM_SMCR_OCCS ((uint16_t)0x0008)
#define | TIM_SMCR_SMS ((uint16_t)0x0007)
#define | TIM_SMCR_SMS_0 ((uint16_t)0x0001)
#define | TIM_SMCR_SMS_1 ((uint16_t)0x0002)
#define | TIM_SMCR_SMS_2 ((uint16_t)0x0004)
#define | TIM_SMCR_TS ((uint16_t)0x0070)
#define | TIM_SMCR_TS_0 ((uint16_t)0x0010)
#define | TIM_SMCR_TS_1 ((uint16_t)0x0020)
#define | TIM_SMCR_TS_2 ((uint16_t)0x0040)
#define | TIM_SR_CC1IF ((uint16_t)0x0002)
#define | TIM_SR_CC1OF ((uint16_t)0x0200)
#define | TIM_SR_CC2IF ((uint16_t)0x0004)
#define | TIM_SR_CC2OF ((uint16_t)0x0400)
#define | TIM_SR_CC3IF ((uint16_t)0x0008)
#define | TIM_SR_CC3OF ((uint16_t)0x0800)
#define | TIM_SR_CC4IF ((uint16_t)0x0010)
#define | TIM_SR_CC4OF ((uint16_t)0x1000)
#define | TIM_SR_TIF ((uint16_t)0x0040)
#define | TIM_SR_UIF ((uint16_t)0x0001)
#define | UART4 ((USART_TypeDef *) UART4_BASE)
#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define | UART5 ((USART_TypeDef *) UART5_BASE)
#define | UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define | USART1 ((USART_TypeDef *) USART1_BASE)
#define | USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define | USART2 ((USART_TypeDef *) USART2_BASE)
#define | USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define | USART3 ((USART_TypeDef *) USART3_BASE)
#define | USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define | USART_BRR_DIV_FRACTION ((uint16_t)0x000F)
#define | USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0)
#define | USART_CR1_IDLEIE ((uint16_t)0x0010)
#define | USART_CR1_M ((uint16_t)0x1000)
#define | USART_CR1_OVER8 ((uint16_t)0x8000)
#define | USART_CR1_PCE ((uint16_t)0x0400)
#define | USART_CR1_PEIE ((uint16_t)0x0100)
#define | USART_CR1_PS ((uint16_t)0x0200)
#define | USART_CR1_RE ((uint16_t)0x0004)
#define | USART_CR1_RWU ((uint16_t)0x0002)
#define | USART_CR1_RXNEIE ((uint16_t)0x0020)
#define | USART_CR1_SBK ((uint16_t)0x0001)
#define | USART_CR1_TCIE ((uint16_t)0x0040)
#define | USART_CR1_TE ((uint16_t)0x0008)
#define | USART_CR1_TXEIE ((uint16_t)0x0080)
#define | USART_CR1_UE ((uint16_t)0x2000)
#define | USART_CR1_WAKE ((uint16_t)0x0800)
#define | USART_CR2_ADD ((uint16_t)0x000F)
#define | USART_CR2_CLKEN ((uint16_t)0x0800)
#define | USART_CR2_CPHA ((uint16_t)0x0200)
#define | USART_CR2_CPOL ((uint16_t)0x0400)
#define | USART_CR2_LBCL ((uint16_t)0x0100)
#define | USART_CR2_LBDIE ((uint16_t)0x0040)
#define | USART_CR2_LBDL ((uint16_t)0x0020)
#define | USART_CR2_LINEN ((uint16_t)0x4000)
#define | USART_CR2_STOP ((uint16_t)0x3000)
#define | USART_CR2_STOP_0 ((uint16_t)0x1000)
#define | USART_CR2_STOP_1 ((uint16_t)0x2000)
#define | USART_CR3_CTSE ((uint16_t)0x0200)
#define | USART_CR3_CTSIE ((uint16_t)0x0400)
#define | USART_CR3_DMAR ((uint16_t)0x0040)
#define | USART_CR3_DMAT ((uint16_t)0x0080)
#define | USART_CR3_EIE ((uint16_t)0x0001)
#define | USART_CR3_HDSEL ((uint16_t)0x0008)
#define | USART_CR3_IREN ((uint16_t)0x0002)
#define | USART_CR3_IRLP ((uint16_t)0x0004)
#define | USART_CR3_NACK ((uint16_t)0x0010)
#define | USART_CR3_ONEBIT ((uint16_t)0x0800)
#define | USART_CR3_RTSE ((uint16_t)0x0100)
#define | USART_CR3_SCEN ((uint16_t)0x0020)
#define | USART_DR_DR ((uint16_t)0x01FF)
#define | USART_GTPR_GT ((uint16_t)0xFF00)
#define | USART_GTPR_PSC ((uint16_t)0x00FF)
#define | USART_GTPR_PSC_0 ((uint16_t)0x0001)
#define | USART_GTPR_PSC_1 ((uint16_t)0x0002)
#define | USART_GTPR_PSC_2 ((uint16_t)0x0004)
#define | USART_GTPR_PSC_3 ((uint16_t)0x0008)
#define | USART_GTPR_PSC_4 ((uint16_t)0x0010)
#define | USART_GTPR_PSC_5 ((uint16_t)0x0020)
#define | USART_GTPR_PSC_6 ((uint16_t)0x0040)
#define | USART_GTPR_PSC_7 ((uint16_t)0x0080)
#define | USART_SR_CTS ((uint16_t)0x0200)
#define | USART_SR_FE ((uint16_t)0x0002)
#define | USART_SR_IDLE ((uint16_t)0x0010)
#define | USART_SR_LBD ((uint16_t)0x0100)
#define | USART_SR_NE ((uint16_t)0x0004)
#define | USART_SR_ORE ((uint16_t)0x0008)
#define | USART_SR_PE ((uint16_t)0x0001)
#define | USART_SR_RXNE ((uint16_t)0x0020)
#define | USART_SR_TC ((uint16_t)0x0040)
#define | USART_SR_TXE ((uint16_t)0x0080)
#define | USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)
#define | USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)
#define | USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)
#define | USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)
#define | USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)
#define | USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)
#define | USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)
#define | USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)
#define | USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)
#define | USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)
#define | USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)
#define | USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)
#define | USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)
#define | USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)
#define | USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)
#define | USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)
#define | USB_BTABLE_BTABLE ((uint16_t)0xFFF8)
#define | USB_CNTR_CTRM ((uint16_t)0x8000)
#define | USB_CNTR_ERRM ((uint16_t)0x2000)
#define | USB_CNTR_ESOFM ((uint16_t)0x0100)
#define | USB_CNTR_FRES ((uint16_t)0x0001)
#define | USB_CNTR_FSUSP ((uint16_t)0x0008)
#define | USB_CNTR_LP_MODE ((uint16_t)0x0004)
#define | USB_CNTR_PDWN ((uint16_t)0x0002)
#define | USB_CNTR_PMAOVRM ((uint16_t)0x4000)
#define | USB_CNTR_RESETM ((uint16_t)0x0400)
#define | USB_CNTR_RESUME ((uint16_t)0x0010)
#define | USB_CNTR_SOFM ((uint16_t)0x0200)
#define | USB_CNTR_SUSPM ((uint16_t)0x0800)
#define | USB_CNTR_WKUPM ((uint16_t)0x1000)
#define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)
#define | USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)
#define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)
#define | USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)
#define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)
#define | USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)
#define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)
#define | USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)
#define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)
#define | USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)
#define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)
#define | USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)
#define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)
#define | USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)
#define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)
#define | USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)
#define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)
#define | USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)
#define | USB_DADDR_ADD ((uint8_t)0x7F)
#define | USB_DADDR_ADD0 ((uint8_t)0x01)
#define | USB_DADDR_ADD1 ((uint8_t)0x02)
#define | USB_DADDR_ADD2 ((uint8_t)0x04)
#define | USB_DADDR_ADD3 ((uint8_t)0x08)
#define | USB_DADDR_ADD4 ((uint8_t)0x10)
#define | USB_DADDR_ADD5 ((uint8_t)0x20)
#define | USB_DADDR_ADD6 ((uint8_t)0x40)
#define | USB_DADDR_EF ((uint8_t)0x80)
#define | USB_EP0R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP0R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP0R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP0R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP0R_EA ((uint16_t)0x000F)
#define | USB_EP0R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP0R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP0R_SETUP ((uint16_t)0x0800)
#define | USB_EP0R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP0R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP1R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP1R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP1R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP1R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP1R_EA ((uint16_t)0x000F)
#define | USB_EP1R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP1R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP1R_SETUP ((uint16_t)0x0800)
#define | USB_EP1R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP1R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP2R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP2R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP2R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP2R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP2R_EA ((uint16_t)0x000F)
#define | USB_EP2R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP2R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP2R_SETUP ((uint16_t)0x0800)
#define | USB_EP2R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP2R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP3R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP3R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP3R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP3R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP3R_EA ((uint16_t)0x000F)
#define | USB_EP3R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP3R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP3R_SETUP ((uint16_t)0x0800)
#define | USB_EP3R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP3R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP4R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP4R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP4R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP4R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP4R_EA ((uint16_t)0x000F)
#define | USB_EP4R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP4R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP4R_SETUP ((uint16_t)0x0800)
#define | USB_EP4R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP4R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP5R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP5R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP5R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP5R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP5R_EA ((uint16_t)0x000F)
#define | USB_EP5R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP5R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP5R_SETUP ((uint16_t)0x0800)
#define | USB_EP5R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP5R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP6R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP6R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP6R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP6R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP6R_EA ((uint16_t)0x000F)
#define | USB_EP6R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP6R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP6R_SETUP ((uint16_t)0x0800)
#define | USB_EP6R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP6R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP7R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP7R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP7R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP7R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP7R_EA ((uint16_t)0x000F)
#define | USB_EP7R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP7R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP7R_SETUP ((uint16_t)0x0800)
#define | USB_EP7R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP7R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_FNR_FN ((uint16_t)0x07FF)
#define | USB_FNR_LCK ((uint16_t)0x2000)
#define | USB_FNR_LSOF ((uint16_t)0x1800)
#define | USB_FNR_RXDM ((uint16_t)0x4000)
#define | USB_FNR_RXDP ((uint16_t)0x8000)
#define | USB_ISTR_CTR ((uint16_t)0x8000)
#define | USB_ISTR_DIR ((uint16_t)0x0010)
#define | USB_ISTR_EP_ID ((uint16_t)0x000F)
#define | USB_ISTR_ERR ((uint16_t)0x2000)
#define | USB_ISTR_ESOF ((uint16_t)0x0100)
#define | USB_ISTR_PMAOVR ((uint16_t)0x4000)
#define | USB_ISTR_RESET ((uint16_t)0x0400)
#define | USB_ISTR_SOF ((uint16_t)0x0200)
#define | USB_ISTR_SUSP ((uint16_t)0x0800)
#define | USB_ISTR_WKUP ((uint16_t)0x1000)
#define | WRITE_REG(REG, VAL) ((REG) = (VAL))
#define | WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define | WWDG_CFR_EWI ((uint16_t)0x0200)
#define | WWDG_CFR_W ((uint16_t)0x007F)
#define | WWDG_CFR_W0 ((uint16_t)0x0001)
#define | WWDG_CFR_W1 ((uint16_t)0x0002)
#define | WWDG_CFR_W2 ((uint16_t)0x0004)
#define | WWDG_CFR_W3 ((uint16_t)0x0008)
#define | WWDG_CFR_W4 ((uint16_t)0x0010)
#define | WWDG_CFR_W5 ((uint16_t)0x0020)
#define | WWDG_CFR_W6 ((uint16_t)0x0040)
#define | WWDG_CFR_WDGTB ((uint16_t)0x0180)
#define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
#define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T0 ((uint8_t)0x01)
#define | WWDG_CR_T1 ((uint8_t)0x02)
#define | WWDG_CR_T2 ((uint8_t)0x04)
#define | WWDG_CR_T3 ((uint8_t)0x08)
#define | WWDG_CR_T4 ((uint8_t)0x10)
#define | WWDG_CR_T5 ((uint8_t)0x20)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_SR_EWIF ((uint8_t)0x01)

Typedefs

typedef enum IRQn | IRQn_Type
typedef enum FlagStatus | ITStatus

Enumerations

enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }
enum IRQn {
NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
SVC_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3,
FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,
EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,
DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,
DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_IRQn = 18, USB_HP_IRQn = 19,
USB_LP_IRQn = 20, DAC_IRQn = 21, COMP_IRQn = 22, EXTI9_5_IRQn = 23,
LCD_IRQn = 24, TIM9_IRQn = 25, TIM10_IRQn = 26, TIM11_IRQn = 27,
TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35,
SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39,
EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, USB_FS_WKUP_IRQn = 42, TIM6_IRQn = 43,
TIM7_IRQn = 44, SDIO_IRQn = 45, TIM5_IRQn = 46, SPI3_IRQn = 47,
UART4_IRQn = 48, UART5_IRQn = 49, DMA2_Channel1_IRQn = 50, DMA2_Channel2_IRQn = 51,
DMA2_Channel3_IRQn = 52, DMA2_Channel4_IRQn = 53, DMA2_Channel5_IRQn = 54, AES_IRQn = 55,
COMP_ACQ_IRQn = 56
}

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32L1xx High-, Medium-density and Medium-density Plus devices.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012 The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:
  • Configuration section that allows to select:
    • The device used in the target application
    • To use or not the peripheral’s drivers in application code(i.e. code will be based on direct access to peripheral’s registers rather than drivers API), this option is controlled by "#define USE_STDPERIPH_DRIVER"
    • To change few application-specific parameters such as the HSE crystal frequency
  • Data structures and the address mapping for all peripherals
  • Peripheral's registers declarations and bits definition
  • Macros to access peripheral’s registers hardware
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_adc.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and Configuration + Power saving + Analog Watchdog configuration + Temperature Sensor & Vrefint (Voltage Reference internal) management + Regular Channels Configuration + Regular Channels DMA Configuration + Injected channels Configuration + Interrupts and flags management. More...

#include "stm32l1xx_adc.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
#define | CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
#define | CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
#define | CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
#define | CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
#define | CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)
#define | CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
#define | CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
#define | CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF)
#define | JDR_OFFSET ((uint8_t)0x30)
#define | JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
#define | JSQR_JL_SET ((uint32_t)0x00300000)
#define | JSQR_JSQ_SET ((uint32_t)0x0000001F)
#define | SMPR0_SMP_SET ((uint32_t)0x00000007)
#define | SMPR1_SMP_SET ((uint32_t)0x00000007)
#define | SMPR2_SMP_SET ((uint32_t)0x00000007)
#define | SMPR3_SMP_SET ((uint32_t)0x00000007)
#define | SQR1_L_RESET ((uint32_t)0xFE0FFFFF)
#define | SQR1_SQ_SET ((uint32_t)0x0000001F)
#define | SQR2_SQ_SET ((uint32_t)0x0000001F)
#define | SQR3_SQ_SET ((uint32_t)0x0000001F)
#define | SQR4_SQ_SET ((uint32_t)0x0000001F)
#define | SQR5_SQ_SET ((uint32_t)0x0000001F)

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_BankSelection (ADC_TypeDef *ADCx, uint8_t ADC_Bank)
Selects the specified ADC Channels Bank.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
void | ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
void | ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes ADC1 peripheral registers to their default reset values.
void | ADC_DelaySelectionConfig (ADC_TypeDef *ADCx, uint8_t ADC_DelayLength)
Defines the length of the delay which is applied after a conversion or a sequence of conversion.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode).
void | ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
void | ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_PowerDownCmd (ADC_TypeDef *ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
Enables or disables the ADC Power Down during Delay and/or Idle phase.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.
void | ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and Configuration + Power saving + Analog Watchdog configuration + Temperature Sensor & Vrefint (Voltage Reference internal) management + Regular Channels Configuration + Regular Channels DMA Configuration + Injected channels Configuration + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
================================================================================
                      ##### How to use this driver #####
================================================================================
    [..]
    (#) Configure the ADC Prescaler, conversion resolution and data alignment
        using the ADC_Init() function.
    (#) Activate the ADC peripheral using ADC_Cmd() function.

    *** Regular channels group configuration ***
    ============================================
    [..]
    (+) To configure the ADC regular channels group features, use
        ADC_Init() and ADC_RegularChannelConfig() functions.
    (+) To activate the continuous mode, use the ADC_continuousModeCmd()
        function.
    (+) To configurate and activate the Discontinuous mode, use the
        ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
    (+) To read the ADC converted values, use the ADC_GetConversionValue()
        function.

    *** DMA for Regular channels group features configuration ***
    =============================================================
    [..]
    (+) To enable the DMA mode for regular channels group, use the
               ADC_DMACmd() function.
    (+) To enable the generation of DMA requests continuously at the end
               of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
               function.

    *** Injected channels group configuration ***
    =============================================
    [..]
    (+) To configure the ADC Injected channels group features, use
        ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
        functions.
    (+) To activate the continuous mode, use the ADC_continuousModeCmd()
        function.
    (+) To activate the Injected Discontinuous mode, use the
        ADC_InjectedDiscModeCmd() function.
    (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
        function.
    (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
        function.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_adc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_adc.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_adc.h File Reference

This file contains all the functions prototypes for the ADC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | ADC_CommonInitTypeDef
struct | ADC_InitTypeDef
ADC Init structure definition. More...

Defines

#define | ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define | ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define | ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define | ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define | ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define | ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define | ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define | ADC_Bank_A ((uint8_t)0x00)
#define | ADC_Bank_B ((uint8_t)0x01)
#define | ADC_Channel_0 ((uint8_t)0x00)
#define | ADC_Channel_0b ADC_Channel_0
#define | ADC_Channel_1 ((uint8_t)0x01)
#define | ADC_Channel_10 ((uint8_t)0x0A)
#define | ADC_Channel_10b ADC_Channel_10
#define | ADC_Channel_11 ((uint8_t)0x0B)
#define | ADC_Channel_11b ADC_Channel_11
#define | ADC_Channel_12 ((uint8_t)0x0C)
#define | ADC_Channel_12b ADC_Channel_12
#define | ADC_Channel_13 ((uint8_t)0x0D)
#define | ADC_Channel_14 ((uint8_t)0x0E)
#define | ADC_Channel_15 ((uint8_t)0x0F)
#define | ADC_Channel_16 ((uint8_t)0x10)
#define | ADC_Channel_17 ((uint8_t)0x11)
#define | ADC_Channel_18 ((uint8_t)0x12)
#define | ADC_Channel_19 ((uint8_t)0x13)
#define | ADC_Channel_1b ADC_Channel_1
#define | ADC_Channel_2 ((uint8_t)0x02)
#define | ADC_Channel_20 ((uint8_t)0x14)
#define | ADC_Channel_21 ((uint8_t)0x15)
#define | ADC_Channel_22 ((uint8_t)0x16)
#define | ADC_Channel_23 ((uint8_t)0x17)
#define | ADC_Channel_24 ((uint8_t)0x18)
#define | ADC_Channel_25 ((uint8_t)0x19)
#define | ADC_Channel_27 ((uint8_t)0x1B)
#define | ADC_Channel_28 ((uint8_t)0x1C)
#define | ADC_Channel_29 ((uint8_t)0x1D)
#define | ADC_Channel_2b ADC_Channel_2
#define | ADC_Channel_3 ((uint8_t)0x03)
#define | ADC_Channel_30 ((uint8_t)0x1E)
#define | ADC_Channel_31 ((uint8_t)0x1F)
#define | ADC_Channel_3b ADC_Channel_3
#define | ADC_Channel_4 ((uint8_t)0x04)
#define | ADC_Channel_5 ((uint8_t)0x05)
#define | ADC_Channel_6 ((uint8_t)0x06)
#define | ADC_Channel_6b ADC_Channel_6
#define | ADC_Channel_7 ((uint8_t)0x07)
#define | ADC_Channel_7b ADC_Channel_7
#define | ADC_Channel_8 ((uint8_t)0x08)
#define | ADC_Channel_8b ADC_Channel_8
#define | ADC_Channel_9 ((uint8_t)0x09)
#define | ADC_Channel_9b ADC_Channel_9
#define | ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define | ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define | ADC_DataAlign_Left ((uint32_t)0x00000800)
#define | ADC_DataAlign_Right ((uint32_t)0x00000000)
#define | ADC_DelayLength_127Cycles ((uint8_t)0x60)
#define | ADC_DelayLength_15Cycles ((uint8_t)0x30)
#define | ADC_DelayLength_255Cycles ((uint8_t)0x70)
#define | ADC_DelayLength_31Cycles ((uint8_t)0x40)
#define | ADC_DelayLength_63Cycles ((uint8_t)0x50)
#define | ADC_DelayLength_7Cycles ((uint8_t)0x20)
#define | ADC_DelayLength_Freeze ((uint8_t)0x10)
#define | ADC_DelayLength_None ((uint8_t)0x00)
#define | ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
#define | ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
#define | ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
#define | ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
#define | ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
#define | ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
#define | ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
#define | ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
#define | ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
#define | ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
#define | ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
#define | ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
#define | ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
#define | ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
#define | ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
#define | ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
#define | ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
#define | ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
#define | ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
#define | ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
#define | ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
#define | ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
#define | ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
#define | ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define | ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define | ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define | ADC_FLAG_ADONS ((uint16_t)0x0040)
#define | ADC_FLAG_AWD ((uint16_t)0x0001)
#define | ADC_FLAG_EOC ((uint16_t)0x0002)
#define | ADC_FLAG_JCNR ((uint16_t)0x0200)
#define | ADC_FLAG_JEOC ((uint16_t)0x0004)
#define | ADC_FLAG_JSTRT ((uint16_t)0x0008)
#define | ADC_FLAG_OVR ((uint16_t)0x0020)
#define | ADC_FLAG_RCNR ((uint16_t)0x0100)
#define | ADC_FLAG_STRT ((uint16_t)0x0010)
#define | ADC_InjectedChannel_1 ((uint8_t)0x18)
#define | ADC_InjectedChannel_2 ((uint8_t)0x1C)
#define | ADC_InjectedChannel_3 ((uint8_t)0x20)
#define | ADC_InjectedChannel_4 ((uint8_t)0x24)
#define | ADC_IT_AWD ((uint16_t)0x0106)
#define | ADC_IT_EOC ((uint16_t)0x0205)
#define | ADC_IT_JEOC ((uint16_t)0x0407)
#define | ADC_IT_OVR ((uint16_t)0x201A)
#define | ADC_PowerDown_Delay ((uint32_t)0x00010000)
#define | ADC_PowerDown_Idle ((uint32_t)0x00020000)
#define | ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
#define | ADC_Prescaler_Div1 ((uint32_t)0x00000000)
#define | ADC_Prescaler_Div2 ((uint32_t)0x00010000)
#define | ADC_Prescaler_Div4 ((uint32_t)0x00020000)
#define | ADC_Resolution_10b ((uint32_t)0x01000000)
#define | ADC_Resolution_12b ((uint32_t)0x00000000)
#define | ADC_Resolution_6b ((uint32_t)0x03000000)
#define | ADC_Resolution_8b ((uint32_t)0x02000000)
#define | ADC_SampleTime_16Cycles ((uint8_t)0x02)
#define | ADC_SampleTime_192Cycles ((uint8_t)0x06)
#define | ADC_SampleTime_24Cycles ((uint8_t)0x03)
#define | ADC_SampleTime_384Cycles ((uint8_t)0x07)
#define | ADC_SampleTime_48Cycles ((uint8_t)0x04)
#define | ADC_SampleTime_4Cycles ((uint8_t)0x00)
#define | ADC_SampleTime_96Cycles ((uint8_t)0x05)
#define | ADC_SampleTime_9Cycles ((uint8_t)0x01)
#define | IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define | IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_DELAY_LENGTH(LENGTH)
#define | IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
#define | IS_ADC_EXT_TRIG(REGTRIG)
#define | IS_ADC_EXT_TRIG_EDGE(EDGE)
#define | IS_ADC_GET_FLAG(FLAG)
#define | IS_ADC_INJECTED_CHANNEL(CHANNEL)
#define | IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
#define | IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
#define | IS_ADC_IT(IT)
#define | IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
#define | IS_ADC_POWER_DOWN(DWON)
#define | IS_ADC_PRESCALER(PRESCALER)
#define | IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
#define | IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
#define | IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
#define | IS_ADC_RESOLUTION(RESOLUTION)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_BankSelection (ADC_TypeDef *ADCx, uint8_t ADC_Bank)
Selects the specified ADC Channels Bank.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
void | ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
void | ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes ADC1 peripheral registers to their default reset values.
void | ADC_DelaySelectionConfig (ADC_TypeDef *ADCx, uint8_t ADC_DelayLength)
Defines the length of the delay which is applied after a conversion or a sequence of conversion.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode).
void | ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
void | ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_PowerDownCmd (ADC_TypeDef *ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
Enables or disables the ADC Power Down during Delay and/or Idle phase.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampling time.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.
void | ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

This file contains all the functions prototypes for the ADC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_adc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_aes.c File Reference

This file provides firmware functions to manage the following functionalities of the AES peripheral: + Configuration + Read/Write operations + DMA transfers management + Interrupts and flags management. More...

#include "stm32l1xx_aes.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)

Functions

void | AES_ClearFlag (uint32_t AES_FLAG)
Clears the AES flags.
void | AES_ClearITPendingBit (uint32_t AES_IT)
Clears the AES's interrupt pending bits.
void | AES_Cmd (FunctionalState NewState)
Enable or disable the AES peripheral.
void | AES_DeInit (void)
Deinitializes AES peripheral registers to their default reset values.
void | AES_DMAConfig (uint32_t AES_DMATransfer, FunctionalState NewState)
Configures the AES DMA interface.
FlagStatus | AES_GetFlagStatus (uint32_t AES_FLAG)
Checks whether the specified AES flag is set or not.
ITStatus | AES_GetITStatus (uint32_t AES_IT)
Checks whether the specified AES interrupt has occurred or not.
void | AES_Init (AES_InitTypeDef *AES_InitStruct)
Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

void | AES_ITConfig (uint32_t AES_IT, FunctionalState NewState)
Enables or disables the specified AES interrupt.
void | AES_IVInit (AES_IVInitTypeDef *AES_IVInitStruct)
Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.
void | AES_IVStructInit (AES_IVInitTypeDef *AES_IVInitStruct)
Fills each AES_IVInitStruct member with its default value.
void | AES_KeyInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
void | AES_KeyStructInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Fills each AES_KeyInitStruct member with its default value.
void | AES_ReadIV (AES_IVInitTypeDef *AES_IVInitStruct)
Read the Initialization Vector IV value.
void | AES_ReadKey (AES_KeyInitTypeDef *AES_KeyInitStruct)
Read the Key value.
uint32_t | AES_ReadSubData (void)
Returns the data in DOUTR register processed by AES peripheral.
void | AES_StructInit (AES_InitTypeDef *AES_InitStruct)
Fills each AES_InitStruct member with its default value.
void | AES_WriteSubData (uint32_t Data)
Write data in DINR register to be processed by AES peripheral.

Detailed Description

This file provides firmware functions to manage the following functionalities of the AES peripheral: + Configuration + Read/Write operations + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
 ===============================================================================
                        ##### AES Peripheral features #####
 ===============================================================================
....[..]
   (#) The Advanced Encryption Standard hardware accelerator (AES) can be used
       to both encipher and decipher data using AES algorithm.
   (#) The AES supports 4 operation modes:
       (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
       (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
       (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
       (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
   (#) Moreover 3 chaining modes are supported:
       (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
       (++) Cipher block chaining (CBC): Each block is XORed with the previous block
       (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
          plain text to give the cipher text
  (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
  (#) The AES peripheral supports write/read error handling with interrupt capability.
  (#) Automatic data flow control with support of direct memory access (DMA) using
      2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
      (DMA2 Channel3).

                      ##### How to use this driver #####
 ===============================================================================
    [..]
        (#) AES AHB clock must be enabled to get write access to AES registers
            using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
        (#) Initialize the key using AES_KeyInit().
        (#) Configure the AES operation mode using AES_Init().
        (#) If required, enable interrupt source using AES_ITConfig() and
            enable the AES interrupt vector using NVIC_Init().
        (#) If required, when using the DMA mode.
            (##) Configure the DMA using DMA_Init().
            (##) Enable DMA requests using AES_DMAConfig().
        (#) Enable the AES peripheral using AES_Cmd().
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_aes.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_aes.h File Reference

This file contains all the functions prototypes for the AES firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | AES_InitTypeDef
AES Init structure definition. More...
struct | AES_IVInitTypeDef
AES Initialization Vectors (IV) structure definition. More...
struct | AES_KeyInitTypeDef
AES Key(s) structure definition. More...

Defines

#define | AES_Chaining_CBC AES_CR_CHMOD_0
#define | AES_Chaining_CTR AES_CR_CHMOD_1
#define | AES_Chaining_ECB ((uint32_t)0x00000000)
#define | AES_DataType_16b AES_CR_DATATYPE_0
#define | AES_DataType_1b AES_CR_DATATYPE
#define | AES_DataType_32b ((uint32_t)0x00000000)
#define | AES_DataType_8b AES_CR_DATATYPE_1
#define | AES_DMATransfer_In AES_CR_DMAINEN
#define | AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN)
#define | AES_DMATransfer_Out AES_CR_DMAOUTEN
#define | AES_FLAG_CCF AES_SR_CCF
#define | AES_FLAG_RDERR AES_SR_RDERR
#define | AES_FLAG_WRERR AES_SR_WRERR
#define | AES_IT_CC AES_CR_CCIE
#define | AES_IT_ERR AES_CR_ERRIE
#define | AES_Operation_Decryp AES_CR_MODE_1
#define | AES_Operation_Encryp ((uint32_t)0x00000000)
#define | AES_Operation_KeyDeriv AES_CR_MODE_0
#define | AES_Operation_KeyDerivAndDecryp AES_CR_MODE
#define | IS_AES_CHAINING(CHAINING)
#define | IS_AES_DATATYPE(DATATYPE)
#define | IS_AES_DMA_TRANSFER(TRANSFER)
#define | IS_AES_FLAG(FLAG)
#define | IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
#define | IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
#define | IS_AES_MODE(OPERATION)

Functions

ErrorStatus | AES_CBC_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CBC Mode.
ErrorStatus | AES_CBC_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CBC Mode.
void | AES_ClearFlag (uint32_t AES_FLAG)
Clears the AES flags.
void | AES_ClearITPendingBit (uint32_t AES_IT)
Clears the AES's interrupt pending bits.
void | AES_Cmd (FunctionalState NewState)
Enable or disable the AES peripheral.
ErrorStatus | AES_CTR_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CTR Mode.
ErrorStatus | AES_CTR_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CTR Mode.
void | AES_DeInit (void)
Deinitializes AES peripheral registers to their default reset values.
void | AES_DMAConfig (uint32_t AES_DMATransfer, FunctionalState NewState)
Configures the AES DMA interface.
ErrorStatus | AES_ECB_Decrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in ECB Mode.
ErrorStatus | AES_ECB_Encrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in ECB Mode.
FlagStatus | AES_GetFlagStatus (uint32_t AES_FLAG)
Checks whether the specified AES flag is set or not.
ITStatus | AES_GetITStatus (uint32_t AES_IT)
Checks whether the specified AES interrupt has occurred or not.
void | AES_Init (AES_InitTypeDef *AES_InitStruct)
Initializes the AES peripheral according to the specified parameters in the AES_InitStruct:

  • AES_Operation: specifies the operation mode (encryption, decryption...).

void | AES_ITConfig (uint32_t AES_IT, FunctionalState NewState)
Enables or disables the specified AES interrupt.
void | AES_IVInit (AES_IVInitTypeDef *AES_IVInitStruct)
Initializes the AES Initialization Vector IV according to the specified parameters in the AES_IVInitStruct.
void | AES_IVStructInit (AES_IVInitTypeDef *AES_IVInitStruct)
Fills each AES_IVInitStruct member with its default value.
void | AES_KeyInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
void | AES_KeyStructInit (AES_KeyInitTypeDef *AES_KeyInitStruct)
Fills each AES_KeyInitStruct member with its default value.
void | AES_ReadIV (AES_IVInitTypeDef *AES_IVInitStruct)
Read the Initialization Vector IV value.
void | AES_ReadKey (AES_KeyInitTypeDef *AES_KeyInitStruct)
Read the Key value.
uint32_t | AES_ReadSubData (void)
Returns the data in DOUTR register processed by AES peripheral.
void | AES_StructInit (AES_InitTypeDef *AES_InitStruct)
Fills each AES_InitStruct member with its default value.
void | AES_WriteSubData (uint32_t Data)
Write data in DINR register to be processed by AES peripheral.

Detailed Description

This file contains all the functions prototypes for the AES firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_aes.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes_util.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_aes_util.c File Reference

This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR modes. More...

#include "stm32l1xx_aes.h"

Go to the source code of this file.

Defines

#define | AES_CC_TIMEOUT ((uint32_t) 0x00010000)

Functions

ErrorStatus | AES_CBC_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CBC Mode.
ErrorStatus | AES_CBC_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CBC Mode.
ErrorStatus | AES_CTR_Decrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in CTR Mode.
ErrorStatus | AES_CTR_Encrypt (uint8_t *Key, uint8_t InitVectors[16], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in CTR Mode.
ErrorStatus | AES_ECB_Decrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Decrypt using AES in ECB Mode.
ErrorStatus | AES_ECB_Encrypt (uint8_t *Key, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt using AES in ECB Mode.

Detailed Description

This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR modes.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

================================================================================
                        ##### How to use this driver #####
================================================================================
          [..]
           (#) Enable The AES controller clock using
               RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.

           (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
           (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.

           (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
           (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.

           (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
           (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.

  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_aes_util.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_comp.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Functions

stm32l1xx_comp.c File Reference

This file provides firmware functions to manage the following functionalities of the comparators (COMP1 and COMP2) peripheral: + Comparators configuration + Window mode control + Internal Reference Voltage (VREFINT) output. More...

#include "stm32l1xx_comp.h"

Go to the source code of this file.

Functions

void | COMP_Cmd (FunctionalState NewState)
Enable or disable the COMP1 peripheral.
void | COMP_DeInit (void)
Deinitializes COMP peripheral registers to their default reset values.
uint8_t | COMP_GetOutputLevel (uint32_t COMP_Selection)
Return the output level (high or low) of the selected comparator.
void | COMP_Init (COMP_InitTypeDef *COMP_InitStruct)
Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.
void | COMP_SW1SwitchConfig (FunctionalState NewState)
Close or Open the SW1 switch.
void | COMP_VrefintOutputCmd (FunctionalState NewState)
Enables or disables the output of internal reference voltage (VREFINT).
void | COMP_WindowCmd (FunctionalState NewState)
Enables or disables the window mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the comparators (COMP1 and COMP2) peripheral: + Comparators configuration + Window mode control + Internal Reference Voltage (VREFINT) output.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..] The device integrates two analog comparators COMP1 and COMP2:
         (+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting
             input with the ADC channels.
         (+) COMP2 is a rail-to-rail comparator whose the inverting input can be
             selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4
             VREFINT, VREFINT, PB3 and whose the output can be redirected to
             embedded timers: TIM2, TIM3, TIM4, TIM10.

         (+) The two comparators COMP1 and COMP2 can be combined in window mode.

         -@-
            (#@) Comparator APB clock must be enabled to get write access
                 to comparator register using
                 RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).

            (#@) COMP1 comparator and ADC can't be used at the same time since
                 they share the same ADC switch matrix (analog switches).

            (#@) When an I/O is used as comparator input, the corresponding GPIO
                 registers should be configured in analog mode.

            (#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
                 GPIO pin. They are only internal.
                 To get the comparator output level, use COMP_GetOutputLevel().

            (#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21
                 and EXTI Line 22 respectively.
                 Interrupts can be used by configuring the EXTI Line using the
                 EXTI peripheral driver.

            (#@) After enabling the comparator (COMP1 or COMP2), user should wait
                 for start-up time (tSTART) to get right output levels.
                 Please refer to product datasheet for more information on tSTART.

            (#@) Comparators cannot be used to exit the device from Sleep or Stop
                 mode when the internal reference voltage is switched off using
                 the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_comp.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_comp.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_comp.h File Reference

This file contains all the functions prototypes for the COMP firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...

Defines

#define | COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
#define | COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
#define | COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
#define | COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
#define | COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
#define | COMP_InvertingInput_IO ((uint32_t)0x00040000)
#define | COMP_InvertingInput_None ((uint32_t)0x00000000)
#define | COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
#define | COMP_OutputLevel_High ((uint32_t)0x00000001)
#define | COMP_OutputLevel_Low ((uint32_t)0x00000000)
#define | COMP_OutputSelect_None ((uint32_t)0x00E00000)
#define | COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
#define | COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
#define | COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
#define | COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
#define | COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
#define | COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
#define | COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
#define | COMP_Selection_COMP1 ((uint32_t)0x00000001)
#define | COMP_Selection_COMP2 ((uint32_t)0x00000002)
#define | COMP_Speed_Fast ((uint32_t)0x00001000)
#define | COMP_Speed_Slow ((uint32_t)0x00000000)
#define | IS_COMP_ALL_PERIPH(PERIPH)
#define | IS_COMP_INVERTING_INPUT(INPUT)
#define | IS_COMP_OUTPUT(OUTPUT)
#define | IS_COMP_SPEED(SPEED)

Functions

void | COMP_Cmd (FunctionalState NewState)
Enable or disable the COMP1 peripheral.
void | COMP_DeInit (void)
Deinitializes COMP peripheral registers to their default reset values.
uint8_t | COMP_GetOutputLevel (uint32_t COMP_Selection)
Return the output level (high or low) of the selected comparator.
void | COMP_Init (COMP_InitTypeDef *COMP_InitStruct)
Initializes the COMP2 peripheral according to the specified parameters in the COMP_InitStruct.
void | COMP_SW1SwitchConfig (FunctionalState NewState)
Close or Open the SW1 switch.
void | COMP_VrefintOutputCmd (FunctionalState NewState)
Enables or disables the output of internal reference voltage (VREFINT).
void | COMP_WindowCmd (FunctionalState NewState)
Enables or disables the window mode.

Detailed Description

This file contains all the functions prototypes for the COMP firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_comp.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_crc.c File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • src
Functions

stm32l1xx_crc.c File Reference

This file provides all the CRC firmware functions. More...

#include "stm32l1xx_crc.h"

Go to the source code of this file.

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Detailed Description

This file provides all the CRC firmware functions.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_crc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_crc.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Functions

stm32l1xx_crc.h File Reference

This file contains all the functions prototypes for the CRC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Detailed Description

This file contains all the functions prototypes for the CRC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_crc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dac.c File Reference

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  • src
Defines | Functions

stm32l1xx_dac.c File Reference

This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral: + DAC channels configuration: trigger, output buffer, data format + DMA management + Interrupts and flags management. More...

#include "stm32l1xx_dac.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR_CLEAR_MASK ((uint32_t)0x00000FFE)
#define | DHR12R1_OFFSET ((uint32_t)0x00000008)
#define | DHR12R2_OFFSET ((uint32_t)0x00000014)
#define | DHR12RD_OFFSET ((uint32_t)0x00000020)
#define | DOR_OFFSET ((uint32_t)0x0000002C)
#define | DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
#define | DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Functions

void | DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel's pending flags.
void | DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel's interrupt pending bits.
void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
FlagStatus | DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
ITStatus | DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral: + DAC channels configuration: trigger, output buffer, data format + DMA management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  *
 ===============================================================================
                        ##### DAC Peripheral features #####
 ===============================================================================
    [..] The device integrates two 12-bit Digital Analog Converters that can
         be used independently or simultaneously (dual mode):
         (#) DAC channel1 with DAC_OUT1 (PA4) as output.
         (#) DAC channel2 with DAC_OUT2 (PA5) as output.

    [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
         and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
         DAC_SetChannel1Data()/DAC_SetChannel2Data.

    [..] Digital to Analog conversion can be triggered by:
         (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
             The used pin (GPIOx_Pin9) must be configured in input mode.
         (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9
             (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
             The timer TRGO event should be selected using TIM_SelectOutputTrigger()
         (#) Software using DAC_Trigger_Software.

    [..] Each DAC channel integrates an output buffer that can be used to
         reduce the output impedance, and to drive external loads directly
         without having to add an external operational amplifier.
         To enable, the output buffer use
         DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;

    [..] Refer to the device datasheet for more details about output impedance
         value with and without output buffer.

    [..] Both DAC channels can be used to generate:
         (#) Noise wave using DAC_WaveGeneration_Noise
         (#) Triangle wave using DAC_WaveGeneration_Triangle

    [..] Wave generation can be disabled using DAC_WaveGeneration_None.

    [..] The DAC data format can be:
         (#) 8-bit right alignment using DAC_Align_8b_R
         (#) 12-bit left alignment using DAC_Align_12b_L
         (#) 12-bit right alignment using DAC_Align_12b_R

    [..] The analog output voltage on each DAC channel pin is determined
         by the following equation: DAC_OUTx = VREF+ * DOR / 4095
         with  DOR is the Data Output Register.
         VEF+ is the input voltage reference (refer to the device datasheet)
         e.g. To set DAC_OUT1 to 0.7V, use
         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
         Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.

    [..] A DMA1 request can be generated when an external trigger (but not
         a software trigger) occurs if DMA1 requests are enabled using
         DAC_DMACmd()
    [..] DMA1 requests are mapped as following:
         (#) DAC channel1 is mapped on DMA1 channel3 which must be already
             configured.
         (#) DAC channel2 is mapped on DMA1 channel4 which must be already
             configured.

                      ##### How to use this driver #####
 ===============================================================================
    [..]
        (+) DAC APB clock must be enabled to get write access to DAC registers using
            RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
        (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
        (+) Configure the DAC channel using DAC_Init()
        (+) Enable the DAC channel using DAC_Cmd()
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dac.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dac.h File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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Data Structures | Defines | Functions

stm32l1xx_dac.h File Reference

This file contains all the functions prototypes for the DAC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | DAC_InitTypeDef
DAC Init structure definition. More...

Defines

#define | DAC_Align_12b_L ((uint32_t)0x00000004)
#define | DAC_Align_12b_R ((uint32_t)0x00000000)
#define | DAC_Align_8b_R ((uint32_t)0x00000008)
#define | DAC_Channel_1 ((uint32_t)0x00000000)
#define | DAC_Channel_2 ((uint32_t)0x00000010)
#define | DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define | DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define | DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
#define | DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
#define | DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
#define | DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
#define | DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
#define | DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
#define | DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
#define | DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
#define | DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
#define | DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
#define | DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
#define | DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
#define | DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define | DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
#define | DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
#define | DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
#define | DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
#define | DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
#define | DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
#define | DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
#define | DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
#define | DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
#define | DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
#define | DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
#define | DAC_Trigger_None ((uint32_t)0x00000000)
#define | DAC_Trigger_Software ((uint32_t)0x0000003C)
#define | DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
#define | DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
#define | DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
#define | DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
#define | DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C)
#define | DAC_Wave_Noise ((uint32_t)0x00000040)
#define | DAC_Wave_Triangle ((uint32_t)0x00000080)
#define | DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define | DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define | DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
#define | IS_DAC_GENERATE_WAVE(WAVE)
#define | IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_WAVE(WAVE)

Functions

void | DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel's pending flags.
void | DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel's interrupt pending bits.
void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
FlagStatus | DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
ITStatus | DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

This file contains all the functions prototypes for the DAC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dac.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dbgmcu.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_dbgmcu.c File Reference

This file provides all the DBGMCU firmware functions. More...

#include "stm32l1xx_dbgmcu.h"

Go to the source code of this file.

Defines

#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Functions

void | DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB1 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB2 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures low power mode behavior when the MCU is in Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Detailed Description

This file provides all the DBGMCU firmware functions.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dbgmcu.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dbgmcu.h File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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Defines | Functions

stm32l1xx_dbgmcu.h File Reference

This file contains all the functions prototypes for the DBGMCU firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define | DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define | DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
#define | DBGMCU_RTC_STOP ((uint32_t)0x00000400)
#define | DBGMCU_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM10_STOP ((uint32_t)0x00000008)
#define | DBGMCU_TIM11_STOP ((uint32_t)0x00000010)
#define | DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
#define | DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
#define | DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
#define | DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
#define | DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
#define | DBGMCU_TIM9_STOP ((uint32_t)0x00000004)
#define | DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
#define | IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
#define | IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
#define | IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))

Functions

void | DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB1 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB2 peripheral behavior when the MCU is in Debug mode.
void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures low power mode behavior when the MCU is in Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Detailed Description

This file contains all the functions prototypes for the DBGMCU firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dbgmcu.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dma.c File Reference

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Defines | Functions

stm32l1xx_dma.c File Reference

This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA): + Initialization and Configuration + Data Counter + Interrupts and flags management. More...

#include "stm32l1xx_dma.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
#define | DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define | DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
#define | DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | FLAG_MASK ((uint32_t)0x10000000)

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA): + Initialization and Configuration + Data Counter + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
    (#) Enable The DMA controller clock using
        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
        using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
    (#) Enable and configure the peripheral to be connected to the DMA channel
               (except for internal SRAM / FLASH memories: no initialization is
               necessary).
    (#) For a given Channel, program the Source and Destination addresses,
        the transfer Direction, the Buffer Size, the Peripheral and Memory
        Incrementation mode and Data Size, the Circular or Normal mode,
        the channel transfer Priority and the Memory-to-Memory transfer
        mode (if needed) using the DMA_Init() function.
    (#) Enable the NVIC and the corresponding interrupt(s) using the function
        DMA_ITConfig() if you need to use DMA interrupts.
    (#) Enable the DMA channel using the DMA_Cmd() function.
    (#) Activate the needed channel Request using PPP_DMACmd() function for
        any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
        The function allowing this operation is provided in each PPP peripheral
        driver (ie. SPI_DMACmd for SPI peripheral).
    (#) Optionally, you can configure the number of data to be transferred
        when the channel is disabled (ie. after each Transfer Complete event
        or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
        And you can get the number of remaining data to be transferred using
        the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
        enabled and running).
    (#) To control DMA events you can use one of the following two methods:
        (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
        (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
             phase and DMA_GetITStatus() function into interrupt routines in
             communication phase.
             After checking on a flag you should clear it using DMA_ClearFlag()
             function. And after checking on an interrupt event you should
             clear it using DMA_ClearITPendingBit() function.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dma.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dma.h File Reference

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  • inc
Data Structures | Defines | Functions

stm32l1xx_dma.h File Reference

This file contains all the functions prototypes for the DMA firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Init structure definition. More...

Defines

#define | DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define | DMA1_IT_GL1 ((uint32_t)0x00000001)
#define | DMA1_IT_GL2 ((uint32_t)0x00000010)
#define | DMA1_IT_GL3 ((uint32_t)0x00000100)
#define | DMA1_IT_GL4 ((uint32_t)0x00001000)
#define | DMA1_IT_GL5 ((uint32_t)0x00010000)
#define | DMA1_IT_GL6 ((uint32_t)0x00100000)
#define | DMA1_IT_GL7 ((uint32_t)0x01000000)
#define | DMA1_IT_HT1 ((uint32_t)0x00000004)
#define | DMA1_IT_HT2 ((uint32_t)0x00000040)
#define | DMA1_IT_HT3 ((uint32_t)0x00000400)
#define | DMA1_IT_HT4 ((uint32_t)0x00004000)
#define | DMA1_IT_HT5 ((uint32_t)0x00040000)
#define | DMA1_IT_HT6 ((uint32_t)0x00400000)
#define | DMA1_IT_HT7 ((uint32_t)0x04000000)
#define | DMA1_IT_TC1 ((uint32_t)0x00000002)
#define | DMA1_IT_TC2 ((uint32_t)0x00000020)
#define | DMA1_IT_TC3 ((uint32_t)0x00000200)
#define | DMA1_IT_TC4 ((uint32_t)0x00002000)
#define | DMA1_IT_TC5 ((uint32_t)0x00020000)
#define | DMA1_IT_TC6 ((uint32_t)0x00200000)
#define | DMA1_IT_TC7 ((uint32_t)0x02000000)
#define | DMA1_IT_TE1 ((uint32_t)0x00000008)
#define | DMA1_IT_TE2 ((uint32_t)0x00000080)
#define | DMA1_IT_TE3 ((uint32_t)0x00000800)
#define | DMA1_IT_TE4 ((uint32_t)0x00008000)
#define | DMA1_IT_TE5 ((uint32_t)0x00080000)
#define | DMA1_IT_TE6 ((uint32_t)0x00800000)
#define | DMA1_IT_TE7 ((uint32_t)0x08000000)
#define | DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define | DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define | DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define | DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define | DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define | DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define | DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define | DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define | DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define | DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define | DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define | DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define | DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define | DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define | DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define | DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define | DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define | DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define | DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define | DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define | DMA2_IT_GL1 ((uint32_t)0x10000001)
#define | DMA2_IT_GL2 ((uint32_t)0x10000010)
#define | DMA2_IT_GL3 ((uint32_t)0x10000100)
#define | DMA2_IT_GL4 ((uint32_t)0x10001000)
#define | DMA2_IT_GL5 ((uint32_t)0x10010000)
#define | DMA2_IT_HT1 ((uint32_t)0x10000004)
#define | DMA2_IT_HT2 ((uint32_t)0x10000040)
#define | DMA2_IT_HT3 ((uint32_t)0x10000400)
#define | DMA2_IT_HT4 ((uint32_t)0x10004000)
#define | DMA2_IT_HT5 ((uint32_t)0x10040000)
#define | DMA2_IT_TC1 ((uint32_t)0x10000002)
#define | DMA2_IT_TC2 ((uint32_t)0x10000020)
#define | DMA2_IT_TC3 ((uint32_t)0x10000200)
#define | DMA2_IT_TC4 ((uint32_t)0x10002000)
#define | DMA2_IT_TC5 ((uint32_t)0x10020000)
#define | DMA2_IT_TE1 ((uint32_t)0x10000008)
#define | DMA2_IT_TE2 ((uint32_t)0x10000080)
#define | DMA2_IT_TE3 ((uint32_t)0x10000800)
#define | DMA2_IT_TE4 ((uint32_t)0x10008000)
#define | DMA2_IT_TE5 ((uint32_t)0x10080000)
#define | DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define | DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define | DMA_IT_HT ((uint32_t)0x00000004)
#define | DMA_IT_TC ((uint32_t)0x00000002)
#define | DMA_IT_TE ((uint32_t)0x00000008)
#define | DMA_M2M_Disable ((uint32_t)0x00000000)
#define | DMA_M2M_Enable ((uint32_t)0x00004000)
#define | DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define | DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define | DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define | DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define | DMA_Mode_Circular ((uint32_t)0x00000020)
#define | DMA_Mode_Normal ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define | DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define | DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define | DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define | DMA_Priority_High ((uint32_t)0x00002000)
#define | DMA_Priority_Low ((uint32_t)0x00000000)
#define | DMA_Priority_Medium ((uint32_t)0x00001000)
#define | DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define | IS_DMA_ALL_PERIPH(PERIPH)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define | IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define | IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define | IS_DMA_DIR(DIR)
#define | IS_DMA_GET_FLAG(FLAG)
#define | IS_DMA_GET_IT(IT)
#define | IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_PRIORITY(PRIORITY)

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

This file contains all the functions prototypes for the DMA firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_dma.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_exti.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_exti.c File Reference

This file provides firmware functions to manage the following functionalities of the EXTI peripheral: + Initialization and Configuration + Interrupts and flags management. More...

#include "stm32l1xx_exti.h"

Go to the source code of this file.

Defines

#define | EXTI_LINENONE ((uint32_t)0x00000)

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

This file provides firmware functions to manage the following functionalities of the EXTI peripheral: + Initialization and Configuration + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  ==============================================================================
                            ##### EXTI features #####
  ==============================================================================
    [..] External interrupt/event lines are mapped as following:
         (#) All available GPIO pins are connected to the 16 external
             interrupt/event lines from EXTI0 to EXTI15.
         (#) EXTI line 16 is connected to the PVD output.
         (#) EXTI line 17 is connected to the RTC Alarm event.
         (#) EXTI line 18 is connected to the USB Device FS wakeup event.
         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
         (#) EXTI line 20 is connected to the RTC Wakeup event.
         (#) EXTI line 21 is connected to the Comparator 1 wakeup event.
         (#) EXTI line 22 is connected to the Comparator 2 wakeup event.
         (#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.

                       ##### How to use this driver #####
  ==============================================================================
    [..] In order to use an I/O pin as an external interrupt source, follow
         steps below:
    (#) Configure the I/O in input mode using GPIO_Init()
    (#) Select the input source pin for the EXTI line using
        SYSCFG_EXTILineConfig()
    (#) Select the mode(interrupt, event) and configure the trigger
        selection (Rising, falling or both) using EXTI_Init()
    (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
    [..]
    (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_exti.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_exti.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • inc
Data Structures | Defines | Enumerations | Functions

stm32l1xx_exti.h File Reference

This file contains all the functions prototypes for the EXTI firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | EXTI_InitTypeDef
EXTI Init Structure definition. More...

Defines

#define | EXTI_Line0 ((uint32_t)0x00000001)
#define | EXTI_Line1 ((uint32_t)0x00000002)
#define | EXTI_Line10 ((uint32_t)0x00000400)
#define | EXTI_Line11 ((uint32_t)0x00000800)
#define | EXTI_Line12 ((uint32_t)0x00001000)
#define | EXTI_Line13 ((uint32_t)0x00002000)
#define | EXTI_Line14 ((uint32_t)0x00004000)
#define | EXTI_Line15 ((uint32_t)0x00008000)
#define | EXTI_Line16 ((uint32_t)0x00010000)
#define | EXTI_Line17 ((uint32_t)0x00020000)
#define | EXTI_Line18 ((uint32_t)0x00040000)
#define | EXTI_Line19 ((uint32_t)0x00080000)
#define | EXTI_Line2 ((uint32_t)0x00000004)
#define | EXTI_Line20 ((uint32_t)0x00100000)
#define | EXTI_Line21 ((uint32_t)0x00200000)
#define | EXTI_Line22 ((uint32_t)0x00400000)
#define | EXTI_Line23 ((uint32_t)0x00800000)
#define | EXTI_Line3 ((uint32_t)0x00000008)
#define | EXTI_Line4 ((uint32_t)0x00000010)
#define | EXTI_Line5 ((uint32_t)0x00000020)
#define | EXTI_Line6 ((uint32_t)0x00000040)
#define | EXTI_Line7 ((uint32_t)0x00000080)
#define | EXTI_Line8 ((uint32_t)0x00000100)
#define | EXTI_Line9 ((uint32_t)0x00000200)
#define | IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define | IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define | IS_EXTI_TRIGGER(TRIGGER)
#define | IS_GET_EXTI_LINE(LINE)

Enumerations

enum | EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }

EXTI mode enumeration.

More...
enum | EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }

EXTI Trigger enumeration.

More...

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

This file contains all the functions prototypes for the EXTI firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_exti.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • src
Defines | Functions

stm32l1xx_flash.c File Reference

This file provides all the Flash firmware functions. These functions can be executed from Internal FLASH or Internal SRAM memories. The functions that should be called from SRAM are defined inside the "stm32l1xx_flash_ramfunc.c" file. This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + FLASH Interface configuration + FLASH Memory Programming + DATA EEPROM Programming + Option Bytes Programming + Interrupts and flags management. More...

#include "stm32l1xx_flash.h"

Go to the source code of this file.

Defines

#define | WRP01_MASK ((uint32_t)0x0000FFFF)
#define | WRP1011_MASK ((uint32_t)0xFFFF0000)
#define | WRP23_MASK ((uint32_t)0xFFFF0000)
#define | WRP45_MASK ((uint32_t)0x0000FFFF)
#define | WRP67_MASK ((uint32_t)0xFFFF0000)
#define | WRP89_MASK ((uint32_t)0x0000FFFF)

Functions

FLASH_Status | DATA_EEPROM_EraseByte (uint32_t Address)
Erase a byte in data memory.
FLASH_Status | DATA_EEPROM_EraseHalfWord (uint32_t Address)
Erase a halfword in data memory.
FLASH_Status | DATA_EEPROM_EraseWord (uint32_t Address)
Erase a word in data memory.
FLASH_Status | DATA_EEPROM_FastProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory.
void | DATA_EEPROM_FixedTimeProgramCmd (FunctionalState NewState)
Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
void | DATA_EEPROM_Lock (void)
Locks the Data memory and FLASH_PECR register access.
FLASH_Status | DATA_EEPROM_ProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory without erase.
void | DATA_EEPROM_Unlock (void)
Unlocks the data memory and FLASH_PECR register access.
void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified page in program memory.
FLASH_Status | FLASH_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in program memory.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the Program memory access.
FLASH_Status | FLASH_OB_BootConfig (uint8_t OB_BOOT)
Configures to boot from Bank1 or Bank2.
FLASH_Status | FLASH_OB_BORConfig (uint8_t OB_BOR)
Programs the FLASH brownout reset threshold level Option Byte.
uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
FlagStatus | FLASH_OB_GetRDP (void)
Checks whether the FLASH Read out Protection Status is set or not.
uint8_t | FLASH_OB_GetUser (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_OB_GetWRP (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP1 (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP2 (void)
Returns the FLASH Write Protection Option Bytes value.
void | FLASH_OB_Launch (void)
Launch the option byte loading.
void | FLASH_OB_Lock (void)
Locks the option bytes block access.
FLASH_Status | FLASH_OB_RDPConfig (uint8_t OB_RDP)
Enables or disables the read out protection.
void | FLASH_OB_Unlock (void)
Unlocks the option bytes block access.
FLASH_Status | FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_OB_WRP1Config (uint32_t OB_WRP1, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRP2Config (uint32_t OB_WRP2, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
Write protects the desired pages.
void | FLASH_PrefetchBufferCmd (FunctionalState NewState)
Enables or disables the Prefetch Buffer.
void | FLASH_ReadAccess64Cmd (FunctionalState NewState)
Enables or disables read access to flash by 64 bits.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_SLEEPPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during Sleep mode.
void | FLASH_Unlock (void)
Unlocks the FLASH control register and program memory access.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Detailed Description

This file provides all the Flash firmware functions. These functions can be executed from Internal FLASH or Internal SRAM memories. The functions that should be called from SRAM are defined inside the "stm32l1xx_flash_ramfunc.c" file. This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + FLASH Interface configuration + FLASH Memory Programming + DATA EEPROM Programming + Option Bytes Programming + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..] This driver provides functions to configure and program the Flash
         memory of all STM32L1xx devices.
    [..] These functions are split in 5 groups:
         (#) FLASH Interface configuration functions: this group includes
             the management of following features:
             (++) Set the latency.
             (++) Enable/Disable the prefetch buffer.
             (++) Enable/Disable the 64 bit Read Access.
             (++) Enable/Disable the RUN PowerDown mode.
             (++) Enable/Disable the SLEEP PowerDown mode.

         (#) FLASH Memory Programming functions: this group includes all
             needed functions to erase and program the main memory:
             (++) Lock and Unlock the Flash interface.
             (++) Erase function: Erase Page.
             (++) Program functions: Fast Word and Half Page(should be
                  executed from internal SRAM).

         (#) DATA EEPROM Programming functions: this group includes all
             needed functions to erase and program the DATA EEPROM memory:
             (++) Lock and Unlock the DATA EEPROM interface.
             (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
             (++) Double Word (should be executed from internal SRAM).
             (++) Program functions: Fast Program Byte, Fast Program Half-Word,
                  FastProgramWord, Program Byte, Program Half-Word,
                  Program Word and Program Double-Word (should be executed
                  from internal SRAM).

         (#) FLASH Option Bytes Programming functions: this group includes
             all needed functions to:
             (++) Lock and Unlock the Flash Option bytes.
             (++) Set/Reset the write protection.
             (++) Set the Read protection Level.
             (++) Set the BOR level.
             (++) rogram the user option Bytes.
             (++) Launch the Option Bytes loader.
             (++) Get the Write protection.
             (++) Get the read protection status.
             (++) Get the BOR level.
             (++) Get the user option bytes.

         (#) FLASH Interrupts and flag management functions: this group
             includes all needed functions to:
             (++) Enable/Disable the flash interrupt sources.
             (++) Get flags status.
             (++) Clear flags.
             (++) Get Flash operation status.
             (++) Wait for last flash operation.

  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_flash.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm32l1xx_flash.h File Reference

This file contains all the functions prototypes for the FLASH firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ENDHV FLASH_SR_ENHV
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_READY FLASH_SR_READY
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_IT_EOP FLASH_PECR_EOPIE
#define | FLASH_IT_ERR FLASH_PECR_ERRIE
#define | FLASH_Latency_0 ((uint8_t)0x00)
#define | FLASH_Latency_1 ((uint8_t)0x01)
#define | FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8)
#define | FLASH_OPTKEY2 ((uint32_t)0x24252627)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637)
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD)
#define | FLASH_PEKEY1 ((uint32_t)0x89ABCDEF)
#define | FLASH_PEKEY2 ((uint32_t)0x02030405)
#define | FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF)
#define | FLASH_PRGKEY2 ((uint32_t)0x13141516)
#define | IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
#define | IS_FLASH_GET_FLAG(FLAG)
#define | IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))
#define | IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_RDP(LEVEL)
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
#define | OB_BOOT_BANK1 ((uint8_t)0x80)
#define | OB_BOOT_BANK2 ((uint8_t)0x00)
#define | OB_BOR_LEVEL1 ((uint8_t)0x08)
#define | OB_BOR_LEVEL2 ((uint8_t)0x09)
#define | OB_BOR_LEVEL3 ((uint8_t)0x0A)
#define | OB_BOR_LEVEL4 ((uint8_t)0x0B)
#define | OB_BOR_LEVEL5 ((uint8_t)0x0C)
#define | OB_BOR_OFF ((uint8_t)0x00)
#define | OB_IWDG_HW ((uint8_t)0x00)
#define | OB_IWDG_SW ((uint8_t)0x10)
#define | OB_RDP_Level_0 ((uint8_t)0xAA)
Read Protection Level.
#define | OB_RDP_Level_1 ((uint8_t)0xBB)
#define | OB_STDBY_NoRST ((uint8_t)0x40)
#define | OB_STDBY_RST ((uint8_t)0x00)
#define | OB_STOP_NoRST ((uint8_t)0x20)
#define | OB_STOP_RST ((uint8_t)0x00)
#define | OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000)
#define | OB_WRP1_Pages512to527 ((uint32_t)0x00000001)
#define | OB_WRP1_Pages528to543 ((uint32_t)0x00000002)
#define | OB_WRP1_Pages544to559 ((uint32_t)0x00000004)
#define | OB_WRP1_Pages560to575 ((uint32_t)0x00000008)
#define | OB_WRP1_Pages576to591 ((uint32_t)0x00000010)
#define | OB_WRP1_Pages592to607 ((uint32_t)0x00000020)
#define | OB_WRP1_Pages608to623 ((uint32_t)0x00000040)
#define | OB_WRP1_Pages624to639 ((uint32_t)0x00000080)
#define | OB_WRP1_Pages640to655 ((uint32_t)0x00000100)
#define | OB_WRP1_Pages656to671 ((uint32_t)0x00000200)
#define | OB_WRP1_Pages672to687 ((uint32_t)0x00000400)
#define | OB_WRP1_Pages688to703 ((uint32_t)0x00000800)
#define | OB_WRP1_Pages704to719 ((uint32_t)0x00001000)
#define | OB_WRP1_Pages720to735 ((uint32_t)0x00002000)
#define | OB_WRP1_Pages736to751 ((uint32_t)0x00004000)
#define | OB_WRP1_Pages752to767 ((uint32_t)0x00008000)
#define | OB_WRP1_Pages768to783 ((uint32_t)0x00010000)
#define | OB_WRP1_Pages784to799 ((uint32_t)0x00020000)
#define | OB_WRP1_Pages800to815 ((uint32_t)0x00040000)
#define | OB_WRP1_Pages816to831 ((uint32_t)0x00080000)
#define | OB_WRP1_Pages832to847 ((uint32_t)0x00100000)
#define | OB_WRP1_Pages848to863 ((uint32_t)0x00200000)
#define | OB_WRP1_Pages864to879 ((uint32_t)0x00400000)
#define | OB_WRP1_Pages880to895 ((uint32_t)0x00800000)
#define | OB_WRP1_Pages896to911 ((uint32_t)0x01000000)
#define | OB_WRP1_Pages912to927 ((uint32_t)0x02000000)
#define | OB_WRP1_Pages928to943 ((uint32_t)0x04000000)
#define | OB_WRP1_Pages944to959 ((uint32_t)0x08000000)
#define | OB_WRP1_Pages960to975 ((uint32_t)0x10000000)
#define | OB_WRP1_Pages976to991 ((uint32_t)0x20000000)
#define | OB_WRP1_Pages992to1007 ((uint32_t)0x40000000)
#define | OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001)
#define | OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002)
#define | OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004)
#define | OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008)
#define | OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010)
#define | OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020)
#define | OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040)
#define | OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080)
#define | OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100)
#define | OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200)
#define | OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400)
#define | OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800)
#define | OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000)
#define | OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000)
#define | OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000)
#define | OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000)
#define | OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000)
#define | OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000)
#define | OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000)
#define | OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000)
#define | OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000)
#define | OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000)
#define | OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000)
#define | OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000)
#define | OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000)
#define | OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000)
#define | OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000)
#define | OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000)
#define | OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000)
#define | OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000)
#define | OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000)
#define | OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000)
#define | OB_WRP_AllPages ((uint32_t)0xFFFFFFFF)
#define | OB_WRP_Pages0to15 ((uint32_t)0x00000001)
#define | OB_WRP_Pages112to127 ((uint32_t)0x00000080)
#define | OB_WRP_Pages128to143 ((uint32_t)0x00000100)
#define | OB_WRP_Pages144to159 ((uint32_t)0x00000200)
#define | OB_WRP_Pages160to175 ((uint32_t)0x00000400)
#define | OB_WRP_Pages16to31 ((uint32_t)0x00000002)
#define | OB_WRP_Pages176to191 ((uint32_t)0x00000800)
#define | OB_WRP_Pages192to207 ((uint32_t)0x00001000)
#define | OB_WRP_Pages208to223 ((uint32_t)0x00002000)
#define | OB_WRP_Pages224to239 ((uint32_t)0x00004000)
#define | OB_WRP_Pages240to255 ((uint32_t)0x00008000)
#define | OB_WRP_Pages256to271 ((uint32_t)0x00010000)
#define | OB_WRP_Pages272to287 ((uint32_t)0x00020000)
#define | OB_WRP_Pages288to303 ((uint32_t)0x00040000)
#define | OB_WRP_Pages304to319 ((uint32_t)0x00080000)
#define | OB_WRP_Pages320to335 ((uint32_t)0x00100000)
#define | OB_WRP_Pages32to47 ((uint32_t)0x00000004)
#define | OB_WRP_Pages336to351 ((uint32_t)0x00200000)
#define | OB_WRP_Pages352to367 ((uint32_t)0x00400000)
#define | OB_WRP_Pages368to383 ((uint32_t)0x00800000)
#define | OB_WRP_Pages384to399 ((uint32_t)0x01000000)
#define | OB_WRP_Pages400to415 ((uint32_t)0x02000000)
#define | OB_WRP_Pages416to431 ((uint32_t)0x04000000)
#define | OB_WRP_Pages432to447 ((uint32_t)0x08000000)
#define | OB_WRP_Pages448to463 ((uint32_t)0x10000000)
#define | OB_WRP_Pages464to479 ((uint32_t)0x20000000)
#define | OB_WRP_Pages480to495 ((uint32_t)0x40000000)
#define | OB_WRP_Pages48to63 ((uint32_t)0x00000008)
#define | OB_WRP_Pages496to511 ((uint32_t)0x80000000)
#define | OB_WRP_Pages64to79 ((uint32_t)0x00000010)
#define | OB_WRP_Pages80to95 ((uint32_t)0x00000020)
#define | OB_WRP_Pages96to111 ((uint32_t)0x00000040)

Enumerations

enum FLASH_Status {
FLASH_BUSY = 1, FLASH_ERROR_WRP, FLASH_ERROR_PROGRAM, FLASH_COMPLETE,
FLASH_TIMEOUT
}

FLASH Status.

More...

Functions

FLASH_Status | DATA_EEPROM_EraseByte (uint32_t Address)
Erase a byte in data memory.
__RAM_FUNC | DATA_EEPROM_EraseDoubleWord (uint32_t Address)
Erase a double word in data memory.
FLASH_Status | DATA_EEPROM_EraseHalfWord (uint32_t Address)
Erase a halfword in data memory.
FLASH_Status | DATA_EEPROM_EraseWord (uint32_t Address)
Erase a word in data memory.
FLASH_Status | DATA_EEPROM_FastProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory.
FLASH_Status | DATA_EEPROM_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory.
void | DATA_EEPROM_FixedTimeProgramCmd (FunctionalState NewState)
Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
void | DATA_EEPROM_Lock (void)
Locks the Data memory and FLASH_PECR register access.
FLASH_Status | DATA_EEPROM_ProgramByte (uint32_t Address, uint8_t Data)
Write a Byte at a specified address in data memory without erase.
__RAM_FUNC | DATA_EEPROM_ProgramDoubleWord (uint32_t Address, uint64_t Data)
Write a double word in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramHalfWord (uint32_t Address, uint16_t Data)
Writes a half word at a specified address in data memory without erase.
FLASH_Status | DATA_EEPROM_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in data memory without erase.
void | DATA_EEPROM_Unlock (void)
Unlocks the data memory and FLASH_PECR register access.
void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified page in program memory.
__RAM_FUNC | FLASH_EraseParallelPage (uint32_t Page_Address1, uint32_t Page_Address2)
Erases a specified 2 page in program memory in parallel.
FLASH_Status | FLASH_FastProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address in program memory.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the Program memory access.
FLASH_Status | FLASH_OB_BootConfig (uint8_t OB_BOOT)
Configures to boot from Bank1 or Bank2.
FLASH_Status | FLASH_OB_BORConfig (uint8_t OB_BOR)
Programs the FLASH brownout reset threshold level Option Byte.
uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
FlagStatus | FLASH_OB_GetRDP (void)
Checks whether the FLASH Read out Protection Status is set or not.
uint8_t | FLASH_OB_GetUser (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_OB_GetWRP (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP1 (void)
Returns the FLASH Write Protection Option Bytes value.
uint32_t | FLASH_OB_GetWRP2 (void)
Returns the FLASH Write Protection Option Bytes value.
void | FLASH_OB_Launch (void)
Launch the option byte loading.
void | FLASH_OB_Lock (void)
Locks the option bytes block access.
FLASH_Status | FLASH_OB_RDPConfig (uint8_t OB_RDP)
Enables or disables the read out protection.
void | FLASH_OB_Unlock (void)
Unlocks the option bytes block access.
FLASH_Status | FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_OB_WRP1Config (uint32_t OB_WRP1, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRP2Config (uint32_t OB_WRP2, FunctionalState NewState)
Write protects the desired pages.
FLASH_Status | FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
Write protects the desired pages.
void | FLASH_PrefetchBufferCmd (FunctionalState NewState)
Enables or disables the Prefetch Buffer.
__RAM_FUNC | FLASH_ProgramHalfPage (uint32_t Address, uint32_t *pBuffer)
Programs a half page in program memory.
__RAM_FUNC | FLASH_ProgramParallelHalfPage (uint32_t Address1, uint32_t *pBuffer1, uint32_t Address2, uint32_t *pBuffer2)
Programs 2 half page in program memory in parallel.
void | FLASH_ReadAccess64Cmd (FunctionalState NewState)
Enables or disables read access to flash by 64 bits.
__RAM_FUNC | FLASH_RUNPowerDownCmd (FunctionalState NewState)
FLASH memory functions that should be executed from internal SRAM.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
FLASH memory functions that can be executed from FLASH.
void | FLASH_SLEEPPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during Sleep mode.
void | FLASH_Unlock (void)
Unlocks the FLASH control register and program memory access.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Detailed Description

This file contains all the functions prototypes for the FLASH firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_flash.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash_ramfunc.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Functions

stm32l1xx_flash_ramfunc.c File Reference

This file provides all the Flash firmware functions which should be executed from the internal SRAM. This file should be placed in internal SRAM. Other FLASH memory functions that can be used from the FLASH are defined in the "stm32l1xx_flash.c" file. More...

#include "stm32l1xx_flash.h"

Go to the source code of this file.

Functions

__RAM_FUNC | DATA_EEPROM_EraseDoubleWord (uint32_t Address)
Erase a double word in data memory.
__RAM_FUNC | DATA_EEPROM_ProgramDoubleWord (uint32_t Address, uint64_t Data)
Write a double word in data memory without erase.
FLASH_Status | FLASH_EraseParallelPage (uint32_t Page_Address1, uint32_t Page_Address2)
Erases a specified 2 page in program memory in parallel.
__RAM_FUNC | FLASH_ProgramHalfPage (uint32_t Address, uint32_t *pBuffer)
Programs a half page in program memory.
__RAM_FUNC | FLASH_ProgramParallelHalfPage (uint32_t Address1, uint32_t *pBuffer1, uint32_t Address2, uint32_t *pBuffer2)
Programs 2 half page in program memory in parallel.
__RAM_FUNC | FLASH_RUNPowerDownCmd (FunctionalState NewState)
Enable or disable the power down mode during RUN mode.
static __RAM_FUNC | GetStatus (void)
Returns the FLASH Status.
static __RAM_FUNC | WaitForLastOperation (uint32_t Timeout)
Waits for a FLASH operation to complete or a TIMEOUT to occur.

Detailed Description

This file provides all the Flash firmware functions which should be executed from the internal SRAM. This file should be placed in internal SRAM. Other FLASH memory functions that can be used from the FLASH are defined in the "stm32l1xx_flash.c" file.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

    *** ARM Compiler ***
    --------------------
    [..] RAM functions are defined using the toolchain options.
         Functions that are be executed in RAM should reside in a separate
         source module. Using the 'Options for File' dialog you can simply change
         the 'Code / Const' area of a module to a memory space in physical RAM.
         Available memory areas are declared in the 'Target' tab of the
         Options for Target' dialog.

    *** ICCARM Compiler ***
    -----------------------
    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".

    *** GNU Compiler ***
    --------------------
    [..] RAM functions are defined using a specific toolchain attribute
         "__attribute__((section(".data")))".

    *** TASKING Compiler ***
    ------------------------
    [..] RAM functions are defined using a specific toolchain pragma. This
         pragma is defined inside this file.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_flash_ramfunc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_fsmc.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Functions

stm32l1xx_fsmc.c File Reference

This file provides firmware functions to manage the following functionalities of the FSMC peripheral: + Initialization + Interrupts and flags management. More...

#include "stm32l1xx_fsmc.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Functions

void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.

Detailed Description

This file provides firmware functions to manage the following functionalities of the FSMC peripheral: + Initialization + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_fsmc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_fsmc.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_fsmc.h File Reference

This file contains all the functions prototypes for the FSMC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | FSMC_NORSRAMInitTypeDef
FSMC NOR/SRAM Init structure definition. More...
struct | FSMC_NORSRAMTimingInitTypeDef
Timing parameters For NOR/SRAM Banks. More...

Defines

#define | FSMC_AccessMode_A ((uint32_t)0x00000000)
#define | FSMC_AccessMode_B ((uint32_t)0x10000000)
#define | FSMC_AccessMode_C ((uint32_t)0x20000000)
#define | FSMC_AccessMode_D ((uint32_t)0x30000000)
#define | FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define | FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define | FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define | FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define | FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define | FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define | FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define | FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define | FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define | FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define | FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define | FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define | FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define | FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define | FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define | FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define | FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define | FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define | FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define | FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define | FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define | FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define | FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define | FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define | FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define | IS_FSMC_ACCESS_MODE(MODE)
#define | IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_ASYNWAIT(STATE)
#define | IS_FSMC_BURSTMODE(STATE)
#define | IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
#define | IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
#define | IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
#define | IS_FSMC_EXTENDED_MODE(MODE)
#define | IS_FSMC_MEMORY(MEMORY)
#define | IS_FSMC_MEMORY_WIDTH(WIDTH)
#define | IS_FSMC_MUX(MUX)
#define | IS_FSMC_NORSRAM_BANK(BANK)
#define | IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_WAIT_POLARITY(POLARITY)
#define | IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
#define | IS_FSMC_WAITE_SIGNAL(SIGNAL)
#define | IS_FSMC_WRAP_MODE(MODE)
#define | IS_FSMC_WRITE_BURST(BURST)
#define | IS_FSMC_WRITE_OPERATION(OPERATION)

Functions

void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.

Detailed Description

This file contains all the functions prototypes for the FSMC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_fsmc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_gpio.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Functions

stm32l1xx_gpio.c File Reference

This file provides firmware functions to manage the following functionalities of the GPIO peripheral: + Initialization and Configuration + GPIO Read and Write + GPIO Alternate functions configuration. More...

#include "stm32l1xx_gpio.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
Changes the mapping of the specified pin.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

This file provides firmware functions to manage the following functionalities of the GPIO peripheral: + Initialization and Configuration + GPIO Read and Write + GPIO Alternate functions configuration.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
    ===========================================================================
                         ##### How to use this driver #####
    ===========================================================================
      [..]
      (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
      (#) Configure the GPIO pin(s) using GPIO_Init()
          Four possible configuration are available for each pin:
         (++) Input: Floating, Pull-up, Pull-down.
         (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
              Open Drain (Pull-up, Pull-down or no Pull).
              In output mode, the speed is configurable: Very Low, Low,
              Medium or High.
         (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
              Open Drain (Pull-up, Pull-down or no Pull).
         (++) Analog: required mode when a pin is to be used as ADC channel,
              DAC output or comparator input.
      (#) Peripherals alternate function:
          (++) For ADC, DAC and comparators, configure the desired pin in
               analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
          (++) For other peripherals (TIM, USART...):
              (+++) Connect the pin to the desired peripherals' Alternate
                    Function (AF) using GPIO_PinAFConfig() function.
              (+++) Configure the desired pin in alternate function mode using
                    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
              (+++) Select the type, pull-up/pull-down and output speed via
                    GPIO_PuPd, GPIO_OType and GPIO_Speed members.
              (+++) Call GPIO_Init() function.
      (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
      (#) To set/reset the level of a pin configured in output mode use
          GPIO_SetBits()/GPIO_ResetBits()
      (#) During and just after reset, the alternate functions are not
          active and the GPIO pins are configured in input floating mode
          (except JTAG pins).
      (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
          general-purpose (PC14 and PC15, respectively) when the LSE
          oscillator is off. The LSE has priority over the GPIO function.
      (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
          general-purpose PH0 and PH1, respectively, when the HSE
          oscillator is off. The HSE has priority over the GPIO function.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_gpio.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_gpio.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Enumerations | Functions

stm32l1xx_gpio.h File Reference

This file contains all the functions prototypes for the GPIO firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_AF_EVENTOUT ((uint8_t)0x0F)
AF 15 selection.
#define | GPIO_AF_FSMC ((uint8_t)0x0C)
AF 12 selection.
#define | GPIO_AF_I2C1 ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF_I2C2 ((uint8_t)0x04)
#define | GPIO_AF_LCD ((uint8_t)0x0B)
AF 11 selection.
#define | GPIO_AF_MCO ((uint8_t)0x00)
#define | GPIO_AF_RI ((uint8_t)0x0E)
AF 14 selection.
#define | GPIO_AF_RTC_50Hz ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF_RTC_AF1 ((uint8_t)0x00)
#define | GPIO_AF_SDIO ((uint8_t)0x0C)
#define | GPIO_AF_SPI1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF_SPI2 ((uint8_t)0x05)
#define | GPIO_AF_SPI3 ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF_SWJ ((uint8_t)0x00)
#define | GPIO_AF_TIM10 ((uint8_t)0x03)
#define | GPIO_AF_TIM11 ((uint8_t)0x03)
#define | GPIO_AF_TIM2 ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF_TIM3 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF_TIM4 ((uint8_t)0x02)
#define | GPIO_AF_TIM5 ((uint8_t)0x02)
#define | GPIO_AF_TIM9 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF_TRACE ((uint8_t)0x00)
#define | GPIO_AF_UART4 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF_UART5 ((uint8_t)0x08)
#define | GPIO_AF_USART1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF_USART2 ((uint8_t)0x07)
#define | GPIO_AF_USART3 ((uint8_t)0x07)
#define | GPIO_AF_USB ((uint8_t)0xA)
AF 10 selection.
#define | GPIO_AF_WKUP ((uint8_t)0x00)
#define | GPIO_Mode_AIN GPIO_Mode_AN
#define | GPIO_Pin_0 ((uint16_t)0x0001)
#define | GPIO_Pin_1 ((uint16_t)0x0002)
#define | GPIO_Pin_10 ((uint16_t)0x0400)
#define | GPIO_Pin_11 ((uint16_t)0x0800)
#define | GPIO_Pin_12 ((uint16_t)0x1000)
#define | GPIO_Pin_13 ((uint16_t)0x2000)
#define | GPIO_Pin_14 ((uint16_t)0x4000)
#define | GPIO_Pin_15 ((uint16_t)0x8000)
#define | GPIO_Pin_2 ((uint16_t)0x0004)
#define | GPIO_Pin_3 ((uint16_t)0x0008)
#define | GPIO_Pin_4 ((uint16_t)0x0010)
#define | GPIO_Pin_5 ((uint16_t)0x0020)
#define | GPIO_Pin_6 ((uint16_t)0x0040)
#define | GPIO_Pin_7 ((uint16_t)0x0080)
#define | GPIO_Pin_8 ((uint16_t)0x0100)
#define | GPIO_Pin_9 ((uint16_t)0x0200)
#define | GPIO_Pin_All ((uint16_t)0xFFFF)
#define | GPIO_PinSource0 ((uint8_t)0x00)
#define | GPIO_PinSource1 ((uint8_t)0x01)
#define | GPIO_PinSource10 ((uint8_t)0x0A)
#define | GPIO_PinSource11 ((uint8_t)0x0B)
#define | GPIO_PinSource12 ((uint8_t)0x0C)
#define | GPIO_PinSource13 ((uint8_t)0x0D)
#define | GPIO_PinSource14 ((uint8_t)0x0E)
#define | GPIO_PinSource15 ((uint8_t)0x0F)
#define | GPIO_PinSource2 ((uint8_t)0x02)
#define | GPIO_PinSource3 ((uint8_t)0x03)
#define | GPIO_PinSource4 ((uint8_t)0x04)
#define | GPIO_PinSource5 ((uint8_t)0x05)
#define | GPIO_PinSource6 ((uint8_t)0x06)
#define | GPIO_PinSource7 ((uint8_t)0x07)
#define | GPIO_PinSource8 ((uint8_t)0x08)
#define | GPIO_PinSource9 ((uint8_t)0x09)
#define | IS_GET_GPIO_PIN(PIN)
#define | IS_GPIO_AF(AF)
#define | IS_GPIO_ALL_PERIPH(PERIPH)
#define | IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
#define | IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define | IS_GPIO_PIN_SOURCE(PINSOURCE)
#define | IS_GPIO_PUPD(PUPD)
#define | IS_GPIO_SPEED(SPEED)

Enumerations

enum | BitAction { Bit_RESET = 0, Bit_SET }
enum | GPIOMode_TypeDef { GPIO_Mode_IN = 0x00, GPIO_Mode_OUT = 0x01, GPIO_Mode_AF = 0x02, GPIO_Mode_AN = 0x03 }
enum | GPIOOType_TypeDef { GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01 }
enum | GPIOPuPd_TypeDef { GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02 }
enum | GPIOSpeed_TypeDef { GPIO_Speed_400KHz = 0x00, GPIO_Speed_2MHz = 0x01, GPIO_Speed_10MHz = 0x02, GPIO_Speed_40MHz = 0x03 }

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
Changes the mapping of the specified pin.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

This file contains all the functions prototypes for the GPIO firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_gpio.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_i2c.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_i2c.c File Reference

This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C) + Initialization and Configuration + Data transfers + PEC management + DMA transfers management + Interrupts, events and flags management. More...

#include "stm32l1xx_i2c.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_CLEAR_MASK ((uint16_t)0xFBF5)
#define | FLAG_MASK ((uint32_t)0x00FFFFFF)
#define | ITEN_MASK ((uint32_t)0x07000000)

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
Checks whether the last I2Cx Event is equal to the one passed as parameter.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C) + Initialization and Configuration + Data transfers + PEC management + DMA transfers management + Interrupts, events and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  *
  * ============================================================================
  *                    ##### How to use this driver #####
  * ============================================================================
   [..]
   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
       function for I2C1 or I2C2.
   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using
       RCC_AHBPeriphClockCmd() function.
   (#) Peripherals alternate function:
       (++) Connect the pin to the desired peripherals' Alternate
            Function (AF) using GPIO_PinAFConfig() function.
       (++) Configure the desired pin in alternate function by:
            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
       (++) Select the type, pull-up/pull-down and output speed via
            GPIO_PuPd, GPIO_OType and GPIO_Speed members
       (++) Call GPIO_Init() function.
   (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
       Address using the I2C_Init() function.
   (#) Optionally you can enable/configure the following parameters without
       re-initialization (i.e there is no need to call again I2C_Init() function):
       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
       (++) Enable the general call using the I2C_GeneralCallCmd() function.
       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
       (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
            function.
       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
       (++) For SMBus Mode:
            (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function.
            (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function.
   (#) Enable the NVIC and the corresponding interrupt using the function
       I2C_ITConfig() if you need to use interrupt mode.
   (#) When using the DMA mode
      (++) Configure the DMA using DMA_Init() function.
      (++) Active the needed channel Request using I2C_DMACmd() or
           I2C_DMALastTransferCmd() function.
   (#) Enable the I2C using the I2C_Cmd() function.
   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
       transfers.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_i2c.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_i2c.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_i2c.h File Reference

This file contains all the functions prototypes for the I2C firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
I2C Init structure definition. More...

Defines

#define | I2C_Ack_Disable ((uint16_t)0x0000)
#define | I2C_Ack_Enable ((uint16_t)0x0400)
#define | I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define | I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define | I2C_Direction_Receiver ((uint8_t)0x01)
#define | I2C_Direction_Transmitter ((uint8_t)0x00)
#define | I2C_DutyCycle_16_9 ((uint16_t)0x4000)
#define | I2C_DutyCycle_2 ((uint16_t)0xBFFF)
#define | I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)
Communication events.
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)
#define | I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)
#define | I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)
=============================================================================== I2C Master Events (Events grouped in order of communication) ===============================================================================
#define | I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)
#define | I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)
Address Acknowledge.
#define | I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)
#define | I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)
Communication events.
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)
#define | I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)
#define | I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)
=============================================================================== I2C Slave Events (Events grouped in order of communication) ===============================================================================
#define | I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)
#define | I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)
#define | I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)
#define | I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)
#define | I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define | I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define | I2C_FLAG_AF ((uint32_t)0x10000400)
#define | I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define | I2C_FLAG_BERR ((uint32_t)0x10000100)
#define | I2C_FLAG_BTF ((uint32_t)0x10000004)
#define | I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define | I2C_FLAG_DUALF ((uint32_t)0x00800000)
SR2 register flags.
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define | I2C_FLAG_MSL ((uint32_t)0x00010000)
#define | I2C_FLAG_OVR ((uint32_t)0x10000800)
#define | I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define | I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define | I2C_FLAG_SB ((uint32_t)0x10000001)
#define | I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
SR1 register flags.
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define | I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define | I2C_FLAG_TRA ((uint32_t)0x00040000)
#define | I2C_FLAG_TXE ((uint32_t)0x10000080)
#define | I2C_IT_ADD10 ((uint32_t)0x02000008)
#define | I2C_IT_ADDR ((uint32_t)0x02000002)
#define | I2C_IT_AF ((uint32_t)0x01000400)
#define | I2C_IT_ARLO ((uint32_t)0x01000200)
#define | I2C_IT_BERR ((uint32_t)0x01000100)
#define | I2C_IT_BTF ((uint32_t)0x02000004)
#define | I2C_IT_BUF ((uint16_t)0x0400)
#define | I2C_IT_ERR ((uint16_t)0x0100)
#define | I2C_IT_EVT ((uint16_t)0x0200)
#define | I2C_IT_OVR ((uint32_t)0x01000800)
#define | I2C_IT_PECERR ((uint32_t)0x01001000)
#define | I2C_IT_RXNE ((uint32_t)0x06000040)
#define | I2C_IT_SB ((uint32_t)0x02000001)
#define | I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define | I2C_IT_STOPF ((uint32_t)0x02000010)
#define | I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define | I2C_IT_TXE ((uint32_t)0x06000080)
#define | I2C_Mode_I2C ((uint16_t)0x0000)
#define | I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define | I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define | I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define | I2C_NACKPosition_Next ((uint16_t)0x0800)
#define | I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define | I2C_PECPosition_Next ((uint16_t)0x0800)
#define | I2C_Register_CCR ((uint8_t)0x1C)
#define | I2C_Register_CR1 ((uint8_t)0x00)
#define | I2C_Register_CR2 ((uint8_t)0x04)
#define | I2C_Register_DR ((uint8_t)0x10)
#define | I2C_Register_OAR1 ((uint8_t)0x08)
#define | I2C_Register_OAR2 ((uint8_t)0x0C)
#define | I2C_Register_SR1 ((uint8_t)0x14)
#define | I2C_Register_SR2 ((uint8_t)0x18)
#define | I2C_Register_TRISE ((uint8_t)0x20)
#define | I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define | I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define | IS_I2C_ACK_STATE(STATE)
#define | IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
#define | IS_I2C_ALL_PERIPH(PERIPH)
#define | IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
#define | IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
#define | IS_I2C_DIRECTION(DIRECTION)
#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_EVENT(EVENT)
#define | IS_I2C_GET_FLAG(FLAG)
#define | IS_I2C_GET_IT(IT)
#define | IS_I2C_MODE(MODE)
#define | IS_I2C_NACK_POSITION(POSITION)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
#define | IS_I2C_PEC_POSITION(POSITION)
#define | IS_I2C_REGISTER(REGISTER)
#define | IS_I2C_SMBUS_ALERT(ALERT)

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
Checks whether the last I2Cx Event is equal to the one passed as parameter.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

This file contains all the functions prototypes for the I2C firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_i2c.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_iwdg.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • src
Defines | Functions

stm32l1xx_iwdg.c File Reference

This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral: + Prescaler and Counter configuration + IWDG activation + Flag management. More...

#include "stm32l1xx_iwdg.h"

Go to the source code of this file.

Defines

#define | KR_KEY_ENABLE ((uint16_t)0xCCCC)
#define | KR_KEY_RELOAD ((uint16_t)0xAAAA)

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral: + Prescaler and Counter configuration + IWDG activation + Flag management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  *
  ==============================================================================
                          ##### IWDG features #####
  ==============================================================================
    [..] The IWDG can be started by either software or hardware (configurable
         through option byte).

    [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
         thus stays active even if the main clock fails.
         Once the IWDG is started, the LSI is forced ON and cannot be disabled
         (LSI cannot be disabled too), and the counter starts counting down from
         the reset value of 0xFFF. When it reaches the end of count value (0x000)
         a system reset is generated.
         The IWDG counter should be reloaded at regular intervals to prevent
         an MCU reset.

    [..] The IWDG is implemented in the VDD voltage domain that is still functional
         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).

    [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
         reset occurs.

    [..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM10 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.
         For more information, please refer to the STM32L1xx Reference manual.

                          ##### How to use this driver #####
  ==============================================================================
    [..]
    (#) Enable write access to IWDG_PR and IWDG_RLR registers using
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
    (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.

    (#) Configure the IWDG counter value using IWDG_SetReload() function.
        This value will be loaded in the IWDG counter each time the counter
        is reloaded, then the IWDG will start counting down from this value.

    (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
        in software mode (no need to enable the LSI, it will be enabled
        by hardware).

    (#) Then the application program must reload the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        IWDG_ReloadCounter() function.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_iwdg.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_iwdg.h File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Functions

stm32l1xx_iwdg.h File Reference

This file contains all the functions prototypes for the IWDG firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define | IS_IWDG_PRESCALER(PRESCALER)
#define | IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
#define | IS_IWDG_WRITE_ACCESS(ACCESS)
#define | IWDG_FLAG_PVU ((uint16_t)0x0001)
#define | IWDG_FLAG_RVU ((uint16_t)0x0002)
#define | IWDG_Prescaler_128 ((uint8_t)0x05)
#define | IWDG_Prescaler_16 ((uint8_t)0x02)
#define | IWDG_Prescaler_256 ((uint8_t)0x06)
#define | IWDG_Prescaler_32 ((uint8_t)0x03)
#define | IWDG_Prescaler_4 ((uint8_t)0x00)
#define | IWDG_Prescaler_64 ((uint8_t)0x04)
#define | IWDG_Prescaler_8 ((uint8_t)0x01)
#define | IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define | IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

This file contains all the functions prototypes for the IWDG firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_iwdg.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_lcd.c File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_lcd.c File Reference

This file provides firmware functions to manage the following functionalities of the LCD controller (LCD) peripheral: + Initialization and configuration + LCD RAM memory write + Interrupts and flags management. More...

#include "stm32l1xx_lcd.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | BLINK_MASK ((uint32_t)0xFFFC1FFF)
#define | CONTRAST_MASK ((uint32_t)0xFFFFE3FF)
#define | CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))
#define | CR_MASK ((uint32_t)0xFFFFFF81)
#define | CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))
#define | CR_OFFSET (LCD_OFFSET + 0x00)
#define | DEAD_MASK ((uint32_t)0xFFFFFC7F)
#define | FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))
#define | FCR_MASK ((uint32_t)0xFC03FFFF)
#define | FCR_OFFSET (LCD_OFFSET + 0x04)
#define | HD_BitNumber 0x00
#define | LCD_OFFSET (LCD_BASE - PERIPH_BASE)
#define | LCDEN_BitNumber 0x00
#define | MUX_SEG_BitNumber 0x07
#define | PON_MASK ((uint32_t)0xFFFFFF8F)
#define | SR_OFFSET (LCD_OFFSET + 0x08)
#define | SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))
#define | UDR_BitNumber 0x02

Functions

void | LCD_BlinkConfig (uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
Configures the LCD Blink mode and Blink frequency.
void | LCD_ClearFlag (uint32_t LCD_FLAG)
Clears the LCD's pending flags.
void | LCD_ClearITPendingBit (uint32_t LCD_IT)
Clears the LCD's interrupt pending bits.
void | LCD_Cmd (FunctionalState NewState)
Enables or disables the LCD Controller.
void | LCD_ContrastConfig (uint32_t LCD_Contrast)
Configures the LCD Contrast.
void | LCD_DeadTimeConfig (uint32_t LCD_DeadTime)
Configures the LCD dead time.
void | LCD_DeInit (void)
Deinitializes the LCD peripheral registers to their default reset values.
FlagStatus | LCD_GetFlagStatus (uint32_t LCD_FLAG)
Checks whether the specified LCD flag is set or not.
ITStatus | LCD_GetITStatus (uint32_t LCD_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | LCD_HighDriveCmd (FunctionalState NewState)
Enables or disables the low resistance divider.
void | LCD_Init (LCD_InitTypeDef *LCD_InitStruct)
Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.
void | LCD_ITConfig (uint32_t LCD_IT, FunctionalState NewState)
Enables or disables the specified LCD interrupts.
void | LCD_MuxSegmentCmd (FunctionalState NewState)
Enables or disables the Mux Segment.
void | LCD_PulseOnDurationConfig (uint32_t LCD_PulseOnDuration)
Configures the LCD pulses on duration.
void | LCD_StructInit (LCD_InitTypeDef *LCD_InitStruct)
Fills each LCD_InitStruct member with its default value.
void | LCD_UpdateDisplayRequest (void)
Enables the Update Display Request.
void | LCD_WaitForSynchro (void)
Waits until the LCD FCR register is synchronized in the LCDCLK domain.
void | LCD_Write (uint32_t LCD_RAMRegister, uint32_t LCD_Data)
Writes a word in the specific LCD RAM.

Detailed Description

This file provides firmware functions to manage the following functionalities of the LCD controller (LCD) peripheral: + Initialization and configuration + LCD RAM memory write + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

 ===============================================================================
                            ##### LCD Clock #####
 ===============================================================================
    [..] LCDCLK is the same as RTCCLK.
    [..] To configure the RTCCLK/LCDCLK, proceed as follows:
         (+) Enable the Power Controller (PWR) APB1 interface clock using the
             RCC_APB1PeriphClockCmd() function.
         (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
         (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.

    [..] The frequency generator allows you to achieve various LCD frame rates
         starting from an LCD input clock frequency (LCDCLK) which can vary
         from 32 kHz up to 1 MHz.

                      ##### LCD and low power modes #####
 ===============================================================================
    [..] The LCD still active during STOP mode.

                      ##### How to use this driver #####
 ===============================================================================
    [..]
        (#) Enable LCD clock using
            RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function.
        (#) Configure the LCD prescaler, divider, duty, bias and voltage source
            using LCD_Init() function.
        (#) Optionally you can enable/configure:
            (++) LCD High Drive using the LCD_HighDriveCmd() function.
            (++) LCD COM/SEG Mux using the LCD_MuxSegmentCmd() function.
            (++) LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function.
            (++) LCD Dead Time using the LCD_DeadTimeConfig() function
            (++) The LCD Blink mode and frequency using the LCD_BlinkConfig() function.
            (++) The LCD Contrast using the LCD_ContrastConfig() function.
        (#) Call the LCD_WaitForSynchro() function to wait for LCD_FCR register
            synchronization.
        (#) Call the LCD_Cmd() to enable the LCD controller.
        (#) Wait until the LCD Controller status is enabled and the step-up
            converter is ready using the LCD_GetFlagStatus() and
            LCD_FLAG_ENS and LCD_FLAG_RDY flags.
        (#) Write to the LCD RAM memory using the LCD_Write() function.
        (#) Request an update display using the LCD_UpdateDisplayRequest()
            function.
        (#) Wait until the update display is finished by checking the UDD
            flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD).
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_lcd.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_lcd.h File Reference

  • File List
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Data Structures | Defines | Functions

stm32l1xx_lcd.h File Reference

This file contains all the functions prototypes for the LCD firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...

Defines

#define | IS_LCD_BIAS(BIAS)
#define | IS_LCD_BLINK_FREQUENCY(FREQUENCY)
#define | IS_LCD_BLINK_MODE(MODE)
#define | IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))
#define | IS_LCD_CONTRAST(CONTRAST)
#define | IS_LCD_DEAD_TIME(TIME)
#define | IS_LCD_DIVIDER(DIVIDER)
#define | IS_LCD_DUTY(DUTY)
#define | IS_LCD_GET_FLAG(FLAG)
#define | IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))
#define | IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))
#define | IS_LCD_PRESCALER(PRESCALER)
#define | IS_LCD_PULSE_ON_DURATION(DURATION)
#define | IS_LCD_RAM_REGISTER(REGISTER)
#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | LCD_Bias_1_2 LCD_CR_BIAS_0
#define | LCD_Bias_1_3 LCD_CR_BIAS_1
#define | LCD_Bias_1_4 ((uint32_t)0x00000000)
#define | LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000)
#define | LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000)
#define | LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000)
#define | LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000)
#define | LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000)
#define | LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000)
#define | LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000)
#define | LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000)
#define | LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000)
#define | LCD_BlinkMode_Off ((uint32_t)0x00000000)
#define | LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000)
#define | LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000)
#define | LCD_Contrast_Level_0 ((uint32_t)0x00000000)
#define | LCD_Contrast_Level_1 ((uint32_t)0x00000400)
#define | LCD_Contrast_Level_2 ((uint32_t)0x00000800)
#define | LCD_Contrast_Level_3 ((uint32_t)0x00000C00)
#define | LCD_Contrast_Level_4 ((uint32_t)0x00001000)
#define | LCD_Contrast_Level_5 ((uint32_t)0x00001400)
#define | LCD_Contrast_Level_6 ((uint32_t)0x00001800)
#define | LCD_Contrast_Level_7 ((uint32_t)0x00001C00)
#define | LCD_DeadTime_0 ((uint32_t)0x00000000)
#define | LCD_DeadTime_1 ((uint32_t)0x00000080)
#define | LCD_DeadTime_2 ((uint32_t)0x00000100)
#define | LCD_DeadTime_3 ((uint32_t)0x00000180)
#define | LCD_DeadTime_4 ((uint32_t)0x00000200)
#define | LCD_DeadTime_5 ((uint32_t)0x00000280)
#define | LCD_DeadTime_6 ((uint32_t)0x00000300)
#define | LCD_DeadTime_7 ((uint32_t)0x00000380)
#define | LCD_Divider_16 ((uint32_t)0x00000000)
#define | LCD_Divider_17 ((uint32_t)0x00040000)
#define | LCD_Divider_18 ((uint32_t)0x00080000)
#define | LCD_Divider_19 ((uint32_t)0x000C0000)
#define | LCD_Divider_20 ((uint32_t)0x00100000)
#define | LCD_Divider_21 ((uint32_t)0x00140000)
#define | LCD_Divider_22 ((uint32_t)0x00180000)
#define | LCD_Divider_23 ((uint32_t)0x001C0000)
#define | LCD_Divider_24 ((uint32_t)0x00200000)
#define | LCD_Divider_25 ((uint32_t)0x00240000)
#define | LCD_Divider_26 ((uint32_t)0x00280000)
#define | LCD_Divider_27 ((uint32_t)0x002C0000)
#define | LCD_Divider_28 ((uint32_t)0x00300000)
#define | LCD_Divider_29 ((uint32_t)0x00340000)
#define | LCD_Divider_30 ((uint32_t)0x00380000)
#define | LCD_Divider_31 ((uint32_t)0x003C0000)
#define | LCD_Duty_1_2 ((uint32_t)0x00000004)
#define | LCD_Duty_1_3 ((uint32_t)0x00000008)
#define | LCD_Duty_1_4 ((uint32_t)0x0000000C)
#define | LCD_Duty_1_8 ((uint32_t)0x00000010)
#define | LCD_Duty_Static ((uint32_t)0x00000000)
#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_UDR LCD_SR_UDR
#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE
#define | LCD_Prescaler_1 ((uint32_t)0x00000000)
#define | LCD_Prescaler_1024 ((uint32_t)0x02800000)
#define | LCD_Prescaler_128 ((uint32_t)0x01C00000)
#define | LCD_Prescaler_16 ((uint32_t)0x01000000)
#define | LCD_Prescaler_16384 ((uint32_t)0x03800000)
#define | LCD_Prescaler_2 ((uint32_t)0x00400000)
#define | LCD_Prescaler_2048 ((uint32_t)0x02C00000)
#define | LCD_Prescaler_256 ((uint32_t)0x02000000)
#define | LCD_Prescaler_32 ((uint32_t)0x01400000)
#define | LCD_Prescaler_32768 ((uint32_t)0x03C00000)
#define | LCD_Prescaler_4 ((uint32_t)0x00800000)
#define | LCD_Prescaler_4096 ((uint32_t)0x03000000)
#define | LCD_Prescaler_512 ((uint32_t)0x02400000)
#define | LCD_Prescaler_64 ((uint32_t)0x01800000)
#define | LCD_Prescaler_8 ((uint32_t)0x00C00000)
#define | LCD_Prescaler_8192 ((uint32_t)0x03400000)
#define | LCD_PulseOnDuration_0 ((uint32_t)0x00000000)
#define | LCD_PulseOnDuration_1 ((uint32_t)0x00000010)
#define | LCD_PulseOnDuration_2 ((uint32_t)0x00000020)
#define | LCD_PulseOnDuration_3 ((uint32_t)0x00000030)
#define | LCD_PulseOnDuration_4 ((uint32_t)0x00000040)
#define | LCD_PulseOnDuration_5 ((uint32_t)0x00000050)
#define | LCD_PulseOnDuration_6 ((uint32_t)0x00000060)
#define | LCD_PulseOnDuration_7 ((uint32_t)0x00000070)
#define | LCD_RAMRegister_0 ((uint32_t)0x00000000)
#define | LCD_RAMRegister_1 ((uint32_t)0x00000001)
#define | LCD_RAMRegister_10 ((uint32_t)0x0000000A)
#define | LCD_RAMRegister_11 ((uint32_t)0x0000000B)
#define | LCD_RAMRegister_12 ((uint32_t)0x0000000C)
#define | LCD_RAMRegister_13 ((uint32_t)0x0000000D)
#define | LCD_RAMRegister_14 ((uint32_t)0x0000000E)
#define | LCD_RAMRegister_15 ((uint32_t)0x0000000F)
#define | LCD_RAMRegister_2 ((uint32_t)0x00000002)
#define | LCD_RAMRegister_3 ((uint32_t)0x00000003)
#define | LCD_RAMRegister_4 ((uint32_t)0x00000004)
#define | LCD_RAMRegister_5 ((uint32_t)0x00000005)
#define | LCD_RAMRegister_6 ((uint32_t)0x00000006)
#define | LCD_RAMRegister_7 ((uint32_t)0x00000007)
#define | LCD_RAMRegister_8 ((uint32_t)0x00000008)
#define | LCD_RAMRegister_9 ((uint32_t)0x00000009)
#define | LCD_VoltageSource_External LCD_CR_VSEL
#define | LCD_VoltageSource_Internal ((uint32_t)0x00000000)

Functions

void | LCD_BlinkConfig (uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
Configures the LCD Blink mode and Blink frequency.
void | LCD_ClearFlag (uint32_t LCD_FLAG)
Clears the LCD's pending flags.
void | LCD_ClearITPendingBit (uint32_t LCD_IT)
Clears the LCD's interrupt pending bits.
void | LCD_Cmd (FunctionalState NewState)
Enables or disables the LCD Controller.
void | LCD_ContrastConfig (uint32_t LCD_Contrast)
Configures the LCD Contrast.
void | LCD_DeadTimeConfig (uint32_t LCD_DeadTime)
Configures the LCD dead time.
void | LCD_DeInit (void)
Deinitializes the LCD peripheral registers to their default reset values.
FlagStatus | LCD_GetFlagStatus (uint32_t LCD_FLAG)
Checks whether the specified LCD flag is set or not.
ITStatus | LCD_GetITStatus (uint32_t LCD_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | LCD_HighDriveCmd (FunctionalState NewState)
Enables or disables the low resistance divider.
void | LCD_Init (LCD_InitTypeDef *LCD_InitStruct)
Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct.
void | LCD_ITConfig (uint32_t LCD_IT, FunctionalState NewState)
Enables or disables the specified LCD interrupts.
void | LCD_MuxSegmentCmd (FunctionalState NewState)
Enables or disables the Mux Segment.
void | LCD_PulseOnDurationConfig (uint32_t LCD_PulseOnDuration)
Configures the LCD pulses on duration.
void | LCD_StructInit (LCD_InitTypeDef *LCD_InitStruct)
Fills each LCD_InitStruct member with its default value.
void | LCD_UpdateDisplayRequest (void)
Enables the Update Display Request.
void | LCD_WaitForSynchro (void)
Waits until the LCD FCR register is synchronized in the LCDCLK domain.
void | LCD_Write (uint32_t LCD_RAMRegister, uint32_t LCD_Data)
Writes a word in the specific LCD RAM.

Detailed Description

This file contains all the functions prototypes for the LCD firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_lcd.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_opamp.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Functions

stm32l1xx_opamp.c File Reference

This file provides firmware functions to manage the following functionalities of the operational amplifiers (opamp) peripheral: + Initialization and configuration + Calibration management. More...

#include "stm32l1xx_opamp.h"

Go to the source code of this file.

Functions

void | OPAMP_Cmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the OPAMP peripheral.
void | OPAMP_DeInit (void)
Deinitialize the OPAMPs register to its default reset value.
FlagStatus | OPAMP_GetFlagStatus (uint32_t OPAMP_Selection)
Checks whether the specified OPAMP calibration flag is set or not.
void | OPAMP_LowPowerCmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the low power mode for OPAMP peripheral.
void | OPAMP_OffsetTrimConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in normal mode.
void | OPAMP_OffsetTrimLowPowerConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in low power mode.
void | OPAMP_OffsetTrimmingModeSelect (uint32_t OPAMP_Trimming)
Select the trimming mode.
void | OPAMP_PowerRangeSelect (uint32_t OPAMP_PowerRange)
Select the OPAMP power range.
void | OPAMP_SwitchCmd (uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
Close or Open the OPAMP switches.

Detailed Description

This file provides firmware functions to manage the following functionalities of the operational amplifiers (opamp) peripheral: + Initialization and configuration + Calibration management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  ==============================================================================
                            ##### How to use this driver #####
  ==============================================================================
    [..] The device integrates three independent rail-to-rail operational amplifiers
         OPAMP1, OPAMP2 and OPAMP3:
               (+) Internal connections to the ADC.
               (+) Internal connections to the DAC.
               (+) Internal connection to COMP1 (only OPAMP3).
               (+) Internal connection for unity gain (voltage follower) configuration.
               (+) Calibration capability.
               (+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).
    [..]
         (#) COMP AHB clock must be enabled to get write access
             to OPAMP registers using
         (#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)

         (#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)
             and OPAMPx_OUT in analog mode.

         (#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()

         (#) Enable the OPAMP peripheral using OPAMP_Cmd()

         -@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled
             and the ADC must use the OPAMP output channel number:
             (+@) OPAMP1 output is connected to ADC channel 3.
             (+@) OPAMP2 output is connected to ADC channel 8.
             (+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).

  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_opamp.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_opamp.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Functions

stm32l1xx_opamp.h File Reference

This file contains all the functions prototypes for the operational amplifiers (opamp) firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | IS_OPAMP_ALL_PERIPH(PERIPH)
#define | IS_OPAMP_INPUT(INPUT)
#define | IS_OPAMP_RANGE(RANGE)
#define | IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F)
#define | OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H
#define | OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L
#define | OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1
#define | OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1
#define | OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1
#define | OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1
#define | OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1
#define | OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2
#define | OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2
#define | OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2
#define | OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2
#define | OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2
#define | OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2
#define | OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3
#define | OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3
#define | OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3
#define | OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3
#define | OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3
#define | OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE
#define | OPAMP_PowerRange_Low ((uint32_t)0x00000000)
#define | OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD
#define | OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD
#define | OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD
#define | OPAMP_Trimming_Factory ((uint32_t)0x00000000)
#define | OPAMP_Trimming_User OPAMP_OTR_OT_USER

Functions

void | OPAMP_Cmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the OPAMP peripheral.
void | OPAMP_DeInit (void)
Deinitialize the OPAMPs register to its default reset value.
FlagStatus | OPAMP_GetFlagStatus (uint32_t OPAMP_Selection)
Checks whether the specified OPAMP calibration flag is set or not.
void | OPAMP_LowPowerCmd (uint32_t OPAMP_Selection, FunctionalState NewState)
Enable or disable the low power mode for OPAMP peripheral.
void | OPAMP_OffsetTrimConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in normal mode.
void | OPAMP_OffsetTrimLowPowerConfig (uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
Configure the trimming value of OPAMPs in low power mode.
void | OPAMP_OffsetTrimmingModeSelect (uint32_t OPAMP_Trimming)
Select the trimming mode.
void | OPAMP_PowerRangeSelect (uint32_t OPAMP_PowerRange)
Select the OPAMP power range.
void | OPAMP_SwitchCmd (uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
Close or Open the OPAMP switches.

Detailed Description

This file contains all the functions prototypes for the operational amplifiers (opamp) firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_opamp.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_pwr.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_pwr.c File Reference

This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + RTC Domain Access + PVD configuration + WakeUp pins configuration + Ultra Low Power mode configuration + Voltage Scaling configuration + Low Power modes configuration + Flags management. More...

#include "stm32l1xx_pwr.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
#define | CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define | CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
#define | CR_OFFSET (PWR_OFFSET + 0x00)
#define | CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
#define | CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
#define | CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
#define | CSR_OFFSET (PWR_OFFSET + 0x04)
#define | DBP_BitNumber 0x08
#define | EWUP_BitNumber 0x08
#define | FWU_BitNumber 0x0A
#define | PVDE_BitNumber 0x04
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | ULP_BitNumber 0x09

Functions

void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterLowPowerRunMode (FunctionalState NewState)
Enters/Exits the Low Power Run mode.
void | PWR_EnterSleepMode (uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
Enters Sleep mode.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
void | PWR_FastWakeUpCmd (FunctionalState NewState)
Enables or disables the Fast WakeUp from Ultra Low Power mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_RTCAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_UltraLowPowerCmd (FunctionalState NewState)
Enables or disables the Ultra Low Power mode.
void | PWR_VoltageScalingConfig (uint32_t PWR_VoltageScaling)
Configures the voltage scaling range.
void | PWR_WakeUpPinCmd (uint32_t PWR_WakeUpPin, FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + RTC Domain Access + PVD configuration + WakeUp pins configuration + Ultra Low Power mode configuration + Voltage Scaling configuration + Low Power modes configuration + Flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_pwr.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_pwr.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Functions

stm32l1xx_pwr.h File Reference

This file contains all the functions prototypes for the PWR firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
#define | IS_PWR_GET_FLAG(FLAG)
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_REGLP PWR_CSR_REGLPF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_VOS PWR_CSR_VOSF
#define | PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLevel_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLevel_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLevel_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLevel_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLevel_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLevel_7 PWR_CR_PLS_LEV7
#define | PWR_Regulator_LowPower PWR_CR_LPSDSR
#define | PWR_Regulator_ON ((uint32_t)0x00000000)
#define | PWR_SLEEPEntry_WFE ((uint8_t)0x02)
#define | PWR_SLEEPEntry_WFI ((uint8_t)0x01)
#define | PWR_STOPEntry_WFE ((uint8_t)0x02)
#define | PWR_STOPEntry_WFI ((uint8_t)0x01)
#define | PWR_VoltageScaling_Range1 PWR_CR_VOS_0
#define | PWR_VoltageScaling_Range2 PWR_CR_VOS_1
#define | PWR_VoltageScaling_Range3 PWR_CR_VOS
#define | PWR_WakeUpPin_1 ((uint32_t)0x00000000)
#define | PWR_WakeUpPin_2 ((uint32_t)0x00000004)
#define | PWR_WakeUpPin_3 ((uint32_t)0x00000008)

Functions

void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterLowPowerRunMode (FunctionalState NewState)
Enters/Exits the Low Power Run mode.
void | PWR_EnterSleepMode (uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
Enters Sleep mode.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
void | PWR_FastWakeUpCmd (FunctionalState NewState)
Enables or disables the Fast WakeUp from Ultra Low Power mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_RTCAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_UltraLowPowerCmd (FunctionalState NewState)
Enables or disables the Ultra Low Power mode.
void | PWR_VoltageScalingConfig (uint32_t PWR_VoltageScaling)
Configures the voltage scaling range.
void | PWR_WakeUpPinCmd (uint32_t PWR_WakeUpPin, FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

This file contains all the functions prototypes for the PWR firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_pwr.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rcc.c File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions | Variables

stm32l1xx_rcc.c File Reference

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: + Internal/external clocks, PLL, CSS and MCO configuration + System, AHB and APB busses clocks configuration + Peripheral clocks configuration + Interrupts and flags management. More...

#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
#define | CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
#define | CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
#define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
#define | CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
#define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define | CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
#define | CR_OFFSET (RCC_OFFSET + 0x00)
#define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define | CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
#define | CSR_LSECSSON_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))
#define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define | CSR_OFFSET (RCC_OFFSET + 0x34)
#define | CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define | CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
#define | CSSON_BitNumber 0x1C
#define | FLAG_MASK ((uint8_t)0x1F)
#define | HSION_BitNumber 0x00
#define | ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
#define | LSECSSON_BitNumber 0x0B
#define | LSION_BitNumber 0x00
#define | MSION_BitNumber 0x08
#define | PLLON_BitNumber 0x18
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RTCEN_BitNumber 0x16
#define | RTCRST_BitNumber 0x17

Functions

void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock during SLEEP mode.
void | RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during SLEEP mode.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during SLEEP mode.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of the System, AHB and APB busses clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the LSE Clock Security System.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
Selects the clock source to output on MCO pin (PA8).
void | RCC_MSICmd (FunctionalState NewState)
Enables or disables the Internal Multi Speed oscillator (MSI).
void | RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
Configures the Internal Multi Speed oscillator (MSI) clock range.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC and LCD clock (RTCCLK / LCDCLK).
void | RCC_RTCResetCmd (FunctionalState NewState)
Forces or releases the RTC peripheral and associated resources reset.
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Variables

static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}
static __I uint8_t | PLLMulTable [9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}

Detailed Description

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: + Internal/external clocks, PLL, CSS and MCO configuration + System, AHB and APB busses clocks configuration + Peripheral clocks configuration + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

 ===============================================================================
                        ##### RCC specific features #####
 ===============================================================================
    [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
         all peripherals are off except internal SRAM, Flash and JTAG.
         (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
             all peripherals mapped on these busses are running at MSI speed.
         (#) The clock for all peripherals is switched off, except the SRAM and
             FLASH.
         (#) All GPIOs are in input floating state, except the JTAG pins which
             are assigned to be used for debug purpose.
    [..] Once the device started from reset, the user application has to:
         (#) Configure the clock source to be used to drive the System clock
             (if the application needs higher frequency/performance)
         (#) Configure the System clock frequency and Flash settings
         (#) Configure the AHB and APB busses prescalers
         (#) Enable the clock for the peripheral(s) to be used
         (#) Configure the clock source(s) for peripherals whose clocks are not
             derived from the System clock (ADC, RTC/LCD and IWDG)
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_rcc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rcc.h File Reference

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Data Structures | Defines | Functions

stm32l1xx_rcc.h File Reference

This file contains all the functions prototypes for the RCC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | RCC_ClocksTypeDef

Defines

#define | IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_GET_IT(IT)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_MCO_DIV(DIV)
#define | IS_RCC_MCO_SOURCE(SOURCE)
#define | IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
#define | IS_RCC_MSI_CLOCK_RANGE(RANGE)
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_PLL_DIV(DIV)
#define | IS_RCC_PLL_MUL(MUL)
#define | IS_RCC_PLL_SOURCE(SOURCE)
#define | IS_RCC_RTCCLK_SOURCE(SOURCE)
#define | IS_RCC_SYSCLK_SOURCE(SOURCE)
#define | RCC_AHBPeriph_AES RCC_AHBENR_AESEN
#define | RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
#define | RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
#define | RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
#define | RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
#define | RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN
#define | RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
#define | RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
#define | RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
#define | RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
#define | RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
#define | RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
#define | RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
#define | RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
#define | RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
#define | RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
#define | RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
#define | RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
#define | RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
#define | RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
#define | RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
#define | RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
#define | RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
#define | RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
#define | RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
#define | RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
#define | RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
#define | RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
#define | RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
#define | RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
#define | RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
#define | RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
#define | RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
#define | RCC_APB1Periph_USB RCC_APB1ENR_USBEN
#define | RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
#define | RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
#define | RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN
#define | RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
#define | RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
#define | RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
#define | RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
#define | RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x5D)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x5F)
#define | RCC_FLAG_LSECSS ((uint8_t)0x4A)
#define | RCC_FLAG_LSERDY ((uint8_t)0x49)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x41)
#define | RCC_FLAG_MSIRDY ((uint8_t)0x29)
#define | RCC_FLAG_OBLRST ((uint8_t)0x59)
#define | RCC_FLAG_PINRST ((uint8_t)0x5A)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PORRST ((uint8_t)0x5B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x5C)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x5E)
#define | RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
#define | RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HSE_Bypass ((uint8_t)0x05)
#define | RCC_HSE_OFF ((uint8_t)0x00)
#define | RCC_HSE_ON ((uint8_t)0x01)
#define | RCC_IT_CSS ((uint8_t)0x80)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_LSECSS ((uint8_t)0x40)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_MSIRDY ((uint8_t)0x20)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)
#define | RCC_LSE_Bypass ((uint8_t)0x05)
#define | RCC_LSE_OFF ((uint8_t)0x00)
#define | RCC_LSE_ON ((uint8_t)0x01)
#define | RCC_MCODiv_1 ((uint8_t)0x00)
#define | RCC_MCODiv_16 ((uint8_t)0x40)
#define | RCC_MCODiv_2 ((uint8_t)0x10)
#define | RCC_MCODiv_4 ((uint8_t)0x20)
#define | RCC_MCODiv_8 ((uint8_t)0x30)
#define | RCC_MCOSource_HSE ((uint8_t)0x04)
#define | RCC_MCOSource_HSI ((uint8_t)0x02)
#define | RCC_MCOSource_LSE ((uint8_t)0x07)
#define | RCC_MCOSource_LSI ((uint8_t)0x06)
#define | RCC_MCOSource_MSI ((uint8_t)0x03)
#define | RCC_MCOSource_NoClock ((uint8_t)0x00)
#define | RCC_MCOSource_PLLCLK ((uint8_t)0x05)
#define | RCC_MCOSource_SYSCLK ((uint8_t)0x01)
#define | RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0
#define | RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1
#define | RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2
#define | RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3
#define | RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4
#define | RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5
#define | RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6
#define | RCC_PLLDiv_2 ((uint8_t)0x40)
#define | RCC_PLLDiv_3 ((uint8_t)0x80)
#define | RCC_PLLDiv_4 ((uint8_t)0xC0)
#define | RCC_PLLMul_12 ((uint8_t)0x10)
#define | RCC_PLLMul_16 ((uint8_t)0x14)
#define | RCC_PLLMul_24 ((uint8_t)0x18)
#define | RCC_PLLMul_3 ((uint8_t)0x00)
#define | RCC_PLLMul_32 ((uint8_t)0x1C)
#define | RCC_PLLMul_4 ((uint8_t)0x04)
#define | RCC_PLLMul_48 ((uint8_t)0x20)
#define | RCC_PLLMul_6 ((uint8_t)0x08)
#define | RCC_PLLMul_8 ((uint8_t)0x0C)
#define | RCC_PLLSource_HSE ((uint8_t)0x01)
#define | RCC_PLLSource_HSI ((uint8_t)0x00)
#define | RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
#define | RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
#define | RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
#define | RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
#define | RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
#define | RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
#define | RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
#define | RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
#define | RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL

Functions

void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock during SLEEP mode.
void | RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during SLEEP mode.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during SLEEP mode.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of the System, AHB and APB busses clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the LSE Clock Security System.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
Selects the clock source to output on MCO pin (PA8).
void | RCC_MSICmd (FunctionalState NewState)
Enables or disables the Internal Multi Speed oscillator (MSI).
void | RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
Configures the Internal Multi Speed oscillator (MSI) clock range.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC and LCD clock (RTCCLK / LCDCLK).
void | RCC_RTCResetCmd (FunctionalState NewState)
Forces or releases the RTC peripheral and associated resources reset.
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Detailed Description

This file contains all the functions prototypes for the RCC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_rcc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rtc.c File Reference

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Defines | Functions

stm32l1xx_rtc.c File Reference

This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + Daylight Saving configuration + Output pin Configuration + Coarse digital Calibration configuration + Smooth digital Calibration configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + Output Type Config configuration + Shift control synchronisation + Interrupts and flags management. More...

#include "stm32l1xx_rtc.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | INITMODE_TIMEOUT ((uint32_t) 0x00002000)
#define | RECALPF_TIMEOUT ((uint32_t) 0x00001000)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_FLAGS_MASK
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | SHPF_TIMEOUT ((uint32_t) 0x00002000)
#define | SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)

Functions

ErrorStatus | RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
Enables or disables the specified RTC Alarm.
void | RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).
void | RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
Configure the RTC AlarmA/B Subseconds value and mask.
static uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
void | RTC_BypassShadowCmd (FunctionalState NewState)
Enables or Disables the Bypass Shadow feature.
static uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
void | RTC_CalibOutputCmd (FunctionalState NewState)
Enables or disables the RTC clock to be output through the relative pin.
void | RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
void | RTC_ClearFlag (uint32_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint32_t RTC_IT)
Clears the RTC's interrupt pending bits.
ErrorStatus | RTC_CoarseCalibCmd (FunctionalState NewState)
Enables or disables the Coarse calibration process.
ErrorStatus | RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
Configures the Coarse Calibration parameters.
void | RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).
void | RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
Adds or substract one hour from the current time.
ErrorStatus | RTC_DeInit (void)
Deinitializes the RTC registers to their default reset values.
ErrorStatus | RTC_EnterInitMode (void)
Enters the RTC Initialization mode.
void | RTC_ExitInitMode (void)
Exits the RTC Initialization mode.
void | RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Get the RTC Alarm value and masks.
uint32_t | RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
Gets the RTC Alarm Subseconds value.
void | RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Get the RTC current date.
FlagStatus | RTC_GetFlagStatus (uint32_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint32_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
uint32_t | RTC_GetStoreOperation (void)
Returns the RTC Day Light Saving stored operation.
uint32_t | RTC_GetSubSecond (void)
Gets the RTC current Calendar Subseconds value.
void | RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Get the RTC current Time.
void | RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
Get the RTC TimeStamp value and masks.
uint32_t | RTC_GetTimeStampSubSecond (void)
Get the RTC timestamp Subseconds value.
uint32_t | RTC_GetWakeUpCounter (void)
Returns the RTC WakeUp timer counter value.
ErrorStatus | RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
Configures the RTC output source (AFO_ALARM).
void | RTC_OutputTypeConfig (uint32_t RTC_OutputType)
Configures the RTC Output Pin mode.
uint32_t | RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
Reads data from the specified RTC Backup data Register.
ErrorStatus | RTC_RefClockCmd (FunctionalState NewState)
Enables or disables the RTC reference clock detection.
void | RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the specified RTC Alarm.
ErrorStatus | RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
ErrorStatus | RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
Configures the RTC Wakeup counter.
ErrorStatus | RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
Configures the Smooth Calibration Settings.
void | RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
Fills each RTC_InitStruct member with its default value.
ErrorStatus | RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
Configures the Synchronization Shift Control Settings.
void | RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
Enables or Disables the Tamper detection.
void | RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
Configures the Tampers Filter.
void | RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
Configures the Tampers Pins input Precharge Duration.
void | RTC_TamperPullUpCmd (FunctionalState NewState)
Enables or Disables the Precharge of Tamper pin.
void | RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
Configures the Tampers Sampling Frequency.
void | RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
Configures the select Tamper pin edge.
void | RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.
void | RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
Enables or Disables the TimeStamp on Tamper Detection Event.
void | RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).
ErrorStatus | RTC_WaitForSynchro (void)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
void | RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
Configures the RTC Wakeup clock source.
ErrorStatus | RTC_WakeUpCmd (FunctionalState NewState)
Enables or Disables the RTC WakeUp timer.
void | RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
Writes a data in a specified RTC Backup data register.
void | RTC_WriteProtectionCmd (FunctionalState NewState)
Enables or disables the RTC registers write protection.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + Daylight Saving configuration + Output pin Configuration + Coarse digital Calibration configuration + Smooth digital Calibration configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + Output Type Config configuration + Shift control synchronisation + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

 ===============================================================================
                        ##### RTC Domain Reset #####
 ===============================================================================
    [..] After power-on reset, the RTC domain (RTC clock source configuration,
         RTC registers and RTC Backup data registers) is reset. You can also
         reset this domain by software using the RCC_RTCResetCmd() function.

                    ##### RTC Operating Condition #####
 ===============================================================================
    [..] As long as the supply voltage remains in the operating range,
         the RTC never stops, regardless of the device status (Run mode,
         low power modes or under reset).

                       ##### RTC Domain Access #####
 ===============================================================================
    [..] After reset, the RTC domain (RTC clock source configuration,
         RTC registers and RTC Backup data registers) are protected against
         possible stray write accesses.
    [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
         (+) Enable the Power Controller (PWR) APB1 interface clock using the
             RCC_APB1PeriphClockCmd() function.
         (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
         (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
         (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.

                     ##### How to use this driver #####
 ===============================================================================
    [..]
        (+) Enable the RTC domain access (see description in the section above)
        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
            RTC hour format using the RTC_Init() function.
 ***Time and Date configuration ***
 ==================================
    [..]
        (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
            and RTC_SetDate() functions.
        (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
            functions.
        (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
        (+) Use the RTC_DayLightSavingConfig() function to add or sub one
            hour to the RTC Calendar.

 ***Alarm configuration ***
 ==========================
    [..]
        (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
        (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
        (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
        (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.

 ***RTC Wakeup configuration ***
 ===============================
    [..]
        (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
            function.
        (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
            function.
        (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
        (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
            function.

 ***Outputs configuration ***
 ============================
    [..] The RTC has 2 different outputs:
        (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
            and WaKeUp signals.
            To output the selected RTC signal on RTC_AF1 pin, use the
            RTC_OutputConfig() function.
        (+) AFO_CALIB: this output is 512Hz signal or 1Hz.
            To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
            function.

 ***Smooth digital Calibration configuration ***
 ===============================================
    [..]
        (+) Configure the RTC Original Digital Calibration Value and the corresponding
            calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
            function.

 ***Coarse digital Calibration configuration ***
 ===============================================
    [..]
        (+) Configure the RTC Coarse Calibration Value and the corresponding
            sign using the RTC_CoarseCalibConfig() function.
        (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd()
            function.

 ***TimeStamp configuration ***
 ==============================
    [..]
        (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp
            using the RTC_TimeStampCmd() function.
        (+) To read the RTC TimeStamp Time and Date register, use the
            RTC_GetTimeStamp() function.
        (+) To read the RTC TimeStamp SubSecond register, use the
            RTC_GetTimeStampSubSecond() function.

 ***Tamper configuration ***
 ===========================
    [..]
        (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
            function.
        (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
            filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
            function.
        (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
            function.
        (+) Configure the Tamper precharge or discharge duration using
            RTC_TamperPinsPrechargeDuration() function.
        (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
        (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
        (+) Enable the Time stamp on Tamper detection event using
            RTC_TSOnTamperDetecCmd() function.

 ***Backup Data Registers configuration ***
 ==========================================
    [..]
        (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
            function.
        (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
            function.

                       ##### RTC and low power modes #####
 ===============================================================================
    [..] The MCU can be woken up from a low power mode by an RTC alternate
         function.
    [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
         RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
         These RTC alternate functions can wake up the system from the Stop
         and Standby lowpower modes.
         The system can also wake up from low power modes without depending
         on an external interrupt (Auto-wakeup mode), by using the RTC alarm
         or the RTC wakeup events.
    [..] The RTC provides a programmable time base for waking up from the
         Stop or Standby mode at regular intervals.
         Wakeup from STOP and Standby modes is possible only when the RTC
         clock source is LSE or LSI.

               ##### Selection of RTC_AF1 alternate functions #####
 ===============================================================================
    [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
         (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
         (+) AFO_ALARM output.
         (+) AFO_CALIB output.
         (+) AFI_TAMPER.
         (+) AFI_TIMESTAMP.

   +------------------------------------------------------------------------------------------+
   |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2  |ALARMOUTTYPE  |
   |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |ENABLED |  AFO_ALARM   |
   |  and function   |          |          |           |              |        |Configuration |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |   Alarm out     |          |          |           |              | Don't  |              |
   |   output OD     |     1    |    0     |Don't care | Don't care   | care   |      0       |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |   Alarm out     |          |          |           |              | Don't  |              |
   |   output PP     |     1    |    0     |Don't care | Don't care   | care   |      1       |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   | Calibration out |          |          |           |              | Don't  |              |
   |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |  TAMPER input   |          |          |           |              | Don't  |              |
   |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |  TIMESTAMP and  |          |          |           |              | Don't  |              |
   |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
   |   floating      |          |          |           |              |        |              |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   | TIMESTAMP input |          |          |           |              | Don't  |              |
   |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |  Wakeup Pin 2   |     0    |    0     |     0     |      0       |   1    |  Don't care  |
   |-----------------|----------|----------|-----------|--------------|--------|--------------|
   |  Standard GPIO  |     0    |    0     |     0     |      0       |   0    |  Don't care  |
   +------------------------------------------------------------------------------------------+
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_rtc.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rtc.h File Reference

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Data Structures | Defines | Functions

stm32l1xx_rtc.h File Reference

This file contains all the functions prototypes for the RTC firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_InitTypeDef
RTC Init structures definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...

Defines

#define | IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
#define | IS_RTC_BKP(BKP)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)
#define | IS_RTC_CALIB_SIGN(SIGN)
#define | IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
#define | IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
#define | IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
#define | IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
#define | IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
#define | IS_RTC_GET_FLAG(FLAG)
#define | IS_RTC_GET_IT(IT)
#define | IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
#define | RTC_Alarm_A ((uint32_t)0x00000100)
#define | RTC_Alarm_B ((uint32_t)0x00000200)
#define | RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
#define | RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
#define | RTC_AlarmMask_All ((uint32_t)0x80808080)
#define | RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
#define | RTC_AlarmMask_Hours ((uint32_t)0x00800000)
#define | RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
#define | RTC_AlarmMask_None ((uint32_t)0x00000000)
#define | RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
#define | RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000)
#define | RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000)
#define | RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000)
#define | RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000)
#define | RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000)
#define | RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000)
#define | RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000)
#define | RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000)
#define | RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000)
#define | RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000)
#define | RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000)
#define | RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
#define | RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
#define | RTC_CalibSign_Negative ((uint32_t)0x00000080)
#define | RTC_CalibSign_Positive ((uint32_t)0x00000000)
#define | RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
#define | RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
#define | RTC_DigitalCalibCmd RTC_CoarseCalibCmd
#define | RTC_DigitalCalibConfig RTC_CoarseCalibConfig
#define | RTC_FLAG_ALRAF ((uint32_t)0x00000100)
#define | RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
#define | RTC_FLAG_ALRBF ((uint32_t)0x00000200)
#define | RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
#define | RTC_FLAG_INITF ((uint32_t)0x00000040)
#define | RTC_FLAG_INITS ((uint32_t)0x00000010)
#define | RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define | RTC_FLAG_RSF ((uint32_t)0x00000020)
#define | RTC_FLAG_SHPF ((uint32_t)0x00000008)
#define | RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
#define | RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
#define | RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
#define | RTC_FLAG_TSF ((uint32_t)0x00000800)
#define | RTC_FLAG_TSOVF ((uint32_t)0x00001000)
#define | RTC_FLAG_WUTF ((uint32_t)0x00000400)
#define | RTC_FLAG_WUTWF ((uint32_t)0x00000004)
#define | RTC_Format_BCD ((uint32_t)0x000000001)
#define | RTC_Format_BIN ((uint32_t)0x000000000)
#define | RTC_H12_AM ((uint8_t)0x00)
#define | RTC_H12_PM ((uint8_t)0x40)
#define | RTC_HourFormat_12 ((uint32_t)0x00000040)
#define | RTC_HourFormat_24 ((uint32_t)0x00000000)
#define | RTC_IT_ALRA ((uint32_t)0x00001000)
#define | RTC_IT_ALRB ((uint32_t)0x00002000)
#define | RTC_IT_TAMP ((uint32_t)0x00000004)
#define | RTC_IT_TAMP1 ((uint32_t)0x00020000)
#define | RTC_IT_TAMP2 ((uint32_t)0x00040000)
#define | RTC_IT_TAMP3 ((uint32_t)0x00080000)
#define | RTC_IT_TS ((uint32_t)0x00008000)
#define | RTC_IT_WUT ((uint32_t)0x00004000)
#define | RTC_Month_April ((uint8_t)0x04)
#define | RTC_Month_August ((uint8_t)0x08)
#define | RTC_Month_December ((uint8_t)0x12)
#define | RTC_Month_February ((uint8_t)0x02)
#define | RTC_Month_January ((uint8_t)0x01)
#define | RTC_Month_July ((uint8_t)0x07)
#define | RTC_Month_June ((uint8_t)0x06)
#define | RTC_Month_March ((uint8_t)0x03)
#define | RTC_Month_May ((uint8_t)0x05)
#define | RTC_Month_November ((uint8_t)0x11)
#define | RTC_Month_October ((uint8_t)0x10)
#define | RTC_Month_September ((uint8_t)0x09)
#define | RTC_Output_AlarmA ((uint32_t)0x00200000)
#define | RTC_Output_AlarmB ((uint32_t)0x00400000)
#define | RTC_Output_Disable ((uint32_t)0x00000000)
#define | RTC_Output_WakeUp ((uint32_t)0x00600000)
#define | RTC_OutputPolarity_High ((uint32_t)0x00000000)
#define | RTC_OutputPolarity_Low ((uint32_t)0x00100000)
#define | RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
#define | RTC_OutputType_PushPull ((uint32_t)0x00040000)
#define | RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
#define | RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
#define | RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000)
#define | RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000)
#define | RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000)
#define | RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000)
#define | RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000)
#define | RTC_StoreOperation_Reset ((uint32_t)0x00000000)
#define | RTC_StoreOperation_Set ((uint32_t)0x00040000)
#define | RTC_Tamper_1 RTC_TAFCR_TAMP1E
#define | RTC_Tamper_2 RTC_TAFCR_TAMP2E
#define | RTC_Tamper_3 RTC_TAFCR_TAMP3E
#define | RTC_TamperFilter_2Sample ((uint32_t)0x00000800)
#define | RTC_TamperFilter_4Sample ((uint32_t)0x00001000)
#define | RTC_TamperFilter_8Sample ((uint32_t)0x00001800)
#define | RTC_TamperFilter_Disable ((uint32_t)0x00000000)
#define | RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)
#define | RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500)
#define | RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100)
#define | RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400)
#define | RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700)
#define | RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000)
#define | RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300)
#define | RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600)
#define | RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200)
#define | RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
#define | RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
#define | RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
#define | RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
#define | RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
#define | RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
#define | RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
#define | RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
#define | RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
#define | RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
#define | RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
#define | RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
#define | RTC_Weekday_Friday ((uint8_t)0x05)
#define | RTC_Weekday_Monday ((uint8_t)0x01)
#define | RTC_Weekday_Saturday ((uint8_t)0x06)
#define | RTC_Weekday_Sunday ((uint8_t)0x07)
#define | RTC_Weekday_Thursday ((uint8_t)0x04)
#define | RTC_Weekday_Tuesday ((uint8_t)0x02)
#define | RTC_Weekday_Wednesday ((uint8_t)0x03)

Functions

ErrorStatus | RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
Enables or disables the specified RTC Alarm.
void | RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).
void | RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
Configure the RTC AlarmA/B Subseconds value and mask.
void | RTC_BypassShadowCmd (FunctionalState NewState)
Enables or Disables the Bypass Shadow feature.
void | RTC_CalibOutputCmd (FunctionalState NewState)
Enables or disables the RTC clock to be output through the relative pin.
void | RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
void | RTC_ClearFlag (uint32_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint32_t RTC_IT)
Clears the RTC's interrupt pending bits.
ErrorStatus | RTC_CoarseCalibCmd (FunctionalState NewState)
Enables or disables the Coarse calibration process.
ErrorStatus | RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
Configures the Coarse Calibration parameters.
void | RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).
void | RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
Adds or substract one hour from the current time.
ErrorStatus | RTC_DeInit (void)
Deinitializes the RTC registers to their default reset values.
ErrorStatus | RTC_EnterInitMode (void)
Enters the RTC Initialization mode.
void | RTC_ExitInitMode (void)
Exits the RTC Initialization mode.
void | RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Get the RTC Alarm value and masks.
uint32_t | RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
Gets the RTC Alarm Subseconds value.
void | RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Get the RTC current date.
FlagStatus | RTC_GetFlagStatus (uint32_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint32_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
uint32_t | RTC_GetStoreOperation (void)
Returns the RTC Day Light Saving stored operation.
uint32_t | RTC_GetSubSecond (void)
Gets the RTC current Calendar Subseconds value.
void | RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Get the RTC current Time.
void | RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
Get the RTC TimeStamp value and masks.
uint32_t | RTC_GetTimeStampSubSecond (void)
Get the RTC timestamp Subseconds value.
uint32_t | RTC_GetWakeUpCounter (void)
Returns the RTC WakeUp timer counter value.
ErrorStatus | RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
Configures the RTC output source (AFO_ALARM).
void | RTC_OutputTypeConfig (uint32_t RTC_OutputType)
Configures the RTC Output Pin mode.
uint32_t | RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
Reads data from the specified RTC Backup data Register.
ErrorStatus | RTC_RefClockCmd (FunctionalState NewState)
Enables or disables the RTC reference clock detection.
void | RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the specified RTC Alarm.
ErrorStatus | RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
ErrorStatus | RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
Configures the RTC Wakeup counter.
ErrorStatus | RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
Configures the Smooth Calibration Settings.
void | RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
Fills each RTC_InitStruct member with its default value.
ErrorStatus | RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
Configures the Synchronization Shift Control Settings.
void | RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
Enables or Disables the Tamper detection.
void | RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
Configures the Tampers Filter.
void | RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
Configures the Tampers Pins input Precharge Duration.
void | RTC_TamperPullUpCmd (FunctionalState NewState)
Enables or Disables the Precharge of Tamper pin.
void | RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
Configures the Tampers Sampling Frequency.
void | RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
Configures the select Tamper pin edge.
void | RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.
void | RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
Enables or Disables the TimeStamp on Tamper Detection Event.
void | RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).
ErrorStatus | RTC_WaitForSynchro (void)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
void | RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
Configures the RTC Wakeup clock source.
ErrorStatus | RTC_WakeUpCmd (FunctionalState NewState)
Enables or Disables the RTC WakeUp timer.
void | RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
Writes a data in a specified RTC Backup data register.
void | RTC_WriteProtectionCmd (FunctionalState NewState)
Enables or disables the RTC registers write protection.

Detailed Description

This file contains all the functions prototypes for the RTC firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_rtc.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_sdio.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_sdio.c File Reference

This file provides firmware functions to manage the following functionalities of the SDIO peripheral: + Initialization + Interrupts and flags management. More...

#include "stm32l1xx_sdio.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | ATACMD_BitNumber 0x0E
#define | CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
#define | CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
#define | CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define | CLKEN_BitNumber 0x08
#define | CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
#define | CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
#define | CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
#define | CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
#define | CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define | CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
#define | DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
#define | DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
#define | DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define | DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
#define | DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
#define | DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
#define | DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
#define | DMAEN_BitNumber 0x03
#define | ENCMDCOMPL_BitNumber 0x0C
#define | NIEN_BitNumber 0x0D
#define | PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
#define | RWMOD_BitNumber 0x0A
#define | RWSTART_BitNumber 0x08
#define | RWSTOP_BitNumber 0x09
#define | SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
#define | SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
#define | SDIOEN_BitNumber 0x0B
#define | SDIOSUSPEND_BitNumber 0x0B

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SDIO peripheral: + Initialization + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
    (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
       (PLLVCO) througth a fixed divider by 2.
       Before to start working with SDIO peripheral make sure that the PLLVCO is
       well configured to 96MHz.
       The SDIO peripheral uses two clock signals:
       (++) SDIO adapter clock (SDIOCLK = 48 MHz).
       (++) APB2 bus clock (PCLK2).
            PCLK2 and SDIO_CK clock frequencies must respect the following
            condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).
    (#) Enable peripheral clock using
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
    (#) According to the SDIO mode, enable the GPIO clocks using
        RCC_AHBPeriphClockCmd() function.
        The I/O can be one of the following configurations:
        (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
        (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
        (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].

    (#) Peripheral's alternate function:
        (++) Connect the pin to the desired peripherals' Alternate
             Function (AF) using GPIO_PinAFConfig() function.
        (++) Configure the desired pin in alternate function by:
             GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
        (++) Select the type, pull-up/pull-down and output speed via
             GPIO_PuPd, GPIO_OType and GPIO_Speed members.
        (++) Call GPIO_Init() function.

    (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
        hardware, flow control and the Clock Divider using the SDIO_Init()
        function.
    (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
        function.
    (#) Enable the clock using the SDIO_ClockCmd() function.
    (#) Enable the NVIC and the corresponding interrupt using the function
        SDIO_ITConfig() if you need to use interrupt mode.
    (#) When using the DMA mode
        (++) Configure the DMA using DMA_Init() function.
        (++) Active the needed channel Request using SDIO_DMACmd() function.
    (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
    (#) To control the CPSM (Command Path State Machine) and send commands to the
        card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and
        SDIO_GetResponse() functions. First, user has to fill the command
        structure (pointer to SDIO_CmdInitTypeDef) according to the selected
        command to be sent. The parameters that should be filled are:
        (++) Command Argument.
        (++) Command Index.
        (++) Command Response type.
        (++) Command Wait.
        (++) CPSM Status (Enable or Disable).
        To check if the command is well received, read the SDIO_CMDRESP register
        using the SDIO_GetCommandResponse(). The SDIO responses registers
        (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function.
    (#) To control the DPSM (Data Path State Machine) and send/receive
        data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
        SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.

    *** Read Operations ***
    -----------------------
      [..]
      (#) First, user has to fill the data structure (pointer to
          SDIO_DataInitTypeDef) according to the selected data type to be received.
          The parameters that should be filled are:
          (++) Data TimeOut.
          (++) Data Length.
          (++) Data Block size.
          (++) Data Transfer direction: should be from card (To SDIO).
          (++) Data Transfer mode.
          (++) DPSM Status (Enable or Disable).
      (#) Configure the SDIO resources to receive the data from the card
          according to selected transfer mode (Refer to Step 8, 9 and 10).
      (#) Send the selected Read command (refer to step 11).
      (#) Use the SDIO flags/interrupts to check the transfer status.

  *** Write Operations ***
  ------------------------
    [..]
    (#) First, user has to fill the data structure (pointer to
        SDIO_DataInitTypeDef) according to the selected data type to be received.
        The parameters that should be filled are:
        (++) Data TimeOut.
        (++) Data Length.
        (++) Data Block size.
        (++) Data Transfer direction:  should be to card (To CARD).
        (++) Data Transfer mode.
        (++) DPSM Status (Enable or Disable).
    (#) Configure the SDIO resources to send the data to the card
        according to selected transfer mode (Refer to Step 8, 9 and 10).
    (#) Send the selected Write command (refer to step 11).
    (#) Use the SDIO flags/interrupts to check the transfer status.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_sdio.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_sdio.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_sdio.h File Reference

This file contains all the functions prototypes for the SDIO firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | SDIO_CmdInitTypeDef
struct | SDIO_DataInitTypeDef
struct | SDIO_InitTypeDef

Defines

#define | IS_SDIO_BLOCK_SIZE(SIZE)
#define | IS_SDIO_BUS_WIDE(WIDE)
#define | IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define | IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_CLOCK_BYPASS(BYPASS)
#define | IS_SDIO_CLOCK_EDGE(EDGE)
#define | IS_SDIO_CLOCK_POWER_SAVE(SAVE)
#define | IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
#define | IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
#define | IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
#define | IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
#define | IS_SDIO_FLAG(FLAG)
#define | IS_SDIO_GET_IT(IT)
#define | IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
#define | IS_SDIO_READWAIT_MODE(MODE)
#define | IS_SDIO_RESP(RESP)
#define | IS_SDIO_RESPONSE(RESPONSE)
#define | IS_SDIO_TRANSFER_DIR(DIR)
#define | IS_SDIO_TRANSFER_MODE(MODE)
#define | IS_SDIO_WAIT(WAIT)
#define | SDIO_BusWide_1b ((uint32_t)0x00000000)
#define | SDIO_BusWide_4b ((uint32_t)0x00000800)
#define | SDIO_BusWide_8b ((uint32_t)0x00001000)
#define | SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define | SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define | SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define | SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define | SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define | SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define | SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define | SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define | SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define | SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define | SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define | SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define | SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define | SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define | SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define | SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define | SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define | SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define | SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define | SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define | SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define | SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define | SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define | SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define | SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define | SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define | SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define | SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define | SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define | SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define | SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define | SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define | SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_IT_RXACT ((uint32_t)0x00002000)
#define | SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define | SDIO_IT_TXACT ((uint32_t)0x00001000)
#define | SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define | SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define | SDIO_PowerState_ON ((uint32_t)0x00000003)
#define | SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define | SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define | SDIO_RESP1 ((uint32_t)0x00000000)
#define | SDIO_RESP2 ((uint32_t)0x00000004)
#define | SDIO_RESP3 ((uint32_t)0x00000008)
#define | SDIO_RESP4 ((uint32_t)0x0000000C)
#define | SDIO_Response_Long ((uint32_t)0x000000C0)
#define | SDIO_Response_No ((uint32_t)0x00000000)
#define | SDIO_Response_Short ((uint32_t)0x00000040)
#define | SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define | SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define | SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define | SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define | SDIO_Wait_IT ((uint32_t)0x00000100)
#define | SDIO_Wait_No ((uint32_t)0x00000000)
#define | SDIO_Wait_Pend ((uint32_t)0x00000200)

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

This file contains all the functions prototypes for the SDIO firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_sdio.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_spi.c File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_spi.c File Reference

This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI): + Initialization and Configuration + Data transfers functions + Hardware CRC Calculation + DMA transfers management + Interrupts and flags management. More...

#include "stm32l1xx_spi.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_CLEAR_MASK ((uint16_t)0x3040)
#define | I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values.
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI): + Initialization and Configuration + Data transfers functions + Hardware CRC Calculation + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
    [..] The I2S feature is not implemented in STM32L1xx Ultra Low Power
         Medium-density devices and it's supported only STM32L1xx Ultra Low Power
         Medium-density Plus and High-density devices.

 ===============================================================================
                       ##### How to use this driver #####
 ===============================================================================
    [..]
        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
            function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
            function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)
            for SPI3.

        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using
            RCC_AHBPeriphClockCmd() function.

        (#) Peripherals alternate function:
            (++) Connect the pin to the desired peripherals' Alternate
                 Function (AF) using GPIO_PinAFConfig() function.
            (++) Configure the desired pin in alternate function by:
                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
            (++) Select the type, pull-up/pull-down and output speed via
                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
            (++) Call GPIO_Init() function.

        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
            function.In I2S mode, program the Mode, Standard, Data Format, MCLK
            Output, Audio frequency and Polarity using I2S_Init() function.

        (#) Enable the NVIC and the corresponding interrupt using the function
            SPI_ITConfig() if you need to use interrupt mode.

        (#) When using the DMA mode
            (++) Configure the DMA using DMA_Init() function.
            (++) Active the needed channel Request using SPI_I2S_DMACmd() function.

        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
            I2S_Cmd().

        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.

        (#) Optionally, you can enable/configure the following parameters without
            re-initialization (i.e there is no need to call again SPI_Init() function):
            (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
                 is programmed as Data direction parameter using the SPI_Init()
                 function it can be possible to switch between SPI_Direction_Tx
                 or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
            (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
                 using the SPI_Init() function it can be possible to manage the
                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
            (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
            (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.

        (#) To use the CRC Hardware calculation feature refer to the Peripheral
            CRC hardware Calculation subsection.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_spi.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_spi.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_spi.h File Reference

This file contains all the functions prototypes for the SPI firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | SPI_InitTypeDef
SPI Init structure definition. More...

Defines

#define | I2S_AudioFreq_11k ((uint32_t)11025)
#define | I2S_AudioFreq_16k ((uint32_t)16000)
#define | I2S_AudioFreq_192k ((uint32_t)192000)
#define | I2S_AudioFreq_22k ((uint32_t)22050)
#define | I2S_AudioFreq_32k ((uint32_t)32000)
#define | I2S_AudioFreq_44k ((uint32_t)44100)
#define | I2S_AudioFreq_48k ((uint32_t)48000)
#define | I2S_AudioFreq_8k ((uint32_t)8000)
#define | I2S_AudioFreq_96k ((uint32_t)96000)
#define | I2S_AudioFreq_Default ((uint32_t)2)
#define | I2S_CPOL_High ((uint16_t)0x0008)
#define | I2S_CPOL_Low ((uint16_t)0x0000)
#define | I2S_DataFormat_16b ((uint16_t)0x0000)
#define | I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define | I2S_DataFormat_24b ((uint16_t)0x0003)
#define | I2S_DataFormat_32b ((uint16_t)0x0005)
#define | I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define | I2S_FLAG_UDR ((uint16_t)0x0008)
#define | I2S_IT_UDR ((uint8_t)0x53)
#define | I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define | I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define | I2S_Mode_MasterRx ((uint16_t)0x0300)
#define | I2S_Mode_MasterTx ((uint16_t)0x0200)
#define | I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define | I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define | I2S_Standard_LSB ((uint16_t)0x0020)
#define | I2S_Standard_MSB ((uint16_t)0x0010)
#define | I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define | I2S_Standard_PCMShort ((uint16_t)0x0030)
#define | I2S_Standard_Phillips ((uint16_t)0x0000)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_SPI_23_PERIPH(PERIPH)
#define | IS_SPI_ALL_PERIPH(PERIPH)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_DIRECTION(DIRECTION)
#define | IS_SPI_DIRECTION_MODE(MODE)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define | IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define | IS_SPI_I2S_CONFIG_IT(IT)
#define | IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
#define | IS_SPI_I2S_GET_FLAG(FLAG)
#define | IS_SPI_I2S_GET_IT(IT)
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSS_INTERNAL(INTERNAL)
#define | SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define | SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define | SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define | SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define | SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define | SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define | SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define | SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define | SPI_ClearFlag SPI_I2S_ClearFlag
#define | SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
#define | SPI_CPHA_1Edge ((uint16_t)0x0000)
#define | SPI_CPHA_2Edge ((uint16_t)0x0001)
#define | SPI_CPOL_High ((uint16_t)0x0002)
#define | SPI_CPOL_Low ((uint16_t)0x0000)
#define | SPI_CRC_Rx ((uint8_t)0x01)
#define | SPI_CRC_Tx ((uint8_t)0x00)
#define | SPI_DataSize_16b ((uint16_t)0x0800)
#define | SPI_DataSize_8b ((uint16_t)0x0000)
#define | SPI_DeInit SPI_I2S_DeInit
#define | SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define | SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define | SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define | SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define | SPI_Direction_Rx ((uint16_t)0xBFFF)
#define | SPI_Direction_Tx ((uint16_t)0x4000)
#define | SPI_DMACmd SPI_I2S_DMACmd
#define | SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
#define | SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
#define | SPI_FirstBit_LSB ((uint16_t)0x0080)
#define | SPI_FirstBit_MSB ((uint16_t)0x0000)
#define | SPI_FLAG_BSY SPI_I2S_FLAG_BSY
#define | SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define | SPI_FLAG_MODF ((uint16_t)0x0020)
#define | SPI_FLAG_OVR SPI_I2S_FLAG_OVR
#define | SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
#define | SPI_FLAG_TXE SPI_I2S_FLAG_TXE
#define | SPI_GetFlagStatus SPI_I2S_GetFlagStatus
#define | SPI_GetITStatus SPI_I2S_GetITStatus
#define | SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define | SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define | SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define | SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
#define | SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define | SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define | SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define | SPI_I2S_IT_ERR ((uint8_t)0x50)
#define | SPI_I2S_IT_FRE ((uint8_t)0x58)
#define | SPI_I2S_IT_OVR ((uint8_t)0x56)
#define | SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define | SPI_I2S_IT_TXE ((uint8_t)0x71)
#define | SPI_IT_CRCERR ((uint8_t)0x54)
#define | SPI_IT_ERR SPI_I2S_IT_ERR
#define | SPI_IT_MODF ((uint8_t)0x55)
#define | SPI_IT_OVR SPI_I2S_IT_OVR
#define | SPI_IT_RXNE SPI_I2S_IT_RXNE
#define | SPI_IT_TXE SPI_I2S_IT_TXE
#define | SPI_ITConfig SPI_I2S_ITConfig
#define | SPI_Mode_Master ((uint16_t)0x0104)
#define | SPI_Mode_Slave ((uint16_t)0x0000)
#define | SPI_NSS_Hard ((uint16_t)0x0000)
#define | SPI_NSS_Soft ((uint16_t)0x0200)
#define | SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define | SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define | SPI_ReceiveData SPI_I2S_ReceiveData
#define | SPI_SendData SPI_I2S_SendData

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values.
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

This file contains all the functions prototypes for the SPI firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_spi.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_syscfg.c File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • STM32L1xx_StdPeriph_Driver
  • src
Defines | Functions

stm32l1xx_syscfg.c File Reference

This file provides firmware functions to manage the following functionalities of the SYSCFG and RI peripherals: + SYSCFG Initialization and Configuration + RI Initialization and Configuration. More...

#include "stm32l1xx_syscfg.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | IC_ROUTING_MASK ((uint32_t)0x0000000F)
#define | TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF)

Functions

void | SYSCFG_DeInit (void)
Deinitializes the SYSCFG registers to their default reset values.
void | SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
uint32_t | SYSCFG_GetBootMode (void)
Returns the boot mode as configured by user.
void | SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
Changes the mapping of the specified memory.
void | SYSCFG_RIChannelSpeedConfig (uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
Configures the ADC channels speed.
void | SYSCFG_RIDeInit (void)
Deinitializes the RI registers to their default reset values.
void | SYSCFG_RIHysteresisConfig (uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState)
Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.
void | SYSCFG_RIIOSwitchConfig (uint32_t RI_IOSwitch, FunctionalState NewState)
Close or Open the routing interface Input Output switches.
void | SYSCFG_RIResistorConfig (uint32_t RI_Resistor, FunctionalState NewState)
Configures the Pull-up and Pull-down Resistors.
void | SYSCFG_RISwitchControlModeCmd (FunctionalState NewState)
Enable or disable the switch control mode.
void | SYSCFG_RITIMInputCaptureConfig (uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.
void | SYSCFG_RITIMSelect (uint32_t TIM_Select)
Configures the routing interface to select which Timer to be routed.
void | SYSCFG_USBPuCmd (FunctionalState NewState)
Control the internal pull-up on USB DP line.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SYSCFG and RI peripherals: + SYSCFG Initialization and Configuration + RI Initialization and Configuration.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..] This driver provides functions for:
         (#) Remapping the memory accessible in the code area using
          SYSCFG_MemoryRemapConfig().
         (#) Manage the EXTI lines connection to the GPIOs using
             SYSCFG_EXTILineConfig().
         (#) Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).
         (#) Input routing of COMP1 and COMP2.
         (#) Routing of internal reference voltage VREFINT to PB0 and PB1.
         (#) The RI registers can be accessed only when the comparator
             APB interface clock is enabled.
             To enable comparator clock use:
             RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
             Following functions uses RI registers:
             (++) SYSCFG_RIDeInit()
             (++) SYSCFG_RITIMSelect()
             (++) SYSCFG_RITIMInputCaptureConfig()
             (++) SYSCFG_RIResistorConfig()
             (++) SYSCFG_RIChannelSpeedConfig()
             (++) SYSCFG_RIIOSwitchConfig()
             (++) SYSCFG_RISwitchControlModeCmd()
             (++) SYSCFG_RIHysteresisConfig()
         (#) The SYSCFG registers can be accessed only when the SYSCFG
             interface APB clock is enabled.
             To enable SYSCFG APB clock use:
             RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
             Following functions uses SYSCFG registers:
             (++) SYSCFG_DeInit()
             (++) SYSCFG_MemoryRemapConfig()
             (++) SYSCFG_GetBootMode()
             (++) SYSCFG_USBPuCmd()
             (++) SYSCFG_EXTILineConfig()
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_syscfg.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_syscfg.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Functions

stm32l1xx_syscfg.h File Reference

This file contains all the functions prototypes for the SYSCFG firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | EXTI_PinSource0 ((uint8_t)0x00)
#define | EXTI_PinSource1 ((uint8_t)0x01)
#define | EXTI_PinSource10 ((uint8_t)0x0A)
#define | EXTI_PinSource11 ((uint8_t)0x0B)
#define | EXTI_PinSource12 ((uint8_t)0x0C)
#define | EXTI_PinSource13 ((uint8_t)0x0D)
#define | EXTI_PinSource14 ((uint8_t)0x0E)
#define | EXTI_PinSource15 ((uint8_t)0x0F)
#define | EXTI_PinSource2 ((uint8_t)0x02)
#define | EXTI_PinSource3 ((uint8_t)0x03)
#define | EXTI_PinSource4 ((uint8_t)0x04)
#define | EXTI_PinSource5 ((uint8_t)0x05)
#define | EXTI_PinSource6 ((uint8_t)0x06)
#define | EXTI_PinSource7 ((uint8_t)0x07)
#define | EXTI_PinSource8 ((uint8_t)0x08)
#define | EXTI_PinSource9 ((uint8_t)0x09)
#define | EXTI_PortSourceGPIOA ((uint8_t)0x00)
#define | EXTI_PortSourceGPIOB ((uint8_t)0x01)
#define | EXTI_PortSourceGPIOC ((uint8_t)0x02)
#define | EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define | EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define | EXTI_PortSourceGPIOF ((uint8_t)0x06)
#define | EXTI_PortSourceGPIOG ((uint8_t)0x07)
#define | EXTI_PortSourceGPIOH ((uint8_t)0x05)
#define | IS_EXTI_PIN_SOURCE(PINSOURCE)
#define | IS_EXTI_PORT_SOURCE(PORTSOURCE)
#define | IS_RI_CHANNEL(CHANNEL)
#define | IS_RI_CHANNELSPEED(SPEED)
#define | IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
#define | IS_RI_INPUTCAPTURE_ROUTING(ROUTING)
#define | IS_RI_IOSWITCH(IOSWITCH)
#define | IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define | IS_RI_PORT(PORT)
#define | IS_RI_RESISTOR(RESISTOR)
#define | IS_RI_TIM(TIM)
#define | IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP)
#define | RI_Channel_13 ((uint32_t)0x10000000)
#define | RI_Channel_3 ((uint32_t)0x04000000)
#define | RI_Channel_8 ((uint32_t)0x08000000)
#define | RI_ChannelSpeed_Fast ((uint32_t)0x00000000)
#define | RI_ChannelSpeed_Slow ((uint32_t)0x00000001)
#define | RI_InputCapture_IC1 RI_ICR_IC1
#define | RI_InputCapture_IC2 RI_ICR_IC2
#define | RI_InputCapture_IC3 RI_ICR_IC3
#define | RI_InputCapture_IC4 RI_ICR_IC4
#define | RI_InputCaptureRouting_0 ((uint32_t)0x00000000)
#define | RI_InputCaptureRouting_1 ((uint32_t)0x00000001)
#define | RI_InputCaptureRouting_10 ((uint32_t)0x0000000A)
#define | RI_InputCaptureRouting_11 ((uint32_t)0x0000000B)
#define | RI_InputCaptureRouting_12 ((uint32_t)0x0000000C)
#define | RI_InputCaptureRouting_13 ((uint32_t)0x0000000D)
#define | RI_InputCaptureRouting_14 ((uint32_t)0x0000000E)
#define | RI_InputCaptureRouting_15 ((uint32_t)0x0000000F)
#define | RI_InputCaptureRouting_2 ((uint32_t)0x00000002)
#define | RI_InputCaptureRouting_3 ((uint32_t)0x00000003)
#define | RI_InputCaptureRouting_4 ((uint32_t)0x00000004)
#define | RI_InputCaptureRouting_5 ((uint32_t)0x00000005)
#define | RI_InputCaptureRouting_6 ((uint32_t)0x00000006)
#define | RI_InputCaptureRouting_7 ((uint32_t)0x00000007)
#define | RI_InputCaptureRouting_8 ((uint32_t)0x00000008)
#define | RI_InputCaptureRouting_9 ((uint32_t)0x00000009)
#define | RI_IOSwitch_CH0 ((uint32_t)0x80000001)
#define | RI_IOSwitch_CH0b ((uint32_t)0x00010000)
#define | RI_IOSwitch_CH1 ((uint32_t)0x80000002)
#define | RI_IOSwitch_CH10 ((uint32_t)0x80000400)
#define | RI_IOSwitch_CH10b ((uint32_t)0x01000000)
#define | RI_IOSwitch_CH11 ((uint32_t)0x80000800)
#define | RI_IOSwitch_CH11b ((uint32_t)0x02000000)
#define | RI_IOSwitch_CH12 ((uint32_t)0x80001000)
#define | RI_IOSwitch_CH12b ((uint32_t)0x04000000)
#define | RI_IOSwitch_CH13 ((uint32_t)0x80002000)
#define | RI_IOSwitch_CH14 ((uint32_t)0x80004000)
#define | RI_IOSwitch_CH15 ((uint32_t)0x80008000)
#define | RI_IOSwitch_CH18 ((uint32_t)0x80040000)
#define | RI_IOSwitch_CH19 ((uint32_t)0x80080000)
#define | RI_IOSwitch_CH1b ((uint32_t)0x00020000)
#define | RI_IOSwitch_CH2 ((uint32_t)0x80000004)
#define | RI_IOSwitch_CH20 ((uint32_t)0x80100000)
#define | RI_IOSwitch_CH21 ((uint32_t)0x80200000)
#define | RI_IOSwitch_CH22 ((uint32_t)0x80400000)
#define | RI_IOSwitch_CH23 ((uint32_t)0x80800000)
#define | RI_IOSwitch_CH24 ((uint32_t)0x81000000)
#define | RI_IOSwitch_CH25 ((uint32_t)0x82000000)
#define | RI_IOSwitch_CH27 ((uint32_t)0x88000000)
#define | RI_IOSwitch_CH28 ((uint32_t)0x90000000)
#define | RI_IOSwitch_CH29 ((uint32_t)0xA0000000)
#define | RI_IOSwitch_CH2b ((uint32_t)0x00040000)
#define | RI_IOSwitch_CH3 ((uint32_t)0x80000008)
#define | RI_IOSwitch_CH30 ((uint32_t)0xC0000000)
#define | RI_IOSwitch_CH31 ((uint32_t)0x80010000)
#define | RI_IOSwitch_CH3b ((uint32_t)0x00080000)
#define | RI_IOSwitch_CH4 ((uint32_t)0x80000010)
#define | RI_IOSwitch_CH5 ((uint32_t)0x80000020)
#define | RI_IOSwitch_CH6 ((uint32_t)0x80000040)
#define | RI_IOSwitch_CH6b ((uint32_t)0x00100000)
#define | RI_IOSwitch_CH7 ((uint32_t)0x80000080)
#define | RI_IOSwitch_CH7b ((uint32_t)0x00200000)
#define | RI_IOSwitch_CH8 ((uint32_t)0x80000100)
#define | RI_IOSwitch_CH8b ((uint32_t)0x00400000)
#define | RI_IOSwitch_CH9 ((uint32_t)0x80000200)
#define | RI_IOSwitch_CH9b ((uint32_t)0x00800000)
#define | RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
#define | RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
#define | RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
#define | RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
#define | RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
#define | RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
#define | RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
#define | RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)
#define | RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
#define | RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
#define | RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
#define | RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)
#define | RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
#define | RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
#define | RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)
#define | RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)
#define | RI_IOSwitch_VCOMP ((uint32_t)0x84000000)
#define | RI_Pin_0 ((uint16_t)0x0001)
#define | RI_Pin_1 ((uint16_t)0x0002)
#define | RI_Pin_10 ((uint16_t)0x0400)
#define | RI_Pin_11 ((uint16_t)0x0800)
#define | RI_Pin_12 ((uint16_t)0x1000)
#define | RI_Pin_13 ((uint16_t)0x2000)
#define | RI_Pin_14 ((uint16_t)0x4000)
#define | RI_Pin_15 ((uint16_t)0x8000)
#define | RI_Pin_2 ((uint16_t)0x0004)
#define | RI_Pin_3 ((uint16_t)0x0008)
#define | RI_Pin_4 ((uint16_t)0x0010)
#define | RI_Pin_5 ((uint16_t)0x0020)
#define | RI_Pin_6 ((uint16_t)0x0040)
#define | RI_Pin_7 ((uint16_t)0x0080)
#define | RI_Pin_8 ((uint16_t)0x0100)
#define | RI_Pin_9 ((uint16_t)0x0200)
#define | RI_Pin_All ((uint16_t)0xFFFF)
#define | RI_PortA ((uint8_t)0x01)
#define | RI_PortB ((uint8_t)0x02)
#define | RI_PortC ((uint8_t)0x03)
#define | RI_PortD ((uint8_t)0x04)
#define | RI_PortE ((uint8_t)0x05)
#define | RI_PortF ((uint8_t)0x06)
#define | RI_PortG ((uint8_t)0x07)
#define | RI_Resistor_10KPD COMP_CSR_10KPD
#define | RI_Resistor_10KPU COMP_CSR_10KPU
#define | RI_Resistor_400KPD COMP_CSR_400KPD
#define | RI_Resistor_400KPU COMP_CSR_400KPU
#define | SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define | SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#define | SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define | SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
#define | TIM_Select_None ((uint32_t)0x00000000)
#define | TIM_Select_TIM2 ((uint32_t)0x00010000)
#define | TIM_Select_TIM3 ((uint32_t)0x00020000)
#define | TIM_Select_TIM4 ((uint32_t)0x00030000)

Functions

void | SYSCFG_DeInit (void)
Deinitializes the SYSCFG registers to their default reset values.
void | SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
uint32_t | SYSCFG_GetBootMode (void)
Returns the boot mode as configured by user.
void | SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
Changes the mapping of the specified memory.
void | SYSCFG_RIChannelSpeedConfig (uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
Configures the ADC channels speed.
void | SYSCFG_RIDeInit (void)
Deinitializes the RI registers to their default reset values.
void | SYSCFG_RIHysteresisConfig (uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState)
Enable or disable Hysteresis of the input schmitt triger of Ports A..E When the I/Os are programmed in input mode by standard I/O port registers, the Schmitt trigger and the hysteresis are enabled by default.
void | SYSCFG_RIIOSwitchConfig (uint32_t RI_IOSwitch, FunctionalState NewState)
Close or Open the routing interface Input Output switches.
void | SYSCFG_RIResistorConfig (uint32_t RI_Resistor, FunctionalState NewState)
Configures the Pull-up and Pull-down Resistors.
void | SYSCFG_RISwitchControlModeCmd (FunctionalState NewState)
Enable or disable the switch control mode.
void | SYSCFG_RITIMInputCaptureConfig (uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
Configures the routing interface to map Input Capture 1, 2, 3 or 4 to a selected I/O pin.
void | SYSCFG_RITIMSelect (uint32_t TIM_Select)
Configures the routing interface to select which Timer to be routed.
void | SYSCFG_USBPuCmd (FunctionalState NewState)
Control the internal pull-up on USB DP line.

Detailed Description

This file contains all the functions prototypes for the SYSCFG firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_syscfg.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_tim.c File Reference

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Defines | Functions

stm32l1xx_tim.c File Reference

This file provides firmware functions to manage the following functionalities of the TIM peripheral: + TimeBase management + Output Compare management + Input Capture management + Interrupts, DMA and flags management + Clocks management + Synchronization management + Specific interface management + Specific remapping management. More...

#include "stm32l1xx_tim.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CCER_CCE_SET ((uint16_t)0x0001)
#define | CCMR_OFFSET ((uint16_t)0x0018)
#define | SMCR_ETR_MASK ((uint16_t)0x00FF)

Functions

static void | TI1_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint32_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint32_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint32_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint32_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint32_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_RemapConfig (TIM_TypeDef *TIMx, uint32_t TIM_Remap)
Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCREFClear (TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

This file provides firmware functions to manage the following functionalities of the TIM peripheral: + TimeBase management + Output Compare management + Input Capture management + Interrupts, DMA and flags management + Clocks management + Synchronization management + Specific interface management + Specific remapping management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012

 ===============================================================================
                    ##### How to use this driver #####
 ===============================================================================
    [..] This driver provides functions to configure and program the TIM
         of all STM32L1xx devices These functions are split in 8 groups:
         (#) TIM TimeBase management: this group includes all needed functions
             to configure the TM Timebase unit:
             (++) Set/Get Prescaler.
             (++) Set/Get Autoreload.
             (++) Counter modes configuration.
             (++) Set Clock division.
             (++) Select the One Pulse mode.
             (++) Update Request Configuration.
             (++) Update Disable Configuration.
             (++) Auto-Preload Configuration.
             (++) Enable/Disable the counter.

         (#) TIM Output Compare management: this group includes all needed
             functions to configure the Capture/Compare unit used in Output
             compare mode:
             (++) Configure each channel, independently, in Output Compare mode.
             (++) Select the output compare modes.
             (++) Select the Polarities of each channel.
             (++) Set/Get the Capture/Compare register values.
             (++) Select the Output Compare Fast mode.
             (++) Select the Output Compare Forced mode.
             (++) Output Compare-Preload Configuration.
             (++) Clear Output Compare Reference.
             (++) Select the OCREF Clear signal.
             (++) Enable/Disable the Capture/Compare Channels.

         (#) TIM Input Capture management: this group includes all needed
             functions to configure the Capture/Compare unit used in
             Input Capture mode:
             (++) Configure each channel in input capture mode.
             (++) Configure Channel1/2 in PWM Input mode.
             (++) Set the Input Capture Prescaler.
             (++) Get the Capture/Compare values.

         (#) TIM interrupts, DMA and flags management.
             (++) Enable/Disable interrupt sources.
             (++) Get flags status.
             (++) Clear flags/ Pending bits.
             (++) Enable/Disable DMA requests.
             (++) Configure DMA burst mode.
             (++) Select CaptureCompare DMA request.

         (#) TIM clocks management: this group includes all needed functions
             to configure the clock controller unit:
             (++) Select internal/External clock.
             (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.

         (#) TIM synchronization management: this group includes all needed.
             functions to configure the Synchronization unit:
             (++) Select Input Trigger.
             (++) Select Output Trigger.
             (++) Select Master Slave Mode.
             (++) ETR Configuration when used as external trigger.

         (#) TIM specific interface management, this group includes all
             needed functions to use the specific TIM interface:
             (++) Encoder Interface Configuration.
             (++) Select Hall Sensor.

         (#) TIM specific remapping management includes the Remapping
             configuration of specific timers
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_tim.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_tim.h File Reference

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32l1xx_tim.h File Reference

This file contains all the functions prototypes for the TIM firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | TIM_ICInitTypeDef
TIM Input Capture Init structure definition. More...
struct | TIM_OCInitTypeDef
TIM Output Compare Init structure definition. More...
struct | TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition. More...

Defines

#define | IS_TIM_ALL_PERIPH(PERIPH)
#define | IS_TIM_CCX(CCX)
#define | IS_TIM_CHANNEL(CHANNEL)
#define | IS_TIM_CKD_DIV(DIV)
#define | IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
#define | IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
#define | IS_TIM_EXT_POLARITY(POLARITY)
#define | IS_TIM_EXT_PRESCALER(PRESCALER)
#define | IS_TIM_FORCED_ACTION(ACTION)
#define | IS_TIM_GET_FLAG(FLAG)
#define | IS_TIM_GET_IT(IT)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
#define | IS_TIM_LIST1_PERIPH(PERIPH)
#define | IS_TIM_LIST2_PERIPH(PERIPH)
#define | IS_TIM_LIST3_PERIPH(PERIPH)
#define | IS_TIM_LIST4_PERIPH(PERIPH)
#define | IS_TIM_LIST5_PERIPH(PERIPH)
#define | IS_TIM_LIST6_PERIPH(PERIPH)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCCLEAR_STATE(STATE)
#define | IS_TIM_OCFAST_STATE(STATE)
#define | IS_TIM_OCM(MODE)
#define | IS_TIM_OCPRELOAD_STATE(STATE)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_OUTPUT_STATE(STATE)
#define | IS_TIM_PRESCALER_RELOAD(RELOAD)
#define | IS_TIM_PWMI_CHANNEL(CHANNEL)
#define | IS_TIM_REMAP(TIM_REMAP)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_UPDATE_SOURCE(SOURCE)
#define | TIM10_ETR_LSE ((uint32_t)0xFFFB0000)
#define | TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
#define | TIM10_GPIO ((uint32_t)0xFFF40000)
#define | TIM10_LSE ((uint32_t)0xFFF40002)
#define | TIM10_LSI ((uint32_t)0xFFF40001)
#define | TIM10_RI ((uint32_t)0xFFF40008)
#define | TIM10_RTC ((uint32_t)0xFFF40003)
#define | TIM11_ETR_LSE ((uint32_t)0xFFFB0000)
#define | TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
#define | TIM11_GPIO ((uint32_t)0xFFF40000)
#define | TIM11_HSE_RTC ((uint32_t)0xFFF40002)
#define | TIM11_MSI ((uint32_t)0xFFF40001)
#define | TIM11_RI ((uint32_t)0xFFF40008)
#define | TIM2_TIM10_OC ((uint32_t)0xFFFE0000)
#define | TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)
#define | TIM3_TIM11_OC ((uint32_t)0xFFFE0000)
#define | TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)
#define | TIM9_GPIO ((uint32_t)0xFFFC0000)
#define | TIM9_LSE ((uint32_t)0xFFFC0001)
#define | TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)
#define | TIM9_TS_IO ((uint32_t)0xFFFB0004)
#define | TIM_CCx_Disable ((uint16_t)0x0000)
#define | TIM_CCx_Enable ((uint16_t)0x0001)
#define | TIM_Channel_1 ((uint16_t)0x0000)
#define | TIM_Channel_2 ((uint16_t)0x0004)
#define | TIM_Channel_3 ((uint16_t)0x0008)
#define | TIM_Channel_4 ((uint16_t)0x000C)
#define | TIM_CKD_DIV1 ((uint16_t)0x0000)
#define | TIM_CKD_DIV2 ((uint16_t)0x0100)
#define | TIM_CKD_DIV4 ((uint16_t)0x0200)
#define | TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define | TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define | TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
#define | TIM_CounterMode_Down ((uint16_t)0x0010)
#define | TIM_CounterMode_Up ((uint16_t)0x0000)
#define | TIM_DMA_CC1 ((uint16_t)0x0200)
#define | TIM_DMA_CC2 ((uint16_t)0x0400)
#define | TIM_DMA_CC3 ((uint16_t)0x0800)
#define | TIM_DMA_CC4 ((uint16_t)0x1000)
#define | TIM_DMA_Trigger ((uint16_t)0x4000)
#define | TIM_DMA_Update ((uint16_t)0x0100)
#define | TIM_DMABase_ARR ((uint16_t)0x000B)
#define | TIM_DMABase_CCER ((uint16_t)0x0008)
#define | TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define | TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define | TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define | TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define | TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define | TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define | TIM_DMABase_CNT ((uint16_t)0x0009)
#define | TIM_DMABase_CR1 ((uint16_t)0x0000)
#define | TIM_DMABase_CR2 ((uint16_t)0x0001)
#define | TIM_DMABase_DCR ((uint16_t)0x0012)
#define | TIM_DMABase_DIER ((uint16_t)0x0003)
#define | TIM_DMABase_EGR ((uint16_t)0x0005)
#define | TIM_DMABase_OR ((uint16_t)0x0013)
#define | TIM_DMABase_PSC ((uint16_t)0x000A)
#define | TIM_DMABase_SMCR ((uint16_t)0x0002)
#define | TIM_DMABase_SR ((uint16_t)0x0004)
#define | TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define | TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define | TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define | TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define | TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define | TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define | TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define | TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define | TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define | TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define | TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define | TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define | TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define | TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define | TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define | TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define | TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
#define | TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
#define | TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define | TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define | TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define | TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define | TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define | TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define | TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define | TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define | TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define | TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define | TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define | TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define | TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define | TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define | TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define | TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define | TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define | TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define | TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define | TIM_EncoderMode_TI12 ((uint16_t)0x0003)
#define | TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define | TIM_EventSource_CC1 ((uint16_t)0x0002)
#define | TIM_EventSource_CC2 ((uint16_t)0x0004)
#define | TIM_EventSource_CC3 ((uint16_t)0x0008)
#define | TIM_EventSource_CC4 ((uint16_t)0x0010)
#define | TIM_EventSource_Trigger ((uint16_t)0x0040)
#define | TIM_EventSource_Update ((uint16_t)0x0001)
#define | TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define | TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
#define | TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define | TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define | TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
#define | TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define | TIM_FLAG_CC1 ((uint16_t)0x0002)
#define | TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define | TIM_FLAG_CC2 ((uint16_t)0x0004)
#define | TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define | TIM_FLAG_CC3 ((uint16_t)0x0008)
#define | TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define | TIM_FLAG_CC4 ((uint16_t)0x0010)
#define | TIM_FLAG_CC4OF ((uint16_t)0x1000)
#define | TIM_FLAG_Trigger ((uint16_t)0x0040)
#define | TIM_FLAG_Update ((uint16_t)0x0001)
#define | TIM_ForcedAction_Active ((uint16_t)0x0050)
#define | TIM_ForcedAction_InActive ((uint16_t)0x0040)
#define | TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define | TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define | TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV1 ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV2 ((uint16_t)0x0004)
#define | TIM_ICPSC_DIV4 ((uint16_t)0x0008)
#define | TIM_ICPSC_DIV8 ((uint16_t)0x000C)
#define | TIM_ICSelection_DirectTI ((uint16_t)0x0001)
#define | TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
#define | TIM_ICSelection_TRC ((uint16_t)0x0003)
#define | TIM_IT_CC1 ((uint16_t)0x0002)
#define | TIM_IT_CC2 ((uint16_t)0x0004)
#define | TIM_IT_CC3 ((uint16_t)0x0008)
#define | TIM_IT_CC4 ((uint16_t)0x0010)
#define | TIM_IT_Trigger ((uint16_t)0x0040)
#define | TIM_IT_Update ((uint16_t)0x0001)
#define | TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
#define | TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define | TIM_OCClear_Disable ((uint16_t)0x0000)
#define | TIM_OCClear_Enable ((uint16_t)0x0080)
#define | TIM_OCFast_Disable ((uint16_t)0x0000)
#define | TIM_OCFast_Enable ((uint16_t)0x0004)
#define | TIM_OCMode_Active ((uint16_t)0x0010)
#define | TIM_OCMode_Inactive ((uint16_t)0x0020)
#define | TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define | TIM_OCMode_PWM2 ((uint16_t)0x0070)
#define | TIM_OCMode_Timing ((uint16_t)0x0000)
#define | TIM_OCMode_Toggle ((uint16_t)0x0030)
#define | TIM_OCPolarity_High ((uint16_t)0x0000)
#define | TIM_OCPolarity_Low ((uint16_t)0x0002)
#define | TIM_OCPreload_Disable ((uint16_t)0x0000)
#define | TIM_OCPreload_Enable ((uint16_t)0x0008)
#define | TIM_OCREFERENCECECLEAR_SOURCE(SOURCE)
#define | TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
#define | TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
#define | TIM_OPMode_Repetitive ((uint16_t)0x0000)
#define | TIM_OPMode_Single ((uint16_t)0x0008)
#define | TIM_OutputState_Disable ((uint16_t)0x0000)
#define | TIM_OutputState_Enable ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define | TIM_SlaveMode_External1 ((uint16_t)0x0007)
#define | TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define | TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define | TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define | TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define | TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
#define | TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define | TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define | TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define | TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define | TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define | TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define | TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
#define | TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define | TIM_TRGOSource_Update ((uint16_t)0x0020)
#define | TIM_TS_ETRF ((uint16_t)0x0070)
#define | TIM_TS_ITR0 ((uint16_t)0x0000)
#define | TIM_TS_ITR1 ((uint16_t)0x0010)
#define | TIM_TS_ITR2 ((uint16_t)0x0020)
#define | TIM_TS_ITR3 ((uint16_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define | TIM_UpdateSource_Global ((uint16_t)0x0000)
#define | TIM_UpdateSource_Regular ((uint16_t)0x0001)

Functions

void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint32_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint32_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint32_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint32_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint32_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_RemapConfig (TIM_TypeDef *TIMx, uint32_t TIM_Remap)
Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input Capabilities.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCREFClear (TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

This file contains all the functions prototypes for the TIM firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_tim.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_usart.c File Reference

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Defines | Functions

stm32l1xx_usart.c File Reference

This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART): + Initialization and Configuration + Data transfers + Multi-Processor Communication + LIN mode + Half-duplex mode + Smartcard mode + IrDA mode + DMA transfers management + Interrupts and flags management. More...

#include "stm32l1xx_usart.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_CLEAR_MASK
#define | CR2_CLOCK_CLEAR_MASK
#define | CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | IT_MASK ((uint16_t)0x001F)

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART's DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART): + Initialization and Configuration + Data transfers + Multi-Processor Communication + LIN mode + Half-duplex mode + Smartcard mode + IrDA mode + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
 ===============================================================================
                       ##### How to use this driver #####
 ===============================================================================
    [..]
        (#) Enable peripheral clock using
            RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) function for
            USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
            function for USART2 and USART3.
        (#) According to the USART mode, enable the GPIO clocks using
            RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
            or and SCLK).
        (#) Peripheral's alternate function:
            (++) Connect the pin to the desired peripherals' Alternate
                 Function (AF) using GPIO_PinAFConfig() function.
            (++) Configure the desired pin in alternate function by:
                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
            (++) Select the type, pull-up/pull-down and output speed via
                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
            (++) Call GPIO_Init() function.
        (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
               flow control and Mode(Receiver/Transmitter) using the SPI_Init()
               function.
        (#) For synchronous mode, enable the clock and program the polarity,
            phase and last bit using the USART_ClockInit() function.
        (#) Enable the NVIC and the corresponding interrupt using the function
            USART_ITConfig() if you need to use interrupt mode.
        (#) When using the DMA mode.
            (++) Configure the DMA using DMA_Init() function.
            (++) Active the needed channel Request using USART_DMACmd() function.
        (#) Enable the USART using the USART_Cmd() function.
        (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
    [..]
        Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
        for more details.
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_usart.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_usart.h File Reference

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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Data Structures | Defines | Functions

stm32l1xx_usart.h File Reference

This file contains all the functions prototypes for the USART firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Data Structures

struct | USART_ClockInitTypeDef
USART Clock Init Structure definition. More...
struct | USART_InitTypeDef
USART Init Structure definition. More...

Defines

#define | IS_USART_123_PERIPH(PERIPH)
#define | IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define | IS_USART_ALL_PERIPH(PERIPH)
#define | IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
#define | IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_USART_CLEAR_IT(IT)
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_CONFIG_IT(IT)
#define | IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
#define | IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
#define | IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
#define | IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
#define | IS_USART_FLAG(FLAG)
#define | IS_USART_GET_IT(IT)
#define | IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_USART_IRDA_MODE(MODE)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_WAKEUP(WAKEUP)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | USART_Clock_Disable ((uint16_t)0x0000)
#define | USART_Clock_Enable ((uint16_t)0x0800)
#define | USART_CPHA_1Edge ((uint16_t)0x0000)
#define | USART_CPHA_2Edge ((uint16_t)0x0200)
#define | USART_CPOL_High ((uint16_t)0x0400)
#define | USART_CPOL_Low ((uint16_t)0x0000)
#define | USART_DMAReq_Rx ((uint16_t)0x0040)
#define | USART_DMAReq_Tx ((uint16_t)0x0080)
#define | USART_FLAG_CTS ((uint16_t)0x0200)
#define | USART_FLAG_FE ((uint16_t)0x0002)
#define | USART_FLAG_IDLE ((uint16_t)0x0010)
#define | USART_FLAG_LBD ((uint16_t)0x0100)
#define | USART_FLAG_NE ((uint16_t)0x0004)
#define | USART_FLAG_ORE ((uint16_t)0x0008)
#define | USART_FLAG_PE ((uint16_t)0x0001)
#define | USART_FLAG_RXNE ((uint16_t)0x0020)
#define | USART_FLAG_TC ((uint16_t)0x0040)
#define | USART_FLAG_TXE ((uint16_t)0x0080)
#define | USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define | USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define | USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define | USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define | USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define | USART_IrDAMode_Normal ((uint16_t)0x0000)
#define | USART_IT_CTS ((uint16_t)0x096A)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_FE ((uint16_t)0x0160)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_LBD ((uint16_t)0x0846)
#define | USART_IT_NE ((uint16_t)0x0260)
#define | USART_IT_ORE USART_IT_ORE_ER
#define | USART_IT_ORE_ER ((uint16_t)0x0360)
#define | USART_IT_ORE_RX ((uint16_t)0x0325)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_LastBit_Disable ((uint16_t)0x0000)
#define | USART_LastBit_Enable ((uint16_t)0x0100)
#define | USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define | USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define | USART_Mode_Rx ((uint16_t)0x0004)
#define | USART_Mode_Tx ((uint16_t)0x0008)
#define | USART_Parity_Even ((uint16_t)0x0400)
#define | USART_Parity_No ((uint16_t)0x0000)
#define | USART_Parity_Odd ((uint16_t)0x0600)
#define | USART_StopBits_0_5 ((uint16_t)0x1000)
#define | USART_StopBits_1 ((uint16_t)0x0000)
#define | USART_StopBits_1_5 ((uint16_t)0x3000)
#define | USART_StopBits_2 ((uint16_t)0x2000)
#define | USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define | USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define | USART_WordLength_8b ((uint16_t)0x0000)
#define | USART_WordLength_9b ((uint16_t)0x1000)

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct.
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART's DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct.
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

This file contains all the functions prototypes for the USART firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_usart.h.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_wwdg.c File Reference

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Defines | Functions

stm32l1xx_wwdg.c File Reference

This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral: + Prescaler, Refresh window and Counter configuration + WWDG activation + Interrupts and flags management. More...

#include "stm32l1xx_wwdg.h"
#include "stm32l1xx_rcc.h"

Go to the source code of this file.

Defines

#define | BIT_MASK ((uint8_t)0x7F)
#define | CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
#define | CFR_OFFSET (WWDG_OFFSET + 0x04)
#define | CFR_W_MASK ((uint32_t)0xFFFFFF80)
#define | CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
#define | EWI_BitNumber 0x09
#define | WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral: + Prescaler, Refresh window and Counter configuration + WWDG activation + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
  *
  ==============================================================================
                           ##### WWDG features #####
  ==============================================================================
    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
        time period, unless the program refreshes the counter (downcounter)
        before to reach 0x3F value (i.e. a reset is generated when the counter
        value rolls over from 0x40 to 0x3F).
    [..] An MCU reset is also generated if the counter value is refreshed
         before the counter has reached the refresh window value. This
         implies that the counter must be refreshed in a limited window.

    [..] Once enabled the WWDG cannot be disabled except by a system reset.

    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
         reset occurs.

    [..] The WWDG counter input clock is derived from the APB clock divided
         by a programmable prescaler.

    [..] WWDG counter clock = PCLK1 / Prescaler.
    [..] WWDG timeout = (WWDG counter clock) * (counter value).

    [..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.

                       ##### How to use this driver #####
  ==============================================================================
    [..]
        (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
            function.

        (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.

        (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.

        (#) Set the WWDG counter value and start it using WWDG_Enable() function.
            When the WWDG is enabled the counter value should be configured to
            a value greater than 0x40 to prevent generating an immediate reset.

        (#) Optionally you can enable the Early wakeup interrupt which is
            generated when the counter reach 0x40.
            Once enabled this interrupt cannot be disabled except by a system reset.

        (#) Then the application program must refresh the WWDG counter at regular
            intervals during normal operation to prevent an MCU reset, using
            WWDG_SetCounter() function. This operation must occur only when
            the counter value is lower than the refresh window value,
            programmed using WWDG_SetWindowValue().

  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_wwdg.c.


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_wwdg.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc
Defines | Functions

stm32l1xx_wwdg.h File Reference

This file contains all the functions prototypes for the WWDG firmware library. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
#define | IS_WWDG_PRESCALER(PRESCALER)
#define | IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define | WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define | WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define | WWDG_Prescaler_8 ((uint32_t)0x00000180)

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

This file contains all the functions prototypes for the WWDG firmware library.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file stm32l1xx_wwdg.h.


STM32L1xx Standard Peripherals Firmware Library: system_stm32l1xx.c File Reference

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Defines | Functions | Variables

system_stm32l1xx.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32L1xx Ultra Low Power devices, and is generated by the clock configuration tool "STM32L1xx_Clock_Configuration_V1.1.0.xls". More...

#include "stm32l1xx.h"

Go to the source code of this file.

Defines

#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, AHB/APBx prescalers and Flash settings.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
void | SystemInit (void)
Setup the microcontroller system.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | PLLMulTable [9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}
uint32_t | SystemCoreClock = 32000000

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32L1xx Ultra Low Power devices, and is generated by the clock configuration tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings), depending on the configuration made in the clock xls tool. This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32l1xx_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and MSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define in "stm32l1xx.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

5. This file configures the system clock as follows: ============================================================================= System Clock Configuration ============================================================================= System Clock source | PLL(HSE) ----------------------------------------------------------------------------- SYSCLK | 32000000 Hz ----------------------------------------------------------------------------- HCLK | 32000000 Hz ----------------------------------------------------------------------------- AHB Prescaler | 1 ----------------------------------------------------------------------------- APB1 Prescaler | 1 ----------------------------------------------------------------------------- APB2 Prescaler | 1 ----------------------------------------------------------------------------- HSE Frequency | 8000000 Hz ----------------------------------------------------------------------------- PLL DIV | 3 ----------------------------------------------------------------------------- PLL MUL | 12 ----------------------------------------------------------------------------- VDD | 3.3 V ----------------------------------------------------------------------------- Vcore | 1.8 V (Range 1) ----------------------------------------------------------------------------- Flash Latency | 1 WS ----------------------------------------------------------------------------- SDIO clock (SDIOCLK) | 48000000 Hz ----------------------------------------------------------------------------- Require 48MHz for USB clock | Disabled ----------------------------------------------------------------------------- =============================================================================

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.

© COPYRIGHT 2012 STMicroelectronics

Definition in file system_stm32l1xx.c.


STM32L1xx Standard Peripherals Firmware Library: system_stm32l1xx.h File Reference

  • File List
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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
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  • Device
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Functions | Variables

system_stm32l1xx.h File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. More...

Go to the source code of this file.

Functions

void | SystemCoreClockUpdate (void)
Update SystemCoreClock according to Clock Register Values The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
void | SystemInit (void)
Setup the microcontroller system.

Variables

uint32_t | SystemCoreClock

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.

Author:
MCD Application Team
Version:
V1.1.0
Date:
24-January-2012
Attention:

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Definition in file system_stm32l1xx.h.


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __CM3_REV : stm32l1xx.h
  • __MPU_PRESENT : stm32l1xx.h
  • __NVIC_PRIO_BITS : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_MAIN : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_RC : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_SUB1 : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_SUB2 : stm32l1xx.h
  • __Vendor_SysTickConfig : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Data Structures

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
ADC_Common_TypeDef |
ADC_CommonInitTypeDef |
ADC_InitTypeDef | ADC Init structure definition
ADC_TypeDef | Analog to Digital Converter
AES_InitTypeDef | AES Init structure definition
AES_IVInitTypeDef | AES Initialization Vectors (IV) structure definition
AES_KeyInitTypeDef | AES Key(s) structure definition
AES_TypeDef | AES hardware accelerator
COMP_InitTypeDef | COMP Init structure definition
COMP_TypeDef | Comparator
CRC_TypeDef | CRC calculation unit
DAC_InitTypeDef | DAC Init structure definition
DAC_TypeDef | Digital to Analog Converter
DBGMCU_TypeDef | Debug MCU
DMA_Channel_TypeDef | DMA Controller
DMA_InitTypeDef | DMA Init structure definition
DMA_TypeDef |
EXTI_InitTypeDef | EXTI Init Structure definition
EXTI_TypeDef | External Interrupt/Event Controller
FLASH_TypeDef | FLASH Registers
FSMC_Bank1_TypeDef | Flexible Static Memory Controller
FSMC_Bank1E_TypeDef | Flexible Static Memory Controller Bank1E
FSMC_NORSRAMInitTypeDef | FSMC NOR/SRAM Init structure definition
FSMC_NORSRAMTimingInitTypeDef | Timing parameters For NOR/SRAM Banks
GPIO_InitTypeDef | GPIO Init structure definition
GPIO_TypeDef | General Purpose IO
I2C_InitTypeDef | I2C Init structure definition
I2C_TypeDef | Inter-integrated Circuit Interface
I2S_InitTypeDef | I2S Init structure definition
IWDG_TypeDef | Independent WATCHDOG
LCD_InitTypeDef | LCD Init structure definition
LCD_TypeDef | LCD
NVIC_InitTypeDef | NVIC Init Structure definition
OB_TypeDef | Option Bytes Registers
OPAMP_TypeDef | Operational Amplifier (OPAMP)
PWR_TypeDef | Power Control
RCC_ClocksTypeDef |
RCC_TypeDef | Reset and Clock Control
RI_TypeDef | Routing Interface
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_InitTypeDef | RTC Init structures definition
RTC_TimeTypeDef | RTC Time structure definition
RTC_TypeDef | Real-Time Clock
SDIO_CmdInitTypeDef |
SDIO_DataInitTypeDef |
SDIO_InitTypeDef |
SDIO_TypeDef | SD host Interface
SPI_InitTypeDef | SPI Init structure definition
SPI_TypeDef | Serial Peripheral Interface
SYSCFG_TypeDef | SysTem Configuration
TIM_ICInitTypeDef | TIM Input Capture Init structure definition
TIM_OCInitTypeDef | TIM Output Compare Init structure definition
TIM_TimeBaseInitTypeDef | TIM Time Base Init structure definition
TIM_TypeDef | TIM
USART_ClockInitTypeDef | USART Clock Init Structure definition
USART_InitTypeDef | USART Init Structure definition
USART_TypeDef | Universal Synchronous Asynchronous Receiver Transmitter
WWDG_TypeDef | Window WATCHDOG


STM32L1xx Standard Peripherals Firmware Library: Data Structure Index

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structure Index

A | C | D | E | F | G | I | L | N | O | P | R | S | T | U | W
A
AES_InitTypeDef COMP_InitTypeDef DAC_TypeDef
E
FSMC_Bank1_TypeDef GPIO_InitTypeDef I2S_InitTypeDef
N
P
RI_TypeDef RTC_TypeDef SDIO_TypeDef TIM_ICInitTypeDef USART_ClockInitTypeDef
ADC_Common_TypeDef AES_IVInitTypeDef COMP_TypeDef DBGMCU_TypeDef EXTI_InitTypeDef FSMC_Bank1E_TypeDef GPIO_TypeDef IWDG_TypeDef NVIC_InitTypeDef PWR_TypeDef RTC_AlarmTypeDef
S
SPI_InitTypeDef TIM_OCInitTypeDef USART_InitTypeDef
ADC_CommonInitTypeDef AES_KeyInitTypeDef CRC_TypeDef DMA_Channel_TypeDef EXTI_TypeDef FSMC_NORSRAMInitTypeDef
I
L
O
R
RTC_DateTypeDef SDIO_CmdInitTypeDef SPI_TypeDef TIM_TimeBaseInitTypeDef USART_TypeDef
ADC_InitTypeDef AES_TypeDef
D
DMA_InitTypeDef
F
FSMC_NORSRAMTimingInitTypeDef I2C_InitTypeDef LCD_InitTypeDef OB_TypeDef RCC_ClocksTypeDef RTC_InitTypeDef SDIO_DataInitTypeDef SYSCFG_TypeDef TIM_TypeDef
W
ADC_TypeDef
C
DAC_InitTypeDef DMA_TypeDef FLASH_TypeDef
G
I2C_TypeDef LCD_TypeDef OPAMP_TypeDef RCC_TypeDef RTC_TimeTypeDef SDIO_InitTypeDef
T
U
WWDG_TypeDef


CMSIS: Cortex Microcontroller Software Interface Standard

Cortex Microcontroller Software Interface Standard

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

Version: 2.10 - July 2011

Information in this file, the accompany manuals, and software is
Copyright © ARM Ltd.
All rights reserved.

Revision History

  • Version 1.00: initial release.
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
  • Version 1.02: added Cortex-M0.
  • Version 1.10: second review.
  • Version 1.20: third review.
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
  • Version 1.30: updated Device Support Packages.
  • Version 2.00: added Cortex-M4 support.
  • Version 2.01: internal review.
  • Version 2.02: updated Device Specific Defines
  • Version 2.10: reworked core include files

Contents

  1. About
  2. Coding Rules and Conventions
  3. CMSIS Files
  4. Core Peripheral Access Layer
  5. CMSIS Example
  6. CMSIS MISRA-C:2004 Compliance Exceptions

About

The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges that are faced when software components are deployed to physical microcontroller devices based on a Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components.

ARM provides as part of the CMSIS the following software layers that are available for various compiler implementations:

  • Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to access core registers and peripherals. It defines also a device independent interface for RTOS Kernels that includes debug channel definitions.

These software layers are expanded by Silicon partners with:

  • Device Peripheral Access Layer: provides definitions for all device peripherals
  • Access Functions for Peripherals (optional): provides additional helper functions for peripherals

CMSIS defines for a Cortex-M Microcontroller System:

  • A common way to access peripheral registers and a common way to define exception vectors.
  • The register names of the Core Peripherals and the names of the Core Exception Vectors.
  • An device independent interface for RTOS Kernels including a debug channel.

By using CMSIS compliant software components, the user can easier re-use template code. CMSIS is intended to enable the combination of software components from multiple middleware vendors.

Coding Rules and Conventions

The following section describes the coding rules and conventions used in the CMSIS implementation. It contains also information about data types and version number information.

Essentials

  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, there are disable and enable sequences for PC-LINT inserted.
  • ANSI standard data types defined in the ANSI C header file <stdint.h> are used.
  • #define constants that include expressions must be enclosed by parenthesis.
  • Variables and parameters have a complete data type.
  • All functions in the Core Peripheral Access Layer are re-entrant.
  • The Core Peripheral Access Layer has no blocking code (which means that wait/query loops are done at other software layers).
  • For each exception/interrupt there is definition for:
    • an exception/interrupt handler with the postfix _Handler (for exceptions) or _IRQHandler (for interrupts).
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
    • a #define of the interrupt number with the postfix _IRQn.

Recommendations

The CMSIS recommends the following conventions for identifiers.

  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
  • CamelCase names to identify peripherals access functions and interrupts.
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
  • Doxygen comments for all functions are included as described under Function Comments below.
Comments
  • Comments use the ANSI C90 style (/* comment */) or C++ style (// comment). It is assumed that the programming tools support today consistently the C++ comment style.
  • Function Comments provide for each function the following information:
    • one-line brief function overview.
    • detailed parameter explanation.
    • detailed information about return values.
    • detailed description of the actual function.

    Doxygen Example:

    /**
 * @brief  Enable Interrupt in NVIC Interrupt Controller
 * @param  IRQn  interrupt number that specifies the interrupt
 * @return none.
 * Enable the specified interrupt in the NVIC Interrupt Controller.
 * Other settings of the interrupt such as priority are not affected.
 */

Data Types and IO Type Qualifiers

The Cortex-M HAL uses the standard types from the standard ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers.

IO Type Qualifier | #define | Description
__I | volatile const | Read access only
__O | volatile | Write access only
__IO | volatile | Read and write access

CMSIS Version Number

File core_cm4.h contains the version number of the CMSIS with the following define:

#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
#define __CM4_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

File core_cm3.h contains the version number of the CMSIS with the following define:

#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
#define __CM3_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)

File core_cm0.h contains the version number of the CMSIS with the following define:

#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
#define __CM0_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)

CMSIS Cortex Core

File core_cm4.h contains the type of the CMSIS Cortex-M with the following define:

#define __CORTEX_M                (0x04)

File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:

#define __CORTEX_M                (0x03)

File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:

#define __CORTEX_M                (0x00)

CMSIS Files

This section describes the Files provided in context with the CMSIS to access the Cortex-M hardware and peripherals.

File | Provider | Description
device.h | Device specific (provided by silicon partner) | Defines the peripherals for the actual device. The file may use several other include files to define the peripherals of the actual device.
core_cm0.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm4.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the core peripherals for the Cortex-M4 CPU and core peripherals.
core_cm4_simd.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the Cortex-M4 Core SIMD functions.
core_cmFunc.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the Cortex-M Core Register access functions.
core_cmInstr.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the Cortex-M Core instructions.
startup_device | ARM (adapted by compiler partner / silicon partner) | Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_device | ARM (adapted by silicon partner) | Provides a device specific configuration file for the device. It configures the device initializes typically the oscillator (PLL) that is part of the microcontroller device

device.h

The file device.h is provided by the silicon vendor and is the central include file that the application programmer is using in the C source code. This file contains:

  • Interrupt Number Definition: provides interrupt numbers (IRQn) for all core and device specific exceptions and interrupts.

  • Configuration for core_cm0.h / core_cm3.h / core_cm4.h: reflects the actual configuration of the Cortex-M processor that is part of the actual device. As such the file core_cm0.h / core_cm3.h / core_cm4.h is included that implements access to processor registers and core peripherals.

  • Device Peripheral Access Layer: provides definitions for all device peripherals. It contains all data structures and the address mapping for the device specific peripherals.

  • Access Functions for Peripherals (optional): provides additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device specific library provided by the silicon vendor.

Interrupt Number Definition

To access the device specific interrupts the device.h file defines IRQn numbers for the complete device using a enum typedef as shown below:

typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
/******  STM32 specific Interrupt Numbers ****************************************************************/
  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
  :
  :
  } IRQn_Type;

Device Specific Defines

The following device implementation specific defines are set in the device header file and are used for the Cortex-M core configuration options. Some configuration options are reflected in the CMSIS layer using the #define settings described below.

Several features in core_cm#.h are configured by the following defines that must be defined before #include <core_cm#.h> preprocessor command.

#define | Core | Value | Description
__CM0_REV | M0 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__CM3_REV | M3 | 0x0101 | 0x0200 | Core revision number ([15:8] revision number, [7:0] patch number)
__CM4_REV | M4 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | M0, M3, M4 | 2 .. 8 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | M0, M3, M4 | 0 | 1 | Defines if a MPU is present or not
__FPU_PRESENT | M4 | 0 | 1 | Defines if a FPU is present or not
__Vendor_SysTickConfig | M0, M3, M4 | 0 | 1 | When this define is setup to 1, the SysTickConfig function in core_cm3.h is excluded. In this case the device.h file must contain a vendor specific implementation of this function.

Device Peripheral Access Layer

Each peripheral uses a prefix which consists of <device abbreviation>_ and <peripheral name>_ to identify peripheral registers that access this specific peripheral. The intention of this is to avoid name collisions caused due to short names. If more than one peripheral of the same type exists, identifiers have a postfix (digit or letter). For example:

  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
    typedef struct
{
  union {
  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
       uint32_t RESERVED0;
  };
  union {
  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
  };
  union {
  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
  };
  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
       uint8_t  RESERVED1[7];
  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
       uint8_t  RESERVED2[7];
  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
       uint8_t  RESERVED3[3];
  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
       uint8_t  RESERVED4[3];
  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
       uint8_t  RESERVED5[7];
  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
       uint8_t  RESERVED6[39];
  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
} LPC_UART_TypeDef;
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. For example UART1->THR is the transmit holding register of UART1.
    #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
Minimal Requiements

To access the peripheral registers and related function in a device the files device.h and core_cm0.h / core_cm3.h defines as a minimum:

  • The Register Layout Typedef for each peripheral that defines all register names. Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of the peripheral registers. For example:
    typedef struct
{
  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
} SysTick_Type;
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined). For example:
    #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
  • Access Definition for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, LPC_UART2). For Example:
    #define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */

These definitions allow to access the peripheral registers from user code with simple assignments like:

SysTick->CTRL = 0;
Optional Features

In addition the device.h file may define:

  • #define constants that simplify access to the peripheral registers. These constant define bit-positions or other specific patterns are that required for the programming of the peripheral registers. The identifiers used start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
  • Functions that perform more complex functions with the peripheral (i.e. status query before a sending register is accessed). Again these function start with <device abbreviation>_ and <peripheral name>_.

core_cm0.h

File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers and core peripherals with efficient functions (defined as static inline).

This file implement the Core Peripheral Access Layer for a Cortex-M0.

The define __CMSIS_GENERIC allows to use core_cm0.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cm3.h

File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers and core peripherals with efficient functions (defined as static inline).

This file implement the Core Peripheral Access Layer for a Cortex-M3.

The define __CMSIS_GENERIC allows to use core_cm3.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cm4.h, core_cm4_simd.h

File core_cm4.h describes the data structures for the Cortex-M4 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm4_simd.h defines Cortex-M4 SIMD instructions.

Together these files implement the Core Peripheral Access Layer for a Cortex-M4.

The define __CMSIS_GENERIC allows to use core_cm4.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cmFunc.h and core_cmInstr.h

File core_cmFunc.h defines the Cortex-M Core Register access functions (defined as static inline).

File core_cmInstr.h defines the Cortex-M Core instructions (defined as static inline).

These files are part of the Core Peripheral Access Layer for a Cortex-M.

startup_device

A template file for startup_device is provided by ARM for each supported compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific interrupt handlers. Each interrupt handler is defined as weak function to an dummy handler. Therefore the interrupt handler can be directly used in application software without any requirements to adapt the startup_device file.

The following exception names are fixed and define the start of the vector table for a Cortex-M0:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

The following exception names are fixed and define the start of the vector table for a Cortex-M3:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

In the following examples for device specific interrupts are shown:

; External Interrupts
                DCD     WWDG_IRQHandler           ; Window Watchdog
                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
                DCD     TAMPER_IRQHandler         ; Tamper

Device specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

Default_Handler PROC
                EXPORT WWDG_IRQHandler   [WEAK]
                EXPORT PVD_IRQHandler    [WEAK]
                EXPORT TAMPER_IRQHandler [WEAK]
                :
                :
                WWDG_IRQHandler
                PVD_IRQHandler
                TAMPER_IRQHandler
                :
                :
                B .
                ENDP

The user application may simply define an interrupt handler function by using the handler name as shown below.

void WWDG_IRQHandler(void)
{
  :
  :
}

system_device.c

A template file for system_device.c is provided by ARM but adapted by the silicon vendor to match their actual device. As a minimum requirement this file must provide a device specific system configuration function and a global variable that contains the system frequency. It configures the device and initializes typically the oscillator (PLL) that is part of the microcontroller device.

The file system_device.c must provide as a minimum requirement the SystemInit function as shown below.

Function Definition | Description
void SystemInit (void) | Setup the microcontroller system. Typically this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with variable clock speed it also updates the variable SystemCoreClock. SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void) | Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.

Also part of the file system_device.c is the variable SystemCoreClock which contains the current CPU clock speed shown below.

Variable Definition | Description
uint32_t SystemCoreClock | Contains the system core clock (which is the system clock frequency supplied to the SysTick timer and the processor core clock). This variable can be used by the user application to setup the SysTick timer or configure other parameters. It may also be used by debugger to query the frequency of the debug timer or configure the trace clock speed. SystemCoreClock is initialized with a correct predefined value. The compiler must be configured to avoid the removal of this variable in case that the application program is not using it. It is important for debug systems that the variable is physically present in memory so that it can be examined to configure the debugger.

Note

  • The above definitions are the minimum requirements for the file system_device.c. This file may export more functions or variables that provide a more flexible configuration of the microcontroller system.

Core Peripheral Access Layer

Cortex-M Core Register Access

The following functions are defined in core_cm0.h / core_cm3.h and provide access to Cortex-M core registers.

Function Definition | Core | Core Register | Description
void __enable_irq (void) | M0, M3, M4 | PRIMASK = 0 | Global Interrupt enable (using the instruction CPSIE i)
void __disable_irq (void) | M0, M3, M4 | PRIMASK = 1 | Global Interrupt disable (using the instruction CPSID i)
uint32_t __get_CONTROL (void) | M0, M3, M4 | return CONTROL | Return Control Register Value (using the instruction MRS)
void __set_CONTROL (uint32_t value) | M0, M3, M4 | CONTROL = value | Set CONTROL register value (using the instruction MSR)
uint32_t __get_IPSR (void) | M0, M3, M4 | return IPSR | Return IPSR Register Value (using the instruction MRS)
uint32_t __get_APSR (void) | M0, M3, M4 | return APSR | Return APSR Register Value (using the instruction MRS)
uint32_t __get_xPSR (void) | M0, M3, M4 | return xPSR | Return xPSR Register Value (using the instruction MRS)
uint32_t __get_PSP (void) | M0, M3, M4 | return PSP | Return Process Stack Pointer (using the instruction MRS)
void __set_PSP (uint32_t TopOfProcStack) | >M0, M3, M4 | PSP = TopOfProcStack | Set Process Stack Pointer value (using the instruction MSR)
uint32_t __get_MSP (void) | M0, M3, M4 | return MSP | Return Main Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack) | M0, M3, M4 | MSP = TopOfMainStack | Set Main Stack Pointer (using the instruction MSR)
uint32_t __get_PRIMASK (void) | M0, M3, M4 | return PRIMASK | Return Priority Mask Register (using the instruction MRS)
void __set_PRIMASK (uint32_t value) | M0, M3, M4 | PRIMASK = value | Assign value to Priority Mask Register (using the instruction MSR)
void __enable_fault_irq (void) | M3, M4 | FAULTMASK = 0 | Global Fault exception and Interrupt enable (using the instruction CPSIE f)
void __disable_fault_irq (void) | M3, M4 | FAULTMASK = 1 | Global Fault exception and Interrupt disable (using the instruction CPSID f)
uint32_t __get_BASEPRI (void) | M3, M4 | return BASEPRI | Return Base Priority (using the instruction MRS)
void __set_BASEPRI (uint32_t value) | M3, M4 | BASEPRI = value | Set Base Priority (using the instruction MSR)
uint32_t __get_FAULTMASK (void) | M3, M4 | return FAULTMASK | Return Fault Mask Register (using the instruction MRS)
void __set_FAULTMASK (uint32_t value) | M3, M4 | FAULTMASK = value | Assign value to Fault Mask Register (using the instruction MSR)
uint32_t __get_FPSCR (void) | M4 | return FPSCR | Return Floating Point Status / Control Register
void __set_FPSCR (uint32_t value) | M4 | FPSCR = value | Assign value to Floating Point Status / Control Register

Cortex-M Instruction Access

The following functions are defined in core_cm0.h / core_cm3.hand generate specific Cortex-M instructions. The functions are implemented in the file core_cm0.c / core_cm3.c.

Name | Core | Generated CPU Instruction | Description
void __NOP (void) | M0, M3, M4 | NOP | No Operation
void __WFI (void) | M0, M3, M4 | WFI | Wait for Interrupt
void __WFE (void) | M0, M3, M4 | WFE | Wait for Event
void __SEV (void) | M0, M3, M4 | SEV | Set Event
void __ISB (void) | M0, M3, M4 | ISB | Instruction Synchronization Barrier
void __DSB (void) | M0, M3, M4 | DSB | Data Synchronization Barrier
void __DMB (void) | M0, M3, M4 | DMB | Data Memory Barrier
uint32_t __REV (uint32_t value) | M0, M3, M4 | REV | Reverse byte order in integer value.
uint32_t __REV16 (uint16_t value) | M0, M3, M4 | REV16 | Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value) | M0, M3, M4 | REVSH | Reverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value) | M3, M4 | RBIT | Reverse bit order of value
uint8_t __LDREXB (uint8_t *addr) | M3, M4 | LDREXB | Load exclusive byte
uint16_t __LDREXH (uint16_t *addr) | M3, M4 | LDREXH | Load exclusive half-word
uint32_t __LDREXW (uint32_t *addr) | M3, M4 | LDREXW | Load exclusive word
uint8_t __STREXB (uint8_t value, uint8_t *addr) | M3, M4 | STREXB | Store exclusive byte
uint16_t __STREXH (uint16_t value, uint16_t *addr) | M3, M4 | STREXH | Store exclusive half-word
uint32_t __STREXW (uint32_t value, uint32_t *addr) | M3, M4 | STREXW | Store exclusive word
void __CLREX (void) | M3, M4 | CLREX | Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
void __SSAT (void) | M3, M4 | SSAT | saturate a signed value
void __USAT (void) | M3, M4 | USAT | saturate an unsigned value

NVIC Access Functions

The CMSIS provides access to the NVIC via the register interface structure and several helper functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative IRQn values are used for processor core exceptions.

For the IRQn values of core exceptions the file device.h provides the following enum names.

Core Exception enum Value | Core | IRQn | Description
NonMaskableInt_IRQn | M0, M3, M4 | -14 | Cortex-M Non Maskable Interrupt
HardFault_IRQn | M0, M3, M4 | -13 | Cortex-M Hard Fault Interrupt
MemoryManagement_IRQn | M3, M4 | -12 | Cortex-M Memory Management Interrupt
BusFault_IRQn | M3, M4 | -11 | Cortex-M Bus Fault Interrupt
UsageFault_IRQn | M3, M4 | -10 | Cortex-M Usage Fault Interrupt
SVCall_IRQn | M0, M3, M4 | -5 | Cortex-M SV Call Interrupt
DebugMonitor_IRQn | M3, M4 | -4 | Cortex-M Debug Monitor Interrupt
PendSV_IRQn | M0, M3, M4 | -2 | Cortex-M Pend SV Interrupt
SysTick_IRQn | M0, M3, M4 | -1 | Cortex-M System Tick Interrupt

The following functions simplify the setup of the NVIC. The functions are defined as static inline.

Name | Core | Parameter | Description
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup) | M3, M4 | Priority Grouping Value | Set the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void) | M3, M4 | (void) | Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Enable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Return 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Set IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Clear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn) | M3, M4 | IRQ Number | Return 1 if IRQn is active else 0
void NVIC_SetPriority ( IRQn_Type IRQn, uint32_t priority) | M0, M3, M4 | IRQ Number, Priority | Set Priority for IRQn (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn) | M0, M3, M4 | IRQ Number | Get Priority for IRQn
uint32_t NVIC_EncodePriority ( uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) | M3, M4 | IRQ Number, Priority Group, Preemptive Priority, Sub Priority | Encode priority for given group, preemptive and sub priority
void NVIC_DecodePriority ( uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) | M3, M4 | Priority, Priority Group, pointer to Preempt. Priority, pointer to Sub Priority | Decode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void) | M0, M3, M4 | (void) | Resets the System

Note

  • The processor exceptions have negative enum values. Device specific interrupts have positive enum values and start with 0. The values are defined in device.h file.

  • The values for PreemptPriority and SubPriority used in functions NVIC_EncodePriority and NVIC_DecodePriority depend on the available __NVIC_PRIO_BITS implemented in the NVIC.

SysTick Configuration Function

The following function is used to configure the SysTick timer and start the SysTick interrupt.

Name | Parameter | Description
uint32_t SysTickConfig (uint32_t ticks) | ticks is SysTick counter reload value | Setup the SysTick timer and enable the SysTick interrupt. After this call the SysTick timer creates interrupts with the specified time interval. Return: 0 when successful, 1 on failure.

Cortex-M3 / Cortex-M4 ITM Debug Access

The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.

Note

  • The ITM channel 31 is selected for the RTOS kernel since some kernels may use the Privileged level for program execution. ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level. The ITM channel 0 may be therefore enabled for the user task whereas ITM channel 31 may be accessible only in Privileged level from the RTOS kernel itself.

The prototype of the ITM_SendChar routine is shown in the table below.

Name | Parameter | Description
void uint32_t ITM_SendChar(uint32_t chr) | character to output | The function outputs a character via the ITM channel 0. The function returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previous character send is not transmitted. Return: the input character 'chr'.

Example for the usage of the ITM Channel 31 for RTOS Kernels:

  // check if debugger connected and ITM channel enabled for tracing
  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
  (ITM->TCR & ITM_TCR_ITMENA) &&
  (ITM->TER & (1UL << 31))) {
    // transmit trace data
    while (ITM->PORT31_U32 == 0);
    ITM->PORT[31].u8 = task_id;      // id of next task
    while (ITM->PORT[31].u32 == 0);
    ITM->PORT[31].u32 = task_status; // status information
  }

Cortex-M3 additional Debug Access

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

The buffer variable and the prototypes of the additional functions are shown in the table below.

Name | Parameter | Description
extern volatile int ITM_RxBuffer |  | Buffer to transmit data towards debug system. Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void) | none | The nonblocking functions returns the character stored in ITM_RxBuffer. Return: -1 indicates that no character was received.
int ITM_CheckChar (void) | none | The function checks if a character is available in ITM_RxBuffer. Return: 1 indicates that a character is available, 0 indicates that no character is available.

CMSIS Example

The following section shows a typical example for using the CMSIS layer in user applications. The example is based on a STM32F10x Device.

#include "stm32f10x.h"

volatile uint32_t msTicks;                       /* timeTicks counter */

void SysTick_Handler(void) {
  msTicks++;                                     /* increment timeTicks counter */
}

__INLINE static void Delay (uint32_t dlyTicks) {
  uint32_t curTicks = msTicks;

  while ((msTicks - curTicks) < dlyTicks);
}

__INLINE static void LED_Config(void) {
  ;                                              /* Configure the LEDs */
}

__INLINE static void LED_On (uint32_t led) {
  ;                                              /* Turn On  LED */
}

__INLINE static void LED_Off (uint32_t led) {
  ;                                              /* Turn Off LED */
}

int main (void) {
  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
    ;                                            /* Handle Error */
    while (1);
  }

  LED_Config();                                  /* configure the LEDs */

  while(1) {
    LED_On (0x100);                              /* Turn  on the LED   */
    Delay (100);                                 /* delay  100 Msec    */
    LED_Off (0x100);                             /* Turn off the LED   */
    Delay (100);                                 /* delay  100 Msec    */
  }
}

CMSIS MISRA-C:2004 Compliance Exceptions

CMSIS violates following MISRA-C2004 Rules:

  • Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'.
  • Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers.
  • Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code.


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS

CMSIS Directory Reference

Directories

directory Device


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST

ST Directory Reference

Directories

directory STM32L1xx


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx
  • Source
  • Templates

Templates Directory Reference

Files

file system_stm32l1xx.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32L1xx Ultra Low Power devices, and is generated by the clock configuration tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0

STM32L1xx_StdPeriph_Lib_V1.1.0 Directory Reference

Directories

directory Libraries


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32L1xx/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx

STM32L1xx Directory Reference

Directories

directory | Include
directory | Source


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/STM32L1xx_StdPeriph_Driver/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver

STM32L1xx_StdPeriph_Driver Directory Reference

Directories

directory | inc
directory | src


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/STM32L1xx_StdPeriph_Driver/src/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src

src Directory Reference

Files

file | misc.c [code]

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).

file | stm32l1xx_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and Configuration + Power saving + Analog Watchdog configuration + Temperature Sensor & Vrefint (Voltage Reference internal) management + Regular Channels Configuration + Regular Channels DMA Configuration + Injected channels Configuration + Interrupts and flags management.

file | stm32l1xx_aes.c [code]

This file provides firmware functions to manage the following functionalities of the AES peripheral: + Configuration + Read/Write operations + DMA transfers management + Interrupts and flags management.

file | stm32l1xx_aes_util.c [code]

This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR modes.

file | stm32l1xx_comp.c [code]

This file provides firmware functions to manage the following functionalities of the comparators (COMP1 and COMP2) peripheral: + Comparators configuration + Window mode control + Internal Reference Voltage (VREFINT) output.

file | stm32l1xx_crc.c [code]

This file provides all the CRC firmware functions.

file | stm32l1xx_dac.c [code]

This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral: + DAC channels configuration: trigger, output buffer, data format + DMA management + Interrupts and flags management.

file | stm32l1xx_dbgmcu.c [code]

This file provides all the DBGMCU firmware functions.

file | stm32l1xx_dma.c [code]

This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA): + Initialization and Configuration + Data Counter + Interrupts and flags management.

file | stm32l1xx_exti.c [code]

This file provides firmware functions to manage the following functionalities of the EXTI peripheral: + Initialization and Configuration + Interrupts and flags management.

file | stm32l1xx_flash.c [code]

This file provides all the Flash firmware functions. These functions can be executed from Internal FLASH or Internal SRAM memories. The functions that should be called from SRAM are defined inside the "stm32l1xx_flash_ramfunc.c" file. This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + FLASH Interface configuration + FLASH Memory Programming + DATA EEPROM Programming + Option Bytes Programming + Interrupts and flags management.

file | stm32l1xx_flash_ramfunc.c [code]

This file provides all the Flash firmware functions which should be executed from the internal SRAM. This file should be placed in internal SRAM. Other FLASH memory functions that can be used from the FLASH are defined in the "stm32l1xx_flash.c" file.

file | stm32l1xx_fsmc.c [code]

This file provides firmware functions to manage the following functionalities of the FSMC peripheral: + Initialization + Interrupts and flags management.

file | stm32l1xx_gpio.c [code]

This file provides firmware functions to manage the following functionalities of the GPIO peripheral: + Initialization and Configuration + GPIO Read and Write + GPIO Alternate functions configuration.

file | stm32l1xx_i2c.c [code]

This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C) + Initialization and Configuration + Data transfers + PEC management + DMA transfers management + Interrupts, events and flags management.

file | stm32l1xx_iwdg.c [code]

This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral: + Prescaler and Counter configuration + IWDG activation + Flag management.

file | stm32l1xx_lcd.c [code]

This file provides firmware functions to manage the following functionalities of the LCD controller (LCD) peripheral: + Initialization and configuration + LCD RAM memory write + Interrupts and flags management.

file | stm32l1xx_opamp.c [code]

This file provides firmware functions to manage the following functionalities of the operational amplifiers (opamp) peripheral: + Initialization and configuration + Calibration management.

file | stm32l1xx_pwr.c [code]

This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + RTC Domain Access + PVD configuration + WakeUp pins configuration + Ultra Low Power mode configuration + Voltage Scaling configuration + Low Power modes configuration + Flags management.

file | stm32l1xx_rcc.c [code]

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: + Internal/external clocks, PLL, CSS and MCO configuration + System, AHB and APB busses clocks configuration + Peripheral clocks configuration + Interrupts and flags management.

file | stm32l1xx_rtc.c [code]

This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + Daylight Saving configuration + Output pin Configuration + Coarse digital Calibration configuration + Smooth digital Calibration configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + Output Type Config configuration + Shift control synchronisation + Interrupts and flags management.

file | stm32l1xx_sdio.c [code]

This file provides firmware functions to manage the following functionalities of the SDIO peripheral: + Initialization + Interrupts and flags management.

file | stm32l1xx_spi.c [code]

This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI): + Initialization and Configuration + Data transfers functions + Hardware CRC Calculation + DMA transfers management + Interrupts and flags management.

file | stm32l1xx_syscfg.c [code]

This file provides firmware functions to manage the following functionalities of the SYSCFG and RI peripherals: + SYSCFG Initialization and Configuration + RI Initialization and Configuration.

file | stm32l1xx_tim.c [code]

This file provides firmware functions to manage the following functionalities of the TIM peripheral: + TimeBase management + Output Compare management + Input Capture management + Interrupts, DMA and flags management + Clocks management + Synchronization management + Specific interface management + Specific remapping management.

file | stm32l1xx_usart.c [code]

This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART): + Initialization and Configuration + Data transfers + Multi-Processor Communication + LIN mode + Half-duplex mode + Smartcard mode + IrDA mode + DMA transfers management + Interrupts and flags management.

file | stm32l1xx_wwdg.c [code]

This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral: + Prescaler, Refresh window and Counter configuration + WWDG activation + Interrupts and flags management.


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device

Device Directory Reference

Directories

directory ST


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

inc Directory Reference

Files

file | misc.h [code]

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).

file | stm32l1xx_adc.h [code]

This file contains all the functions prototypes for the ADC firmware library.

file | stm32l1xx_aes.h [code]

This file contains all the functions prototypes for the AES firmware library.

file | stm32l1xx_comp.h [code]

This file contains all the functions prototypes for the COMP firmware library.

file | stm32l1xx_crc.h [code]

This file contains all the functions prototypes for the CRC firmware library.

file | stm32l1xx_dac.h [code]

This file contains all the functions prototypes for the DAC firmware library.

file | stm32l1xx_dbgmcu.h [code]

This file contains all the functions prototypes for the DBGMCU firmware library.

file | stm32l1xx_dma.h [code]

This file contains all the functions prototypes for the DMA firmware library.

file | stm32l1xx_exti.h [code]

This file contains all the functions prototypes for the EXTI firmware library.

file | stm32l1xx_flash.h [code]

This file contains all the functions prototypes for the FLASH firmware library.

file | stm32l1xx_fsmc.h [code]

This file contains all the functions prototypes for the FSMC firmware library.

file | stm32l1xx_gpio.h [code]

This file contains all the functions prototypes for the GPIO firmware library.

file | stm32l1xx_i2c.h [code]

This file contains all the functions prototypes for the I2C firmware library.

file | stm32l1xx_iwdg.h [code]

This file contains all the functions prototypes for the IWDG firmware library.

file | stm32l1xx_lcd.h [code]

This file contains all the functions prototypes for the LCD firmware library.

file | stm32l1xx_opamp.h [code]

This file contains all the functions prototypes for the operational amplifiers (opamp) firmware library.

file | stm32l1xx_pwr.h [code]

This file contains all the functions prototypes for the PWR firmware library.

file | stm32l1xx_rcc.h [code]

This file contains all the functions prototypes for the RCC firmware library.

file | stm32l1xx_rtc.h [code]

This file contains all the functions prototypes for the RTC firmware library.

file | stm32l1xx_sdio.h [code]

This file contains all the functions prototypes for the SDIO firmware library.

file | stm32l1xx_spi.h [code]

This file contains all the functions prototypes for the SPI firmware library.

file | stm32l1xx_syscfg.h [code]

This file contains all the functions prototypes for the SYSCFG firmware library.

file | stm32l1xx_tim.h [code]

This file contains all the functions prototypes for the TIM firmware library.

file | stm32l1xx_usart.h [code]

This file contains all the functions prototypes for the USART firmware library.

file | stm32l1xx_wwdg.h [code]

This file contains all the functions prototypes for the WWDG firmware library.


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx
  • Source

Source Directory Reference

Directories

directory Templates


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx
  • Include

Include Directory Reference

Files

file | stm32l1xx.h [code]

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32L1xx High-, Medium-density and Medium-density Plus devices.

file | system_stm32l1xx.h [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.


STM32L1xx Standard Peripherals Firmware Library: C:/Documents and Settings/youssef ghannouchi/Desktop/Lib_Gen/STM32L1xx_StdPeriph_Lib_V1.1.0/Libraries/ Directory Reference

  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries

Libraries Directory Reference

Directories

directory | CMSIS
directory | STM32L1xx_StdPeriph_Driver


STM32L1xx Standard Peripherals Firmware Library: Directories

Directories

This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • STM32L1xx_StdPeriph_Lib_V1.1.0
    • Libraries
      • CMSIS
        • Device
          • ST
            • STM32L1xx
              • Include
              • Source
                • Templates
      • STM32L1xx_StdPeriph_Driver
        • inc
        • src


STM32L1xx Standard Peripherals Firmware Library: File List

  • File List
  • Globals

File List

Here is a list of all files with brief descriptions:
misc.c [code] | This file provides all the miscellaneous firmware functions (add-on to CMSIS functions)
misc.h [code] | This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions)
stm32l1xx.h [code] | CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32L1xx High-, Medium-density and Medium-density Plus devices
stm32l1xx_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and Configuration + Power saving + Analog Watchdog configuration + Temperature Sensor & Vrefint (Voltage Reference internal) management + Regular Channels Configuration + Regular Channels DMA Configuration + Injected channels Configuration + Interrupts and flags management
stm32l1xx_adc.h [code] | This file contains all the functions prototypes for the ADC firmware library
stm32l1xx_aes.c [code] | This file provides firmware functions to manage the following functionalities of the AES peripheral: + Configuration + Read/Write operations + DMA transfers management + Interrupts and flags management
stm32l1xx_aes.h [code] | This file contains all the functions prototypes for the AES firmware library
stm32l1xx_aes_util.c [code] | This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR modes
stm32l1xx_comp.c [code] | This file provides firmware functions to manage the following functionalities of the comparators (COMP1 and COMP2) peripheral: + Comparators configuration + Window mode control + Internal Reference Voltage (VREFINT) output
stm32l1xx_comp.h [code] | This file contains all the functions prototypes for the COMP firmware library
stm32l1xx_crc.c [code] | This file provides all the CRC firmware functions
stm32l1xx_crc.h [code] | This file contains all the functions prototypes for the CRC firmware library
stm32l1xx_dac.c [code] | This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral: + DAC channels configuration: trigger, output buffer, data format + DMA management + Interrupts and flags management
stm32l1xx_dac.h [code] | This file contains all the functions prototypes for the DAC firmware library
stm32l1xx_dbgmcu.c [code] | This file provides all the DBGMCU firmware functions
stm32l1xx_dbgmcu.h [code] | This file contains all the functions prototypes for the DBGMCU firmware library
stm32l1xx_dma.c [code] | This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA): + Initialization and Configuration + Data Counter + Interrupts and flags management
stm32l1xx_dma.h [code] | This file contains all the functions prototypes for the DMA firmware library
stm32l1xx_exti.c [code] | This file provides firmware functions to manage the following functionalities of the EXTI peripheral: + Initialization and Configuration + Interrupts and flags management
stm32l1xx_exti.h [code] | This file contains all the functions prototypes for the EXTI firmware library
stm32l1xx_flash.c [code] | This file provides all the Flash firmware functions. These functions can be executed from Internal FLASH or Internal SRAM memories. The functions that should be called from SRAM are defined inside the "stm32l1xx_flash_ramfunc.c" file. This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + FLASH Interface configuration + FLASH Memory Programming + DATA EEPROM Programming + Option Bytes Programming + Interrupts and flags management
stm32l1xx_flash.h [code] | This file contains all the functions prototypes for the FLASH firmware library
stm32l1xx_flash_ramfunc.c [code] | This file provides all the Flash firmware functions which should be executed from the internal SRAM. This file should be placed in internal SRAM. Other FLASH memory functions that can be used from the FLASH are defined in the "stm32l1xx_flash.c" file
stm32l1xx_fsmc.c [code] | This file provides firmware functions to manage the following functionalities of the FSMC peripheral: + Initialization + Interrupts and flags management
stm32l1xx_fsmc.h [code] | This file contains all the functions prototypes for the FSMC firmware library
stm32l1xx_gpio.c [code] | This file provides firmware functions to manage the following functionalities of the GPIO peripheral: + Initialization and Configuration + GPIO Read and Write + GPIO Alternate functions configuration
stm32l1xx_gpio.h [code] | This file contains all the functions prototypes for the GPIO firmware library
stm32l1xx_i2c.c [code] | This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C) + Initialization and Configuration + Data transfers + PEC management + DMA transfers management + Interrupts, events and flags management
stm32l1xx_i2c.h [code] | This file contains all the functions prototypes for the I2C firmware library
stm32l1xx_iwdg.c [code] | This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral: + Prescaler and Counter configuration + IWDG activation + Flag management
stm32l1xx_iwdg.h [code] | This file contains all the functions prototypes for the IWDG firmware library
stm32l1xx_lcd.c [code] | This file provides firmware functions to manage the following functionalities of the LCD controller (LCD) peripheral: + Initialization and configuration + LCD RAM memory write + Interrupts and flags management
stm32l1xx_lcd.h [code] | This file contains all the functions prototypes for the LCD firmware library
stm32l1xx_opamp.c [code] | This file provides firmware functions to manage the following functionalities of the operational amplifiers (opamp) peripheral: + Initialization and configuration + Calibration management
stm32l1xx_opamp.h [code] | This file contains all the functions prototypes for the operational amplifiers (opamp) firmware library
stm32l1xx_pwr.c [code] | This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + RTC Domain Access + PVD configuration + WakeUp pins configuration + Ultra Low Power mode configuration + Voltage Scaling configuration + Low Power modes configuration + Flags management
stm32l1xx_pwr.h [code] | This file contains all the functions prototypes for the PWR firmware library
stm32l1xx_rcc.c [code] | This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: + Internal/external clocks, PLL, CSS and MCO configuration + System, AHB and APB busses clocks configuration + Peripheral clocks configuration + Interrupts and flags management
stm32l1xx_rcc.h [code] | This file contains all the functions prototypes for the RCC firmware library
stm32l1xx_rtc.c [code] | This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + Daylight Saving configuration + Output pin Configuration + Coarse digital Calibration configuration + Smooth digital Calibration configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + Output Type Config configuration + Shift control synchronisation + Interrupts and flags management
stm32l1xx_rtc.h [code] | This file contains all the functions prototypes for the RTC firmware library
stm32l1xx_sdio.c [code] | This file provides firmware functions to manage the following functionalities of the SDIO peripheral: + Initialization + Interrupts and flags management
stm32l1xx_sdio.h [code] | This file contains all the functions prototypes for the SDIO firmware library
stm32l1xx_spi.c [code] | This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI): + Initialization and Configuration + Data transfers functions + Hardware CRC Calculation + DMA transfers management + Interrupts and flags management
stm32l1xx_spi.h [code] | This file contains all the functions prototypes for the SPI firmware library
stm32l1xx_syscfg.c [code] | This file provides firmware functions to manage the following functionalities of the SYSCFG and RI peripherals: + SYSCFG Initialization and Configuration + RI Initialization and Configuration
stm32l1xx_syscfg.h [code] | This file contains all the functions prototypes for the SYSCFG firmware library
stm32l1xx_tim.c [code] | This file provides firmware functions to manage the following functionalities of the TIM peripheral: + TimeBase management + Output Compare management + Input Capture management + Interrupts, DMA and flags management + Clocks management + Synchronization management + Specific interface management + Specific remapping management
stm32l1xx_tim.h [code] | This file contains all the functions prototypes for the TIM firmware library
stm32l1xx_usart.c [code] | This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART): + Initialization and Configuration + Data transfers + Multi-Processor Communication + LIN mode + Half-duplex mode + Smartcard mode + IrDA mode + DMA transfers management + Interrupts and flags management
stm32l1xx_usart.h [code] | This file contains all the functions prototypes for the USART firmware library
stm32l1xx_wwdg.c [code] | This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral: + Prescaler, Refresh window and Counter configuration + WWDG activation + Interrupts and flags management
stm32l1xx_wwdg.h [code] | This file contains all the functions prototypes for the WWDG firmware library
system_stm32l1xx.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32L1xx Ultra Low Power devices, and is generated by the clock configuration tool "STM32L1xx_Clock_Configuration_V1.1.0.xls"
system_stm32l1xx.h [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Header File


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • JDR1 : ADC_TypeDef
  • JDR2 : ADC_TypeDef
  • JDR3 : ADC_TypeDef
  • JDR4 : ADC_TypeDef
  • JOFR1 : ADC_TypeDef
  • JOFR2 : ADC_TypeDef
  • JOFR3 : ADC_TypeDef
  • JOFR4 : ADC_TypeDef
  • JSQR : ADC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KEYR0 : AES_TypeDef
  • KEYR1 : AES_TypeDef
  • KEYR2 : AES_TypeDef
  • KEYR3 : AES_TypeDef
  • KR : IWDG_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • LCD_Bias : LCD_InitTypeDef
  • LCD_Divider : LCD_InitTypeDef
  • LCD_Duty : LCD_InitTypeDef
  • LCD_Prescaler : LCD_InitTypeDef
  • LCD_VoltageSource : LCD_InitTypeDef
  • LCKR : GPIO_TypeDef
  • LPOTR : OPAMP_TypeDef
  • LTR : ADC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MASK : SDIO_TypeDef
  • MEMRMP : SYSCFG_TypeDef
  • MODER : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • NVIC_IRQChannel : NVIC_InitTypeDef
  • NVIC_IRQChannelCmd : NVIC_InitTypeDef
  • NVIC_IRQChannelPreemptionPriority : NVIC_InitTypeDef
  • NVIC_IRQChannelSubPriority : NVIC_InitTypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • OAR1 : I2C_TypeDef
  • OAR2 : I2C_TypeDef
  • OBR : FLASH_TypeDef
  • ODR : GPIO_TypeDef
  • OPTKEYR : FLASH_TypeDef
  • OR : TIM_TypeDef
  • OSPEEDR : GPIO_TypeDef
  • OTR : OPAMP_TypeDef
  • OTYPER : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • BKP0R : RTC_TypeDef
  • BKP10R : RTC_TypeDef
  • BKP11R : RTC_TypeDef
  • BKP12R : RTC_TypeDef
  • BKP13R : RTC_TypeDef
  • BKP14R : RTC_TypeDef
  • BKP15R : RTC_TypeDef
  • BKP16R : RTC_TypeDef
  • BKP17R : RTC_TypeDef
  • BKP18R : RTC_TypeDef
  • BKP19R : RTC_TypeDef
  • BKP1R : RTC_TypeDef
  • BKP20R : RTC_TypeDef
  • BKP21R : RTC_TypeDef
  • BKP22R : RTC_TypeDef
  • BKP23R : RTC_TypeDef
  • BKP24R : RTC_TypeDef
  • BKP25R : RTC_TypeDef
  • BKP26R : RTC_TypeDef
  • BKP27R : RTC_TypeDef
  • BKP28R : RTC_TypeDef
  • BKP29R : RTC_TypeDef
  • BKP2R : RTC_TypeDef
  • BKP30R : RTC_TypeDef
  • BKP31R : RTC_TypeDef
  • BKP3R : RTC_TypeDef
  • BKP4R : RTC_TypeDef
  • BKP5R : RTC_TypeDef
  • BKP6R : RTC_TypeDef
  • BKP7R : RTC_TypeDef
  • BKP8R : RTC_TypeDef
  • BKP9R : RTC_TypeDef
  • BRR : USART_TypeDef , GPIO_TypeDef
  • BSRRH : GPIO_TypeDef
  • BSRRL : GPIO_TypeDef
  • BTCR : FSMC_Bank1_TypeDef
  • BWTR : FSMC_Bank1E_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • CALIBR : RTC_TypeDef
  • CALR : RTC_TypeDef
  • CCER : TIM_TypeDef
  • CCMR1 : TIM_TypeDef
  • CCMR2 : TIM_TypeDef
  • CCR : I2C_TypeDef , ADC_Common_TypeDef , DMA_Channel_TypeDef
  • CCR1 : TIM_TypeDef
  • CCR2 : TIM_TypeDef
  • CCR3 : TIM_TypeDef
  • CCR4 : TIM_TypeDef
  • CFGR : RCC_TypeDef
  • CFR : WWDG_TypeDef
  • CIR : RCC_TypeDef
  • CLKCR : SDIO_TypeDef
  • CLR : LCD_TypeDef
  • CMAR : DMA_Channel_TypeDef
  • CMD : SDIO_TypeDef
  • CNDTR : DMA_Channel_TypeDef
  • CNT : TIM_TypeDef
  • COMP_InvertingInput : COMP_InitTypeDef
  • COMP_OutputSelect : COMP_InitTypeDef
  • COMP_Speed : COMP_InitTypeDef
  • CPAR : DMA_Channel_TypeDef
  • CR : RCC_TypeDef , RTC_TypeDef , WWDG_TypeDef , PWR_TypeDef , AES_TypeDef , CRC_TypeDef , DAC_TypeDef , DBGMCU_TypeDef , LCD_TypeDef
  • CR1 : ADC_TypeDef , I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • CR2 : I2C_TypeDef , ADC_TypeDef , USART_TypeDef , SPI_TypeDef , TIM_TypeDef
  • CR3 : USART_TypeDef
  • CRCPR : SPI_TypeDef
  • CSR : RCC_TypeDef , ADC_Common_TypeDef , PWR_TypeDef , COMP_TypeDef , OPAMP_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • DAC_LFSRUnmask_TriangleAmplitude : DAC_InitTypeDef
  • DAC_OutputBuffer : DAC_InitTypeDef
  • DAC_Trigger : DAC_InitTypeDef
  • DAC_WaveGeneration : DAC_InitTypeDef
  • DCOUNT : SDIO_TypeDef
  • DCR : TIM_TypeDef
  • DCTRL : SDIO_TypeDef
  • DHR12L1 : DAC_TypeDef
  • DHR12L2 : DAC_TypeDef
  • DHR12LD : DAC_TypeDef
  • DHR12R1 : DAC_TypeDef
  • DHR12R2 : DAC_TypeDef
  • DHR12RD : DAC_TypeDef
  • DHR8R1 : DAC_TypeDef
  • DHR8R2 : DAC_TypeDef
  • DHR8RD : DAC_TypeDef
  • DIER : TIM_TypeDef
  • DINR : AES_TypeDef
  • DLEN : SDIO_TypeDef
  • DMA_BufferSize : DMA_InitTypeDef
  • DMA_DIR : DMA_InitTypeDef
  • DMA_M2M : DMA_InitTypeDef
  • DMA_MemoryBaseAddr : DMA_InitTypeDef
  • DMA_MemoryDataSize : DMA_InitTypeDef
  • DMA_MemoryInc : DMA_InitTypeDef
  • DMA_Mode : DMA_InitTypeDef
  • DMA_PeripheralBaseAddr : DMA_InitTypeDef
  • DMA_PeripheralDataSize : DMA_InitTypeDef
  • DMA_PeripheralInc : DMA_InitTypeDef
  • DMA_Priority : DMA_InitTypeDef
  • DMAR : TIM_TypeDef
  • DOR1 : DAC_TypeDef
  • DOR2 : DAC_TypeDef
  • DOUTR : AES_TypeDef
  • DR : I2C_TypeDef , SPI_TypeDef , CRC_TypeDef , ADC_TypeDef , USART_TypeDef , RTC_TypeDef
  • DTIMER : SDIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • EGR : TIM_TypeDef
  • EMR : EXTI_TypeDef
  • EXTI_Line : EXTI_InitTypeDef
  • EXTI_LineCmd : EXTI_InitTypeDef
  • EXTI_Mode : EXTI_InitTypeDef
  • EXTI_Trigger : EXTI_InitTypeDef
  • EXTICR : SYSCFG_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • FCR : LCD_TypeDef
  • FIFO : SDIO_TypeDef
  • FIFOCNT : SDIO_TypeDef
  • FSMC_AccessMode : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressHoldTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AsynchronousWait : FSMC_NORSRAMInitTypeDef
  • FSMC_Bank : FSMC_NORSRAMInitTypeDef
  • FSMC_BurstAccessMode : FSMC_NORSRAMInitTypeDef
  • FSMC_BusTurnAroundDuration : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CLKDivision : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataAddressMux : FSMC_NORSRAMInitTypeDef
  • FSMC_DataLatency : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_ExtendedMode : FSMC_NORSRAMInitTypeDef
  • FSMC_MemoryDataWidth : FSMC_NORSRAMInitTypeDef
  • FSMC_MemoryType : FSMC_NORSRAMInitTypeDef
  • FSMC_ReadWriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignal : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalActive : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalPolarity : FSMC_NORSRAMInitTypeDef
  • FSMC_WrapMode : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteBurst : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteOperation : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FTSR : EXTI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • GPIO_Mode : GPIO_InitTypeDef
  • GPIO_OType : GPIO_InitTypeDef
  • GPIO_Pin : GPIO_InitTypeDef
  • GPIO_PuPd : GPIO_InitTypeDef
  • GPIO_Speed : GPIO_InitTypeDef
  • GTPR : USART_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • HCLK_Frequency : RCC_ClocksTypeDef
  • HTR : ADC_TypeDef
  • HYSCR1 : RI_TypeDef
  • HYSCR2 : RI_TypeDef
  • HYSCR3 : RI_TypeDef
  • HYSCR4 : RI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2C_Ack : I2C_InitTypeDef
  • I2C_AcknowledgedAddress : I2C_InitTypeDef
  • I2C_ClockSpeed : I2C_InitTypeDef
  • I2C_DutyCycle : I2C_InitTypeDef
  • I2C_Mode : I2C_InitTypeDef
  • I2C_OwnAddress1 : I2C_InitTypeDef
  • I2S_AudioFreq : I2S_InitTypeDef
  • I2S_CPOL : I2S_InitTypeDef
  • I2S_DataFormat : I2S_InitTypeDef
  • I2S_MCLKOutput : I2S_InitTypeDef
  • I2S_Mode : I2S_InitTypeDef
  • I2S_Standard : I2S_InitTypeDef
  • I2SCFGR : SPI_TypeDef
  • I2SPR : SPI_TypeDef
  • ICR : SDIO_TypeDef , RI_TypeDef
  • ICSCR : RCC_TypeDef
  • IDCODE : DBGMCU_TypeDef
  • IDR : CRC_TypeDef , GPIO_TypeDef
  • IFCR : DMA_TypeDef
  • IMR : EXTI_TypeDef
  • ISR : DMA_TypeDef , RTC_TypeDef
  • IVR0 : AES_TypeDef
  • IVR1 : AES_TypeDef
  • IVR2 : AES_TypeDef
  • IVR3 : AES_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PCLK1_Frequency : RCC_ClocksTypeDef
  • PCLK2_Frequency : RCC_ClocksTypeDef
  • PDKEYR : FLASH_TypeDef
  • PECR : FLASH_TypeDef
  • PEKEYR : FLASH_TypeDef
  • PMC : SYSCFG_TypeDef
  • POWER : SDIO_TypeDef
  • PR : EXTI_TypeDef , IWDG_TypeDef
  • PRER : RTC_TypeDef
  • PRGKEYR : FLASH_TypeDef
  • PSC : TIM_TypeDef
  • PUPDR : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RAM : LCD_TypeDef
  • RDP : OB_TypeDef
  • RESERVED : LCD_TypeDef , FLASH_TypeDef
  • RESERVED0 : SDIO_TypeDef , SPI_TypeDef , CRC_TypeDef , TIM_TypeDef , USART_TypeDef , GPIO_TypeDef , I2C_TypeDef
  • RESERVED1 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef , CRC_TypeDef , GPIO_TypeDef , I2C_TypeDef , SDIO_TypeDef
  • RESERVED10 : TIM_TypeDef
  • RESERVED12 : TIM_TypeDef
  • RESERVED17 : TIM_TypeDef
  • RESERVED18 : TIM_TypeDef
  • RESERVED19 : TIM_TypeDef
  • RESERVED2 : GPIO_TypeDef , I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED20 : TIM_TypeDef
  • RESERVED3 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef , GPIO_TypeDef , I2C_TypeDef
  • RESERVED4 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED5 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED6 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED7 : I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef
  • RESERVED8 : TIM_TypeDef , SPI_TypeDef , I2C_TypeDef
  • RESP1 : SDIO_TypeDef
  • RESP2 : SDIO_TypeDef
  • RESP3 : SDIO_TypeDef
  • RESP4 : SDIO_TypeDef
  • RESPCMD : SDIO_TypeDef
  • RLR : IWDG_TypeDef
  • RTC_AlarmDateWeekDay : RTC_AlarmTypeDef
  • RTC_AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • RTC_AlarmMask : RTC_AlarmTypeDef
  • RTC_AlarmTime : RTC_AlarmTypeDef
  • RTC_AsynchPrediv : RTC_InitTypeDef
  • RTC_Date : RTC_DateTypeDef
  • RTC_H12 : RTC_TimeTypeDef
  • RTC_HourFormat : RTC_InitTypeDef
  • RTC_Hours : RTC_TimeTypeDef
  • RTC_Minutes : RTC_TimeTypeDef
  • RTC_Month : RTC_DateTypeDef
  • RTC_Seconds : RTC_TimeTypeDef
  • RTC_SynchPrediv : RTC_InitTypeDef
  • RTC_WeekDay : RTC_DateTypeDef
  • RTC_Year : RTC_DateTypeDef
  • RTSR : EXTI_TypeDef
  • RXCRCR : SPI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SDIO_Argument : SDIO_CmdInitTypeDef
  • SDIO_BusWide : SDIO_InitTypeDef
  • SDIO_ClockBypass : SDIO_InitTypeDef
  • SDIO_ClockDiv : SDIO_InitTypeDef
  • SDIO_ClockEdge : SDIO_InitTypeDef
  • SDIO_ClockPowerSave : SDIO_InitTypeDef
  • SDIO_CmdIndex : SDIO_CmdInitTypeDef
  • SDIO_CPSM : SDIO_CmdInitTypeDef
  • SDIO_DataBlockSize : SDIO_DataInitTypeDef
  • SDIO_DataLength : SDIO_DataInitTypeDef
  • SDIO_DataTimeOut : SDIO_DataInitTypeDef
  • SDIO_DPSM : SDIO_DataInitTypeDef
  • SDIO_HardwareFlowControl : SDIO_InitTypeDef
  • SDIO_Response : SDIO_CmdInitTypeDef
  • SDIO_TransferDir : SDIO_DataInitTypeDef
  • SDIO_TransferMode : SDIO_DataInitTypeDef
  • SDIO_Wait : SDIO_CmdInitTypeDef
  • SHIFTR : RTC_TypeDef
  • SMCR : TIM_TypeDef
  • SMPR0 : ADC_TypeDef
  • SMPR1 : ADC_TypeDef
  • SMPR2 : ADC_TypeDef
  • SMPR3 : ADC_TypeDef
  • SPI_BaudRatePrescaler : SPI_InitTypeDef
  • SPI_CPHA : SPI_InitTypeDef
  • SPI_CPOL : SPI_InitTypeDef
  • SPI_CRCPolynomial : SPI_InitTypeDef
  • SPI_DataSize : SPI_InitTypeDef
  • SPI_Direction : SPI_InitTypeDef
  • SPI_FirstBit : SPI_InitTypeDef
  • SPI_Mode : SPI_InitTypeDef
  • SPI_NSS : SPI_InitTypeDef
  • SQR1 : ADC_TypeDef
  • SQR2 : ADC_TypeDef
  • SQR3 : ADC_TypeDef
  • SQR4 : ADC_TypeDef
  • SQR5 : ADC_TypeDef
  • SR : ADC_TypeDef , TIM_TypeDef , USART_TypeDef , AES_TypeDef , DAC_TypeDef , LCD_TypeDef , WWDG_TypeDef , FLASH_TypeDef , SPI_TypeDef , IWDG_TypeDef
  • SR1 : I2C_TypeDef
  • SR2 : I2C_TypeDef
  • SSR : RTC_TypeDef
  • STA : SDIO_TypeDef
  • SWIER : EXTI_TypeDef
  • SWTRIGR : DAC_TypeDef
  • SYSCLK_Frequency : RCC_ClocksTypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TAFCR : RTC_TypeDef
  • TIM_Channel : TIM_ICInitTypeDef
  • TIM_ClockDivision : TIM_TimeBaseInitTypeDef
  • TIM_CounterMode : TIM_TimeBaseInitTypeDef
  • TIM_ICFilter : TIM_ICInitTypeDef
  • TIM_ICPolarity : TIM_ICInitTypeDef
  • TIM_ICPrescaler : TIM_ICInitTypeDef
  • TIM_ICSelection : TIM_ICInitTypeDef
  • TIM_OCMode : TIM_OCInitTypeDef
  • TIM_OCPolarity : TIM_OCInitTypeDef
  • TIM_OutputState : TIM_OCInitTypeDef
  • TIM_Period : TIM_TimeBaseInitTypeDef
  • TIM_Prescaler : TIM_TimeBaseInitTypeDef
  • TIM_Pulse : TIM_OCInitTypeDef
  • TR : RTC_TypeDef
  • TRISE : I2C_TypeDef
  • TSDR : RTC_TypeDef
  • TSSSR : RTC_TypeDef
  • TSTR : RTC_TypeDef
  • TXCRCR : SPI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • USART_BaudRate : USART_InitTypeDef
  • USART_Clock : USART_ClockInitTypeDef
  • USART_CPHA : USART_ClockInitTypeDef
  • USART_CPOL : USART_ClockInitTypeDef
  • USART_HardwareFlowControl : USART_InitTypeDef
  • USART_LastBit : USART_ClockInitTypeDef
  • USART_Mode : USART_InitTypeDef
  • USART_Parity : USART_InitTypeDef
  • USART_StopBits : USART_InitTypeDef
  • USART_WordLength : USART_InitTypeDef
  • USER : OB_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WPR : RTC_TypeDef
  • WRP01 : OB_TypeDef
  • WRP1011 : OB_TypeDef
  • WRP23 : OB_TypeDef
  • WRP45 : OB_TypeDef
  • WRP67 : OB_TypeDef
  • WRP89 : OB_TypeDef
  • WRPR : FLASH_TypeDef
  • WRPR1 : FLASH_TypeDef
  • WRPR2 : FLASH_TypeDef
  • WUTR : RTC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- a -

  • ACR : FLASH_TypeDef
  • ADC_ContinuousConvMode : ADC_InitTypeDef
  • ADC_DataAlign : ADC_InitTypeDef
  • ADC_ExternalTrigConv : ADC_InitTypeDef
  • ADC_ExternalTrigConvEdge : ADC_InitTypeDef
  • ADC_NbrOfConversion : ADC_InitTypeDef
  • ADC_Prescaler : ADC_CommonInitTypeDef
  • ADC_Resolution : ADC_InitTypeDef
  • ADC_ScanConvMode : ADC_InitTypeDef
  • AES_Chaining : AES_InitTypeDef
  • AES_DataType : AES_InitTypeDef
  • AES_IV0 : AES_IVInitTypeDef
  • AES_IV1 : AES_IVInitTypeDef
  • AES_IV2 : AES_IVInitTypeDef
  • AES_IV3 : AES_IVInitTypeDef
  • AES_Key0 : AES_KeyInitTypeDef
  • AES_Key1 : AES_KeyInitTypeDef
  • AES_Key2 : AES_KeyInitTypeDef
  • AES_Key3 : AES_KeyInitTypeDef
  • AES_Operation : AES_InitTypeDef
  • AFR : GPIO_TypeDef
  • AHBENR : RCC_TypeDef
  • AHBLPENR : RCC_TypeDef
  • AHBRSTR : RCC_TypeDef
  • ALRMAR : RTC_TypeDef
  • ALRMASSR : RTC_TypeDef
  • ALRMBR : RTC_TypeDef
  • ALRMBSSR : RTC_TypeDef
  • APB1ENR : RCC_TypeDef
  • APB1FZ : DBGMCU_TypeDef
  • APB1LPENR : RCC_TypeDef
  • APB1RSTR : RCC_TypeDef
  • APB2ENR : RCC_TypeDef
  • APB2FZ : DBGMCU_TypeDef
  • APB2LPENR : RCC_TypeDef
  • APB2RSTR : RCC_TypeDef
  • ARG : SDIO_TypeDef
  • ARR : TIM_TypeDef
  • ASCR1 : RI_TypeDef
  • ASCR2 : RI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- j -

  • JDR1 : ADC_TypeDef
  • JDR2 : ADC_TypeDef
  • JDR3 : ADC_TypeDef
  • JDR4 : ADC_TypeDef
  • JOFR1 : ADC_TypeDef
  • JOFR2 : ADC_TypeDef
  • JOFR3 : ADC_TypeDef
  • JOFR4 : ADC_TypeDef
  • JSQR : ADC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- k -

  • KEYR0 : AES_TypeDef
  • KEYR1 : AES_TypeDef
  • KEYR2 : AES_TypeDef
  • KEYR3 : AES_TypeDef
  • KR : IWDG_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- l -

  • LCD_Bias : LCD_InitTypeDef
  • LCD_Divider : LCD_InitTypeDef
  • LCD_Duty : LCD_InitTypeDef
  • LCD_Prescaler : LCD_InitTypeDef
  • LCD_VoltageSource : LCD_InitTypeDef
  • LCKR : GPIO_TypeDef
  • LPOTR : OPAMP_TypeDef
  • LTR : ADC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- m -

  • MASK : SDIO_TypeDef
  • MEMRMP : SYSCFG_TypeDef
  • MODER : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- n -

  • NVIC_IRQChannel : NVIC_InitTypeDef
  • NVIC_IRQChannelCmd : NVIC_InitTypeDef
  • NVIC_IRQChannelPreemptionPriority : NVIC_InitTypeDef
  • NVIC_IRQChannelSubPriority : NVIC_InitTypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- o -

  • OAR1 : I2C_TypeDef
  • OAR2 : I2C_TypeDef
  • OBR : FLASH_TypeDef
  • ODR : GPIO_TypeDef
  • OPTKEYR : FLASH_TypeDef
  • OR : TIM_TypeDef
  • OSPEEDR : GPIO_TypeDef
  • OTR : OPAMP_TypeDef
  • OTYPER : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- b -

  • BKP0R : RTC_TypeDef
  • BKP10R : RTC_TypeDef
  • BKP11R : RTC_TypeDef
  • BKP12R : RTC_TypeDef
  • BKP13R : RTC_TypeDef
  • BKP14R : RTC_TypeDef
  • BKP15R : RTC_TypeDef
  • BKP16R : RTC_TypeDef
  • BKP17R : RTC_TypeDef
  • BKP18R : RTC_TypeDef
  • BKP19R : RTC_TypeDef
  • BKP1R : RTC_TypeDef
  • BKP20R : RTC_TypeDef
  • BKP21R : RTC_TypeDef
  • BKP22R : RTC_TypeDef
  • BKP23R : RTC_TypeDef
  • BKP24R : RTC_TypeDef
  • BKP25R : RTC_TypeDef
  • BKP26R : RTC_TypeDef
  • BKP27R : RTC_TypeDef
  • BKP28R : RTC_TypeDef
  • BKP29R : RTC_TypeDef
  • BKP2R : RTC_TypeDef
  • BKP30R : RTC_TypeDef
  • BKP31R : RTC_TypeDef
  • BKP3R : RTC_TypeDef
  • BKP4R : RTC_TypeDef
  • BKP5R : RTC_TypeDef
  • BKP6R : RTC_TypeDef
  • BKP7R : RTC_TypeDef
  • BKP8R : RTC_TypeDef
  • BKP9R : RTC_TypeDef
  • BRR : USART_TypeDef , GPIO_TypeDef
  • BSRRH : GPIO_TypeDef
  • BSRRL : GPIO_TypeDef
  • BTCR : FSMC_Bank1_TypeDef
  • BWTR : FSMC_Bank1E_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- c -

  • CALIBR : RTC_TypeDef
  • CALR : RTC_TypeDef
  • CCER : TIM_TypeDef
  • CCMR1 : TIM_TypeDef
  • CCMR2 : TIM_TypeDef
  • CCR : I2C_TypeDef , ADC_Common_TypeDef , DMA_Channel_TypeDef
  • CCR1 : TIM_TypeDef
  • CCR2 : TIM_TypeDef
  • CCR3 : TIM_TypeDef
  • CCR4 : TIM_TypeDef
  • CFGR : RCC_TypeDef
  • CFR : WWDG_TypeDef
  • CIR : RCC_TypeDef
  • CLKCR : SDIO_TypeDef
  • CLR : LCD_TypeDef
  • CMAR : DMA_Channel_TypeDef
  • CMD : SDIO_TypeDef
  • CNDTR : DMA_Channel_TypeDef
  • CNT : TIM_TypeDef
  • COMP_InvertingInput : COMP_InitTypeDef
  • COMP_OutputSelect : COMP_InitTypeDef
  • COMP_Speed : COMP_InitTypeDef
  • CPAR : DMA_Channel_TypeDef
  • CR : RCC_TypeDef , RTC_TypeDef , WWDG_TypeDef , PWR_TypeDef , AES_TypeDef , CRC_TypeDef , DAC_TypeDef , DBGMCU_TypeDef , LCD_TypeDef
  • CR1 : ADC_TypeDef , I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • CR2 : I2C_TypeDef , ADC_TypeDef , USART_TypeDef , SPI_TypeDef , TIM_TypeDef
  • CR3 : USART_TypeDef
  • CRCPR : SPI_TypeDef
  • CSR : RCC_TypeDef , ADC_Common_TypeDef , PWR_TypeDef , COMP_TypeDef , OPAMP_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- d -

  • DAC_LFSRUnmask_TriangleAmplitude : DAC_InitTypeDef
  • DAC_OutputBuffer : DAC_InitTypeDef
  • DAC_Trigger : DAC_InitTypeDef
  • DAC_WaveGeneration : DAC_InitTypeDef
  • DCOUNT : SDIO_TypeDef
  • DCR : TIM_TypeDef
  • DCTRL : SDIO_TypeDef
  • DHR12L1 : DAC_TypeDef
  • DHR12L2 : DAC_TypeDef
  • DHR12LD : DAC_TypeDef
  • DHR12R1 : DAC_TypeDef
  • DHR12R2 : DAC_TypeDef
  • DHR12RD : DAC_TypeDef
  • DHR8R1 : DAC_TypeDef
  • DHR8R2 : DAC_TypeDef
  • DHR8RD : DAC_TypeDef
  • DIER : TIM_TypeDef
  • DINR : AES_TypeDef
  • DLEN : SDIO_TypeDef
  • DMA_BufferSize : DMA_InitTypeDef
  • DMA_DIR : DMA_InitTypeDef
  • DMA_M2M : DMA_InitTypeDef
  • DMA_MemoryBaseAddr : DMA_InitTypeDef
  • DMA_MemoryDataSize : DMA_InitTypeDef
  • DMA_MemoryInc : DMA_InitTypeDef
  • DMA_Mode : DMA_InitTypeDef
  • DMA_PeripheralBaseAddr : DMA_InitTypeDef
  • DMA_PeripheralDataSize : DMA_InitTypeDef
  • DMA_PeripheralInc : DMA_InitTypeDef
  • DMA_Priority : DMA_InitTypeDef
  • DMAR : TIM_TypeDef
  • DOR1 : DAC_TypeDef
  • DOR2 : DAC_TypeDef
  • DOUTR : AES_TypeDef
  • DR : I2C_TypeDef , SPI_TypeDef , CRC_TypeDef , ADC_TypeDef , USART_TypeDef , RTC_TypeDef
  • DTIMER : SDIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- e -

  • EGR : TIM_TypeDef
  • EMR : EXTI_TypeDef
  • EXTI_Line : EXTI_InitTypeDef
  • EXTI_LineCmd : EXTI_InitTypeDef
  • EXTI_Mode : EXTI_InitTypeDef
  • EXTI_Trigger : EXTI_InitTypeDef
  • EXTICR : SYSCFG_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
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- f -

  • FCR : LCD_TypeDef
  • FIFO : SDIO_TypeDef
  • FIFOCNT : SDIO_TypeDef
  • FSMC_AccessMode : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressHoldTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AsynchronousWait : FSMC_NORSRAMInitTypeDef
  • FSMC_Bank : FSMC_NORSRAMInitTypeDef
  • FSMC_BurstAccessMode : FSMC_NORSRAMInitTypeDef
  • FSMC_BusTurnAroundDuration : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CLKDivision : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataAddressMux : FSMC_NORSRAMInitTypeDef
  • FSMC_DataLatency : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_ExtendedMode : FSMC_NORSRAMInitTypeDef
  • FSMC_MemoryDataWidth : FSMC_NORSRAMInitTypeDef
  • FSMC_MemoryType : FSMC_NORSRAMInitTypeDef
  • FSMC_ReadWriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignal : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalActive : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalPolarity : FSMC_NORSRAMInitTypeDef
  • FSMC_WrapMode : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteBurst : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteOperation : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FTSR : EXTI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- g -

  • GPIO_Mode : GPIO_InitTypeDef
  • GPIO_OType : GPIO_InitTypeDef
  • GPIO_Pin : GPIO_InitTypeDef
  • GPIO_PuPd : GPIO_InitTypeDef
  • GPIO_Speed : GPIO_InitTypeDef
  • GTPR : USART_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- h -

  • HCLK_Frequency : RCC_ClocksTypeDef
  • HTR : ADC_TypeDef
  • HYSCR1 : RI_TypeDef
  • HYSCR2 : RI_TypeDef
  • HYSCR3 : RI_TypeDef
  • HYSCR4 : RI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- i -

  • I2C_Ack : I2C_InitTypeDef
  • I2C_AcknowledgedAddress : I2C_InitTypeDef
  • I2C_ClockSpeed : I2C_InitTypeDef
  • I2C_DutyCycle : I2C_InitTypeDef
  • I2C_Mode : I2C_InitTypeDef
  • I2C_OwnAddress1 : I2C_InitTypeDef
  • I2S_AudioFreq : I2S_InitTypeDef
  • I2S_CPOL : I2S_InitTypeDef
  • I2S_DataFormat : I2S_InitTypeDef
  • I2S_MCLKOutput : I2S_InitTypeDef
  • I2S_Mode : I2S_InitTypeDef
  • I2S_Standard : I2S_InitTypeDef
  • I2SCFGR : SPI_TypeDef
  • I2SPR : SPI_TypeDef
  • ICR : SDIO_TypeDef , RI_TypeDef
  • ICSCR : RCC_TypeDef
  • IDCODE : DBGMCU_TypeDef
  • IDR : CRC_TypeDef , GPIO_TypeDef
  • IFCR : DMA_TypeDef
  • IMR : EXTI_TypeDef
  • ISR : DMA_TypeDef , RTC_TypeDef
  • IVR0 : AES_TypeDef
  • IVR1 : AES_TypeDef
  • IVR2 : AES_TypeDef
  • IVR3 : AES_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- p -

  • PCLK1_Frequency : RCC_ClocksTypeDef
  • PCLK2_Frequency : RCC_ClocksTypeDef
  • PDKEYR : FLASH_TypeDef
  • PECR : FLASH_TypeDef
  • PEKEYR : FLASH_TypeDef
  • PMC : SYSCFG_TypeDef
  • POWER : SDIO_TypeDef
  • PR : EXTI_TypeDef , IWDG_TypeDef
  • PRER : RTC_TypeDef
  • PRGKEYR : FLASH_TypeDef
  • PSC : TIM_TypeDef
  • PUPDR : GPIO_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

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- r -

  • RAM : LCD_TypeDef
  • RDP : OB_TypeDef
  • RESERVED : LCD_TypeDef , FLASH_TypeDef
  • RESERVED0 : SDIO_TypeDef , SPI_TypeDef , CRC_TypeDef , TIM_TypeDef , USART_TypeDef , GPIO_TypeDef , I2C_TypeDef
  • RESERVED1 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef , CRC_TypeDef , GPIO_TypeDef , I2C_TypeDef , SDIO_TypeDef
  • RESERVED10 : TIM_TypeDef
  • RESERVED12 : TIM_TypeDef
  • RESERVED17 : TIM_TypeDef
  • RESERVED18 : TIM_TypeDef
  • RESERVED19 : TIM_TypeDef
  • RESERVED2 : GPIO_TypeDef , I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED20 : TIM_TypeDef
  • RESERVED3 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef , GPIO_TypeDef , I2C_TypeDef
  • RESERVED4 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED5 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED6 : I2C_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED7 : I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef
  • RESERVED8 : TIM_TypeDef , SPI_TypeDef , I2C_TypeDef
  • RESP1 : SDIO_TypeDef
  • RESP2 : SDIO_TypeDef
  • RESP3 : SDIO_TypeDef
  • RESP4 : SDIO_TypeDef
  • RESPCMD : SDIO_TypeDef
  • RLR : IWDG_TypeDef
  • RTC_AlarmDateWeekDay : RTC_AlarmTypeDef
  • RTC_AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • RTC_AlarmMask : RTC_AlarmTypeDef
  • RTC_AlarmTime : RTC_AlarmTypeDef
  • RTC_AsynchPrediv : RTC_InitTypeDef
  • RTC_Date : RTC_DateTypeDef
  • RTC_H12 : RTC_TimeTypeDef
  • RTC_HourFormat : RTC_InitTypeDef
  • RTC_Hours : RTC_TimeTypeDef
  • RTC_Minutes : RTC_TimeTypeDef
  • RTC_Month : RTC_DateTypeDef
  • RTC_Seconds : RTC_TimeTypeDef
  • RTC_SynchPrediv : RTC_InitTypeDef
  • RTC_WeekDay : RTC_DateTypeDef
  • RTC_Year : RTC_DateTypeDef
  • RTSR : EXTI_TypeDef
  • RXCRCR : SPI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
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- s -

  • SDIO_Argument : SDIO_CmdInitTypeDef
  • SDIO_BusWide : SDIO_InitTypeDef
  • SDIO_ClockBypass : SDIO_InitTypeDef
  • SDIO_ClockDiv : SDIO_InitTypeDef
  • SDIO_ClockEdge : SDIO_InitTypeDef
  • SDIO_ClockPowerSave : SDIO_InitTypeDef
  • SDIO_CmdIndex : SDIO_CmdInitTypeDef
  • SDIO_CPSM : SDIO_CmdInitTypeDef
  • SDIO_DataBlockSize : SDIO_DataInitTypeDef
  • SDIO_DataLength : SDIO_DataInitTypeDef
  • SDIO_DataTimeOut : SDIO_DataInitTypeDef
  • SDIO_DPSM : SDIO_DataInitTypeDef
  • SDIO_HardwareFlowControl : SDIO_InitTypeDef
  • SDIO_Response : SDIO_CmdInitTypeDef
  • SDIO_TransferDir : SDIO_DataInitTypeDef
  • SDIO_TransferMode : SDIO_DataInitTypeDef
  • SDIO_Wait : SDIO_CmdInitTypeDef
  • SHIFTR : RTC_TypeDef
  • SMCR : TIM_TypeDef
  • SMPR0 : ADC_TypeDef
  • SMPR1 : ADC_TypeDef
  • SMPR2 : ADC_TypeDef
  • SMPR3 : ADC_TypeDef
  • SPI_BaudRatePrescaler : SPI_InitTypeDef
  • SPI_CPHA : SPI_InitTypeDef
  • SPI_CPOL : SPI_InitTypeDef
  • SPI_CRCPolynomial : SPI_InitTypeDef
  • SPI_DataSize : SPI_InitTypeDef
  • SPI_Direction : SPI_InitTypeDef
  • SPI_FirstBit : SPI_InitTypeDef
  • SPI_Mode : SPI_InitTypeDef
  • SPI_NSS : SPI_InitTypeDef
  • SQR1 : ADC_TypeDef
  • SQR2 : ADC_TypeDef
  • SQR3 : ADC_TypeDef
  • SQR4 : ADC_TypeDef
  • SQR5 : ADC_TypeDef
  • SR : ADC_TypeDef , TIM_TypeDef , USART_TypeDef , AES_TypeDef , DAC_TypeDef , LCD_TypeDef , WWDG_TypeDef , FLASH_TypeDef , SPI_TypeDef , IWDG_TypeDef
  • SR1 : I2C_TypeDef
  • SR2 : I2C_TypeDef
  • SSR : RTC_TypeDef
  • STA : SDIO_TypeDef
  • SWIER : EXTI_TypeDef
  • SWTRIGR : DAC_TypeDef
  • SYSCLK_Frequency : RCC_ClocksTypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
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- t -

  • TAFCR : RTC_TypeDef
  • TIM_Channel : TIM_ICInitTypeDef
  • TIM_ClockDivision : TIM_TimeBaseInitTypeDef
  • TIM_CounterMode : TIM_TimeBaseInitTypeDef
  • TIM_ICFilter : TIM_ICInitTypeDef
  • TIM_ICPolarity : TIM_ICInitTypeDef
  • TIM_ICPrescaler : TIM_ICInitTypeDef
  • TIM_ICSelection : TIM_ICInitTypeDef
  • TIM_OCMode : TIM_OCInitTypeDef
  • TIM_OCPolarity : TIM_OCInitTypeDef
  • TIM_OutputState : TIM_OCInitTypeDef
  • TIM_Period : TIM_TimeBaseInitTypeDef
  • TIM_Prescaler : TIM_TimeBaseInitTypeDef
  • TIM_Pulse : TIM_OCInitTypeDef
  • TR : RTC_TypeDef
  • TRISE : I2C_TypeDef
  • TSDR : RTC_TypeDef
  • TSSSR : RTC_TypeDef
  • TSTR : RTC_TypeDef
  • TXCRCR : SPI_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- u -

  • USART_BaudRate : USART_InitTypeDef
  • USART_Clock : USART_ClockInitTypeDef
  • USART_CPHA : USART_ClockInitTypeDef
  • USART_CPOL : USART_ClockInitTypeDef
  • USART_HardwareFlowControl : USART_InitTypeDef
  • USART_LastBit : USART_ClockInitTypeDef
  • USART_Mode : USART_InitTypeDef
  • USART_Parity : USART_InitTypeDef
  • USART_StopBits : USART_InitTypeDef
  • USART_WordLength : USART_InitTypeDef
  • USER : OB_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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- w -

  • WPR : RTC_TypeDef
  • WRP01 : OB_TypeDef
  • WRP1011 : OB_TypeDef
  • WRP23 : OB_TypeDef
  • WRP45 : OB_TypeDef
  • WRP67 : OB_TypeDef
  • WRP89 : OB_TypeDef
  • WRPR : FLASH_TypeDef
  • WRPR1 : FLASH_TypeDef
  • WRPR2 : FLASH_TypeDef
  • WUTR : RTC_TypeDef


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- j -

  • JDR_OFFSET : stm32l1xx_adc.c
  • JSQR_JL_RESET : stm32l1xx_adc.c
  • JSQR_JL_SET : stm32l1xx_adc.c
  • JSQR_JSQ_SET : stm32l1xx_adc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- k -

  • KR_KEY_ENABLE : stm32l1xx_iwdg.c
  • KR_KEY_RELOAD : stm32l1xx_iwdg.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LCD : stm32l1xx.h
  • LCD_BASE : stm32l1xx.h
  • LCD_Bias_1_2 : stm32l1xx_lcd.h
  • LCD_Bias_1_3 : stm32l1xx_lcd.h
  • LCD_Bias_1_4 : stm32l1xx_lcd.h
  • LCD_BlinkConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_BlinkFrequency_Div1024 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div128 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div16 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div256 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div32 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div512 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div64 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div8 : stm32l1xx_lcd.h
  • LCD_BlinkMode_AllSEG_AllCOM : stm32l1xx_lcd.h
  • LCD_BlinkMode_Off : stm32l1xx_lcd.h
  • LCD_BlinkMode_SEG0_AllCOM : stm32l1xx_lcd.h
  • LCD_BlinkMode_SEG0_COM0 : stm32l1xx_lcd.h
  • LCD_ClearFlag() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_ClearITPendingBit() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_CLR_SOFC : stm32l1xx.h
  • LCD_CLR_UDDC : stm32l1xx.h
  • LCD_Cmd() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Contrast_Level_0 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_1 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_2 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_3 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_4 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_5 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_6 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_7 : stm32l1xx_lcd.h
  • LCD_ContrastConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_CR_BIAS : stm32l1xx.h
  • LCD_CR_BIAS_0 : stm32l1xx.h
  • LCD_CR_BIAS_1 : stm32l1xx.h
  • LCD_CR_DUTY : stm32l1xx.h
  • LCD_CR_DUTY_0 : stm32l1xx.h
  • LCD_CR_DUTY_1 : stm32l1xx.h
  • LCD_CR_DUTY_2 : stm32l1xx.h
  • LCD_CR_LCDEN : stm32l1xx.h
  • LCD_CR_MUX_SEG : stm32l1xx.h
  • LCD_CR_VSEL : stm32l1xx.h
  • LCD_DeadTime_0 : stm32l1xx_lcd.h
  • LCD_DeadTime_1 : stm32l1xx_lcd.h
  • LCD_DeadTime_2 : stm32l1xx_lcd.h
  • LCD_DeadTime_3 : stm32l1xx_lcd.h
  • LCD_DeadTime_4 : stm32l1xx_lcd.h
  • LCD_DeadTime_5 : stm32l1xx_lcd.h
  • LCD_DeadTime_6 : stm32l1xx_lcd.h
  • LCD_DeadTime_7 : stm32l1xx_lcd.h
  • LCD_DeadTimeConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_DeInit() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Divider_16 : stm32l1xx_lcd.h
  • LCD_Divider_17 : stm32l1xx_lcd.h
  • LCD_Divider_18 : stm32l1xx_lcd.h
  • LCD_Divider_19 : stm32l1xx_lcd.h
  • LCD_Divider_20 : stm32l1xx_lcd.h
  • LCD_Divider_21 : stm32l1xx_lcd.h
  • LCD_Divider_22 : stm32l1xx_lcd.h
  • LCD_Divider_23 : stm32l1xx_lcd.h
  • LCD_Divider_24 : stm32l1xx_lcd.h
  • LCD_Divider_25 : stm32l1xx_lcd.h
  • LCD_Divider_26 : stm32l1xx_lcd.h
  • LCD_Divider_27 : stm32l1xx_lcd.h
  • LCD_Divider_28 : stm32l1xx_lcd.h
  • LCD_Divider_29 : stm32l1xx_lcd.h
  • LCD_Divider_30 : stm32l1xx_lcd.h
  • LCD_Divider_31 : stm32l1xx_lcd.h
  • LCD_Duty_1_2 : stm32l1xx_lcd.h
  • LCD_Duty_1_3 : stm32l1xx_lcd.h
  • LCD_Duty_1_4 : stm32l1xx_lcd.h
  • LCD_Duty_1_8 : stm32l1xx_lcd.h
  • LCD_Duty_Static : stm32l1xx_lcd.h
  • LCD_FCR_BLINK : stm32l1xx.h
  • LCD_FCR_BLINK_0 : stm32l1xx.h
  • LCD_FCR_BLINK_1 : stm32l1xx.h
  • LCD_FCR_BLINKF : stm32l1xx.h
  • LCD_FCR_BLINKF_0 : stm32l1xx.h
  • LCD_FCR_BLINKF_1 : stm32l1xx.h
  • LCD_FCR_BLINKF_2 : stm32l1xx.h
  • LCD_FCR_CC : stm32l1xx.h
  • LCD_FCR_CC_0 : stm32l1xx.h
  • LCD_FCR_CC_1 : stm32l1xx.h
  • LCD_FCR_CC_2 : stm32l1xx.h
  • LCD_FCR_DEAD : stm32l1xx.h
  • LCD_FCR_DEAD_0 : stm32l1xx.h
  • LCD_FCR_DEAD_1 : stm32l1xx.h
  • LCD_FCR_DEAD_2 : stm32l1xx.h
  • LCD_FCR_DIV : stm32l1xx.h
  • LCD_FCR_HD : stm32l1xx.h
  • LCD_FCR_PON : stm32l1xx.h
  • LCD_FCR_PON_0 : stm32l1xx.h
  • LCD_FCR_PON_1 : stm32l1xx.h
  • LCD_FCR_PON_2 : stm32l1xx.h
  • LCD_FCR_PS : stm32l1xx.h
  • LCD_FCR_SOFIE : stm32l1xx.h
  • LCD_FCR_UDDIE : stm32l1xx.h
  • LCD_FLAG_ENS : stm32l1xx_lcd.h
  • LCD_FLAG_FCRSF : stm32l1xx_lcd.h
  • LCD_FLAG_RDY : stm32l1xx_lcd.h
  • LCD_FLAG_SOF : stm32l1xx_lcd.h
  • LCD_FLAG_UDD : stm32l1xx_lcd.h
  • LCD_FLAG_UDR : stm32l1xx_lcd.h
  • LCD_GetFlagStatus() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_GetITStatus() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_HighDriveCmd() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Init() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_IRQn : stm32l1xx.h
  • LCD_IT_SOF : stm32l1xx_lcd.h
  • LCD_IT_UDD : stm32l1xx_lcd.h
  • LCD_ITConfig() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_MuxSegmentCmd() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_OFFSET : stm32l1xx_lcd.c
  • LCD_Prescaler_1 : stm32l1xx_lcd.h
  • LCD_Prescaler_1024 : stm32l1xx_lcd.h
  • LCD_Prescaler_128 : stm32l1xx_lcd.h
  • LCD_Prescaler_16 : stm32l1xx_lcd.h
  • LCD_Prescaler_16384 : stm32l1xx_lcd.h
  • LCD_Prescaler_2 : stm32l1xx_lcd.h
  • LCD_Prescaler_2048 : stm32l1xx_lcd.h
  • LCD_Prescaler_256 : stm32l1xx_lcd.h
  • LCD_Prescaler_32 : stm32l1xx_lcd.h
  • LCD_Prescaler_32768 : stm32l1xx_lcd.h
  • LCD_Prescaler_4 : stm32l1xx_lcd.h
  • LCD_Prescaler_4096 : stm32l1xx_lcd.h
  • LCD_Prescaler_512 : stm32l1xx_lcd.h
  • LCD_Prescaler_64 : stm32l1xx_lcd.h
  • LCD_Prescaler_8 : stm32l1xx_lcd.h
  • LCD_Prescaler_8192 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_0 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_1 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_2 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_3 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_4 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_5 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_6 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_7 : stm32l1xx_lcd.h
  • LCD_PulseOnDurationConfig() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_RAM_SEGMENT_DATA : stm32l1xx.h
  • LCD_RAMRegister_0 : stm32l1xx_lcd.h
  • LCD_RAMRegister_1 : stm32l1xx_lcd.h
  • LCD_RAMRegister_10 : stm32l1xx_lcd.h
  • LCD_RAMRegister_11 : stm32l1xx_lcd.h
  • LCD_RAMRegister_12 : stm32l1xx_lcd.h
  • LCD_RAMRegister_13 : stm32l1xx_lcd.h
  • LCD_RAMRegister_14 : stm32l1xx_lcd.h
  • LCD_RAMRegister_15 : stm32l1xx_lcd.h
  • LCD_RAMRegister_2 : stm32l1xx_lcd.h
  • LCD_RAMRegister_3 : stm32l1xx_lcd.h
  • LCD_RAMRegister_4 : stm32l1xx_lcd.h
  • LCD_RAMRegister_5 : stm32l1xx_lcd.h
  • LCD_RAMRegister_6 : stm32l1xx_lcd.h
  • LCD_RAMRegister_7 : stm32l1xx_lcd.h
  • LCD_RAMRegister_8 : stm32l1xx_lcd.h
  • LCD_RAMRegister_9 : stm32l1xx_lcd.h
  • LCD_SR_ENS : stm32l1xx.h
  • LCD_SR_FCRSR : stm32l1xx.h
  • LCD_SR_RDY : stm32l1xx.h
  • LCD_SR_SOF : stm32l1xx.h
  • LCD_SR_UDD : stm32l1xx.h
  • LCD_SR_UDR : stm32l1xx.h
  • LCD_StructInit() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_UpdateDisplayRequest() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_VoltageSource_External : stm32l1xx_lcd.h
  • LCD_VoltageSource_Internal : stm32l1xx_lcd.h
  • LCD_WaitForSynchro() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_Write() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCDEN_BitNumber : stm32l1xx_lcd.c
  • LSE_VALUE : stm32l1xx.h
  • LSECSSON_BitNumber : stm32l1xx_rcc.c
  • LSI_VALUE : stm32l1xx.h
  • LSION_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
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  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MemoryManagement_IRQn : stm32l1xx.h
  • MODIFY_REG : stm32l1xx.h
  • MSION_BitNumber : stm32l1xx_rcc.c
  • MUX_SEG_BitNumber : stm32l1xx_lcd.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NIEN_BitNumber : stm32l1xx_sdio.c
  • NonMaskableInt_IRQn : stm32l1xx.h
  • NVIC_IABR_ACTIVE : stm32l1xx.h
  • NVIC_IABR_ACTIVE_0 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_1 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_10 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_11 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_12 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_13 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_14 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_15 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_16 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_17 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_18 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_19 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_2 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_20 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_21 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_22 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_23 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_24 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_25 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_26 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_27 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_28 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_29 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_3 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_30 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_31 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_4 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_5 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_6 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_7 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_8 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_9 : stm32l1xx.h
  • NVIC_ICER_CLRENA : stm32l1xx.h
  • NVIC_ICER_CLRENA_0 : stm32l1xx.h
  • NVIC_ICER_CLRENA_1 : stm32l1xx.h
  • NVIC_ICER_CLRENA_10 : stm32l1xx.h
  • NVIC_ICER_CLRENA_11 : stm32l1xx.h
  • NVIC_ICER_CLRENA_12 : stm32l1xx.h
  • NVIC_ICER_CLRENA_13 : stm32l1xx.h
  • NVIC_ICER_CLRENA_14 : stm32l1xx.h
  • NVIC_ICER_CLRENA_15 : stm32l1xx.h
  • NVIC_ICER_CLRENA_16 : stm32l1xx.h
  • NVIC_ICER_CLRENA_17 : stm32l1xx.h
  • NVIC_ICER_CLRENA_18 : stm32l1xx.h
  • NVIC_ICER_CLRENA_19 : stm32l1xx.h
  • NVIC_ICER_CLRENA_2 : stm32l1xx.h
  • NVIC_ICER_CLRENA_20 : stm32l1xx.h
  • NVIC_ICER_CLRENA_21 : stm32l1xx.h
  • NVIC_ICER_CLRENA_22 : stm32l1xx.h
  • NVIC_ICER_CLRENA_23 : stm32l1xx.h
  • NVIC_ICER_CLRENA_24 : stm32l1xx.h
  • NVIC_ICER_CLRENA_25 : stm32l1xx.h
  • NVIC_ICER_CLRENA_26 : stm32l1xx.h
  • NVIC_ICER_CLRENA_27 : stm32l1xx.h
  • NVIC_ICER_CLRENA_28 : stm32l1xx.h
  • NVIC_ICER_CLRENA_29 : stm32l1xx.h
  • NVIC_ICER_CLRENA_3 : stm32l1xx.h
  • NVIC_ICER_CLRENA_30 : stm32l1xx.h
  • NVIC_ICER_CLRENA_31 : stm32l1xx.h
  • NVIC_ICER_CLRENA_4 : stm32l1xx.h
  • NVIC_ICER_CLRENA_5 : stm32l1xx.h
  • NVIC_ICER_CLRENA_6 : stm32l1xx.h
  • NVIC_ICER_CLRENA_7 : stm32l1xx.h
  • NVIC_ICER_CLRENA_8 : stm32l1xx.h
  • NVIC_ICER_CLRENA_9 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_0 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_1 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_10 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_11 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_12 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_13 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_14 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_15 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_16 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_17 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_18 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_19 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_2 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_20 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_21 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_22 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_23 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_24 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_25 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_26 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_27 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_28 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_29 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_3 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_30 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_31 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_4 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_5 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_6 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_7 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_8 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_9 : stm32l1xx.h
  • NVIC_Init() : misc.h , misc.c
  • NVIC_IPR0_PRI_0 : stm32l1xx.h
  • NVIC_IPR0_PRI_1 : stm32l1xx.h
  • NVIC_IPR0_PRI_2 : stm32l1xx.h
  • NVIC_IPR0_PRI_3 : stm32l1xx.h
  • NVIC_IPR1_PRI_4 : stm32l1xx.h
  • NVIC_IPR1_PRI_5 : stm32l1xx.h
  • NVIC_IPR1_PRI_6 : stm32l1xx.h
  • NVIC_IPR1_PRI_7 : stm32l1xx.h
  • NVIC_IPR2_PRI_10 : stm32l1xx.h
  • NVIC_IPR2_PRI_11 : stm32l1xx.h
  • NVIC_IPR2_PRI_8 : stm32l1xx.h
  • NVIC_IPR2_PRI_9 : stm32l1xx.h
  • NVIC_IPR3_PRI_12 : stm32l1xx.h
  • NVIC_IPR3_PRI_13 : stm32l1xx.h
  • NVIC_IPR3_PRI_14 : stm32l1xx.h
  • NVIC_IPR3_PRI_15 : stm32l1xx.h
  • NVIC_IPR4_PRI_16 : stm32l1xx.h
  • NVIC_IPR4_PRI_17 : stm32l1xx.h
  • NVIC_IPR4_PRI_18 : stm32l1xx.h
  • NVIC_IPR4_PRI_19 : stm32l1xx.h
  • NVIC_IPR5_PRI_20 : stm32l1xx.h
  • NVIC_IPR5_PRI_21 : stm32l1xx.h
  • NVIC_IPR5_PRI_22 : stm32l1xx.h
  • NVIC_IPR5_PRI_23 : stm32l1xx.h
  • NVIC_IPR6_PRI_24 : stm32l1xx.h
  • NVIC_IPR6_PRI_25 : stm32l1xx.h
  • NVIC_IPR6_PRI_26 : stm32l1xx.h
  • NVIC_IPR6_PRI_27 : stm32l1xx.h
  • NVIC_IPR7_PRI_28 : stm32l1xx.h
  • NVIC_IPR7_PRI_29 : stm32l1xx.h
  • NVIC_IPR7_PRI_30 : stm32l1xx.h
  • NVIC_IPR7_PRI_31 : stm32l1xx.h
  • NVIC_ISER_SETENA : stm32l1xx.h
  • NVIC_ISER_SETENA_0 : stm32l1xx.h
  • NVIC_ISER_SETENA_1 : stm32l1xx.h
  • NVIC_ISER_SETENA_10 : stm32l1xx.h
  • NVIC_ISER_SETENA_11 : stm32l1xx.h
  • NVIC_ISER_SETENA_12 : stm32l1xx.h
  • NVIC_ISER_SETENA_13 : stm32l1xx.h
  • NVIC_ISER_SETENA_14 : stm32l1xx.h
  • NVIC_ISER_SETENA_15 : stm32l1xx.h
  • NVIC_ISER_SETENA_16 : stm32l1xx.h
  • NVIC_ISER_SETENA_17 : stm32l1xx.h
  • NVIC_ISER_SETENA_18 : stm32l1xx.h
  • NVIC_ISER_SETENA_19 : stm32l1xx.h
  • NVIC_ISER_SETENA_2 : stm32l1xx.h
  • NVIC_ISER_SETENA_20 : stm32l1xx.h
  • NVIC_ISER_SETENA_21 : stm32l1xx.h
  • NVIC_ISER_SETENA_22 : stm32l1xx.h
  • NVIC_ISER_SETENA_23 : stm32l1xx.h
  • NVIC_ISER_SETENA_24 : stm32l1xx.h
  • NVIC_ISER_SETENA_25 : stm32l1xx.h
  • NVIC_ISER_SETENA_26 : stm32l1xx.h
  • NVIC_ISER_SETENA_27 : stm32l1xx.h
  • NVIC_ISER_SETENA_28 : stm32l1xx.h
  • NVIC_ISER_SETENA_29 : stm32l1xx.h
  • NVIC_ISER_SETENA_3 : stm32l1xx.h
  • NVIC_ISER_SETENA_30 : stm32l1xx.h
  • NVIC_ISER_SETENA_31 : stm32l1xx.h
  • NVIC_ISER_SETENA_4 : stm32l1xx.h
  • NVIC_ISER_SETENA_5 : stm32l1xx.h
  • NVIC_ISER_SETENA_6 : stm32l1xx.h
  • NVIC_ISER_SETENA_7 : stm32l1xx.h
  • NVIC_ISER_SETENA_8 : stm32l1xx.h
  • NVIC_ISER_SETENA_9 : stm32l1xx.h
  • NVIC_ISPR_SETPEND : stm32l1xx.h
  • NVIC_ISPR_SETPEND_0 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_1 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_10 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_11 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_12 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_13 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_14 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_15 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_16 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_17 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_18 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_19 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_2 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_20 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_21 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_22 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_23 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_24 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_25 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_26 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_27 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_28 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_29 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_3 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_30 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_31 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_4 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_5 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_6 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_7 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_8 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_9 : stm32l1xx.h
  • NVIC_LP_SEVONPEND : misc.h
  • NVIC_LP_SLEEPDEEP : misc.h
  • NVIC_LP_SLEEPONEXIT : misc.h
  • NVIC_PriorityGroup_0 : misc.h
  • NVIC_PriorityGroup_1 : misc.h
  • NVIC_PriorityGroup_2 : misc.h
  • NVIC_PriorityGroup_3 : misc.h
  • NVIC_PriorityGroup_4 : misc.h
  • NVIC_PriorityGroupConfig() : misc.c , misc.h
  • NVIC_SetVectorTable() : misc.h , misc.c
  • NVIC_SystemLPConfig() : misc.c , misc.h
  • NVIC_VectTab_FLASH : misc.h
  • NVIC_VectTab_RAM : misc.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB : stm32l1xx.h
  • OB_BASE : stm32l1xx.h
  • OB_BOOT_BANK1 : stm32l1xx_flash.h
  • OB_BOOT_BANK2 : stm32l1xx_flash.h
  • OB_BOR_LEVEL1 : stm32l1xx_flash.h
  • OB_BOR_LEVEL2 : stm32l1xx_flash.h
  • OB_BOR_LEVEL3 : stm32l1xx_flash.h
  • OB_BOR_LEVEL4 : stm32l1xx_flash.h
  • OB_BOR_LEVEL5 : stm32l1xx_flash.h
  • OB_BOR_OFF : stm32l1xx_flash.h
  • OB_IWDG_HW : stm32l1xx_flash.h
  • OB_IWDG_SW : stm32l1xx_flash.h
  • OB_RDP_Level_0 : stm32l1xx_flash.h
  • OB_RDP_Level_1 : stm32l1xx_flash.h
  • OB_STDBY_NoRST : stm32l1xx_flash.h
  • OB_STDBY_RST : stm32l1xx_flash.h
  • OB_STOP_NoRST : stm32l1xx_flash.h
  • OB_STOP_RST : stm32l1xx_flash.h
  • OB_WRP1_AllPages : stm32l1xx_flash.h
  • OB_WRP1_Pages1008to1023 : stm32l1xx_flash.h
  • OB_WRP1_Pages512to527 : stm32l1xx_flash.h
  • OB_WRP1_Pages528to543 : stm32l1xx_flash.h
  • OB_WRP1_Pages544to559 : stm32l1xx_flash.h
  • OB_WRP1_Pages560to575 : stm32l1xx_flash.h
  • OB_WRP1_Pages576to591 : stm32l1xx_flash.h
  • OB_WRP1_Pages592to607 : stm32l1xx_flash.h
  • OB_WRP1_Pages608to623 : stm32l1xx_flash.h
  • OB_WRP1_Pages624to639 : stm32l1xx_flash.h
  • OB_WRP1_Pages640to655 : stm32l1xx_flash.h
  • OB_WRP1_Pages656to671 : stm32l1xx_flash.h
  • OB_WRP1_Pages672to687 : stm32l1xx_flash.h
  • OB_WRP1_Pages688to703 : stm32l1xx_flash.h
  • OB_WRP1_Pages704to719 : stm32l1xx_flash.h
  • OB_WRP1_Pages720to735 : stm32l1xx_flash.h
  • OB_WRP1_Pages736to751 : stm32l1xx_flash.h
  • OB_WRP1_Pages752to767 : stm32l1xx_flash.h
  • OB_WRP1_Pages768to783 : stm32l1xx_flash.h
  • OB_WRP1_Pages784to799 : stm32l1xx_flash.h
  • OB_WRP1_Pages800to815 : stm32l1xx_flash.h
  • OB_WRP1_Pages816to831 : stm32l1xx_flash.h
  • OB_WRP1_Pages832to847 : stm32l1xx_flash.h
  • OB_WRP1_Pages848to863 : stm32l1xx_flash.h
  • OB_WRP1_Pages864to879 : stm32l1xx_flash.h
  • OB_WRP1_Pages880to895 : stm32l1xx_flash.h
  • OB_WRP1_Pages896to911 : stm32l1xx_flash.h
  • OB_WRP1_Pages912to927 : stm32l1xx_flash.h
  • OB_WRP1_Pages928to943 : stm32l1xx_flash.h
  • OB_WRP1_Pages944to959 : stm32l1xx_flash.h
  • OB_WRP1_Pages960to975 : stm32l1xx_flash.h
  • OB_WRP1_Pages976to991 : stm32l1xx_flash.h
  • OB_WRP1_Pages992to1007 : stm32l1xx_flash.h
  • OB_WRP2_AllPages : stm32l1xx_flash.h
  • OB_WRP2_Pages1024to1039 : stm32l1xx_flash.h
  • OB_WRP2_Pages1040to1055 : stm32l1xx_flash.h
  • OB_WRP2_Pages1056to1071 : stm32l1xx_flash.h
  • OB_WRP2_Pages1072to1087 : stm32l1xx_flash.h
  • OB_WRP2_Pages1088to1103 : stm32l1xx_flash.h
  • OB_WRP2_Pages1104to1119 : stm32l1xx_flash.h
  • OB_WRP2_Pages1120to1135 : stm32l1xx_flash.h
  • OB_WRP2_Pages1136to1151 : stm32l1xx_flash.h
  • OB_WRP2_Pages1152to1167 : stm32l1xx_flash.h
  • OB_WRP2_Pages1168to1183 : stm32l1xx_flash.h
  • OB_WRP2_Pages1184to1199 : stm32l1xx_flash.h
  • OB_WRP2_Pages1200to1215 : stm32l1xx_flash.h
  • OB_WRP2_Pages1216to1231 : stm32l1xx_flash.h
  • OB_WRP2_Pages1232to1247 : stm32l1xx_flash.h
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  • OPAMP : stm32l1xx.h
  • OPAMP_BASE : stm32l1xx.h
  • OPAMP_Cmd() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_CSR_ANAWSEL1 : stm32l1xx.h
  • OPAMP_CSR_ANAWSEL2 : stm32l1xx.h
  • OPAMP_CSR_ANAWSEL3 : stm32l1xx.h
  • OPAMP_CSR_AOP_RANGE : stm32l1xx.h
  • OPAMP_CSR_OPA1CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA1CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA1CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA1LPM : stm32l1xx.h
  • OPAMP_CSR_OPA1PD : stm32l1xx.h
  • OPAMP_CSR_OPA2CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA2CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA2CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA2LPM : stm32l1xx.h
  • OPAMP_CSR_OPA2PD : stm32l1xx.h
  • OPAMP_CSR_OPA3CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA3CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA3CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA3LPM : stm32l1xx.h
  • OPAMP_CSR_OPA3PD : stm32l1xx.h
  • OPAMP_CSR_S3SEL1 : stm32l1xx.h
  • OPAMP_CSR_S3SEL2 : stm32l1xx.h
  • OPAMP_CSR_S3SEL3 : stm32l1xx.h
  • OPAMP_CSR_S4SEL1 : stm32l1xx.h
  • OPAMP_CSR_S4SEL2 : stm32l1xx.h
  • OPAMP_CSR_S4SEL3 : stm32l1xx.h
  • OPAMP_CSR_S5SEL1 : stm32l1xx.h
  • OPAMP_CSR_S5SEL2 : stm32l1xx.h
  • OPAMP_CSR_S5SEL3 : stm32l1xx.h
  • OPAMP_CSR_S6SEL1 : stm32l1xx.h
  • OPAMP_CSR_S6SEL2 : stm32l1xx.h
  • OPAMP_CSR_S6SEL3 : stm32l1xx.h
  • OPAMP_CSR_S7SEL2 : stm32l1xx.h
  • OPAMP_DeInit() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_GetFlagStatus() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_Input_NMOS : stm32l1xx_opamp.h
  • OPAMP_Input_PMOS : stm32l1xx_opamp.h
  • OPAMP_LowPowerCmd() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_OffsetTrimConfig() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_OffsetTrimLowPowerConfig() : stm32l1xx_opamp.c , stm32l1xx_opamp.h
  • OPAMP_OffsetTrimmingModeSelect() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_OPAMP1Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch7 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OTR_AO1_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_AO2_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_AO3_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_OT_USER : stm32l1xx.h
  • OPAMP_PowerRange_High : stm32l1xx_opamp.h
  • OPAMP_PowerRange_Low : stm32l1xx_opamp.h
  • OPAMP_PowerRangeSelect() : stm32l1xx_opamp.c , stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP1 : stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP2 : stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP3 : stm32l1xx_opamp.h
  • OPAMP_SwitchCmd() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_Trimming_Factory : stm32l1xx_opamp.h
  • OPAMP_Trimming_User : stm32l1xx_opamp.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC : stm32l1xx.h
  • ADC1 : stm32l1xx.h
  • ADC1_BASE : stm32l1xx.h
  • ADC1_IRQn : stm32l1xx.h
  • ADC_AnalogWatchdog_AllInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_AllRegAllInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_AllRegEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_None : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleRegEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdogCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_AnalogWatchdogSingleChannelConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_AnalogWatchdogThresholdsConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_AutoInjectedConvCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Bank_A : stm32l1xx_adc.h
  • ADC_Bank_B : stm32l1xx_adc.h
  • ADC_BankSelection() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_BASE : stm32l1xx.h
  • ADC_CCR_ADCPRE : stm32l1xx.h
  • ADC_CCR_ADCPRE_0 : stm32l1xx.h
  • ADC_CCR_ADCPRE_1 : stm32l1xx.h
  • ADC_CCR_TSVREFE : stm32l1xx.h
  • ADC_Channel_0 : stm32l1xx_adc.h
  • ADC_Channel_0b : stm32l1xx_adc.h
  • ADC_Channel_1 : stm32l1xx_adc.h
  • ADC_Channel_10 : stm32l1xx_adc.h
  • ADC_Channel_10b : stm32l1xx_adc.h
  • ADC_Channel_11 : stm32l1xx_adc.h
  • ADC_Channel_11b : stm32l1xx_adc.h
  • ADC_Channel_12 : stm32l1xx_adc.h
  • ADC_Channel_12b : stm32l1xx_adc.h
  • ADC_Channel_13 : stm32l1xx_adc.h
  • ADC_Channel_14 : stm32l1xx_adc.h
  • ADC_Channel_15 : stm32l1xx_adc.h
  • ADC_Channel_16 : stm32l1xx_adc.h
  • ADC_Channel_17 : stm32l1xx_adc.h
  • ADC_Channel_18 : stm32l1xx_adc.h
  • ADC_Channel_19 : stm32l1xx_adc.h
  • ADC_Channel_1b : stm32l1xx_adc.h
  • ADC_Channel_2 : stm32l1xx_adc.h
  • ADC_Channel_20 : stm32l1xx_adc.h
  • ADC_Channel_21 : stm32l1xx_adc.h
  • ADC_Channel_22 : stm32l1xx_adc.h
  • ADC_Channel_23 : stm32l1xx_adc.h
  • ADC_Channel_24 : stm32l1xx_adc.h
  • ADC_Channel_25 : stm32l1xx_adc.h
  • ADC_Channel_27 : stm32l1xx_adc.h
  • ADC_Channel_28 : stm32l1xx_adc.h
  • ADC_Channel_29 : stm32l1xx_adc.h
  • ADC_Channel_2b : stm32l1xx_adc.h
  • ADC_Channel_3 : stm32l1xx_adc.h
  • ADC_Channel_30 : stm32l1xx_adc.h
  • ADC_Channel_31 : stm32l1xx_adc.h
  • ADC_Channel_3b : stm32l1xx_adc.h
  • ADC_Channel_4 : stm32l1xx_adc.h
  • ADC_Channel_5 : stm32l1xx_adc.h
  • ADC_Channel_6 : stm32l1xx_adc.h
  • ADC_Channel_6b : stm32l1xx_adc.h
  • ADC_Channel_7 : stm32l1xx_adc.h
  • ADC_Channel_7b : stm32l1xx_adc.h
  • ADC_Channel_8 : stm32l1xx_adc.h
  • ADC_Channel_8b : stm32l1xx_adc.h
  • ADC_Channel_9 : stm32l1xx_adc.h
  • ADC_Channel_9b : stm32l1xx_adc.h
  • ADC_Channel_TempSensor : stm32l1xx_adc.h
  • ADC_Channel_Vrefint : stm32l1xx_adc.h
  • ADC_ClearFlag() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ClearITPendingBit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Cmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_CommonInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_CommonStructInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ContinuousModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_CR1_AWDCH : stm32l1xx.h
  • ADC_CR1_AWDCH_0 : stm32l1xx.h
  • ADC_CR1_AWDCH_1 : stm32l1xx.h
  • ADC_CR1_AWDCH_2 : stm32l1xx.h
  • ADC_CR1_AWDCH_3 : stm32l1xx.h
  • ADC_CR1_AWDCH_4 : stm32l1xx.h
  • ADC_CR1_AWDEN : stm32l1xx.h
  • ADC_CR1_AWDIE : stm32l1xx.h
  • ADC_CR1_AWDSGL : stm32l1xx.h
  • ADC_CR1_DISCEN : stm32l1xx.h
  • ADC_CR1_DISCNUM : stm32l1xx.h
  • ADC_CR1_DISCNUM_0 : stm32l1xx.h
  • ADC_CR1_DISCNUM_1 : stm32l1xx.h
  • ADC_CR1_DISCNUM_2 : stm32l1xx.h
  • ADC_CR1_EOCIE : stm32l1xx.h
  • ADC_CR1_JAUTO : stm32l1xx.h
  • ADC_CR1_JAWDEN : stm32l1xx.h
  • ADC_CR1_JDISCEN : stm32l1xx.h
  • ADC_CR1_JEOCIE : stm32l1xx.h
  • ADC_CR1_OVRIE : stm32l1xx.h
  • ADC_CR1_PDD : stm32l1xx.h
  • ADC_CR1_PDI : stm32l1xx.h
  • ADC_CR1_RES : stm32l1xx.h
  • ADC_CR1_RES_0 : stm32l1xx.h
  • ADC_CR1_RES_1 : stm32l1xx.h
  • ADC_CR1_SCAN : stm32l1xx.h
  • ADC_CR2_ADON : stm32l1xx.h
  • ADC_CR2_ALIGN : stm32l1xx.h
  • ADC_CR2_CFG : stm32l1xx.h
  • ADC_CR2_CONT : stm32l1xx.h
  • ADC_CR2_DDS : stm32l1xx.h
  • ADC_CR2_DELS : stm32l1xx.h
  • ADC_CR2_DELS_0 : stm32l1xx.h
  • ADC_CR2_DELS_1 : stm32l1xx.h
  • ADC_CR2_DELS_2 : stm32l1xx.h
  • ADC_CR2_DMA : stm32l1xx.h
  • ADC_CR2_EOCS : stm32l1xx.h
  • ADC_CR2_EXTEN : stm32l1xx.h
  • ADC_CR2_EXTEN_0 : stm32l1xx.h
  • ADC_CR2_EXTEN_1 : stm32l1xx.h
  • ADC_CR2_EXTSEL : stm32l1xx.h
  • ADC_CR2_EXTSEL_0 : stm32l1xx.h
  • ADC_CR2_EXTSEL_1 : stm32l1xx.h
  • ADC_CR2_EXTSEL_2 : stm32l1xx.h
  • ADC_CR2_EXTSEL_3 : stm32l1xx.h
  • ADC_CR2_JEXTEN : stm32l1xx.h
  • ADC_CR2_JEXTEN_0 : stm32l1xx.h
  • ADC_CR2_JEXTEN_1 : stm32l1xx.h
  • ADC_CR2_JEXTSEL : stm32l1xx.h
  • ADC_CR2_JEXTSEL_0 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_1 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_2 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_3 : stm32l1xx.h
  • ADC_CR2_JSWSTART : stm32l1xx.h
  • ADC_CR2_SWSTART : stm32l1xx.h
  • ADC_CSR_ADONS1 : stm32l1xx.h
  • ADC_CSR_AWD1 : stm32l1xx.h
  • ADC_CSR_EOC1 : stm32l1xx.h
  • ADC_CSR_JEOC1 : stm32l1xx.h
  • ADC_CSR_JSTRT1 : stm32l1xx.h
  • ADC_CSR_OVR1 : stm32l1xx.h
  • ADC_CSR_STRT1 : stm32l1xx.h
  • ADC_DataAlign_Left : stm32l1xx_adc.h
  • ADC_DataAlign_Right : stm32l1xx_adc.h
  • ADC_DeInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DelayLength_127Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_15Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_255Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_31Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_63Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_7Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_Freeze : stm32l1xx_adc.h
  • ADC_DelayLength_None : stm32l1xx_adc.h
  • ADC_DelaySelectionConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DiscModeChannelCountConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DiscModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DMACmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DMARequestAfterLastTransferCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DR_DATA : stm32l1xx.h
  • ADC_EOCOnEachRegularChannelCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ExternalTrigConv_Ext_IT11 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T4_CC4 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T4_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T6_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T9_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T9_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_Falling : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_None : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_Rising : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_RisingFalling : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_Ext_IT15 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T10_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T2_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T2_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T3_CC4 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T7_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T9_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T9_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_Falling : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_None : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_Rising : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_RisingFalling : stm32l1xx_adc.h
  • ADC_ExternalTrigInjectedConvConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ExternalTrigInjectedConvEdgeConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_FLAG_ADONS : stm32l1xx_adc.h
  • ADC_FLAG_AWD : stm32l1xx_adc.h
  • ADC_FLAG_EOC : stm32l1xx_adc.h
  • ADC_FLAG_JCNR : stm32l1xx_adc.h
  • ADC_FLAG_JEOC : stm32l1xx_adc.h
  • ADC_FLAG_JSTRT : stm32l1xx_adc.h
  • ADC_FLAG_OVR : stm32l1xx_adc.h
  • ADC_FLAG_RCNR : stm32l1xx_adc.h
  • ADC_FLAG_STRT : stm32l1xx_adc.h
  • ADC_GetConversionValue() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetFlagStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetInjectedConversionValue() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetITStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetSoftwareStartConvStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetSoftwareStartInjectedConvCmdStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_HTR_HT : stm32l1xx.h
  • ADC_Init() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedChannel_1 : stm32l1xx_adc.h
  • ADC_InjectedChannel_2 : stm32l1xx_adc.h
  • ADC_InjectedChannel_3 : stm32l1xx_adc.h
  • ADC_InjectedChannel_4 : stm32l1xx_adc.h
  • ADC_InjectedChannelConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedDiscModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedSequencerLengthConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_IT_AWD : stm32l1xx_adc.h
  • ADC_IT_EOC : stm32l1xx_adc.h
  • ADC_IT_JEOC : stm32l1xx_adc.h
  • ADC_IT_OVR : stm32l1xx_adc.h
  • ADC_ITConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_JDR1_JDATA : stm32l1xx.h
  • ADC_JDR2_JDATA : stm32l1xx.h
  • ADC_JDR3_JDATA : stm32l1xx.h
  • ADC_JDR4_JDATA : stm32l1xx.h
  • ADC_JOFR1_JOFFSET1 : stm32l1xx.h
  • ADC_JOFR2_JOFFSET2 : stm32l1xx.h
  • ADC_JOFR3_JOFFSET3 : stm32l1xx.h
  • ADC_JOFR4_JOFFSET4 : stm32l1xx.h
  • ADC_JSQR_JL : stm32l1xx.h
  • ADC_JSQR_JL_0 : stm32l1xx.h
  • ADC_JSQR_JL_1 : stm32l1xx.h
  • ADC_JSQR_JSQ1 : stm32l1xx.h
  • ADC_JSQR_JSQ1_0 : stm32l1xx.h
  • ADC_JSQR_JSQ1_1 : stm32l1xx.h
  • ADC_JSQR_JSQ1_2 : stm32l1xx.h
  • ADC_JSQR_JSQ1_3 : stm32l1xx.h
  • ADC_JSQR_JSQ1_4 : stm32l1xx.h
  • ADC_JSQR_JSQ2 : stm32l1xx.h
  • ADC_JSQR_JSQ2_0 : stm32l1xx.h
  • ADC_JSQR_JSQ2_1 : stm32l1xx.h
  • ADC_JSQR_JSQ2_2 : stm32l1xx.h
  • ADC_JSQR_JSQ2_3 : stm32l1xx.h
  • ADC_JSQR_JSQ2_4 : stm32l1xx.h
  • ADC_JSQR_JSQ3 : stm32l1xx.h
  • ADC_JSQR_JSQ3_0 : stm32l1xx.h
  • ADC_JSQR_JSQ3_1 : stm32l1xx.h
  • ADC_JSQR_JSQ3_2 : stm32l1xx.h
  • ADC_JSQR_JSQ3_3 : stm32l1xx.h
  • ADC_JSQR_JSQ3_4 : stm32l1xx.h
  • ADC_JSQR_JSQ4 : stm32l1xx.h
  • ADC_JSQR_JSQ4_0 : stm32l1xx.h
  • ADC_JSQR_JSQ4_1 : stm32l1xx.h
  • ADC_JSQR_JSQ4_2 : stm32l1xx.h
  • ADC_JSQR_JSQ4_3 : stm32l1xx.h
  • ADC_JSQR_JSQ4_4 : stm32l1xx.h
  • ADC_LTR_LT : stm32l1xx.h
  • ADC_PowerDown_Delay : stm32l1xx_adc.h
  • ADC_PowerDown_Idle : stm32l1xx_adc.h
  • ADC_PowerDown_Idle_Delay : stm32l1xx_adc.h
  • ADC_PowerDownCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Prescaler_Div1 : stm32l1xx_adc.h
  • ADC_Prescaler_Div2 : stm32l1xx_adc.h
  • ADC_Prescaler_Div4 : stm32l1xx_adc.h
  • ADC_RegularChannelConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Resolution_10b : stm32l1xx_adc.h
  • ADC_Resolution_12b : stm32l1xx_adc.h
  • ADC_Resolution_6b : stm32l1xx_adc.h
  • ADC_Resolution_8b : stm32l1xx_adc.h
  • ADC_SampleTime_16Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_192Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_24Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_384Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_48Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_4Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_96Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_9Cycles : stm32l1xx_adc.h
  • ADC_SetInjectedOffset() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_SMPR1_SMP20 : stm32l1xx.h
  • ADC_SMPR1_SMP20_0 : stm32l1xx.h
  • ADC_SMPR1_SMP20_1 : stm32l1xx.h
  • ADC_SMPR1_SMP20_2 : stm32l1xx.h
  • ADC_SMPR1_SMP21 : stm32l1xx.h
  • ADC_SMPR1_SMP21_0 : stm32l1xx.h
  • ADC_SMPR1_SMP21_1 : stm32l1xx.h
  • ADC_SMPR1_SMP21_2 : stm32l1xx.h
  • ADC_SMPR1_SMP22 : stm32l1xx.h
  • ADC_SMPR1_SMP22_0 : stm32l1xx.h
  • ADC_SMPR1_SMP22_1 : stm32l1xx.h
  • ADC_SMPR1_SMP22_2 : stm32l1xx.h
  • ADC_SMPR1_SMP23 : stm32l1xx.h
  • ADC_SMPR1_SMP23_0 : stm32l1xx.h
  • ADC_SMPR1_SMP23_1 : stm32l1xx.h
  • ADC_SMPR1_SMP23_2 : stm32l1xx.h
  • ADC_SMPR1_SMP24 : stm32l1xx.h
  • ADC_SMPR1_SMP24_0 : stm32l1xx.h
  • ADC_SMPR1_SMP24_1 : stm32l1xx.h
  • ADC_SMPR1_SMP24_2 : stm32l1xx.h
  • ADC_SMPR1_SMP25 : stm32l1xx.h
  • ADC_SMPR1_SMP25_0 : stm32l1xx.h
  • ADC_SMPR1_SMP25_1 : stm32l1xx.h
  • ADC_SMPR1_SMP25_2 : stm32l1xx.h
  • ADC_SMPR1_SMP26 : stm32l1xx.h
  • ADC_SMPR1_SMP26_0 : stm32l1xx.h
  • ADC_SMPR1_SMP26_1 : stm32l1xx.h
  • ADC_SMPR1_SMP26_2 : stm32l1xx.h
  • ADC_SMPR1_SMP27 : stm32l1xx.h
  • ADC_SMPR1_SMP27_0 : stm32l1xx.h
  • ADC_SMPR1_SMP27_1 : stm32l1xx.h
  • ADC_SMPR1_SMP27_2 : stm32l1xx.h
  • ADC_SMPR1_SMP28 : stm32l1xx.h
  • ADC_SMPR1_SMP28_0 : stm32l1xx.h
  • ADC_SMPR1_SMP28_1 : stm32l1xx.h
  • ADC_SMPR1_SMP28_2 : stm32l1xx.h
  • ADC_SMPR1_SMP29 : stm32l1xx.h
  • ADC_SMPR1_SMP29_0 : stm32l1xx.h
  • ADC_SMPR1_SMP29_1 : stm32l1xx.h
  • ADC_SMPR1_SMP29_2 : stm32l1xx.h
  • ADC_SMPR2_SMP10 : stm32l1xx.h
  • ADC_SMPR2_SMP10_0 : stm32l1xx.h
  • ADC_SMPR2_SMP10_1 : stm32l1xx.h
  • ADC_SMPR2_SMP10_2 : stm32l1xx.h
  • ADC_SMPR2_SMP11 : stm32l1xx.h
  • ADC_SMPR2_SMP11_0 : stm32l1xx.h
  • ADC_SMPR2_SMP11_1 : stm32l1xx.h
  • ADC_SMPR2_SMP11_2 : stm32l1xx.h
  • ADC_SMPR2_SMP12 : stm32l1xx.h
  • ADC_SMPR2_SMP12_0 : stm32l1xx.h
  • ADC_SMPR2_SMP12_1 : stm32l1xx.h
  • ADC_SMPR2_SMP12_2 : stm32l1xx.h
  • ADC_SMPR2_SMP13 : stm32l1xx.h
  • ADC_SMPR2_SMP13_0 : stm32l1xx.h
  • ADC_SMPR2_SMP13_1 : stm32l1xx.h
  • ADC_SMPR2_SMP13_2 : stm32l1xx.h
  • ADC_SMPR2_SMP14 : stm32l1xx.h
  • ADC_SMPR2_SMP14_0 : stm32l1xx.h
  • ADC_SMPR2_SMP14_1 : stm32l1xx.h
  • ADC_SMPR2_SMP14_2 : stm32l1xx.h
  • ADC_SMPR2_SMP15 : stm32l1xx.h
  • ADC_SMPR2_SMP15_0 : stm32l1xx.h
  • ADC_SMPR2_SMP15_1 : stm32l1xx.h
  • ADC_SMPR2_SMP15_2 : stm32l1xx.h
  • ADC_SMPR2_SMP16 : stm32l1xx.h
  • ADC_SMPR2_SMP16_0 : stm32l1xx.h
  • ADC_SMPR2_SMP16_1 : stm32l1xx.h
  • ADC_SMPR2_SMP16_2 : stm32l1xx.h
  • ADC_SMPR2_SMP17 : stm32l1xx.h
  • ADC_SMPR2_SMP17_0 : stm32l1xx.h
  • ADC_SMPR2_SMP17_1 : stm32l1xx.h
  • ADC_SMPR2_SMP17_2 : stm32l1xx.h
  • ADC_SMPR2_SMP18 : stm32l1xx.h
  • ADC_SMPR2_SMP18_0 : stm32l1xx.h
  • ADC_SMPR2_SMP18_1 : stm32l1xx.h
  • ADC_SMPR2_SMP18_2 : stm32l1xx.h
  • ADC_SMPR2_SMP19 : stm32l1xx.h
  • ADC_SMPR2_SMP19_0 : stm32l1xx.h
  • ADC_SMPR2_SMP19_1 : stm32l1xx.h
  • ADC_SMPR2_SMP19_2 : stm32l1xx.h
  • ADC_SMPR3_SMP0 : stm32l1xx.h
  • ADC_SMPR3_SMP0_0 : stm32l1xx.h
  • ADC_SMPR3_SMP0_1 : stm32l1xx.h
  • ADC_SMPR3_SMP0_2 : stm32l1xx.h
  • ADC_SMPR3_SMP1 : stm32l1xx.h
  • ADC_SMPR3_SMP1_0 : stm32l1xx.h
  • ADC_SMPR3_SMP1_1 : stm32l1xx.h
  • ADC_SMPR3_SMP1_2 : stm32l1xx.h
  • ADC_SMPR3_SMP2 : stm32l1xx.h
  • ADC_SMPR3_SMP2_0 : stm32l1xx.h
  • ADC_SMPR3_SMP2_1 : stm32l1xx.h
  • ADC_SMPR3_SMP2_2 : stm32l1xx.h
  • ADC_SMPR3_SMP3 : stm32l1xx.h
  • ADC_SMPR3_SMP30 : stm32l1xx.h
  • ADC_SMPR3_SMP30_0 : stm32l1xx.h
  • ADC_SMPR3_SMP30_1 : stm32l1xx.h
  • ADC_SMPR3_SMP30_2 : stm32l1xx.h
  • ADC_SMPR3_SMP31 : stm32l1xx.h
  • ADC_SMPR3_SMP31_0 : stm32l1xx.h
  • ADC_SMPR3_SMP31_1 : stm32l1xx.h
  • ADC_SMPR3_SMP31_2 : stm32l1xx.h
  • ADC_SMPR3_SMP3_0 : stm32l1xx.h
  • ADC_SMPR3_SMP3_1 : stm32l1xx.h
  • ADC_SMPR3_SMP3_2 : stm32l1xx.h
  • ADC_SMPR3_SMP4 : stm32l1xx.h
  • ADC_SMPR3_SMP4_0 : stm32l1xx.h
  • ADC_SMPR3_SMP4_1 : stm32l1xx.h
  • ADC_SMPR3_SMP4_2 : stm32l1xx.h
  • ADC_SMPR3_SMP5 : stm32l1xx.h
  • ADC_SMPR3_SMP5_0 : stm32l1xx.h
  • ADC_SMPR3_SMP5_1 : stm32l1xx.h
  • ADC_SMPR3_SMP5_2 : stm32l1xx.h
  • ADC_SMPR3_SMP6 : stm32l1xx.h
  • ADC_SMPR3_SMP6_0 : stm32l1xx.h
  • ADC_SMPR3_SMP6_1 : stm32l1xx.h
  • ADC_SMPR3_SMP6_2 : stm32l1xx.h
  • ADC_SMPR3_SMP7 : stm32l1xx.h
  • ADC_SMPR3_SMP7_0 : stm32l1xx.h
  • ADC_SMPR3_SMP7_1 : stm32l1xx.h
  • ADC_SMPR3_SMP7_2 : stm32l1xx.h
  • ADC_SMPR3_SMP8 : stm32l1xx.h
  • ADC_SMPR3_SMP8_0 : stm32l1xx.h
  • ADC_SMPR3_SMP8_1 : stm32l1xx.h
  • ADC_SMPR3_SMP8_2 : stm32l1xx.h
  • ADC_SMPR3_SMP9 : stm32l1xx.h
  • ADC_SMPR3_SMP9_0 : stm32l1xx.h
  • ADC_SMPR3_SMP9_1 : stm32l1xx.h
  • ADC_SMPR3_SMP9_2 : stm32l1xx.h
  • ADC_SoftwareStartConv() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_SoftwareStartInjectedConv() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_SQR1_L : stm32l1xx.h
  • ADC_SQR1_L_0 : stm32l1xx.h
  • ADC_SQR1_L_1 : stm32l1xx.h
  • ADC_SQR1_L_2 : stm32l1xx.h
  • ADC_SQR1_L_3 : stm32l1xx.h
  • ADC_SQR1_SQ25 : stm32l1xx.h
  • ADC_SQR1_SQ25_0 : stm32l1xx.h
  • ADC_SQR1_SQ25_1 : stm32l1xx.h
  • ADC_SQR1_SQ25_2 : stm32l1xx.h
  • ADC_SQR1_SQ25_3 : stm32l1xx.h
  • ADC_SQR1_SQ25_4 : stm32l1xx.h
  • ADC_SQR1_SQ26 : stm32l1xx.h
  • ADC_SQR1_SQ26_0 : stm32l1xx.h
  • ADC_SQR1_SQ26_1 : stm32l1xx.h
  • ADC_SQR1_SQ26_2 : stm32l1xx.h
  • ADC_SQR1_SQ26_3 : stm32l1xx.h
  • ADC_SQR1_SQ26_4 : stm32l1xx.h
  • ADC_SQR1_SQ27 : stm32l1xx.h
  • ADC_SQR1_SQ27_0 : stm32l1xx.h
  • ADC_SQR1_SQ27_1 : stm32l1xx.h
  • ADC_SQR1_SQ27_2 : stm32l1xx.h
  • ADC_SQR1_SQ27_3 : stm32l1xx.h
  • ADC_SQR1_SQ27_4 : stm32l1xx.h
  • ADC_SQR1_SQ28 : stm32l1xx.h
  • ADC_SQR1_SQ28_0 : stm32l1xx.h
  • ADC_SQR1_SQ28_1 : stm32l1xx.h
  • ADC_SQR1_SQ28_2 : stm32l1xx.h
  • ADC_SQR1_SQ28_3 : stm32l1xx.h
  • ADC_SQR1_SQ28_4 : stm32l1xx.h
  • ADC_SQR2_SQ19 : stm32l1xx.h
  • ADC_SQR2_SQ19_0 : stm32l1xx.h
  • ADC_SQR2_SQ19_1 : stm32l1xx.h
  • ADC_SQR2_SQ19_2 : stm32l1xx.h
  • ADC_SQR2_SQ19_3 : stm32l1xx.h
  • ADC_SQR2_SQ19_4 : stm32l1xx.h
  • ADC_SQR2_SQ20 : stm32l1xx.h
  • ADC_SQR2_SQ20_0 : stm32l1xx.h
  • ADC_SQR2_SQ20_1 : stm32l1xx.h
  • ADC_SQR2_SQ20_2 : stm32l1xx.h
  • ADC_SQR2_SQ20_3 : stm32l1xx.h
  • ADC_SQR2_SQ20_4 : stm32l1xx.h
  • ADC_SQR2_SQ21 : stm32l1xx.h
  • ADC_SQR2_SQ21_0 : stm32l1xx.h
  • ADC_SQR2_SQ21_1 : stm32l1xx.h
  • ADC_SQR2_SQ21_2 : stm32l1xx.h
  • ADC_SQR2_SQ21_3 : stm32l1xx.h
  • ADC_SQR2_SQ21_4 : stm32l1xx.h
  • ADC_SQR2_SQ22 : stm32l1xx.h
  • ADC_SQR2_SQ22_0 : stm32l1xx.h
  • ADC_SQR2_SQ22_1 : stm32l1xx.h
  • ADC_SQR2_SQ22_2 : stm32l1xx.h
  • ADC_SQR2_SQ22_3 : stm32l1xx.h
  • ADC_SQR2_SQ22_4 : stm32l1xx.h
  • ADC_SQR2_SQ23 : stm32l1xx.h
  • ADC_SQR2_SQ23_0 : stm32l1xx.h
  • ADC_SQR2_SQ23_1 : stm32l1xx.h
  • ADC_SQR2_SQ23_2 : stm32l1xx.h
  • ADC_SQR2_SQ23_3 : stm32l1xx.h
  • ADC_SQR2_SQ23_4 : stm32l1xx.h
  • ADC_SQR2_SQ24 : stm32l1xx.h
  • ADC_SQR2_SQ24_0 : stm32l1xx.h
  • ADC_SQR2_SQ24_1 : stm32l1xx.h
  • ADC_SQR2_SQ24_2 : stm32l1xx.h
  • ADC_SQR2_SQ24_3 : stm32l1xx.h
  • ADC_SQR2_SQ24_4 : stm32l1xx.h
  • ADC_SQR3_SQ13 : stm32l1xx.h
  • ADC_SQR3_SQ13_0 : stm32l1xx.h
  • ADC_SQR3_SQ13_1 : stm32l1xx.h
  • ADC_SQR3_SQ13_2 : stm32l1xx.h
  • ADC_SQR3_SQ13_3 : stm32l1xx.h
  • ADC_SQR3_SQ13_4 : stm32l1xx.h
  • ADC_SQR3_SQ14 : stm32l1xx.h
  • ADC_SQR3_SQ14_0 : stm32l1xx.h
  • ADC_SQR3_SQ14_1 : stm32l1xx.h
  • ADC_SQR3_SQ14_2 : stm32l1xx.h
  • ADC_SQR3_SQ14_3 : stm32l1xx.h
  • ADC_SQR3_SQ14_4 : stm32l1xx.h
  • ADC_SQR3_SQ15 : stm32l1xx.h
  • ADC_SQR3_SQ15_0 : stm32l1xx.h
  • ADC_SQR3_SQ15_1 : stm32l1xx.h
  • ADC_SQR3_SQ15_2 : stm32l1xx.h
  • ADC_SQR3_SQ15_3 : stm32l1xx.h
  • ADC_SQR3_SQ15_4 : stm32l1xx.h
  • ADC_SQR3_SQ16 : stm32l1xx.h
  • ADC_SQR3_SQ16_0 : stm32l1xx.h
  • ADC_SQR3_SQ16_1 : stm32l1xx.h
  • ADC_SQR3_SQ16_2 : stm32l1xx.h
  • ADC_SQR3_SQ16_3 : stm32l1xx.h
  • ADC_SQR3_SQ16_4 : stm32l1xx.h
  • ADC_SQR3_SQ17 : stm32l1xx.h
  • ADC_SQR3_SQ17_0 : stm32l1xx.h
  • ADC_SQR3_SQ17_1 : stm32l1xx.h
  • ADC_SQR3_SQ17_2 : stm32l1xx.h
  • ADC_SQR3_SQ17_3 : stm32l1xx.h
  • ADC_SQR3_SQ17_4 : stm32l1xx.h
  • ADC_SQR3_SQ18 : stm32l1xx.h
  • ADC_SQR3_SQ18_0 : stm32l1xx.h
  • ADC_SQR3_SQ18_1 : stm32l1xx.h
  • ADC_SQR3_SQ18_2 : stm32l1xx.h
  • ADC_SQR3_SQ18_3 : stm32l1xx.h
  • ADC_SQR3_SQ18_4 : stm32l1xx.h
  • ADC_SQR4_SQ10 : stm32l1xx.h
  • ADC_SQR4_SQ10_0 : stm32l1xx.h
  • ADC_SQR4_SQ10_1 : stm32l1xx.h
  • ADC_SQR4_SQ10_2 : stm32l1xx.h
  • ADC_SQR4_SQ10_3 : stm32l1xx.h
  • ADC_SQR4_SQ10_4 : stm32l1xx.h
  • ADC_SQR4_SQ11 : stm32l1xx.h
  • ADC_SQR4_SQ11_0 : stm32l1xx.h
  • ADC_SQR4_SQ11_1 : stm32l1xx.h
  • ADC_SQR4_SQ11_2 : stm32l1xx.h
  • ADC_SQR4_SQ11_3 : stm32l1xx.h
  • ADC_SQR4_SQ11_4 : stm32l1xx.h
  • ADC_SQR4_SQ12 : stm32l1xx.h
  • ADC_SQR4_SQ12_0 : stm32l1xx.h
  • ADC_SQR4_SQ12_1 : stm32l1xx.h
  • ADC_SQR4_SQ12_2 : stm32l1xx.h
  • ADC_SQR4_SQ12_3 : stm32l1xx.h
  • ADC_SQR4_SQ12_4 : stm32l1xx.h
  • ADC_SQR4_SQ7 : stm32l1xx.h
  • ADC_SQR4_SQ7_0 : stm32l1xx.h
  • ADC_SQR4_SQ7_1 : stm32l1xx.h
  • ADC_SQR4_SQ7_2 : stm32l1xx.h
  • ADC_SQR4_SQ7_3 : stm32l1xx.h
  • ADC_SQR4_SQ7_4 : stm32l1xx.h
  • ADC_SQR4_SQ8 : stm32l1xx.h
  • ADC_SQR4_SQ8_0 : stm32l1xx.h
  • ADC_SQR4_SQ8_1 : stm32l1xx.h
  • ADC_SQR4_SQ8_2 : stm32l1xx.h
  • ADC_SQR4_SQ8_3 : stm32l1xx.h
  • ADC_SQR4_SQ8_4 : stm32l1xx.h
  • ADC_SQR4_SQ9 : stm32l1xx.h
  • ADC_SQR4_SQ9_0 : stm32l1xx.h
  • ADC_SQR4_SQ9_1 : stm32l1xx.h
  • ADC_SQR4_SQ9_2 : stm32l1xx.h
  • ADC_SQR4_SQ9_3 : stm32l1xx.h
  • ADC_SQR4_SQ9_4 : stm32l1xx.h
  • ADC_SQR5_SQ1 : stm32l1xx.h
  • ADC_SQR5_SQ1_0 : stm32l1xx.h
  • ADC_SQR5_SQ1_1 : stm32l1xx.h
  • ADC_SQR5_SQ1_2 : stm32l1xx.h
  • ADC_SQR5_SQ1_3 : stm32l1xx.h
  • ADC_SQR5_SQ1_4 : stm32l1xx.h
  • ADC_SQR5_SQ2 : stm32l1xx.h
  • ADC_SQR5_SQ2_0 : stm32l1xx.h
  • ADC_SQR5_SQ2_1 : stm32l1xx.h
  • ADC_SQR5_SQ2_2 : stm32l1xx.h
  • ADC_SQR5_SQ2_3 : stm32l1xx.h
  • ADC_SQR5_SQ2_4 : stm32l1xx.h
  • ADC_SQR5_SQ3 : stm32l1xx.h
  • ADC_SQR5_SQ3_0 : stm32l1xx.h
  • ADC_SQR5_SQ3_1 : stm32l1xx.h
  • ADC_SQR5_SQ3_2 : stm32l1xx.h
  • ADC_SQR5_SQ3_3 : stm32l1xx.h
  • ADC_SQR5_SQ3_4 : stm32l1xx.h
  • ADC_SQR5_SQ4 : stm32l1xx.h
  • ADC_SQR5_SQ4_0 : stm32l1xx.h
  • ADC_SQR5_SQ4_1 : stm32l1xx.h
  • ADC_SQR5_SQ4_2 : stm32l1xx.h
  • ADC_SQR5_SQ4_3 : stm32l1xx.h
  • ADC_SQR5_SQ4_4 : stm32l1xx.h
  • ADC_SQR5_SQ5 : stm32l1xx.h
  • ADC_SQR5_SQ5_0 : stm32l1xx.h
  • ADC_SQR5_SQ5_1 : stm32l1xx.h
  • ADC_SQR5_SQ5_2 : stm32l1xx.h
  • ADC_SQR5_SQ5_3 : stm32l1xx.h
  • ADC_SQR5_SQ5_4 : stm32l1xx.h
  • ADC_SQR5_SQ6 : stm32l1xx.h
  • ADC_SQR5_SQ6_0 : stm32l1xx.h
  • ADC_SQR5_SQ6_1 : stm32l1xx.h
  • ADC_SQR5_SQ6_2 : stm32l1xx.h
  • ADC_SQR5_SQ6_3 : stm32l1xx.h
  • ADC_SQR5_SQ6_4 : stm32l1xx.h
  • ADC_SR_ADONS : stm32l1xx.h
  • ADC_SR_AWD : stm32l1xx.h
  • ADC_SR_EOC : stm32l1xx.h
  • ADC_SR_JCNR : stm32l1xx.h
  • ADC_SR_JEOC : stm32l1xx.h
  • ADC_SR_JSTRT : stm32l1xx.h
  • ADC_SR_OVR : stm32l1xx.h
  • ADC_SR_RCNR : stm32l1xx.h
  • ADC_SR_STRT : stm32l1xx.h
  • ADC_StructInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_TempSensorVrefintCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • AES : stm32l1xx.h
  • AES_BASE : stm32l1xx.h
  • AES_CBC_Decrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_CBC_Encrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_CC_TIMEOUT : stm32l1xx_aes_util.c
  • AES_Chaining_CBC : stm32l1xx_aes.h
  • AES_Chaining_CTR : stm32l1xx_aes.h
  • AES_Chaining_ECB : stm32l1xx_aes.h
  • AES_ClearFlag() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ClearITPendingBit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_Cmd() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_CR_CCFC : stm32l1xx.h
  • AES_CR_CCIE : stm32l1xx.h
  • AES_CR_CHMOD : stm32l1xx.h
  • AES_CR_CHMOD_0 : stm32l1xx.h
  • AES_CR_CHMOD_1 : stm32l1xx.h
  • AES_CR_DATATYPE : stm32l1xx.h
  • AES_CR_DATATYPE_0 : stm32l1xx.h
  • AES_CR_DATATYPE_1 : stm32l1xx.h
  • AES_CR_DMAINEN : stm32l1xx.h
  • AES_CR_DMAOUTEN : stm32l1xx.h
  • AES_CR_EN : stm32l1xx.h
  • AES_CR_ERRC : stm32l1xx.h
  • AES_CR_ERRIE : stm32l1xx.h
  • AES_CR_MODE : stm32l1xx.h
  • AES_CR_MODE_0 : stm32l1xx.h
  • AES_CR_MODE_1 : stm32l1xx.h
  • AES_CTR_Decrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_CTR_Encrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_DataType_16b : stm32l1xx_aes.h
  • AES_DataType_1b : stm32l1xx_aes.h
  • AES_DataType_32b : stm32l1xx_aes.h
  • AES_DataType_8b : stm32l1xx_aes.h
  • AES_DeInit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_DINR : stm32l1xx.h
  • AES_DMAConfig() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_DMATransfer_In : stm32l1xx_aes.h
  • AES_DMATransfer_InOut : stm32l1xx_aes.h
  • AES_DMATransfer_Out : stm32l1xx_aes.h
  • AES_DOUTR : stm32l1xx.h
  • AES_ECB_Decrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_ECB_Encrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_FLAG_CCF : stm32l1xx_aes.h
  • AES_FLAG_RDERR : stm32l1xx_aes.h
  • AES_FLAG_WRERR : stm32l1xx_aes.h
  • AES_GetFlagStatus() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_GetITStatus() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_Init() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_IRQn : stm32l1xx.h
  • AES_IT_CC : stm32l1xx_aes.h
  • AES_IT_ERR : stm32l1xx_aes.h
  • AES_ITConfig() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_IVInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_IVR0 : stm32l1xx.h
  • AES_IVR1 : stm32l1xx.h
  • AES_IVR2 : stm32l1xx.h
  • AES_IVR3 : stm32l1xx.h
  • AES_IVStructInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_KeyInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_KEYR0 : stm32l1xx.h
  • AES_KEYR1 : stm32l1xx.h
  • AES_KEYR2 : stm32l1xx.h
  • AES_KEYR3 : stm32l1xx.h
  • AES_KeyStructInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_Operation_Decryp : stm32l1xx_aes.h
  • AES_Operation_Encryp : stm32l1xx_aes.h
  • AES_Operation_KeyDeriv : stm32l1xx_aes.h
  • AES_Operation_KeyDerivAndDecryp : stm32l1xx_aes.h
  • AES_ReadIV() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ReadKey() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ReadSubData() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_SR_CCF : stm32l1xx.h
  • AES_SR_RDERR : stm32l1xx.h
  • AES_SR_WRERR : stm32l1xx.h
  • AES_StructInit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_WriteSubData() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AHBPERIPH_BASE : stm32l1xx.h
  • AHBPrescTable : system_stm32l1xx.c
  • AIRCR_VECTKEY_MASK : misc.c
  • APB1PERIPH_BASE : stm32l1xx.h
  • APB2PERIPH_BASE : stm32l1xx.h
  • APBAHBPrescTable : stm32l1xx_rcc.c
  • ATACMD_BitNumber : stm32l1xx_sdio.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BIT_MASK : stm32l1xx_wwdg.c
  • Bit_RESET : stm32l1xx_gpio.h
  • Bit_SET : stm32l1xx_gpio.h
  • BitAction : stm32l1xx_gpio.h
  • BLINK_MASK : stm32l1xx_lcd.c
  • BusFault_IRQn : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • l
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CCER_CCE_SET : stm32l1xx_tim.c
  • CCMR_OFFSET : stm32l1xx_tim.c
  • CCR_CLEAR_MASK : stm32l1xx_dma.c
  • CFGR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CFGR_BYTE4_ADDRESS : stm32l1xx_rcc.c
  • CFR_EWI_BB : stm32l1xx_wwdg.c
  • CFR_OFFSET : stm32l1xx_wwdg.c
  • CFR_W_MASK : stm32l1xx_wwdg.c
  • CFR_WDGTB_MASK : stm32l1xx_wwdg.c
  • CIR_BYTE2_ADDRESS : stm32l1xx_rcc.c
  • CIR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CLEAR_BIT : stm32l1xx.h
  • CLEAR_REG : stm32l1xx.h
  • CLKCR_CLEAR_MASK : stm32l1xx_sdio.c
  • CLKCR_CLKEN_BB : stm32l1xx_sdio.c
  • CLKCR_OFFSET : stm32l1xx_sdio.c
  • CLKEN_BitNumber : stm32l1xx_sdio.c
  • CMD_ATACMD_BB : stm32l1xx_sdio.c
  • CMD_CLEAR_MASK : stm32l1xx_sdio.c
  • CMD_ENCMDCOMPL_BB : stm32l1xx_sdio.c
  • CMD_NIEN_BB : stm32l1xx_sdio.c
  • CMD_OFFSET : stm32l1xx_sdio.c
  • CMD_SDIOSUSPEND_BB : stm32l1xx_sdio.c
  • COMP : stm32l1xx.h
  • COMP_ACQ_IRQn : stm32l1xx.h
  • COMP_BASE : stm32l1xx.h
  • COMP_Cmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_CSR_10KPD : stm32l1xx.h
  • COMP_CSR_10KPU : stm32l1xx.h
  • COMP_CSR_400KPD : stm32l1xx.h
  • COMP_CSR_400KPU : stm32l1xx.h
  • COMP_CSR_CAIE : stm32l1xx.h
  • COMP_CSR_CAIF : stm32l1xx.h
  • COMP_CSR_CMP1EN : stm32l1xx.h
  • COMP_CSR_CMP1OUT : stm32l1xx.h
  • COMP_CSR_CMP2OUT : stm32l1xx.h
  • COMP_CSR_FCH3 : stm32l1xx.h
  • COMP_CSR_FCH8 : stm32l1xx.h
  • COMP_CSR_INSEL : stm32l1xx.h
  • COMP_CSR_INSEL_0 : stm32l1xx.h
  • COMP_CSR_INSEL_1 : stm32l1xx.h
  • COMP_CSR_INSEL_2 : stm32l1xx.h
  • COMP_CSR_OUTSEL : stm32l1xx.h
  • COMP_CSR_OUTSEL_0 : stm32l1xx.h
  • COMP_CSR_OUTSEL_1 : stm32l1xx.h
  • COMP_CSR_OUTSEL_2 : stm32l1xx.h
  • COMP_CSR_RCH13 : stm32l1xx.h
  • COMP_CSR_SPEED : stm32l1xx.h
  • COMP_CSR_SW1 : stm32l1xx.h
  • COMP_CSR_TSUSP : stm32l1xx.h
  • COMP_CSR_VREFOUTEN : stm32l1xx.h
  • COMP_CSR_WNDWE : stm32l1xx.h
  • COMP_DeInit() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_GetOutputLevel() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_Init() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_InvertingInput_1_2VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_1_4VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_3_4VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_DAC1 : stm32l1xx_comp.h
  • COMP_InvertingInput_DAC2 : stm32l1xx_comp.h
  • COMP_InvertingInput_IO : stm32l1xx_comp.h
  • COMP_InvertingInput_None : stm32l1xx_comp.h
  • COMP_InvertingInput_VREFINT : stm32l1xx_comp.h
  • COMP_IRQn : stm32l1xx.h
  • COMP_OutputLevel_High : stm32l1xx_comp.h
  • COMP_OutputLevel_Low : stm32l1xx_comp.h
  • COMP_OutputSelect_None : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM10IC1 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM2IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM2OCREFCLR : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM3IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM3OCREFCLR : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM4IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM4OCREFCLR : stm32l1xx_comp.h
  • COMP_Selection_COMP1 : stm32l1xx_comp.h
  • COMP_Selection_COMP2 : stm32l1xx_comp.h
  • COMP_Speed_Fast : stm32l1xx_comp.h
  • COMP_Speed_Slow : stm32l1xx_comp.h
  • COMP_SW1SwitchConfig() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_VrefintOutputCmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_WindowCmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • CONTRAST_MASK : stm32l1xx_lcd.c
  • CR1_AWDCH_RESET : stm32l1xx_adc.c
  • CR1_AWDMODE_RESET : stm32l1xx_adc.c
  • CR1_CLEAR_MASK : stm32l1xx_adc.c , stm32l1xx_i2c.c , stm32l1xx_spi.c , stm32l1xx_usart.c
  • CR1_DISCNUM_RESET : stm32l1xx_adc.c
  • CR2_CLEAR_MASK : stm32l1xx_adc.c
  • CR2_CLOCK_CLEAR_MASK : stm32l1xx_usart.c
  • CR2_DELS_RESET : stm32l1xx_adc.c
  • CR2_JEXTEN_RESET : stm32l1xx_adc.c
  • CR2_JEXTSEL_RESET : stm32l1xx_adc.c
  • CR3_CLEAR_MASK : stm32l1xx_usart.c
  • CR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CR_CLEAR_MASK : stm32l1xx_aes.c , stm32l1xx_dac.c , stm32l1xx_adc.c
  • CR_CSSON_BB : stm32l1xx_rcc.c
  • CR_DBP_BB : stm32l1xx_pwr.c
  • CR_DS_MASK : stm32l1xx_pwr.c
  • CR_FWU_BB : stm32l1xx_pwr.c
  • CR_HSION_BB : stm32l1xx_rcc.c
  • CR_LCDEN_BB : stm32l1xx_lcd.c
  • CR_MASK : stm32l1xx_lcd.c
  • CR_MSION_BB : stm32l1xx_rcc.c
  • CR_MUX_SEG_BB : stm32l1xx_lcd.c
  • CR_OFFSET : stm32l1xx_rcc.c , stm32l1xx_pwr.c , stm32l1xx_lcd.c
  • CR_PLLON_BB : stm32l1xx_rcc.c
  • CR_PLS_MASK : stm32l1xx_pwr.c
  • CR_PVDE_BB : stm32l1xx_pwr.c
  • CR_ULP_BB : stm32l1xx_pwr.c
  • CR_VOS_MASK : stm32l1xx_pwr.c
  • CRC : stm32l1xx.h
  • CRC_BASE : stm32l1xx.h
  • CRC_CalcBlockCRC() : stm32l1xx_crc.c , stm32l1xx_crc.h
  • CRC_CalcCRC() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_CR_RESET : stm32l1xx.h
  • CRC_DR_DR : stm32l1xx.h
  • CRC_GetCRC() : stm32l1xx_crc.c , stm32l1xx_crc.h
  • CRC_GetIDRegister() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_IDR_IDR : stm32l1xx.h
  • CRC_ResetDR() : stm32l1xx_crc.c , stm32l1xx_crc.h
  • CRC_SetIDRegister() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CSR_BYTE2_ADDRESS : stm32l1xx_rcc.c
  • CSR_EWUP_BB : stm32l1xx_pwr.c
  • CSR_LSECSSON_BB : stm32l1xx_rcc.c
  • CSR_LSION_BB : stm32l1xx_rcc.c
  • CSR_OFFSET : stm32l1xx_pwr.c , stm32l1xx_rcc.c
  • CSR_RTCEN_BB : stm32l1xx_rcc.c
  • CSR_RTCRST_BB : stm32l1xx_rcc.c
  • CSSON_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • d
  • e
  • f
  • g
  • h
  • i
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  • k
  • l
  • m
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC : stm32l1xx.h
  • DAC_Align_12b_L : stm32l1xx_dac.h
  • DAC_Align_12b_R : stm32l1xx_dac.h
  • DAC_Align_8b_R : stm32l1xx_dac.h
  • DAC_BASE : stm32l1xx.h
  • DAC_Channel_1 : stm32l1xx_dac.h
  • DAC_Channel_2 : stm32l1xx_dac.h
  • DAC_ClearFlag() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_ClearITPendingBit() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_Cmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_CR_BOFF1 : stm32l1xx.h
  • DAC_CR_BOFF2 : stm32l1xx.h
  • DAC_CR_DMAEN1 : stm32l1xx.h
  • DAC_CR_DMAEN2 : stm32l1xx.h
  • DAC_CR_DMAUDRIE1 : stm32l1xx.h
  • DAC_CR_DMAUDRIE2 : stm32l1xx.h
  • DAC_CR_EN1 : stm32l1xx.h
  • DAC_CR_EN2 : stm32l1xx.h
  • DAC_CR_MAMP1 : stm32l1xx.h
  • DAC_CR_MAMP1_0 : stm32l1xx.h
  • DAC_CR_MAMP1_1 : stm32l1xx.h
  • DAC_CR_MAMP1_2 : stm32l1xx.h
  • DAC_CR_MAMP1_3 : stm32l1xx.h
  • DAC_CR_MAMP2 : stm32l1xx.h
  • DAC_CR_MAMP2_0 : stm32l1xx.h
  • DAC_CR_MAMP2_1 : stm32l1xx.h
  • DAC_CR_MAMP2_2 : stm32l1xx.h
  • DAC_CR_MAMP2_3 : stm32l1xx.h
  • DAC_CR_TEN1 : stm32l1xx.h
  • DAC_CR_TEN2 : stm32l1xx.h
  • DAC_CR_TSEL1 : stm32l1xx.h
  • DAC_CR_TSEL1_0 : stm32l1xx.h
  • DAC_CR_TSEL1_1 : stm32l1xx.h
  • DAC_CR_TSEL1_2 : stm32l1xx.h
  • DAC_CR_TSEL2 : stm32l1xx.h
  • DAC_CR_TSEL2_0 : stm32l1xx.h
  • DAC_CR_TSEL2_1 : stm32l1xx.h
  • DAC_CR_TSEL2_2 : stm32l1xx.h
  • DAC_CR_WAVE1 : stm32l1xx.h
  • DAC_CR_WAVE1_0 : stm32l1xx.h
  • DAC_CR_WAVE1_1 : stm32l1xx.h
  • DAC_CR_WAVE2 : stm32l1xx.h
  • DAC_CR_WAVE2_0 : stm32l1xx.h
  • DAC_CR_WAVE2_1 : stm32l1xx.h
  • DAC_DeInit() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_DHR12L1_DACC1DHR : stm32l1xx.h
  • DAC_DHR12L2_DACC2DHR : stm32l1xx.h
  • DAC_DHR12LD_DACC1DHR : stm32l1xx.h
  • DAC_DHR12LD_DACC2DHR : stm32l1xx.h
  • DAC_DHR12R1_DACC1DHR : stm32l1xx.h
  • DAC_DHR12R2_DACC2DHR : stm32l1xx.h
  • DAC_DHR12RD_DACC1DHR : stm32l1xx.h
  • DAC_DHR12RD_DACC2DHR : stm32l1xx.h
  • DAC_DHR8R1_DACC1DHR : stm32l1xx.h
  • DAC_DHR8R2_DACC2DHR : stm32l1xx.h
  • DAC_DHR8RD_DACC1DHR : stm32l1xx.h
  • DAC_DHR8RD_DACC2DHR : stm32l1xx.h
  • DAC_DMACmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_DOR1_DACC1DOR : stm32l1xx.h
  • DAC_DOR2_DACC2DOR : stm32l1xx.h
  • DAC_DualSoftwareTriggerCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_FLAG_DMAUDR : stm32l1xx_dac.h
  • DAC_GetDataOutputValue() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_GetFlagStatus() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_GetITStatus() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_Init() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_IRQn : stm32l1xx.h
  • DAC_IT_DMAUDR : stm32l1xx_dac.h
  • DAC_ITConfig() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_LFSRUnmask_Bit0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits10_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits11_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits1_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits2_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits3_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits4_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits5_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits6_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits7_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits8_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits9_0 : stm32l1xx_dac.h
  • DAC_OutputBuffer_Disable : stm32l1xx_dac.h
  • DAC_OutputBuffer_Enable : stm32l1xx_dac.h
  • DAC_SetChannel1Data() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SetChannel2Data() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SetDualChannelData() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SoftwareTriggerCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SR_DMAUDR1 : stm32l1xx.h
  • DAC_SR_DMAUDR2 : stm32l1xx.h
  • DAC_StructInit() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SWTRIGR_SWTRIG1 : stm32l1xx.h
  • DAC_SWTRIGR_SWTRIG2 : stm32l1xx.h
  • DAC_TriangleAmplitude_1 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_1023 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_127 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_15 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_2047 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_255 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_3 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_31 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_4095 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_511 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_63 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_7 : stm32l1xx_dac.h
  • DAC_Trigger_Ext_IT9 : stm32l1xx_dac.h
  • DAC_Trigger_None : stm32l1xx_dac.h
  • DAC_Trigger_Software : stm32l1xx_dac.h
  • DAC_Trigger_T2_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T4_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T6_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T7_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T9_TRGO : stm32l1xx_dac.h
  • DAC_Wave_Noise : stm32l1xx_dac.h
  • DAC_Wave_Triangle : stm32l1xx_dac.h
  • DAC_WaveGeneration_Noise : stm32l1xx_dac.h
  • DAC_WaveGeneration_None : stm32l1xx_dac.h
  • DAC_WaveGeneration_Triangle : stm32l1xx_dac.h
  • DAC_WaveGenerationCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DATA_EEPROM_EraseByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_EraseDoubleWord() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • DATA_EEPROM_EraseHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_EraseWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FixedTimeProgramCmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_Lock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramDoubleWord() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • DATA_EEPROM_ProgramHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_Unlock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DBGMCU : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_IWDG_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_RTC_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM2_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM3_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM4_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM5_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM6_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM7_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_WWDG_STOP : stm32l1xx.h
  • DBGMCU_APB1PeriphConfig() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_APB2_FZ_DBG_TIM10_STOP : stm32l1xx.h
  • DBGMCU_APB2_FZ_DBG_TIM11_STOP : stm32l1xx.h
  • DBGMCU_APB2_FZ_DBG_TIM9_STOP : stm32l1xx.h
  • DBGMCU_APB2PeriphConfig() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_BASE : stm32l1xx.h
  • DBGMCU_Config() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_CR_DBG_SLEEP : stm32l1xx.h
  • DBGMCU_CR_DBG_STANDBY : stm32l1xx.h
  • DBGMCU_CR_DBG_STOP : stm32l1xx.h
  • DBGMCU_CR_TRACE_IOEN : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE_0 : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE_1 : stm32l1xx.h
  • DBGMCU_GetDEVID() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_GetREVID() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_I2C1_SMBUS_TIMEOUT : stm32l1xx_dbgmcu.h
  • DBGMCU_I2C2_SMBUS_TIMEOUT : stm32l1xx_dbgmcu.h
  • DBGMCU_IDCODE_DEV_ID : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_0 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_1 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_10 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_11 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_12 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_13 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_14 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_15 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_2 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_3 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_4 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_5 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_6 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_7 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_8 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_9 : stm32l1xx.h
  • DBGMCU_IWDG_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_RTC_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_SLEEP : stm32l1xx_dbgmcu.h
  • DBGMCU_STANDBY : stm32l1xx_dbgmcu.h
  • DBGMCU_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM10_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM11_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM2_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM3_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM4_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM5_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM6_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM7_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM9_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_WWDG_STOP : stm32l1xx_dbgmcu.h
  • DBP_BitNumber : stm32l1xx_pwr.c
  • DCTRL_CLEAR_MASK : stm32l1xx_sdio.c
  • DCTRL_DMAEN_BB : stm32l1xx_sdio.c
  • DCTRL_OFFSET : stm32l1xx_sdio.c
  • DCTRL_RWMOD_BB : stm32l1xx_sdio.c
  • DCTRL_RWSTART_BB : stm32l1xx_sdio.c
  • DCTRL_RWSTOP_BB : stm32l1xx_sdio.c
  • DCTRL_SDIOEN_BB : stm32l1xx_sdio.c
  • DEAD_MASK : stm32l1xx_lcd.c
  • DebugMonitor_IRQn : stm32l1xx.h
  • DHR12R1_OFFSET : stm32l1xx_dac.c
  • DHR12R2_OFFSET : stm32l1xx_dac.c
  • DHR12RD_OFFSET : stm32l1xx_dac.c
  • DISABLE : stm32l1xx.h
  • DMA1 : stm32l1xx.h
  • DMA1_BASE : stm32l1xx.h
  • DMA1_Channel1 : stm32l1xx.h
  • DMA1_Channel1_BASE : stm32l1xx.h
  • DMA1_Channel1_IRQn : stm32l1xx.h
  • DMA1_CHANNEL1_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel2 : stm32l1xx.h
  • DMA1_Channel2_BASE : stm32l1xx.h
  • DMA1_Channel2_IRQn : stm32l1xx.h
  • DMA1_CHANNEL2_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel3 : stm32l1xx.h
  • DMA1_Channel3_BASE : stm32l1xx.h
  • DMA1_Channel3_IRQn : stm32l1xx.h
  • DMA1_CHANNEL3_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel4 : stm32l1xx.h
  • DMA1_Channel4_BASE : stm32l1xx.h
  • DMA1_Channel4_IRQn : stm32l1xx.h
  • DMA1_CHANNEL4_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel5 : stm32l1xx.h
  • DMA1_Channel5_BASE : stm32l1xx.h
  • DMA1_Channel5_IRQn : stm32l1xx.h
  • DMA1_CHANNEL5_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel6 : stm32l1xx.h
  • DMA1_Channel6_BASE : stm32l1xx.h
  • DMA1_Channel6_IRQn : stm32l1xx.h
  • DMA1_CHANNEL6_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel7 : stm32l1xx.h
  • DMA1_Channel7_BASE : stm32l1xx.h
  • DMA1_Channel7_IRQn : stm32l1xx.h
  • DMA1_CHANNEL7_IT_MASK : stm32l1xx_dma.c
  • DMA1_FLAG_GL1 : stm32l1xx_dma.h
  • DMA1_FLAG_GL2 : stm32l1xx_dma.h
  • DMA1_FLAG_GL3 : stm32l1xx_dma.h
  • DMA1_FLAG_GL4 : stm32l1xx_dma.h
  • DMA1_FLAG_GL5 : stm32l1xx_dma.h
  • DMA1_FLAG_GL6 : stm32l1xx_dma.h
  • DMA1_FLAG_GL7 : stm32l1xx_dma.h
  • DMA1_FLAG_HT1 : stm32l1xx_dma.h
  • DMA1_FLAG_HT2 : stm32l1xx_dma.h
  • DMA1_FLAG_HT3 : stm32l1xx_dma.h
  • DMA1_FLAG_HT4 : stm32l1xx_dma.h
  • DMA1_FLAG_HT5 : stm32l1xx_dma.h
  • DMA1_FLAG_HT6 : stm32l1xx_dma.h
  • DMA1_FLAG_HT7 : stm32l1xx_dma.h
  • DMA1_FLAG_TC1 : stm32l1xx_dma.h
  • DMA1_FLAG_TC2 : stm32l1xx_dma.h
  • DMA1_FLAG_TC3 : stm32l1xx_dma.h
  • DMA1_FLAG_TC4 : stm32l1xx_dma.h
  • DMA1_FLAG_TC5 : stm32l1xx_dma.h
  • DMA1_FLAG_TC6 : stm32l1xx_dma.h
  • DMA1_FLAG_TC7 : stm32l1xx_dma.h
  • DMA1_FLAG_TE1 : stm32l1xx_dma.h
  • DMA1_FLAG_TE2 : stm32l1xx_dma.h
  • DMA1_FLAG_TE3 : stm32l1xx_dma.h
  • DMA1_FLAG_TE4 : stm32l1xx_dma.h
  • DMA1_FLAG_TE5 : stm32l1xx_dma.h
  • DMA1_FLAG_TE6 : stm32l1xx_dma.h
  • DMA1_FLAG_TE7 : stm32l1xx_dma.h
  • DMA1_IT_GL1 : stm32l1xx_dma.h
  • DMA1_IT_GL2 : stm32l1xx_dma.h
  • DMA1_IT_GL3 : stm32l1xx_dma.h
  • DMA1_IT_GL4 : stm32l1xx_dma.h
  • DMA1_IT_GL5 : stm32l1xx_dma.h
  • DMA1_IT_GL6 : stm32l1xx_dma.h
  • DMA1_IT_GL7 : stm32l1xx_dma.h
  • DMA1_IT_HT1 : stm32l1xx_dma.h
  • DMA1_IT_HT2 : stm32l1xx_dma.h
  • DMA1_IT_HT3 : stm32l1xx_dma.h
  • DMA1_IT_HT4 : stm32l1xx_dma.h
  • DMA1_IT_HT5 : stm32l1xx_dma.h
  • DMA1_IT_HT6 : stm32l1xx_dma.h
  • DMA1_IT_HT7 : stm32l1xx_dma.h
  • DMA1_IT_TC1 : stm32l1xx_dma.h
  • DMA1_IT_TC2 : stm32l1xx_dma.h
  • DMA1_IT_TC3 : stm32l1xx_dma.h
  • DMA1_IT_TC4 : stm32l1xx_dma.h
  • DMA1_IT_TC5 : stm32l1xx_dma.h
  • DMA1_IT_TC6 : stm32l1xx_dma.h
  • DMA1_IT_TC7 : stm32l1xx_dma.h
  • DMA1_IT_TE1 : stm32l1xx_dma.h
  • DMA1_IT_TE2 : stm32l1xx_dma.h
  • DMA1_IT_TE3 : stm32l1xx_dma.h
  • DMA1_IT_TE4 : stm32l1xx_dma.h
  • DMA1_IT_TE5 : stm32l1xx_dma.h
  • DMA1_IT_TE6 : stm32l1xx_dma.h
  • DMA1_IT_TE7 : stm32l1xx_dma.h
  • DMA2 : stm32l1xx.h
  • DMA2_BASE : stm32l1xx.h
  • DMA2_Channel1 : stm32l1xx.h
  • DMA2_Channel1_BASE : stm32l1xx.h
  • DMA2_Channel1_IRQn : stm32l1xx.h
  • DMA2_CHANNEL1_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel2 : stm32l1xx.h
  • DMA2_Channel2_BASE : stm32l1xx.h
  • DMA2_Channel2_IRQn : stm32l1xx.h
  • DMA2_CHANNEL2_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel3 : stm32l1xx.h
  • DMA2_Channel3_BASE : stm32l1xx.h
  • DMA2_Channel3_IRQn : stm32l1xx.h
  • DMA2_CHANNEL3_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel4 : stm32l1xx.h
  • DMA2_Channel4_BASE : stm32l1xx.h
  • DMA2_Channel4_IRQn : stm32l1xx.h
  • DMA2_CHANNEL4_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel5 : stm32l1xx.h
  • DMA2_Channel5_BASE : stm32l1xx.h
  • DMA2_Channel5_IRQn : stm32l1xx.h
  • DMA2_CHANNEL5_IT_MASK : stm32l1xx_dma.c
  • DMA2_FLAG_GL1 : stm32l1xx_dma.h
  • DMA2_FLAG_GL2 : stm32l1xx_dma.h
  • DMA2_FLAG_GL3 : stm32l1xx_dma.h
  • DMA2_FLAG_GL4 : stm32l1xx_dma.h
  • DMA2_FLAG_GL5 : stm32l1xx_dma.h
  • DMA2_FLAG_HT1 : stm32l1xx_dma.h
  • DMA2_FLAG_HT2 : stm32l1xx_dma.h
  • DMA2_FLAG_HT3 : stm32l1xx_dma.h
  • DMA2_FLAG_HT4 : stm32l1xx_dma.h
  • DMA2_FLAG_HT5 : stm32l1xx_dma.h
  • DMA2_FLAG_TC1 : stm32l1xx_dma.h
  • DMA2_FLAG_TC2 : stm32l1xx_dma.h
  • DMA2_FLAG_TC3 : stm32l1xx_dma.h
  • DMA2_FLAG_TC4 : stm32l1xx_dma.h
  • DMA2_FLAG_TC5 : stm32l1xx_dma.h
  • DMA2_FLAG_TE1 : stm32l1xx_dma.h
  • DMA2_FLAG_TE2 : stm32l1xx_dma.h
  • DMA2_FLAG_TE3 : stm32l1xx_dma.h
  • DMA2_FLAG_TE4 : stm32l1xx_dma.h
  • DMA2_FLAG_TE5 : stm32l1xx_dma.h
  • DMA2_IT_GL1 : stm32l1xx_dma.h
  • DMA2_IT_GL2 : stm32l1xx_dma.h
  • DMA2_IT_GL3 : stm32l1xx_dma.h
  • DMA2_IT_GL4 : stm32l1xx_dma.h
  • DMA2_IT_GL5 : stm32l1xx_dma.h
  • DMA2_IT_HT1 : stm32l1xx_dma.h
  • DMA2_IT_HT2 : stm32l1xx_dma.h
  • DMA2_IT_HT3 : stm32l1xx_dma.h
  • DMA2_IT_HT4 : stm32l1xx_dma.h
  • DMA2_IT_HT5 : stm32l1xx_dma.h
  • DMA2_IT_TC1 : stm32l1xx_dma.h
  • DMA2_IT_TC2 : stm32l1xx_dma.h
  • DMA2_IT_TC3 : stm32l1xx_dma.h
  • DMA2_IT_TC4 : stm32l1xx_dma.h
  • DMA2_IT_TC5 : stm32l1xx_dma.h
  • DMA2_IT_TE1 : stm32l1xx_dma.h
  • DMA2_IT_TE2 : stm32l1xx_dma.h
  • DMA2_IT_TE3 : stm32l1xx_dma.h
  • DMA2_IT_TE4 : stm32l1xx_dma.h
  • DMA2_IT_TE5 : stm32l1xx_dma.h
  • DMA_CCR1_CIRC : stm32l1xx.h
  • DMA_CCR1_DIR : stm32l1xx.h
  • DMA_CCR1_EN : stm32l1xx.h
  • DMA_CCR1_HTIE : stm32l1xx.h
  • DMA_CCR1_MEM2MEM : stm32l1xx.h
  • DMA_CCR1_MINC : stm32l1xx.h
  • DMA_CCR1_MSIZE : stm32l1xx.h
  • DMA_CCR1_MSIZE_0 : stm32l1xx.h
  • DMA_CCR1_MSIZE_1 : stm32l1xx.h
  • DMA_CCR1_PINC : stm32l1xx.h
  • DMA_CCR1_PL : stm32l1xx.h
  • DMA_CCR1_PL_0 : stm32l1xx.h
  • DMA_CCR1_PL_1 : stm32l1xx.h
  • DMA_CCR1_PSIZE : stm32l1xx.h
  • DMA_CCR1_PSIZE_0 : stm32l1xx.h
  • DMA_CCR1_PSIZE_1 : stm32l1xx.h
  • DMA_CCR1_TCIE : stm32l1xx.h
  • DMA_CCR1_TEIE : stm32l1xx.h
  • DMA_CCR2_CIRC : stm32l1xx.h
  • DMA_CCR2_DIR : stm32l1xx.h
  • DMA_CCR2_EN : stm32l1xx.h
  • DMA_CCR2_HTIE : stm32l1xx.h
  • DMA_CCR2_MEM2MEM : stm32l1xx.h
  • DMA_CCR2_MINC : stm32l1xx.h
  • DMA_CCR2_MSIZE : stm32l1xx.h
  • DMA_CCR2_MSIZE_0 : stm32l1xx.h
  • DMA_CCR2_MSIZE_1 : stm32l1xx.h
  • DMA_CCR2_PINC : stm32l1xx.h
  • DMA_CCR2_PL : stm32l1xx.h
  • DMA_CCR2_PL_0 : stm32l1xx.h
  • DMA_CCR2_PL_1 : stm32l1xx.h
  • DMA_CCR2_PSIZE : stm32l1xx.h
  • DMA_CCR2_PSIZE_0 : stm32l1xx.h
  • DMA_CCR2_PSIZE_1 : stm32l1xx.h
  • DMA_CCR2_TCIE : stm32l1xx.h
  • DMA_CCR2_TEIE : stm32l1xx.h
  • DMA_CCR3_CIRC : stm32l1xx.h
  • DMA_CCR3_DIR : stm32l1xx.h
  • DMA_CCR3_EN : stm32l1xx.h
  • DMA_CCR3_HTIE : stm32l1xx.h
  • DMA_CCR3_MEM2MEM : stm32l1xx.h
  • DMA_CCR3_MINC : stm32l1xx.h
  • DMA_CCR3_MSIZE : stm32l1xx.h
  • DMA_CCR3_MSIZE_0 : stm32l1xx.h
  • DMA_CCR3_MSIZE_1 : stm32l1xx.h
  • DMA_CCR3_PINC : stm32l1xx.h
  • DMA_CCR3_PL : stm32l1xx.h
  • DMA_CCR3_PL_0 : stm32l1xx.h
  • DMA_CCR3_PL_1 : stm32l1xx.h
  • DMA_CCR3_PSIZE : stm32l1xx.h
  • DMA_CCR3_PSIZE_0 : stm32l1xx.h
  • DMA_CCR3_PSIZE_1 : stm32l1xx.h
  • DMA_CCR3_TCIE : stm32l1xx.h
  • DMA_CCR3_TEIE : stm32l1xx.h
  • DMA_CCR4_CIRC : stm32l1xx.h
  • DMA_CCR4_DIR : stm32l1xx.h
  • DMA_CCR4_EN : stm32l1xx.h
  • DMA_CCR4_HTIE : stm32l1xx.h
  • DMA_CCR4_MEM2MEM : stm32l1xx.h
  • DMA_CCR4_MINC : stm32l1xx.h
  • DMA_CCR4_MSIZE : stm32l1xx.h
  • DMA_CCR4_MSIZE_0 : stm32l1xx.h
  • DMA_CCR4_MSIZE_1 : stm32l1xx.h
  • DMA_CCR4_PINC : stm32l1xx.h
  • DMA_CCR4_PL : stm32l1xx.h
  • DMA_CCR4_PL_0 : stm32l1xx.h
  • DMA_CCR4_PL_1 : stm32l1xx.h
  • DMA_CCR4_PSIZE : stm32l1xx.h
  • DMA_CCR4_PSIZE_0 : stm32l1xx.h
  • DMA_CCR4_PSIZE_1 : stm32l1xx.h
  • DMA_CCR4_TCIE : stm32l1xx.h
  • DMA_CCR4_TEIE : stm32l1xx.h
  • DMA_CCR5_CIRC : stm32l1xx.h
  • DMA_CCR5_DIR : stm32l1xx.h
  • DMA_CCR5_EN : stm32l1xx.h
  • DMA_CCR5_HTIE : stm32l1xx.h
  • DMA_CCR5_MEM2MEM : stm32l1xx.h
  • DMA_CCR5_MINC : stm32l1xx.h
  • DMA_CCR5_MSIZE : stm32l1xx.h
  • DMA_CCR5_MSIZE_0 : stm32l1xx.h
  • DMA_CCR5_MSIZE_1 : stm32l1xx.h
  • DMA_CCR5_PINC : stm32l1xx.h
  • DMA_CCR5_PL : stm32l1xx.h
  • DMA_CCR5_PL_0 : stm32l1xx.h
  • DMA_CCR5_PL_1 : stm32l1xx.h
  • DMA_CCR5_PSIZE : stm32l1xx.h
  • DMA_CCR5_PSIZE_0 : stm32l1xx.h
  • DMA_CCR5_PSIZE_1 : stm32l1xx.h
  • DMA_CCR5_TCIE : stm32l1xx.h
  • DMA_CCR5_TEIE : stm32l1xx.h
  • DMA_CCR6_CIRC : stm32l1xx.h
  • DMA_CCR6_DIR : stm32l1xx.h
  • DMA_CCR6_EN : stm32l1xx.h
  • DMA_CCR6_HTIE : stm32l1xx.h
  • DMA_CCR6_MEM2MEM : stm32l1xx.h
  • DMA_CCR6_MINC : stm32l1xx.h
  • DMA_CCR6_MSIZE : stm32l1xx.h
  • DMA_CCR6_MSIZE_0 : stm32l1xx.h
  • DMA_CCR6_MSIZE_1 : stm32l1xx.h
  • DMA_CCR6_PINC : stm32l1xx.h
  • DMA_CCR6_PL : stm32l1xx.h
  • DMA_CCR6_PL_0 : stm32l1xx.h
  • DMA_CCR6_PL_1 : stm32l1xx.h
  • DMA_CCR6_PSIZE : stm32l1xx.h
  • DMA_CCR6_PSIZE_0 : stm32l1xx.h
  • DMA_CCR6_PSIZE_1 : stm32l1xx.h
  • DMA_CCR6_TCIE : stm32l1xx.h
  • DMA_CCR6_TEIE : stm32l1xx.h
  • DMA_CCR7_CIRC : stm32l1xx.h
  • DMA_CCR7_DIR : stm32l1xx.h
  • DMA_CCR7_EN : stm32l1xx.h
  • DMA_CCR7_HTIE : stm32l1xx.h
  • DMA_CCR7_MEM2MEM : stm32l1xx.h
  • DMA_CCR7_MINC : stm32l1xx.h
  • DMA_CCR7_MSIZE : stm32l1xx.h
  • DMA_CCR7_MSIZE_0 : stm32l1xx.h
  • DMA_CCR7_MSIZE_1 : stm32l1xx.h
  • DMA_CCR7_PINC : stm32l1xx.h
  • DMA_CCR7_PL : stm32l1xx.h
  • DMA_CCR7_PL_0 : stm32l1xx.h
  • DMA_CCR7_PL_1 : stm32l1xx.h
  • DMA_CCR7_PSIZE : stm32l1xx.h
  • DMA_CCR7_PSIZE_0 : stm32l1xx.h
  • DMA_CCR7_PSIZE_1 : stm32l1xx.h
  • DMA_CCR7_TCIE : stm32l1xx.h
  • DMA_CCR7_TEIE : stm32l1xx.h
  • DMA_ClearFlag() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_ClearITPendingBit() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_CMAR1_MA : stm32l1xx.h
  • DMA_CMAR2_MA : stm32l1xx.h
  • DMA_CMAR3_MA : stm32l1xx.h
  • DMA_CMAR4_MA : stm32l1xx.h
  • DMA_CMAR5_MA : stm32l1xx.h
  • DMA_CMAR6_MA : stm32l1xx.h
  • DMA_CMAR7_MA : stm32l1xx.h
  • DMA_Cmd() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_CNDTR1_NDT : stm32l1xx.h
  • DMA_CNDTR2_NDT : stm32l1xx.h
  • DMA_CNDTR3_NDT : stm32l1xx.h
  • DMA_CNDTR4_NDT : stm32l1xx.h
  • DMA_CNDTR5_NDT : stm32l1xx.h
  • DMA_CNDTR6_NDT : stm32l1xx.h
  • DMA_CNDTR7_NDT : stm32l1xx.h
  • DMA_CPAR1_PA : stm32l1xx.h
  • DMA_CPAR2_PA : stm32l1xx.h
  • DMA_CPAR3_PA : stm32l1xx.h
  • DMA_CPAR4_PA : stm32l1xx.h
  • DMA_CPAR5_PA : stm32l1xx.h
  • DMA_CPAR6_PA : stm32l1xx.h
  • DMA_CPAR7_PA : stm32l1xx.h
  • DMA_DeInit() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_DIR_PeripheralDST : stm32l1xx_dma.h
  • DMA_DIR_PeripheralSRC : stm32l1xx_dma.h
  • DMA_GetCurrDataCounter() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_GetFlagStatus() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_GetITStatus() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_IFCR_CGIF1 : stm32l1xx.h
  • DMA_IFCR_CGIF2 : stm32l1xx.h
  • DMA_IFCR_CGIF3 : stm32l1xx.h
  • DMA_IFCR_CGIF4 : stm32l1xx.h
  • DMA_IFCR_CGIF5 : stm32l1xx.h
  • DMA_IFCR_CGIF6 : stm32l1xx.h
  • DMA_IFCR_CGIF7 : stm32l1xx.h
  • DMA_IFCR_CHTIF1 : stm32l1xx.h
  • DMA_IFCR_CHTIF2 : stm32l1xx.h
  • DMA_IFCR_CHTIF3 : stm32l1xx.h
  • DMA_IFCR_CHTIF4 : stm32l1xx.h
  • DMA_IFCR_CHTIF5 : stm32l1xx.h
  • DMA_IFCR_CHTIF6 : stm32l1xx.h
  • DMA_IFCR_CHTIF7 : stm32l1xx.h
  • DMA_IFCR_CTCIF1 : stm32l1xx.h
  • DMA_IFCR_CTCIF2 : stm32l1xx.h
  • DMA_IFCR_CTCIF3 : stm32l1xx.h
  • DMA_IFCR_CTCIF4 : stm32l1xx.h
  • DMA_IFCR_CTCIF5 : stm32l1xx.h
  • DMA_IFCR_CTCIF6 : stm32l1xx.h
  • DMA_IFCR_CTCIF7 : stm32l1xx.h
  • DMA_IFCR_CTEIF1 : stm32l1xx.h
  • DMA_IFCR_CTEIF2 : stm32l1xx.h
  • DMA_IFCR_CTEIF3 : stm32l1xx.h
  • DMA_IFCR_CTEIF4 : stm32l1xx.h
  • DMA_IFCR_CTEIF5 : stm32l1xx.h
  • DMA_IFCR_CTEIF6 : stm32l1xx.h
  • DMA_IFCR_CTEIF7 : stm32l1xx.h
  • DMA_Init() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_ISR_GIF1 : stm32l1xx.h
  • DMA_ISR_GIF2 : stm32l1xx.h
  • DMA_ISR_GIF3 : stm32l1xx.h
  • DMA_ISR_GIF4 : stm32l1xx.h
  • DMA_ISR_GIF5 : stm32l1xx.h
  • DMA_ISR_GIF6 : stm32l1xx.h
  • DMA_ISR_GIF7 : stm32l1xx.h
  • DMA_ISR_HTIF1 : stm32l1xx.h
  • DMA_ISR_HTIF2 : stm32l1xx.h
  • DMA_ISR_HTIF3 : stm32l1xx.h
  • DMA_ISR_HTIF4 : stm32l1xx.h
  • DMA_ISR_HTIF5 : stm32l1xx.h
  • DMA_ISR_HTIF6 : stm32l1xx.h
  • DMA_ISR_HTIF7 : stm32l1xx.h
  • DMA_ISR_TCIF1 : stm32l1xx.h
  • DMA_ISR_TCIF2 : stm32l1xx.h
  • DMA_ISR_TCIF3 : stm32l1xx.h
  • DMA_ISR_TCIF4 : stm32l1xx.h
  • DMA_ISR_TCIF5 : stm32l1xx.h
  • DMA_ISR_TCIF6 : stm32l1xx.h
  • DMA_ISR_TCIF7 : stm32l1xx.h
  • DMA_ISR_TEIF1 : stm32l1xx.h
  • DMA_ISR_TEIF2 : stm32l1xx.h
  • DMA_ISR_TEIF3 : stm32l1xx.h
  • DMA_ISR_TEIF4 : stm32l1xx.h
  • DMA_ISR_TEIF5 : stm32l1xx.h
  • DMA_ISR_TEIF6 : stm32l1xx.h
  • DMA_ISR_TEIF7 : stm32l1xx.h
  • DMA_IT_HT : stm32l1xx_dma.h
  • DMA_IT_TC : stm32l1xx_dma.h
  • DMA_IT_TE : stm32l1xx_dma.h
  • DMA_ITConfig() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_M2M_Disable : stm32l1xx_dma.h
  • DMA_M2M_Enable : stm32l1xx_dma.h
  • DMA_MemoryDataSize_Byte : stm32l1xx_dma.h
  • DMA_MemoryDataSize_HalfWord : stm32l1xx_dma.h
  • DMA_MemoryDataSize_Word : stm32l1xx_dma.h
  • DMA_MemoryInc_Disable : stm32l1xx_dma.h
  • DMA_MemoryInc_Enable : stm32l1xx_dma.h
  • DMA_Mode_Circular : stm32l1xx_dma.h
  • DMA_Mode_Normal : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_Byte : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_HalfWord : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_Word : stm32l1xx_dma.h
  • DMA_PeripheralInc_Disable : stm32l1xx_dma.h
  • DMA_PeripheralInc_Enable : stm32l1xx_dma.h
  • DMA_Priority_High : stm32l1xx_dma.h
  • DMA_Priority_Low : stm32l1xx_dma.h
  • DMA_Priority_Medium : stm32l1xx_dma.h
  • DMA_Priority_VeryHigh : stm32l1xx_dma.h
  • DMA_SetCurrDataCounter() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_StructInit() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMAEN_BitNumber : stm32l1xx_sdio.c
  • DOR_OFFSET : stm32l1xx_dac.c
  • DUAL_SWTRIG_RESET : stm32l1xx_dac.c
  • DUAL_SWTRIG_SET : stm32l1xx_dac.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ENABLE : stm32l1xx.h
  • ENCMDCOMPL_BitNumber : stm32l1xx_sdio.c
  • ERROR : stm32l1xx.h
  • ErrorStatus : stm32l1xx.h
  • EWI_BitNumber : stm32l1xx_wwdg.c
  • EWUP_BitNumber : stm32l1xx_pwr.c
  • EXTI : stm32l1xx.h
  • EXTI0_IRQn : stm32l1xx.h
  • EXTI15_10_IRQn : stm32l1xx.h
  • EXTI1_IRQn : stm32l1xx.h
  • EXTI2_IRQn : stm32l1xx.h
  • EXTI3_IRQn : stm32l1xx.h
  • EXTI4_IRQn : stm32l1xx.h
  • EXTI9_5_IRQn : stm32l1xx.h
  • EXTI_BASE : stm32l1xx.h
  • EXTI_ClearFlag() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_ClearITPendingBit() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_DeInit() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_EMR_MR0 : stm32l1xx.h
  • EXTI_EMR_MR1 : stm32l1xx.h
  • EXTI_EMR_MR10 : stm32l1xx.h
  • EXTI_EMR_MR11 : stm32l1xx.h
  • EXTI_EMR_MR12 : stm32l1xx.h
  • EXTI_EMR_MR13 : stm32l1xx.h
  • EXTI_EMR_MR14 : stm32l1xx.h
  • EXTI_EMR_MR15 : stm32l1xx.h
  • EXTI_EMR_MR16 : stm32l1xx.h
  • EXTI_EMR_MR17 : stm32l1xx.h
  • EXTI_EMR_MR18 : stm32l1xx.h
  • EXTI_EMR_MR19 : stm32l1xx.h
  • EXTI_EMR_MR2 : stm32l1xx.h
  • EXTI_EMR_MR20 : stm32l1xx.h
  • EXTI_EMR_MR21 : stm32l1xx.h
  • EXTI_EMR_MR22 : stm32l1xx.h
  • EXTI_EMR_MR23 : stm32l1xx.h
  • EXTI_EMR_MR3 : stm32l1xx.h
  • EXTI_EMR_MR4 : stm32l1xx.h
  • EXTI_EMR_MR5 : stm32l1xx.h
  • EXTI_EMR_MR6 : stm32l1xx.h
  • EXTI_EMR_MR7 : stm32l1xx.h
  • EXTI_EMR_MR8 : stm32l1xx.h
  • EXTI_EMR_MR9 : stm32l1xx.h
  • EXTI_FTSR_TR0 : stm32l1xx.h
  • EXTI_FTSR_TR1 : stm32l1xx.h
  • EXTI_FTSR_TR10 : stm32l1xx.h
  • EXTI_FTSR_TR11 : stm32l1xx.h
  • EXTI_FTSR_TR12 : stm32l1xx.h
  • EXTI_FTSR_TR13 : stm32l1xx.h
  • EXTI_FTSR_TR14 : stm32l1xx.h
  • EXTI_FTSR_TR15 : stm32l1xx.h
  • EXTI_FTSR_TR16 : stm32l1xx.h
  • EXTI_FTSR_TR17 : stm32l1xx.h
  • EXTI_FTSR_TR18 : stm32l1xx.h
  • EXTI_FTSR_TR19 : stm32l1xx.h
  • EXTI_FTSR_TR2 : stm32l1xx.h
  • EXTI_FTSR_TR20 : stm32l1xx.h
  • EXTI_FTSR_TR21 : stm32l1xx.h
  • EXTI_FTSR_TR22 : stm32l1xx.h
  • EXTI_FTSR_TR23 : stm32l1xx.h
  • EXTI_FTSR_TR3 : stm32l1xx.h
  • EXTI_FTSR_TR4 : stm32l1xx.h
  • EXTI_FTSR_TR5 : stm32l1xx.h
  • EXTI_FTSR_TR6 : stm32l1xx.h
  • EXTI_FTSR_TR7 : stm32l1xx.h
  • EXTI_FTSR_TR8 : stm32l1xx.h
  • EXTI_FTSR_TR9 : stm32l1xx.h
  • EXTI_GenerateSWInterrupt() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_GetFlagStatus() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_GetITStatus() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_IMR_MR0 : stm32l1xx.h
  • EXTI_IMR_MR1 : stm32l1xx.h
  • EXTI_IMR_MR10 : stm32l1xx.h
  • EXTI_IMR_MR11 : stm32l1xx.h
  • EXTI_IMR_MR12 : stm32l1xx.h
  • EXTI_IMR_MR13 : stm32l1xx.h
  • EXTI_IMR_MR14 : stm32l1xx.h
  • EXTI_IMR_MR15 : stm32l1xx.h
  • EXTI_IMR_MR16 : stm32l1xx.h
  • EXTI_IMR_MR17 : stm32l1xx.h
  • EXTI_IMR_MR18 : stm32l1xx.h
  • EXTI_IMR_MR19 : stm32l1xx.h
  • EXTI_IMR_MR2 : stm32l1xx.h
  • EXTI_IMR_MR20 : stm32l1xx.h
  • EXTI_IMR_MR21 : stm32l1xx.h
  • EXTI_IMR_MR22 : stm32l1xx.h
  • EXTI_IMR_MR23 : stm32l1xx.h
  • EXTI_IMR_MR3 : stm32l1xx.h
  • EXTI_IMR_MR4 : stm32l1xx.h
  • EXTI_IMR_MR5 : stm32l1xx.h
  • EXTI_IMR_MR6 : stm32l1xx.h
  • EXTI_IMR_MR7 : stm32l1xx.h
  • EXTI_IMR_MR8 : stm32l1xx.h
  • EXTI_IMR_MR9 : stm32l1xx.h
  • EXTI_Init() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_Line0 : stm32l1xx_exti.h
  • EXTI_Line1 : stm32l1xx_exti.h
  • EXTI_Line10 : stm32l1xx_exti.h
  • EXTI_Line11 : stm32l1xx_exti.h
  • EXTI_Line12 : stm32l1xx_exti.h
  • EXTI_Line13 : stm32l1xx_exti.h
  • EXTI_Line14 : stm32l1xx_exti.h
  • EXTI_Line15 : stm32l1xx_exti.h
  • EXTI_Line16 : stm32l1xx_exti.h
  • EXTI_Line17 : stm32l1xx_exti.h
  • EXTI_Line18 : stm32l1xx_exti.h
  • EXTI_Line19 : stm32l1xx_exti.h
  • EXTI_Line2 : stm32l1xx_exti.h
  • EXTI_Line20 : stm32l1xx_exti.h
  • EXTI_Line21 : stm32l1xx_exti.h
  • EXTI_Line22 : stm32l1xx_exti.h
  • EXTI_Line23 : stm32l1xx_exti.h
  • EXTI_Line3 : stm32l1xx_exti.h
  • EXTI_Line4 : stm32l1xx_exti.h
  • EXTI_Line5 : stm32l1xx_exti.h
  • EXTI_Line6 : stm32l1xx_exti.h
  • EXTI_Line7 : stm32l1xx_exti.h
  • EXTI_Line8 : stm32l1xx_exti.h
  • EXTI_Line9 : stm32l1xx_exti.h
  • EXTI_LINENONE : stm32l1xx_exti.c
  • EXTI_Mode_Event : stm32l1xx_exti.h
  • EXTI_Mode_Interrupt : stm32l1xx_exti.h
  • EXTI_PinSource0 : stm32l1xx_syscfg.h
  • EXTI_PinSource1 : stm32l1xx_syscfg.h
  • EXTI_PinSource10 : stm32l1xx_syscfg.h
  • EXTI_PinSource11 : stm32l1xx_syscfg.h
  • EXTI_PinSource12 : stm32l1xx_syscfg.h
  • EXTI_PinSource13 : stm32l1xx_syscfg.h
  • EXTI_PinSource14 : stm32l1xx_syscfg.h
  • EXTI_PinSource15 : stm32l1xx_syscfg.h
  • EXTI_PinSource2 : stm32l1xx_syscfg.h
  • EXTI_PinSource3 : stm32l1xx_syscfg.h
  • EXTI_PinSource4 : stm32l1xx_syscfg.h
  • EXTI_PinSource5 : stm32l1xx_syscfg.h
  • EXTI_PinSource6 : stm32l1xx_syscfg.h
  • EXTI_PinSource7 : stm32l1xx_syscfg.h
  • EXTI_PinSource8 : stm32l1xx_syscfg.h
  • EXTI_PinSource9 : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOA : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOB : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOC : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOD : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOE : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOF : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOG : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOH : stm32l1xx_syscfg.h
  • EXTI_PR_PR0 : stm32l1xx.h
  • EXTI_PR_PR1 : stm32l1xx.h
  • EXTI_PR_PR10 : stm32l1xx.h
  • EXTI_PR_PR11 : stm32l1xx.h
  • EXTI_PR_PR12 : stm32l1xx.h
  • EXTI_PR_PR13 : stm32l1xx.h
  • EXTI_PR_PR14 : stm32l1xx.h
  • EXTI_PR_PR15 : stm32l1xx.h
  • EXTI_PR_PR16 : stm32l1xx.h
  • EXTI_PR_PR17 : stm32l1xx.h
  • EXTI_PR_PR18 : stm32l1xx.h
  • EXTI_PR_PR19 : stm32l1xx.h
  • EXTI_PR_PR2 : stm32l1xx.h
  • EXTI_PR_PR20 : stm32l1xx.h
  • EXTI_PR_PR21 : stm32l1xx.h
  • EXTI_PR_PR22 : stm32l1xx.h
  • EXTI_PR_PR23 : stm32l1xx.h
  • EXTI_PR_PR3 : stm32l1xx.h
  • EXTI_PR_PR4 : stm32l1xx.h
  • EXTI_PR_PR5 : stm32l1xx.h
  • EXTI_PR_PR6 : stm32l1xx.h
  • EXTI_PR_PR7 : stm32l1xx.h
  • EXTI_PR_PR8 : stm32l1xx.h
  • EXTI_PR_PR9 : stm32l1xx.h
  • EXTI_RTSR_TR0 : stm32l1xx.h
  • EXTI_RTSR_TR1 : stm32l1xx.h
  • EXTI_RTSR_TR10 : stm32l1xx.h
  • EXTI_RTSR_TR11 : stm32l1xx.h
  • EXTI_RTSR_TR12 : stm32l1xx.h
  • EXTI_RTSR_TR13 : stm32l1xx.h
  • EXTI_RTSR_TR14 : stm32l1xx.h
  • EXTI_RTSR_TR15 : stm32l1xx.h
  • EXTI_RTSR_TR16 : stm32l1xx.h
  • EXTI_RTSR_TR17 : stm32l1xx.h
  • EXTI_RTSR_TR18 : stm32l1xx.h
  • EXTI_RTSR_TR19 : stm32l1xx.h
  • EXTI_RTSR_TR2 : stm32l1xx.h
  • EXTI_RTSR_TR20 : stm32l1xx.h
  • EXTI_RTSR_TR21 : stm32l1xx.h
  • EXTI_RTSR_TR22 : stm32l1xx.h
  • EXTI_RTSR_TR23 : stm32l1xx.h
  • EXTI_RTSR_TR3 : stm32l1xx.h
  • EXTI_RTSR_TR4 : stm32l1xx.h
  • EXTI_RTSR_TR5 : stm32l1xx.h
  • EXTI_RTSR_TR6 : stm32l1xx.h
  • EXTI_RTSR_TR7 : stm32l1xx.h
  • EXTI_RTSR_TR8 : stm32l1xx.h
  • EXTI_RTSR_TR9 : stm32l1xx.h
  • EXTI_StructInit() : stm32l1xx_exti.c , stm32l1xx_exti.h
  • EXTI_SWIER_SWIER0 : stm32l1xx.h
  • EXTI_SWIER_SWIER1 : stm32l1xx.h
  • EXTI_SWIER_SWIER10 : stm32l1xx.h
  • EXTI_SWIER_SWIER11 : stm32l1xx.h
  • EXTI_SWIER_SWIER12 : stm32l1xx.h
  • EXTI_SWIER_SWIER13 : stm32l1xx.h
  • EXTI_SWIER_SWIER14 : stm32l1xx.h
  • EXTI_SWIER_SWIER15 : stm32l1xx.h
  • EXTI_SWIER_SWIER16 : stm32l1xx.h
  • EXTI_SWIER_SWIER17 : stm32l1xx.h
  • EXTI_SWIER_SWIER18 : stm32l1xx.h
  • EXTI_SWIER_SWIER19 : stm32l1xx.h
  • EXTI_SWIER_SWIER2 : stm32l1xx.h
  • EXTI_SWIER_SWIER20 : stm32l1xx.h
  • EXTI_SWIER_SWIER21 : stm32l1xx.h
  • EXTI_SWIER_SWIER22 : stm32l1xx.h
  • EXTI_SWIER_SWIER23 : stm32l1xx.h
  • EXTI_SWIER_SWIER3 : stm32l1xx.h
  • EXTI_SWIER_SWIER4 : stm32l1xx.h
  • EXTI_SWIER_SWIER5 : stm32l1xx.h
  • EXTI_SWIER_SWIER6 : stm32l1xx.h
  • EXTI_SWIER_SWIER7 : stm32l1xx.h
  • EXTI_SWIER_SWIER8 : stm32l1xx.h
  • EXTI_SWIER_SWIER9 : stm32l1xx.h
  • EXTI_Trigger_Falling : stm32l1xx_exti.h
  • EXTI_Trigger_Rising : stm32l1xx_exti.h
  • EXTI_Trigger_Rising_Falling : stm32l1xx_exti.h
  • EXTIMode_TypeDef : stm32l1xx_exti.h
  • EXTITrigger_TypeDef : stm32l1xx_exti.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • a
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  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
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  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FCR_HD_BB : stm32l1xx_lcd.c
  • FCR_MASK : stm32l1xx_lcd.c
  • FCR_OFFSET : stm32l1xx_lcd.c
  • FLAG_MASK : stm32l1xx_dma.c , stm32l1xx_i2c.c , stm32l1xx_rcc.c
  • FlagStatus : stm32l1xx.h
  • FLASH : stm32l1xx.h
  • FLASH_ACR_ACC64 : stm32l1xx.h
  • FLASH_ACR_LATENCY : stm32l1xx.h
  • FLASH_ACR_PRFTEN : stm32l1xx.h
  • FLASH_ACR_RUN_PD : stm32l1xx.h
  • FLASH_ACR_SLEEP_PD : stm32l1xx.h
  • FLASH_BASE : stm32l1xx.h
  • FLASH_BUSY : stm32l1xx_flash.h
  • FLASH_ClearFlag() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_COMPLETE : stm32l1xx_flash.h
  • FLASH_ER_PRG_TIMEOUT : stm32l1xx_flash.h
  • FLASH_ErasePage() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_EraseParallelPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_ERROR_PROGRAM : stm32l1xx_flash.h
  • FLASH_ERROR_WRP : stm32l1xx_flash.h
  • FLASH_FastProgramWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_FLAG_BSY : stm32l1xx_flash.h
  • FLASH_FLAG_ENDHV : stm32l1xx_flash.h
  • FLASH_FLAG_EOP : stm32l1xx_flash.h
  • FLASH_FLAG_OPTVERR : stm32l1xx_flash.h
  • FLASH_FLAG_OPTVERRUSR : stm32l1xx_flash.h
  • FLASH_FLAG_PGAERR : stm32l1xx_flash.h
  • FLASH_FLAG_READY : stm32l1xx_flash.h
  • FLASH_FLAG_SIZERR : stm32l1xx_flash.h
  • FLASH_FLAG_WRPERR : stm32l1xx_flash.h
  • FLASH_GetFlagStatus() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_GetStatus() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_IRQn : stm32l1xx.h
  • FLASH_IT_EOP : stm32l1xx_flash.h
  • FLASH_IT_ERR : stm32l1xx_flash.h
  • FLASH_ITConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_Latency_0 : stm32l1xx_flash.h
  • FLASH_Latency_1 : stm32l1xx_flash.h
  • FLASH_Lock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_BootConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_BORConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetBOR() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetRDP() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetUser() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP1() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP2() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_Launch() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_Lock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_RDPConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_Unlock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_UserConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRP1Config() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRP2Config() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRPConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OBR_BOR_LEV : stm32l1xx.h
  • FLASH_OBR_IWDG_SW : stm32l1xx.h
  • FLASH_OBR_nRST_BFB2 : stm32l1xx.h
  • FLASH_OBR_nRST_STDBY : stm32l1xx.h
  • FLASH_OBR_nRST_STOP : stm32l1xx.h
  • FLASH_OBR_RDPRT : stm32l1xx.h
  • FLASH_OBR_USER : stm32l1xx.h
  • FLASH_OPTKEY1 : stm32l1xx_flash.h
  • FLASH_OPTKEY2 : stm32l1xx_flash.h
  • FLASH_OPTKEYR_OPTKEYR : stm32l1xx.h
  • FLASH_PDKEY1 : stm32l1xx_flash.h
  • FLASH_PDKEY2 : stm32l1xx_flash.h
  • FLASH_PDKEYR_PDKEYR : stm32l1xx.h
  • FLASH_PECR_DATA : stm32l1xx.h
  • FLASH_PECR_EOPIE : stm32l1xx.h
  • FLASH_PECR_ERASE : stm32l1xx.h
  • FLASH_PECR_ERRIE : stm32l1xx.h
  • FLASH_PECR_FPRG : stm32l1xx.h
  • FLASH_PECR_FTDW : stm32l1xx.h
  • FLASH_PECR_OBL_LAUNCH : stm32l1xx.h
  • FLASH_PECR_OPTLOCK : stm32l1xx.h
  • FLASH_PECR_PARALLBANK : stm32l1xx.h
  • FLASH_PECR_PELOCK : stm32l1xx.h
  • FLASH_PECR_PRGLOCK : stm32l1xx.h
  • FLASH_PECR_PROG : stm32l1xx.h
  • FLASH_PEKEY1 : stm32l1xx_flash.h
  • FLASH_PEKEY2 : stm32l1xx_flash.h
  • FLASH_PEKEYR_PEKEYR : stm32l1xx.h
  • FLASH_PrefetchBufferCmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_PRGKEY1 : stm32l1xx_flash.h
  • FLASH_PRGKEY2 : stm32l1xx_flash.h
  • FLASH_PRGKEYR_PRGKEYR : stm32l1xx.h
  • FLASH_ProgramHalfPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_ProgramParallelHalfPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_R_BASE : stm32l1xx.h
  • FLASH_ReadAccess64Cmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_RUNPowerDownCmd() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_SetLatency() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_SLEEPPowerDownCmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_SR_BSY : stm32l1xx.h
  • FLASH_SR_ENHV : stm32l1xx.h
  • FLASH_SR_EOP : stm32l1xx.h
  • FLASH_SR_OPTVERR : stm32l1xx.h
  • FLASH_SR_OPTVERRUSR : stm32l1xx.h
  • FLASH_SR_PGAERR : stm32l1xx.h
  • FLASH_SR_READY : stm32l1xx.h
  • FLASH_SR_SIZERR : stm32l1xx.h
  • FLASH_SR_WRPERR : stm32l1xx.h
  • FLASH_Status : stm32l1xx_flash.h
  • FLASH_TIMEOUT : stm32l1xx_flash.h
  • FLASH_Unlock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_WaitForLastOperation() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_WRPR1_WRP : stm32l1xx.h
  • FLASH_WRPR2_WRP : stm32l1xx.h
  • FLASH_WRPR_WRP : stm32l1xx.h
  • FSMC_AccessMode_A : stm32l1xx_fsmc.h
  • FSMC_AccessMode_B : stm32l1xx_fsmc.h
  • FSMC_AccessMode_C : stm32l1xx_fsmc.h
  • FSMC_AccessMode_D : stm32l1xx_fsmc.h
  • FSMC_AsynchronousWait_Disable : stm32l1xx_fsmc.h
  • FSMC_AsynchronousWait_Enable : stm32l1xx_fsmc.h
  • FSMC_Bank1 : stm32l1xx.h
  • FSMC_Bank1_NORSRAM1 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM2 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM3 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM4 : stm32l1xx_fsmc.h
  • FSMC_Bank1_R_BASE : stm32l1xx.h
  • FSMC_Bank1E : stm32l1xx.h
  • FSMC_Bank1E_R_BASE : stm32l1xx.h
  • FSMC_BCR1_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR1_BURSTEN : stm32l1xx.h
  • FSMC_BCR1_CBURSTRW : stm32l1xx.h
  • FSMC_BCR1_EXTMOD : stm32l1xx.h
  • FSMC_BCR1_FACCEN : stm32l1xx.h
  • FSMC_BCR1_MBKEN : stm32l1xx.h
  • FSMC_BCR1_MTYP : stm32l1xx.h
  • FSMC_BCR1_MTYP_0 : stm32l1xx.h
  • FSMC_BCR1_MTYP_1 : stm32l1xx.h
  • FSMC_BCR1_MUXEN : stm32l1xx.h
  • FSMC_BCR1_MWID : stm32l1xx.h
  • FSMC_BCR1_MWID_0 : stm32l1xx.h
  • FSMC_BCR1_MWID_1 : stm32l1xx.h
  • FSMC_BCR1_WAITCFG : stm32l1xx.h
  • FSMC_BCR1_WAITEN : stm32l1xx.h
  • FSMC_BCR1_WAITPOL : stm32l1xx.h
  • FSMC_BCR1_WRAPMOD : stm32l1xx.h
  • FSMC_BCR1_WREN : stm32l1xx.h
  • FSMC_BCR2_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR2_BURSTEN : stm32l1xx.h
  • FSMC_BCR2_CBURSTRW : stm32l1xx.h
  • FSMC_BCR2_EXTMOD : stm32l1xx.h
  • FSMC_BCR2_FACCEN : stm32l1xx.h
  • FSMC_BCR2_MBKEN : stm32l1xx.h
  • FSMC_BCR2_MTYP : stm32l1xx.h
  • FSMC_BCR2_MTYP_0 : stm32l1xx.h
  • FSMC_BCR2_MTYP_1 : stm32l1xx.h
  • FSMC_BCR2_MUXEN : stm32l1xx.h
  • FSMC_BCR2_MWID : stm32l1xx.h
  • FSMC_BCR2_MWID_0 : stm32l1xx.h
  • FSMC_BCR2_MWID_1 : stm32l1xx.h
  • FSMC_BCR2_WAITCFG : stm32l1xx.h
  • FSMC_BCR2_WAITEN : stm32l1xx.h
  • FSMC_BCR2_WAITPOL : stm32l1xx.h
  • FSMC_BCR2_WRAPMOD : stm32l1xx.h
  • FSMC_BCR2_WREN : stm32l1xx.h
  • FSMC_BCR3_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR3_BURSTEN : stm32l1xx.h
  • FSMC_BCR3_CBURSTRW : stm32l1xx.h
  • FSMC_BCR3_EXTMOD : stm32l1xx.h
  • FSMC_BCR3_FACCEN : stm32l1xx.h
  • FSMC_BCR3_MBKEN : stm32l1xx.h
  • FSMC_BCR3_MTYP : stm32l1xx.h
  • FSMC_BCR3_MTYP_0 : stm32l1xx.h
  • FSMC_BCR3_MTYP_1 : stm32l1xx.h
  • FSMC_BCR3_MUXEN : stm32l1xx.h
  • FSMC_BCR3_MWID : stm32l1xx.h
  • FSMC_BCR3_MWID_0 : stm32l1xx.h
  • FSMC_BCR3_MWID_1 : stm32l1xx.h
  • FSMC_BCR3_WAITCFG : stm32l1xx.h
  • FSMC_BCR3_WAITEN : stm32l1xx.h
  • FSMC_BCR3_WAITPOL : stm32l1xx.h
  • FSMC_BCR3_WRAPMOD : stm32l1xx.h
  • FSMC_BCR3_WREN : stm32l1xx.h
  • FSMC_BCR4_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR4_BURSTEN : stm32l1xx.h
  • FSMC_BCR4_CBURSTRW : stm32l1xx.h
  • FSMC_BCR4_EXTMOD : stm32l1xx.h
  • FSMC_BCR4_FACCEN : stm32l1xx.h
  • FSMC_BCR4_MBKEN : stm32l1xx.h
  • FSMC_BCR4_MTYP : stm32l1xx.h
  • FSMC_BCR4_MTYP_0 : stm32l1xx.h
  • FSMC_BCR4_MTYP_1 : stm32l1xx.h
  • FSMC_BCR4_MUXEN : stm32l1xx.h
  • FSMC_BCR4_MWID : stm32l1xx.h
  • FSMC_BCR4_MWID_0 : stm32l1xx.h
  • FSMC_BCR4_MWID_1 : stm32l1xx.h
  • FSMC_BCR4_WAITCFG : stm32l1xx.h
  • FSMC_BCR4_WAITEN : stm32l1xx.h
  • FSMC_BCR4_WAITPOL : stm32l1xx.h
  • FSMC_BCR4_WRAPMOD : stm32l1xx.h
  • FSMC_BCR4_WREN : stm32l1xx.h
  • FSMC_BTR1_ACCMOD : stm32l1xx.h
  • FSMC_BTR1_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR1_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR1_ADDSET : stm32l1xx.h
  • FSMC_BTR1_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR1_DATAST : stm32l1xx.h
  • FSMC_BTR1_DATAST_0 : stm32l1xx.h
  • FSMC_BTR1_DATAST_1 : stm32l1xx.h
  • FSMC_BTR1_DATAST_2 : stm32l1xx.h
  • FSMC_BTR1_DATAST_3 : stm32l1xx.h
  • FSMC_BTR1_DATLAT : stm32l1xx.h
  • FSMC_BTR1_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR2_ACCMOD : stm32l1xx.h
  • FSMC_BTR2_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR2_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR2_ADDSET : stm32l1xx.h
  • FSMC_BTR2_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR2_DATAST : stm32l1xx.h
  • FSMC_BTR2_DATAST_0 : stm32l1xx.h
  • FSMC_BTR2_DATAST_1 : stm32l1xx.h
  • FSMC_BTR2_DATAST_2 : stm32l1xx.h
  • FSMC_BTR2_DATAST_3 : stm32l1xx.h
  • FSMC_BTR2_DATLAT : stm32l1xx.h
  • FSMC_BTR2_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR3_ACCMOD : stm32l1xx.h
  • FSMC_BTR3_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR3_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR3_ADDSET : stm32l1xx.h
  • FSMC_BTR3_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR3_DATAST : stm32l1xx.h
  • FSMC_BTR3_DATAST_0 : stm32l1xx.h
  • FSMC_BTR3_DATAST_1 : stm32l1xx.h
  • FSMC_BTR3_DATAST_2 : stm32l1xx.h
  • FSMC_BTR3_DATAST_3 : stm32l1xx.h
  • FSMC_BTR3_DATLAT : stm32l1xx.h
  • FSMC_BTR3_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR4_ACCMOD : stm32l1xx.h
  • FSMC_BTR4_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR4_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR4_ADDSET : stm32l1xx.h
  • FSMC_BTR4_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR4_DATAST : stm32l1xx.h
  • FSMC_BTR4_DATAST_0 : stm32l1xx.h
  • FSMC_BTR4_DATAST_1 : stm32l1xx.h
  • FSMC_BTR4_DATAST_2 : stm32l1xx.h
  • FSMC_BTR4_DATAST_3 : stm32l1xx.h
  • FSMC_BTR4_DATLAT : stm32l1xx.h
  • FSMC_BTR4_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_3 : stm32l1xx.h
  • FSMC_BurstAccessMode_Disable : stm32l1xx_fsmc.h
  • FSMC_BurstAccessMode_Enable : stm32l1xx_fsmc.h
  • FSMC_BWTR1_ACCMOD : stm32l1xx.h
  • FSMC_BWTR1_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR1_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR1_DATAST : stm32l1xx.h
  • FSMC_BWTR1_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR2_DATAST : stm32l1xx.h
  • FSMC_BWTR2_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR3_DATAST : stm32l1xx.h
  • FSMC_BWTR3_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR4_DATAST : stm32l1xx.h
  • FSMC_BWTR4_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_3 : stm32l1xx.h
  • FSMC_DataAddressMux_Disable : stm32l1xx_fsmc.h
  • FSMC_DataAddressMux_Enable : stm32l1xx_fsmc.h
  • FSMC_ExtendedMode_Disable : stm32l1xx_fsmc.h
  • FSMC_ExtendedMode_Enable : stm32l1xx_fsmc.h
  • FSMC_MemoryDataWidth_16b : stm32l1xx_fsmc.h
  • FSMC_MemoryDataWidth_8b : stm32l1xx_fsmc.h
  • FSMC_MemoryType_NOR : stm32l1xx_fsmc.h
  • FSMC_MemoryType_PSRAM : stm32l1xx_fsmc.h
  • FSMC_MemoryType_SRAM : stm32l1xx_fsmc.h
  • FSMC_NORSRAMCmd() : stm32l1xx_fsmc.c , stm32l1xx_fsmc.h
  • FSMC_NORSRAMDeInit() : stm32l1xx_fsmc.h , stm32l1xx_fsmc.c
  • FSMC_NORSRAMInit() : stm32l1xx_fsmc.h , stm32l1xx_fsmc.c
  • FSMC_NORSRAMStructInit() : stm32l1xx_fsmc.c , stm32l1xx_fsmc.h
  • FSMC_R_BASE : stm32l1xx.h
  • FSMC_WaitSignal_Disable : stm32l1xx_fsmc.h
  • FSMC_WaitSignal_Enable : stm32l1xx_fsmc.h
  • FSMC_WaitSignalActive_BeforeWaitState : stm32l1xx_fsmc.h
  • FSMC_WaitSignalActive_DuringWaitState : stm32l1xx_fsmc.h
  • FSMC_WaitSignalPolarity_High : stm32l1xx_fsmc.h
  • FSMC_WaitSignalPolarity_Low : stm32l1xx_fsmc.h
  • FSMC_WrapMode_Disable : stm32l1xx_fsmc.h
  • FSMC_WrapMode_Enable : stm32l1xx_fsmc.h
  • FSMC_WriteBurst_Disable : stm32l1xx_fsmc.h
  • FSMC_WriteBurst_Enable : stm32l1xx_fsmc.h
  • FSMC_WriteOperation_Disable : stm32l1xx_fsmc.h
  • FSMC_WriteOperation_Enable : stm32l1xx_fsmc.h
  • FunctionalState : stm32l1xx.h
  • FWU_BitNumber : stm32l1xx_pwr.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GetStatus() : stm32l1xx_flash_ramfunc.c
  • GPIO_AF_EVENTOUT : stm32l1xx_gpio.h
  • GPIO_AF_FSMC : stm32l1xx_gpio.h
  • GPIO_AF_I2C1 : stm32l1xx_gpio.h
  • GPIO_AF_I2C2 : stm32l1xx_gpio.h
  • GPIO_AF_LCD : stm32l1xx_gpio.h
  • GPIO_AF_MCO : stm32l1xx_gpio.h
  • GPIO_AF_RI : stm32l1xx_gpio.h
  • GPIO_AF_RTC_50Hz : stm32l1xx_gpio.h
  • GPIO_AF_RTC_AF1 : stm32l1xx_gpio.h
  • GPIO_AF_SDIO : stm32l1xx_gpio.h
  • GPIO_AF_SPI1 : stm32l1xx_gpio.h
  • GPIO_AF_SPI2 : stm32l1xx_gpio.h
  • GPIO_AF_SPI3 : stm32l1xx_gpio.h
  • GPIO_AF_SWJ : stm32l1xx_gpio.h
  • GPIO_AF_TIM10 : stm32l1xx_gpio.h
  • GPIO_AF_TIM11 : stm32l1xx_gpio.h
  • GPIO_AF_TIM2 : stm32l1xx_gpio.h
  • GPIO_AF_TIM3 : stm32l1xx_gpio.h
  • GPIO_AF_TIM4 : stm32l1xx_gpio.h
  • GPIO_AF_TIM5 : stm32l1xx_gpio.h
  • GPIO_AF_TIM9 : stm32l1xx_gpio.h
  • GPIO_AF_TRACE : stm32l1xx_gpio.h
  • GPIO_AF_UART4 : stm32l1xx_gpio.h
  • GPIO_AF_UART5 : stm32l1xx_gpio.h
  • GPIO_AF_USART1 : stm32l1xx_gpio.h
  • GPIO_AF_USART2 : stm32l1xx_gpio.h
  • GPIO_AF_USART3 : stm32l1xx_gpio.h
  • GPIO_AF_USB : stm32l1xx_gpio.h
  • GPIO_AF_WKUP : stm32l1xx_gpio.h
  • GPIO_AFRH_AFRH10 : stm32l1xx.h
  • GPIO_AFRH_AFRH11 : stm32l1xx.h
  • GPIO_AFRH_AFRH12 : stm32l1xx.h
  • GPIO_AFRH_AFRH13 : stm32l1xx.h
  • GPIO_AFRH_AFRH14 : stm32l1xx.h
  • GPIO_AFRH_AFRH15 : stm32l1xx.h
  • GPIO_AFRH_AFRH8 : stm32l1xx.h
  • GPIO_AFRH_AFRH9 : stm32l1xx.h
  • GPIO_AFRL_AFRL0 : stm32l1xx.h
  • GPIO_AFRL_AFRL1 : stm32l1xx.h
  • GPIO_AFRL_AFRL2 : stm32l1xx.h
  • GPIO_AFRL_AFRL3 : stm32l1xx.h
  • GPIO_AFRL_AFRL4 : stm32l1xx.h
  • GPIO_AFRL_AFRL5 : stm32l1xx.h
  • GPIO_AFRL_AFRL6 : stm32l1xx.h
  • GPIO_AFRL_AFRL7 : stm32l1xx.h
  • GPIO_BSRR_BR_0 : stm32l1xx.h
  • GPIO_BSRR_BR_1 : stm32l1xx.h
  • GPIO_BSRR_BR_10 : stm32l1xx.h
  • GPIO_BSRR_BR_11 : stm32l1xx.h
  • GPIO_BSRR_BR_12 : stm32l1xx.h
  • GPIO_BSRR_BR_13 : stm32l1xx.h
  • GPIO_BSRR_BR_14 : stm32l1xx.h
  • GPIO_BSRR_BR_15 : stm32l1xx.h
  • GPIO_BSRR_BR_2 : stm32l1xx.h
  • GPIO_BSRR_BR_3 : stm32l1xx.h
  • GPIO_BSRR_BR_4 : stm32l1xx.h
  • GPIO_BSRR_BR_5 : stm32l1xx.h
  • GPIO_BSRR_BR_6 : stm32l1xx.h
  • GPIO_BSRR_BR_7 : stm32l1xx.h
  • GPIO_BSRR_BR_8 : stm32l1xx.h
  • GPIO_BSRR_BR_9 : stm32l1xx.h
  • GPIO_BSRR_BS_0 : stm32l1xx.h
  • GPIO_BSRR_BS_1 : stm32l1xx.h
  • GPIO_BSRR_BS_10 : stm32l1xx.h
  • GPIO_BSRR_BS_11 : stm32l1xx.h
  • GPIO_BSRR_BS_12 : stm32l1xx.h
  • GPIO_BSRR_BS_13 : stm32l1xx.h
  • GPIO_BSRR_BS_14 : stm32l1xx.h
  • GPIO_BSRR_BS_15 : stm32l1xx.h
  • GPIO_BSRR_BS_2 : stm32l1xx.h
  • GPIO_BSRR_BS_3 : stm32l1xx.h
  • GPIO_BSRR_BS_4 : stm32l1xx.h
  • GPIO_BSRR_BS_5 : stm32l1xx.h
  • GPIO_BSRR_BS_6 : stm32l1xx.h
  • GPIO_BSRR_BS_7 : stm32l1xx.h
  • GPIO_BSRR_BS_8 : stm32l1xx.h
  • GPIO_BSRR_BS_9 : stm32l1xx.h
  • GPIO_DeInit() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_IDR_IDR_0 : stm32l1xx.h
  • GPIO_IDR_IDR_1 : stm32l1xx.h
  • GPIO_IDR_IDR_10 : stm32l1xx.h
  • GPIO_IDR_IDR_11 : stm32l1xx.h
  • GPIO_IDR_IDR_12 : stm32l1xx.h
  • GPIO_IDR_IDR_13 : stm32l1xx.h
  • GPIO_IDR_IDR_14 : stm32l1xx.h
  • GPIO_IDR_IDR_15 : stm32l1xx.h
  • GPIO_IDR_IDR_2 : stm32l1xx.h
  • GPIO_IDR_IDR_3 : stm32l1xx.h
  • GPIO_IDR_IDR_4 : stm32l1xx.h
  • GPIO_IDR_IDR_5 : stm32l1xx.h
  • GPIO_IDR_IDR_6 : stm32l1xx.h
  • GPIO_IDR_IDR_7 : stm32l1xx.h
  • GPIO_IDR_IDR_8 : stm32l1xx.h
  • GPIO_IDR_IDR_9 : stm32l1xx.h
  • GPIO_Init() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_LCKR_LCK0 : stm32l1xx.h
  • GPIO_LCKR_LCK1 : stm32l1xx.h
  • GPIO_LCKR_LCK10 : stm32l1xx.h
  • GPIO_LCKR_LCK11 : stm32l1xx.h
  • GPIO_LCKR_LCK12 : stm32l1xx.h
  • GPIO_LCKR_LCK13 : stm32l1xx.h
  • GPIO_LCKR_LCK14 : stm32l1xx.h
  • GPIO_LCKR_LCK15 : stm32l1xx.h
  • GPIO_LCKR_LCK2 : stm32l1xx.h
  • GPIO_LCKR_LCK3 : stm32l1xx.h
  • GPIO_LCKR_LCK4 : stm32l1xx.h
  • GPIO_LCKR_LCK5 : stm32l1xx.h
  • GPIO_LCKR_LCK6 : stm32l1xx.h
  • GPIO_LCKR_LCK7 : stm32l1xx.h
  • GPIO_LCKR_LCK8 : stm32l1xx.h
  • GPIO_LCKR_LCK9 : stm32l1xx.h
  • GPIO_LCKR_LCKK : stm32l1xx.h
  • GPIO_Mode_AF : stm32l1xx_gpio.h
  • GPIO_Mode_AIN : stm32l1xx_gpio.h
  • GPIO_Mode_AN : stm32l1xx_gpio.h
  • GPIO_Mode_IN : stm32l1xx_gpio.h
  • GPIO_Mode_OUT : stm32l1xx_gpio.h
  • GPIO_MODER_MODER0 : stm32l1xx.h
  • GPIO_MODER_MODER0_0 : stm32l1xx.h
  • GPIO_MODER_MODER0_1 : stm32l1xx.h
  • GPIO_MODER_MODER1 : stm32l1xx.h
  • GPIO_MODER_MODER10 : stm32l1xx.h
  • GPIO_MODER_MODER10_0 : stm32l1xx.h
  • GPIO_MODER_MODER10_1 : stm32l1xx.h
  • GPIO_MODER_MODER11 : stm32l1xx.h
  • GPIO_MODER_MODER11_0 : stm32l1xx.h
  • GPIO_MODER_MODER11_1 : stm32l1xx.h
  • GPIO_MODER_MODER12 : stm32l1xx.h
  • GPIO_MODER_MODER12_0 : stm32l1xx.h
  • GPIO_MODER_MODER12_1 : stm32l1xx.h
  • GPIO_MODER_MODER13 : stm32l1xx.h
  • GPIO_MODER_MODER13_0 : stm32l1xx.h
  • GPIO_MODER_MODER13_1 : stm32l1xx.h
  • GPIO_MODER_MODER14 : stm32l1xx.h
  • GPIO_MODER_MODER14_0 : stm32l1xx.h
  • GPIO_MODER_MODER14_1 : stm32l1xx.h
  • GPIO_MODER_MODER15 : stm32l1xx.h
  • GPIO_MODER_MODER15_0 : stm32l1xx.h
  • GPIO_MODER_MODER15_1 : stm32l1xx.h
  • GPIO_MODER_MODER1_0 : stm32l1xx.h
  • GPIO_MODER_MODER1_1 : stm32l1xx.h
  • GPIO_MODER_MODER2 : stm32l1xx.h
  • GPIO_MODER_MODER2_0 : stm32l1xx.h
  • GPIO_MODER_MODER2_1 : stm32l1xx.h
  • GPIO_MODER_MODER3 : stm32l1xx.h
  • GPIO_MODER_MODER3_0 : stm32l1xx.h
  • GPIO_MODER_MODER3_1 : stm32l1xx.h
  • GPIO_MODER_MODER4 : stm32l1xx.h
  • GPIO_MODER_MODER4_0 : stm32l1xx.h
  • GPIO_MODER_MODER4_1 : stm32l1xx.h
  • GPIO_MODER_MODER5 : stm32l1xx.h
  • GPIO_MODER_MODER5_0 : stm32l1xx.h
  • GPIO_MODER_MODER5_1 : stm32l1xx.h
  • GPIO_MODER_MODER6 : stm32l1xx.h
  • GPIO_MODER_MODER6_0 : stm32l1xx.h
  • GPIO_MODER_MODER6_1 : stm32l1xx.h
  • GPIO_MODER_MODER7 : stm32l1xx.h
  • GPIO_MODER_MODER7_0 : stm32l1xx.h
  • GPIO_MODER_MODER7_1 : stm32l1xx.h
  • GPIO_MODER_MODER8 : stm32l1xx.h
  • GPIO_MODER_MODER8_0 : stm32l1xx.h
  • GPIO_MODER_MODER8_1 : stm32l1xx.h
  • GPIO_MODER_MODER9 : stm32l1xx.h
  • GPIO_MODER_MODER9_0 : stm32l1xx.h
  • GPIO_MODER_MODER9_1 : stm32l1xx.h
  • GPIO_ODR_ODR_0 : stm32l1xx.h
  • GPIO_ODR_ODR_1 : stm32l1xx.h
  • GPIO_ODR_ODR_10 : stm32l1xx.h
  • GPIO_ODR_ODR_11 : stm32l1xx.h
  • GPIO_ODR_ODR_12 : stm32l1xx.h
  • GPIO_ODR_ODR_13 : stm32l1xx.h
  • GPIO_ODR_ODR_14 : stm32l1xx.h
  • GPIO_ODR_ODR_15 : stm32l1xx.h
  • GPIO_ODR_ODR_2 : stm32l1xx.h
  • GPIO_ODR_ODR_3 : stm32l1xx.h
  • GPIO_ODR_ODR_4 : stm32l1xx.h
  • GPIO_ODR_ODR_5 : stm32l1xx.h
  • GPIO_ODR_ODR_6 : stm32l1xx.h
  • GPIO_ODR_ODR_7 : stm32l1xx.h
  • GPIO_ODR_ODR_8 : stm32l1xx.h
  • GPIO_ODR_ODR_9 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9_1 : stm32l1xx.h
  • GPIO_OType_OD : stm32l1xx_gpio.h
  • GPIO_OType_PP : stm32l1xx_gpio.h
  • GPIO_OTYPER_IDR_0 : stm32l1xx.h
  • GPIO_OTYPER_IDR_1 : stm32l1xx.h
  • GPIO_OTYPER_IDR_10 : stm32l1xx.h
  • GPIO_OTYPER_IDR_11 : stm32l1xx.h
  • GPIO_OTYPER_IDR_12 : stm32l1xx.h
  • GPIO_OTYPER_IDR_13 : stm32l1xx.h
  • GPIO_OTYPER_IDR_14 : stm32l1xx.h
  • GPIO_OTYPER_IDR_15 : stm32l1xx.h
  • GPIO_OTYPER_IDR_2 : stm32l1xx.h
  • GPIO_OTYPER_IDR_3 : stm32l1xx.h
  • GPIO_OTYPER_IDR_4 : stm32l1xx.h
  • GPIO_OTYPER_IDR_5 : stm32l1xx.h
  • GPIO_OTYPER_IDR_6 : stm32l1xx.h
  • GPIO_OTYPER_IDR_7 : stm32l1xx.h
  • GPIO_OTYPER_IDR_8 : stm32l1xx.h
  • GPIO_OTYPER_IDR_9 : stm32l1xx.h
  • GPIO_OTYPER_ODR_0 : stm32l1xx.h
  • GPIO_OTYPER_ODR_1 : stm32l1xx.h
  • GPIO_OTYPER_ODR_10 : stm32l1xx.h
  • GPIO_OTYPER_ODR_11 : stm32l1xx.h
  • GPIO_OTYPER_ODR_12 : stm32l1xx.h
  • GPIO_OTYPER_ODR_13 : stm32l1xx.h
  • GPIO_OTYPER_ODR_14 : stm32l1xx.h
  • GPIO_OTYPER_ODR_15 : stm32l1xx.h
  • GPIO_OTYPER_ODR_2 : stm32l1xx.h
  • GPIO_OTYPER_ODR_3 : stm32l1xx.h
  • GPIO_OTYPER_ODR_4 : stm32l1xx.h
  • GPIO_OTYPER_ODR_5 : stm32l1xx.h
  • GPIO_OTYPER_ODR_6 : stm32l1xx.h
  • GPIO_OTYPER_ODR_7 : stm32l1xx.h
  • GPIO_OTYPER_ODR_8 : stm32l1xx.h
  • GPIO_OTYPER_ODR_9 : stm32l1xx.h
  • GPIO_OTYPER_OT_0 : stm32l1xx.h
  • GPIO_OTYPER_OT_1 : stm32l1xx.h
  • GPIO_OTYPER_OT_10 : stm32l1xx.h
  • GPIO_OTYPER_OT_11 : stm32l1xx.h
  • GPIO_OTYPER_OT_12 : stm32l1xx.h
  • GPIO_OTYPER_OT_13 : stm32l1xx.h
  • GPIO_OTYPER_OT_14 : stm32l1xx.h
  • GPIO_OTYPER_OT_15 : stm32l1xx.h
  • GPIO_OTYPER_OT_2 : stm32l1xx.h
  • GPIO_OTYPER_OT_3 : stm32l1xx.h
  • GPIO_OTYPER_OT_4 : stm32l1xx.h
  • GPIO_OTYPER_OT_5 : stm32l1xx.h
  • GPIO_OTYPER_OT_6 : stm32l1xx.h
  • GPIO_OTYPER_OT_7 : stm32l1xx.h
  • GPIO_OTYPER_OT_8 : stm32l1xx.h
  • GPIO_OTYPER_OT_9 : stm32l1xx.h
  • GPIO_Pin_0 : stm32l1xx_gpio.h
  • GPIO_Pin_1 : stm32l1xx_gpio.h
  • GPIO_Pin_10 : stm32l1xx_gpio.h
  • GPIO_Pin_11 : stm32l1xx_gpio.h
  • GPIO_Pin_12 : stm32l1xx_gpio.h
  • GPIO_Pin_13 : stm32l1xx_gpio.h
  • GPIO_Pin_14 : stm32l1xx_gpio.h
  • GPIO_Pin_15 : stm32l1xx_gpio.h
  • GPIO_Pin_2 : stm32l1xx_gpio.h
  • GPIO_Pin_3 : stm32l1xx_gpio.h
  • GPIO_Pin_4 : stm32l1xx_gpio.h
  • GPIO_Pin_5 : stm32l1xx_gpio.h
  • GPIO_Pin_6 : stm32l1xx_gpio.h
  • GPIO_Pin_7 : stm32l1xx_gpio.h
  • GPIO_Pin_8 : stm32l1xx_gpio.h
  • GPIO_Pin_9 : stm32l1xx_gpio.h
  • GPIO_Pin_All : stm32l1xx_gpio.h
  • GPIO_PinAFConfig() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_PinLockConfig() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_PinSource0 : stm32l1xx_gpio.h
  • GPIO_PinSource1 : stm32l1xx_gpio.h
  • GPIO_PinSource10 : stm32l1xx_gpio.h
  • GPIO_PinSource11 : stm32l1xx_gpio.h
  • GPIO_PinSource12 : stm32l1xx_gpio.h
  • GPIO_PinSource13 : stm32l1xx_gpio.h
  • GPIO_PinSource14 : stm32l1xx_gpio.h
  • GPIO_PinSource15 : stm32l1xx_gpio.h
  • GPIO_PinSource2 : stm32l1xx_gpio.h
  • GPIO_PinSource3 : stm32l1xx_gpio.h
  • GPIO_PinSource4 : stm32l1xx_gpio.h
  • GPIO_PinSource5 : stm32l1xx_gpio.h
  • GPIO_PinSource6 : stm32l1xx_gpio.h
  • GPIO_PinSource7 : stm32l1xx_gpio.h
  • GPIO_PinSource8 : stm32l1xx_gpio.h
  • GPIO_PinSource9 : stm32l1xx_gpio.h
  • GPIO_PuPd_DOWN : stm32l1xx_gpio.h
  • GPIO_PuPd_NOPULL : stm32l1xx_gpio.h
  • GPIO_PuPd_UP : stm32l1xx_gpio.h
  • GPIO_PUPDR_PUPDR0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR0_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR0_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9_1 : stm32l1xx.h
  • GPIO_ReadInputData() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadInputDataBit() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_ReadOutputData() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadOutputDataBit() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_ResetBits() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_SetBits() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_Speed_10MHz : stm32l1xx_gpio.h
  • GPIO_Speed_2MHz : stm32l1xx_gpio.h
  • GPIO_Speed_400KHz : stm32l1xx_gpio.h
  • GPIO_Speed_40MHz : stm32l1xx_gpio.h
  • GPIO_StructInit() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_ToggleBits() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_Write() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_WriteBit() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIOA : stm32l1xx.h
  • GPIOA_BASE : stm32l1xx.h
  • GPIOB : stm32l1xx.h
  • GPIOB_BASE : stm32l1xx.h
  • GPIOC : stm32l1xx.h
  • GPIOC_BASE : stm32l1xx.h
  • GPIOD : stm32l1xx.h
  • GPIOD_BASE : stm32l1xx.h
  • GPIOE : stm32l1xx.h
  • GPIOE_BASE : stm32l1xx.h
  • GPIOF : stm32l1xx.h
  • GPIOF_BASE : stm32l1xx.h
  • GPIOG : stm32l1xx.h
  • GPIOG_BASE : stm32l1xx.h
  • GPIOH : stm32l1xx.h
  • GPIOH_BASE : stm32l1xx.h
  • GPIOMode_TypeDef : stm32l1xx_gpio.h
  • GPIOOType_TypeDef : stm32l1xx_gpio.h
  • GPIOPuPd_TypeDef : stm32l1xx_gpio.h
  • GPIOSpeed_TypeDef : stm32l1xx_gpio.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HD_BitNumber : stm32l1xx_lcd.c
  • HSE_STARTUP_TIMEOUT : stm32l1xx.h
  • HSE_VALUE : stm32l1xx.h
  • HSI_STARTUP_TIMEOUT : stm32l1xx.h
  • HSI_VALUE : stm32l1xx.h
  • HSION_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C1 : stm32l1xx.h
  • I2C1_BASE : stm32l1xx.h
  • I2C1_ER_IRQn : stm32l1xx.h
  • I2C1_EV_IRQn : stm32l1xx.h
  • I2C2 : stm32l1xx.h
  • I2C2_BASE : stm32l1xx.h
  • I2C2_ER_IRQn : stm32l1xx.h
  • I2C2_EV_IRQn : stm32l1xx.h
  • I2C_Ack_Disable : stm32l1xx_i2c.h
  • I2C_Ack_Enable : stm32l1xx_i2c.h
  • I2C_AcknowledgeConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_AcknowledgedAddress_10bit : stm32l1xx_i2c.h
  • I2C_AcknowledgedAddress_7bit : stm32l1xx_i2c.h
  • I2C_ARPCmd() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_CalculatePEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_CCR_CCR : stm32l1xx.h
  • I2C_CCR_DUTY : stm32l1xx.h
  • I2C_CCR_FS : stm32l1xx.h
  • I2C_CheckEvent() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ClearFlag() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ClearITPendingBit() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Cmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_CR1_ACK : stm32l1xx.h
  • I2C_CR1_ALERT : stm32l1xx.h
  • I2C_CR1_ENARP : stm32l1xx.h
  • I2C_CR1_ENGC : stm32l1xx.h
  • I2C_CR1_ENPEC : stm32l1xx.h
  • I2C_CR1_NOSTRETCH : stm32l1xx.h
  • I2C_CR1_PE : stm32l1xx.h
  • I2C_CR1_PEC : stm32l1xx.h
  • I2C_CR1_POS : stm32l1xx.h
  • I2C_CR1_SMBTYPE : stm32l1xx.h
  • I2C_CR1_SMBUS : stm32l1xx.h
  • I2C_CR1_START : stm32l1xx.h
  • I2C_CR1_STOP : stm32l1xx.h
  • I2C_CR1_SWRST : stm32l1xx.h
  • I2C_CR2_DMAEN : stm32l1xx.h
  • I2C_CR2_FREQ : stm32l1xx.h
  • I2C_CR2_FREQ_0 : stm32l1xx.h
  • I2C_CR2_FREQ_1 : stm32l1xx.h
  • I2C_CR2_FREQ_2 : stm32l1xx.h
  • I2C_CR2_FREQ_3 : stm32l1xx.h
  • I2C_CR2_FREQ_4 : stm32l1xx.h
  • I2C_CR2_FREQ_5 : stm32l1xx.h
  • I2C_CR2_ITBUFEN : stm32l1xx.h
  • I2C_CR2_ITERREN : stm32l1xx.h
  • I2C_CR2_ITEVTEN : stm32l1xx.h
  • I2C_CR2_LAST : stm32l1xx.h
  • I2C_DeInit() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Direction_Receiver : stm32l1xx_i2c.h
  • I2C_Direction_Transmitter : stm32l1xx_i2c.h
  • I2C_DMACmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DMALastTransferCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DR_DR : stm32l1xx.h
  • I2C_DualAddressCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DutyCycle_16_9 : stm32l1xx_i2c.h
  • I2C_DutyCycle_2 : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_FastModeDutyCycleConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_FLAG_ADD10 : stm32l1xx_i2c.h
  • I2C_FLAG_ADDR : stm32l1xx_i2c.h
  • I2C_FLAG_AF : stm32l1xx_i2c.h
  • I2C_FLAG_ARLO : stm32l1xx_i2c.h
  • I2C_FLAG_BERR : stm32l1xx_i2c.h
  • I2C_FLAG_BTF : stm32l1xx_i2c.h
  • I2C_FLAG_BUSY : stm32l1xx_i2c.h
  • I2C_FLAG_DUALF : stm32l1xx_i2c.h
  • I2C_FLAG_GENCALL : stm32l1xx_i2c.h
  • I2C_FLAG_MSL : stm32l1xx_i2c.h
  • I2C_FLAG_OVR : stm32l1xx_i2c.h
  • I2C_FLAG_PECERR : stm32l1xx_i2c.h
  • I2C_FLAG_RXNE : stm32l1xx_i2c.h
  • I2C_FLAG_SB : stm32l1xx_i2c.h
  • I2C_FLAG_SMBALERT : stm32l1xx_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32l1xx_i2c.h
  • I2C_FLAG_SMBHOST : stm32l1xx_i2c.h
  • I2C_FLAG_STOPF : stm32l1xx_i2c.h
  • I2C_FLAG_TIMEOUT : stm32l1xx_i2c.h
  • I2C_FLAG_TRA : stm32l1xx_i2c.h
  • I2C_FLAG_TXE : stm32l1xx_i2c.h
  • I2C_GeneralCallCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GenerateSTART() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GenerateSTOP() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetFlagStatus() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetITStatus() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetLastEvent() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetPEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Init() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_IT_ADD10 : stm32l1xx_i2c.h
  • I2C_IT_ADDR : stm32l1xx_i2c.h
  • I2C_IT_AF : stm32l1xx_i2c.h
  • I2C_IT_ARLO : stm32l1xx_i2c.h
  • I2C_IT_BERR : stm32l1xx_i2c.h
  • I2C_IT_BTF : stm32l1xx_i2c.h
  • I2C_IT_BUF : stm32l1xx_i2c.h
  • I2C_IT_ERR : stm32l1xx_i2c.h
  • I2C_IT_EVT : stm32l1xx_i2c.h
  • I2C_IT_OVR : stm32l1xx_i2c.h
  • I2C_IT_PECERR : stm32l1xx_i2c.h
  • I2C_IT_RXNE : stm32l1xx_i2c.h
  • I2C_IT_SB : stm32l1xx_i2c.h
  • I2C_IT_SMBALERT : stm32l1xx_i2c.h
  • I2C_IT_STOPF : stm32l1xx_i2c.h
  • I2C_IT_TIMEOUT : stm32l1xx_i2c.h
  • I2C_IT_TXE : stm32l1xx_i2c.h
  • I2C_ITConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Mode_I2C : stm32l1xx_i2c.h
  • I2C_Mode_SMBusDevice : stm32l1xx_i2c.h
  • I2C_Mode_SMBusHost : stm32l1xx_i2c.h
  • I2C_NACKPosition_Current : stm32l1xx_i2c.h
  • I2C_NACKPosition_Next : stm32l1xx_i2c.h
  • I2C_NACKPositionConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_OAR1_ADD0 : stm32l1xx.h
  • I2C_OAR1_ADD1 : stm32l1xx.h
  • I2C_OAR1_ADD1_7 : stm32l1xx.h
  • I2C_OAR1_ADD2 : stm32l1xx.h
  • I2C_OAR1_ADD3 : stm32l1xx.h
  • I2C_OAR1_ADD4 : stm32l1xx.h
  • I2C_OAR1_ADD5 : stm32l1xx.h
  • I2C_OAR1_ADD6 : stm32l1xx.h
  • I2C_OAR1_ADD7 : stm32l1xx.h
  • I2C_OAR1_ADD8 : stm32l1xx.h
  • I2C_OAR1_ADD8_9 : stm32l1xx.h
  • I2C_OAR1_ADD9 : stm32l1xx.h
  • I2C_OAR1_ADDMODE : stm32l1xx.h
  • I2C_OAR2_ADD2 : stm32l1xx.h
  • I2C_OAR2_ENDUAL : stm32l1xx.h
  • I2C_OwnAddress2Config() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_PECPosition_Current : stm32l1xx_i2c.h
  • I2C_PECPosition_Next : stm32l1xx_i2c.h
  • I2C_PECPositionConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ReadRegister() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ReceiveData() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Register_CCR : stm32l1xx_i2c.h
  • I2C_Register_CR1 : stm32l1xx_i2c.h
  • I2C_Register_CR2 : stm32l1xx_i2c.h
  • I2C_Register_DR : stm32l1xx_i2c.h
  • I2C_Register_OAR1 : stm32l1xx_i2c.h
  • I2C_Register_OAR2 : stm32l1xx_i2c.h
  • I2C_Register_SR1 : stm32l1xx_i2c.h
  • I2C_Register_SR2 : stm32l1xx_i2c.h
  • I2C_Register_TRISE : stm32l1xx_i2c.h
  • I2C_Send7bitAddress() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SendData() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SMBusAlert_High : stm32l1xx_i2c.h
  • I2C_SMBusAlert_Low : stm32l1xx_i2c.h
  • I2C_SMBusAlertConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SoftwareResetCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SR1_ADD10 : stm32l1xx.h
  • I2C_SR1_ADDR : stm32l1xx.h
  • I2C_SR1_AF : stm32l1xx.h
  • I2C_SR1_ARLO : stm32l1xx.h
  • I2C_SR1_BERR : stm32l1xx.h
  • I2C_SR1_BTF : stm32l1xx.h
  • I2C_SR1_OVR : stm32l1xx.h
  • I2C_SR1_PECERR : stm32l1xx.h
  • I2C_SR1_RXNE : stm32l1xx.h
  • I2C_SR1_SB : stm32l1xx.h
  • I2C_SR1_SMBALERT : stm32l1xx.h
  • I2C_SR1_STOPF : stm32l1xx.h
  • I2C_SR1_TIMEOUT : stm32l1xx.h
  • I2C_SR1_TXE : stm32l1xx.h
  • I2C_SR2_BUSY : stm32l1xx.h
  • I2C_SR2_DUALF : stm32l1xx.h
  • I2C_SR2_GENCALL : stm32l1xx.h
  • I2C_SR2_MSL : stm32l1xx.h
  • I2C_SR2_PEC : stm32l1xx.h
  • I2C_SR2_SMBDEFAULT : stm32l1xx.h
  • I2C_SR2_SMBHOST : stm32l1xx.h
  • I2C_SR2_TRA : stm32l1xx.h
  • I2C_StretchClockCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_StructInit() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_TransmitPEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_TRISE_TRISE : stm32l1xx.h
  • I2S_AudioFreq_11k : stm32l1xx_spi.h
  • I2S_AudioFreq_16k : stm32l1xx_spi.h
  • I2S_AudioFreq_192k : stm32l1xx_spi.h
  • I2S_AudioFreq_22k : stm32l1xx_spi.h
  • I2S_AudioFreq_32k : stm32l1xx_spi.h
  • I2S_AudioFreq_44k : stm32l1xx_spi.h
  • I2S_AudioFreq_48k : stm32l1xx_spi.h
  • I2S_AudioFreq_8k : stm32l1xx_spi.h
  • I2S_AudioFreq_96k : stm32l1xx_spi.h
  • I2S_AudioFreq_Default : stm32l1xx_spi.h
  • I2S_Cmd() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • I2S_CPOL_High : stm32l1xx_spi.h
  • I2S_CPOL_Low : stm32l1xx_spi.h
  • I2S_DataFormat_16b : stm32l1xx_spi.h
  • I2S_DataFormat_16bextended : stm32l1xx_spi.h
  • I2S_DataFormat_24b : stm32l1xx_spi.h
  • I2S_DataFormat_32b : stm32l1xx_spi.h
  • I2S_FLAG_CHSIDE : stm32l1xx_spi.h
  • I2S_FLAG_UDR : stm32l1xx_spi.h
  • I2S_Init() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • I2S_IT_UDR : stm32l1xx_spi.h
  • I2S_MCLKOutput_Disable : stm32l1xx_spi.h
  • I2S_MCLKOutput_Enable : stm32l1xx_spi.h
  • I2S_Mode_MasterRx : stm32l1xx_spi.h
  • I2S_Mode_MasterTx : stm32l1xx_spi.h
  • I2S_Mode_SlaveRx : stm32l1xx_spi.h
  • I2S_Mode_SlaveTx : stm32l1xx_spi.h
  • I2S_Standard_LSB : stm32l1xx_spi.h
  • I2S_Standard_MSB : stm32l1xx_spi.h
  • I2S_Standard_PCMLong : stm32l1xx_spi.h
  • I2S_Standard_PCMShort : stm32l1xx_spi.h
  • I2S_Standard_Phillips : stm32l1xx_spi.h
  • I2S_StructInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • I2SCFGR_CLEAR_Mask : stm32l1xx_spi.c
  • IC_ROUTING_MASK : stm32l1xx_syscfg.c
  • ICSCR_BYTE4_ADDRESS : stm32l1xx_rcc.c
  • IDCODE_DEVID_MASK : stm32l1xx_dbgmcu.c
  • INITMODE_TIMEOUT : stm32l1xx_rtc.c
  • IRQn : stm32l1xx.h
  • IRQn_Type : stm32l1xx.h
  • IS_ADC_ALL_PERIPH : stm32l1xx_adc.h
  • IS_ADC_ANALOG_WATCHDOG : stm32l1xx_adc.h
  • IS_ADC_BANK : stm32l1xx_adc.h
  • IS_ADC_CHANNEL : stm32l1xx_adc.h
  • IS_ADC_CLEAR_FLAG : stm32l1xx_adc.h
  • IS_ADC_DATA_ALIGN : stm32l1xx_adc.h
  • IS_ADC_DELAY_LENGTH : stm32l1xx_adc.h
  • IS_ADC_DMA_PERIPH : stm32l1xx_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32l1xx_adc.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32l1xx_adc.h
  • IS_ADC_EXT_TRIG : stm32l1xx_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32l1xx_adc.h
  • IS_ADC_GET_FLAG : stm32l1xx_adc.h
  • IS_ADC_INJECTED_CHANNEL : stm32l1xx_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32l1xx_adc.h
  • IS_ADC_INJECTED_RANK : stm32l1xx_adc.h
  • IS_ADC_IT : stm32l1xx_adc.h
  • IS_ADC_OFFSET : stm32l1xx_adc.h
  • IS_ADC_POWER_DOWN : stm32l1xx_adc.h
  • IS_ADC_PRESCALER : stm32l1xx_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32l1xx_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32l1xx_adc.h
  • IS_ADC_REGULAR_RANK : stm32l1xx_adc.h
  • IS_ADC_RESOLUTION : stm32l1xx_adc.h
  • IS_ADC_SAMPLE_TIME : stm32l1xx_adc.h
  • IS_ADC_THRESHOLD : stm32l1xx_adc.h
  • IS_AES_CHAINING : stm32l1xx_aes.h
  • IS_AES_DATATYPE : stm32l1xx_aes.h
  • IS_AES_DMA_TRANSFER : stm32l1xx_aes.h
  • IS_AES_FLAG : stm32l1xx_aes.h
  • IS_AES_GET_IT : stm32l1xx_aes.h
  • IS_AES_IT : stm32l1xx_aes.h
  • IS_AES_MODE : stm32l1xx_aes.h
  • IS_ALARM_MASK : stm32l1xx_rtc.h
  • IS_COMP_ALL_PERIPH : stm32l1xx_comp.h
  • IS_COMP_INVERTING_INPUT : stm32l1xx_comp.h
  • IS_COMP_OUTPUT : stm32l1xx_comp.h
  • IS_COMP_SPEED : stm32l1xx_comp.h
  • IS_DAC_ALIGN : stm32l1xx_dac.h
  • IS_DAC_CHANNEL : stm32l1xx_dac.h
  • IS_DAC_DATA : stm32l1xx_dac.h
  • IS_DAC_FLAG : stm32l1xx_dac.h
  • IS_DAC_GENERATE_WAVE : stm32l1xx_dac.h
  • IS_DAC_IT : stm32l1xx_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32l1xx_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32l1xx_dac.h
  • IS_DAC_TRIGGER : stm32l1xx_dac.h
  • IS_DAC_WAVE : stm32l1xx_dac.h
  • IS_DBGMCU_APB1PERIPH : stm32l1xx_dbgmcu.h
  • IS_DBGMCU_APB2PERIPH : stm32l1xx_dbgmcu.h
  • IS_DBGMCU_PERIPH : stm32l1xx_dbgmcu.h
  • IS_DMA_ALL_PERIPH : stm32l1xx_dma.h
  • IS_DMA_BUFFER_SIZE : stm32l1xx_dma.h
  • IS_DMA_CLEAR_FLAG : stm32l1xx_dma.h
  • IS_DMA_CLEAR_IT : stm32l1xx_dma.h
  • IS_DMA_CONFIG_IT : stm32l1xx_dma.h
  • IS_DMA_DIR : stm32l1xx_dma.h
  • IS_DMA_GET_FLAG : stm32l1xx_dma.h
  • IS_DMA_GET_IT : stm32l1xx_dma.h
  • IS_DMA_M2M_STATE : stm32l1xx_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32l1xx_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32l1xx_dma.h
  • IS_DMA_MODE : stm32l1xx_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32l1xx_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32l1xx_dma.h
  • IS_DMA_PRIORITY : stm32l1xx_dma.h
  • IS_EXTI_LINE : stm32l1xx_exti.h
  • IS_EXTI_MODE : stm32l1xx_exti.h
  • IS_EXTI_PIN_SOURCE : stm32l1xx_syscfg.h
  • IS_EXTI_PORT_SOURCE : stm32l1xx_syscfg.h
  • IS_EXTI_TRIGGER : stm32l1xx_exti.h
  • IS_FLASH_CLEAR_FLAG : stm32l1xx_flash.h
  • IS_FLASH_DATA_ADDRESS : stm32l1xx_flash.h
  • IS_FLASH_GET_FLAG : stm32l1xx_flash.h
  • IS_FLASH_IT : stm32l1xx_flash.h
  • IS_FLASH_LATENCY : stm32l1xx_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32l1xx_flash.h
  • IS_FSMC_ACCESS_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_ADDRESS_HOLD_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_ADDRESS_SETUP_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_ASYNWAIT : stm32l1xx_fsmc.h
  • IS_FSMC_BURSTMODE : stm32l1xx_fsmc.h
  • IS_FSMC_CLK_DIV : stm32l1xx_fsmc.h
  • IS_FSMC_DATA_LATENCY : stm32l1xx_fsmc.h
  • IS_FSMC_DATASETUP_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_EXTENDED_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_MEMORY : stm32l1xx_fsmc.h
  • IS_FSMC_MEMORY_WIDTH : stm32l1xx_fsmc.h
  • IS_FSMC_MUX : stm32l1xx_fsmc.h
  • IS_FSMC_NORSRAM_BANK : stm32l1xx_fsmc.h
  • IS_FSMC_TURNAROUND_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_WAIT_POLARITY : stm32l1xx_fsmc.h
  • IS_FSMC_WAIT_SIGNAL_ACTIVE : stm32l1xx_fsmc.h
  • IS_FSMC_WAITE_SIGNAL : stm32l1xx_fsmc.h
  • IS_FSMC_WRAP_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_WRITE_BURST : stm32l1xx_fsmc.h
  • IS_FSMC_WRITE_OPERATION : stm32l1xx_fsmc.h
  • IS_FUNCTIONAL_STATE : stm32l1xx.h
  • IS_GET_EXTI_LINE : stm32l1xx_exti.h
  • IS_GET_GPIO_PIN : stm32l1xx_gpio.h
  • IS_GPIO_AF : stm32l1xx_gpio.h
  • IS_GPIO_ALL_PERIPH : stm32l1xx_gpio.h
  • IS_GPIO_BIT_ACTION : stm32l1xx_gpio.h
  • IS_GPIO_MODE : stm32l1xx_gpio.h
  • IS_GPIO_OTYPE : stm32l1xx_gpio.h
  • IS_GPIO_PIN : stm32l1xx_gpio.h
  • IS_GPIO_PIN_SOURCE : stm32l1xx_gpio.h
  • IS_GPIO_PUPD : stm32l1xx_gpio.h
  • IS_GPIO_SPEED : stm32l1xx_gpio.h
  • IS_I2C_ACK_STATE : stm32l1xx_i2c.h
  • IS_I2C_ACKNOWLEDGE_ADDRESS : stm32l1xx_i2c.h
  • IS_I2C_ALL_PERIPH : stm32l1xx_i2c.h
  • IS_I2C_CLEAR_FLAG : stm32l1xx_i2c.h
  • IS_I2C_CLEAR_IT : stm32l1xx_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32l1xx_i2c.h
  • IS_I2C_CONFIG_IT : stm32l1xx_i2c.h
  • IS_I2C_DIRECTION : stm32l1xx_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32l1xx_i2c.h
  • IS_I2C_EVENT : stm32l1xx_i2c.h
  • IS_I2C_GET_FLAG : stm32l1xx_i2c.h
  • IS_I2C_GET_IT : stm32l1xx_i2c.h
  • IS_I2C_MODE : stm32l1xx_i2c.h
  • IS_I2C_NACK_POSITION : stm32l1xx_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32l1xx_i2c.h
  • IS_I2C_PEC_POSITION : stm32l1xx_i2c.h
  • IS_I2C_REGISTER : stm32l1xx_i2c.h
  • IS_I2C_SMBUS_ALERT : stm32l1xx_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32l1xx_spi.h
  • IS_I2S_CPOL : stm32l1xx_spi.h
  • IS_I2S_DATA_FORMAT : stm32l1xx_spi.h
  • IS_I2S_MCLK_OUTPUT : stm32l1xx_spi.h
  • IS_I2S_MODE : stm32l1xx_spi.h
  • IS_I2S_STANDARD : stm32l1xx_spi.h
  • IS_IWDG_FLAG : stm32l1xx_iwdg.h
  • IS_IWDG_PRESCALER : stm32l1xx_iwdg.h
  • IS_IWDG_RELOAD : stm32l1xx_iwdg.h
  • IS_IWDG_WRITE_ACCESS : stm32l1xx_iwdg.h
  • IS_LCD_BIAS : stm32l1xx_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32l1xx_lcd.h
  • IS_LCD_BLINK_MODE : stm32l1xx_lcd.h
  • IS_LCD_CLEAR_FLAG : stm32l1xx_lcd.h
  • IS_LCD_CONTRAST : stm32l1xx_lcd.h
  • IS_LCD_DEAD_TIME : stm32l1xx_lcd.h
  • IS_LCD_DIVIDER : stm32l1xx_lcd.h
  • IS_LCD_DUTY : stm32l1xx_lcd.h
  • IS_LCD_GET_FLAG : stm32l1xx_lcd.h
  • IS_LCD_GET_IT : stm32l1xx_lcd.h
  • IS_LCD_IT : stm32l1xx_lcd.h
  • IS_LCD_PRESCALER : stm32l1xx_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32l1xx_lcd.h
  • IS_LCD_RAM_REGISTER : stm32l1xx_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32l1xx_lcd.h
  • IS_NVIC_LP : misc.h
  • IS_NVIC_OFFSET : misc.h
  • IS_NVIC_PREEMPTION_PRIORITY : misc.h
  • IS_NVIC_PRIORITY_GROUP : misc.h
  • IS_NVIC_SUB_PRIORITY : misc.h
  • IS_NVIC_VECTTAB : misc.h
  • IS_OB_BOOT_BANK : stm32l1xx_flash.h
  • IS_OB_BOR_LEVEL : stm32l1xx_flash.h
  • IS_OB_IWDG_SOURCE : stm32l1xx_flash.h
  • IS_OB_RDP : stm32l1xx_flash.h
  • IS_OB_STDBY_SOURCE : stm32l1xx_flash.h
  • IS_OB_STOP_SOURCE : stm32l1xx_flash.h
  • IS_OB_WRP : stm32l1xx_flash.h
  • IS_OPAMP_ALL_PERIPH : stm32l1xx_opamp.h
  • IS_OPAMP_INPUT : stm32l1xx_opamp.h
  • IS_OPAMP_RANGE : stm32l1xx_opamp.h
  • IS_OPAMP_SWITCH : stm32l1xx_opamp.h
  • IS_OPAMP_TRIMMING : stm32l1xx_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32l1xx_opamp.h
  • IS_PWR_CLEAR_FLAG : stm32l1xx_pwr.h
  • IS_PWR_GET_FLAG : stm32l1xx_pwr.h
  • IS_PWR_PVD_LEVEL : stm32l1xx_pwr.h
  • IS_PWR_REGULATOR : stm32l1xx_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32l1xx_pwr.h
  • IS_PWR_STOP_ENTRY : stm32l1xx_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32l1xx_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32l1xx_pwr.h
  • IS_RCC_AHB_LPMODE_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_AHB_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_APB1_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_APB2_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_CLEAR_IT : stm32l1xx_rcc.h
  • IS_RCC_FLAG : stm32l1xx_rcc.h
  • IS_RCC_GET_IT : stm32l1xx_rcc.h
  • IS_RCC_HCLK : stm32l1xx_rcc.h
  • IS_RCC_HSE : stm32l1xx_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32l1xx_rcc.h
  • IS_RCC_IT : stm32l1xx_rcc.h
  • IS_RCC_LSE : stm32l1xx_rcc.h
  • IS_RCC_MCO_DIV : stm32l1xx_rcc.h
  • IS_RCC_MCO_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_MSI_CALIBRATION_VALUE : stm32l1xx_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32l1xx_rcc.h
  • IS_RCC_PCLK : stm32l1xx_rcc.h
  • IS_RCC_PLL_DIV : stm32l1xx_rcc.h
  • IS_RCC_PLL_MUL : stm32l1xx_rcc.h
  • IS_RCC_PLL_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_RTCCLK_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_SYSCLK_SOURCE : stm32l1xx_rcc.h
  • IS_RI_CHANNEL : stm32l1xx_syscfg.h
  • IS_RI_CHANNELSPEED : stm32l1xx_syscfg.h
  • IS_RI_INPUTCAPTURE : stm32l1xx_syscfg.h
  • IS_RI_INPUTCAPTURE_ROUTING : stm32l1xx_syscfg.h
  • IS_RI_IOSWITCH : stm32l1xx_syscfg.h
  • IS_RI_PIN : stm32l1xx_syscfg.h
  • IS_RI_PORT : stm32l1xx_syscfg.h
  • IS_RI_RESISTOR : stm32l1xx_syscfg.h
  • IS_RI_TIM : stm32l1xx_syscfg.h
  • IS_RTC_ALARM : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32l1xx_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32l1xx_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32l1xx_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32l1xx_rtc.h
  • IS_RTC_BKP : stm32l1xx_rtc.h
  • IS_RTC_CALIB_OUTPUT : stm32l1xx_rtc.h
  • IS_RTC_CALIB_SIGN : stm32l1xx_rtc.h
  • IS_RTC_CALIB_VALUE : stm32l1xx_rtc.h
  • IS_RTC_CLEAR_FLAG : stm32l1xx_rtc.h
  • IS_RTC_CLEAR_IT : stm32l1xx_rtc.h
  • IS_RTC_CMD_ALARM : stm32l1xx_rtc.h
  • IS_RTC_CONFIG_IT : stm32l1xx_rtc.h
  • IS_RTC_DATE : stm32l1xx_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32l1xx_rtc.h
  • IS_RTC_FORMAT : stm32l1xx_rtc.h
  • IS_RTC_GET_FLAG : stm32l1xx_rtc.h
  • IS_RTC_GET_IT : stm32l1xx_rtc.h
  • IS_RTC_H12 : stm32l1xx_rtc.h
  • IS_RTC_HOUR12 : stm32l1xx_rtc.h
  • IS_RTC_HOUR24 : stm32l1xx_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32l1xx_rtc.h
  • IS_RTC_MINUTES : stm32l1xx_rtc.h
  • IS_RTC_MONTH : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT_POL : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32l1xx_rtc.h
  • IS_RTC_SECONDS : stm32l1xx_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32l1xx_rtc.h
  • IS_RTC_SHIFT_SUBFS : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32l1xx_rtc.h
  • IS_RTC_STORE_OPERATION : stm32l1xx_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32l1xx_rtc.h
  • IS_RTC_TAMPER : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_FILTER : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_TRIGGER : stm32l1xx_rtc.h
  • IS_RTC_TIMESTAMP_EDGE : stm32l1xx_rtc.h
  • IS_RTC_WAKEUP_CLOCK : stm32l1xx_rtc.h
  • IS_RTC_WAKEUP_COUNTER : stm32l1xx_rtc.h
  • IS_RTC_WEEKDAY : stm32l1xx_rtc.h
  • IS_RTC_YEAR : stm32l1xx_rtc.h
  • IS_SDIO_BLOCK_SIZE : stm32l1xx_sdio.h
  • IS_SDIO_BUS_WIDE : stm32l1xx_sdio.h
  • IS_SDIO_CLEAR_FLAG : stm32l1xx_sdio.h
  • IS_SDIO_CLEAR_IT : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_BYPASS : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_EDGE : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_POWER_SAVE : stm32l1xx_sdio.h
  • IS_SDIO_CMD_INDEX : stm32l1xx_sdio.h
  • IS_SDIO_CPSM : stm32l1xx_sdio.h
  • IS_SDIO_DATA_LENGTH : stm32l1xx_sdio.h
  • IS_SDIO_DPSM : stm32l1xx_sdio.h
  • IS_SDIO_FLAG : stm32l1xx_sdio.h
  • IS_SDIO_GET_IT : stm32l1xx_sdio.h
  • IS_SDIO_HARDWARE_FLOW_CONTROL : stm32l1xx_sdio.h
  • IS_SDIO_IT : stm32l1xx_sdio.h
  • IS_SDIO_POWER_STATE : stm32l1xx_sdio.h
  • IS_SDIO_READWAIT_MODE : stm32l1xx_sdio.h
  • IS_SDIO_RESP : stm32l1xx_sdio.h
  • IS_SDIO_RESPONSE : stm32l1xx_sdio.h
  • IS_SDIO_TRANSFER_DIR : stm32l1xx_sdio.h
  • IS_SDIO_TRANSFER_MODE : stm32l1xx_sdio.h
  • IS_SDIO_WAIT : stm32l1xx_sdio.h
  • IS_SPI_23_PERIPH : stm32l1xx_spi.h
  • IS_SPI_ALL_PERIPH : stm32l1xx_spi.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32l1xx_spi.h
  • IS_SPI_CPHA : stm32l1xx_spi.h
  • IS_SPI_CPOL : stm32l1xx_spi.h
  • IS_SPI_CRC : stm32l1xx_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32l1xx_spi.h
  • IS_SPI_DATASIZE : stm32l1xx_spi.h
  • IS_SPI_DIRECTION : stm32l1xx_spi.h
  • IS_SPI_DIRECTION_MODE : stm32l1xx_spi.h
  • IS_SPI_FIRST_BIT : stm32l1xx_spi.h
  • IS_SPI_I2S_CLEAR_FLAG : stm32l1xx_spi.h
  • IS_SPI_I2S_CLEAR_IT : stm32l1xx_spi.h
  • IS_SPI_I2S_CONFIG_IT : stm32l1xx_spi.h
  • IS_SPI_I2S_DMAREQ : stm32l1xx_spi.h
  • IS_SPI_I2S_GET_FLAG : stm32l1xx_spi.h
  • IS_SPI_I2S_GET_IT : stm32l1xx_spi.h
  • IS_SPI_MODE : stm32l1xx_spi.h
  • IS_SPI_NSS : stm32l1xx_spi.h
  • IS_SPI_NSS_INTERNAL : stm32l1xx_spi.h
  • IS_SYSCFG_MEMORY_REMAP_CONFING : stm32l1xx_syscfg.h
  • IS_SYSTICK_CLK_SOURCE : misc.h
  • IS_TIM_ALL_PERIPH : stm32l1xx_tim.h
  • IS_TIM_CCX : stm32l1xx_tim.h
  • IS_TIM_CHANNEL : stm32l1xx_tim.h
  • IS_TIM_CKD_DIV : stm32l1xx_tim.h
  • IS_TIM_CLEAR_FLAG : stm32l1xx_tim.h
  • IS_TIM_COUNTER_MODE : stm32l1xx_tim.h
  • IS_TIM_DMA_BASE : stm32l1xx_tim.h
  • IS_TIM_DMA_LENGTH : stm32l1xx_tim.h
  • IS_TIM_DMA_SOURCE : stm32l1xx_tim.h
  • IS_TIM_ENCODER_MODE : stm32l1xx_tim.h
  • IS_TIM_EVENT_SOURCE : stm32l1xx_tim.h
  • IS_TIM_EXT_FILTER : stm32l1xx_tim.h
  • IS_TIM_EXT_POLARITY : stm32l1xx_tim.h
  • IS_TIM_EXT_PRESCALER : stm32l1xx_tim.h
  • IS_TIM_FORCED_ACTION : stm32l1xx_tim.h
  • IS_TIM_GET_FLAG : stm32l1xx_tim.h
  • IS_TIM_GET_IT : stm32l1xx_tim.h
  • IS_TIM_IC_FILTER : stm32l1xx_tim.h
  • IS_TIM_IC_POLARITY : stm32l1xx_tim.h
  • IS_TIM_IC_PRESCALER : stm32l1xx_tim.h
  • IS_TIM_IC_SELECTION : stm32l1xx_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32l1xx_tim.h
  • IS_TIM_IT : stm32l1xx_tim.h
  • IS_TIM_LIST1_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST2_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST3_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST4_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST5_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST6_PERIPH : stm32l1xx_tim.h
  • IS_TIM_MSM_STATE : stm32l1xx_tim.h
  • IS_TIM_OC_MODE : stm32l1xx_tim.h
  • IS_TIM_OC_POLARITY : stm32l1xx_tim.h
  • IS_TIM_OCCLEAR_STATE : stm32l1xx_tim.h
  • IS_TIM_OCFAST_STATE : stm32l1xx_tim.h
  • IS_TIM_OCM : stm32l1xx_tim.h
  • IS_TIM_OCPRELOAD_STATE : stm32l1xx_tim.h
  • IS_TIM_OPM_MODE : stm32l1xx_tim.h
  • IS_TIM_OUTPUT_STATE : stm32l1xx_tim.h
  • IS_TIM_PRESCALER_RELOAD : stm32l1xx_tim.h
  • IS_TIM_PWMI_CHANNEL : stm32l1xx_tim.h
  • IS_TIM_REMAP : stm32l1xx_tim.h
  • IS_TIM_SLAVE_MODE : stm32l1xx_tim.h
  • IS_TIM_TRGO_SOURCE : stm32l1xx_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32l1xx_tim.h
  • IS_TIM_UPDATE_SOURCE : stm32l1xx_tim.h
  • IS_USART_123_PERIPH : stm32l1xx_usart.h
  • IS_USART_ADDRESS : stm32l1xx_usart.h
  • IS_USART_ALL_PERIPH : stm32l1xx_usart.h
  • IS_USART_BAUDRATE : stm32l1xx_usart.h
  • IS_USART_CLEAR_FLAG : stm32l1xx_usart.h
  • IS_USART_CLEAR_IT : stm32l1xx_usart.h
  • IS_USART_CLOCK : stm32l1xx_usart.h
  • IS_USART_CONFIG_IT : stm32l1xx_usart.h
  • IS_USART_CPHA : stm32l1xx_usart.h
  • IS_USART_CPOL : stm32l1xx_usart.h
  • IS_USART_DATA : stm32l1xx_usart.h
  • IS_USART_DMAREQ : stm32l1xx_usart.h
  • IS_USART_FLAG : stm32l1xx_usart.h
  • IS_USART_GET_IT : stm32l1xx_usart.h
  • IS_USART_HARDWARE_FLOW_CONTROL : stm32l1xx_usart.h
  • IS_USART_IRDA_MODE : stm32l1xx_usart.h
  • IS_USART_LASTBIT : stm32l1xx_usart.h
  • IS_USART_LIN_BREAK_DETECT_LENGTH : stm32l1xx_usart.h
  • IS_USART_MODE : stm32l1xx_usart.h
  • IS_USART_PARITY : stm32l1xx_usart.h
  • IS_USART_STOPBITS : stm32l1xx_usart.h
  • IS_USART_WAKEUP : stm32l1xx_usart.h
  • IS_USART_WORD_LENGTH : stm32l1xx_usart.h
  • IS_WWDG_COUNTER : stm32l1xx_wwdg.h
  • IS_WWDG_PRESCALER : stm32l1xx_wwdg.h
  • IS_WWDG_WINDOW_VALUE : stm32l1xx_wwdg.h
  • IT_MASK : stm32l1xx_usart.c
  • ITEN_MASK : stm32l1xx_i2c.c
  • ITStatus : stm32l1xx.h
  • IWDG : stm32l1xx.h
  • IWDG_BASE : stm32l1xx.h
  • IWDG_Enable() : stm32l1xx_iwdg.h , stm32l1xx_iwdg.c
  • IWDG_FLAG_PVU : stm32l1xx_iwdg.h
  • IWDG_FLAG_RVU : stm32l1xx_iwdg.h
  • IWDG_GetFlagStatus() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_KR_KEY : stm32l1xx.h
  • IWDG_PR_PR : stm32l1xx.h
  • IWDG_PR_PR_0 : stm32l1xx.h
  • IWDG_PR_PR_1 : stm32l1xx.h
  • IWDG_PR_PR_2 : stm32l1xx.h
  • IWDG_Prescaler_128 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_16 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_256 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_32 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_4 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_64 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_8 : stm32l1xx_iwdg.h
  • IWDG_ReloadCounter() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_RLR_RL : stm32l1xx.h
  • IWDG_SetPrescaler() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_SetReload() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_SR_PVU : stm32l1xx.h
  • IWDG_SR_RVU : stm32l1xx.h
  • IWDG_WriteAccess_Disable : stm32l1xx_iwdg.h
  • IWDG_WriteAccess_Enable : stm32l1xx_iwdg.h
  • IWDG_WriteAccessCmd() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PendSV_IRQn : stm32l1xx.h
  • PERIPH_BASE : stm32l1xx.h
  • PERIPH_BB_BASE : stm32l1xx.h
  • PLLMulTable : system_stm32l1xx.c , stm32l1xx_rcc.c
  • PLLON_BitNumber : stm32l1xx_rcc.c
  • PON_MASK : stm32l1xx_lcd.c
  • PVD_IRQn : stm32l1xx.h
  • PVDE_BitNumber : stm32l1xx_pwr.c
  • PWR : stm32l1xx.h
  • PWR_BASE : stm32l1xx.h
  • PWR_ClearFlag() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_CR_CSBF : stm32l1xx.h
  • PWR_CR_CWUF : stm32l1xx.h
  • PWR_CR_DBP : stm32l1xx.h
  • PWR_CR_FWU : stm32l1xx.h
  • PWR_CR_LPRUN : stm32l1xx.h
  • PWR_CR_LPSDSR : stm32l1xx.h
  • PWR_CR_PDDS : stm32l1xx.h
  • PWR_CR_PLS : stm32l1xx.h
  • PWR_CR_PLS_0 : stm32l1xx.h
  • PWR_CR_PLS_1 : stm32l1xx.h
  • PWR_CR_PLS_2 : stm32l1xx.h
  • PWR_CR_PLS_LEV0 : stm32l1xx.h
  • PWR_CR_PLS_LEV1 : stm32l1xx.h
  • PWR_CR_PLS_LEV2 : stm32l1xx.h
  • PWR_CR_PLS_LEV3 : stm32l1xx.h
  • PWR_CR_PLS_LEV4 : stm32l1xx.h
  • PWR_CR_PLS_LEV5 : stm32l1xx.h
  • PWR_CR_PLS_LEV6 : stm32l1xx.h
  • PWR_CR_PLS_LEV7 : stm32l1xx.h
  • PWR_CR_PVDE : stm32l1xx.h
  • PWR_CR_ULP : stm32l1xx.h
  • PWR_CR_VOS : stm32l1xx.h
  • PWR_CR_VOS_0 : stm32l1xx.h
  • PWR_CR_VOS_1 : stm32l1xx.h
  • PWR_CSR_EWUP1 : stm32l1xx.h
  • PWR_CSR_EWUP2 : stm32l1xx.h
  • PWR_CSR_EWUP3 : stm32l1xx.h
  • PWR_CSR_PVDO : stm32l1xx.h
  • PWR_CSR_REGLPF : stm32l1xx.h
  • PWR_CSR_SBF : stm32l1xx.h
  • PWR_CSR_VOSF : stm32l1xx.h
  • PWR_CSR_VREFINTRDYF : stm32l1xx.h
  • PWR_CSR_WUF : stm32l1xx.h
  • PWR_DeInit() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterLowPowerRunMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterSleepMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterSTANDBYMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterSTOPMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_FastWakeUpCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_FLAG_PVDO : stm32l1xx_pwr.h
  • PWR_FLAG_REGLP : stm32l1xx_pwr.h
  • PWR_FLAG_SB : stm32l1xx_pwr.h
  • PWR_FLAG_VOS : stm32l1xx_pwr.h
  • PWR_FLAG_VREFINTRDY : stm32l1xx_pwr.h
  • PWR_FLAG_WU : stm32l1xx_pwr.h
  • PWR_GetFlagStatus() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_OFFSET : stm32l1xx_pwr.c
  • PWR_PVDCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_PVDLevel_0 : stm32l1xx_pwr.h
  • PWR_PVDLevel_1 : stm32l1xx_pwr.h
  • PWR_PVDLevel_2 : stm32l1xx_pwr.h
  • PWR_PVDLevel_3 : stm32l1xx_pwr.h
  • PWR_PVDLevel_4 : stm32l1xx_pwr.h
  • PWR_PVDLevel_5 : stm32l1xx_pwr.h
  • PWR_PVDLevel_6 : stm32l1xx_pwr.h
  • PWR_PVDLevel_7 : stm32l1xx_pwr.h
  • PWR_PVDLevelConfig() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_PWRCTRL_MASK : stm32l1xx_sdio.c
  • PWR_Regulator_LowPower : stm32l1xx_pwr.h
  • PWR_Regulator_ON : stm32l1xx_pwr.h
  • PWR_RTCAccessCmd() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_SLEEPEntry_WFE : stm32l1xx_pwr.h
  • PWR_SLEEPEntry_WFI : stm32l1xx_pwr.h
  • PWR_STOPEntry_WFE : stm32l1xx_pwr.h
  • PWR_STOPEntry_WFI : stm32l1xx_pwr.h
  • PWR_UltraLowPowerCmd() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range1 : stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range2 : stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range3 : stm32l1xx_pwr.h
  • PWR_VoltageScalingConfig() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_WakeUpPin_1 : stm32l1xx_pwr.h
  • PWR_WakeUpPin_2 : stm32l1xx_pwr.h
  • PWR_WakeUpPin_3 : stm32l1xx_pwr.h
  • PWR_WakeUpPinCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC : stm32l1xx.h
  • RCC_AdjustHSICalibrationValue() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AdjustMSICalibrationValue() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AHBENR_AESEN : stm32l1xx.h
  • RCC_AHBENR_CRCEN : stm32l1xx.h
  • RCC_AHBENR_DMA1EN : stm32l1xx.h
  • RCC_AHBENR_DMA2EN : stm32l1xx.h
  • RCC_AHBENR_FLITFEN : stm32l1xx.h
  • RCC_AHBENR_FSMCEN : stm32l1xx.h
  • RCC_AHBENR_GPIOAEN : stm32l1xx.h
  • RCC_AHBENR_GPIOBEN : stm32l1xx.h
  • RCC_AHBENR_GPIOCEN : stm32l1xx.h
  • RCC_AHBENR_GPIODEN : stm32l1xx.h
  • RCC_AHBENR_GPIOEEN : stm32l1xx.h
  • RCC_AHBENR_GPIOFEN : stm32l1xx.h
  • RCC_AHBENR_GPIOGEN : stm32l1xx.h
  • RCC_AHBENR_GPIOHEN : stm32l1xx.h
  • RCC_AHBLPENR_AESLPEN : stm32l1xx.h
  • RCC_AHBLPENR_CRCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_DMA1LPEN : stm32l1xx.h
  • RCC_AHBLPENR_DMA2LPEN : stm32l1xx.h
  • RCC_AHBLPENR_FLITFLPEN : stm32l1xx.h
  • RCC_AHBLPENR_FSMCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOALPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOBLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIODLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOELPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOFLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOGLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOHLPEN : stm32l1xx.h
  • RCC_AHBLPENR_SRAMLPEN : stm32l1xx.h
  • RCC_AHBPeriph_AES : stm32l1xx_rcc.h
  • RCC_AHBPeriph_CRC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_DMA1 : stm32l1xx_rcc.h
  • RCC_AHBPeriph_DMA2 : stm32l1xx_rcc.h
  • RCC_AHBPeriph_FLITF : stm32l1xx_rcc.h
  • RCC_AHBPeriph_FSMC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOA : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOB : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOD : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOE : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOF : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOG : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOH : stm32l1xx_rcc.h
  • RCC_AHBPeriph_SRAM : stm32l1xx_rcc.h
  • RCC_AHBPeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AHBPeriphClockLPModeCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AHBPeriphResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AHBRSTR_AESRST : stm32l1xx.h
  • RCC_AHBRSTR_CRCRST : stm32l1xx.h
  • RCC_AHBRSTR_DMA1RST : stm32l1xx.h
  • RCC_AHBRSTR_DMA2RST : stm32l1xx.h
  • RCC_AHBRSTR_FLITFRST : stm32l1xx.h
  • RCC_AHBRSTR_FSMCRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOARST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOBRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOCRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIODRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOERST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOFRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOGRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOHRST : stm32l1xx.h
  • RCC_APB1ENR_COMPEN : stm32l1xx.h
  • RCC_APB1ENR_DACEN : stm32l1xx.h
  • RCC_APB1ENR_I2C1EN : stm32l1xx.h
  • RCC_APB1ENR_I2C2EN : stm32l1xx.h
  • RCC_APB1ENR_LCDEN : stm32l1xx.h
  • RCC_APB1ENR_PWREN : stm32l1xx.h
  • RCC_APB1ENR_SPI2EN : stm32l1xx.h
  • RCC_APB1ENR_SPI3EN : stm32l1xx.h
  • RCC_APB1ENR_TIM2EN : stm32l1xx.h
  • RCC_APB1ENR_TIM3EN : stm32l1xx.h
  • RCC_APB1ENR_TIM4EN : stm32l1xx.h
  • RCC_APB1ENR_TIM5EN : stm32l1xx.h
  • RCC_APB1ENR_TIM6EN : stm32l1xx.h
  • RCC_APB1ENR_TIM7EN : stm32l1xx.h
  • RCC_APB1ENR_UART4EN : stm32l1xx.h
  • RCC_APB1ENR_UART5EN : stm32l1xx.h
  • RCC_APB1ENR_USART2EN : stm32l1xx.h
  • RCC_APB1ENR_USART3EN : stm32l1xx.h
  • RCC_APB1ENR_USBEN : stm32l1xx.h
  • RCC_APB1ENR_WWDGEN : stm32l1xx.h
  • RCC_APB1LPENR_COMPLPEN : stm32l1xx.h
  • RCC_APB1LPENR_DACLPEN : stm32l1xx.h
  • RCC_APB1LPENR_I2C1LPEN : stm32l1xx.h
  • RCC_APB1LPENR_I2C2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_LCDLPEN : stm32l1xx.h
  • RCC_APB1LPENR_PWRLPEN : stm32l1xx.h
  • RCC_APB1LPENR_SPI2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_SPI3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM4LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM5LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM6LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM7LPEN : stm32l1xx.h
  • RCC_APB1LPENR_UART4LPEN : stm32l1xx.h
  • RCC_APB1LPENR_UART5LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USART2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USART3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USBLPEN : stm32l1xx.h
  • RCC_APB1LPENR_WWDGLPEN : stm32l1xx.h
  • RCC_APB1Periph_COMP : stm32l1xx_rcc.h
  • RCC_APB1Periph_DAC : stm32l1xx_rcc.h
  • RCC_APB1Periph_I2C1 : stm32l1xx_rcc.h
  • RCC_APB1Periph_I2C2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_LCD : stm32l1xx_rcc.h
  • RCC_APB1Periph_PWR : stm32l1xx_rcc.h
  • RCC_APB1Periph_SPI2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_SPI3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM4 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM5 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM6 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM7 : stm32l1xx_rcc.h
  • RCC_APB1Periph_UART4 : stm32l1xx_rcc.h
  • RCC_APB1Periph_UART5 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USART2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USART3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USB : stm32l1xx_rcc.h
  • RCC_APB1Periph_WWDG : stm32l1xx_rcc.h
  • RCC_APB1PeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1PeriphClockLPModeCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1PeriphResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1RSTR_COMPRST : stm32l1xx.h
  • RCC_APB1RSTR_DACRST : stm32l1xx.h
  • RCC_APB1RSTR_I2C1RST : stm32l1xx.h
  • RCC_APB1RSTR_I2C2RST : stm32l1xx.h
  • RCC_APB1RSTR_LCDRST : stm32l1xx.h
  • RCC_APB1RSTR_PWRRST : stm32l1xx.h
  • RCC_APB1RSTR_SPI2RST : stm32l1xx.h
  • RCC_APB1RSTR_SPI3RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM2RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM3RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM4RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM5RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM6RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM7RST : stm32l1xx.h
  • RCC_APB1RSTR_UART4RST : stm32l1xx.h
  • RCC_APB1RSTR_UART5RST : stm32l1xx.h
  • RCC_APB1RSTR_USART2RST : stm32l1xx.h
  • RCC_APB1RSTR_USART3RST : stm32l1xx.h
  • RCC_APB1RSTR_USBRST : stm32l1xx.h
  • RCC_APB1RSTR_WWDGRST : stm32l1xx.h
  • RCC_APB2ENR_ADC1EN : stm32l1xx.h
  • RCC_APB2ENR_SDIOEN : stm32l1xx.h
  • RCC_APB2ENR_SPI1EN : stm32l1xx.h
  • RCC_APB2ENR_SYSCFGEN : stm32l1xx.h
  • RCC_APB2ENR_TIM10EN : stm32l1xx.h
  • RCC_APB2ENR_TIM11EN : stm32l1xx.h
  • RCC_APB2ENR_TIM9EN : stm32l1xx.h
  • RCC_APB2ENR_USART1EN : stm32l1xx.h
  • RCC_APB2LPENR_ADC1LPEN : stm32l1xx.h
  • RCC_APB2LPENR_SDIOLPEN : stm32l1xx.h
  • RCC_APB2LPENR_SPI1LPEN : stm32l1xx.h
  • RCC_APB2LPENR_SYSCFGLPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM10LPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM11LPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM9LPEN : stm32l1xx.h
  • RCC_APB2LPENR_USART1LPEN : stm32l1xx.h
  • RCC_APB2Periph_ADC1 : stm32l1xx_rcc.h
  • RCC_APB2Periph_SDIO : stm32l1xx_rcc.h
  • RCC_APB2Periph_SPI1 : stm32l1xx_rcc.h
  • RCC_APB2Periph_SYSCFG : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM10 : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM11 : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM9 : stm32l1xx_rcc.h
  • RCC_APB2Periph_USART1 : stm32l1xx_rcc.h
  • RCC_APB2PeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB2PeriphClockLPModeCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB2PeriphResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB2RSTR_ADC1RST : stm32l1xx.h
  • RCC_APB2RSTR_SDIORST : stm32l1xx.h
  • RCC_APB2RSTR_SPI1RST : stm32l1xx.h
  • RCC_APB2RSTR_SYSCFGRST : stm32l1xx.h
  • RCC_APB2RSTR_TIM10RST : stm32l1xx.h
  • RCC_APB2RSTR_TIM11RST : stm32l1xx.h
  • RCC_APB2RSTR_TIM9RST : stm32l1xx.h
  • RCC_APB2RSTR_USART1RST : stm32l1xx.h
  • RCC_BASE : stm32l1xx.h
  • RCC_CFGR_HPRE : stm32l1xx.h
  • RCC_CFGR_HPRE_0 : stm32l1xx.h
  • RCC_CFGR_HPRE_1 : stm32l1xx.h
  • RCC_CFGR_HPRE_2 : stm32l1xx.h
  • RCC_CFGR_HPRE_3 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV1 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV128 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV16 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV2 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV256 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV4 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV512 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV64 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV8 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV1 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV16 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV2 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV4 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV8 : stm32l1xx.h
  • RCC_CFGR_MCO_HSE : stm32l1xx.h
  • RCC_CFGR_MCO_HSI : stm32l1xx.h
  • RCC_CFGR_MCO_LSE : stm32l1xx.h
  • RCC_CFGR_MCO_LSI : stm32l1xx.h
  • RCC_CFGR_MCO_MSI : stm32l1xx.h
  • RCC_CFGR_MCO_NOCLOCK : stm32l1xx.h
  • RCC_CFGR_MCO_PLL : stm32l1xx.h
  • RCC_CFGR_MCO_SYSCLK : stm32l1xx.h
  • RCC_CFGR_MCOPRE : stm32l1xx.h
  • RCC_CFGR_MCOPRE_0 : stm32l1xx.h
  • RCC_CFGR_MCOPRE_1 : stm32l1xx.h
  • RCC_CFGR_MCOPRE_2 : stm32l1xx.h
  • RCC_CFGR_MCOSEL : stm32l1xx.h
  • RCC_CFGR_MCOSEL_0 : stm32l1xx.h
  • RCC_CFGR_MCOSEL_1 : stm32l1xx.h
  • RCC_CFGR_MCOSEL_2 : stm32l1xx.h
  • RCC_CFGR_PLLDIV : stm32l1xx.h
  • RCC_CFGR_PLLDIV1 : stm32l1xx.h
  • RCC_CFGR_PLLDIV2 : stm32l1xx.h
  • RCC_CFGR_PLLDIV3 : stm32l1xx.h
  • RCC_CFGR_PLLDIV4 : stm32l1xx.h
  • RCC_CFGR_PLLDIV_0 : stm32l1xx.h
  • RCC_CFGR_PLLDIV_1 : stm32l1xx.h
  • RCC_CFGR_PLLMUL : stm32l1xx.h
  • RCC_CFGR_PLLMUL12 : stm32l1xx.h
  • RCC_CFGR_PLLMUL16 : stm32l1xx.h
  • RCC_CFGR_PLLMUL24 : stm32l1xx.h
  • RCC_CFGR_PLLMUL3 : stm32l1xx.h
  • RCC_CFGR_PLLMUL32 : stm32l1xx.h
  • RCC_CFGR_PLLMUL4 : stm32l1xx.h
  • RCC_CFGR_PLLMUL48 : stm32l1xx.h
  • RCC_CFGR_PLLMUL6 : stm32l1xx.h
  • RCC_CFGR_PLLMUL8 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_0 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_1 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_2 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_3 : stm32l1xx.h
  • RCC_CFGR_PLLSRC : stm32l1xx.h
  • RCC_CFGR_PLLSRC_HSE : stm32l1xx.h
  • RCC_CFGR_PLLSRC_HSI : stm32l1xx.h
  • RCC_CFGR_PPRE1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_0 : stm32l1xx.h
  • RCC_CFGR_PPRE1_1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_2 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV16 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV2 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV4 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV8 : stm32l1xx.h
  • RCC_CFGR_PPRE2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_0 : stm32l1xx.h
  • RCC_CFGR_PPRE2_1 : stm32l1xx.h
  • RCC_CFGR_PPRE2_2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV1 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV16 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV4 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV8 : stm32l1xx.h
  • RCC_CFGR_SW : stm32l1xx.h
  • RCC_CFGR_SW_0 : stm32l1xx.h
  • RCC_CFGR_SW_1 : stm32l1xx.h
  • RCC_CFGR_SW_HSE : stm32l1xx.h
  • RCC_CFGR_SW_HSI : stm32l1xx.h
  • RCC_CFGR_SW_MSI : stm32l1xx.h
  • RCC_CFGR_SW_PLL : stm32l1xx.h
  • RCC_CFGR_SWS : stm32l1xx.h
  • RCC_CFGR_SWS_0 : stm32l1xx.h
  • RCC_CFGR_SWS_1 : stm32l1xx.h
  • RCC_CFGR_SWS_HSE : stm32l1xx.h
  • RCC_CFGR_SWS_HSI : stm32l1xx.h
  • RCC_CFGR_SWS_MSI : stm32l1xx.h
  • RCC_CFGR_SWS_PLL : stm32l1xx.h
  • RCC_CIR_CSSC : stm32l1xx.h
  • RCC_CIR_CSSF : stm32l1xx.h
  • RCC_CIR_HSERDYC : stm32l1xx.h
  • RCC_CIR_HSERDYF : stm32l1xx.h
  • RCC_CIR_HSERDYIE : stm32l1xx.h
  • RCC_CIR_HSIRDYC : stm32l1xx.h
  • RCC_CIR_HSIRDYF : stm32l1xx.h
  • RCC_CIR_HSIRDYIE : stm32l1xx.h
  • RCC_CIR_LSECSS : stm32l1xx.h
  • RCC_CIR_LSECSSC : stm32l1xx.h
  • RCC_CIR_LSECSSIE : stm32l1xx.h
  • RCC_CIR_LSERDYC : stm32l1xx.h
  • RCC_CIR_LSERDYF : stm32l1xx.h
  • RCC_CIR_LSERDYIE : stm32l1xx.h
  • RCC_CIR_LSIRDYC : stm32l1xx.h
  • RCC_CIR_LSIRDYF : stm32l1xx.h
  • RCC_CIR_LSIRDYIE : stm32l1xx.h
  • RCC_CIR_MSIRDYC : stm32l1xx.h
  • RCC_CIR_MSIRDYF : stm32l1xx.h
  • RCC_CIR_MSIRDYIE : stm32l1xx.h
  • RCC_CIR_PLLRDYC : stm32l1xx.h
  • RCC_CIR_PLLRDYF : stm32l1xx.h
  • RCC_CIR_PLLRDYIE : stm32l1xx.h
  • RCC_ClearFlag() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ClearITPendingBit() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ClockSecuritySystemCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_CR_CSSON : stm32l1xx.h
  • RCC_CR_HSEBYP : stm32l1xx.h
  • RCC_CR_HSEON : stm32l1xx.h
  • RCC_CR_HSERDY : stm32l1xx.h
  • RCC_CR_HSION : stm32l1xx.h
  • RCC_CR_HSIRDY : stm32l1xx.h
  • RCC_CR_MSION : stm32l1xx.h
  • RCC_CR_MSIRDY : stm32l1xx.h
  • RCC_CR_PLLON : stm32l1xx.h
  • RCC_CR_PLLRDY : stm32l1xx.h
  • RCC_CR_RTCPRE : stm32l1xx.h
  • RCC_CR_RTCPRE_0 : stm32l1xx.h
  • RCC_CR_RTCPRE_1 : stm32l1xx.h
  • RCC_CSR_IWDGRSTF : stm32l1xx.h
  • RCC_CSR_LPWRRSTF : stm32l1xx.h
  • RCC_CSR_LSEBYP : stm32l1xx.h
  • RCC_CSR_LSECSSD : stm32l1xx.h
  • RCC_CSR_LSECSSON : stm32l1xx.h
  • RCC_CSR_LSEON : stm32l1xx.h
  • RCC_CSR_LSERDY : stm32l1xx.h
  • RCC_CSR_LSION : stm32l1xx.h
  • RCC_CSR_LSIRDY : stm32l1xx.h
  • RCC_CSR_OBLRSTF : stm32l1xx.h
  • RCC_CSR_PINRSTF : stm32l1xx.h
  • RCC_CSR_PORRSTF : stm32l1xx.h
  • RCC_CSR_RMVF : stm32l1xx.h
  • RCC_CSR_RTCEN : stm32l1xx.h
  • RCC_CSR_RTCRST : stm32l1xx.h
  • RCC_CSR_RTCSEL : stm32l1xx.h
  • RCC_CSR_RTCSEL_0 : stm32l1xx.h
  • RCC_CSR_RTCSEL_1 : stm32l1xx.h
  • RCC_CSR_RTCSEL_HSE : stm32l1xx.h
  • RCC_CSR_RTCSEL_LSE : stm32l1xx.h
  • RCC_CSR_RTCSEL_LSI : stm32l1xx.h
  • RCC_CSR_RTCSEL_NOCLOCK : stm32l1xx.h
  • RCC_CSR_SFTRSTF : stm32l1xx.h
  • RCC_CSR_WWDGRSTF : stm32l1xx.h
  • RCC_DeInit() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_FLAG_HSERDY : stm32l1xx_rcc.h
  • RCC_FLAG_HSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_IWDGRST : stm32l1xx_rcc.h
  • RCC_FLAG_LPWRRST : stm32l1xx_rcc.h
  • RCC_FLAG_LSECSS : stm32l1xx_rcc.h
  • RCC_FLAG_LSERDY : stm32l1xx_rcc.h
  • RCC_FLAG_LSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_MSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_OBLRST : stm32l1xx_rcc.h
  • RCC_FLAG_PINRST : stm32l1xx_rcc.h
  • RCC_FLAG_PLLRDY : stm32l1xx_rcc.h
  • RCC_FLAG_PORRST : stm32l1xx_rcc.h
  • RCC_FLAG_SFTRST : stm32l1xx_rcc.h
  • RCC_FLAG_WWDGRST : stm32l1xx_rcc.h
  • RCC_GetClocksFreq() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetFlagStatus() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetITStatus() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetSYSCLKSource() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HCLK_Div1 : stm32l1xx_rcc.h
  • RCC_HCLK_Div16 : stm32l1xx_rcc.h
  • RCC_HCLK_Div2 : stm32l1xx_rcc.h
  • RCC_HCLK_Div4 : stm32l1xx_rcc.h
  • RCC_HCLK_Div8 : stm32l1xx_rcc.h
  • RCC_HCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HSE_Bypass : stm32l1xx_rcc.h
  • RCC_HSE_OFF : stm32l1xx_rcc.h
  • RCC_HSE_ON : stm32l1xx_rcc.h
  • RCC_HSEConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ICSCR_HSICAL : stm32l1xx.h
  • RCC_ICSCR_HSITRIM : stm32l1xx.h
  • RCC_ICSCR_MSICAL : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_0 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_1 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_2 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_3 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_4 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_5 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_6 : stm32l1xx.h
  • RCC_ICSCR_MSITRIM : stm32l1xx.h
  • RCC_IRQn : stm32l1xx.h
  • RCC_IT_CSS : stm32l1xx_rcc.h
  • RCC_IT_HSERDY : stm32l1xx_rcc.h
  • RCC_IT_HSIRDY : stm32l1xx_rcc.h
  • RCC_IT_LSECSS : stm32l1xx_rcc.h
  • RCC_IT_LSERDY : stm32l1xx_rcc.h
  • RCC_IT_LSIRDY : stm32l1xx_rcc.h
  • RCC_IT_MSIRDY : stm32l1xx_rcc.h
  • RCC_IT_PLLRDY : stm32l1xx_rcc.h
  • RCC_ITConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSE_Bypass : stm32l1xx_rcc.h
  • RCC_LSE_OFF : stm32l1xx_rcc.h
  • RCC_LSE_ON : stm32l1xx_rcc.h
  • RCC_LSEClockSecuritySystemCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSEConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MCOConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MCODiv_1 : stm32l1xx_rcc.h
  • RCC_MCODiv_16 : stm32l1xx_rcc.h
  • RCC_MCODiv_2 : stm32l1xx_rcc.h
  • RCC_MCODiv_4 : stm32l1xx_rcc.h
  • RCC_MCODiv_8 : stm32l1xx_rcc.h
  • RCC_MCOSource_HSE : stm32l1xx_rcc.h
  • RCC_MCOSource_HSI : stm32l1xx_rcc.h
  • RCC_MCOSource_LSE : stm32l1xx_rcc.h
  • RCC_MCOSource_LSI : stm32l1xx_rcc.h
  • RCC_MCOSource_MSI : stm32l1xx_rcc.h
  • RCC_MCOSource_NoClock : stm32l1xx_rcc.h
  • RCC_MCOSource_PLLCLK : stm32l1xx_rcc.h
  • RCC_MCOSource_SYSCLK : stm32l1xx_rcc.h
  • RCC_MSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MSIRange_0 : stm32l1xx_rcc.h
  • RCC_MSIRange_1 : stm32l1xx_rcc.h
  • RCC_MSIRange_2 : stm32l1xx_rcc.h
  • RCC_MSIRange_3 : stm32l1xx_rcc.h
  • RCC_MSIRange_4 : stm32l1xx_rcc.h
  • RCC_MSIRange_5 : stm32l1xx_rcc.h
  • RCC_MSIRange_6 : stm32l1xx_rcc.h
  • RCC_MSIRangeConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_OFFSET : stm32l1xx_rcc.c
  • RCC_PCLK1Config() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PCLK2Config() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PLLCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PLLConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PLLDiv_2 : stm32l1xx_rcc.h
  • RCC_PLLDiv_3 : stm32l1xx_rcc.h
  • RCC_PLLDiv_4 : stm32l1xx_rcc.h
  • RCC_PLLMul_12 : stm32l1xx_rcc.h
  • RCC_PLLMul_16 : stm32l1xx_rcc.h
  • RCC_PLLMul_24 : stm32l1xx_rcc.h
  • RCC_PLLMul_3 : stm32l1xx_rcc.h
  • RCC_PLLMul_32 : stm32l1xx_rcc.h
  • RCC_PLLMul_4 : stm32l1xx_rcc.h
  • RCC_PLLMul_48 : stm32l1xx_rcc.h
  • RCC_PLLMul_6 : stm32l1xx_rcc.h
  • RCC_PLLMul_8 : stm32l1xx_rcc.h
  • RCC_PLLSource_HSE : stm32l1xx_rcc.h
  • RCC_PLLSource_HSI : stm32l1xx_rcc.h
  • RCC_RTCCLKCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_RTCCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_RTCCLKSource_HSE_Div16 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div2 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div4 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div8 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_LSE : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_LSI : stm32l1xx_rcc.h
  • RCC_RTCResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_SYSCLK_Div1 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div128 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div16 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div2 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div256 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div4 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div512 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div64 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div8 : stm32l1xx_rcc.h
  • RCC_SYSCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_SYSCLKSource_HSE : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_HSI : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_MSI : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_PLLCLK : stm32l1xx_rcc.h
  • RCC_WaitForHSEStartUp() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • READ_BIT : stm32l1xx.h
  • READ_REG : stm32l1xx.h
  • RECALPF_TIMEOUT : stm32l1xx_rtc.c
  • RESET : stm32l1xx.h
  • RI : stm32l1xx.h
  • RI_ASCR1_CH : stm32l1xx.h
  • RI_ASCR1_CH_0 : stm32l1xx.h
  • RI_ASCR1_CH_1 : stm32l1xx.h
  • RI_ASCR1_CH_10 : stm32l1xx.h
  • RI_ASCR1_CH_11 : stm32l1xx.h
  • RI_ASCR1_CH_12 : stm32l1xx.h
  • RI_ASCR1_CH_13 : stm32l1xx.h
  • RI_ASCR1_CH_14 : stm32l1xx.h
  • RI_ASCR1_CH_15 : stm32l1xx.h
  • RI_ASCR1_CH_18 : stm32l1xx.h
  • RI_ASCR1_CH_19 : stm32l1xx.h
  • RI_ASCR1_CH_2 : stm32l1xx.h
  • RI_ASCR1_CH_20 : stm32l1xx.h
  • RI_ASCR1_CH_21 : stm32l1xx.h
  • RI_ASCR1_CH_22 : stm32l1xx.h
  • RI_ASCR1_CH_23 : stm32l1xx.h
  • RI_ASCR1_CH_24 : stm32l1xx.h
  • RI_ASCR1_CH_25 : stm32l1xx.h
  • RI_ASCR1_CH_27 : stm32l1xx.h
  • RI_ASCR1_CH_28 : stm32l1xx.h
  • RI_ASCR1_CH_29 : stm32l1xx.h
  • RI_ASCR1_CH_3 : stm32l1xx.h
  • RI_ASCR1_CH_30 : stm32l1xx.h
  • RI_ASCR1_CH_31 : stm32l1xx.h
  • RI_ASCR1_CH_4 : stm32l1xx.h
  • RI_ASCR1_CH_5 : stm32l1xx.h
  • RI_ASCR1_CH_6 : stm32l1xx.h
  • RI_ASCR1_CH_7 : stm32l1xx.h
  • RI_ASCR1_CH_8 : stm32l1xx.h
  • RI_ASCR1_CH_9 : stm32l1xx.h
  • RI_ASCR1_SCM : stm32l1xx.h
  • RI_ASCR1_VCOMP : stm32l1xx.h
  • RI_ASCR2_CH0b : stm32l1xx.h
  • RI_ASCR2_CH10b : stm32l1xx.h
  • RI_ASCR2_CH11b : stm32l1xx.h
  • RI_ASCR2_CH12b : stm32l1xx.h
  • RI_ASCR2_CH1b : stm32l1xx.h
  • RI_ASCR2_CH2b : stm32l1xx.h
  • RI_ASCR2_CH3b : stm32l1xx.h
  • RI_ASCR2_CH6b : stm32l1xx.h
  • RI_ASCR2_CH7b : stm32l1xx.h
  • RI_ASCR2_CH8b : stm32l1xx.h
  • RI_ASCR2_CH9b : stm32l1xx.h
  • RI_ASCR2_GR10_1 : stm32l1xx.h
  • RI_ASCR2_GR10_2 : stm32l1xx.h
  • RI_ASCR2_GR10_3 : stm32l1xx.h
  • RI_ASCR2_GR10_4 : stm32l1xx.h
  • RI_ASCR2_GR4_1 : stm32l1xx.h
  • RI_ASCR2_GR4_2 : stm32l1xx.h
  • RI_ASCR2_GR4_3 : stm32l1xx.h
  • RI_ASCR2_GR4_4 : stm32l1xx.h
  • RI_ASCR2_GR5_1 : stm32l1xx.h
  • RI_ASCR2_GR5_2 : stm32l1xx.h
  • RI_ASCR2_GR5_3 : stm32l1xx.h
  • RI_ASCR2_GR5_4 : stm32l1xx.h
  • RI_ASCR2_GR6_1 : stm32l1xx.h
  • RI_ASCR2_GR6_2 : stm32l1xx.h
  • RI_ASCR2_GR6_3 : stm32l1xx.h
  • RI_ASCR2_GR6_4 : stm32l1xx.h
  • RI_BASE : stm32l1xx.h
  • RI_Channel_13 : stm32l1xx_syscfg.h
  • RI_Channel_3 : stm32l1xx_syscfg.h
  • RI_Channel_8 : stm32l1xx_syscfg.h
  • RI_ChannelSpeed_Fast : stm32l1xx_syscfg.h
  • RI_ChannelSpeed_Slow : stm32l1xx_syscfg.h
  • RI_HYSCR1_PA : stm32l1xx.h
  • RI_HYSCR1_PA_0 : stm32l1xx.h
  • RI_HYSCR1_PA_1 : stm32l1xx.h
  • RI_HYSCR1_PA_10 : stm32l1xx.h
  • RI_HYSCR1_PA_11 : stm32l1xx.h
  • RI_HYSCR1_PA_12 : stm32l1xx.h
  • RI_HYSCR1_PA_13 : stm32l1xx.h
  • RI_HYSCR1_PA_14 : stm32l1xx.h
  • RI_HYSCR1_PA_15 : stm32l1xx.h
  • RI_HYSCR1_PA_2 : stm32l1xx.h
  • RI_HYSCR1_PA_3 : stm32l1xx.h
  • RI_HYSCR1_PA_4 : stm32l1xx.h
  • RI_HYSCR1_PA_5 : stm32l1xx.h
  • RI_HYSCR1_PA_6 : stm32l1xx.h
  • RI_HYSCR1_PA_7 : stm32l1xx.h
  • RI_HYSCR1_PA_8 : stm32l1xx.h
  • RI_HYSCR1_PA_9 : stm32l1xx.h
  • RI_HYSCR1_PB : stm32l1xx.h
  • RI_HYSCR1_PB_0 : stm32l1xx.h
  • RI_HYSCR1_PB_1 : stm32l1xx.h
  • RI_HYSCR1_PB_10 : stm32l1xx.h
  • RI_HYSCR1_PB_11 : stm32l1xx.h
  • RI_HYSCR1_PB_12 : stm32l1xx.h
  • RI_HYSCR1_PB_13 : stm32l1xx.h
  • RI_HYSCR1_PB_14 : stm32l1xx.h
  • RI_HYSCR1_PB_15 : stm32l1xx.h
  • RI_HYSCR1_PB_2 : stm32l1xx.h
  • RI_HYSCR1_PB_3 : stm32l1xx.h
  • RI_HYSCR1_PB_4 : stm32l1xx.h
  • RI_HYSCR1_PB_5 : stm32l1xx.h
  • RI_HYSCR1_PB_6 : stm32l1xx.h
  • RI_HYSCR1_PB_7 : stm32l1xx.h
  • RI_HYSCR1_PB_8 : stm32l1xx.h
  • RI_HYSCR1_PB_9 : stm32l1xx.h
  • RI_HYSCR2_PC : stm32l1xx.h
  • RI_HYSCR2_PC_0 : stm32l1xx.h
  • RI_HYSCR2_PC_1 : stm32l1xx.h
  • RI_HYSCR2_PC_10 : stm32l1xx.h
  • RI_HYSCR2_PC_11 : stm32l1xx.h
  • RI_HYSCR2_PC_12 : stm32l1xx.h
  • RI_HYSCR2_PC_13 : stm32l1xx.h
  • RI_HYSCR2_PC_14 : stm32l1xx.h
  • RI_HYSCR2_PC_15 : stm32l1xx.h
  • RI_HYSCR2_PC_2 : stm32l1xx.h
  • RI_HYSCR2_PC_3 : stm32l1xx.h
  • RI_HYSCR2_PC_4 : stm32l1xx.h
  • RI_HYSCR2_PC_5 : stm32l1xx.h
  • RI_HYSCR2_PC_6 : stm32l1xx.h
  • RI_HYSCR2_PC_7 : stm32l1xx.h
  • RI_HYSCR2_PC_8 : stm32l1xx.h
  • RI_HYSCR2_PC_9 : stm32l1xx.h
  • RI_HYSCR2_PD : stm32l1xx.h
  • RI_HYSCR2_PD_0 : stm32l1xx.h
  • RI_HYSCR2_PD_1 : stm32l1xx.h
  • RI_HYSCR2_PD_10 : stm32l1xx.h
  • RI_HYSCR2_PD_11 : stm32l1xx.h
  • RI_HYSCR2_PD_12 : stm32l1xx.h
  • RI_HYSCR2_PD_13 : stm32l1xx.h
  • RI_HYSCR2_PD_14 : stm32l1xx.h
  • RI_HYSCR2_PD_15 : stm32l1xx.h
  • RI_HYSCR2_PD_2 : stm32l1xx.h
  • RI_HYSCR2_PD_3 : stm32l1xx.h
  • RI_HYSCR2_PD_4 : stm32l1xx.h
  • RI_HYSCR2_PD_5 : stm32l1xx.h
  • RI_HYSCR2_PD_6 : stm32l1xx.h
  • RI_HYSCR2_PD_7 : stm32l1xx.h
  • RI_HYSCR2_PD_8 : stm32l1xx.h
  • RI_HYSCR2_PD_9 : stm32l1xx.h
  • RI_HYSCR2_PE : stm32l1xx.h
  • RI_HYSCR2_PE_0 : stm32l1xx.h
  • RI_HYSCR2_PE_1 : stm32l1xx.h
  • RI_HYSCR2_PE_10 : stm32l1xx.h
  • RI_HYSCR2_PE_11 : stm32l1xx.h
  • RI_HYSCR2_PE_12 : stm32l1xx.h
  • RI_HYSCR2_PE_13 : stm32l1xx.h
  • RI_HYSCR2_PE_14 : stm32l1xx.h
  • RI_HYSCR2_PE_15 : stm32l1xx.h
  • RI_HYSCR2_PE_2 : stm32l1xx.h
  • RI_HYSCR2_PE_3 : stm32l1xx.h
  • RI_HYSCR2_PE_4 : stm32l1xx.h
  • RI_HYSCR2_PE_5 : stm32l1xx.h
  • RI_HYSCR2_PE_6 : stm32l1xx.h
  • RI_HYSCR2_PE_7 : stm32l1xx.h
  • RI_HYSCR2_PE_8 : stm32l1xx.h
  • RI_HYSCR2_PE_9 : stm32l1xx.h
  • RI_HYSCR3_PF : stm32l1xx.h
  • RI_HYSCR3_PF_0 : stm32l1xx.h
  • RI_HYSCR3_PF_1 : stm32l1xx.h
  • RI_HYSCR3_PF_10 : stm32l1xx.h
  • RI_HYSCR3_PF_11 : stm32l1xx.h
  • RI_HYSCR3_PF_12 : stm32l1xx.h
  • RI_HYSCR3_PF_13 : stm32l1xx.h
  • RI_HYSCR3_PF_14 : stm32l1xx.h
  • RI_HYSCR3_PF_15 : stm32l1xx.h
  • RI_HYSCR3_PF_2 : stm32l1xx.h
  • RI_HYSCR3_PF_3 : stm32l1xx.h
  • RI_HYSCR3_PF_4 : stm32l1xx.h
  • RI_HYSCR3_PF_5 : stm32l1xx.h
  • RI_HYSCR3_PF_6 : stm32l1xx.h
  • RI_HYSCR3_PF_7 : stm32l1xx.h
  • RI_HYSCR3_PF_8 : stm32l1xx.h
  • RI_HYSCR3_PF_9 : stm32l1xx.h
  • RI_HYSCR4_PG : stm32l1xx.h
  • RI_HYSCR4_PG_0 : stm32l1xx.h
  • RI_HYSCR4_PG_1 : stm32l1xx.h
  • RI_HYSCR4_PG_10 : stm32l1xx.h
  • RI_HYSCR4_PG_11 : stm32l1xx.h
  • RI_HYSCR4_PG_12 : stm32l1xx.h
  • RI_HYSCR4_PG_13 : stm32l1xx.h
  • RI_HYSCR4_PG_14 : stm32l1xx.h
  • RI_HYSCR4_PG_15 : stm32l1xx.h
  • RI_HYSCR4_PG_2 : stm32l1xx.h
  • RI_HYSCR4_PG_3 : stm32l1xx.h
  • RI_HYSCR4_PG_4 : stm32l1xx.h
  • RI_HYSCR4_PG_5 : stm32l1xx.h
  • RI_HYSCR4_PG_6 : stm32l1xx.h
  • RI_HYSCR4_PG_7 : stm32l1xx.h
  • RI_HYSCR4_PG_8 : stm32l1xx.h
  • RI_HYSCR4_PG_9 : stm32l1xx.h
  • RI_ICR_IC1 : stm32l1xx.h
  • RI_ICR_IC1Z : stm32l1xx.h
  • RI_ICR_IC1Z_0 : stm32l1xx.h
  • RI_ICR_IC1Z_1 : stm32l1xx.h
  • RI_ICR_IC1Z_2 : stm32l1xx.h
  • RI_ICR_IC1Z_3 : stm32l1xx.h
  • RI_ICR_IC2 : stm32l1xx.h
  • RI_ICR_IC2Z : stm32l1xx.h
  • RI_ICR_IC2Z_0 : stm32l1xx.h
  • RI_ICR_IC2Z_1 : stm32l1xx.h
  • RI_ICR_IC2Z_2 : stm32l1xx.h
  • RI_ICR_IC2Z_3 : stm32l1xx.h
  • RI_ICR_IC3 : stm32l1xx.h
  • RI_ICR_IC3Z : stm32l1xx.h
  • RI_ICR_IC3Z_0 : stm32l1xx.h
  • RI_ICR_IC3Z_1 : stm32l1xx.h
  • RI_ICR_IC3Z_2 : stm32l1xx.h
  • RI_ICR_IC3Z_3 : stm32l1xx.h
  • RI_ICR_IC4 : stm32l1xx.h
  • RI_ICR_IC4Z : stm32l1xx.h
  • RI_ICR_IC4Z_0 : stm32l1xx.h
  • RI_ICR_IC4Z_1 : stm32l1xx.h
  • RI_ICR_IC4Z_2 : stm32l1xx.h
  • RI_ICR_IC4Z_3 : stm32l1xx.h
  • RI_ICR_TIM : stm32l1xx.h
  • RI_ICR_TIM_0 : stm32l1xx.h
  • RI_ICR_TIM_1 : stm32l1xx.h
  • RI_InputCapture_IC1 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC2 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC3 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC4 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_0 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_1 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_10 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_11 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_12 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_13 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_14 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_15 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_2 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_3 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_4 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_5 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_6 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_7 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_8 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_9 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH0 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH0b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH10 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH10b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH11 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH11b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH12 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH12b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH13 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH14 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH15 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH18 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH19 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH1b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH20 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH21 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH22 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH23 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH24 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH25 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH27 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH28 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH29 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH2b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH30 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH31 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH3b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH5 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH6 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH6b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH7 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH7b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH8 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH8b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH9 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH9b : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_VCOMP : stm32l1xx_syscfg.h
  • RI_Pin_0 : stm32l1xx_syscfg.h
  • RI_Pin_1 : stm32l1xx_syscfg.h
  • RI_Pin_10 : stm32l1xx_syscfg.h
  • RI_Pin_11 : stm32l1xx_syscfg.h
  • RI_Pin_12 : stm32l1xx_syscfg.h
  • RI_Pin_13 : stm32l1xx_syscfg.h
  • RI_Pin_14 : stm32l1xx_syscfg.h
  • RI_Pin_15 : stm32l1xx_syscfg.h
  • RI_Pin_2 : stm32l1xx_syscfg.h
  • RI_Pin_3 : stm32l1xx_syscfg.h
  • RI_Pin_4 : stm32l1xx_syscfg.h
  • RI_Pin_5 : stm32l1xx_syscfg.h
  • RI_Pin_6 : stm32l1xx_syscfg.h
  • RI_Pin_7 : stm32l1xx_syscfg.h
  • RI_Pin_8 : stm32l1xx_syscfg.h
  • RI_Pin_9 : stm32l1xx_syscfg.h
  • RI_Pin_All : stm32l1xx_syscfg.h
  • RI_PortA : stm32l1xx_syscfg.h
  • RI_PortB : stm32l1xx_syscfg.h
  • RI_PortC : stm32l1xx_syscfg.h
  • RI_PortD : stm32l1xx_syscfg.h
  • RI_PortE : stm32l1xx_syscfg.h
  • RI_PortF : stm32l1xx_syscfg.h
  • RI_PortG : stm32l1xx_syscfg.h
  • RI_Resistor_10KPD : stm32l1xx_syscfg.h
  • RI_Resistor_10KPU : stm32l1xx_syscfg.h
  • RI_Resistor_400KPD : stm32l1xx_syscfg.h
  • RI_Resistor_400KPU : stm32l1xx_syscfg.h
  • RTC : stm32l1xx.h
  • RTC_Alarm_A : stm32l1xx_rtc.h
  • RTC_Alarm_B : stm32l1xx_rtc.h
  • RTC_Alarm_IRQn : stm32l1xx.h
  • RTC_AlarmCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_AlarmDateWeekDaySel_Date : stm32l1xx_rtc.h
  • RTC_AlarmDateWeekDaySel_WeekDay : stm32l1xx_rtc.h
  • RTC_AlarmMask_All : stm32l1xx_rtc.h
  • RTC_AlarmMask_DateWeekDay : stm32l1xx_rtc.h
  • RTC_AlarmMask_Hours : stm32l1xx_rtc.h
  • RTC_AlarmMask_Minutes : stm32l1xx_rtc.h
  • RTC_AlarmMask_None : stm32l1xx_rtc.h
  • RTC_AlarmMask_Seconds : stm32l1xx_rtc.h
  • RTC_AlarmStructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_AlarmSubSecondConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_AlarmSubSecondMask_All : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_None : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_1 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_10 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_11 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_12 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_13 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_2 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_3 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_4 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_5 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_6 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_7 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_8 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_9 : stm32l1xx_rtc.h
  • RTC_ALRMAR_DT : stm32l1xx.h
  • RTC_ALRMAR_DT_0 : stm32l1xx.h
  • RTC_ALRMAR_DT_1 : stm32l1xx.h
  • RTC_ALRMAR_DU : stm32l1xx.h
  • RTC_ALRMAR_DU_0 : stm32l1xx.h
  • RTC_ALRMAR_DU_1 : stm32l1xx.h
  • RTC_ALRMAR_DU_2 : stm32l1xx.h
  • RTC_ALRMAR_DU_3 : stm32l1xx.h
  • RTC_ALRMAR_HT : stm32l1xx.h
  • RTC_ALRMAR_HT_0 : stm32l1xx.h
  • RTC_ALRMAR_HT_1 : stm32l1xx.h
  • RTC_ALRMAR_HU : stm32l1xx.h
  • RTC_ALRMAR_HU_0 : stm32l1xx.h
  • RTC_ALRMAR_HU_1 : stm32l1xx.h
  • RTC_ALRMAR_HU_2 : stm32l1xx.h
  • RTC_ALRMAR_HU_3 : stm32l1xx.h
  • RTC_ALRMAR_MNT : stm32l1xx.h
  • RTC_ALRMAR_MNT_0 : stm32l1xx.h
  • RTC_ALRMAR_MNT_1 : stm32l1xx.h
  • RTC_ALRMAR_MNT_2 : stm32l1xx.h
  • RTC_ALRMAR_MNU : stm32l1xx.h
  • RTC_ALRMAR_MNU_0 : stm32l1xx.h
  • RTC_ALRMAR_MNU_1 : stm32l1xx.h
  • RTC_ALRMAR_MNU_2 : stm32l1xx.h
  • RTC_ALRMAR_MNU_3 : stm32l1xx.h
  • RTC_ALRMAR_MSK1 : stm32l1xx.h
  • RTC_ALRMAR_MSK2 : stm32l1xx.h
  • RTC_ALRMAR_MSK3 : stm32l1xx.h
  • RTC_ALRMAR_MSK4 : stm32l1xx.h
  • RTC_ALRMAR_PM : stm32l1xx.h
  • RTC_ALRMAR_ST : stm32l1xx.h
  • RTC_ALRMAR_ST_0 : stm32l1xx.h
  • RTC_ALRMAR_ST_1 : stm32l1xx.h
  • RTC_ALRMAR_ST_2 : stm32l1xx.h
  • RTC_ALRMAR_SU : stm32l1xx.h
  • RTC_ALRMAR_SU_0 : stm32l1xx.h
  • RTC_ALRMAR_SU_1 : stm32l1xx.h
  • RTC_ALRMAR_SU_2 : stm32l1xx.h
  • RTC_ALRMAR_SU_3 : stm32l1xx.h
  • RTC_ALRMAR_WDSEL : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_0 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_1 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_2 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_3 : stm32l1xx.h
  • RTC_ALRMASSR_SS : stm32l1xx.h
  • RTC_ALRMBR_DT : stm32l1xx.h
  • RTC_ALRMBR_DT_0 : stm32l1xx.h
  • RTC_ALRMBR_DT_1 : stm32l1xx.h
  • RTC_ALRMBR_DU : stm32l1xx.h
  • RTC_ALRMBR_DU_0 : stm32l1xx.h
  • RTC_ALRMBR_DU_1 : stm32l1xx.h
  • RTC_ALRMBR_DU_2 : stm32l1xx.h
  • RTC_ALRMBR_DU_3 : stm32l1xx.h
  • RTC_ALRMBR_HT : stm32l1xx.h
  • RTC_ALRMBR_HT_0 : stm32l1xx.h
  • RTC_ALRMBR_HT_1 : stm32l1xx.h
  • RTC_ALRMBR_HU : stm32l1xx.h
  • RTC_ALRMBR_HU_0 : stm32l1xx.h
  • RTC_ALRMBR_HU_1 : stm32l1xx.h
  • RTC_ALRMBR_HU_2 : stm32l1xx.h
  • RTC_ALRMBR_HU_3 : stm32l1xx.h
  • RTC_ALRMBR_MNT : stm32l1xx.h
  • RTC_ALRMBR_MNT_0 : stm32l1xx.h
  • RTC_ALRMBR_MNT_1 : stm32l1xx.h
  • RTC_ALRMBR_MNT_2 : stm32l1xx.h
  • RTC_ALRMBR_MNU : stm32l1xx.h
  • RTC_ALRMBR_MNU_0 : stm32l1xx.h
  • RTC_ALRMBR_MNU_1 : stm32l1xx.h
  • RTC_ALRMBR_MNU_2 : stm32l1xx.h
  • RTC_ALRMBR_MNU_3 : stm32l1xx.h
  • RTC_ALRMBR_MSK1 : stm32l1xx.h
  • RTC_ALRMBR_MSK2 : stm32l1xx.h
  • RTC_ALRMBR_MSK3 : stm32l1xx.h
  • RTC_ALRMBR_MSK4 : stm32l1xx.h
  • RTC_ALRMBR_PM : stm32l1xx.h
  • RTC_ALRMBR_ST : stm32l1xx.h
  • RTC_ALRMBR_ST_0 : stm32l1xx.h
  • RTC_ALRMBR_ST_1 : stm32l1xx.h
  • RTC_ALRMBR_ST_2 : stm32l1xx.h
  • RTC_ALRMBR_SU : stm32l1xx.h
  • RTC_ALRMBR_SU_0 : stm32l1xx.h
  • RTC_ALRMBR_SU_1 : stm32l1xx.h
  • RTC_ALRMBR_SU_2 : stm32l1xx.h
  • RTC_ALRMBR_SU_3 : stm32l1xx.h
  • RTC_ALRMBR_WDSEL : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_0 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_1 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_2 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_3 : stm32l1xx.h
  • RTC_ALRMBSSR_SS : stm32l1xx.h
  • RTC_BASE : stm32l1xx.h
  • RTC_Bcd2ToByte() : stm32l1xx_rtc.c
  • RTC_BKP0R : stm32l1xx.h
  • RTC_BKP10R : stm32l1xx.h
  • RTC_BKP11R : stm32l1xx.h
  • RTC_BKP12R : stm32l1xx.h
  • RTC_BKP13R : stm32l1xx.h
  • RTC_BKP14R : stm32l1xx.h
  • RTC_BKP15R : stm32l1xx.h
  • RTC_BKP16R : stm32l1xx.h
  • RTC_BKP17R : stm32l1xx.h
  • RTC_BKP18R : stm32l1xx.h
  • RTC_BKP19R : stm32l1xx.h
  • RTC_BKP1R : stm32l1xx.h
  • RTC_BKP20R : stm32l1xx.h
  • RTC_BKP21R : stm32l1xx.h
  • RTC_BKP22R : stm32l1xx.h
  • RTC_BKP23R : stm32l1xx.h
  • RTC_BKP24R : stm32l1xx.h
  • RTC_BKP25R : stm32l1xx.h
  • RTC_BKP26R : stm32l1xx.h
  • RTC_BKP27R : stm32l1xx.h
  • RTC_BKP28R : stm32l1xx.h
  • RTC_BKP29R : stm32l1xx.h
  • RTC_BKP2R : stm32l1xx.h
  • RTC_BKP30R : stm32l1xx.h
  • RTC_BKP31R : stm32l1xx.h
  • RTC_BKP3R : stm32l1xx.h
  • RTC_BKP4R : stm32l1xx.h
  • RTC_BKP5R : stm32l1xx.h
  • RTC_BKP6R : stm32l1xx.h
  • RTC_BKP7R : stm32l1xx.h
  • RTC_BKP8R : stm32l1xx.h
  • RTC_BKP9R : stm32l1xx.h
  • RTC_BKP_DR0 : stm32l1xx_rtc.h
  • RTC_BKP_DR1 : stm32l1xx_rtc.h
  • RTC_BKP_DR10 : stm32l1xx_rtc.h
  • RTC_BKP_DR11 : stm32l1xx_rtc.h
  • RTC_BKP_DR12 : stm32l1xx_rtc.h
  • RTC_BKP_DR13 : stm32l1xx_rtc.h
  • RTC_BKP_DR14 : stm32l1xx_rtc.h
  • RTC_BKP_DR15 : stm32l1xx_rtc.h
  • RTC_BKP_DR16 : stm32l1xx_rtc.h
  • RTC_BKP_DR17 : stm32l1xx_rtc.h
  • RTC_BKP_DR18 : stm32l1xx_rtc.h
  • RTC_BKP_DR19 : stm32l1xx_rtc.h
  • RTC_BKP_DR2 : stm32l1xx_rtc.h
  • RTC_BKP_DR20 : stm32l1xx_rtc.h
  • RTC_BKP_DR21 : stm32l1xx_rtc.h
  • RTC_BKP_DR22 : stm32l1xx_rtc.h
  • RTC_BKP_DR23 : stm32l1xx_rtc.h
  • RTC_BKP_DR24 : stm32l1xx_rtc.h
  • RTC_BKP_DR25 : stm32l1xx_rtc.h
  • RTC_BKP_DR26 : stm32l1xx_rtc.h
  • RTC_BKP_DR27 : stm32l1xx_rtc.h
  • RTC_BKP_DR28 : stm32l1xx_rtc.h
  • RTC_BKP_DR29 : stm32l1xx_rtc.h
  • RTC_BKP_DR3 : stm32l1xx_rtc.h
  • RTC_BKP_DR30 : stm32l1xx_rtc.h
  • RTC_BKP_DR31 : stm32l1xx_rtc.h
  • RTC_BKP_DR4 : stm32l1xx_rtc.h
  • RTC_BKP_DR5 : stm32l1xx_rtc.h
  • RTC_BKP_DR6 : stm32l1xx_rtc.h
  • RTC_BKP_DR7 : stm32l1xx_rtc.h
  • RTC_BKP_DR8 : stm32l1xx_rtc.h
  • RTC_BKP_DR9 : stm32l1xx_rtc.h
  • RTC_BypassShadowCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ByteToBcd2() : stm32l1xx_rtc.c
  • RTC_CalibOutput_1Hz : stm32l1xx_rtc.h
  • RTC_CalibOutput_512Hz : stm32l1xx_rtc.h
  • RTC_CalibOutputCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_CalibOutputConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_CALIBR_DC : stm32l1xx.h
  • RTC_CALIBR_DCS : stm32l1xx.h
  • RTC_CalibSign_Negative : stm32l1xx_rtc.h
  • RTC_CalibSign_Positive : stm32l1xx_rtc.h
  • RTC_CALR_CALM : stm32l1xx.h
  • RTC_CALR_CALM_0 : stm32l1xx.h
  • RTC_CALR_CALM_1 : stm32l1xx.h
  • RTC_CALR_CALM_2 : stm32l1xx.h
  • RTC_CALR_CALM_3 : stm32l1xx.h
  • RTC_CALR_CALM_4 : stm32l1xx.h
  • RTC_CALR_CALM_5 : stm32l1xx.h
  • RTC_CALR_CALM_6 : stm32l1xx.h
  • RTC_CALR_CALM_7 : stm32l1xx.h
  • RTC_CALR_CALM_8 : stm32l1xx.h
  • RTC_CALR_CALP : stm32l1xx.h
  • RTC_CALR_CALW16 : stm32l1xx.h
  • RTC_CALR_CALW8 : stm32l1xx.h
  • RTC_ClearFlag() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_ClearITPendingBit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_CoarseCalibCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_CoarseCalibConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_CR_ADD1H : stm32l1xx.h
  • RTC_CR_ALRAE : stm32l1xx.h
  • RTC_CR_ALRAIE : stm32l1xx.h
  • RTC_CR_ALRBE : stm32l1xx.h
  • RTC_CR_ALRBIE : stm32l1xx.h
  • RTC_CR_BCK : stm32l1xx.h
  • RTC_CR_BYPSHAD : stm32l1xx.h
  • RTC_CR_COE : stm32l1xx.h
  • RTC_CR_COSEL : stm32l1xx.h
  • RTC_CR_DCE : stm32l1xx.h
  • RTC_CR_FMT : stm32l1xx.h
  • RTC_CR_OSEL : stm32l1xx.h
  • RTC_CR_OSEL_0 : stm32l1xx.h
  • RTC_CR_OSEL_1 : stm32l1xx.h
  • RTC_CR_POL : stm32l1xx.h
  • RTC_CR_REFCKON : stm32l1xx.h
  • RTC_CR_SUB1H : stm32l1xx.h
  • RTC_CR_TSE : stm32l1xx.h
  • RTC_CR_TSEDGE : stm32l1xx.h
  • RTC_CR_TSIE : stm32l1xx.h
  • RTC_CR_WUCKSEL : stm32l1xx.h
  • RTC_CR_WUCKSEL_0 : stm32l1xx.h
  • RTC_CR_WUCKSEL_1 : stm32l1xx.h
  • RTC_CR_WUCKSEL_2 : stm32l1xx.h
  • RTC_CR_WUTE : stm32l1xx.h
  • RTC_CR_WUTIE : stm32l1xx.h
  • RTC_DateStructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_DayLightSaving_ADD1H : stm32l1xx_rtc.h
  • RTC_DayLightSaving_SUB1H : stm32l1xx_rtc.h
  • RTC_DayLightSavingConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_DeInit() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_DigitalCalibCmd : stm32l1xx_rtc.h
  • RTC_DigitalCalibConfig : stm32l1xx_rtc.h
  • RTC_DR_DT : stm32l1xx.h
  • RTC_DR_DT_0 : stm32l1xx.h
  • RTC_DR_DT_1 : stm32l1xx.h
  • RTC_DR_DU : stm32l1xx.h
  • RTC_DR_DU_0 : stm32l1xx.h
  • RTC_DR_DU_1 : stm32l1xx.h
  • RTC_DR_DU_2 : stm32l1xx.h
  • RTC_DR_DU_3 : stm32l1xx.h
  • RTC_DR_MT : stm32l1xx.h
  • RTC_DR_MU : stm32l1xx.h
  • RTC_DR_MU_0 : stm32l1xx.h
  • RTC_DR_MU_1 : stm32l1xx.h
  • RTC_DR_MU_2 : stm32l1xx.h
  • RTC_DR_MU_3 : stm32l1xx.h
  • RTC_DR_RESERVED_MASK : stm32l1xx_rtc.c
  • RTC_DR_WDU : stm32l1xx.h
  • RTC_DR_WDU_0 : stm32l1xx.h
  • RTC_DR_WDU_1 : stm32l1xx.h
  • RTC_DR_WDU_2 : stm32l1xx.h
  • RTC_DR_YT : stm32l1xx.h
  • RTC_DR_YT_0 : stm32l1xx.h
  • RTC_DR_YT_1 : stm32l1xx.h
  • RTC_DR_YT_2 : stm32l1xx.h
  • RTC_DR_YT_3 : stm32l1xx.h
  • RTC_DR_YU : stm32l1xx.h
  • RTC_DR_YU_0 : stm32l1xx.h
  • RTC_DR_YU_1 : stm32l1xx.h
  • RTC_DR_YU_2 : stm32l1xx.h
  • RTC_DR_YU_3 : stm32l1xx.h
  • RTC_EnterInitMode() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ExitInitMode() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_FLAG_ALRAF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRAWF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRBF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRBWF : stm32l1xx_rtc.h
  • RTC_FLAG_INITF : stm32l1xx_rtc.h
  • RTC_FLAG_INITS : stm32l1xx_rtc.h
  • RTC_FLAG_RECALPF : stm32l1xx_rtc.h
  • RTC_FLAG_RSF : stm32l1xx_rtc.h
  • RTC_FLAG_SHPF : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP1F : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP2F : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP3F : stm32l1xx_rtc.h
  • RTC_FLAG_TSF : stm32l1xx_rtc.h
  • RTC_FLAG_TSOVF : stm32l1xx_rtc.h
  • RTC_FLAG_WUTF : stm32l1xx_rtc.h
  • RTC_FLAG_WUTWF : stm32l1xx_rtc.h
  • RTC_FLAGS_MASK : stm32l1xx_rtc.c
  • RTC_Format_BCD : stm32l1xx_rtc.h
  • RTC_Format_BIN : stm32l1xx_rtc.h
  • RTC_GetAlarm() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetAlarmSubSecond() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetDate() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_GetFlagStatus() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetITStatus() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_GetStoreOperation() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetSubSecond() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_GetTime() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetTimeStamp() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_GetTimeStampSubSecond() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetWakeUpCounter() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_H12_AM : stm32l1xx_rtc.h
  • RTC_H12_PM : stm32l1xx_rtc.h
  • RTC_HourFormat_12 : stm32l1xx_rtc.h
  • RTC_HourFormat_24 : stm32l1xx_rtc.h
  • RTC_Init() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_INIT_MASK : stm32l1xx_rtc.c
  • RTC_ISR_ALRAF : stm32l1xx.h
  • RTC_ISR_ALRAWF : stm32l1xx.h
  • RTC_ISR_ALRBF : stm32l1xx.h
  • RTC_ISR_ALRBWF : stm32l1xx.h
  • RTC_ISR_INIT : stm32l1xx.h
  • RTC_ISR_INITF : stm32l1xx.h
  • RTC_ISR_INITS : stm32l1xx.h
  • RTC_ISR_RECALPF : stm32l1xx.h
  • RTC_ISR_RSF : stm32l1xx.h
  • RTC_ISR_SHPF : stm32l1xx.h
  • RTC_ISR_TAMP1F : stm32l1xx.h
  • RTC_ISR_TAMP2F : stm32l1xx.h
  • RTC_ISR_TAMP3F : stm32l1xx.h
  • RTC_ISR_TSF : stm32l1xx.h
  • RTC_ISR_TSOVF : stm32l1xx.h
  • RTC_ISR_WUTF : stm32l1xx.h
  • RTC_ISR_WUTWF : stm32l1xx.h
  • RTC_IT_ALRA : stm32l1xx_rtc.h
  • RTC_IT_ALRB : stm32l1xx_rtc.h
  • RTC_IT_TAMP : stm32l1xx_rtc.h
  • RTC_IT_TAMP1 : stm32l1xx_rtc.h
  • RTC_IT_TAMP2 : stm32l1xx_rtc.h
  • RTC_IT_TAMP3 : stm32l1xx_rtc.h
  • RTC_IT_TS : stm32l1xx_rtc.h
  • RTC_IT_WUT : stm32l1xx_rtc.h
  • RTC_ITConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_Month_April : stm32l1xx_rtc.h
  • RTC_Month_August : stm32l1xx_rtc.h
  • RTC_Month_December : stm32l1xx_rtc.h
  • RTC_Month_February : stm32l1xx_rtc.h
  • RTC_Month_January : stm32l1xx_rtc.h
  • RTC_Month_July : stm32l1xx_rtc.h
  • RTC_Month_June : stm32l1xx_rtc.h
  • RTC_Month_March : stm32l1xx_rtc.h
  • RTC_Month_May : stm32l1xx_rtc.h
  • RTC_Month_November : stm32l1xx_rtc.h
  • RTC_Month_October : stm32l1xx_rtc.h
  • RTC_Month_September : stm32l1xx_rtc.h
  • RTC_Output_AlarmA : stm32l1xx_rtc.h
  • RTC_Output_AlarmB : stm32l1xx_rtc.h
  • RTC_Output_Disable : stm32l1xx_rtc.h
  • RTC_Output_WakeUp : stm32l1xx_rtc.h
  • RTC_OutputConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_OutputPolarity_High : stm32l1xx_rtc.h
  • RTC_OutputPolarity_Low : stm32l1xx_rtc.h
  • RTC_OutputType_OpenDrain : stm32l1xx_rtc.h
  • RTC_OutputType_PushPull : stm32l1xx_rtc.h
  • RTC_OutputTypeConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_PRER_PREDIV_A : stm32l1xx.h
  • RTC_PRER_PREDIV_S : stm32l1xx.h
  • RTC_ReadBackupRegister() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_RefClockCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_RSF_MASK : stm32l1xx_rtc.c
  • RTC_SetAlarm() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SetDate() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_SetTime() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SetWakeUpCounter() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_ShiftAdd1S_Reset : stm32l1xx_rtc.h
  • RTC_ShiftAdd1S_Set : stm32l1xx_rtc.h
  • RTC_SHIFTR_ADD1S : stm32l1xx.h
  • RTC_SHIFTR_SUBFS : stm32l1xx.h
  • RTC_SmoothCalibConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SmoothCalibPeriod_16sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPeriod_32sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPeriod_8sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPlusPulses_Reset : stm32l1xx_rtc.h
  • RTC_SmoothCalibPlusPulses_Set : stm32l1xx_rtc.h
  • RTC_SSR_SS : stm32l1xx.h
  • RTC_StoreOperation_Reset : stm32l1xx_rtc.h
  • RTC_StoreOperation_Set : stm32l1xx_rtc.h
  • RTC_StructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_SynchroShiftConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TAFCR_ALARMOUTTYPE : stm32l1xx.h
  • RTC_TAFCR_TAMP1E : stm32l1xx.h
  • RTC_TAFCR_TAMP1TRG : stm32l1xx.h
  • RTC_TAFCR_TAMP2E : stm32l1xx.h
  • RTC_TAFCR_TAMP2TRG : stm32l1xx.h
  • RTC_TAFCR_TAMP3E : stm32l1xx.h
  • RTC_TAFCR_TAMP3TRG : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_2 : stm32l1xx.h
  • RTC_TAFCR_TAMPIE : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPPUDIS : stm32l1xx.h
  • RTC_TAFCR_TAMPTS : stm32l1xx.h
  • RTC_Tamper_1 : stm32l1xx_rtc.h
  • RTC_Tamper_2 : stm32l1xx_rtc.h
  • RTC_Tamper_3 : stm32l1xx_rtc.h
  • RTC_TamperCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperFilter_2Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_4Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_8Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_Disable : stm32l1xx_rtc.h
  • RTC_TamperFilterConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperPinsPrechargeDuration() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_1RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_2RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_4RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_8RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPullUpCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TamperSamplingFreq_RTCCLK_Div1024 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div16384 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div2048 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div256 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div32768 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div4096 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div512 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div8192 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreqConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TamperTrigger_FallingEdge : stm32l1xx_rtc.h
  • RTC_TamperTrigger_HighLevel : stm32l1xx_rtc.h
  • RTC_TamperTrigger_LowLevel : stm32l1xx_rtc.h
  • RTC_TamperTrigger_RisingEdge : stm32l1xx_rtc.h
  • RTC_TamperTriggerConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TimeStampCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TimeStampEdge_Falling : stm32l1xx_rtc.h
  • RTC_TimeStampEdge_Rising : stm32l1xx_rtc.h
  • RTC_TimeStampOnTamperDetectionCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TimeStructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TR_HT : stm32l1xx.h
  • RTC_TR_HT_0 : stm32l1xx.h
  • RTC_TR_HT_1 : stm32l1xx.h
  • RTC_TR_HU : stm32l1xx.h
  • RTC_TR_HU_0 : stm32l1xx.h
  • RTC_TR_HU_1 : stm32l1xx.h
  • RTC_TR_HU_2 : stm32l1xx.h
  • RTC_TR_HU_3 : stm32l1xx.h
  • RTC_TR_MNT : stm32l1xx.h
  • RTC_TR_MNT_0 : stm32l1xx.h
  • RTC_TR_MNT_1 : stm32l1xx.h
  • RTC_TR_MNT_2 : stm32l1xx.h
  • RTC_TR_MNU : stm32l1xx.h
  • RTC_TR_MNU_0 : stm32l1xx.h
  • RTC_TR_MNU_1 : stm32l1xx.h
  • RTC_TR_MNU_2 : stm32l1xx.h
  • RTC_TR_MNU_3 : stm32l1xx.h
  • RTC_TR_PM : stm32l1xx.h
  • RTC_TR_RESERVED_MASK : stm32l1xx_rtc.c
  • RTC_TR_ST : stm32l1xx.h
  • RTC_TR_ST_0 : stm32l1xx.h
  • RTC_TR_ST_1 : stm32l1xx.h
  • RTC_TR_ST_2 : stm32l1xx.h
  • RTC_TR_SU : stm32l1xx.h
  • RTC_TR_SU_0 : stm32l1xx.h
  • RTC_TR_SU_1 : stm32l1xx.h
  • RTC_TR_SU_2 : stm32l1xx.h
  • RTC_TR_SU_3 : stm32l1xx.h
  • RTC_TSDR_DT : stm32l1xx.h
  • RTC_TSDR_DT_0 : stm32l1xx.h
  • RTC_TSDR_DT_1 : stm32l1xx.h
  • RTC_TSDR_DU : stm32l1xx.h
  • RTC_TSDR_DU_0 : stm32l1xx.h
  • RTC_TSDR_DU_1 : stm32l1xx.h
  • RTC_TSDR_DU_2 : stm32l1xx.h
  • RTC_TSDR_DU_3 : stm32l1xx.h
  • RTC_TSDR_MT : stm32l1xx.h
  • RTC_TSDR_MU : stm32l1xx.h
  • RTC_TSDR_MU_0 : stm32l1xx.h
  • RTC_TSDR_MU_1 : stm32l1xx.h
  • RTC_TSDR_MU_2 : stm32l1xx.h
  • RTC_TSDR_MU_3 : stm32l1xx.h
  • RTC_TSDR_WDU : stm32l1xx.h
  • RTC_TSDR_WDU_0 : stm32l1xx.h
  • RTC_TSDR_WDU_1 : stm32l1xx.h
  • RTC_TSDR_WDU_2 : stm32l1xx.h
  • RTC_TSSSR_SS : stm32l1xx.h
  • RTC_TSTR_HT : stm32l1xx.h
  • RTC_TSTR_HT_0 : stm32l1xx.h
  • RTC_TSTR_HT_1 : stm32l1xx.h
  • RTC_TSTR_HU : stm32l1xx.h
  • RTC_TSTR_HU_0 : stm32l1xx.h
  • RTC_TSTR_HU_1 : stm32l1xx.h
  • RTC_TSTR_HU_2 : stm32l1xx.h
  • RTC_TSTR_HU_3 : stm32l1xx.h
  • RTC_TSTR_MNT : stm32l1xx.h
  • RTC_TSTR_MNT_0 : stm32l1xx.h
  • RTC_TSTR_MNT_1 : stm32l1xx.h
  • RTC_TSTR_MNT_2 : stm32l1xx.h
  • RTC_TSTR_MNU : stm32l1xx.h
  • RTC_TSTR_MNU_0 : stm32l1xx.h
  • RTC_TSTR_MNU_1 : stm32l1xx.h
  • RTC_TSTR_MNU_2 : stm32l1xx.h
  • RTC_TSTR_MNU_3 : stm32l1xx.h
  • RTC_TSTR_PM : stm32l1xx.h
  • RTC_TSTR_ST : stm32l1xx.h
  • RTC_TSTR_ST_0 : stm32l1xx.h
  • RTC_TSTR_ST_1 : stm32l1xx.h
  • RTC_TSTR_ST_2 : stm32l1xx.h
  • RTC_TSTR_SU : stm32l1xx.h
  • RTC_TSTR_SU_0 : stm32l1xx.h
  • RTC_TSTR_SU_1 : stm32l1xx.h
  • RTC_TSTR_SU_2 : stm32l1xx.h
  • RTC_TSTR_SU_3 : stm32l1xx.h
  • RTC_WaitForSynchro() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WakeUpClock_CK_SPRE_16bits : stm32l1xx_rtc.h
  • RTC_WakeUpClock_CK_SPRE_17bits : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div16 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div2 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div4 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div8 : stm32l1xx_rtc.h
  • RTC_WakeUpClockConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WakeUpCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_Weekday_Friday : stm32l1xx_rtc.h
  • RTC_Weekday_Monday : stm32l1xx_rtc.h
  • RTC_Weekday_Saturday : stm32l1xx_rtc.h
  • RTC_Weekday_Sunday : stm32l1xx_rtc.h
  • RTC_Weekday_Thursday : stm32l1xx_rtc.h
  • RTC_Weekday_Tuesday : stm32l1xx_rtc.h
  • RTC_Weekday_Wednesday : stm32l1xx_rtc.h
  • RTC_WKUP_IRQn : stm32l1xx.h
  • RTC_WPR_KEY : stm32l1xx.h
  • RTC_WriteBackupRegister() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_WriteProtectionCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WUTR_WUT : stm32l1xx.h
  • RTCEN_BitNumber : stm32l1xx_rcc.c
  • RTCRST_BitNumber : stm32l1xx_rcc.c
  • RWMOD_BitNumber : stm32l1xx_sdio.c
  • RWSTART_BitNumber : stm32l1xx_sdio.c
  • RWSTOP_BitNumber : stm32l1xx_sdio.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SCB_AFSR_IMPDEF : stm32l1xx.h
  • SCB_AIRCR_ENDIANESS : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP0 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP1 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP2 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP3 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP4 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP5 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP6 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP7 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_0 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_1 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_2 : stm32l1xx.h
  • SCB_AIRCR_SYSRESETREQ : stm32l1xx.h
  • SCB_AIRCR_VECTCLRACTIVE : stm32l1xx.h
  • SCB_AIRCR_VECTKEY : stm32l1xx.h
  • SCB_AIRCR_VECTRESET : stm32l1xx.h
  • SCB_BFAR_ADDRESS : stm32l1xx.h
  • SCB_CCR_BFHFNMIGN : stm32l1xx.h
  • SCB_CCR_DIV_0_TRP : stm32l1xx.h
  • SCB_CCR_NONBASETHRDENA : stm32l1xx.h
  • SCB_CCR_STKALIGN : stm32l1xx.h
  • SCB_CCR_UNALIGN_TRP : stm32l1xx.h
  • SCB_CCR_USERSETMPEND : stm32l1xx.h
  • SCB_CFSR_BFARVALID : stm32l1xx.h
  • SCB_CFSR_DACCVIOL : stm32l1xx.h
  • SCB_CFSR_DIVBYZERO : stm32l1xx.h
  • SCB_CFSR_IACCVIOL : stm32l1xx.h
  • SCB_CFSR_IBUSERR : stm32l1xx.h
  • SCB_CFSR_IMPRECISERR : stm32l1xx.h
  • SCB_CFSR_INVPC : stm32l1xx.h
  • SCB_CFSR_INVSTATE : stm32l1xx.h
  • SCB_CFSR_MMARVALID : stm32l1xx.h
  • SCB_CFSR_MSTKERR : stm32l1xx.h
  • SCB_CFSR_MUNSTKERR : stm32l1xx.h
  • SCB_CFSR_NOCP : stm32l1xx.h
  • SCB_CFSR_PRECISERR : stm32l1xx.h
  • SCB_CFSR_STKERR : stm32l1xx.h
  • SCB_CFSR_UNALIGNED : stm32l1xx.h
  • SCB_CFSR_UNDEFINSTR : stm32l1xx.h
  • SCB_CFSR_UNSTKERR : stm32l1xx.h
  • SCB_CPUID_Constant : stm32l1xx.h
  • SCB_CPUID_IMPLEMENTER : stm32l1xx.h
  • SCB_CPUID_PARTNO : stm32l1xx.h
  • SCB_CPUID_REVISION : stm32l1xx.h
  • SCB_CPUID_VARIANT : stm32l1xx.h
  • SCB_DFSR_BKPT : stm32l1xx.h
  • SCB_DFSR_DWTTRAP : stm32l1xx.h
  • SCB_DFSR_EXTERNAL : stm32l1xx.h
  • SCB_DFSR_HALTED : stm32l1xx.h
  • SCB_DFSR_VCATCH : stm32l1xx.h
  • SCB_HFSR_DEBUGEVT : stm32l1xx.h
  • SCB_HFSR_FORCED : stm32l1xx.h
  • SCB_HFSR_VECTTBL : stm32l1xx.h
  • SCB_ICSR_ISRPENDING : stm32l1xx.h
  • SCB_ICSR_ISRPREEMPT : stm32l1xx.h
  • SCB_ICSR_NMIPENDSET : stm32l1xx.h
  • SCB_ICSR_PENDSTCLR : stm32l1xx.h
  • SCB_ICSR_PENDSTSET : stm32l1xx.h
  • SCB_ICSR_PENDSVCLR : stm32l1xx.h
  • SCB_ICSR_PENDSVSET : stm32l1xx.h
  • SCB_ICSR_RETTOBASE : stm32l1xx.h
  • SCB_ICSR_VECTACTIVE : stm32l1xx.h
  • SCB_ICSR_VECTPENDING : stm32l1xx.h
  • SCB_MMFAR_ADDRESS : stm32l1xx.h
  • SCB_SCR_SEVONPEND : stm32l1xx.h
  • SCB_SCR_SLEEPDEEP : stm32l1xx.h
  • SCB_SCR_SLEEPONEXIT : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTACT : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTENA : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTPENDED : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTACT : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTENA : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTPENDED : stm32l1xx.h
  • SCB_SHCSR_MONITORACT : stm32l1xx.h
  • SCB_SHCSR_PENDSVACT : stm32l1xx.h
  • SCB_SHCSR_SVCALLACT : stm32l1xx.h
  • SCB_SHCSR_SVCALLPENDED : stm32l1xx.h
  • SCB_SHCSR_SYSTICKACT : stm32l1xx.h
  • SCB_SHCSR_USGFAULTACT : stm32l1xx.h
  • SCB_SHCSR_USGFAULTENA : stm32l1xx.h
  • SCB_SHCSR_USGFAULTPENDED : stm32l1xx.h
  • SCB_SHPR_PRI_N : stm32l1xx.h
  • SCB_SHPR_PRI_N1 : stm32l1xx.h
  • SCB_SHPR_PRI_N2 : stm32l1xx.h
  • SCB_SHPR_PRI_N3 : stm32l1xx.h
  • SCB_VTOR_TBLBASE : stm32l1xx.h
  • SCB_VTOR_TBLOFF : stm32l1xx.h
  • SDIO : stm32l1xx.h
  • SDIO_ARG_CMDARG : stm32l1xx.h
  • SDIO_BASE : stm32l1xx.h
  • SDIO_BusWide_1b : stm32l1xx_sdio.h
  • SDIO_BusWide_4b : stm32l1xx_sdio.h
  • SDIO_BusWide_8b : stm32l1xx_sdio.h
  • SDIO_CEATAITCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ClearFlag() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ClearITPendingBit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_CLKCR_BYPASS : stm32l1xx.h
  • SDIO_CLKCR_CLKDIV : stm32l1xx.h
  • SDIO_CLKCR_CLKEN : stm32l1xx.h
  • SDIO_CLKCR_HWFC_EN : stm32l1xx.h
  • SDIO_CLKCR_NEGEDGE : stm32l1xx.h
  • SDIO_CLKCR_PWRSAV : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS_0 : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS_1 : stm32l1xx.h
  • SDIO_ClockBypass_Disable : stm32l1xx_sdio.h
  • SDIO_ClockBypass_Enable : stm32l1xx_sdio.h
  • SDIO_ClockCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ClockEdge_Falling : stm32l1xx_sdio.h
  • SDIO_ClockEdge_Rising : stm32l1xx_sdio.h
  • SDIO_ClockPowerSave_Disable : stm32l1xx_sdio.h
  • SDIO_ClockPowerSave_Enable : stm32l1xx_sdio.h
  • SDIO_CMD_CEATACMD : stm32l1xx.h
  • SDIO_CMD_CMDINDEX : stm32l1xx.h
  • SDIO_CMD_CPSMEN : stm32l1xx.h
  • SDIO_CMD_ENCMDCOMPL : stm32l1xx.h
  • SDIO_CMD_NIEN : stm32l1xx.h
  • SDIO_CMD_SDIOSUSPEND : stm32l1xx.h
  • SDIO_CMD_WAITINT : stm32l1xx.h
  • SDIO_CMD_WAITPEND : stm32l1xx.h
  • SDIO_CMD_WAITRESP : stm32l1xx.h
  • SDIO_CMD_WAITRESP_0 : stm32l1xx.h
  • SDIO_CMD_WAITRESP_1 : stm32l1xx.h
  • SDIO_CmdStructInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_CommandCompletionCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_CPSM_Disable : stm32l1xx_sdio.h
  • SDIO_CPSM_Enable : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_1024b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_128b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_16384b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_16b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_1b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_2048b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_256b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_2b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_32b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_4096b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_4b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_512b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_64b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_8192b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_8b : stm32l1xx_sdio.h
  • SDIO_DataConfig() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DataStructInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DCOUNT_DATACOUNT : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_0 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_1 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_2 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_3 : stm32l1xx.h
  • SDIO_DCTRL_DMAEN : stm32l1xx.h
  • SDIO_DCTRL_DTDIR : stm32l1xx.h
  • SDIO_DCTRL_DTEN : stm32l1xx.h
  • SDIO_DCTRL_DTMODE : stm32l1xx.h
  • SDIO_DCTRL_RWMOD : stm32l1xx.h
  • SDIO_DCTRL_RWSTART : stm32l1xx.h
  • SDIO_DCTRL_RWSTOP : stm32l1xx.h
  • SDIO_DCTRL_SDIOEN : stm32l1xx.h
  • SDIO_DeInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DLEN_DATALENGTH : stm32l1xx.h
  • SDIO_DMACmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DPSM_Disable : stm32l1xx_sdio.h
  • SDIO_DPSM_Enable : stm32l1xx_sdio.h
  • SDIO_DTIMER_DATATIME : stm32l1xx.h
  • SDIO_FIFO_FIFODATA : stm32l1xx.h
  • SDIO_FIFOCNT_FIFOCOUNT : stm32l1xx.h
  • SDIO_FLAG_CCRCFAIL : stm32l1xx_sdio.h
  • SDIO_FLAG_CEATAEND : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDACT : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDREND : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDSENT : stm32l1xx_sdio.h
  • SDIO_FLAG_CTIMEOUT : stm32l1xx_sdio.h
  • SDIO_FLAG_DATAEND : stm32l1xx_sdio.h
  • SDIO_FLAG_DBCKEND : stm32l1xx_sdio.h
  • SDIO_FLAG_DCRCFAIL : stm32l1xx_sdio.h
  • SDIO_FLAG_DTIMEOUT : stm32l1xx_sdio.h
  • SDIO_FLAG_RXACT : stm32l1xx_sdio.h
  • SDIO_FLAG_RXDAVL : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOE : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOF : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOHF : stm32l1xx_sdio.h
  • SDIO_FLAG_RXOVERR : stm32l1xx_sdio.h
  • SDIO_FLAG_SDIOIT : stm32l1xx_sdio.h
  • SDIO_FLAG_STBITERR : stm32l1xx_sdio.h
  • SDIO_FLAG_TXACT : stm32l1xx_sdio.h
  • SDIO_FLAG_TXDAVL : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOE : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOF : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOHE : stm32l1xx_sdio.h
  • SDIO_FLAG_TXUNDERR : stm32l1xx_sdio.h
  • SDIO_GetCommandResponse() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetDataCounter() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetFIFOCount() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetFlagStatus() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetITStatus() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetPowerState() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetResponse() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_HardwareFlowControl_Disable : stm32l1xx_sdio.h
  • SDIO_HardwareFlowControl_Enable : stm32l1xx_sdio.h
  • SDIO_ICR_CCRCFAILC : stm32l1xx.h
  • SDIO_ICR_CEATAENDC : stm32l1xx.h
  • SDIO_ICR_CMDRENDC : stm32l1xx.h
  • SDIO_ICR_CMDSENTC : stm32l1xx.h
  • SDIO_ICR_CTIMEOUTC : stm32l1xx.h
  • SDIO_ICR_DATAENDC : stm32l1xx.h
  • SDIO_ICR_DBCKENDC : stm32l1xx.h
  • SDIO_ICR_DCRCFAILC : stm32l1xx.h
  • SDIO_ICR_DTIMEOUTC : stm32l1xx.h
  • SDIO_ICR_RXOVERRC : stm32l1xx.h
  • SDIO_ICR_SDIOITC : stm32l1xx.h
  • SDIO_ICR_STBITERRC : stm32l1xx.h
  • SDIO_ICR_TXUNDERRC : stm32l1xx.h
  • SDIO_Init() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_IRQn : stm32l1xx.h
  • SDIO_IT_CCRCFAIL : stm32l1xx_sdio.h
  • SDIO_IT_CEATAEND : stm32l1xx_sdio.h
  • SDIO_IT_CMDACT : stm32l1xx_sdio.h
  • SDIO_IT_CMDREND : stm32l1xx_sdio.h
  • SDIO_IT_CMDSENT : stm32l1xx_sdio.h
  • SDIO_IT_CTIMEOUT : stm32l1xx_sdio.h
  • SDIO_IT_DATAEND : stm32l1xx_sdio.h
  • SDIO_IT_DBCKEND : stm32l1xx_sdio.h
  • SDIO_IT_DCRCFAIL : stm32l1xx_sdio.h
  • SDIO_IT_DTIMEOUT : stm32l1xx_sdio.h
  • SDIO_IT_RXACT : stm32l1xx_sdio.h
  • SDIO_IT_RXDAVL : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOE : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOF : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOHF : stm32l1xx_sdio.h
  • SDIO_IT_RXOVERR : stm32l1xx_sdio.h
  • SDIO_IT_SDIOIT : stm32l1xx_sdio.h
  • SDIO_IT_STBITERR : stm32l1xx_sdio.h
  • SDIO_IT_TXACT : stm32l1xx_sdio.h
  • SDIO_IT_TXDAVL : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOE : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOF : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOHE : stm32l1xx_sdio.h
  • SDIO_IT_TXUNDERR : stm32l1xx_sdio.h
  • SDIO_ITConfig() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_MASK_CCRCFAILIE : stm32l1xx.h
  • SDIO_MASK_CEATAENDIE : stm32l1xx.h
  • SDIO_MASK_CMDACTIE : stm32l1xx.h
  • SDIO_MASK_CMDRENDIE : stm32l1xx.h
  • SDIO_MASK_CMDSENTIE : stm32l1xx.h
  • SDIO_MASK_CTIMEOUTIE : stm32l1xx.h
  • SDIO_MASK_DATAENDIE : stm32l1xx.h
  • SDIO_MASK_DBCKENDIE : stm32l1xx.h
  • SDIO_MASK_DCRCFAILIE : stm32l1xx.h
  • SDIO_MASK_DTIMEOUTIE : stm32l1xx.h
  • SDIO_MASK_RXACTIE : stm32l1xx.h
  • SDIO_MASK_RXDAVLIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOEIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOFIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOHFIE : stm32l1xx.h
  • SDIO_MASK_RXOVERRIE : stm32l1xx.h
  • SDIO_MASK_SDIOITIE : stm32l1xx.h
  • SDIO_MASK_STBITERRIE : stm32l1xx.h
  • SDIO_MASK_TXACTIE : stm32l1xx.h
  • SDIO_MASK_TXDAVLIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOEIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOFIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOHEIE : stm32l1xx.h
  • SDIO_MASK_TXUNDERRIE : stm32l1xx.h
  • SDIO_OFFSET : stm32l1xx_sdio.c
  • SDIO_POWER_PWRCTRL : stm32l1xx.h
  • SDIO_POWER_PWRCTRL_0 : stm32l1xx.h
  • SDIO_POWER_PWRCTRL_1 : stm32l1xx.h
  • SDIO_PowerState_OFF : stm32l1xx_sdio.h
  • SDIO_PowerState_ON : stm32l1xx_sdio.h
  • SDIO_ReadData() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ReadWaitMode_CLK : stm32l1xx_sdio.h
  • SDIO_ReadWaitMode_DATA2 : stm32l1xx_sdio.h
  • SDIO_RESP0_CARDSTATUS0 : stm32l1xx.h
  • SDIO_RESP1 : stm32l1xx_sdio.h
  • SDIO_RESP1_CARDSTATUS1 : stm32l1xx.h
  • SDIO_RESP2 : stm32l1xx_sdio.h
  • SDIO_RESP2_CARDSTATUS2 : stm32l1xx.h
  • SDIO_RESP3 : stm32l1xx_sdio.h
  • SDIO_RESP3_CARDSTATUS3 : stm32l1xx.h
  • SDIO_RESP4 : stm32l1xx_sdio.h
  • SDIO_RESP4_CARDSTATUS4 : stm32l1xx.h
  • SDIO_RESP_ADDR : stm32l1xx_sdio.c
  • SDIO_RESPCMD_RESPCMD : stm32l1xx.h
  • SDIO_Response_Long : stm32l1xx_sdio.h
  • SDIO_Response_No : stm32l1xx_sdio.h
  • SDIO_Response_Short : stm32l1xx_sdio.h
  • SDIO_SendCEATACmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SendCommand() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SendSDIOSuspendCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetPowerState() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetSDIOOperation() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetSDIOReadWaitMode() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_STA_CCRCFAIL : stm32l1xx.h
  • SDIO_STA_CEATAEND : stm32l1xx.h
  • SDIO_STA_CMDACT : stm32l1xx.h
  • SDIO_STA_CMDREND : stm32l1xx.h
  • SDIO_STA_CMDSENT : stm32l1xx.h
  • SDIO_STA_CTIMEOUT : stm32l1xx.h
  • SDIO_STA_DATAEND : stm32l1xx.h
  • SDIO_STA_DBCKEND : stm32l1xx.h
  • SDIO_STA_DCRCFAIL : stm32l1xx.h
  • SDIO_STA_DTIMEOUT : stm32l1xx.h
  • SDIO_STA_RXACT : stm32l1xx.h
  • SDIO_STA_RXDAVL : stm32l1xx.h
  • SDIO_STA_RXFIFOE : stm32l1xx.h
  • SDIO_STA_RXFIFOF : stm32l1xx.h
  • SDIO_STA_RXFIFOHF : stm32l1xx.h
  • SDIO_STA_RXOVERR : stm32l1xx.h
  • SDIO_STA_SDIOIT : stm32l1xx.h
  • SDIO_STA_STBITERR : stm32l1xx.h
  • SDIO_STA_TXACT : stm32l1xx.h
  • SDIO_STA_TXDAVL : stm32l1xx.h
  • SDIO_STA_TXFIFOE : stm32l1xx.h
  • SDIO_STA_TXFIFOF : stm32l1xx.h
  • SDIO_STA_TXFIFOHE : stm32l1xx.h
  • SDIO_STA_TXUNDERR : stm32l1xx.h
  • SDIO_StartSDIOReadWait() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_StopSDIOReadWait() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_StructInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_TransferDir_ToCard : stm32l1xx_sdio.h
  • SDIO_TransferDir_ToSDIO : stm32l1xx_sdio.h
  • SDIO_TransferMode_Block : stm32l1xx_sdio.h
  • SDIO_TransferMode_Stream : stm32l1xx_sdio.h
  • SDIO_Wait_IT : stm32l1xx_sdio.h
  • SDIO_Wait_No : stm32l1xx_sdio.h
  • SDIO_Wait_Pend : stm32l1xx_sdio.h
  • SDIO_WriteData() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIOEN_BitNumber : stm32l1xx_sdio.c
  • SDIOSUSPEND_BitNumber : stm32l1xx_sdio.c
  • SET : stm32l1xx.h
  • SET_BIT : stm32l1xx.h
  • SetSysClock() : system_stm32l1xx.c
  • SHPF_TIMEOUT : stm32l1xx_rtc.c
  • SMCR_ETR_MASK : stm32l1xx_tim.c
  • SMPR0_SMP_SET : stm32l1xx_adc.c
  • SMPR1_SMP_SET : stm32l1xx_adc.c
  • SMPR2_SMP_SET : stm32l1xx_adc.c
  • SMPR3_SMP_SET : stm32l1xx_adc.c
  • SPI1 : stm32l1xx.h
  • SPI1_BASE : stm32l1xx.h
  • SPI1_IRQn : stm32l1xx.h
  • SPI2 : stm32l1xx.h
  • SPI2_BASE : stm32l1xx.h
  • SPI2_IRQn : stm32l1xx.h
  • SPI3 : stm32l1xx.h
  • SPI3_BASE : stm32l1xx.h
  • SPI3_IRQn : stm32l1xx.h
  • SPI_BaudRatePrescaler_128 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_16 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_2 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_256 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_32 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_4 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_64 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_8 : stm32l1xx_spi.h
  • SPI_BiDirectionalLineConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_CalculateCRC() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_ClearFlag : stm32l1xx_spi.h
  • SPI_ClearITPendingBit : stm32l1xx_spi.h
  • SPI_Cmd() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_CPHA_1Edge : stm32l1xx_spi.h
  • SPI_CPHA_2Edge : stm32l1xx_spi.h
  • SPI_CPOL_High : stm32l1xx_spi.h
  • SPI_CPOL_Low : stm32l1xx_spi.h
  • SPI_CR1_BIDIMODE : stm32l1xx.h
  • SPI_CR1_BIDIOE : stm32l1xx.h
  • SPI_CR1_BR : stm32l1xx.h
  • SPI_CR1_BR_0 : stm32l1xx.h
  • SPI_CR1_BR_1 : stm32l1xx.h
  • SPI_CR1_BR_2 : stm32l1xx.h
  • SPI_CR1_CPHA : stm32l1xx.h
  • SPI_CR1_CPOL : stm32l1xx.h
  • SPI_CR1_CRCEN : stm32l1xx.h
  • SPI_CR1_CRCNEXT : stm32l1xx.h
  • SPI_CR1_DFF : stm32l1xx.h
  • SPI_CR1_LSBFIRST : stm32l1xx.h
  • SPI_CR1_MSTR : stm32l1xx.h
  • SPI_CR1_RXONLY : stm32l1xx.h
  • SPI_CR1_SPE : stm32l1xx.h
  • SPI_CR1_SSI : stm32l1xx.h
  • SPI_CR1_SSM : stm32l1xx.h
  • SPI_CR2_ERRIE : stm32l1xx.h
  • SPI_CR2_FRF : stm32l1xx.h
  • SPI_CR2_RXDMAEN : stm32l1xx.h
  • SPI_CR2_RXNEIE : stm32l1xx.h
  • SPI_CR2_SSOE : stm32l1xx.h
  • SPI_CR2_TXDMAEN : stm32l1xx.h
  • SPI_CR2_TXEIE : stm32l1xx.h
  • SPI_CRC_Rx : stm32l1xx_spi.h
  • SPI_CRC_Tx : stm32l1xx_spi.h
  • SPI_CRCPR_CRCPOLY : stm32l1xx.h
  • SPI_DataSize_16b : stm32l1xx_spi.h
  • SPI_DataSize_8b : stm32l1xx_spi.h
  • SPI_DataSizeConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_DeInit : stm32l1xx_spi.h
  • SPI_Direction_1Line_Rx : stm32l1xx_spi.h
  • SPI_Direction_1Line_Tx : stm32l1xx_spi.h
  • SPI_Direction_2Lines_FullDuplex : stm32l1xx_spi.h
  • SPI_Direction_2Lines_RxOnly : stm32l1xx_spi.h
  • SPI_Direction_Rx : stm32l1xx_spi.h
  • SPI_Direction_Tx : stm32l1xx_spi.h
  • SPI_DMACmd : stm32l1xx_spi.h
  • SPI_DMAReq_Rx : stm32l1xx_spi.h
  • SPI_DMAReq_Tx : stm32l1xx_spi.h
  • SPI_DR_DR : stm32l1xx.h
  • SPI_FirstBit_LSB : stm32l1xx_spi.h
  • SPI_FirstBit_MSB : stm32l1xx_spi.h
  • SPI_FLAG_BSY : stm32l1xx_spi.h
  • SPI_FLAG_CRCERR : stm32l1xx_spi.h
  • SPI_FLAG_MODF : stm32l1xx_spi.h
  • SPI_FLAG_OVR : stm32l1xx_spi.h
  • SPI_FLAG_RXNE : stm32l1xx_spi.h
  • SPI_FLAG_TXE : stm32l1xx_spi.h
  • SPI_GetCRC() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_GetCRCPolynomial() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_GetFlagStatus : stm32l1xx_spi.h
  • SPI_GetITStatus : stm32l1xx_spi.h
  • SPI_I2S_ClearFlag() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ClearITPendingBit() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_I2S_DeInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_DMACmd() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_I2S_DMAReq_Rx : stm32l1xx_spi.h
  • SPI_I2S_DMAReq_Tx : stm32l1xx_spi.h
  • SPI_I2S_FLAG_BSY : stm32l1xx_spi.h
  • SPI_I2S_FLAG_FRE : stm32l1xx_spi.h
  • SPI_I2S_FLAG_OVR : stm32l1xx_spi.h
  • SPI_I2S_FLAG_RXNE : stm32l1xx_spi.h
  • SPI_I2S_FLAG_TXE : stm32l1xx_spi.h
  • SPI_I2S_GetFlagStatus() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_GetITStatus() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_IT_ERR : stm32l1xx_spi.h
  • SPI_I2S_IT_FRE : stm32l1xx_spi.h
  • SPI_I2S_IT_OVR : stm32l1xx_spi.h
  • SPI_I2S_IT_RXNE : stm32l1xx_spi.h
  • SPI_I2S_IT_TXE : stm32l1xx_spi.h
  • SPI_I2S_ITConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ReceiveData() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_SendData() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2SCFGR_CHLEN : stm32l1xx.h
  • SPI_I2SCFGR_CKPOL : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN_0 : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN_1 : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG_0 : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG_1 : stm32l1xx.h
  • SPI_I2SCFGR_I2SE : stm32l1xx.h
  • SPI_I2SCFGR_I2SMOD : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD_0 : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD_1 : stm32l1xx.h
  • SPI_I2SCFGR_PCMSYNC : stm32l1xx.h
  • SPI_I2SPR_I2SDIV : stm32l1xx.h
  • SPI_I2SPR_MCKOE : stm32l1xx.h
  • SPI_I2SPR_ODD : stm32l1xx.h
  • SPI_Init() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_IT_CRCERR : stm32l1xx_spi.h
  • SPI_IT_ERR : stm32l1xx_spi.h
  • SPI_IT_MODF : stm32l1xx_spi.h
  • SPI_IT_OVR : stm32l1xx_spi.h
  • SPI_IT_RXNE : stm32l1xx_spi.h
  • SPI_IT_TXE : stm32l1xx_spi.h
  • SPI_ITConfig : stm32l1xx_spi.h
  • SPI_Mode_Master : stm32l1xx_spi.h
  • SPI_Mode_Slave : stm32l1xx_spi.h
  • SPI_NSS_Hard : stm32l1xx_spi.h
  • SPI_NSS_Soft : stm32l1xx_spi.h
  • SPI_NSSInternalSoft_Reset : stm32l1xx_spi.h
  • SPI_NSSInternalSoft_Set : stm32l1xx_spi.h
  • SPI_NSSInternalSoftwareConfig() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_ReceiveData : stm32l1xx_spi.h
  • SPI_RXCRCR_RXCRC : stm32l1xx.h
  • SPI_SendData : stm32l1xx_spi.h
  • SPI_SR_BSY : stm32l1xx.h
  • SPI_SR_CHSIDE : stm32l1xx.h
  • SPI_SR_CRCERR : stm32l1xx.h
  • SPI_SR_MODF : stm32l1xx.h
  • SPI_SR_OVR : stm32l1xx.h
  • SPI_SR_RXNE : stm32l1xx.h
  • SPI_SR_TXE : stm32l1xx.h
  • SPI_SR_UDR : stm32l1xx.h
  • SPI_SSOutputCmd() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_StructInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_TransmitCRC() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_TXCRCR_TXCRC : stm32l1xx.h
  • SQR1_L_RESET : stm32l1xx_adc.c
  • SQR1_SQ_SET : stm32l1xx_adc.c
  • SQR2_SQ_SET : stm32l1xx_adc.c
  • SQR3_SQ_SET : stm32l1xx_adc.c
  • SQR4_SQ_SET : stm32l1xx_adc.c
  • SQR5_SQ_SET : stm32l1xx_adc.c
  • SR_OFFSET : stm32l1xx_lcd.c
  • SR_UDR_BB : stm32l1xx_lcd.c
  • SRAM_BASE : stm32l1xx.h
  • SRAM_BB_BASE : stm32l1xx.h
  • STM32L1XX_HD : stm32l1xx.h
  • SUCCESS : stm32l1xx.h
  • SVC_IRQn : stm32l1xx.h
  • SYNCHRO_TIMEOUT : stm32l1xx_rtc.c
  • SYSCFG : stm32l1xx.h
  • SYSCFG_BASE : stm32l1xx.h
  • SYSCFG_DeInit() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_EXTICR1_EXTI0 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PG : stm32l1xx.h
  • SYSCFG_EXTILineConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_GetBootMode() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_MemoryRemap_Flash : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_FSMC : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_SRAM : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_SystemFlash : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemapConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_MEMRMP_BOOT_MODE : stm32l1xx.h
  • SYSCFG_MEMRMP_BOOT_MODE_0 : stm32l1xx.h
  • SYSCFG_MEMRMP_BOOT_MODE_1 : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE_0 : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE_1 : stm32l1xx.h
  • SYSCFG_PMC_USB_PU : stm32l1xx.h
  • SYSCFG_RIChannelSpeedConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RIDeInit() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RIHysteresisConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RIIOSwitchConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RIResistorConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RISwitchControlModeCmd() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RITIMInputCaptureConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RITIMSelect() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_USBPuCmd() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SystemCoreClock : system_stm32l1xx.c , system_stm32l1xx.h
  • SystemCoreClockUpdate() : system_stm32l1xx.h , system_stm32l1xx.c
  • SystemInit() : system_stm32l1xx.c , system_stm32l1xx.h
  • SysTick_CALIB_NOREF : stm32l1xx.h
  • SysTick_CALIB_SKEW : stm32l1xx.h
  • SysTick_CALIB_TENMS : stm32l1xx.h
  • SysTick_CLKSource_HCLK : misc.h
  • SysTick_CLKSource_HCLK_Div8 : misc.h
  • SysTick_CLKSourceConfig() : misc.c , misc.h
  • SysTick_CTRL_CLKSOURCE : stm32l1xx.h
  • SysTick_CTRL_COUNTFLAG : stm32l1xx.h
  • SysTick_CTRL_ENABLE : stm32l1xx.h
  • SysTick_CTRL_TICKINT : stm32l1xx.h
  • SysTick_IRQn : stm32l1xx.h
  • SysTick_LOAD_RELOAD : stm32l1xx.h
  • SysTick_VAL_CURRENT : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TAMPER_STAMP_IRQn : stm32l1xx.h
  • TI1_Config() : stm32l1xx_tim.c
  • TI2_Config() : stm32l1xx_tim.c
  • TI3_Config() : stm32l1xx_tim.c
  • TI4_Config() : stm32l1xx_tim.c
  • TIM10 : stm32l1xx.h
  • TIM10_BASE : stm32l1xx.h
  • TIM10_ETR_LSE : stm32l1xx_tim.h
  • TIM10_ETR_TIM9_TRGO : stm32l1xx_tim.h
  • TIM10_GPIO : stm32l1xx_tim.h
  • TIM10_IRQn : stm32l1xx.h
  • TIM10_LSE : stm32l1xx_tim.h
  • TIM10_LSI : stm32l1xx_tim.h
  • TIM10_RI : stm32l1xx_tim.h
  • TIM10_RTC : stm32l1xx_tim.h
  • TIM11 : stm32l1xx.h
  • TIM11_BASE : stm32l1xx.h
  • TIM11_ETR_LSE : stm32l1xx_tim.h
  • TIM11_ETR_TIM9_TRGO : stm32l1xx_tim.h
  • TIM11_GPIO : stm32l1xx_tim.h
  • TIM11_HSE_RTC : stm32l1xx_tim.h
  • TIM11_IRQn : stm32l1xx.h
  • TIM11_MSI : stm32l1xx_tim.h
  • TIM11_RI : stm32l1xx_tim.h
  • TIM2 : stm32l1xx.h
  • TIM2_BASE : stm32l1xx.h
  • TIM2_IRQn : stm32l1xx.h
  • TIM2_TIM10_OC : stm32l1xx_tim.h
  • TIM2_TIM5_TRGO : stm32l1xx_tim.h
  • TIM3 : stm32l1xx.h
  • TIM3_BASE : stm32l1xx.h
  • TIM3_IRQn : stm32l1xx.h
  • TIM3_TIM11_OC : stm32l1xx_tim.h
  • TIM3_TIM5_TRGO : stm32l1xx_tim.h
  • TIM4 : stm32l1xx.h
  • TIM4_BASE : stm32l1xx.h
  • TIM4_IRQn : stm32l1xx.h
  • TIM5 : stm32l1xx.h
  • TIM5_BASE : stm32l1xx.h
  • TIM5_IRQn : stm32l1xx.h
  • TIM6 : stm32l1xx.h
  • TIM6_BASE : stm32l1xx.h
  • TIM6_IRQn : stm32l1xx.h
  • TIM7 : stm32l1xx.h
  • TIM7_BASE : stm32l1xx.h
  • TIM7_IRQn : stm32l1xx.h
  • TIM9 : stm32l1xx.h
  • TIM9_BASE : stm32l1xx.h
  • TIM9_GPIO : stm32l1xx_tim.h
  • TIM9_IRQn : stm32l1xx.h
  • TIM9_LSE : stm32l1xx_tim.h
  • TIM9_TIM3_TRGO : stm32l1xx_tim.h
  • TIM9_TS_IO : stm32l1xx_tim.h
  • TIM_ARR_ARR : stm32l1xx.h
  • TIM_ARRPreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_CCER_CC1E : stm32l1xx.h
  • TIM_CCER_CC1NP : stm32l1xx.h
  • TIM_CCER_CC1P : stm32l1xx.h
  • TIM_CCER_CC2E : stm32l1xx.h
  • TIM_CCER_CC2NP : stm32l1xx.h
  • TIM_CCER_CC2P : stm32l1xx.h
  • TIM_CCER_CC3E : stm32l1xx.h
  • TIM_CCER_CC3NP : stm32l1xx.h
  • TIM_CCER_CC3P : stm32l1xx.h
  • TIM_CCER_CC4E : stm32l1xx.h
  • TIM_CCER_CC4NP : stm32l1xx.h
  • TIM_CCER_CC4P : stm32l1xx.h
  • TIM_CCMR1_CC1S : stm32l1xx.h
  • TIM_CCMR1_CC1S_0 : stm32l1xx.h
  • TIM_CCMR1_CC1S_1 : stm32l1xx.h
  • TIM_CCMR1_CC2S : stm32l1xx.h
  • TIM_CCMR1_CC2S_0 : stm32l1xx.h
  • TIM_CCMR1_CC2S_1 : stm32l1xx.h
  • TIM_CCMR1_IC1F : stm32l1xx.h
  • TIM_CCMR1_IC1F_0 : stm32l1xx.h
  • TIM_CCMR1_IC1F_1 : stm32l1xx.h
  • TIM_CCMR1_IC1F_2 : stm32l1xx.h
  • TIM_CCMR1_IC1F_3 : stm32l1xx.h
  • TIM_CCMR1_IC1PSC : stm32l1xx.h
  • TIM_CCMR1_IC1PSC_0 : stm32l1xx.h
  • TIM_CCMR1_IC1PSC_1 : stm32l1xx.h
  • TIM_CCMR1_IC2F : stm32l1xx.h
  • TIM_CCMR1_IC2F_0 : stm32l1xx.h
  • TIM_CCMR1_IC2F_1 : stm32l1xx.h
  • TIM_CCMR1_IC2F_2 : stm32l1xx.h
  • TIM_CCMR1_IC2F_3 : stm32l1xx.h
  • TIM_CCMR1_IC2PSC : stm32l1xx.h
  • TIM_CCMR1_IC2PSC_0 : stm32l1xx.h
  • TIM_CCMR1_IC2PSC_1 : stm32l1xx.h
  • TIM_CCMR1_OC1CE : stm32l1xx.h
  • TIM_CCMR1_OC1FE : stm32l1xx.h
  • TIM_CCMR1_OC1M : stm32l1xx.h
  • TIM_CCMR1_OC1M_0 : stm32l1xx.h
  • TIM_CCMR1_OC1M_1 : stm32l1xx.h
  • TIM_CCMR1_OC1M_2 : stm32l1xx.h
  • TIM_CCMR1_OC1PE : stm32l1xx.h
  • TIM_CCMR1_OC2CE : stm32l1xx.h
  • TIM_CCMR1_OC2FE : stm32l1xx.h
  • TIM_CCMR1_OC2M : stm32l1xx.h
  • TIM_CCMR1_OC2M_0 : stm32l1xx.h
  • TIM_CCMR1_OC2M_1 : stm32l1xx.h
  • TIM_CCMR1_OC2M_2 : stm32l1xx.h
  • TIM_CCMR1_OC2PE : stm32l1xx.h
  • TIM_CCMR2_CC3S : stm32l1xx.h
  • TIM_CCMR2_CC3S_0 : stm32l1xx.h
  • TIM_CCMR2_CC3S_1 : stm32l1xx.h
  • TIM_CCMR2_CC4S : stm32l1xx.h
  • TIM_CCMR2_CC4S_0 : stm32l1xx.h
  • TIM_CCMR2_CC4S_1 : stm32l1xx.h
  • TIM_CCMR2_IC3F : stm32l1xx.h
  • TIM_CCMR2_IC3F_0 : stm32l1xx.h
  • TIM_CCMR2_IC3F_1 : stm32l1xx.h
  • TIM_CCMR2_IC3F_2 : stm32l1xx.h
  • TIM_CCMR2_IC3F_3 : stm32l1xx.h
  • TIM_CCMR2_IC3PSC : stm32l1xx.h
  • TIM_CCMR2_IC3PSC_0 : stm32l1xx.h
  • TIM_CCMR2_IC3PSC_1 : stm32l1xx.h
  • TIM_CCMR2_IC4F : stm32l1xx.h
  • TIM_CCMR2_IC4F_0 : stm32l1xx.h
  • TIM_CCMR2_IC4F_1 : stm32l1xx.h
  • TIM_CCMR2_IC4F_2 : stm32l1xx.h
  • TIM_CCMR2_IC4F_3 : stm32l1xx.h
  • TIM_CCMR2_IC4PSC : stm32l1xx.h
  • TIM_CCMR2_IC4PSC_0 : stm32l1xx.h
  • TIM_CCMR2_IC4PSC_1 : stm32l1xx.h
  • TIM_CCMR2_OC3CE : stm32l1xx.h
  • TIM_CCMR2_OC3FE : stm32l1xx.h
  • TIM_CCMR2_OC3M : stm32l1xx.h
  • TIM_CCMR2_OC3M_0 : stm32l1xx.h
  • TIM_CCMR2_OC3M_1 : stm32l1xx.h
  • TIM_CCMR2_OC3M_2 : stm32l1xx.h
  • TIM_CCMR2_OC3PE : stm32l1xx.h
  • TIM_CCMR2_OC4CE : stm32l1xx.h
  • TIM_CCMR2_OC4FE : stm32l1xx.h
  • TIM_CCMR2_OC4M : stm32l1xx.h
  • TIM_CCMR2_OC4M_0 : stm32l1xx.h
  • TIM_CCMR2_OC4M_1 : stm32l1xx.h
  • TIM_CCMR2_OC4M_2 : stm32l1xx.h
  • TIM_CCMR2_OC4PE : stm32l1xx.h
  • TIM_CCR1_CCR1 : stm32l1xx.h
  • TIM_CCR2_CCR2 : stm32l1xx.h
  • TIM_CCR3_CCR3 : stm32l1xx.h
  • TIM_CCR4_CCR4 : stm32l1xx.h
  • TIM_CCx_Disable : stm32l1xx_tim.h
  • TIM_CCx_Enable : stm32l1xx_tim.h
  • TIM_CCxCmd() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_Channel_1 : stm32l1xx_tim.h
  • TIM_Channel_2 : stm32l1xx_tim.h
  • TIM_Channel_3 : stm32l1xx_tim.h
  • TIM_Channel_4 : stm32l1xx_tim.h
  • TIM_CKD_DIV1 : stm32l1xx_tim.h
  • TIM_CKD_DIV2 : stm32l1xx_tim.h
  • TIM_CKD_DIV4 : stm32l1xx_tim.h
  • TIM_ClearFlag() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearITPendingBit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC1Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC2Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC3Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC4Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_Cmd() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_CNT_CNT : stm32l1xx.h
  • TIM_CounterMode_CenterAligned1 : stm32l1xx_tim.h
  • TIM_CounterMode_CenterAligned2 : stm32l1xx_tim.h
  • TIM_CounterMode_CenterAligned3 : stm32l1xx_tim.h
  • TIM_CounterMode_Down : stm32l1xx_tim.h
  • TIM_CounterMode_Up : stm32l1xx_tim.h
  • TIM_CounterModeConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_CR1_ARPE : stm32l1xx.h
  • TIM_CR1_CEN : stm32l1xx.h
  • TIM_CR1_CKD : stm32l1xx.h
  • TIM_CR1_CKD_0 : stm32l1xx.h
  • TIM_CR1_CKD_1 : stm32l1xx.h
  • TIM_CR1_CMS : stm32l1xx.h
  • TIM_CR1_CMS_0 : stm32l1xx.h
  • TIM_CR1_CMS_1 : stm32l1xx.h
  • TIM_CR1_DIR : stm32l1xx.h
  • TIM_CR1_OPM : stm32l1xx.h
  • TIM_CR1_UDIS : stm32l1xx.h
  • TIM_CR1_URS : stm32l1xx.h
  • TIM_CR2_CCDS : stm32l1xx.h
  • TIM_CR2_MMS : stm32l1xx.h
  • TIM_CR2_MMS_0 : stm32l1xx.h
  • TIM_CR2_MMS_1 : stm32l1xx.h
  • TIM_CR2_MMS_2 : stm32l1xx.h
  • TIM_CR2_TI1S : stm32l1xx.h
  • TIM_DCR_DBA : stm32l1xx.h
  • TIM_DCR_DBA_0 : stm32l1xx.h
  • TIM_DCR_DBA_1 : stm32l1xx.h
  • TIM_DCR_DBA_2 : stm32l1xx.h
  • TIM_DCR_DBA_3 : stm32l1xx.h
  • TIM_DCR_DBA_4 : stm32l1xx.h
  • TIM_DCR_DBL : stm32l1xx.h
  • TIM_DCR_DBL_0 : stm32l1xx.h
  • TIM_DCR_DBL_1 : stm32l1xx.h
  • TIM_DCR_DBL_2 : stm32l1xx.h
  • TIM_DCR_DBL_3 : stm32l1xx.h
  • TIM_DCR_DBL_4 : stm32l1xx.h
  • TIM_DeInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DIER_CC1DE : stm32l1xx.h
  • TIM_DIER_CC1IE : stm32l1xx.h
  • TIM_DIER_CC2DE : stm32l1xx.h
  • TIM_DIER_CC2IE : stm32l1xx.h
  • TIM_DIER_CC3DE : stm32l1xx.h
  • TIM_DIER_CC3IE : stm32l1xx.h
  • TIM_DIER_CC4DE : stm32l1xx.h
  • TIM_DIER_CC4IE : stm32l1xx.h
  • TIM_DIER_TDE : stm32l1xx.h
  • TIM_DIER_TIE : stm32l1xx.h
  • TIM_DIER_UDE : stm32l1xx.h
  • TIM_DIER_UIE : stm32l1xx.h
  • TIM_DMA_CC1 : stm32l1xx_tim.h
  • TIM_DMA_CC2 : stm32l1xx_tim.h
  • TIM_DMA_CC3 : stm32l1xx_tim.h
  • TIM_DMA_CC4 : stm32l1xx_tim.h
  • TIM_DMA_Trigger : stm32l1xx_tim.h
  • TIM_DMA_Update : stm32l1xx_tim.h
  • TIM_DMABase_ARR : stm32l1xx_tim.h
  • TIM_DMABase_CCER : stm32l1xx_tim.h
  • TIM_DMABase_CCMR1 : stm32l1xx_tim.h
  • TIM_DMABase_CCMR2 : stm32l1xx_tim.h
  • TIM_DMABase_CCR1 : stm32l1xx_tim.h
  • TIM_DMABase_CCR2 : stm32l1xx_tim.h
  • TIM_DMABase_CCR3 : stm32l1xx_tim.h
  • TIM_DMABase_CCR4 : stm32l1xx_tim.h
  • TIM_DMABase_CNT : stm32l1xx_tim.h
  • TIM_DMABase_CR1 : stm32l1xx_tim.h
  • TIM_DMABase_CR2 : stm32l1xx_tim.h
  • TIM_DMABase_DCR : stm32l1xx_tim.h
  • TIM_DMABase_DIER : stm32l1xx_tim.h
  • TIM_DMABase_EGR : stm32l1xx_tim.h
  • TIM_DMABase_OR : stm32l1xx_tim.h
  • TIM_DMABase_PSC : stm32l1xx_tim.h
  • TIM_DMABase_SMCR : stm32l1xx_tim.h
  • TIM_DMABase_SR : stm32l1xx_tim.h
  • TIM_DMABurstLength_10Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_10Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_11Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_11Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_12Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_12Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_13Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_13Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_14Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_14Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_15Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_15Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_16Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_16Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_17Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_17Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_18Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_18Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_1Byte : stm32l1xx_tim.h
  • TIM_DMABurstLength_1Transfer : stm32l1xx_tim.h
  • TIM_DMABurstLength_2Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_2Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_3Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_3Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_4Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_4Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_5Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_5Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_6Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_6Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_7Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_7Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_8Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_8Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_9Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_9Transfers : stm32l1xx_tim.h
  • TIM_DMACmd() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DMAConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DMAR_DMAB : stm32l1xx.h
  • TIM_EGR_CC1G : stm32l1xx.h
  • TIM_EGR_CC2G : stm32l1xx.h
  • TIM_EGR_CC3G : stm32l1xx.h
  • TIM_EGR_CC4G : stm32l1xx.h
  • TIM_EGR_TG : stm32l1xx.h
  • TIM_EGR_UG : stm32l1xx.h
  • TIM_EncoderInterfaceConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_EncoderMode_TI1 : stm32l1xx_tim.h
  • TIM_EncoderMode_TI12 : stm32l1xx_tim.h
  • TIM_EncoderMode_TI2 : stm32l1xx_tim.h
  • TIM_ETRClockMode1Config() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ETRClockMode2Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ETRConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_EventSource_CC1 : stm32l1xx_tim.h
  • TIM_EventSource_CC2 : stm32l1xx_tim.h
  • TIM_EventSource_CC3 : stm32l1xx_tim.h
  • TIM_EventSource_CC4 : stm32l1xx_tim.h
  • TIM_EventSource_Trigger : stm32l1xx_tim.h
  • TIM_EventSource_Update : stm32l1xx_tim.h
  • TIM_ExtTRGPolarity_Inverted : stm32l1xx_tim.h
  • TIM_ExtTRGPolarity_NonInverted : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV2 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV4 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV8 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_OFF : stm32l1xx_tim.h
  • TIM_FLAG_CC1 : stm32l1xx_tim.h
  • TIM_FLAG_CC1OF : stm32l1xx_tim.h
  • TIM_FLAG_CC2 : stm32l1xx_tim.h
  • TIM_FLAG_CC2OF : stm32l1xx_tim.h
  • TIM_FLAG_CC3 : stm32l1xx_tim.h
  • TIM_FLAG_CC3OF : stm32l1xx_tim.h
  • TIM_FLAG_CC4 : stm32l1xx_tim.h
  • TIM_FLAG_CC4OF : stm32l1xx_tim.h
  • TIM_FLAG_Trigger : stm32l1xx_tim.h
  • TIM_FLAG_Update : stm32l1xx_tim.h
  • TIM_ForcedAction_Active : stm32l1xx_tim.h
  • TIM_ForcedAction_InActive : stm32l1xx_tim.h
  • TIM_ForcedOC1Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC2Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC3Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC4Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GenerateEvent() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture1() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture2() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture3() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture4() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCounter() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetFlagStatus() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetITStatus() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetPrescaler() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ICInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ICPolarity_BothEdge : stm32l1xx_tim.h
  • TIM_ICPolarity_Falling : stm32l1xx_tim.h
  • TIM_ICPolarity_Rising : stm32l1xx_tim.h
  • TIM_ICPSC_DIV1 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV2 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV4 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV8 : stm32l1xx_tim.h
  • TIM_ICSelection_DirectTI : stm32l1xx_tim.h
  • TIM_ICSelection_IndirectTI : stm32l1xx_tim.h
  • TIM_ICSelection_TRC : stm32l1xx_tim.h
  • TIM_ICStructInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_InternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_IT_CC1 : stm32l1xx_tim.h
  • TIM_IT_CC2 : stm32l1xx_tim.h
  • TIM_IT_CC3 : stm32l1xx_tim.h
  • TIM_IT_CC4 : stm32l1xx_tim.h
  • TIM_IT_Trigger : stm32l1xx_tim.h
  • TIM_IT_Update : stm32l1xx_tim.h
  • TIM_ITConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ITRxExternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_MasterSlaveMode_Disable : stm32l1xx_tim.h
  • TIM_MasterSlaveMode_Enable : stm32l1xx_tim.h
  • TIM_OC1FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1PolarityConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC1PreloadConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC2FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2Init() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC2PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2PreloadConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC3FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3PolarityConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC3PreloadConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC4FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4Init() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OC4PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4PreloadConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_OCClear_Disable : stm32l1xx_tim.h
  • TIM_OCClear_Enable : stm32l1xx_tim.h
  • TIM_OCFast_Disable : stm32l1xx_tim.h
  • TIM_OCFast_Enable : stm32l1xx_tim.h
  • TIM_OCMode_Active : stm32l1xx_tim.h
  • TIM_OCMode_Inactive : stm32l1xx_tim.h
  • TIM_OCMode_PWM1 : stm32l1xx_tim.h
  • TIM_OCMode_PWM2 : stm32l1xx_tim.h
  • TIM_OCMode_Timing : stm32l1xx_tim.h
  • TIM_OCMode_Toggle : stm32l1xx_tim.h
  • TIM_OCPolarity_High : stm32l1xx_tim.h
  • TIM_OCPolarity_Low : stm32l1xx_tim.h
  • TIM_OCPreload_Disable : stm32l1xx_tim.h
  • TIM_OCPreload_Enable : stm32l1xx_tim.h
  • TIM_OCREFERENCECECLEAR_SOURCE : stm32l1xx_tim.h
  • TIM_OCReferenceClear_ETRF : stm32l1xx_tim.h
  • TIM_OCReferenceClear_OCREFCLR : stm32l1xx_tim.h
  • TIM_OCStructInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OPMode_Repetitive : stm32l1xx_tim.h
  • TIM_OPMode_Single : stm32l1xx_tim.h
  • TIM_OR_TI1RMP : stm32l1xx.h
  • TIM_OR_TI1RMP_0 : stm32l1xx.h
  • TIM_OR_TI1RMP_1 : stm32l1xx.h
  • TIM_OutputState_Disable : stm32l1xx_tim.h
  • TIM_OutputState_Enable : stm32l1xx_tim.h
  • TIM_PrescalerConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_PSC_PSC : stm32l1xx.h
  • TIM_PSCReloadMode_Immediate : stm32l1xx_tim.h
  • TIM_PSCReloadMode_Update : stm32l1xx_tim.h
  • TIM_PWMIConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_RemapConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SELECT_MASK : stm32l1xx_syscfg.c
  • TIM_Select_None : stm32l1xx_syscfg.h
  • TIM_Select_TIM2 : stm32l1xx_syscfg.h
  • TIM_Select_TIM3 : stm32l1xx_syscfg.h
  • TIM_Select_TIM4 : stm32l1xx_syscfg.h
  • TIM_SelectCCDMA() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectHallSensor() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectInputTrigger() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectMasterSlaveMode() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectOCREFClear() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectOCxM() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectOnePulseMode() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectOutputTrigger() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectSlaveMode() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetAutoreload() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetClockDivision() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCompare1() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetCompare2() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetCompare3() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCompare4() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCounter() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetIC1Prescaler() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetIC2Prescaler() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetIC3Prescaler() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetIC4Prescaler() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SlaveMode_External1 : stm32l1xx_tim.h
  • TIM_SlaveMode_Gated : stm32l1xx_tim.h
  • TIM_SlaveMode_Reset : stm32l1xx_tim.h
  • TIM_SlaveMode_Trigger : stm32l1xx_tim.h
  • TIM_SMCR_ECE : stm32l1xx.h
  • TIM_SMCR_ETF : stm32l1xx.h
  • TIM_SMCR_ETF_0 : stm32l1xx.h
  • TIM_SMCR_ETF_1 : stm32l1xx.h
  • TIM_SMCR_ETF_2 : stm32l1xx.h
  • TIM_SMCR_ETF_3 : stm32l1xx.h
  • TIM_SMCR_ETP : stm32l1xx.h
  • TIM_SMCR_ETPS : stm32l1xx.h
  • TIM_SMCR_ETPS_0 : stm32l1xx.h
  • TIM_SMCR_ETPS_1 : stm32l1xx.h
  • TIM_SMCR_MSM : stm32l1xx.h
  • TIM_SMCR_OCCS : stm32l1xx.h
  • TIM_SMCR_SMS : stm32l1xx.h
  • TIM_SMCR_SMS_0 : stm32l1xx.h
  • TIM_SMCR_SMS_1 : stm32l1xx.h
  • TIM_SMCR_SMS_2 : stm32l1xx.h
  • TIM_SMCR_TS : stm32l1xx.h
  • TIM_SMCR_TS_0 : stm32l1xx.h
  • TIM_SMCR_TS_1 : stm32l1xx.h
  • TIM_SMCR_TS_2 : stm32l1xx.h
  • TIM_SR_CC1IF : stm32l1xx.h
  • TIM_SR_CC1OF : stm32l1xx.h
  • TIM_SR_CC2IF : stm32l1xx.h
  • TIM_SR_CC2OF : stm32l1xx.h
  • TIM_SR_CC3IF : stm32l1xx.h
  • TIM_SR_CC3OF : stm32l1xx.h
  • TIM_SR_CC4IF : stm32l1xx.h
  • TIM_SR_CC4OF : stm32l1xx.h
  • TIM_SR_TIF : stm32l1xx.h
  • TIM_SR_UIF : stm32l1xx.h
  • TIM_TimeBaseInit() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_TimeBaseStructInit() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_TIxExternalCLK1Source_TI1 : stm32l1xx_tim.h
  • TIM_TIxExternalCLK1Source_TI1ED : stm32l1xx_tim.h
  • TIM_TIxExternalCLK1Source_TI2 : stm32l1xx_tim.h
  • TIM_TIxExternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_TRGOSource_Enable : stm32l1xx_tim.h
  • TIM_TRGOSource_OC1 : stm32l1xx_tim.h
  • TIM_TRGOSource_OC1Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC2Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC3Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC4Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_Reset : stm32l1xx_tim.h
  • TIM_TRGOSource_Update : stm32l1xx_tim.h
  • TIM_TS_ETRF : stm32l1xx_tim.h
  • TIM_TS_ITR0 : stm32l1xx_tim.h
  • TIM_TS_ITR1 : stm32l1xx_tim.h
  • TIM_TS_ITR2 : stm32l1xx_tim.h
  • TIM_TS_ITR3 : stm32l1xx_tim.h
  • TIM_TS_TI1F_ED : stm32l1xx_tim.h
  • TIM_TS_TI1FP1 : stm32l1xx_tim.h
  • TIM_TS_TI2FP2 : stm32l1xx_tim.h
  • TIM_UpdateDisableConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_UpdateRequestConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_UpdateSource_Global : stm32l1xx_tim.h
  • TIM_UpdateSource_Regular : stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART4 : stm32l1xx.h
  • UART4_BASE : stm32l1xx.h
  • UART4_IRQn : stm32l1xx.h
  • UART5 : stm32l1xx.h
  • UART5_BASE : stm32l1xx.h
  • UART5_IRQn : stm32l1xx.h
  • UDR_BitNumber : stm32l1xx_lcd.c
  • ULP_BitNumber : stm32l1xx_pwr.c
  • UsageFault_IRQn : stm32l1xx.h
  • USART1 : stm32l1xx.h
  • USART1_BASE : stm32l1xx.h
  • USART1_IRQn : stm32l1xx.h
  • USART2 : stm32l1xx.h
  • USART2_BASE : stm32l1xx.h
  • USART2_IRQn : stm32l1xx.h
  • USART3 : stm32l1xx.h
  • USART3_BASE : stm32l1xx.h
  • USART3_IRQn : stm32l1xx.h
  • USART_BRR_DIV_FRACTION : stm32l1xx.h
  • USART_BRR_DIV_MANTISSA : stm32l1xx.h
  • USART_ClearFlag() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ClearITPendingBit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_Clock_Disable : stm32l1xx_usart.h
  • USART_Clock_Enable : stm32l1xx_usart.h
  • USART_ClockInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ClockStructInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_Cmd() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_CPHA_1Edge : stm32l1xx_usart.h
  • USART_CPHA_2Edge : stm32l1xx_usart.h
  • USART_CPOL_High : stm32l1xx_usart.h
  • USART_CPOL_Low : stm32l1xx_usart.h
  • USART_CR1_IDLEIE : stm32l1xx.h
  • USART_CR1_M : stm32l1xx.h
  • USART_CR1_OVER8 : stm32l1xx.h
  • USART_CR1_PCE : stm32l1xx.h
  • USART_CR1_PEIE : stm32l1xx.h
  • USART_CR1_PS : stm32l1xx.h
  • USART_CR1_RE : stm32l1xx.h
  • USART_CR1_RWU : stm32l1xx.h
  • USART_CR1_RXNEIE : stm32l1xx.h
  • USART_CR1_SBK : stm32l1xx.h
  • USART_CR1_TCIE : stm32l1xx.h
  • USART_CR1_TE : stm32l1xx.h
  • USART_CR1_TXEIE : stm32l1xx.h
  • USART_CR1_UE : stm32l1xx.h
  • USART_CR1_WAKE : stm32l1xx.h
  • USART_CR2_ADD : stm32l1xx.h
  • USART_CR2_CLKEN : stm32l1xx.h
  • USART_CR2_CPHA : stm32l1xx.h
  • USART_CR2_CPOL : stm32l1xx.h
  • USART_CR2_LBCL : stm32l1xx.h
  • USART_CR2_LBDIE : stm32l1xx.h
  • USART_CR2_LBDL : stm32l1xx.h
  • USART_CR2_LINEN : stm32l1xx.h
  • USART_CR2_STOP : stm32l1xx.h
  • USART_CR2_STOP_0 : stm32l1xx.h
  • USART_CR2_STOP_1 : stm32l1xx.h
  • USART_CR3_CTSE : stm32l1xx.h
  • USART_CR3_CTSIE : stm32l1xx.h
  • USART_CR3_DMAR : stm32l1xx.h
  • USART_CR3_DMAT : stm32l1xx.h
  • USART_CR3_EIE : stm32l1xx.h
  • USART_CR3_HDSEL : stm32l1xx.h
  • USART_CR3_IREN : stm32l1xx.h
  • USART_CR3_IRLP : stm32l1xx.h
  • USART_CR3_NACK : stm32l1xx.h
  • USART_CR3_ONEBIT : stm32l1xx.h
  • USART_CR3_RTSE : stm32l1xx.h
  • USART_CR3_SCEN : stm32l1xx.h
  • USART_DeInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_DMACmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_DMAReq_Rx : stm32l1xx_usart.h
  • USART_DMAReq_Tx : stm32l1xx_usart.h
  • USART_DR_DR : stm32l1xx.h
  • USART_FLAG_CTS : stm32l1xx_usart.h
  • USART_FLAG_FE : stm32l1xx_usart.h
  • USART_FLAG_IDLE : stm32l1xx_usart.h
  • USART_FLAG_LBD : stm32l1xx_usart.h
  • USART_FLAG_NE : stm32l1xx_usart.h
  • USART_FLAG_ORE : stm32l1xx_usart.h
  • USART_FLAG_PE : stm32l1xx_usart.h
  • USART_FLAG_RXNE : stm32l1xx_usart.h
  • USART_FLAG_TC : stm32l1xx_usart.h
  • USART_FLAG_TXE : stm32l1xx_usart.h
  • USART_GetFlagStatus() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_GetITStatus() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_GTPR_GT : stm32l1xx.h
  • USART_GTPR_PSC : stm32l1xx.h
  • USART_GTPR_PSC_0 : stm32l1xx.h
  • USART_GTPR_PSC_1 : stm32l1xx.h
  • USART_GTPR_PSC_2 : stm32l1xx.h
  • USART_GTPR_PSC_3 : stm32l1xx.h
  • USART_GTPR_PSC_4 : stm32l1xx.h
  • USART_GTPR_PSC_5 : stm32l1xx.h
  • USART_GTPR_PSC_6 : stm32l1xx.h
  • USART_GTPR_PSC_7 : stm32l1xx.h
  • USART_HalfDuplexCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_HardwareFlowControl_CTS : stm32l1xx_usart.h
  • USART_HardwareFlowControl_None : stm32l1xx_usart.h
  • USART_HardwareFlowControl_RTS : stm32l1xx_usart.h
  • USART_HardwareFlowControl_RTS_CTS : stm32l1xx_usart.h
  • USART_Init() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_IrDACmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_IrDAConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_IrDAMode_LowPower : stm32l1xx_usart.h
  • USART_IrDAMode_Normal : stm32l1xx_usart.h
  • USART_IT_CTS : stm32l1xx_usart.h
  • USART_IT_ERR : stm32l1xx_usart.h
  • USART_IT_FE : stm32l1xx_usart.h
  • USART_IT_IDLE : stm32l1xx_usart.h
  • USART_IT_LBD : stm32l1xx_usart.h
  • USART_IT_NE : stm32l1xx_usart.h
  • USART_IT_ORE : stm32l1xx_usart.h
  • USART_IT_ORE_ER : stm32l1xx_usart.h
  • USART_IT_ORE_RX : stm32l1xx_usart.h
  • USART_IT_PE : stm32l1xx_usart.h
  • USART_IT_RXNE : stm32l1xx_usart.h
  • USART_IT_TC : stm32l1xx_usart.h
  • USART_IT_TXE : stm32l1xx_usart.h
  • USART_ITConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_LastBit_Disable : stm32l1xx_usart.h
  • USART_LastBit_Enable : stm32l1xx_usart.h
  • USART_LINBreakDetectLength_10b : stm32l1xx_usart.h
  • USART_LINBreakDetectLength_11b : stm32l1xx_usart.h
  • USART_LINBreakDetectLengthConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_LINCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_Mode_Rx : stm32l1xx_usart.h
  • USART_Mode_Tx : stm32l1xx_usart.h
  • USART_OneBitMethodCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_OverSampling8Cmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_Parity_Even : stm32l1xx_usart.h
  • USART_Parity_No : stm32l1xx_usart.h
  • USART_Parity_Odd : stm32l1xx_usart.h
  • USART_ReceiveData() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ReceiverWakeUpCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SendBreak() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SendData() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SetAddress() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SetGuardTime() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SetPrescaler() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SmartCardCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SmartCardNACKCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SR_CTS : stm32l1xx.h
  • USART_SR_FE : stm32l1xx.h
  • USART_SR_IDLE : stm32l1xx.h
  • USART_SR_LBD : stm32l1xx.h
  • USART_SR_NE : stm32l1xx.h
  • USART_SR_ORE : stm32l1xx.h
  • USART_SR_PE : stm32l1xx.h
  • USART_SR_RXNE : stm32l1xx.h
  • USART_SR_TC : stm32l1xx.h
  • USART_SR_TXE : stm32l1xx.h
  • USART_StopBits_0_5 : stm32l1xx_usart.h
  • USART_StopBits_1 : stm32l1xx_usart.h
  • USART_StopBits_1_5 : stm32l1xx_usart.h
  • USART_StopBits_2 : stm32l1xx_usart.h
  • USART_StructInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_WakeUp_AddressMark : stm32l1xx_usart.h
  • USART_WakeUp_IdleLine : stm32l1xx_usart.h
  • USART_WakeUpConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_WordLength_8b : stm32l1xx_usart.h
  • USART_WordLength_9b : stm32l1xx_usart.h
  • USB_ADDR0_RX_ADDR0_RX : stm32l1xx.h
  • USB_ADDR0_TX_ADDR0_TX : stm32l1xx.h
  • USB_ADDR1_RX_ADDR1_RX : stm32l1xx.h
  • USB_ADDR1_TX_ADDR1_TX : stm32l1xx.h
  • USB_ADDR2_RX_ADDR2_RX : stm32l1xx.h
  • USB_ADDR2_TX_ADDR2_TX : stm32l1xx.h
  • USB_ADDR3_RX_ADDR3_RX : stm32l1xx.h
  • USB_ADDR3_TX_ADDR3_TX : stm32l1xx.h
  • USB_ADDR4_RX_ADDR4_RX : stm32l1xx.h
  • USB_ADDR4_TX_ADDR4_TX : stm32l1xx.h
  • USB_ADDR5_RX_ADDR5_RX : stm32l1xx.h
  • USB_ADDR5_TX_ADDR5_TX : stm32l1xx.h
  • USB_ADDR6_RX_ADDR6_RX : stm32l1xx.h
  • USB_ADDR6_TX_ADDR6_TX : stm32l1xx.h
  • USB_ADDR7_RX_ADDR7_RX : stm32l1xx.h
  • USB_ADDR7_TX_ADDR7_TX : stm32l1xx.h
  • USB_BTABLE_BTABLE : stm32l1xx.h
  • USB_CNTR_CTRM : stm32l1xx.h
  • USB_CNTR_ERRM : stm32l1xx.h
  • USB_CNTR_ESOFM : stm32l1xx.h
  • USB_CNTR_FRES : stm32l1xx.h
  • USB_CNTR_FSUSP : stm32l1xx.h
  • USB_CNTR_LP_MODE : stm32l1xx.h
  • USB_CNTR_PDWN : stm32l1xx.h
  • USB_CNTR_PMAOVRM : stm32l1xx.h
  • USB_CNTR_RESETM : stm32l1xx.h
  • USB_CNTR_RESUME : stm32l1xx.h
  • USB_CNTR_SOFM : stm32l1xx.h
  • USB_CNTR_SUSPM : stm32l1xx.h
  • USB_CNTR_WKUPM : stm32l1xx.h
  • USB_COUNT0_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_COUNT0_RX_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT0_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_COUNT0_RX_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT0_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT0_RX_COUNT0_RX : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT0_TX_0_COUNT0_TX_0 : stm32l1xx.h
  • USB_COUNT0_TX_1_COUNT0_TX_1 : stm32l1xx.h
  • USB_COUNT0_TX_COUNT0_TX : stm32l1xx.h
  • USB_COUNT1_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_COUNT1_RX_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT1_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_COUNT1_RX_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT1_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT1_RX_COUNT1_RX : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT1_TX_0_COUNT1_TX_0 : stm32l1xx.h
  • USB_COUNT1_TX_1_COUNT1_TX_1 : stm32l1xx.h
  • USB_COUNT1_TX_COUNT1_TX : stm32l1xx.h
  • USB_COUNT2_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_COUNT2_RX_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT2_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_COUNT2_RX_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT2_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT2_RX_COUNT2_RX : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT2_TX_0_COUNT2_TX_0 : stm32l1xx.h
  • USB_COUNT2_TX_1_COUNT2_TX_1 : stm32l1xx.h
  • USB_COUNT2_TX_COUNT2_TX : stm32l1xx.h
  • USB_COUNT3_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_COUNT3_RX_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT3_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_COUNT3_RX_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT3_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT3_RX_COUNT3_RX : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT3_TX_0_COUNT3_TX_0 : stm32l1xx.h
  • USB_COUNT3_TX_1_COUNT3_TX_1 : stm32l1xx.h
  • USB_COUNT3_TX_COUNT3_TX : stm32l1xx.h
  • USB_COUNT4_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_COUNT4_RX_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT4_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_COUNT4_RX_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT4_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT4_RX_COUNT4_RX : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT4_TX_0_COUNT4_TX_0 : stm32l1xx.h
  • USB_COUNT4_TX_1_COUNT4_TX_1 : stm32l1xx.h
  • USB_COUNT4_TX_COUNT4_TX : stm32l1xx.h
  • USB_COUNT5_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_COUNT5_RX_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT5_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_COUNT5_RX_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT5_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT5_RX_COUNT5_RX : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT5_TX_0_COUNT5_TX_0 : stm32l1xx.h
  • USB_COUNT5_TX_1_COUNT5_TX_1 : stm32l1xx.h
  • USB_COUNT5_TX_COUNT5_TX : stm32l1xx.h
  • USB_COUNT6_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_COUNT6_RX_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT6_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_COUNT6_RX_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT6_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT6_RX_COUNT6_RX : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT6_TX_0_COUNT6_TX_0 : stm32l1xx.h
  • USB_COUNT6_TX_1_COUNT6_TX_1 : stm32l1xx.h
  • USB_COUNT6_TX_COUNT6_TX : stm32l1xx.h
  • USB_COUNT7_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_COUNT7_RX_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT7_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_COUNT7_RX_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT7_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT7_RX_COUNT7_RX : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT7_TX_0_COUNT7_TX_0 : stm32l1xx.h
  • USB_COUNT7_TX_1_COUNT7_TX_1 : stm32l1xx.h
  • USB_COUNT7_TX_COUNT7_TX : stm32l1xx.h
  • USB_DADDR_ADD : stm32l1xx.h
  • USB_DADDR_ADD0 : stm32l1xx.h
  • USB_DADDR_ADD1 : stm32l1xx.h
  • USB_DADDR_ADD2 : stm32l1xx.h
  • USB_DADDR_ADD3 : stm32l1xx.h
  • USB_DADDR_ADD4 : stm32l1xx.h
  • USB_DADDR_ADD5 : stm32l1xx.h
  • USB_DADDR_ADD6 : stm32l1xx.h
  • USB_DADDR_EF : stm32l1xx.h
  • USB_EP0R_CTR_RX : stm32l1xx.h
  • USB_EP0R_CTR_TX : stm32l1xx.h
  • USB_EP0R_DTOG_RX : stm32l1xx.h
  • USB_EP0R_DTOG_TX : stm32l1xx.h
  • USB_EP0R_EA : stm32l1xx.h
  • USB_EP0R_EP_KIND : stm32l1xx.h
  • USB_EP0R_EP_TYPE : stm32l1xx.h
  • USB_EP0R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP0R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP0R_SETUP : stm32l1xx.h
  • USB_EP0R_STAT_RX : stm32l1xx.h
  • USB_EP0R_STAT_RX_0 : stm32l1xx.h
  • USB_EP0R_STAT_RX_1 : stm32l1xx.h
  • USB_EP0R_STAT_TX : stm32l1xx.h
  • USB_EP0R_STAT_TX_0 : stm32l1xx.h
  • USB_EP0R_STAT_TX_1 : stm32l1xx.h
  • USB_EP1R_CTR_RX : stm32l1xx.h
  • USB_EP1R_CTR_TX : stm32l1xx.h
  • USB_EP1R_DTOG_RX : stm32l1xx.h
  • USB_EP1R_DTOG_TX : stm32l1xx.h
  • USB_EP1R_EA : stm32l1xx.h
  • USB_EP1R_EP_KIND : stm32l1xx.h
  • USB_EP1R_EP_TYPE : stm32l1xx.h
  • USB_EP1R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP1R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP1R_SETUP : stm32l1xx.h
  • USB_EP1R_STAT_RX : stm32l1xx.h
  • USB_EP1R_STAT_RX_0 : stm32l1xx.h
  • USB_EP1R_STAT_RX_1 : stm32l1xx.h
  • USB_EP1R_STAT_TX : stm32l1xx.h
  • USB_EP1R_STAT_TX_0 : stm32l1xx.h
  • USB_EP1R_STAT_TX_1 : stm32l1xx.h
  • USB_EP2R_CTR_RX : stm32l1xx.h
  • USB_EP2R_CTR_TX : stm32l1xx.h
  • USB_EP2R_DTOG_RX : stm32l1xx.h
  • USB_EP2R_DTOG_TX : stm32l1xx.h
  • USB_EP2R_EA : stm32l1xx.h
  • USB_EP2R_EP_KIND : stm32l1xx.h
  • USB_EP2R_EP_TYPE : stm32l1xx.h
  • USB_EP2R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP2R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP2R_SETUP : stm32l1xx.h
  • USB_EP2R_STAT_RX : stm32l1xx.h
  • USB_EP2R_STAT_RX_0 : stm32l1xx.h
  • USB_EP2R_STAT_RX_1 : stm32l1xx.h
  • USB_EP2R_STAT_TX : stm32l1xx.h
  • USB_EP2R_STAT_TX_0 : stm32l1xx.h
  • USB_EP2R_STAT_TX_1 : stm32l1xx.h
  • USB_EP3R_CTR_RX : stm32l1xx.h
  • USB_EP3R_CTR_TX : stm32l1xx.h
  • USB_EP3R_DTOG_RX : stm32l1xx.h
  • USB_EP3R_DTOG_TX : stm32l1xx.h
  • USB_EP3R_EA : stm32l1xx.h
  • USB_EP3R_EP_KIND : stm32l1xx.h
  • USB_EP3R_EP_TYPE : stm32l1xx.h
  • USB_EP3R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP3R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP3R_SETUP : stm32l1xx.h
  • USB_EP3R_STAT_RX : stm32l1xx.h
  • USB_EP3R_STAT_RX_0 : stm32l1xx.h
  • USB_EP3R_STAT_RX_1 : stm32l1xx.h
  • USB_EP3R_STAT_TX : stm32l1xx.h
  • USB_EP3R_STAT_TX_0 : stm32l1xx.h
  • USB_EP3R_STAT_TX_1 : stm32l1xx.h
  • USB_EP4R_CTR_RX : stm32l1xx.h
  • USB_EP4R_CTR_TX : stm32l1xx.h
  • USB_EP4R_DTOG_RX : stm32l1xx.h
  • USB_EP4R_DTOG_TX : stm32l1xx.h
  • USB_EP4R_EA : stm32l1xx.h
  • USB_EP4R_EP_KIND : stm32l1xx.h
  • USB_EP4R_EP_TYPE : stm32l1xx.h
  • USB_EP4R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP4R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP4R_SETUP : stm32l1xx.h
  • USB_EP4R_STAT_RX : stm32l1xx.h
  • USB_EP4R_STAT_RX_0 : stm32l1xx.h
  • USB_EP4R_STAT_RX_1 : stm32l1xx.h
  • USB_EP4R_STAT_TX : stm32l1xx.h
  • USB_EP4R_STAT_TX_0 : stm32l1xx.h
  • USB_EP4R_STAT_TX_1 : stm32l1xx.h
  • USB_EP5R_CTR_RX : stm32l1xx.h
  • USB_EP5R_CTR_TX : stm32l1xx.h
  • USB_EP5R_DTOG_RX : stm32l1xx.h
  • USB_EP5R_DTOG_TX : stm32l1xx.h
  • USB_EP5R_EA : stm32l1xx.h
  • USB_EP5R_EP_KIND : stm32l1xx.h
  • USB_EP5R_EP_TYPE : stm32l1xx.h
  • USB_EP5R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP5R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP5R_SETUP : stm32l1xx.h
  • USB_EP5R_STAT_RX : stm32l1xx.h
  • USB_EP5R_STAT_RX_0 : stm32l1xx.h
  • USB_EP5R_STAT_RX_1 : stm32l1xx.h
  • USB_EP5R_STAT_TX : stm32l1xx.h
  • USB_EP5R_STAT_TX_0 : stm32l1xx.h
  • USB_EP5R_STAT_TX_1 : stm32l1xx.h
  • USB_EP6R_CTR_RX : stm32l1xx.h
  • USB_EP6R_CTR_TX : stm32l1xx.h
  • USB_EP6R_DTOG_RX : stm32l1xx.h
  • USB_EP6R_DTOG_TX : stm32l1xx.h
  • USB_EP6R_EA : stm32l1xx.h
  • USB_EP6R_EP_KIND : stm32l1xx.h
  • USB_EP6R_EP_TYPE : stm32l1xx.h
  • USB_EP6R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP6R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP6R_SETUP : stm32l1xx.h
  • USB_EP6R_STAT_RX : stm32l1xx.h
  • USB_EP6R_STAT_RX_0 : stm32l1xx.h
  • USB_EP6R_STAT_RX_1 : stm32l1xx.h
  • USB_EP6R_STAT_TX : stm32l1xx.h
  • USB_EP6R_STAT_TX_0 : stm32l1xx.h
  • USB_EP6R_STAT_TX_1 : stm32l1xx.h
  • USB_EP7R_CTR_RX : stm32l1xx.h
  • USB_EP7R_CTR_TX : stm32l1xx.h
  • USB_EP7R_DTOG_RX : stm32l1xx.h
  • USB_EP7R_DTOG_TX : stm32l1xx.h
  • USB_EP7R_EA : stm32l1xx.h
  • USB_EP7R_EP_KIND : stm32l1xx.h
  • USB_EP7R_EP_TYPE : stm32l1xx.h
  • USB_EP7R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP7R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP7R_SETUP : stm32l1xx.h
  • USB_EP7R_STAT_RX : stm32l1xx.h
  • USB_EP7R_STAT_RX_0 : stm32l1xx.h
  • USB_EP7R_STAT_RX_1 : stm32l1xx.h
  • USB_EP7R_STAT_TX : stm32l1xx.h
  • USB_EP7R_STAT_TX_0 : stm32l1xx.h
  • USB_EP7R_STAT_TX_1 : stm32l1xx.h
  • USB_FNR_FN : stm32l1xx.h
  • USB_FNR_LCK : stm32l1xx.h
  • USB_FNR_LSOF : stm32l1xx.h
  • USB_FNR_RXDM : stm32l1xx.h
  • USB_FNR_RXDP : stm32l1xx.h
  • USB_FS_WKUP_IRQn : stm32l1xx.h
  • USB_HP_IRQn : stm32l1xx.h
  • USB_ISTR_CTR : stm32l1xx.h
  • USB_ISTR_DIR : stm32l1xx.h
  • USB_ISTR_EP_ID : stm32l1xx.h
  • USB_ISTR_ERR : stm32l1xx.h
  • USB_ISTR_ESOF : stm32l1xx.h
  • USB_ISTR_PMAOVR : stm32l1xx.h
  • USB_ISTR_RESET : stm32l1xx.h
  • USB_ISTR_SOF : stm32l1xx.h
  • USB_ISTR_SUSP : stm32l1xx.h
  • USB_ISTR_WKUP : stm32l1xx.h
  • USB_LP_IRQn : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VECT_TAB_OFFSET : system_stm32l1xx.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WaitForLastOperation() : stm32l1xx_flash_ramfunc.c
  • WRITE_REG : stm32l1xx.h
  • WRP01_MASK : stm32l1xx_flash.c
  • WRP1011_MASK : stm32l1xx_flash.c
  • WRP23_MASK : stm32l1xx_flash.c
  • WRP45_MASK : stm32l1xx_flash.c
  • WRP67_MASK : stm32l1xx_flash.c
  • WRP89_MASK : stm32l1xx_flash.c
  • WWDG : stm32l1xx.h
  • WWDG_BASE : stm32l1xx.h
  • WWDG_CFR_EWI : stm32l1xx.h
  • WWDG_CFR_W : stm32l1xx.h
  • WWDG_CFR_W0 : stm32l1xx.h
  • WWDG_CFR_W1 : stm32l1xx.h
  • WWDG_CFR_W2 : stm32l1xx.h
  • WWDG_CFR_W3 : stm32l1xx.h
  • WWDG_CFR_W4 : stm32l1xx.h
  • WWDG_CFR_W5 : stm32l1xx.h
  • WWDG_CFR_W6 : stm32l1xx.h
  • WWDG_CFR_WDGTB : stm32l1xx.h
  • WWDG_CFR_WDGTB0 : stm32l1xx.h
  • WWDG_CFR_WDGTB1 : stm32l1xx.h
  • WWDG_ClearFlag() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_CR_T : stm32l1xx.h
  • WWDG_CR_T0 : stm32l1xx.h
  • WWDG_CR_T1 : stm32l1xx.h
  • WWDG_CR_T2 : stm32l1xx.h
  • WWDG_CR_T3 : stm32l1xx.h
  • WWDG_CR_T4 : stm32l1xx.h
  • WWDG_CR_T5 : stm32l1xx.h
  • WWDG_CR_T6 : stm32l1xx.h
  • WWDG_CR_WDGA : stm32l1xx.h
  • WWDG_DeInit() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_Enable() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_EnableIT() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_GetFlagStatus() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_IRQn : stm32l1xx.h
  • WWDG_OFFSET : stm32l1xx_wwdg.c
  • WWDG_Prescaler_1 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_2 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_4 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_8 : stm32l1xx_wwdg.h
  • WWDG_SetCounter() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_SetPrescaler() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_SetWindowValue() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_SR_EWIF : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- _ -

  • __CM3_REV : stm32l1xx.h
  • __MPU_PRESENT : stm32l1xx.h
  • __NVIC_PRIO_BITS : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_MAIN : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_RC : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_SUB1 : stm32l1xx.h
  • __STM32L1XX_STDPERIPH_VERSION_SUB2 : stm32l1xx.h
  • __Vendor_SysTickConfig : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- j -

  • JDR_OFFSET : stm32l1xx_adc.c
  • JSQR_JL_RESET : stm32l1xx_adc.c
  • JSQR_JL_SET : stm32l1xx_adc.c
  • JSQR_JSQ_SET : stm32l1xx_adc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- k -

  • KR_KEY_ENABLE : stm32l1xx_iwdg.c
  • KR_KEY_RELOAD : stm32l1xx_iwdg.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- l -

  • LCD : stm32l1xx.h
  • LCD_BASE : stm32l1xx.h
  • LCD_Bias_1_2 : stm32l1xx_lcd.h
  • LCD_Bias_1_3 : stm32l1xx_lcd.h
  • LCD_Bias_1_4 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div1024 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div128 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div16 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div256 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div32 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div512 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div64 : stm32l1xx_lcd.h
  • LCD_BlinkFrequency_Div8 : stm32l1xx_lcd.h
  • LCD_BlinkMode_AllSEG_AllCOM : stm32l1xx_lcd.h
  • LCD_BlinkMode_Off : stm32l1xx_lcd.h
  • LCD_BlinkMode_SEG0_AllCOM : stm32l1xx_lcd.h
  • LCD_BlinkMode_SEG0_COM0 : stm32l1xx_lcd.h
  • LCD_CLR_SOFC : stm32l1xx.h
  • LCD_CLR_UDDC : stm32l1xx.h
  • LCD_Contrast_Level_0 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_1 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_2 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_3 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_4 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_5 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_6 : stm32l1xx_lcd.h
  • LCD_Contrast_Level_7 : stm32l1xx_lcd.h
  • LCD_CR_BIAS : stm32l1xx.h
  • LCD_CR_BIAS_0 : stm32l1xx.h
  • LCD_CR_BIAS_1 : stm32l1xx.h
  • LCD_CR_DUTY : stm32l1xx.h
  • LCD_CR_DUTY_0 : stm32l1xx.h
  • LCD_CR_DUTY_1 : stm32l1xx.h
  • LCD_CR_DUTY_2 : stm32l1xx.h
  • LCD_CR_LCDEN : stm32l1xx.h
  • LCD_CR_MUX_SEG : stm32l1xx.h
  • LCD_CR_VSEL : stm32l1xx.h
  • LCD_DeadTime_0 : stm32l1xx_lcd.h
  • LCD_DeadTime_1 : stm32l1xx_lcd.h
  • LCD_DeadTime_2 : stm32l1xx_lcd.h
  • LCD_DeadTime_3 : stm32l1xx_lcd.h
  • LCD_DeadTime_4 : stm32l1xx_lcd.h
  • LCD_DeadTime_5 : stm32l1xx_lcd.h
  • LCD_DeadTime_6 : stm32l1xx_lcd.h
  • LCD_DeadTime_7 : stm32l1xx_lcd.h
  • LCD_Divider_16 : stm32l1xx_lcd.h
  • LCD_Divider_17 : stm32l1xx_lcd.h
  • LCD_Divider_18 : stm32l1xx_lcd.h
  • LCD_Divider_19 : stm32l1xx_lcd.h
  • LCD_Divider_20 : stm32l1xx_lcd.h
  • LCD_Divider_21 : stm32l1xx_lcd.h
  • LCD_Divider_22 : stm32l1xx_lcd.h
  • LCD_Divider_23 : stm32l1xx_lcd.h
  • LCD_Divider_24 : stm32l1xx_lcd.h
  • LCD_Divider_25 : stm32l1xx_lcd.h
  • LCD_Divider_26 : stm32l1xx_lcd.h
  • LCD_Divider_27 : stm32l1xx_lcd.h
  • LCD_Divider_28 : stm32l1xx_lcd.h
  • LCD_Divider_29 : stm32l1xx_lcd.h
  • LCD_Divider_30 : stm32l1xx_lcd.h
  • LCD_Divider_31 : stm32l1xx_lcd.h
  • LCD_Duty_1_2 : stm32l1xx_lcd.h
  • LCD_Duty_1_3 : stm32l1xx_lcd.h
  • LCD_Duty_1_4 : stm32l1xx_lcd.h
  • LCD_Duty_1_8 : stm32l1xx_lcd.h
  • LCD_Duty_Static : stm32l1xx_lcd.h
  • LCD_FCR_BLINK : stm32l1xx.h
  • LCD_FCR_BLINK_0 : stm32l1xx.h
  • LCD_FCR_BLINK_1 : stm32l1xx.h
  • LCD_FCR_BLINKF : stm32l1xx.h
  • LCD_FCR_BLINKF_0 : stm32l1xx.h
  • LCD_FCR_BLINKF_1 : stm32l1xx.h
  • LCD_FCR_BLINKF_2 : stm32l1xx.h
  • LCD_FCR_CC : stm32l1xx.h
  • LCD_FCR_CC_0 : stm32l1xx.h
  • LCD_FCR_CC_1 : stm32l1xx.h
  • LCD_FCR_CC_2 : stm32l1xx.h
  • LCD_FCR_DEAD : stm32l1xx.h
  • LCD_FCR_DEAD_0 : stm32l1xx.h
  • LCD_FCR_DEAD_1 : stm32l1xx.h
  • LCD_FCR_DEAD_2 : stm32l1xx.h
  • LCD_FCR_DIV : stm32l1xx.h
  • LCD_FCR_HD : stm32l1xx.h
  • LCD_FCR_PON : stm32l1xx.h
  • LCD_FCR_PON_0 : stm32l1xx.h
  • LCD_FCR_PON_1 : stm32l1xx.h
  • LCD_FCR_PON_2 : stm32l1xx.h
  • LCD_FCR_PS : stm32l1xx.h
  • LCD_FCR_SOFIE : stm32l1xx.h
  • LCD_FCR_UDDIE : stm32l1xx.h
  • LCD_FLAG_ENS : stm32l1xx_lcd.h
  • LCD_FLAG_FCRSF : stm32l1xx_lcd.h
  • LCD_FLAG_RDY : stm32l1xx_lcd.h
  • LCD_FLAG_SOF : stm32l1xx_lcd.h
  • LCD_FLAG_UDD : stm32l1xx_lcd.h
  • LCD_FLAG_UDR : stm32l1xx_lcd.h
  • LCD_IT_SOF : stm32l1xx_lcd.h
  • LCD_IT_UDD : stm32l1xx_lcd.h
  • LCD_OFFSET : stm32l1xx_lcd.c
  • LCD_Prescaler_1 : stm32l1xx_lcd.h
  • LCD_Prescaler_1024 : stm32l1xx_lcd.h
  • LCD_Prescaler_128 : stm32l1xx_lcd.h
  • LCD_Prescaler_16 : stm32l1xx_lcd.h
  • LCD_Prescaler_16384 : stm32l1xx_lcd.h
  • LCD_Prescaler_2 : stm32l1xx_lcd.h
  • LCD_Prescaler_2048 : stm32l1xx_lcd.h
  • LCD_Prescaler_256 : stm32l1xx_lcd.h
  • LCD_Prescaler_32 : stm32l1xx_lcd.h
  • LCD_Prescaler_32768 : stm32l1xx_lcd.h
  • LCD_Prescaler_4 : stm32l1xx_lcd.h
  • LCD_Prescaler_4096 : stm32l1xx_lcd.h
  • LCD_Prescaler_512 : stm32l1xx_lcd.h
  • LCD_Prescaler_64 : stm32l1xx_lcd.h
  • LCD_Prescaler_8 : stm32l1xx_lcd.h
  • LCD_Prescaler_8192 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_0 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_1 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_2 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_3 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_4 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_5 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_6 : stm32l1xx_lcd.h
  • LCD_PulseOnDuration_7 : stm32l1xx_lcd.h
  • LCD_RAM_SEGMENT_DATA : stm32l1xx.h
  • LCD_RAMRegister_0 : stm32l1xx_lcd.h
  • LCD_RAMRegister_1 : stm32l1xx_lcd.h
  • LCD_RAMRegister_10 : stm32l1xx_lcd.h
  • LCD_RAMRegister_11 : stm32l1xx_lcd.h
  • LCD_RAMRegister_12 : stm32l1xx_lcd.h
  • LCD_RAMRegister_13 : stm32l1xx_lcd.h
  • LCD_RAMRegister_14 : stm32l1xx_lcd.h
  • LCD_RAMRegister_15 : stm32l1xx_lcd.h
  • LCD_RAMRegister_2 : stm32l1xx_lcd.h
  • LCD_RAMRegister_3 : stm32l1xx_lcd.h
  • LCD_RAMRegister_4 : stm32l1xx_lcd.h
  • LCD_RAMRegister_5 : stm32l1xx_lcd.h
  • LCD_RAMRegister_6 : stm32l1xx_lcd.h
  • LCD_RAMRegister_7 : stm32l1xx_lcd.h
  • LCD_RAMRegister_8 : stm32l1xx_lcd.h
  • LCD_RAMRegister_9 : stm32l1xx_lcd.h
  • LCD_SR_ENS : stm32l1xx.h
  • LCD_SR_FCRSR : stm32l1xx.h
  • LCD_SR_RDY : stm32l1xx.h
  • LCD_SR_SOF : stm32l1xx.h
  • LCD_SR_UDD : stm32l1xx.h
  • LCD_SR_UDR : stm32l1xx.h
  • LCD_VoltageSource_External : stm32l1xx_lcd.h
  • LCD_VoltageSource_Internal : stm32l1xx_lcd.h
  • LCDEN_BitNumber : stm32l1xx_lcd.c
  • LSE_VALUE : stm32l1xx.h
  • LSECSSON_BitNumber : stm32l1xx_rcc.c
  • LSI_VALUE : stm32l1xx.h
  • LSION_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- m -

  • MODIFY_REG : stm32l1xx.h
  • MSION_BitNumber : stm32l1xx_rcc.c
  • MUX_SEG_BitNumber : stm32l1xx_lcd.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- n -

  • NIEN_BitNumber : stm32l1xx_sdio.c
  • NVIC_IABR_ACTIVE : stm32l1xx.h
  • NVIC_IABR_ACTIVE_0 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_1 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_10 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_11 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_12 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_13 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_14 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_15 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_16 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_17 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_18 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_19 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_2 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_20 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_21 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_22 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_23 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_24 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_25 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_26 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_27 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_28 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_29 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_3 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_30 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_31 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_4 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_5 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_6 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_7 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_8 : stm32l1xx.h
  • NVIC_IABR_ACTIVE_9 : stm32l1xx.h
  • NVIC_ICER_CLRENA : stm32l1xx.h
  • NVIC_ICER_CLRENA_0 : stm32l1xx.h
  • NVIC_ICER_CLRENA_1 : stm32l1xx.h
  • NVIC_ICER_CLRENA_10 : stm32l1xx.h
  • NVIC_ICER_CLRENA_11 : stm32l1xx.h
  • NVIC_ICER_CLRENA_12 : stm32l1xx.h
  • NVIC_ICER_CLRENA_13 : stm32l1xx.h
  • NVIC_ICER_CLRENA_14 : stm32l1xx.h
  • NVIC_ICER_CLRENA_15 : stm32l1xx.h
  • NVIC_ICER_CLRENA_16 : stm32l1xx.h
  • NVIC_ICER_CLRENA_17 : stm32l1xx.h
  • NVIC_ICER_CLRENA_18 : stm32l1xx.h
  • NVIC_ICER_CLRENA_19 : stm32l1xx.h
  • NVIC_ICER_CLRENA_2 : stm32l1xx.h
  • NVIC_ICER_CLRENA_20 : stm32l1xx.h
  • NVIC_ICER_CLRENA_21 : stm32l1xx.h
  • NVIC_ICER_CLRENA_22 : stm32l1xx.h
  • NVIC_ICER_CLRENA_23 : stm32l1xx.h
  • NVIC_ICER_CLRENA_24 : stm32l1xx.h
  • NVIC_ICER_CLRENA_25 : stm32l1xx.h
  • NVIC_ICER_CLRENA_26 : stm32l1xx.h
  • NVIC_ICER_CLRENA_27 : stm32l1xx.h
  • NVIC_ICER_CLRENA_28 : stm32l1xx.h
  • NVIC_ICER_CLRENA_29 : stm32l1xx.h
  • NVIC_ICER_CLRENA_3 : stm32l1xx.h
  • NVIC_ICER_CLRENA_30 : stm32l1xx.h
  • NVIC_ICER_CLRENA_31 : stm32l1xx.h
  • NVIC_ICER_CLRENA_4 : stm32l1xx.h
  • NVIC_ICER_CLRENA_5 : stm32l1xx.h
  • NVIC_ICER_CLRENA_6 : stm32l1xx.h
  • NVIC_ICER_CLRENA_7 : stm32l1xx.h
  • NVIC_ICER_CLRENA_8 : stm32l1xx.h
  • NVIC_ICER_CLRENA_9 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_0 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_1 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_10 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_11 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_12 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_13 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_14 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_15 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_16 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_17 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_18 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_19 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_2 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_20 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_21 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_22 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_23 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_24 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_25 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_26 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_27 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_28 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_29 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_3 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_30 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_31 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_4 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_5 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_6 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_7 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_8 : stm32l1xx.h
  • NVIC_ICPR_CLRPEND_9 : stm32l1xx.h
  • NVIC_IPR0_PRI_0 : stm32l1xx.h
  • NVIC_IPR0_PRI_1 : stm32l1xx.h
  • NVIC_IPR0_PRI_2 : stm32l1xx.h
  • NVIC_IPR0_PRI_3 : stm32l1xx.h
  • NVIC_IPR1_PRI_4 : stm32l1xx.h
  • NVIC_IPR1_PRI_5 : stm32l1xx.h
  • NVIC_IPR1_PRI_6 : stm32l1xx.h
  • NVIC_IPR1_PRI_7 : stm32l1xx.h
  • NVIC_IPR2_PRI_10 : stm32l1xx.h
  • NVIC_IPR2_PRI_11 : stm32l1xx.h
  • NVIC_IPR2_PRI_8 : stm32l1xx.h
  • NVIC_IPR2_PRI_9 : stm32l1xx.h
  • NVIC_IPR3_PRI_12 : stm32l1xx.h
  • NVIC_IPR3_PRI_13 : stm32l1xx.h
  • NVIC_IPR3_PRI_14 : stm32l1xx.h
  • NVIC_IPR3_PRI_15 : stm32l1xx.h
  • NVIC_IPR4_PRI_16 : stm32l1xx.h
  • NVIC_IPR4_PRI_17 : stm32l1xx.h
  • NVIC_IPR4_PRI_18 : stm32l1xx.h
  • NVIC_IPR4_PRI_19 : stm32l1xx.h
  • NVIC_IPR5_PRI_20 : stm32l1xx.h
  • NVIC_IPR5_PRI_21 : stm32l1xx.h
  • NVIC_IPR5_PRI_22 : stm32l1xx.h
  • NVIC_IPR5_PRI_23 : stm32l1xx.h
  • NVIC_IPR6_PRI_24 : stm32l1xx.h
  • NVIC_IPR6_PRI_25 : stm32l1xx.h
  • NVIC_IPR6_PRI_26 : stm32l1xx.h
  • NVIC_IPR6_PRI_27 : stm32l1xx.h
  • NVIC_IPR7_PRI_28 : stm32l1xx.h
  • NVIC_IPR7_PRI_29 : stm32l1xx.h
  • NVIC_IPR7_PRI_30 : stm32l1xx.h
  • NVIC_IPR7_PRI_31 : stm32l1xx.h
  • NVIC_ISER_SETENA : stm32l1xx.h
  • NVIC_ISER_SETENA_0 : stm32l1xx.h
  • NVIC_ISER_SETENA_1 : stm32l1xx.h
  • NVIC_ISER_SETENA_10 : stm32l1xx.h
  • NVIC_ISER_SETENA_11 : stm32l1xx.h
  • NVIC_ISER_SETENA_12 : stm32l1xx.h
  • NVIC_ISER_SETENA_13 : stm32l1xx.h
  • NVIC_ISER_SETENA_14 : stm32l1xx.h
  • NVIC_ISER_SETENA_15 : stm32l1xx.h
  • NVIC_ISER_SETENA_16 : stm32l1xx.h
  • NVIC_ISER_SETENA_17 : stm32l1xx.h
  • NVIC_ISER_SETENA_18 : stm32l1xx.h
  • NVIC_ISER_SETENA_19 : stm32l1xx.h
  • NVIC_ISER_SETENA_2 : stm32l1xx.h
  • NVIC_ISER_SETENA_20 : stm32l1xx.h
  • NVIC_ISER_SETENA_21 : stm32l1xx.h
  • NVIC_ISER_SETENA_22 : stm32l1xx.h
  • NVIC_ISER_SETENA_23 : stm32l1xx.h
  • NVIC_ISER_SETENA_24 : stm32l1xx.h
  • NVIC_ISER_SETENA_25 : stm32l1xx.h
  • NVIC_ISER_SETENA_26 : stm32l1xx.h
  • NVIC_ISER_SETENA_27 : stm32l1xx.h
  • NVIC_ISER_SETENA_28 : stm32l1xx.h
  • NVIC_ISER_SETENA_29 : stm32l1xx.h
  • NVIC_ISER_SETENA_3 : stm32l1xx.h
  • NVIC_ISER_SETENA_30 : stm32l1xx.h
  • NVIC_ISER_SETENA_31 : stm32l1xx.h
  • NVIC_ISER_SETENA_4 : stm32l1xx.h
  • NVIC_ISER_SETENA_5 : stm32l1xx.h
  • NVIC_ISER_SETENA_6 : stm32l1xx.h
  • NVIC_ISER_SETENA_7 : stm32l1xx.h
  • NVIC_ISER_SETENA_8 : stm32l1xx.h
  • NVIC_ISER_SETENA_9 : stm32l1xx.h
  • NVIC_ISPR_SETPEND : stm32l1xx.h
  • NVIC_ISPR_SETPEND_0 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_1 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_10 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_11 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_12 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_13 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_14 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_15 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_16 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_17 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_18 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_19 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_2 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_20 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_21 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_22 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_23 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_24 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_25 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_26 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_27 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_28 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_29 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_3 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_30 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_31 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_4 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_5 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_6 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_7 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_8 : stm32l1xx.h
  • NVIC_ISPR_SETPEND_9 : stm32l1xx.h
  • NVIC_LP_SEVONPEND : misc.h
  • NVIC_LP_SLEEPDEEP : misc.h
  • NVIC_LP_SLEEPONEXIT : misc.h
  • NVIC_PriorityGroup_0 : misc.h
  • NVIC_PriorityGroup_1 : misc.h
  • NVIC_PriorityGroup_2 : misc.h
  • NVIC_PriorityGroup_3 : misc.h
  • NVIC_PriorityGroup_4 : misc.h
  • NVIC_VectTab_FLASH : misc.h
  • NVIC_VectTab_RAM : misc.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- o -

  • OB : stm32l1xx.h
  • OB_BASE : stm32l1xx.h
  • OB_BOOT_BANK1 : stm32l1xx_flash.h
  • OB_BOOT_BANK2 : stm32l1xx_flash.h
  • OB_BOR_LEVEL1 : stm32l1xx_flash.h
  • OB_BOR_LEVEL2 : stm32l1xx_flash.h
  • OB_BOR_LEVEL3 : stm32l1xx_flash.h
  • OB_BOR_LEVEL4 : stm32l1xx_flash.h
  • OB_BOR_LEVEL5 : stm32l1xx_flash.h
  • OB_BOR_OFF : stm32l1xx_flash.h
  • OB_IWDG_HW : stm32l1xx_flash.h
  • OB_IWDG_SW : stm32l1xx_flash.h
  • OB_RDP_Level_0 : stm32l1xx_flash.h
  • OB_RDP_Level_1 : stm32l1xx_flash.h
  • OB_STDBY_NoRST : stm32l1xx_flash.h
  • OB_STDBY_RST : stm32l1xx_flash.h
  • OB_STOP_NoRST : stm32l1xx_flash.h
  • OB_STOP_RST : stm32l1xx_flash.h
  • OB_WRP1_AllPages : stm32l1xx_flash.h
  • OB_WRP1_Pages1008to1023 : stm32l1xx_flash.h
  • OB_WRP1_Pages512to527 : stm32l1xx_flash.h
  • OB_WRP1_Pages528to543 : stm32l1xx_flash.h
  • OB_WRP1_Pages544to559 : stm32l1xx_flash.h
  • OB_WRP1_Pages560to575 : stm32l1xx_flash.h
  • OB_WRP1_Pages576to591 : stm32l1xx_flash.h
  • OB_WRP1_Pages592to607 : stm32l1xx_flash.h
  • OB_WRP1_Pages608to623 : stm32l1xx_flash.h
  • OB_WRP1_Pages624to639 : stm32l1xx_flash.h
  • OB_WRP1_Pages640to655 : stm32l1xx_flash.h
  • OB_WRP1_Pages656to671 : stm32l1xx_flash.h
  • OB_WRP1_Pages672to687 : stm32l1xx_flash.h
  • OB_WRP1_Pages688to703 : stm32l1xx_flash.h
  • OB_WRP1_Pages704to719 : stm32l1xx_flash.h
  • OB_WRP1_Pages720to735 : stm32l1xx_flash.h
  • OB_WRP1_Pages736to751 : stm32l1xx_flash.h
  • OB_WRP1_Pages752to767 : stm32l1xx_flash.h
  • OB_WRP1_Pages768to783 : stm32l1xx_flash.h
  • OB_WRP1_Pages784to799 : stm32l1xx_flash.h
  • OB_WRP1_Pages800to815 : stm32l1xx_flash.h
  • OB_WRP1_Pages816to831 : stm32l1xx_flash.h
  • OB_WRP1_Pages832to847 : stm32l1xx_flash.h
  • OB_WRP1_Pages848to863 : stm32l1xx_flash.h
  • OB_WRP1_Pages864to879 : stm32l1xx_flash.h
  • OB_WRP1_Pages880to895 : stm32l1xx_flash.h
  • OB_WRP1_Pages896to911 : stm32l1xx_flash.h
  • OB_WRP1_Pages912to927 : stm32l1xx_flash.h
  • OB_WRP1_Pages928to943 : stm32l1xx_flash.h
  • OB_WRP1_Pages944to959 : stm32l1xx_flash.h
  • OB_WRP1_Pages960to975 : stm32l1xx_flash.h
  • OB_WRP1_Pages976to991 : stm32l1xx_flash.h
  • OB_WRP1_Pages992to1007 : stm32l1xx_flash.h
  • OB_WRP2_AllPages : stm32l1xx_flash.h
  • OB_WRP2_Pages1024to1039 : stm32l1xx_flash.h
  • OB_WRP2_Pages1040to1055 : stm32l1xx_flash.h
  • OB_WRP2_Pages1056to1071 : stm32l1xx_flash.h
  • OB_WRP2_Pages1072to1087 : stm32l1xx_flash.h
  • OB_WRP2_Pages1088to1103 : stm32l1xx_flash.h
  • OB_WRP2_Pages1104to1119 : stm32l1xx_flash.h
  • OB_WRP2_Pages1120to1135 : stm32l1xx_flash.h
  • OB_WRP2_Pages1136to1151 : stm32l1xx_flash.h
  • OB_WRP2_Pages1152to1167 : stm32l1xx_flash.h
  • OB_WRP2_Pages1168to1183 : stm32l1xx_flash.h
  • OB_WRP2_Pages1184to1199 : stm32l1xx_flash.h
  • OB_WRP2_Pages1200to1215 : stm32l1xx_flash.h
  • OB_WRP2_Pages1216to1231 : stm32l1xx_flash.h
  • OB_WRP2_Pages1232to1247 : stm32l1xx_flash.h
  • OB_WRP2_Pages1248to1263 : stm32l1xx_flash.h
  • OB_WRP2_Pages1264to1279 : stm32l1xx_flash.h
  • OB_WRP2_Pages1280to1295 : stm32l1xx_flash.h
  • OB_WRP2_Pages1296to1311 : stm32l1xx_flash.h
  • OB_WRP2_Pages1312to1327 : stm32l1xx_flash.h
  • OB_WRP2_Pages1328to1343 : stm32l1xx_flash.h
  • OB_WRP2_Pages1344to1359 : stm32l1xx_flash.h
  • OB_WRP2_Pages1360to1375 : stm32l1xx_flash.h
  • OB_WRP2_Pages1376to1391 : stm32l1xx_flash.h
  • OB_WRP2_Pages1392to1407 : stm32l1xx_flash.h
  • OB_WRP2_Pages1408to1423 : stm32l1xx_flash.h
  • OB_WRP2_Pages1424to1439 : stm32l1xx_flash.h
  • OB_WRP2_Pages1440to1455 : stm32l1xx_flash.h
  • OB_WRP2_Pages1456to1471 : stm32l1xx_flash.h
  • OB_WRP2_Pages1472to1487 : stm32l1xx_flash.h
  • OB_WRP2_Pages1488to1503 : stm32l1xx_flash.h
  • OB_WRP2_Pages1504to1519 : stm32l1xx_flash.h
  • OB_WRP2_Pages1520to1535 : stm32l1xx_flash.h
  • OB_WRP_AllPages : stm32l1xx_flash.h
  • OB_WRP_Pages0to15 : stm32l1xx_flash.h
  • OB_WRP_Pages112to127 : stm32l1xx_flash.h
  • OB_WRP_Pages128to143 : stm32l1xx_flash.h
  • OB_WRP_Pages144to159 : stm32l1xx_flash.h
  • OB_WRP_Pages160to175 : stm32l1xx_flash.h
  • OB_WRP_Pages16to31 : stm32l1xx_flash.h
  • OB_WRP_Pages176to191 : stm32l1xx_flash.h
  • OB_WRP_Pages192to207 : stm32l1xx_flash.h
  • OB_WRP_Pages208to223 : stm32l1xx_flash.h
  • OB_WRP_Pages224to239 : stm32l1xx_flash.h
  • OB_WRP_Pages240to255 : stm32l1xx_flash.h
  • OB_WRP_Pages256to271 : stm32l1xx_flash.h
  • OB_WRP_Pages272to287 : stm32l1xx_flash.h
  • OB_WRP_Pages288to303 : stm32l1xx_flash.h
  • OB_WRP_Pages304to319 : stm32l1xx_flash.h
  • OB_WRP_Pages320to335 : stm32l1xx_flash.h
  • OB_WRP_Pages32to47 : stm32l1xx_flash.h
  • OB_WRP_Pages336to351 : stm32l1xx_flash.h
  • OB_WRP_Pages352to367 : stm32l1xx_flash.h
  • OB_WRP_Pages368to383 : stm32l1xx_flash.h
  • OB_WRP_Pages384to399 : stm32l1xx_flash.h
  • OB_WRP_Pages400to415 : stm32l1xx_flash.h
  • OB_WRP_Pages416to431 : stm32l1xx_flash.h
  • OB_WRP_Pages432to447 : stm32l1xx_flash.h
  • OB_WRP_Pages448to463 : stm32l1xx_flash.h
  • OB_WRP_Pages464to479 : stm32l1xx_flash.h
  • OB_WRP_Pages480to495 : stm32l1xx_flash.h
  • OB_WRP_Pages48to63 : stm32l1xx_flash.h
  • OB_WRP_Pages496to511 : stm32l1xx_flash.h
  • OB_WRP_Pages64to79 : stm32l1xx_flash.h
  • OB_WRP_Pages80to95 : stm32l1xx_flash.h
  • OB_WRP_Pages96to111 : stm32l1xx_flash.h
  • OPAMP : stm32l1xx.h
  • OPAMP_BASE : stm32l1xx.h
  • OPAMP_CSR_ANAWSEL1 : stm32l1xx.h
  • OPAMP_CSR_ANAWSEL2 : stm32l1xx.h
  • OPAMP_CSR_ANAWSEL3 : stm32l1xx.h
  • OPAMP_CSR_AOP_RANGE : stm32l1xx.h
  • OPAMP_CSR_OPA1CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA1CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA1CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA1LPM : stm32l1xx.h
  • OPAMP_CSR_OPA1PD : stm32l1xx.h
  • OPAMP_CSR_OPA2CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA2CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA2CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA2LPM : stm32l1xx.h
  • OPAMP_CSR_OPA2PD : stm32l1xx.h
  • OPAMP_CSR_OPA3CAL_H : stm32l1xx.h
  • OPAMP_CSR_OPA3CAL_L : stm32l1xx.h
  • OPAMP_CSR_OPA3CALOUT : stm32l1xx.h
  • OPAMP_CSR_OPA3LPM : stm32l1xx.h
  • OPAMP_CSR_OPA3PD : stm32l1xx.h
  • OPAMP_CSR_S3SEL1 : stm32l1xx.h
  • OPAMP_CSR_S3SEL2 : stm32l1xx.h
  • OPAMP_CSR_S3SEL3 : stm32l1xx.h
  • OPAMP_CSR_S4SEL1 : stm32l1xx.h
  • OPAMP_CSR_S4SEL2 : stm32l1xx.h
  • OPAMP_CSR_S4SEL3 : stm32l1xx.h
  • OPAMP_CSR_S5SEL1 : stm32l1xx.h
  • OPAMP_CSR_S5SEL2 : stm32l1xx.h
  • OPAMP_CSR_S5SEL3 : stm32l1xx.h
  • OPAMP_CSR_S6SEL1 : stm32l1xx.h
  • OPAMP_CSR_S6SEL2 : stm32l1xx.h
  • OPAMP_CSR_S6SEL3 : stm32l1xx.h
  • OPAMP_CSR_S7SEL2 : stm32l1xx.h
  • OPAMP_Input_NMOS : stm32l1xx_opamp.h
  • OPAMP_Input_PMOS : stm32l1xx_opamp.h
  • OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP : stm32l1xx.h
  • OPAMP_OPAMP1Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP1SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2Switch7 : stm32l1xx_opamp.h
  • OPAMP_OPAMP2SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch3 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch4 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch5 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3Switch6 : stm32l1xx_opamp.h
  • OPAMP_OPAMP3SwitchANA : stm32l1xx_opamp.h
  • OPAMP_OTR_AO1_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_AO2_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_AO3_OPT_OFFSET_TRIM : stm32l1xx.h
  • OPAMP_OTR_OT_USER : stm32l1xx.h
  • OPAMP_PowerRange_High : stm32l1xx_opamp.h
  • OPAMP_PowerRange_Low : stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP1 : stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP2 : stm32l1xx_opamp.h
  • OPAMP_Selection_OPAMP3 : stm32l1xx_opamp.h
  • OPAMP_Trimming_Factory : stm32l1xx_opamp.h
  • OPAMP_Trimming_User : stm32l1xx_opamp.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- a -

  • ADC : stm32l1xx.h
  • ADC1 : stm32l1xx.h
  • ADC1_BASE : stm32l1xx.h
  • ADC_AnalogWatchdog_AllInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_AllRegAllInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_AllRegEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_None : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleInjecEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleRegEnable : stm32l1xx_adc.h
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable : stm32l1xx_adc.h
  • ADC_Bank_A : stm32l1xx_adc.h
  • ADC_Bank_B : stm32l1xx_adc.h
  • ADC_BASE : stm32l1xx.h
  • ADC_CCR_ADCPRE : stm32l1xx.h
  • ADC_CCR_ADCPRE_0 : stm32l1xx.h
  • ADC_CCR_ADCPRE_1 : stm32l1xx.h
  • ADC_CCR_TSVREFE : stm32l1xx.h
  • ADC_Channel_0 : stm32l1xx_adc.h
  • ADC_Channel_0b : stm32l1xx_adc.h
  • ADC_Channel_1 : stm32l1xx_adc.h
  • ADC_Channel_10 : stm32l1xx_adc.h
  • ADC_Channel_10b : stm32l1xx_adc.h
  • ADC_Channel_11 : stm32l1xx_adc.h
  • ADC_Channel_11b : stm32l1xx_adc.h
  • ADC_Channel_12 : stm32l1xx_adc.h
  • ADC_Channel_12b : stm32l1xx_adc.h
  • ADC_Channel_13 : stm32l1xx_adc.h
  • ADC_Channel_14 : stm32l1xx_adc.h
  • ADC_Channel_15 : stm32l1xx_adc.h
  • ADC_Channel_16 : stm32l1xx_adc.h
  • ADC_Channel_17 : stm32l1xx_adc.h
  • ADC_Channel_18 : stm32l1xx_adc.h
  • ADC_Channel_19 : stm32l1xx_adc.h
  • ADC_Channel_1b : stm32l1xx_adc.h
  • ADC_Channel_2 : stm32l1xx_adc.h
  • ADC_Channel_20 : stm32l1xx_adc.h
  • ADC_Channel_21 : stm32l1xx_adc.h
  • ADC_Channel_22 : stm32l1xx_adc.h
  • ADC_Channel_23 : stm32l1xx_adc.h
  • ADC_Channel_24 : stm32l1xx_adc.h
  • ADC_Channel_25 : stm32l1xx_adc.h
  • ADC_Channel_27 : stm32l1xx_adc.h
  • ADC_Channel_28 : stm32l1xx_adc.h
  • ADC_Channel_29 : stm32l1xx_adc.h
  • ADC_Channel_2b : stm32l1xx_adc.h
  • ADC_Channel_3 : stm32l1xx_adc.h
  • ADC_Channel_30 : stm32l1xx_adc.h
  • ADC_Channel_31 : stm32l1xx_adc.h
  • ADC_Channel_3b : stm32l1xx_adc.h
  • ADC_Channel_4 : stm32l1xx_adc.h
  • ADC_Channel_5 : stm32l1xx_adc.h
  • ADC_Channel_6 : stm32l1xx_adc.h
  • ADC_Channel_6b : stm32l1xx_adc.h
  • ADC_Channel_7 : stm32l1xx_adc.h
  • ADC_Channel_7b : stm32l1xx_adc.h
  • ADC_Channel_8 : stm32l1xx_adc.h
  • ADC_Channel_8b : stm32l1xx_adc.h
  • ADC_Channel_9 : stm32l1xx_adc.h
  • ADC_Channel_9b : stm32l1xx_adc.h
  • ADC_Channel_TempSensor : stm32l1xx_adc.h
  • ADC_Channel_Vrefint : stm32l1xx_adc.h
  • ADC_CR1_AWDCH : stm32l1xx.h
  • ADC_CR1_AWDCH_0 : stm32l1xx.h
  • ADC_CR1_AWDCH_1 : stm32l1xx.h
  • ADC_CR1_AWDCH_2 : stm32l1xx.h
  • ADC_CR1_AWDCH_3 : stm32l1xx.h
  • ADC_CR1_AWDCH_4 : stm32l1xx.h
  • ADC_CR1_AWDEN : stm32l1xx.h
  • ADC_CR1_AWDIE : stm32l1xx.h
  • ADC_CR1_AWDSGL : stm32l1xx.h
  • ADC_CR1_DISCEN : stm32l1xx.h
  • ADC_CR1_DISCNUM : stm32l1xx.h
  • ADC_CR1_DISCNUM_0 : stm32l1xx.h
  • ADC_CR1_DISCNUM_1 : stm32l1xx.h
  • ADC_CR1_DISCNUM_2 : stm32l1xx.h
  • ADC_CR1_EOCIE : stm32l1xx.h
  • ADC_CR1_JAUTO : stm32l1xx.h
  • ADC_CR1_JAWDEN : stm32l1xx.h
  • ADC_CR1_JDISCEN : stm32l1xx.h
  • ADC_CR1_JEOCIE : stm32l1xx.h
  • ADC_CR1_OVRIE : stm32l1xx.h
  • ADC_CR1_PDD : stm32l1xx.h
  • ADC_CR1_PDI : stm32l1xx.h
  • ADC_CR1_RES : stm32l1xx.h
  • ADC_CR1_RES_0 : stm32l1xx.h
  • ADC_CR1_RES_1 : stm32l1xx.h
  • ADC_CR1_SCAN : stm32l1xx.h
  • ADC_CR2_ADON : stm32l1xx.h
  • ADC_CR2_ALIGN : stm32l1xx.h
  • ADC_CR2_CFG : stm32l1xx.h
  • ADC_CR2_CONT : stm32l1xx.h
  • ADC_CR2_DDS : stm32l1xx.h
  • ADC_CR2_DELS : stm32l1xx.h
  • ADC_CR2_DELS_0 : stm32l1xx.h
  • ADC_CR2_DELS_1 : stm32l1xx.h
  • ADC_CR2_DELS_2 : stm32l1xx.h
  • ADC_CR2_DMA : stm32l1xx.h
  • ADC_CR2_EOCS : stm32l1xx.h
  • ADC_CR2_EXTEN : stm32l1xx.h
  • ADC_CR2_EXTEN_0 : stm32l1xx.h
  • ADC_CR2_EXTEN_1 : stm32l1xx.h
  • ADC_CR2_EXTSEL : stm32l1xx.h
  • ADC_CR2_EXTSEL_0 : stm32l1xx.h
  • ADC_CR2_EXTSEL_1 : stm32l1xx.h
  • ADC_CR2_EXTSEL_2 : stm32l1xx.h
  • ADC_CR2_EXTSEL_3 : stm32l1xx.h
  • ADC_CR2_JEXTEN : stm32l1xx.h
  • ADC_CR2_JEXTEN_0 : stm32l1xx.h
  • ADC_CR2_JEXTEN_1 : stm32l1xx.h
  • ADC_CR2_JEXTSEL : stm32l1xx.h
  • ADC_CR2_JEXTSEL_0 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_1 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_2 : stm32l1xx.h
  • ADC_CR2_JEXTSEL_3 : stm32l1xx.h
  • ADC_CR2_JSWSTART : stm32l1xx.h
  • ADC_CR2_SWSTART : stm32l1xx.h
  • ADC_CSR_ADONS1 : stm32l1xx.h
  • ADC_CSR_AWD1 : stm32l1xx.h
  • ADC_CSR_EOC1 : stm32l1xx.h
  • ADC_CSR_JEOC1 : stm32l1xx.h
  • ADC_CSR_JSTRT1 : stm32l1xx.h
  • ADC_CSR_OVR1 : stm32l1xx.h
  • ADC_CSR_STRT1 : stm32l1xx.h
  • ADC_DataAlign_Left : stm32l1xx_adc.h
  • ADC_DataAlign_Right : stm32l1xx_adc.h
  • ADC_DelayLength_127Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_15Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_255Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_31Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_63Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_7Cycles : stm32l1xx_adc.h
  • ADC_DelayLength_Freeze : stm32l1xx_adc.h
  • ADC_DelayLength_None : stm32l1xx_adc.h
  • ADC_DR_DATA : stm32l1xx.h
  • ADC_ExternalTrigConv_Ext_IT11 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T2_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T3_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T4_CC4 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T4_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T6_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T9_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigConv_T9_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_Falling : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_None : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_Rising : stm32l1xx_adc.h
  • ADC_ExternalTrigConvEdge_RisingFalling : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_Ext_IT15 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T10_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T2_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T2_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T3_CC4 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC2 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC3 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T4_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T7_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T9_CC1 : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConv_T9_TRGO : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_Falling : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_None : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_Rising : stm32l1xx_adc.h
  • ADC_ExternalTrigInjecConvEdge_RisingFalling : stm32l1xx_adc.h
  • ADC_FLAG_ADONS : stm32l1xx_adc.h
  • ADC_FLAG_AWD : stm32l1xx_adc.h
  • ADC_FLAG_EOC : stm32l1xx_adc.h
  • ADC_FLAG_JCNR : stm32l1xx_adc.h
  • ADC_FLAG_JEOC : stm32l1xx_adc.h
  • ADC_FLAG_JSTRT : stm32l1xx_adc.h
  • ADC_FLAG_OVR : stm32l1xx_adc.h
  • ADC_FLAG_RCNR : stm32l1xx_adc.h
  • ADC_FLAG_STRT : stm32l1xx_adc.h
  • ADC_HTR_HT : stm32l1xx.h
  • ADC_InjectedChannel_1 : stm32l1xx_adc.h
  • ADC_InjectedChannel_2 : stm32l1xx_adc.h
  • ADC_InjectedChannel_3 : stm32l1xx_adc.h
  • ADC_InjectedChannel_4 : stm32l1xx_adc.h
  • ADC_IT_AWD : stm32l1xx_adc.h
  • ADC_IT_EOC : stm32l1xx_adc.h
  • ADC_IT_JEOC : stm32l1xx_adc.h
  • ADC_IT_OVR : stm32l1xx_adc.h
  • ADC_JDR1_JDATA : stm32l1xx.h
  • ADC_JDR2_JDATA : stm32l1xx.h
  • ADC_JDR3_JDATA : stm32l1xx.h
  • ADC_JDR4_JDATA : stm32l1xx.h
  • ADC_JOFR1_JOFFSET1 : stm32l1xx.h
  • ADC_JOFR2_JOFFSET2 : stm32l1xx.h
  • ADC_JOFR3_JOFFSET3 : stm32l1xx.h
  • ADC_JOFR4_JOFFSET4 : stm32l1xx.h
  • ADC_JSQR_JL : stm32l1xx.h
  • ADC_JSQR_JL_0 : stm32l1xx.h
  • ADC_JSQR_JL_1 : stm32l1xx.h
  • ADC_JSQR_JSQ1 : stm32l1xx.h
  • ADC_JSQR_JSQ1_0 : stm32l1xx.h
  • ADC_JSQR_JSQ1_1 : stm32l1xx.h
  • ADC_JSQR_JSQ1_2 : stm32l1xx.h
  • ADC_JSQR_JSQ1_3 : stm32l1xx.h
  • ADC_JSQR_JSQ1_4 : stm32l1xx.h
  • ADC_JSQR_JSQ2 : stm32l1xx.h
  • ADC_JSQR_JSQ2_0 : stm32l1xx.h
  • ADC_JSQR_JSQ2_1 : stm32l1xx.h
  • ADC_JSQR_JSQ2_2 : stm32l1xx.h
  • ADC_JSQR_JSQ2_3 : stm32l1xx.h
  • ADC_JSQR_JSQ2_4 : stm32l1xx.h
  • ADC_JSQR_JSQ3 : stm32l1xx.h
  • ADC_JSQR_JSQ3_0 : stm32l1xx.h
  • ADC_JSQR_JSQ3_1 : stm32l1xx.h
  • ADC_JSQR_JSQ3_2 : stm32l1xx.h
  • ADC_JSQR_JSQ3_3 : stm32l1xx.h
  • ADC_JSQR_JSQ3_4 : stm32l1xx.h
  • ADC_JSQR_JSQ4 : stm32l1xx.h
  • ADC_JSQR_JSQ4_0 : stm32l1xx.h
  • ADC_JSQR_JSQ4_1 : stm32l1xx.h
  • ADC_JSQR_JSQ4_2 : stm32l1xx.h
  • ADC_JSQR_JSQ4_3 : stm32l1xx.h
  • ADC_JSQR_JSQ4_4 : stm32l1xx.h
  • ADC_LTR_LT : stm32l1xx.h
  • ADC_PowerDown_Delay : stm32l1xx_adc.h
  • ADC_PowerDown_Idle : stm32l1xx_adc.h
  • ADC_PowerDown_Idle_Delay : stm32l1xx_adc.h
  • ADC_Prescaler_Div1 : stm32l1xx_adc.h
  • ADC_Prescaler_Div2 : stm32l1xx_adc.h
  • ADC_Prescaler_Div4 : stm32l1xx_adc.h
  • ADC_Resolution_10b : stm32l1xx_adc.h
  • ADC_Resolution_12b : stm32l1xx_adc.h
  • ADC_Resolution_6b : stm32l1xx_adc.h
  • ADC_Resolution_8b : stm32l1xx_adc.h
  • ADC_SampleTime_16Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_192Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_24Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_384Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_48Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_4Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_96Cycles : stm32l1xx_adc.h
  • ADC_SampleTime_9Cycles : stm32l1xx_adc.h
  • ADC_SMPR1_SMP20 : stm32l1xx.h
  • ADC_SMPR1_SMP20_0 : stm32l1xx.h
  • ADC_SMPR1_SMP20_1 : stm32l1xx.h
  • ADC_SMPR1_SMP20_2 : stm32l1xx.h
  • ADC_SMPR1_SMP21 : stm32l1xx.h
  • ADC_SMPR1_SMP21_0 : stm32l1xx.h
  • ADC_SMPR1_SMP21_1 : stm32l1xx.h
  • ADC_SMPR1_SMP21_2 : stm32l1xx.h
  • ADC_SMPR1_SMP22 : stm32l1xx.h
  • ADC_SMPR1_SMP22_0 : stm32l1xx.h
  • ADC_SMPR1_SMP22_1 : stm32l1xx.h
  • ADC_SMPR1_SMP22_2 : stm32l1xx.h
  • ADC_SMPR1_SMP23 : stm32l1xx.h
  • ADC_SMPR1_SMP23_0 : stm32l1xx.h
  • ADC_SMPR1_SMP23_1 : stm32l1xx.h
  • ADC_SMPR1_SMP23_2 : stm32l1xx.h
  • ADC_SMPR1_SMP24 : stm32l1xx.h
  • ADC_SMPR1_SMP24_0 : stm32l1xx.h
  • ADC_SMPR1_SMP24_1 : stm32l1xx.h
  • ADC_SMPR1_SMP24_2 : stm32l1xx.h
  • ADC_SMPR1_SMP25 : stm32l1xx.h
  • ADC_SMPR1_SMP25_0 : stm32l1xx.h
  • ADC_SMPR1_SMP25_1 : stm32l1xx.h
  • ADC_SMPR1_SMP25_2 : stm32l1xx.h
  • ADC_SMPR1_SMP26 : stm32l1xx.h
  • ADC_SMPR1_SMP26_0 : stm32l1xx.h
  • ADC_SMPR1_SMP26_1 : stm32l1xx.h
  • ADC_SMPR1_SMP26_2 : stm32l1xx.h
  • ADC_SMPR1_SMP27 : stm32l1xx.h
  • ADC_SMPR1_SMP27_0 : stm32l1xx.h
  • ADC_SMPR1_SMP27_1 : stm32l1xx.h
  • ADC_SMPR1_SMP27_2 : stm32l1xx.h
  • ADC_SMPR1_SMP28 : stm32l1xx.h
  • ADC_SMPR1_SMP28_0 : stm32l1xx.h
  • ADC_SMPR1_SMP28_1 : stm32l1xx.h
  • ADC_SMPR1_SMP28_2 : stm32l1xx.h
  • ADC_SMPR1_SMP29 : stm32l1xx.h
  • ADC_SMPR1_SMP29_0 : stm32l1xx.h
  • ADC_SMPR1_SMP29_1 : stm32l1xx.h
  • ADC_SMPR1_SMP29_2 : stm32l1xx.h
  • ADC_SMPR2_SMP10 : stm32l1xx.h
  • ADC_SMPR2_SMP10_0 : stm32l1xx.h
  • ADC_SMPR2_SMP10_1 : stm32l1xx.h
  • ADC_SMPR2_SMP10_2 : stm32l1xx.h
  • ADC_SMPR2_SMP11 : stm32l1xx.h
  • ADC_SMPR2_SMP11_0 : stm32l1xx.h
  • ADC_SMPR2_SMP11_1 : stm32l1xx.h
  • ADC_SMPR2_SMP11_2 : stm32l1xx.h
  • ADC_SMPR2_SMP12 : stm32l1xx.h
  • ADC_SMPR2_SMP12_0 : stm32l1xx.h
  • ADC_SMPR2_SMP12_1 : stm32l1xx.h
  • ADC_SMPR2_SMP12_2 : stm32l1xx.h
  • ADC_SMPR2_SMP13 : stm32l1xx.h
  • ADC_SMPR2_SMP13_0 : stm32l1xx.h
  • ADC_SMPR2_SMP13_1 : stm32l1xx.h
  • ADC_SMPR2_SMP13_2 : stm32l1xx.h
  • ADC_SMPR2_SMP14 : stm32l1xx.h
  • ADC_SMPR2_SMP14_0 : stm32l1xx.h
  • ADC_SMPR2_SMP14_1 : stm32l1xx.h
  • ADC_SMPR2_SMP14_2 : stm32l1xx.h
  • ADC_SMPR2_SMP15 : stm32l1xx.h
  • ADC_SMPR2_SMP15_0 : stm32l1xx.h
  • ADC_SMPR2_SMP15_1 : stm32l1xx.h
  • ADC_SMPR2_SMP15_2 : stm32l1xx.h
  • ADC_SMPR2_SMP16 : stm32l1xx.h
  • ADC_SMPR2_SMP16_0 : stm32l1xx.h
  • ADC_SMPR2_SMP16_1 : stm32l1xx.h
  • ADC_SMPR2_SMP16_2 : stm32l1xx.h
  • ADC_SMPR2_SMP17 : stm32l1xx.h
  • ADC_SMPR2_SMP17_0 : stm32l1xx.h
  • ADC_SMPR2_SMP17_1 : stm32l1xx.h
  • ADC_SMPR2_SMP17_2 : stm32l1xx.h
  • ADC_SMPR2_SMP18 : stm32l1xx.h
  • ADC_SMPR2_SMP18_0 : stm32l1xx.h
  • ADC_SMPR2_SMP18_1 : stm32l1xx.h
  • ADC_SMPR2_SMP18_2 : stm32l1xx.h
  • ADC_SMPR2_SMP19 : stm32l1xx.h
  • ADC_SMPR2_SMP19_0 : stm32l1xx.h
  • ADC_SMPR2_SMP19_1 : stm32l1xx.h
  • ADC_SMPR2_SMP19_2 : stm32l1xx.h
  • ADC_SMPR3_SMP0 : stm32l1xx.h
  • ADC_SMPR3_SMP0_0 : stm32l1xx.h
  • ADC_SMPR3_SMP0_1 : stm32l1xx.h
  • ADC_SMPR3_SMP0_2 : stm32l1xx.h
  • ADC_SMPR3_SMP1 : stm32l1xx.h
  • ADC_SMPR3_SMP1_0 : stm32l1xx.h
  • ADC_SMPR3_SMP1_1 : stm32l1xx.h
  • ADC_SMPR3_SMP1_2 : stm32l1xx.h
  • ADC_SMPR3_SMP2 : stm32l1xx.h
  • ADC_SMPR3_SMP2_0 : stm32l1xx.h
  • ADC_SMPR3_SMP2_1 : stm32l1xx.h
  • ADC_SMPR3_SMP2_2 : stm32l1xx.h
  • ADC_SMPR3_SMP3 : stm32l1xx.h
  • ADC_SMPR3_SMP30 : stm32l1xx.h
  • ADC_SMPR3_SMP30_0 : stm32l1xx.h
  • ADC_SMPR3_SMP30_1 : stm32l1xx.h
  • ADC_SMPR3_SMP30_2 : stm32l1xx.h
  • ADC_SMPR3_SMP31 : stm32l1xx.h
  • ADC_SMPR3_SMP31_0 : stm32l1xx.h
  • ADC_SMPR3_SMP31_1 : stm32l1xx.h
  • ADC_SMPR3_SMP31_2 : stm32l1xx.h
  • ADC_SMPR3_SMP3_0 : stm32l1xx.h
  • ADC_SMPR3_SMP3_1 : stm32l1xx.h
  • ADC_SMPR3_SMP3_2 : stm32l1xx.h
  • ADC_SMPR3_SMP4 : stm32l1xx.h
  • ADC_SMPR3_SMP4_0 : stm32l1xx.h
  • ADC_SMPR3_SMP4_1 : stm32l1xx.h
  • ADC_SMPR3_SMP4_2 : stm32l1xx.h
  • ADC_SMPR3_SMP5 : stm32l1xx.h
  • ADC_SMPR3_SMP5_0 : stm32l1xx.h
  • ADC_SMPR3_SMP5_1 : stm32l1xx.h
  • ADC_SMPR3_SMP5_2 : stm32l1xx.h
  • ADC_SMPR3_SMP6 : stm32l1xx.h
  • ADC_SMPR3_SMP6_0 : stm32l1xx.h
  • ADC_SMPR3_SMP6_1 : stm32l1xx.h
  • ADC_SMPR3_SMP6_2 : stm32l1xx.h
  • ADC_SMPR3_SMP7 : stm32l1xx.h
  • ADC_SMPR3_SMP7_0 : stm32l1xx.h
  • ADC_SMPR3_SMP7_1 : stm32l1xx.h
  • ADC_SMPR3_SMP7_2 : stm32l1xx.h
  • ADC_SMPR3_SMP8 : stm32l1xx.h
  • ADC_SMPR3_SMP8_0 : stm32l1xx.h
  • ADC_SMPR3_SMP8_1 : stm32l1xx.h
  • ADC_SMPR3_SMP8_2 : stm32l1xx.h
  • ADC_SMPR3_SMP9 : stm32l1xx.h
  • ADC_SMPR3_SMP9_0 : stm32l1xx.h
  • ADC_SMPR3_SMP9_1 : stm32l1xx.h
  • ADC_SMPR3_SMP9_2 : stm32l1xx.h
  • ADC_SQR1_L : stm32l1xx.h
  • ADC_SQR1_L_0 : stm32l1xx.h
  • ADC_SQR1_L_1 : stm32l1xx.h
  • ADC_SQR1_L_2 : stm32l1xx.h
  • ADC_SQR1_L_3 : stm32l1xx.h
  • ADC_SQR1_SQ25 : stm32l1xx.h
  • ADC_SQR1_SQ25_0 : stm32l1xx.h
  • ADC_SQR1_SQ25_1 : stm32l1xx.h
  • ADC_SQR1_SQ25_2 : stm32l1xx.h
  • ADC_SQR1_SQ25_3 : stm32l1xx.h
  • ADC_SQR1_SQ25_4 : stm32l1xx.h
  • ADC_SQR1_SQ26 : stm32l1xx.h
  • ADC_SQR1_SQ26_0 : stm32l1xx.h
  • ADC_SQR1_SQ26_1 : stm32l1xx.h
  • ADC_SQR1_SQ26_2 : stm32l1xx.h
  • ADC_SQR1_SQ26_3 : stm32l1xx.h
  • ADC_SQR1_SQ26_4 : stm32l1xx.h
  • ADC_SQR1_SQ27 : stm32l1xx.h
  • ADC_SQR1_SQ27_0 : stm32l1xx.h
  • ADC_SQR1_SQ27_1 : stm32l1xx.h
  • ADC_SQR1_SQ27_2 : stm32l1xx.h
  • ADC_SQR1_SQ27_3 : stm32l1xx.h
  • ADC_SQR1_SQ27_4 : stm32l1xx.h
  • ADC_SQR1_SQ28 : stm32l1xx.h
  • ADC_SQR1_SQ28_0 : stm32l1xx.h
  • ADC_SQR1_SQ28_1 : stm32l1xx.h
  • ADC_SQR1_SQ28_2 : stm32l1xx.h
  • ADC_SQR1_SQ28_3 : stm32l1xx.h
  • ADC_SQR1_SQ28_4 : stm32l1xx.h
  • ADC_SQR2_SQ19 : stm32l1xx.h
  • ADC_SQR2_SQ19_0 : stm32l1xx.h
  • ADC_SQR2_SQ19_1 : stm32l1xx.h
  • ADC_SQR2_SQ19_2 : stm32l1xx.h
  • ADC_SQR2_SQ19_3 : stm32l1xx.h
  • ADC_SQR2_SQ19_4 : stm32l1xx.h
  • ADC_SQR2_SQ20 : stm32l1xx.h
  • ADC_SQR2_SQ20_0 : stm32l1xx.h
  • ADC_SQR2_SQ20_1 : stm32l1xx.h
  • ADC_SQR2_SQ20_2 : stm32l1xx.h
  • ADC_SQR2_SQ20_3 : stm32l1xx.h
  • ADC_SQR2_SQ20_4 : stm32l1xx.h
  • ADC_SQR2_SQ21 : stm32l1xx.h
  • ADC_SQR2_SQ21_0 : stm32l1xx.h
  • ADC_SQR2_SQ21_1 : stm32l1xx.h
  • ADC_SQR2_SQ21_2 : stm32l1xx.h
  • ADC_SQR2_SQ21_3 : stm32l1xx.h
  • ADC_SQR2_SQ21_4 : stm32l1xx.h
  • ADC_SQR2_SQ22 : stm32l1xx.h
  • ADC_SQR2_SQ22_0 : stm32l1xx.h
  • ADC_SQR2_SQ22_1 : stm32l1xx.h
  • ADC_SQR2_SQ22_2 : stm32l1xx.h
  • ADC_SQR2_SQ22_3 : stm32l1xx.h
  • ADC_SQR2_SQ22_4 : stm32l1xx.h
  • ADC_SQR2_SQ23 : stm32l1xx.h
  • ADC_SQR2_SQ23_0 : stm32l1xx.h
  • ADC_SQR2_SQ23_1 : stm32l1xx.h
  • ADC_SQR2_SQ23_2 : stm32l1xx.h
  • ADC_SQR2_SQ23_3 : stm32l1xx.h
  • ADC_SQR2_SQ23_4 : stm32l1xx.h
  • ADC_SQR2_SQ24 : stm32l1xx.h
  • ADC_SQR2_SQ24_0 : stm32l1xx.h
  • ADC_SQR2_SQ24_1 : stm32l1xx.h
  • ADC_SQR2_SQ24_2 : stm32l1xx.h
  • ADC_SQR2_SQ24_3 : stm32l1xx.h
  • ADC_SQR2_SQ24_4 : stm32l1xx.h
  • ADC_SQR3_SQ13 : stm32l1xx.h
  • ADC_SQR3_SQ13_0 : stm32l1xx.h
  • ADC_SQR3_SQ13_1 : stm32l1xx.h
  • ADC_SQR3_SQ13_2 : stm32l1xx.h
  • ADC_SQR3_SQ13_3 : stm32l1xx.h
  • ADC_SQR3_SQ13_4 : stm32l1xx.h
  • ADC_SQR3_SQ14 : stm32l1xx.h
  • ADC_SQR3_SQ14_0 : stm32l1xx.h
  • ADC_SQR3_SQ14_1 : stm32l1xx.h
  • ADC_SQR3_SQ14_2 : stm32l1xx.h
  • ADC_SQR3_SQ14_3 : stm32l1xx.h
  • ADC_SQR3_SQ14_4 : stm32l1xx.h
  • ADC_SQR3_SQ15 : stm32l1xx.h
  • ADC_SQR3_SQ15_0 : stm32l1xx.h
  • ADC_SQR3_SQ15_1 : stm32l1xx.h
  • ADC_SQR3_SQ15_2 : stm32l1xx.h
  • ADC_SQR3_SQ15_3 : stm32l1xx.h
  • ADC_SQR3_SQ15_4 : stm32l1xx.h
  • ADC_SQR3_SQ16 : stm32l1xx.h
  • ADC_SQR3_SQ16_0 : stm32l1xx.h
  • ADC_SQR3_SQ16_1 : stm32l1xx.h
  • ADC_SQR3_SQ16_2 : stm32l1xx.h
  • ADC_SQR3_SQ16_3 : stm32l1xx.h
  • ADC_SQR3_SQ16_4 : stm32l1xx.h
  • ADC_SQR3_SQ17 : stm32l1xx.h
  • ADC_SQR3_SQ17_0 : stm32l1xx.h
  • ADC_SQR3_SQ17_1 : stm32l1xx.h
  • ADC_SQR3_SQ17_2 : stm32l1xx.h
  • ADC_SQR3_SQ17_3 : stm32l1xx.h
  • ADC_SQR3_SQ17_4 : stm32l1xx.h
  • ADC_SQR3_SQ18 : stm32l1xx.h
  • ADC_SQR3_SQ18_0 : stm32l1xx.h
  • ADC_SQR3_SQ18_1 : stm32l1xx.h
  • ADC_SQR3_SQ18_2 : stm32l1xx.h
  • ADC_SQR3_SQ18_3 : stm32l1xx.h
  • ADC_SQR3_SQ18_4 : stm32l1xx.h
  • ADC_SQR4_SQ10 : stm32l1xx.h
  • ADC_SQR4_SQ10_0 : stm32l1xx.h
  • ADC_SQR4_SQ10_1 : stm32l1xx.h
  • ADC_SQR4_SQ10_2 : stm32l1xx.h
  • ADC_SQR4_SQ10_3 : stm32l1xx.h
  • ADC_SQR4_SQ10_4 : stm32l1xx.h
  • ADC_SQR4_SQ11 : stm32l1xx.h
  • ADC_SQR4_SQ11_0 : stm32l1xx.h
  • ADC_SQR4_SQ11_1 : stm32l1xx.h
  • ADC_SQR4_SQ11_2 : stm32l1xx.h
  • ADC_SQR4_SQ11_3 : stm32l1xx.h
  • ADC_SQR4_SQ11_4 : stm32l1xx.h
  • ADC_SQR4_SQ12 : stm32l1xx.h
  • ADC_SQR4_SQ12_0 : stm32l1xx.h
  • ADC_SQR4_SQ12_1 : stm32l1xx.h
  • ADC_SQR4_SQ12_2 : stm32l1xx.h
  • ADC_SQR4_SQ12_3 : stm32l1xx.h
  • ADC_SQR4_SQ12_4 : stm32l1xx.h
  • ADC_SQR4_SQ7 : stm32l1xx.h
  • ADC_SQR4_SQ7_0 : stm32l1xx.h
  • ADC_SQR4_SQ7_1 : stm32l1xx.h
  • ADC_SQR4_SQ7_2 : stm32l1xx.h
  • ADC_SQR4_SQ7_3 : stm32l1xx.h
  • ADC_SQR4_SQ7_4 : stm32l1xx.h
  • ADC_SQR4_SQ8 : stm32l1xx.h
  • ADC_SQR4_SQ8_0 : stm32l1xx.h
  • ADC_SQR4_SQ8_1 : stm32l1xx.h
  • ADC_SQR4_SQ8_2 : stm32l1xx.h
  • ADC_SQR4_SQ8_3 : stm32l1xx.h
  • ADC_SQR4_SQ8_4 : stm32l1xx.h
  • ADC_SQR4_SQ9 : stm32l1xx.h
  • ADC_SQR4_SQ9_0 : stm32l1xx.h
  • ADC_SQR4_SQ9_1 : stm32l1xx.h
  • ADC_SQR4_SQ9_2 : stm32l1xx.h
  • ADC_SQR4_SQ9_3 : stm32l1xx.h
  • ADC_SQR4_SQ9_4 : stm32l1xx.h
  • ADC_SQR5_SQ1 : stm32l1xx.h
  • ADC_SQR5_SQ1_0 : stm32l1xx.h
  • ADC_SQR5_SQ1_1 : stm32l1xx.h
  • ADC_SQR5_SQ1_2 : stm32l1xx.h
  • ADC_SQR5_SQ1_3 : stm32l1xx.h
  • ADC_SQR5_SQ1_4 : stm32l1xx.h
  • ADC_SQR5_SQ2 : stm32l1xx.h
  • ADC_SQR5_SQ2_0 : stm32l1xx.h
  • ADC_SQR5_SQ2_1 : stm32l1xx.h
  • ADC_SQR5_SQ2_2 : stm32l1xx.h
  • ADC_SQR5_SQ2_3 : stm32l1xx.h
  • ADC_SQR5_SQ2_4 : stm32l1xx.h
  • ADC_SQR5_SQ3 : stm32l1xx.h
  • ADC_SQR5_SQ3_0 : stm32l1xx.h
  • ADC_SQR5_SQ3_1 : stm32l1xx.h
  • ADC_SQR5_SQ3_2 : stm32l1xx.h
  • ADC_SQR5_SQ3_3 : stm32l1xx.h
  • ADC_SQR5_SQ3_4 : stm32l1xx.h
  • ADC_SQR5_SQ4 : stm32l1xx.h
  • ADC_SQR5_SQ4_0 : stm32l1xx.h
  • ADC_SQR5_SQ4_1 : stm32l1xx.h
  • ADC_SQR5_SQ4_2 : stm32l1xx.h
  • ADC_SQR5_SQ4_3 : stm32l1xx.h
  • ADC_SQR5_SQ4_4 : stm32l1xx.h
  • ADC_SQR5_SQ5 : stm32l1xx.h
  • ADC_SQR5_SQ5_0 : stm32l1xx.h
  • ADC_SQR5_SQ5_1 : stm32l1xx.h
  • ADC_SQR5_SQ5_2 : stm32l1xx.h
  • ADC_SQR5_SQ5_3 : stm32l1xx.h
  • ADC_SQR5_SQ5_4 : stm32l1xx.h
  • ADC_SQR5_SQ6 : stm32l1xx.h
  • ADC_SQR5_SQ6_0 : stm32l1xx.h
  • ADC_SQR5_SQ6_1 : stm32l1xx.h
  • ADC_SQR5_SQ6_2 : stm32l1xx.h
  • ADC_SQR5_SQ6_3 : stm32l1xx.h
  • ADC_SQR5_SQ6_4 : stm32l1xx.h
  • ADC_SR_ADONS : stm32l1xx.h
  • ADC_SR_AWD : stm32l1xx.h
  • ADC_SR_EOC : stm32l1xx.h
  • ADC_SR_JCNR : stm32l1xx.h
  • ADC_SR_JEOC : stm32l1xx.h
  • ADC_SR_JSTRT : stm32l1xx.h
  • ADC_SR_OVR : stm32l1xx.h
  • ADC_SR_RCNR : stm32l1xx.h
  • ADC_SR_STRT : stm32l1xx.h
  • AES : stm32l1xx.h
  • AES_BASE : stm32l1xx.h
  • AES_CC_TIMEOUT : stm32l1xx_aes_util.c
  • AES_Chaining_CBC : stm32l1xx_aes.h
  • AES_Chaining_CTR : stm32l1xx_aes.h
  • AES_Chaining_ECB : stm32l1xx_aes.h
  • AES_CR_CCFC : stm32l1xx.h
  • AES_CR_CCIE : stm32l1xx.h
  • AES_CR_CHMOD : stm32l1xx.h
  • AES_CR_CHMOD_0 : stm32l1xx.h
  • AES_CR_CHMOD_1 : stm32l1xx.h
  • AES_CR_DATATYPE : stm32l1xx.h
  • AES_CR_DATATYPE_0 : stm32l1xx.h
  • AES_CR_DATATYPE_1 : stm32l1xx.h
  • AES_CR_DMAINEN : stm32l1xx.h
  • AES_CR_DMAOUTEN : stm32l1xx.h
  • AES_CR_EN : stm32l1xx.h
  • AES_CR_ERRC : stm32l1xx.h
  • AES_CR_ERRIE : stm32l1xx.h
  • AES_CR_MODE : stm32l1xx.h
  • AES_CR_MODE_0 : stm32l1xx.h
  • AES_CR_MODE_1 : stm32l1xx.h
  • AES_DataType_16b : stm32l1xx_aes.h
  • AES_DataType_1b : stm32l1xx_aes.h
  • AES_DataType_32b : stm32l1xx_aes.h
  • AES_DataType_8b : stm32l1xx_aes.h
  • AES_DINR : stm32l1xx.h
  • AES_DMATransfer_In : stm32l1xx_aes.h
  • AES_DMATransfer_InOut : stm32l1xx_aes.h
  • AES_DMATransfer_Out : stm32l1xx_aes.h
  • AES_DOUTR : stm32l1xx.h
  • AES_FLAG_CCF : stm32l1xx_aes.h
  • AES_FLAG_RDERR : stm32l1xx_aes.h
  • AES_FLAG_WRERR : stm32l1xx_aes.h
  • AES_IT_CC : stm32l1xx_aes.h
  • AES_IT_ERR : stm32l1xx_aes.h
  • AES_IVR0 : stm32l1xx.h
  • AES_IVR1 : stm32l1xx.h
  • AES_IVR2 : stm32l1xx.h
  • AES_IVR3 : stm32l1xx.h
  • AES_KEYR0 : stm32l1xx.h
  • AES_KEYR1 : stm32l1xx.h
  • AES_KEYR2 : stm32l1xx.h
  • AES_KEYR3 : stm32l1xx.h
  • AES_Operation_Decryp : stm32l1xx_aes.h
  • AES_Operation_Encryp : stm32l1xx_aes.h
  • AES_Operation_KeyDeriv : stm32l1xx_aes.h
  • AES_Operation_KeyDerivAndDecryp : stm32l1xx_aes.h
  • AES_SR_CCF : stm32l1xx.h
  • AES_SR_RDERR : stm32l1xx.h
  • AES_SR_WRERR : stm32l1xx.h
  • AHBPERIPH_BASE : stm32l1xx.h
  • AIRCR_VECTKEY_MASK : misc.c
  • APB1PERIPH_BASE : stm32l1xx.h
  • APB2PERIPH_BASE : stm32l1xx.h
  • ATACMD_BitNumber : stm32l1xx_sdio.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- b -

  • BIT_MASK : stm32l1xx_wwdg.c
  • BLINK_MASK : stm32l1xx_lcd.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- c -

  • CCER_CCE_SET : stm32l1xx_tim.c
  • CCMR_OFFSET : stm32l1xx_tim.c
  • CCR_CLEAR_MASK : stm32l1xx_dma.c
  • CFGR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CFGR_BYTE4_ADDRESS : stm32l1xx_rcc.c
  • CFR_EWI_BB : stm32l1xx_wwdg.c
  • CFR_OFFSET : stm32l1xx_wwdg.c
  • CFR_W_MASK : stm32l1xx_wwdg.c
  • CFR_WDGTB_MASK : stm32l1xx_wwdg.c
  • CIR_BYTE2_ADDRESS : stm32l1xx_rcc.c
  • CIR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CLEAR_BIT : stm32l1xx.h
  • CLEAR_REG : stm32l1xx.h
  • CLKCR_CLEAR_MASK : stm32l1xx_sdio.c
  • CLKCR_CLKEN_BB : stm32l1xx_sdio.c
  • CLKCR_OFFSET : stm32l1xx_sdio.c
  • CLKEN_BitNumber : stm32l1xx_sdio.c
  • CMD_ATACMD_BB : stm32l1xx_sdio.c
  • CMD_CLEAR_MASK : stm32l1xx_sdio.c
  • CMD_ENCMDCOMPL_BB : stm32l1xx_sdio.c
  • CMD_NIEN_BB : stm32l1xx_sdio.c
  • CMD_OFFSET : stm32l1xx_sdio.c
  • CMD_SDIOSUSPEND_BB : stm32l1xx_sdio.c
  • COMP : stm32l1xx.h
  • COMP_BASE : stm32l1xx.h
  • COMP_CSR_10KPD : stm32l1xx.h
  • COMP_CSR_10KPU : stm32l1xx.h
  • COMP_CSR_400KPD : stm32l1xx.h
  • COMP_CSR_400KPU : stm32l1xx.h
  • COMP_CSR_CAIE : stm32l1xx.h
  • COMP_CSR_CAIF : stm32l1xx.h
  • COMP_CSR_CMP1EN : stm32l1xx.h
  • COMP_CSR_CMP1OUT : stm32l1xx.h
  • COMP_CSR_CMP2OUT : stm32l1xx.h
  • COMP_CSR_FCH3 : stm32l1xx.h
  • COMP_CSR_FCH8 : stm32l1xx.h
  • COMP_CSR_INSEL : stm32l1xx.h
  • COMP_CSR_INSEL_0 : stm32l1xx.h
  • COMP_CSR_INSEL_1 : stm32l1xx.h
  • COMP_CSR_INSEL_2 : stm32l1xx.h
  • COMP_CSR_OUTSEL : stm32l1xx.h
  • COMP_CSR_OUTSEL_0 : stm32l1xx.h
  • COMP_CSR_OUTSEL_1 : stm32l1xx.h
  • COMP_CSR_OUTSEL_2 : stm32l1xx.h
  • COMP_CSR_RCH13 : stm32l1xx.h
  • COMP_CSR_SPEED : stm32l1xx.h
  • COMP_CSR_SW1 : stm32l1xx.h
  • COMP_CSR_TSUSP : stm32l1xx.h
  • COMP_CSR_VREFOUTEN : stm32l1xx.h
  • COMP_CSR_WNDWE : stm32l1xx.h
  • COMP_InvertingInput_1_2VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_1_4VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_3_4VREFINT : stm32l1xx_comp.h
  • COMP_InvertingInput_DAC1 : stm32l1xx_comp.h
  • COMP_InvertingInput_DAC2 : stm32l1xx_comp.h
  • COMP_InvertingInput_IO : stm32l1xx_comp.h
  • COMP_InvertingInput_None : stm32l1xx_comp.h
  • COMP_InvertingInput_VREFINT : stm32l1xx_comp.h
  • COMP_OutputLevel_High : stm32l1xx_comp.h
  • COMP_OutputLevel_Low : stm32l1xx_comp.h
  • COMP_OutputSelect_None : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM10IC1 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM2IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM2OCREFCLR : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM3IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM3OCREFCLR : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM4IC4 : stm32l1xx_comp.h
  • COMP_OutputSelect_TIM4OCREFCLR : stm32l1xx_comp.h
  • COMP_Selection_COMP1 : stm32l1xx_comp.h
  • COMP_Selection_COMP2 : stm32l1xx_comp.h
  • COMP_Speed_Fast : stm32l1xx_comp.h
  • COMP_Speed_Slow : stm32l1xx_comp.h
  • CONTRAST_MASK : stm32l1xx_lcd.c
  • CR1_AWDCH_RESET : stm32l1xx_adc.c
  • CR1_AWDMODE_RESET : stm32l1xx_adc.c
  • CR1_CLEAR_MASK : stm32l1xx_adc.c , stm32l1xx_i2c.c , stm32l1xx_spi.c , stm32l1xx_usart.c
  • CR1_DISCNUM_RESET : stm32l1xx_adc.c
  • CR2_CLEAR_MASK : stm32l1xx_adc.c
  • CR2_CLOCK_CLEAR_MASK : stm32l1xx_usart.c
  • CR2_DELS_RESET : stm32l1xx_adc.c
  • CR2_JEXTEN_RESET : stm32l1xx_adc.c
  • CR2_JEXTSEL_RESET : stm32l1xx_adc.c
  • CR3_CLEAR_MASK : stm32l1xx_usart.c
  • CR_BYTE3_ADDRESS : stm32l1xx_rcc.c
  • CR_CLEAR_MASK : stm32l1xx_dac.c , stm32l1xx_adc.c , stm32l1xx_aes.c
  • CR_CSSON_BB : stm32l1xx_rcc.c
  • CR_DBP_BB : stm32l1xx_pwr.c
  • CR_DS_MASK : stm32l1xx_pwr.c
  • CR_FWU_BB : stm32l1xx_pwr.c
  • CR_HSION_BB : stm32l1xx_rcc.c
  • CR_LCDEN_BB : stm32l1xx_lcd.c
  • CR_MASK : stm32l1xx_lcd.c
  • CR_MSION_BB : stm32l1xx_rcc.c
  • CR_MUX_SEG_BB : stm32l1xx_lcd.c
  • CR_OFFSET : stm32l1xx_rcc.c , stm32l1xx_pwr.c , stm32l1xx_lcd.c
  • CR_PLLON_BB : stm32l1xx_rcc.c
  • CR_PLS_MASK : stm32l1xx_pwr.c
  • CR_PVDE_BB : stm32l1xx_pwr.c
  • CR_ULP_BB : stm32l1xx_pwr.c
  • CR_VOS_MASK : stm32l1xx_pwr.c
  • CRC : stm32l1xx.h
  • CRC_BASE : stm32l1xx.h
  • CRC_CR_RESET : stm32l1xx.h
  • CRC_DR_DR : stm32l1xx.h
  • CRC_IDR_IDR : stm32l1xx.h
  • CSR_BYTE2_ADDRESS : stm32l1xx_rcc.c
  • CSR_EWUP_BB : stm32l1xx_pwr.c
  • CSR_LSECSSON_BB : stm32l1xx_rcc.c
  • CSR_LSION_BB : stm32l1xx_rcc.c
  • CSR_OFFSET : stm32l1xx_pwr.c , stm32l1xx_rcc.c
  • CSR_RTCEN_BB : stm32l1xx_rcc.c
  • CSR_RTCRST_BB : stm32l1xx_rcc.c
  • CSSON_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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- d -

  • DAC : stm32l1xx.h
  • DAC_Align_12b_L : stm32l1xx_dac.h
  • DAC_Align_12b_R : stm32l1xx_dac.h
  • DAC_Align_8b_R : stm32l1xx_dac.h
  • DAC_BASE : stm32l1xx.h
  • DAC_Channel_1 : stm32l1xx_dac.h
  • DAC_Channel_2 : stm32l1xx_dac.h
  • DAC_CR_BOFF1 : stm32l1xx.h
  • DAC_CR_BOFF2 : stm32l1xx.h
  • DAC_CR_DMAEN1 : stm32l1xx.h
  • DAC_CR_DMAEN2 : stm32l1xx.h
  • DAC_CR_DMAUDRIE1 : stm32l1xx.h
  • DAC_CR_DMAUDRIE2 : stm32l1xx.h
  • DAC_CR_EN1 : stm32l1xx.h
  • DAC_CR_EN2 : stm32l1xx.h
  • DAC_CR_MAMP1 : stm32l1xx.h
  • DAC_CR_MAMP1_0 : stm32l1xx.h
  • DAC_CR_MAMP1_1 : stm32l1xx.h
  • DAC_CR_MAMP1_2 : stm32l1xx.h
  • DAC_CR_MAMP1_3 : stm32l1xx.h
  • DAC_CR_MAMP2 : stm32l1xx.h
  • DAC_CR_MAMP2_0 : stm32l1xx.h
  • DAC_CR_MAMP2_1 : stm32l1xx.h
  • DAC_CR_MAMP2_2 : stm32l1xx.h
  • DAC_CR_MAMP2_3 : stm32l1xx.h
  • DAC_CR_TEN1 : stm32l1xx.h
  • DAC_CR_TEN2 : stm32l1xx.h
  • DAC_CR_TSEL1 : stm32l1xx.h
  • DAC_CR_TSEL1_0 : stm32l1xx.h
  • DAC_CR_TSEL1_1 : stm32l1xx.h
  • DAC_CR_TSEL1_2 : stm32l1xx.h
  • DAC_CR_TSEL2 : stm32l1xx.h
  • DAC_CR_TSEL2_0 : stm32l1xx.h
  • DAC_CR_TSEL2_1 : stm32l1xx.h
  • DAC_CR_TSEL2_2 : stm32l1xx.h
  • DAC_CR_WAVE1 : stm32l1xx.h
  • DAC_CR_WAVE1_0 : stm32l1xx.h
  • DAC_CR_WAVE1_1 : stm32l1xx.h
  • DAC_CR_WAVE2 : stm32l1xx.h
  • DAC_CR_WAVE2_0 : stm32l1xx.h
  • DAC_CR_WAVE2_1 : stm32l1xx.h
  • DAC_DHR12L1_DACC1DHR : stm32l1xx.h
  • DAC_DHR12L2_DACC2DHR : stm32l1xx.h
  • DAC_DHR12LD_DACC1DHR : stm32l1xx.h
  • DAC_DHR12LD_DACC2DHR : stm32l1xx.h
  • DAC_DHR12R1_DACC1DHR : stm32l1xx.h
  • DAC_DHR12R2_DACC2DHR : stm32l1xx.h
  • DAC_DHR12RD_DACC1DHR : stm32l1xx.h
  • DAC_DHR12RD_DACC2DHR : stm32l1xx.h
  • DAC_DHR8R1_DACC1DHR : stm32l1xx.h
  • DAC_DHR8R2_DACC2DHR : stm32l1xx.h
  • DAC_DHR8RD_DACC1DHR : stm32l1xx.h
  • DAC_DHR8RD_DACC2DHR : stm32l1xx.h
  • DAC_DOR1_DACC1DOR : stm32l1xx.h
  • DAC_DOR2_DACC2DOR : stm32l1xx.h
  • DAC_FLAG_DMAUDR : stm32l1xx_dac.h
  • DAC_IT_DMAUDR : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bit0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits10_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits11_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits1_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits2_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits3_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits4_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits5_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits6_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits7_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits8_0 : stm32l1xx_dac.h
  • DAC_LFSRUnmask_Bits9_0 : stm32l1xx_dac.h
  • DAC_OutputBuffer_Disable : stm32l1xx_dac.h
  • DAC_OutputBuffer_Enable : stm32l1xx_dac.h
  • DAC_SR_DMAUDR1 : stm32l1xx.h
  • DAC_SR_DMAUDR2 : stm32l1xx.h
  • DAC_SWTRIGR_SWTRIG1 : stm32l1xx.h
  • DAC_SWTRIGR_SWTRIG2 : stm32l1xx.h
  • DAC_TriangleAmplitude_1 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_1023 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_127 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_15 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_2047 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_255 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_3 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_31 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_4095 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_511 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_63 : stm32l1xx_dac.h
  • DAC_TriangleAmplitude_7 : stm32l1xx_dac.h
  • DAC_Trigger_Ext_IT9 : stm32l1xx_dac.h
  • DAC_Trigger_None : stm32l1xx_dac.h
  • DAC_Trigger_Software : stm32l1xx_dac.h
  • DAC_Trigger_T2_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T4_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T6_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T7_TRGO : stm32l1xx_dac.h
  • DAC_Trigger_T9_TRGO : stm32l1xx_dac.h
  • DAC_Wave_Noise : stm32l1xx_dac.h
  • DAC_Wave_Triangle : stm32l1xx_dac.h
  • DAC_WaveGeneration_Noise : stm32l1xx_dac.h
  • DAC_WaveGeneration_None : stm32l1xx_dac.h
  • DAC_WaveGeneration_Triangle : stm32l1xx_dac.h
  • DBGMCU : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_IWDG_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_RTC_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM2_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM3_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM4_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM5_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM6_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_TIM7_STOP : stm32l1xx.h
  • DBGMCU_APB1_FZ_DBG_WWDG_STOP : stm32l1xx.h
  • DBGMCU_APB2_FZ_DBG_TIM10_STOP : stm32l1xx.h
  • DBGMCU_APB2_FZ_DBG_TIM11_STOP : stm32l1xx.h
  • DBGMCU_APB2_FZ_DBG_TIM9_STOP : stm32l1xx.h
  • DBGMCU_BASE : stm32l1xx.h
  • DBGMCU_CR_DBG_SLEEP : stm32l1xx.h
  • DBGMCU_CR_DBG_STANDBY : stm32l1xx.h
  • DBGMCU_CR_DBG_STOP : stm32l1xx.h
  • DBGMCU_CR_TRACE_IOEN : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE_0 : stm32l1xx.h
  • DBGMCU_CR_TRACE_MODE_1 : stm32l1xx.h
  • DBGMCU_I2C1_SMBUS_TIMEOUT : stm32l1xx_dbgmcu.h
  • DBGMCU_I2C2_SMBUS_TIMEOUT : stm32l1xx_dbgmcu.h
  • DBGMCU_IDCODE_DEV_ID : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_0 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_1 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_10 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_11 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_12 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_13 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_14 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_15 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_2 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_3 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_4 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_5 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_6 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_7 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_8 : stm32l1xx.h
  • DBGMCU_IDCODE_REV_ID_9 : stm32l1xx.h
  • DBGMCU_IWDG_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_RTC_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_SLEEP : stm32l1xx_dbgmcu.h
  • DBGMCU_STANDBY : stm32l1xx_dbgmcu.h
  • DBGMCU_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM10_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM11_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM2_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM3_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM4_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM5_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM6_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM7_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_TIM9_STOP : stm32l1xx_dbgmcu.h
  • DBGMCU_WWDG_STOP : stm32l1xx_dbgmcu.h
  • DBP_BitNumber : stm32l1xx_pwr.c
  • DCTRL_CLEAR_MASK : stm32l1xx_sdio.c
  • DCTRL_DMAEN_BB : stm32l1xx_sdio.c
  • DCTRL_OFFSET : stm32l1xx_sdio.c
  • DCTRL_RWMOD_BB : stm32l1xx_sdio.c
  • DCTRL_RWSTART_BB : stm32l1xx_sdio.c
  • DCTRL_RWSTOP_BB : stm32l1xx_sdio.c
  • DCTRL_SDIOEN_BB : stm32l1xx_sdio.c
  • DEAD_MASK : stm32l1xx_lcd.c
  • DHR12R1_OFFSET : stm32l1xx_dac.c
  • DHR12R2_OFFSET : stm32l1xx_dac.c
  • DHR12RD_OFFSET : stm32l1xx_dac.c
  • DMA1 : stm32l1xx.h
  • DMA1_BASE : stm32l1xx.h
  • DMA1_Channel1 : stm32l1xx.h
  • DMA1_Channel1_BASE : stm32l1xx.h
  • DMA1_CHANNEL1_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel2 : stm32l1xx.h
  • DMA1_Channel2_BASE : stm32l1xx.h
  • DMA1_CHANNEL2_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel3 : stm32l1xx.h
  • DMA1_Channel3_BASE : stm32l1xx.h
  • DMA1_CHANNEL3_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel4 : stm32l1xx.h
  • DMA1_Channel4_BASE : stm32l1xx.h
  • DMA1_CHANNEL4_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel5 : stm32l1xx.h
  • DMA1_Channel5_BASE : stm32l1xx.h
  • DMA1_CHANNEL5_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel6 : stm32l1xx.h
  • DMA1_Channel6_BASE : stm32l1xx.h
  • DMA1_CHANNEL6_IT_MASK : stm32l1xx_dma.c
  • DMA1_Channel7 : stm32l1xx.h
  • DMA1_Channel7_BASE : stm32l1xx.h
  • DMA1_CHANNEL7_IT_MASK : stm32l1xx_dma.c
  • DMA1_FLAG_GL1 : stm32l1xx_dma.h
  • DMA1_FLAG_GL2 : stm32l1xx_dma.h
  • DMA1_FLAG_GL3 : stm32l1xx_dma.h
  • DMA1_FLAG_GL4 : stm32l1xx_dma.h
  • DMA1_FLAG_GL5 : stm32l1xx_dma.h
  • DMA1_FLAG_GL6 : stm32l1xx_dma.h
  • DMA1_FLAG_GL7 : stm32l1xx_dma.h
  • DMA1_FLAG_HT1 : stm32l1xx_dma.h
  • DMA1_FLAG_HT2 : stm32l1xx_dma.h
  • DMA1_FLAG_HT3 : stm32l1xx_dma.h
  • DMA1_FLAG_HT4 : stm32l1xx_dma.h
  • DMA1_FLAG_HT5 : stm32l1xx_dma.h
  • DMA1_FLAG_HT6 : stm32l1xx_dma.h
  • DMA1_FLAG_HT7 : stm32l1xx_dma.h
  • DMA1_FLAG_TC1 : stm32l1xx_dma.h
  • DMA1_FLAG_TC2 : stm32l1xx_dma.h
  • DMA1_FLAG_TC3 : stm32l1xx_dma.h
  • DMA1_FLAG_TC4 : stm32l1xx_dma.h
  • DMA1_FLAG_TC5 : stm32l1xx_dma.h
  • DMA1_FLAG_TC6 : stm32l1xx_dma.h
  • DMA1_FLAG_TC7 : stm32l1xx_dma.h
  • DMA1_FLAG_TE1 : stm32l1xx_dma.h
  • DMA1_FLAG_TE2 : stm32l1xx_dma.h
  • DMA1_FLAG_TE3 : stm32l1xx_dma.h
  • DMA1_FLAG_TE4 : stm32l1xx_dma.h
  • DMA1_FLAG_TE5 : stm32l1xx_dma.h
  • DMA1_FLAG_TE6 : stm32l1xx_dma.h
  • DMA1_FLAG_TE7 : stm32l1xx_dma.h
  • DMA1_IT_GL1 : stm32l1xx_dma.h
  • DMA1_IT_GL2 : stm32l1xx_dma.h
  • DMA1_IT_GL3 : stm32l1xx_dma.h
  • DMA1_IT_GL4 : stm32l1xx_dma.h
  • DMA1_IT_GL5 : stm32l1xx_dma.h
  • DMA1_IT_GL6 : stm32l1xx_dma.h
  • DMA1_IT_GL7 : stm32l1xx_dma.h
  • DMA1_IT_HT1 : stm32l1xx_dma.h
  • DMA1_IT_HT2 : stm32l1xx_dma.h
  • DMA1_IT_HT3 : stm32l1xx_dma.h
  • DMA1_IT_HT4 : stm32l1xx_dma.h
  • DMA1_IT_HT5 : stm32l1xx_dma.h
  • DMA1_IT_HT6 : stm32l1xx_dma.h
  • DMA1_IT_HT7 : stm32l1xx_dma.h
  • DMA1_IT_TC1 : stm32l1xx_dma.h
  • DMA1_IT_TC2 : stm32l1xx_dma.h
  • DMA1_IT_TC3 : stm32l1xx_dma.h
  • DMA1_IT_TC4 : stm32l1xx_dma.h
  • DMA1_IT_TC5 : stm32l1xx_dma.h
  • DMA1_IT_TC6 : stm32l1xx_dma.h
  • DMA1_IT_TC7 : stm32l1xx_dma.h
  • DMA1_IT_TE1 : stm32l1xx_dma.h
  • DMA1_IT_TE2 : stm32l1xx_dma.h
  • DMA1_IT_TE3 : stm32l1xx_dma.h
  • DMA1_IT_TE4 : stm32l1xx_dma.h
  • DMA1_IT_TE5 : stm32l1xx_dma.h
  • DMA1_IT_TE6 : stm32l1xx_dma.h
  • DMA1_IT_TE7 : stm32l1xx_dma.h
  • DMA2 : stm32l1xx.h
  • DMA2_BASE : stm32l1xx.h
  • DMA2_Channel1 : stm32l1xx.h
  • DMA2_Channel1_BASE : stm32l1xx.h
  • DMA2_CHANNEL1_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel2 : stm32l1xx.h
  • DMA2_Channel2_BASE : stm32l1xx.h
  • DMA2_CHANNEL2_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel3 : stm32l1xx.h
  • DMA2_Channel3_BASE : stm32l1xx.h
  • DMA2_CHANNEL3_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel4 : stm32l1xx.h
  • DMA2_Channel4_BASE : stm32l1xx.h
  • DMA2_CHANNEL4_IT_MASK : stm32l1xx_dma.c
  • DMA2_Channel5 : stm32l1xx.h
  • DMA2_Channel5_BASE : stm32l1xx.h
  • DMA2_CHANNEL5_IT_MASK : stm32l1xx_dma.c
  • DMA2_FLAG_GL1 : stm32l1xx_dma.h
  • DMA2_FLAG_GL2 : stm32l1xx_dma.h
  • DMA2_FLAG_GL3 : stm32l1xx_dma.h
  • DMA2_FLAG_GL4 : stm32l1xx_dma.h
  • DMA2_FLAG_GL5 : stm32l1xx_dma.h
  • DMA2_FLAG_HT1 : stm32l1xx_dma.h
  • DMA2_FLAG_HT2 : stm32l1xx_dma.h
  • DMA2_FLAG_HT3 : stm32l1xx_dma.h
  • DMA2_FLAG_HT4 : stm32l1xx_dma.h
  • DMA2_FLAG_HT5 : stm32l1xx_dma.h
  • DMA2_FLAG_TC1 : stm32l1xx_dma.h
  • DMA2_FLAG_TC2 : stm32l1xx_dma.h
  • DMA2_FLAG_TC3 : stm32l1xx_dma.h
  • DMA2_FLAG_TC4 : stm32l1xx_dma.h
  • DMA2_FLAG_TC5 : stm32l1xx_dma.h
  • DMA2_FLAG_TE1 : stm32l1xx_dma.h
  • DMA2_FLAG_TE2 : stm32l1xx_dma.h
  • DMA2_FLAG_TE3 : stm32l1xx_dma.h
  • DMA2_FLAG_TE4 : stm32l1xx_dma.h
  • DMA2_FLAG_TE5 : stm32l1xx_dma.h
  • DMA2_IT_GL1 : stm32l1xx_dma.h
  • DMA2_IT_GL2 : stm32l1xx_dma.h
  • DMA2_IT_GL3 : stm32l1xx_dma.h
  • DMA2_IT_GL4 : stm32l1xx_dma.h
  • DMA2_IT_GL5 : stm32l1xx_dma.h
  • DMA2_IT_HT1 : stm32l1xx_dma.h
  • DMA2_IT_HT2 : stm32l1xx_dma.h
  • DMA2_IT_HT3 : stm32l1xx_dma.h
  • DMA2_IT_HT4 : stm32l1xx_dma.h
  • DMA2_IT_HT5 : stm32l1xx_dma.h
  • DMA2_IT_TC1 : stm32l1xx_dma.h
  • DMA2_IT_TC2 : stm32l1xx_dma.h
  • DMA2_IT_TC3 : stm32l1xx_dma.h
  • DMA2_IT_TC4 : stm32l1xx_dma.h
  • DMA2_IT_TC5 : stm32l1xx_dma.h
  • DMA2_IT_TE1 : stm32l1xx_dma.h
  • DMA2_IT_TE2 : stm32l1xx_dma.h
  • DMA2_IT_TE3 : stm32l1xx_dma.h
  • DMA2_IT_TE4 : stm32l1xx_dma.h
  • DMA2_IT_TE5 : stm32l1xx_dma.h
  • DMA_CCR1_CIRC : stm32l1xx.h
  • DMA_CCR1_DIR : stm32l1xx.h
  • DMA_CCR1_EN : stm32l1xx.h
  • DMA_CCR1_HTIE : stm32l1xx.h
  • DMA_CCR1_MEM2MEM : stm32l1xx.h
  • DMA_CCR1_MINC : stm32l1xx.h
  • DMA_CCR1_MSIZE : stm32l1xx.h
  • DMA_CCR1_MSIZE_0 : stm32l1xx.h
  • DMA_CCR1_MSIZE_1 : stm32l1xx.h
  • DMA_CCR1_PINC : stm32l1xx.h
  • DMA_CCR1_PL : stm32l1xx.h
  • DMA_CCR1_PL_0 : stm32l1xx.h
  • DMA_CCR1_PL_1 : stm32l1xx.h
  • DMA_CCR1_PSIZE : stm32l1xx.h
  • DMA_CCR1_PSIZE_0 : stm32l1xx.h
  • DMA_CCR1_PSIZE_1 : stm32l1xx.h
  • DMA_CCR1_TCIE : stm32l1xx.h
  • DMA_CCR1_TEIE : stm32l1xx.h
  • DMA_CCR2_CIRC : stm32l1xx.h
  • DMA_CCR2_DIR : stm32l1xx.h
  • DMA_CCR2_EN : stm32l1xx.h
  • DMA_CCR2_HTIE : stm32l1xx.h
  • DMA_CCR2_MEM2MEM : stm32l1xx.h
  • DMA_CCR2_MINC : stm32l1xx.h
  • DMA_CCR2_MSIZE : stm32l1xx.h
  • DMA_CCR2_MSIZE_0 : stm32l1xx.h
  • DMA_CCR2_MSIZE_1 : stm32l1xx.h
  • DMA_CCR2_PINC : stm32l1xx.h
  • DMA_CCR2_PL : stm32l1xx.h
  • DMA_CCR2_PL_0 : stm32l1xx.h
  • DMA_CCR2_PL_1 : stm32l1xx.h
  • DMA_CCR2_PSIZE : stm32l1xx.h
  • DMA_CCR2_PSIZE_0 : stm32l1xx.h
  • DMA_CCR2_PSIZE_1 : stm32l1xx.h
  • DMA_CCR2_TCIE : stm32l1xx.h
  • DMA_CCR2_TEIE : stm32l1xx.h
  • DMA_CCR3_CIRC : stm32l1xx.h
  • DMA_CCR3_DIR : stm32l1xx.h
  • DMA_CCR3_EN : stm32l1xx.h
  • DMA_CCR3_HTIE : stm32l1xx.h
  • DMA_CCR3_MEM2MEM : stm32l1xx.h
  • DMA_CCR3_MINC : stm32l1xx.h
  • DMA_CCR3_MSIZE : stm32l1xx.h
  • DMA_CCR3_MSIZE_0 : stm32l1xx.h
  • DMA_CCR3_MSIZE_1 : stm32l1xx.h
  • DMA_CCR3_PINC : stm32l1xx.h
  • DMA_CCR3_PL : stm32l1xx.h
  • DMA_CCR3_PL_0 : stm32l1xx.h
  • DMA_CCR3_PL_1 : stm32l1xx.h
  • DMA_CCR3_PSIZE : stm32l1xx.h
  • DMA_CCR3_PSIZE_0 : stm32l1xx.h
  • DMA_CCR3_PSIZE_1 : stm32l1xx.h
  • DMA_CCR3_TCIE : stm32l1xx.h
  • DMA_CCR3_TEIE : stm32l1xx.h
  • DMA_CCR4_CIRC : stm32l1xx.h
  • DMA_CCR4_DIR : stm32l1xx.h
  • DMA_CCR4_EN : stm32l1xx.h
  • DMA_CCR4_HTIE : stm32l1xx.h
  • DMA_CCR4_MEM2MEM : stm32l1xx.h
  • DMA_CCR4_MINC : stm32l1xx.h
  • DMA_CCR4_MSIZE : stm32l1xx.h
  • DMA_CCR4_MSIZE_0 : stm32l1xx.h
  • DMA_CCR4_MSIZE_1 : stm32l1xx.h
  • DMA_CCR4_PINC : stm32l1xx.h
  • DMA_CCR4_PL : stm32l1xx.h
  • DMA_CCR4_PL_0 : stm32l1xx.h
  • DMA_CCR4_PL_1 : stm32l1xx.h
  • DMA_CCR4_PSIZE : stm32l1xx.h
  • DMA_CCR4_PSIZE_0 : stm32l1xx.h
  • DMA_CCR4_PSIZE_1 : stm32l1xx.h
  • DMA_CCR4_TCIE : stm32l1xx.h
  • DMA_CCR4_TEIE : stm32l1xx.h
  • DMA_CCR5_CIRC : stm32l1xx.h
  • DMA_CCR5_DIR : stm32l1xx.h
  • DMA_CCR5_EN : stm32l1xx.h
  • DMA_CCR5_HTIE : stm32l1xx.h
  • DMA_CCR5_MEM2MEM : stm32l1xx.h
  • DMA_CCR5_MINC : stm32l1xx.h
  • DMA_CCR5_MSIZE : stm32l1xx.h
  • DMA_CCR5_MSIZE_0 : stm32l1xx.h
  • DMA_CCR5_MSIZE_1 : stm32l1xx.h
  • DMA_CCR5_PINC : stm32l1xx.h
  • DMA_CCR5_PL : stm32l1xx.h
  • DMA_CCR5_PL_0 : stm32l1xx.h
  • DMA_CCR5_PL_1 : stm32l1xx.h
  • DMA_CCR5_PSIZE : stm32l1xx.h
  • DMA_CCR5_PSIZE_0 : stm32l1xx.h
  • DMA_CCR5_PSIZE_1 : stm32l1xx.h
  • DMA_CCR5_TCIE : stm32l1xx.h
  • DMA_CCR5_TEIE : stm32l1xx.h
  • DMA_CCR6_CIRC : stm32l1xx.h
  • DMA_CCR6_DIR : stm32l1xx.h
  • DMA_CCR6_EN : stm32l1xx.h
  • DMA_CCR6_HTIE : stm32l1xx.h
  • DMA_CCR6_MEM2MEM : stm32l1xx.h
  • DMA_CCR6_MINC : stm32l1xx.h
  • DMA_CCR6_MSIZE : stm32l1xx.h
  • DMA_CCR6_MSIZE_0 : stm32l1xx.h
  • DMA_CCR6_MSIZE_1 : stm32l1xx.h
  • DMA_CCR6_PINC : stm32l1xx.h
  • DMA_CCR6_PL : stm32l1xx.h
  • DMA_CCR6_PL_0 : stm32l1xx.h
  • DMA_CCR6_PL_1 : stm32l1xx.h
  • DMA_CCR6_PSIZE : stm32l1xx.h
  • DMA_CCR6_PSIZE_0 : stm32l1xx.h
  • DMA_CCR6_PSIZE_1 : stm32l1xx.h
  • DMA_CCR6_TCIE : stm32l1xx.h
  • DMA_CCR6_TEIE : stm32l1xx.h
  • DMA_CCR7_CIRC : stm32l1xx.h
  • DMA_CCR7_DIR : stm32l1xx.h
  • DMA_CCR7_EN : stm32l1xx.h
  • DMA_CCR7_HTIE : stm32l1xx.h
  • DMA_CCR7_MEM2MEM : stm32l1xx.h
  • DMA_CCR7_MINC : stm32l1xx.h
  • DMA_CCR7_MSIZE : stm32l1xx.h
  • DMA_CCR7_MSIZE_0 : stm32l1xx.h
  • DMA_CCR7_MSIZE_1 : stm32l1xx.h
  • DMA_CCR7_PINC : stm32l1xx.h
  • DMA_CCR7_PL : stm32l1xx.h
  • DMA_CCR7_PL_0 : stm32l1xx.h
  • DMA_CCR7_PL_1 : stm32l1xx.h
  • DMA_CCR7_PSIZE : stm32l1xx.h
  • DMA_CCR7_PSIZE_0 : stm32l1xx.h
  • DMA_CCR7_PSIZE_1 : stm32l1xx.h
  • DMA_CCR7_TCIE : stm32l1xx.h
  • DMA_CCR7_TEIE : stm32l1xx.h
  • DMA_CMAR1_MA : stm32l1xx.h
  • DMA_CMAR2_MA : stm32l1xx.h
  • DMA_CMAR3_MA : stm32l1xx.h
  • DMA_CMAR4_MA : stm32l1xx.h
  • DMA_CMAR5_MA : stm32l1xx.h
  • DMA_CMAR6_MA : stm32l1xx.h
  • DMA_CMAR7_MA : stm32l1xx.h
  • DMA_CNDTR1_NDT : stm32l1xx.h
  • DMA_CNDTR2_NDT : stm32l1xx.h
  • DMA_CNDTR3_NDT : stm32l1xx.h
  • DMA_CNDTR4_NDT : stm32l1xx.h
  • DMA_CNDTR5_NDT : stm32l1xx.h
  • DMA_CNDTR6_NDT : stm32l1xx.h
  • DMA_CNDTR7_NDT : stm32l1xx.h
  • DMA_CPAR1_PA : stm32l1xx.h
  • DMA_CPAR2_PA : stm32l1xx.h
  • DMA_CPAR3_PA : stm32l1xx.h
  • DMA_CPAR4_PA : stm32l1xx.h
  • DMA_CPAR5_PA : stm32l1xx.h
  • DMA_CPAR6_PA : stm32l1xx.h
  • DMA_CPAR7_PA : stm32l1xx.h
  • DMA_DIR_PeripheralDST : stm32l1xx_dma.h
  • DMA_DIR_PeripheralSRC : stm32l1xx_dma.h
  • DMA_IFCR_CGIF1 : stm32l1xx.h
  • DMA_IFCR_CGIF2 : stm32l1xx.h
  • DMA_IFCR_CGIF3 : stm32l1xx.h
  • DMA_IFCR_CGIF4 : stm32l1xx.h
  • DMA_IFCR_CGIF5 : stm32l1xx.h
  • DMA_IFCR_CGIF6 : stm32l1xx.h
  • DMA_IFCR_CGIF7 : stm32l1xx.h
  • DMA_IFCR_CHTIF1 : stm32l1xx.h
  • DMA_IFCR_CHTIF2 : stm32l1xx.h
  • DMA_IFCR_CHTIF3 : stm32l1xx.h
  • DMA_IFCR_CHTIF4 : stm32l1xx.h
  • DMA_IFCR_CHTIF5 : stm32l1xx.h
  • DMA_IFCR_CHTIF6 : stm32l1xx.h
  • DMA_IFCR_CHTIF7 : stm32l1xx.h
  • DMA_IFCR_CTCIF1 : stm32l1xx.h
  • DMA_IFCR_CTCIF2 : stm32l1xx.h
  • DMA_IFCR_CTCIF3 : stm32l1xx.h
  • DMA_IFCR_CTCIF4 : stm32l1xx.h
  • DMA_IFCR_CTCIF5 : stm32l1xx.h
  • DMA_IFCR_CTCIF6 : stm32l1xx.h
  • DMA_IFCR_CTCIF7 : stm32l1xx.h
  • DMA_IFCR_CTEIF1 : stm32l1xx.h
  • DMA_IFCR_CTEIF2 : stm32l1xx.h
  • DMA_IFCR_CTEIF3 : stm32l1xx.h
  • DMA_IFCR_CTEIF4 : stm32l1xx.h
  • DMA_IFCR_CTEIF5 : stm32l1xx.h
  • DMA_IFCR_CTEIF6 : stm32l1xx.h
  • DMA_IFCR_CTEIF7 : stm32l1xx.h
  • DMA_ISR_GIF1 : stm32l1xx.h
  • DMA_ISR_GIF2 : stm32l1xx.h
  • DMA_ISR_GIF3 : stm32l1xx.h
  • DMA_ISR_GIF4 : stm32l1xx.h
  • DMA_ISR_GIF5 : stm32l1xx.h
  • DMA_ISR_GIF6 : stm32l1xx.h
  • DMA_ISR_GIF7 : stm32l1xx.h
  • DMA_ISR_HTIF1 : stm32l1xx.h
  • DMA_ISR_HTIF2 : stm32l1xx.h
  • DMA_ISR_HTIF3 : stm32l1xx.h
  • DMA_ISR_HTIF4 : stm32l1xx.h
  • DMA_ISR_HTIF5 : stm32l1xx.h
  • DMA_ISR_HTIF6 : stm32l1xx.h
  • DMA_ISR_HTIF7 : stm32l1xx.h
  • DMA_ISR_TCIF1 : stm32l1xx.h
  • DMA_ISR_TCIF2 : stm32l1xx.h
  • DMA_ISR_TCIF3 : stm32l1xx.h
  • DMA_ISR_TCIF4 : stm32l1xx.h
  • DMA_ISR_TCIF5 : stm32l1xx.h
  • DMA_ISR_TCIF6 : stm32l1xx.h
  • DMA_ISR_TCIF7 : stm32l1xx.h
  • DMA_ISR_TEIF1 : stm32l1xx.h
  • DMA_ISR_TEIF2 : stm32l1xx.h
  • DMA_ISR_TEIF3 : stm32l1xx.h
  • DMA_ISR_TEIF4 : stm32l1xx.h
  • DMA_ISR_TEIF5 : stm32l1xx.h
  • DMA_ISR_TEIF6 : stm32l1xx.h
  • DMA_ISR_TEIF7 : stm32l1xx.h
  • DMA_IT_HT : stm32l1xx_dma.h
  • DMA_IT_TC : stm32l1xx_dma.h
  • DMA_IT_TE : stm32l1xx_dma.h
  • DMA_M2M_Disable : stm32l1xx_dma.h
  • DMA_M2M_Enable : stm32l1xx_dma.h
  • DMA_MemoryDataSize_Byte : stm32l1xx_dma.h
  • DMA_MemoryDataSize_HalfWord : stm32l1xx_dma.h
  • DMA_MemoryDataSize_Word : stm32l1xx_dma.h
  • DMA_MemoryInc_Disable : stm32l1xx_dma.h
  • DMA_MemoryInc_Enable : stm32l1xx_dma.h
  • DMA_Mode_Circular : stm32l1xx_dma.h
  • DMA_Mode_Normal : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_Byte : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_HalfWord : stm32l1xx_dma.h
  • DMA_PeripheralDataSize_Word : stm32l1xx_dma.h
  • DMA_PeripheralInc_Disable : stm32l1xx_dma.h
  • DMA_PeripheralInc_Enable : stm32l1xx_dma.h
  • DMA_Priority_High : stm32l1xx_dma.h
  • DMA_Priority_Low : stm32l1xx_dma.h
  • DMA_Priority_Medium : stm32l1xx_dma.h
  • DMA_Priority_VeryHigh : stm32l1xx_dma.h
  • DMAEN_BitNumber : stm32l1xx_sdio.c
  • DOR_OFFSET : stm32l1xx_dac.c
  • DUAL_SWTRIG_RESET : stm32l1xx_dac.c
  • DUAL_SWTRIG_SET : stm32l1xx_dac.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- e -

  • ENCMDCOMPL_BitNumber : stm32l1xx_sdio.c
  • EWI_BitNumber : stm32l1xx_wwdg.c
  • EWUP_BitNumber : stm32l1xx_pwr.c
  • EXTI : stm32l1xx.h
  • EXTI_BASE : stm32l1xx.h
  • EXTI_EMR_MR0 : stm32l1xx.h
  • EXTI_EMR_MR1 : stm32l1xx.h
  • EXTI_EMR_MR10 : stm32l1xx.h
  • EXTI_EMR_MR11 : stm32l1xx.h
  • EXTI_EMR_MR12 : stm32l1xx.h
  • EXTI_EMR_MR13 : stm32l1xx.h
  • EXTI_EMR_MR14 : stm32l1xx.h
  • EXTI_EMR_MR15 : stm32l1xx.h
  • EXTI_EMR_MR16 : stm32l1xx.h
  • EXTI_EMR_MR17 : stm32l1xx.h
  • EXTI_EMR_MR18 : stm32l1xx.h
  • EXTI_EMR_MR19 : stm32l1xx.h
  • EXTI_EMR_MR2 : stm32l1xx.h
  • EXTI_EMR_MR20 : stm32l1xx.h
  • EXTI_EMR_MR21 : stm32l1xx.h
  • EXTI_EMR_MR22 : stm32l1xx.h
  • EXTI_EMR_MR23 : stm32l1xx.h
  • EXTI_EMR_MR3 : stm32l1xx.h
  • EXTI_EMR_MR4 : stm32l1xx.h
  • EXTI_EMR_MR5 : stm32l1xx.h
  • EXTI_EMR_MR6 : stm32l1xx.h
  • EXTI_EMR_MR7 : stm32l1xx.h
  • EXTI_EMR_MR8 : stm32l1xx.h
  • EXTI_EMR_MR9 : stm32l1xx.h
  • EXTI_FTSR_TR0 : stm32l1xx.h
  • EXTI_FTSR_TR1 : stm32l1xx.h
  • EXTI_FTSR_TR10 : stm32l1xx.h
  • EXTI_FTSR_TR11 : stm32l1xx.h
  • EXTI_FTSR_TR12 : stm32l1xx.h
  • EXTI_FTSR_TR13 : stm32l1xx.h
  • EXTI_FTSR_TR14 : stm32l1xx.h
  • EXTI_FTSR_TR15 : stm32l1xx.h
  • EXTI_FTSR_TR16 : stm32l1xx.h
  • EXTI_FTSR_TR17 : stm32l1xx.h
  • EXTI_FTSR_TR18 : stm32l1xx.h
  • EXTI_FTSR_TR19 : stm32l1xx.h
  • EXTI_FTSR_TR2 : stm32l1xx.h
  • EXTI_FTSR_TR20 : stm32l1xx.h
  • EXTI_FTSR_TR21 : stm32l1xx.h
  • EXTI_FTSR_TR22 : stm32l1xx.h
  • EXTI_FTSR_TR23 : stm32l1xx.h
  • EXTI_FTSR_TR3 : stm32l1xx.h
  • EXTI_FTSR_TR4 : stm32l1xx.h
  • EXTI_FTSR_TR5 : stm32l1xx.h
  • EXTI_FTSR_TR6 : stm32l1xx.h
  • EXTI_FTSR_TR7 : stm32l1xx.h
  • EXTI_FTSR_TR8 : stm32l1xx.h
  • EXTI_FTSR_TR9 : stm32l1xx.h
  • EXTI_IMR_MR0 : stm32l1xx.h
  • EXTI_IMR_MR1 : stm32l1xx.h
  • EXTI_IMR_MR10 : stm32l1xx.h
  • EXTI_IMR_MR11 : stm32l1xx.h
  • EXTI_IMR_MR12 : stm32l1xx.h
  • EXTI_IMR_MR13 : stm32l1xx.h
  • EXTI_IMR_MR14 : stm32l1xx.h
  • EXTI_IMR_MR15 : stm32l1xx.h
  • EXTI_IMR_MR16 : stm32l1xx.h
  • EXTI_IMR_MR17 : stm32l1xx.h
  • EXTI_IMR_MR18 : stm32l1xx.h
  • EXTI_IMR_MR19 : stm32l1xx.h
  • EXTI_IMR_MR2 : stm32l1xx.h
  • EXTI_IMR_MR20 : stm32l1xx.h
  • EXTI_IMR_MR21 : stm32l1xx.h
  • EXTI_IMR_MR22 : stm32l1xx.h
  • EXTI_IMR_MR23 : stm32l1xx.h
  • EXTI_IMR_MR3 : stm32l1xx.h
  • EXTI_IMR_MR4 : stm32l1xx.h
  • EXTI_IMR_MR5 : stm32l1xx.h
  • EXTI_IMR_MR6 : stm32l1xx.h
  • EXTI_IMR_MR7 : stm32l1xx.h
  • EXTI_IMR_MR8 : stm32l1xx.h
  • EXTI_IMR_MR9 : stm32l1xx.h
  • EXTI_Line0 : stm32l1xx_exti.h
  • EXTI_Line1 : stm32l1xx_exti.h
  • EXTI_Line10 : stm32l1xx_exti.h
  • EXTI_Line11 : stm32l1xx_exti.h
  • EXTI_Line12 : stm32l1xx_exti.h
  • EXTI_Line13 : stm32l1xx_exti.h
  • EXTI_Line14 : stm32l1xx_exti.h
  • EXTI_Line15 : stm32l1xx_exti.h
  • EXTI_Line16 : stm32l1xx_exti.h
  • EXTI_Line17 : stm32l1xx_exti.h
  • EXTI_Line18 : stm32l1xx_exti.h
  • EXTI_Line19 : stm32l1xx_exti.h
  • EXTI_Line2 : stm32l1xx_exti.h
  • EXTI_Line20 : stm32l1xx_exti.h
  • EXTI_Line21 : stm32l1xx_exti.h
  • EXTI_Line22 : stm32l1xx_exti.h
  • EXTI_Line23 : stm32l1xx_exti.h
  • EXTI_Line3 : stm32l1xx_exti.h
  • EXTI_Line4 : stm32l1xx_exti.h
  • EXTI_Line5 : stm32l1xx_exti.h
  • EXTI_Line6 : stm32l1xx_exti.h
  • EXTI_Line7 : stm32l1xx_exti.h
  • EXTI_Line8 : stm32l1xx_exti.h
  • EXTI_Line9 : stm32l1xx_exti.h
  • EXTI_LINENONE : stm32l1xx_exti.c
  • EXTI_PinSource0 : stm32l1xx_syscfg.h
  • EXTI_PinSource1 : stm32l1xx_syscfg.h
  • EXTI_PinSource10 : stm32l1xx_syscfg.h
  • EXTI_PinSource11 : stm32l1xx_syscfg.h
  • EXTI_PinSource12 : stm32l1xx_syscfg.h
  • EXTI_PinSource13 : stm32l1xx_syscfg.h
  • EXTI_PinSource14 : stm32l1xx_syscfg.h
  • EXTI_PinSource15 : stm32l1xx_syscfg.h
  • EXTI_PinSource2 : stm32l1xx_syscfg.h
  • EXTI_PinSource3 : stm32l1xx_syscfg.h
  • EXTI_PinSource4 : stm32l1xx_syscfg.h
  • EXTI_PinSource5 : stm32l1xx_syscfg.h
  • EXTI_PinSource6 : stm32l1xx_syscfg.h
  • EXTI_PinSource7 : stm32l1xx_syscfg.h
  • EXTI_PinSource8 : stm32l1xx_syscfg.h
  • EXTI_PinSource9 : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOA : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOB : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOC : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOD : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOE : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOF : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOG : stm32l1xx_syscfg.h
  • EXTI_PortSourceGPIOH : stm32l1xx_syscfg.h
  • EXTI_PR_PR0 : stm32l1xx.h
  • EXTI_PR_PR1 : stm32l1xx.h
  • EXTI_PR_PR10 : stm32l1xx.h
  • EXTI_PR_PR11 : stm32l1xx.h
  • EXTI_PR_PR12 : stm32l1xx.h
  • EXTI_PR_PR13 : stm32l1xx.h
  • EXTI_PR_PR14 : stm32l1xx.h
  • EXTI_PR_PR15 : stm32l1xx.h
  • EXTI_PR_PR16 : stm32l1xx.h
  • EXTI_PR_PR17 : stm32l1xx.h
  • EXTI_PR_PR18 : stm32l1xx.h
  • EXTI_PR_PR19 : stm32l1xx.h
  • EXTI_PR_PR2 : stm32l1xx.h
  • EXTI_PR_PR20 : stm32l1xx.h
  • EXTI_PR_PR21 : stm32l1xx.h
  • EXTI_PR_PR22 : stm32l1xx.h
  • EXTI_PR_PR23 : stm32l1xx.h
  • EXTI_PR_PR3 : stm32l1xx.h
  • EXTI_PR_PR4 : stm32l1xx.h
  • EXTI_PR_PR5 : stm32l1xx.h
  • EXTI_PR_PR6 : stm32l1xx.h
  • EXTI_PR_PR7 : stm32l1xx.h
  • EXTI_PR_PR8 : stm32l1xx.h
  • EXTI_PR_PR9 : stm32l1xx.h
  • EXTI_RTSR_TR0 : stm32l1xx.h
  • EXTI_RTSR_TR1 : stm32l1xx.h
  • EXTI_RTSR_TR10 : stm32l1xx.h
  • EXTI_RTSR_TR11 : stm32l1xx.h
  • EXTI_RTSR_TR12 : stm32l1xx.h
  • EXTI_RTSR_TR13 : stm32l1xx.h
  • EXTI_RTSR_TR14 : stm32l1xx.h
  • EXTI_RTSR_TR15 : stm32l1xx.h
  • EXTI_RTSR_TR16 : stm32l1xx.h
  • EXTI_RTSR_TR17 : stm32l1xx.h
  • EXTI_RTSR_TR18 : stm32l1xx.h
  • EXTI_RTSR_TR19 : stm32l1xx.h
  • EXTI_RTSR_TR2 : stm32l1xx.h
  • EXTI_RTSR_TR20 : stm32l1xx.h
  • EXTI_RTSR_TR21 : stm32l1xx.h
  • EXTI_RTSR_TR22 : stm32l1xx.h
  • EXTI_RTSR_TR23 : stm32l1xx.h
  • EXTI_RTSR_TR3 : stm32l1xx.h
  • EXTI_RTSR_TR4 : stm32l1xx.h
  • EXTI_RTSR_TR5 : stm32l1xx.h
  • EXTI_RTSR_TR6 : stm32l1xx.h
  • EXTI_RTSR_TR7 : stm32l1xx.h
  • EXTI_RTSR_TR8 : stm32l1xx.h
  • EXTI_RTSR_TR9 : stm32l1xx.h
  • EXTI_SWIER_SWIER0 : stm32l1xx.h
  • EXTI_SWIER_SWIER1 : stm32l1xx.h
  • EXTI_SWIER_SWIER10 : stm32l1xx.h
  • EXTI_SWIER_SWIER11 : stm32l1xx.h
  • EXTI_SWIER_SWIER12 : stm32l1xx.h
  • EXTI_SWIER_SWIER13 : stm32l1xx.h
  • EXTI_SWIER_SWIER14 : stm32l1xx.h
  • EXTI_SWIER_SWIER15 : stm32l1xx.h
  • EXTI_SWIER_SWIER16 : stm32l1xx.h
  • EXTI_SWIER_SWIER17 : stm32l1xx.h
  • EXTI_SWIER_SWIER18 : stm32l1xx.h
  • EXTI_SWIER_SWIER19 : stm32l1xx.h
  • EXTI_SWIER_SWIER2 : stm32l1xx.h
  • EXTI_SWIER_SWIER20 : stm32l1xx.h
  • EXTI_SWIER_SWIER21 : stm32l1xx.h
  • EXTI_SWIER_SWIER22 : stm32l1xx.h
  • EXTI_SWIER_SWIER23 : stm32l1xx.h
  • EXTI_SWIER_SWIER3 : stm32l1xx.h
  • EXTI_SWIER_SWIER4 : stm32l1xx.h
  • EXTI_SWIER_SWIER5 : stm32l1xx.h
  • EXTI_SWIER_SWIER6 : stm32l1xx.h
  • EXTI_SWIER_SWIER7 : stm32l1xx.h
  • EXTI_SWIER_SWIER8 : stm32l1xx.h
  • EXTI_SWIER_SWIER9 : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- f -

  • FCR_HD_BB : stm32l1xx_lcd.c
  • FCR_MASK : stm32l1xx_lcd.c
  • FCR_OFFSET : stm32l1xx_lcd.c
  • FLAG_MASK : stm32l1xx_dma.c , stm32l1xx_i2c.c , stm32l1xx_rcc.c
  • FLASH : stm32l1xx.h
  • FLASH_ACR_ACC64 : stm32l1xx.h
  • FLASH_ACR_LATENCY : stm32l1xx.h
  • FLASH_ACR_PRFTEN : stm32l1xx.h
  • FLASH_ACR_RUN_PD : stm32l1xx.h
  • FLASH_ACR_SLEEP_PD : stm32l1xx.h
  • FLASH_BASE : stm32l1xx.h
  • FLASH_ER_PRG_TIMEOUT : stm32l1xx_flash.h
  • FLASH_FLAG_BSY : stm32l1xx_flash.h
  • FLASH_FLAG_ENDHV : stm32l1xx_flash.h
  • FLASH_FLAG_EOP : stm32l1xx_flash.h
  • FLASH_FLAG_OPTVERR : stm32l1xx_flash.h
  • FLASH_FLAG_OPTVERRUSR : stm32l1xx_flash.h
  • FLASH_FLAG_PGAERR : stm32l1xx_flash.h
  • FLASH_FLAG_READY : stm32l1xx_flash.h
  • FLASH_FLAG_SIZERR : stm32l1xx_flash.h
  • FLASH_FLAG_WRPERR : stm32l1xx_flash.h
  • FLASH_IT_EOP : stm32l1xx_flash.h
  • FLASH_IT_ERR : stm32l1xx_flash.h
  • FLASH_Latency_0 : stm32l1xx_flash.h
  • FLASH_Latency_1 : stm32l1xx_flash.h
  • FLASH_OBR_BOR_LEV : stm32l1xx.h
  • FLASH_OBR_IWDG_SW : stm32l1xx.h
  • FLASH_OBR_nRST_BFB2 : stm32l1xx.h
  • FLASH_OBR_nRST_STDBY : stm32l1xx.h
  • FLASH_OBR_nRST_STOP : stm32l1xx.h
  • FLASH_OBR_RDPRT : stm32l1xx.h
  • FLASH_OBR_USER : stm32l1xx.h
  • FLASH_OPTKEY1 : stm32l1xx_flash.h
  • FLASH_OPTKEY2 : stm32l1xx_flash.h
  • FLASH_OPTKEYR_OPTKEYR : stm32l1xx.h
  • FLASH_PDKEY1 : stm32l1xx_flash.h
  • FLASH_PDKEY2 : stm32l1xx_flash.h
  • FLASH_PDKEYR_PDKEYR : stm32l1xx.h
  • FLASH_PECR_DATA : stm32l1xx.h
  • FLASH_PECR_EOPIE : stm32l1xx.h
  • FLASH_PECR_ERASE : stm32l1xx.h
  • FLASH_PECR_ERRIE : stm32l1xx.h
  • FLASH_PECR_FPRG : stm32l1xx.h
  • FLASH_PECR_FTDW : stm32l1xx.h
  • FLASH_PECR_OBL_LAUNCH : stm32l1xx.h
  • FLASH_PECR_OPTLOCK : stm32l1xx.h
  • FLASH_PECR_PARALLBANK : stm32l1xx.h
  • FLASH_PECR_PELOCK : stm32l1xx.h
  • FLASH_PECR_PRGLOCK : stm32l1xx.h
  • FLASH_PECR_PROG : stm32l1xx.h
  • FLASH_PEKEY1 : stm32l1xx_flash.h
  • FLASH_PEKEY2 : stm32l1xx_flash.h
  • FLASH_PEKEYR_PEKEYR : stm32l1xx.h
  • FLASH_PRGKEY1 : stm32l1xx_flash.h
  • FLASH_PRGKEY2 : stm32l1xx_flash.h
  • FLASH_PRGKEYR_PRGKEYR : stm32l1xx.h
  • FLASH_R_BASE : stm32l1xx.h
  • FLASH_SR_BSY : stm32l1xx.h
  • FLASH_SR_ENHV : stm32l1xx.h
  • FLASH_SR_EOP : stm32l1xx.h
  • FLASH_SR_OPTVERR : stm32l1xx.h
  • FLASH_SR_OPTVERRUSR : stm32l1xx.h
  • FLASH_SR_PGAERR : stm32l1xx.h
  • FLASH_SR_READY : stm32l1xx.h
  • FLASH_SR_SIZERR : stm32l1xx.h
  • FLASH_SR_WRPERR : stm32l1xx.h
  • FLASH_WRPR1_WRP : stm32l1xx.h
  • FLASH_WRPR2_WRP : stm32l1xx.h
  • FLASH_WRPR_WRP : stm32l1xx.h
  • FSMC_AccessMode_A : stm32l1xx_fsmc.h
  • FSMC_AccessMode_B : stm32l1xx_fsmc.h
  • FSMC_AccessMode_C : stm32l1xx_fsmc.h
  • FSMC_AccessMode_D : stm32l1xx_fsmc.h
  • FSMC_AsynchronousWait_Disable : stm32l1xx_fsmc.h
  • FSMC_AsynchronousWait_Enable : stm32l1xx_fsmc.h
  • FSMC_Bank1 : stm32l1xx.h
  • FSMC_Bank1_NORSRAM1 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM2 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM3 : stm32l1xx_fsmc.h
  • FSMC_Bank1_NORSRAM4 : stm32l1xx_fsmc.h
  • FSMC_Bank1_R_BASE : stm32l1xx.h
  • FSMC_Bank1E : stm32l1xx.h
  • FSMC_Bank1E_R_BASE : stm32l1xx.h
  • FSMC_BCR1_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR1_BURSTEN : stm32l1xx.h
  • FSMC_BCR1_CBURSTRW : stm32l1xx.h
  • FSMC_BCR1_EXTMOD : stm32l1xx.h
  • FSMC_BCR1_FACCEN : stm32l1xx.h
  • FSMC_BCR1_MBKEN : stm32l1xx.h
  • FSMC_BCR1_MTYP : stm32l1xx.h
  • FSMC_BCR1_MTYP_0 : stm32l1xx.h
  • FSMC_BCR1_MTYP_1 : stm32l1xx.h
  • FSMC_BCR1_MUXEN : stm32l1xx.h
  • FSMC_BCR1_MWID : stm32l1xx.h
  • FSMC_BCR1_MWID_0 : stm32l1xx.h
  • FSMC_BCR1_MWID_1 : stm32l1xx.h
  • FSMC_BCR1_WAITCFG : stm32l1xx.h
  • FSMC_BCR1_WAITEN : stm32l1xx.h
  • FSMC_BCR1_WAITPOL : stm32l1xx.h
  • FSMC_BCR1_WRAPMOD : stm32l1xx.h
  • FSMC_BCR1_WREN : stm32l1xx.h
  • FSMC_BCR2_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR2_BURSTEN : stm32l1xx.h
  • FSMC_BCR2_CBURSTRW : stm32l1xx.h
  • FSMC_BCR2_EXTMOD : stm32l1xx.h
  • FSMC_BCR2_FACCEN : stm32l1xx.h
  • FSMC_BCR2_MBKEN : stm32l1xx.h
  • FSMC_BCR2_MTYP : stm32l1xx.h
  • FSMC_BCR2_MTYP_0 : stm32l1xx.h
  • FSMC_BCR2_MTYP_1 : stm32l1xx.h
  • FSMC_BCR2_MUXEN : stm32l1xx.h
  • FSMC_BCR2_MWID : stm32l1xx.h
  • FSMC_BCR2_MWID_0 : stm32l1xx.h
  • FSMC_BCR2_MWID_1 : stm32l1xx.h
  • FSMC_BCR2_WAITCFG : stm32l1xx.h
  • FSMC_BCR2_WAITEN : stm32l1xx.h
  • FSMC_BCR2_WAITPOL : stm32l1xx.h
  • FSMC_BCR2_WRAPMOD : stm32l1xx.h
  • FSMC_BCR2_WREN : stm32l1xx.h
  • FSMC_BCR3_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR3_BURSTEN : stm32l1xx.h
  • FSMC_BCR3_CBURSTRW : stm32l1xx.h
  • FSMC_BCR3_EXTMOD : stm32l1xx.h
  • FSMC_BCR3_FACCEN : stm32l1xx.h
  • FSMC_BCR3_MBKEN : stm32l1xx.h
  • FSMC_BCR3_MTYP : stm32l1xx.h
  • FSMC_BCR3_MTYP_0 : stm32l1xx.h
  • FSMC_BCR3_MTYP_1 : stm32l1xx.h
  • FSMC_BCR3_MUXEN : stm32l1xx.h
  • FSMC_BCR3_MWID : stm32l1xx.h
  • FSMC_BCR3_MWID_0 : stm32l1xx.h
  • FSMC_BCR3_MWID_1 : stm32l1xx.h
  • FSMC_BCR3_WAITCFG : stm32l1xx.h
  • FSMC_BCR3_WAITEN : stm32l1xx.h
  • FSMC_BCR3_WAITPOL : stm32l1xx.h
  • FSMC_BCR3_WRAPMOD : stm32l1xx.h
  • FSMC_BCR3_WREN : stm32l1xx.h
  • FSMC_BCR4_ASYNCWAIT : stm32l1xx.h
  • FSMC_BCR4_BURSTEN : stm32l1xx.h
  • FSMC_BCR4_CBURSTRW : stm32l1xx.h
  • FSMC_BCR4_EXTMOD : stm32l1xx.h
  • FSMC_BCR4_FACCEN : stm32l1xx.h
  • FSMC_BCR4_MBKEN : stm32l1xx.h
  • FSMC_BCR4_MTYP : stm32l1xx.h
  • FSMC_BCR4_MTYP_0 : stm32l1xx.h
  • FSMC_BCR4_MTYP_1 : stm32l1xx.h
  • FSMC_BCR4_MUXEN : stm32l1xx.h
  • FSMC_BCR4_MWID : stm32l1xx.h
  • FSMC_BCR4_MWID_0 : stm32l1xx.h
  • FSMC_BCR4_MWID_1 : stm32l1xx.h
  • FSMC_BCR4_WAITCFG : stm32l1xx.h
  • FSMC_BCR4_WAITEN : stm32l1xx.h
  • FSMC_BCR4_WAITPOL : stm32l1xx.h
  • FSMC_BCR4_WRAPMOD : stm32l1xx.h
  • FSMC_BCR4_WREN : stm32l1xx.h
  • FSMC_BTR1_ACCMOD : stm32l1xx.h
  • FSMC_BTR1_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR1_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR1_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR1_ADDSET : stm32l1xx.h
  • FSMC_BTR1_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR1_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR1_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR1_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR1_DATAST : stm32l1xx.h
  • FSMC_BTR1_DATAST_0 : stm32l1xx.h
  • FSMC_BTR1_DATAST_1 : stm32l1xx.h
  • FSMC_BTR1_DATAST_2 : stm32l1xx.h
  • FSMC_BTR1_DATAST_3 : stm32l1xx.h
  • FSMC_BTR1_DATLAT : stm32l1xx.h
  • FSMC_BTR1_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR1_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR2_ACCMOD : stm32l1xx.h
  • FSMC_BTR2_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR2_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR2_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR2_ADDSET : stm32l1xx.h
  • FSMC_BTR2_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR2_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR2_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR2_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR2_DATAST : stm32l1xx.h
  • FSMC_BTR2_DATAST_0 : stm32l1xx.h
  • FSMC_BTR2_DATAST_1 : stm32l1xx.h
  • FSMC_BTR2_DATAST_2 : stm32l1xx.h
  • FSMC_BTR2_DATAST_3 : stm32l1xx.h
  • FSMC_BTR2_DATLAT : stm32l1xx.h
  • FSMC_BTR2_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR2_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR3_ACCMOD : stm32l1xx.h
  • FSMC_BTR3_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR3_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR3_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR3_ADDSET : stm32l1xx.h
  • FSMC_BTR3_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR3_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR3_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR3_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR3_DATAST : stm32l1xx.h
  • FSMC_BTR3_DATAST_0 : stm32l1xx.h
  • FSMC_BTR3_DATAST_1 : stm32l1xx.h
  • FSMC_BTR3_DATAST_2 : stm32l1xx.h
  • FSMC_BTR3_DATAST_3 : stm32l1xx.h
  • FSMC_BTR3_DATLAT : stm32l1xx.h
  • FSMC_BTR3_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR3_DATLAT_3 : stm32l1xx.h
  • FSMC_BTR4_ACCMOD : stm32l1xx.h
  • FSMC_BTR4_ACCMOD_0 : stm32l1xx.h
  • FSMC_BTR4_ACCMOD_1 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_0 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_1 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_2 : stm32l1xx.h
  • FSMC_BTR4_ADDHLD_3 : stm32l1xx.h
  • FSMC_BTR4_ADDSET : stm32l1xx.h
  • FSMC_BTR4_ADDSET_0 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_1 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_2 : stm32l1xx.h
  • FSMC_BTR4_ADDSET_3 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_0 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_1 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_2 : stm32l1xx.h
  • FSMC_BTR4_BUSTURN_3 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_0 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_1 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_2 : stm32l1xx.h
  • FSMC_BTR4_CLKDIV_3 : stm32l1xx.h
  • FSMC_BTR4_DATAST : stm32l1xx.h
  • FSMC_BTR4_DATAST_0 : stm32l1xx.h
  • FSMC_BTR4_DATAST_1 : stm32l1xx.h
  • FSMC_BTR4_DATAST_2 : stm32l1xx.h
  • FSMC_BTR4_DATAST_3 : stm32l1xx.h
  • FSMC_BTR4_DATLAT : stm32l1xx.h
  • FSMC_BTR4_DATLAT_0 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_1 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_2 : stm32l1xx.h
  • FSMC_BTR4_DATLAT_3 : stm32l1xx.h
  • FSMC_BurstAccessMode_Disable : stm32l1xx_fsmc.h
  • FSMC_BurstAccessMode_Enable : stm32l1xx_fsmc.h
  • FSMC_BWTR1_ACCMOD : stm32l1xx.h
  • FSMC_BWTR1_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR1_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR1_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR1_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR1_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR1_DATAST : stm32l1xx.h
  • FSMC_BWTR1_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR1_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR1_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR2_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR2_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR2_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR2_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR2_DATAST : stm32l1xx.h
  • FSMC_BWTR2_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR2_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR2_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR3_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR3_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR3_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR3_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR3_DATAST : stm32l1xx.h
  • FSMC_BWTR3_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR3_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR3_DATLAT_3 : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD_0 : stm32l1xx.h
  • FSMC_BWTR4_ACCMOD_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_0 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_2 : stm32l1xx.h
  • FSMC_BWTR4_ADDHLD_3 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_0 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_1 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_2 : stm32l1xx.h
  • FSMC_BWTR4_ADDSET_3 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_0 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_1 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_2 : stm32l1xx.h
  • FSMC_BWTR4_CLKDIV_3 : stm32l1xx.h
  • FSMC_BWTR4_DATAST : stm32l1xx.h
  • FSMC_BWTR4_DATAST_0 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_1 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_2 : stm32l1xx.h
  • FSMC_BWTR4_DATAST_3 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_0 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_1 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_2 : stm32l1xx.h
  • FSMC_BWTR4_DATLAT_3 : stm32l1xx.h
  • FSMC_DataAddressMux_Disable : stm32l1xx_fsmc.h
  • FSMC_DataAddressMux_Enable : stm32l1xx_fsmc.h
  • FSMC_ExtendedMode_Disable : stm32l1xx_fsmc.h
  • FSMC_ExtendedMode_Enable : stm32l1xx_fsmc.h
  • FSMC_MemoryDataWidth_16b : stm32l1xx_fsmc.h
  • FSMC_MemoryDataWidth_8b : stm32l1xx_fsmc.h
  • FSMC_MemoryType_NOR : stm32l1xx_fsmc.h
  • FSMC_MemoryType_PSRAM : stm32l1xx_fsmc.h
  • FSMC_MemoryType_SRAM : stm32l1xx_fsmc.h
  • FSMC_R_BASE : stm32l1xx.h
  • FSMC_WaitSignal_Disable : stm32l1xx_fsmc.h
  • FSMC_WaitSignal_Enable : stm32l1xx_fsmc.h
  • FSMC_WaitSignalActive_BeforeWaitState : stm32l1xx_fsmc.h
  • FSMC_WaitSignalActive_DuringWaitState : stm32l1xx_fsmc.h
  • FSMC_WaitSignalPolarity_High : stm32l1xx_fsmc.h
  • FSMC_WaitSignalPolarity_Low : stm32l1xx_fsmc.h
  • FSMC_WrapMode_Disable : stm32l1xx_fsmc.h
  • FSMC_WrapMode_Enable : stm32l1xx_fsmc.h
  • FSMC_WriteBurst_Disable : stm32l1xx_fsmc.h
  • FSMC_WriteBurst_Enable : stm32l1xx_fsmc.h
  • FSMC_WriteOperation_Disable : stm32l1xx_fsmc.h
  • FSMC_WriteOperation_Enable : stm32l1xx_fsmc.h
  • FWU_BitNumber : stm32l1xx_pwr.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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- g -

  • GPIO_AF_EVENTOUT : stm32l1xx_gpio.h
  • GPIO_AF_FSMC : stm32l1xx_gpio.h
  • GPIO_AF_I2C1 : stm32l1xx_gpio.h
  • GPIO_AF_I2C2 : stm32l1xx_gpio.h
  • GPIO_AF_LCD : stm32l1xx_gpio.h
  • GPIO_AF_MCO : stm32l1xx_gpio.h
  • GPIO_AF_RI : stm32l1xx_gpio.h
  • GPIO_AF_RTC_50Hz : stm32l1xx_gpio.h
  • GPIO_AF_RTC_AF1 : stm32l1xx_gpio.h
  • GPIO_AF_SDIO : stm32l1xx_gpio.h
  • GPIO_AF_SPI1 : stm32l1xx_gpio.h
  • GPIO_AF_SPI2 : stm32l1xx_gpio.h
  • GPIO_AF_SPI3 : stm32l1xx_gpio.h
  • GPIO_AF_SWJ : stm32l1xx_gpio.h
  • GPIO_AF_TIM10 : stm32l1xx_gpio.h
  • GPIO_AF_TIM11 : stm32l1xx_gpio.h
  • GPIO_AF_TIM2 : stm32l1xx_gpio.h
  • GPIO_AF_TIM3 : stm32l1xx_gpio.h
  • GPIO_AF_TIM4 : stm32l1xx_gpio.h
  • GPIO_AF_TIM5 : stm32l1xx_gpio.h
  • GPIO_AF_TIM9 : stm32l1xx_gpio.h
  • GPIO_AF_TRACE : stm32l1xx_gpio.h
  • GPIO_AF_UART4 : stm32l1xx_gpio.h
  • GPIO_AF_UART5 : stm32l1xx_gpio.h
  • GPIO_AF_USART1 : stm32l1xx_gpio.h
  • GPIO_AF_USART2 : stm32l1xx_gpio.h
  • GPIO_AF_USART3 : stm32l1xx_gpio.h
  • GPIO_AF_USB : stm32l1xx_gpio.h
  • GPIO_AF_WKUP : stm32l1xx_gpio.h
  • GPIO_AFRH_AFRH10 : stm32l1xx.h
  • GPIO_AFRH_AFRH11 : stm32l1xx.h
  • GPIO_AFRH_AFRH12 : stm32l1xx.h
  • GPIO_AFRH_AFRH13 : stm32l1xx.h
  • GPIO_AFRH_AFRH14 : stm32l1xx.h
  • GPIO_AFRH_AFRH15 : stm32l1xx.h
  • GPIO_AFRH_AFRH8 : stm32l1xx.h
  • GPIO_AFRH_AFRH9 : stm32l1xx.h
  • GPIO_AFRL_AFRL0 : stm32l1xx.h
  • GPIO_AFRL_AFRL1 : stm32l1xx.h
  • GPIO_AFRL_AFRL2 : stm32l1xx.h
  • GPIO_AFRL_AFRL3 : stm32l1xx.h
  • GPIO_AFRL_AFRL4 : stm32l1xx.h
  • GPIO_AFRL_AFRL5 : stm32l1xx.h
  • GPIO_AFRL_AFRL6 : stm32l1xx.h
  • GPIO_AFRL_AFRL7 : stm32l1xx.h
  • GPIO_BSRR_BR_0 : stm32l1xx.h
  • GPIO_BSRR_BR_1 : stm32l1xx.h
  • GPIO_BSRR_BR_10 : stm32l1xx.h
  • GPIO_BSRR_BR_11 : stm32l1xx.h
  • GPIO_BSRR_BR_12 : stm32l1xx.h
  • GPIO_BSRR_BR_13 : stm32l1xx.h
  • GPIO_BSRR_BR_14 : stm32l1xx.h
  • GPIO_BSRR_BR_15 : stm32l1xx.h
  • GPIO_BSRR_BR_2 : stm32l1xx.h
  • GPIO_BSRR_BR_3 : stm32l1xx.h
  • GPIO_BSRR_BR_4 : stm32l1xx.h
  • GPIO_BSRR_BR_5 : stm32l1xx.h
  • GPIO_BSRR_BR_6 : stm32l1xx.h
  • GPIO_BSRR_BR_7 : stm32l1xx.h
  • GPIO_BSRR_BR_8 : stm32l1xx.h
  • GPIO_BSRR_BR_9 : stm32l1xx.h
  • GPIO_BSRR_BS_0 : stm32l1xx.h
  • GPIO_BSRR_BS_1 : stm32l1xx.h
  • GPIO_BSRR_BS_10 : stm32l1xx.h
  • GPIO_BSRR_BS_11 : stm32l1xx.h
  • GPIO_BSRR_BS_12 : stm32l1xx.h
  • GPIO_BSRR_BS_13 : stm32l1xx.h
  • GPIO_BSRR_BS_14 : stm32l1xx.h
  • GPIO_BSRR_BS_15 : stm32l1xx.h
  • GPIO_BSRR_BS_2 : stm32l1xx.h
  • GPIO_BSRR_BS_3 : stm32l1xx.h
  • GPIO_BSRR_BS_4 : stm32l1xx.h
  • GPIO_BSRR_BS_5 : stm32l1xx.h
  • GPIO_BSRR_BS_6 : stm32l1xx.h
  • GPIO_BSRR_BS_7 : stm32l1xx.h
  • GPIO_BSRR_BS_8 : stm32l1xx.h
  • GPIO_BSRR_BS_9 : stm32l1xx.h
  • GPIO_IDR_IDR_0 : stm32l1xx.h
  • GPIO_IDR_IDR_1 : stm32l1xx.h
  • GPIO_IDR_IDR_10 : stm32l1xx.h
  • GPIO_IDR_IDR_11 : stm32l1xx.h
  • GPIO_IDR_IDR_12 : stm32l1xx.h
  • GPIO_IDR_IDR_13 : stm32l1xx.h
  • GPIO_IDR_IDR_14 : stm32l1xx.h
  • GPIO_IDR_IDR_15 : stm32l1xx.h
  • GPIO_IDR_IDR_2 : stm32l1xx.h
  • GPIO_IDR_IDR_3 : stm32l1xx.h
  • GPIO_IDR_IDR_4 : stm32l1xx.h
  • GPIO_IDR_IDR_5 : stm32l1xx.h
  • GPIO_IDR_IDR_6 : stm32l1xx.h
  • GPIO_IDR_IDR_7 : stm32l1xx.h
  • GPIO_IDR_IDR_8 : stm32l1xx.h
  • GPIO_IDR_IDR_9 : stm32l1xx.h
  • GPIO_LCKR_LCK0 : stm32l1xx.h
  • GPIO_LCKR_LCK1 : stm32l1xx.h
  • GPIO_LCKR_LCK10 : stm32l1xx.h
  • GPIO_LCKR_LCK11 : stm32l1xx.h
  • GPIO_LCKR_LCK12 : stm32l1xx.h
  • GPIO_LCKR_LCK13 : stm32l1xx.h
  • GPIO_LCKR_LCK14 : stm32l1xx.h
  • GPIO_LCKR_LCK15 : stm32l1xx.h
  • GPIO_LCKR_LCK2 : stm32l1xx.h
  • GPIO_LCKR_LCK3 : stm32l1xx.h
  • GPIO_LCKR_LCK4 : stm32l1xx.h
  • GPIO_LCKR_LCK5 : stm32l1xx.h
  • GPIO_LCKR_LCK6 : stm32l1xx.h
  • GPIO_LCKR_LCK7 : stm32l1xx.h
  • GPIO_LCKR_LCK8 : stm32l1xx.h
  • GPIO_LCKR_LCK9 : stm32l1xx.h
  • GPIO_LCKR_LCKK : stm32l1xx.h
  • GPIO_Mode_AIN : stm32l1xx_gpio.h
  • GPIO_MODER_MODER0 : stm32l1xx.h
  • GPIO_MODER_MODER0_0 : stm32l1xx.h
  • GPIO_MODER_MODER0_1 : stm32l1xx.h
  • GPIO_MODER_MODER1 : stm32l1xx.h
  • GPIO_MODER_MODER10 : stm32l1xx.h
  • GPIO_MODER_MODER10_0 : stm32l1xx.h
  • GPIO_MODER_MODER10_1 : stm32l1xx.h
  • GPIO_MODER_MODER11 : stm32l1xx.h
  • GPIO_MODER_MODER11_0 : stm32l1xx.h
  • GPIO_MODER_MODER11_1 : stm32l1xx.h
  • GPIO_MODER_MODER12 : stm32l1xx.h
  • GPIO_MODER_MODER12_0 : stm32l1xx.h
  • GPIO_MODER_MODER12_1 : stm32l1xx.h
  • GPIO_MODER_MODER13 : stm32l1xx.h
  • GPIO_MODER_MODER13_0 : stm32l1xx.h
  • GPIO_MODER_MODER13_1 : stm32l1xx.h
  • GPIO_MODER_MODER14 : stm32l1xx.h
  • GPIO_MODER_MODER14_0 : stm32l1xx.h
  • GPIO_MODER_MODER14_1 : stm32l1xx.h
  • GPIO_MODER_MODER15 : stm32l1xx.h
  • GPIO_MODER_MODER15_0 : stm32l1xx.h
  • GPIO_MODER_MODER15_1 : stm32l1xx.h
  • GPIO_MODER_MODER1_0 : stm32l1xx.h
  • GPIO_MODER_MODER1_1 : stm32l1xx.h
  • GPIO_MODER_MODER2 : stm32l1xx.h
  • GPIO_MODER_MODER2_0 : stm32l1xx.h
  • GPIO_MODER_MODER2_1 : stm32l1xx.h
  • GPIO_MODER_MODER3 : stm32l1xx.h
  • GPIO_MODER_MODER3_0 : stm32l1xx.h
  • GPIO_MODER_MODER3_1 : stm32l1xx.h
  • GPIO_MODER_MODER4 : stm32l1xx.h
  • GPIO_MODER_MODER4_0 : stm32l1xx.h
  • GPIO_MODER_MODER4_1 : stm32l1xx.h
  • GPIO_MODER_MODER5 : stm32l1xx.h
  • GPIO_MODER_MODER5_0 : stm32l1xx.h
  • GPIO_MODER_MODER5_1 : stm32l1xx.h
  • GPIO_MODER_MODER6 : stm32l1xx.h
  • GPIO_MODER_MODER6_0 : stm32l1xx.h
  • GPIO_MODER_MODER6_1 : stm32l1xx.h
  • GPIO_MODER_MODER7 : stm32l1xx.h
  • GPIO_MODER_MODER7_0 : stm32l1xx.h
  • GPIO_MODER_MODER7_1 : stm32l1xx.h
  • GPIO_MODER_MODER8 : stm32l1xx.h
  • GPIO_MODER_MODER8_0 : stm32l1xx.h
  • GPIO_MODER_MODER8_1 : stm32l1xx.h
  • GPIO_MODER_MODER9 : stm32l1xx.h
  • GPIO_MODER_MODER9_0 : stm32l1xx.h
  • GPIO_MODER_MODER9_1 : stm32l1xx.h
  • GPIO_ODR_ODR_0 : stm32l1xx.h
  • GPIO_ODR_ODR_1 : stm32l1xx.h
  • GPIO_ODR_ODR_10 : stm32l1xx.h
  • GPIO_ODR_ODR_11 : stm32l1xx.h
  • GPIO_ODR_ODR_12 : stm32l1xx.h
  • GPIO_ODR_ODR_13 : stm32l1xx.h
  • GPIO_ODR_ODR_14 : stm32l1xx.h
  • GPIO_ODR_ODR_15 : stm32l1xx.h
  • GPIO_ODR_ODR_2 : stm32l1xx.h
  • GPIO_ODR_ODR_3 : stm32l1xx.h
  • GPIO_ODR_ODR_4 : stm32l1xx.h
  • GPIO_ODR_ODR_5 : stm32l1xx.h
  • GPIO_ODR_ODR_6 : stm32l1xx.h
  • GPIO_ODR_ODR_7 : stm32l1xx.h
  • GPIO_ODR_ODR_8 : stm32l1xx.h
  • GPIO_ODR_ODR_9 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR0_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR10_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR11_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR12_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR13_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR14_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR15_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR1_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR2_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR3_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR4_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR5_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR6_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR7_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR8_1 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9_0 : stm32l1xx.h
  • GPIO_OSPEEDER_OSPEEDR9_1 : stm32l1xx.h
  • GPIO_OTYPER_IDR_0 : stm32l1xx.h
  • GPIO_OTYPER_IDR_1 : stm32l1xx.h
  • GPIO_OTYPER_IDR_10 : stm32l1xx.h
  • GPIO_OTYPER_IDR_11 : stm32l1xx.h
  • GPIO_OTYPER_IDR_12 : stm32l1xx.h
  • GPIO_OTYPER_IDR_13 : stm32l1xx.h
  • GPIO_OTYPER_IDR_14 : stm32l1xx.h
  • GPIO_OTYPER_IDR_15 : stm32l1xx.h
  • GPIO_OTYPER_IDR_2 : stm32l1xx.h
  • GPIO_OTYPER_IDR_3 : stm32l1xx.h
  • GPIO_OTYPER_IDR_4 : stm32l1xx.h
  • GPIO_OTYPER_IDR_5 : stm32l1xx.h
  • GPIO_OTYPER_IDR_6 : stm32l1xx.h
  • GPIO_OTYPER_IDR_7 : stm32l1xx.h
  • GPIO_OTYPER_IDR_8 : stm32l1xx.h
  • GPIO_OTYPER_IDR_9 : stm32l1xx.h
  • GPIO_OTYPER_ODR_0 : stm32l1xx.h
  • GPIO_OTYPER_ODR_1 : stm32l1xx.h
  • GPIO_OTYPER_ODR_10 : stm32l1xx.h
  • GPIO_OTYPER_ODR_11 : stm32l1xx.h
  • GPIO_OTYPER_ODR_12 : stm32l1xx.h
  • GPIO_OTYPER_ODR_13 : stm32l1xx.h
  • GPIO_OTYPER_ODR_14 : stm32l1xx.h
  • GPIO_OTYPER_ODR_15 : stm32l1xx.h
  • GPIO_OTYPER_ODR_2 : stm32l1xx.h
  • GPIO_OTYPER_ODR_3 : stm32l1xx.h
  • GPIO_OTYPER_ODR_4 : stm32l1xx.h
  • GPIO_OTYPER_ODR_5 : stm32l1xx.h
  • GPIO_OTYPER_ODR_6 : stm32l1xx.h
  • GPIO_OTYPER_ODR_7 : stm32l1xx.h
  • GPIO_OTYPER_ODR_8 : stm32l1xx.h
  • GPIO_OTYPER_ODR_9 : stm32l1xx.h
  • GPIO_OTYPER_OT_0 : stm32l1xx.h
  • GPIO_OTYPER_OT_1 : stm32l1xx.h
  • GPIO_OTYPER_OT_10 : stm32l1xx.h
  • GPIO_OTYPER_OT_11 : stm32l1xx.h
  • GPIO_OTYPER_OT_12 : stm32l1xx.h
  • GPIO_OTYPER_OT_13 : stm32l1xx.h
  • GPIO_OTYPER_OT_14 : stm32l1xx.h
  • GPIO_OTYPER_OT_15 : stm32l1xx.h
  • GPIO_OTYPER_OT_2 : stm32l1xx.h
  • GPIO_OTYPER_OT_3 : stm32l1xx.h
  • GPIO_OTYPER_OT_4 : stm32l1xx.h
  • GPIO_OTYPER_OT_5 : stm32l1xx.h
  • GPIO_OTYPER_OT_6 : stm32l1xx.h
  • GPIO_OTYPER_OT_7 : stm32l1xx.h
  • GPIO_OTYPER_OT_8 : stm32l1xx.h
  • GPIO_OTYPER_OT_9 : stm32l1xx.h
  • GPIO_Pin_0 : stm32l1xx_gpio.h
  • GPIO_Pin_1 : stm32l1xx_gpio.h
  • GPIO_Pin_10 : stm32l1xx_gpio.h
  • GPIO_Pin_11 : stm32l1xx_gpio.h
  • GPIO_Pin_12 : stm32l1xx_gpio.h
  • GPIO_Pin_13 : stm32l1xx_gpio.h
  • GPIO_Pin_14 : stm32l1xx_gpio.h
  • GPIO_Pin_15 : stm32l1xx_gpio.h
  • GPIO_Pin_2 : stm32l1xx_gpio.h
  • GPIO_Pin_3 : stm32l1xx_gpio.h
  • GPIO_Pin_4 : stm32l1xx_gpio.h
  • GPIO_Pin_5 : stm32l1xx_gpio.h
  • GPIO_Pin_6 : stm32l1xx_gpio.h
  • GPIO_Pin_7 : stm32l1xx_gpio.h
  • GPIO_Pin_8 : stm32l1xx_gpio.h
  • GPIO_Pin_9 : stm32l1xx_gpio.h
  • GPIO_Pin_All : stm32l1xx_gpio.h
  • GPIO_PinSource0 : stm32l1xx_gpio.h
  • GPIO_PinSource1 : stm32l1xx_gpio.h
  • GPIO_PinSource10 : stm32l1xx_gpio.h
  • GPIO_PinSource11 : stm32l1xx_gpio.h
  • GPIO_PinSource12 : stm32l1xx_gpio.h
  • GPIO_PinSource13 : stm32l1xx_gpio.h
  • GPIO_PinSource14 : stm32l1xx_gpio.h
  • GPIO_PinSource15 : stm32l1xx_gpio.h
  • GPIO_PinSource2 : stm32l1xx_gpio.h
  • GPIO_PinSource3 : stm32l1xx_gpio.h
  • GPIO_PinSource4 : stm32l1xx_gpio.h
  • GPIO_PinSource5 : stm32l1xx_gpio.h
  • GPIO_PinSource6 : stm32l1xx_gpio.h
  • GPIO_PinSource7 : stm32l1xx_gpio.h
  • GPIO_PinSource8 : stm32l1xx_gpio.h
  • GPIO_PinSource9 : stm32l1xx_gpio.h
  • GPIO_PUPDR_PUPDR0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR0_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR0_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR10_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR11_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR12_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR13_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR14_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR15_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR1_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR2_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR3_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR4_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR5_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR6_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR7_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR8_1 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9_0 : stm32l1xx.h
  • GPIO_PUPDR_PUPDR9_1 : stm32l1xx.h
  • GPIOA : stm32l1xx.h
  • GPIOA_BASE : stm32l1xx.h
  • GPIOB : stm32l1xx.h
  • GPIOB_BASE : stm32l1xx.h
  • GPIOC : stm32l1xx.h
  • GPIOC_BASE : stm32l1xx.h
  • GPIOD : stm32l1xx.h
  • GPIOD_BASE : stm32l1xx.h
  • GPIOE : stm32l1xx.h
  • GPIOE_BASE : stm32l1xx.h
  • GPIOF : stm32l1xx.h
  • GPIOF_BASE : stm32l1xx.h
  • GPIOG : stm32l1xx.h
  • GPIOG_BASE : stm32l1xx.h
  • GPIOH : stm32l1xx.h
  • GPIOH_BASE : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- h -

  • HD_BitNumber : stm32l1xx_lcd.c
  • HSE_STARTUP_TIMEOUT : stm32l1xx.h
  • HSE_VALUE : stm32l1xx.h
  • HSI_STARTUP_TIMEOUT : stm32l1xx.h
  • HSI_VALUE : stm32l1xx.h
  • HSION_BitNumber : stm32l1xx_rcc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- i -

  • I2C1 : stm32l1xx.h
  • I2C1_BASE : stm32l1xx.h
  • I2C2 : stm32l1xx.h
  • I2C2_BASE : stm32l1xx.h
  • I2C_Ack_Disable : stm32l1xx_i2c.h
  • I2C_Ack_Enable : stm32l1xx_i2c.h
  • I2C_AcknowledgedAddress_10bit : stm32l1xx_i2c.h
  • I2C_AcknowledgedAddress_7bit : stm32l1xx_i2c.h
  • I2C_CCR_CCR : stm32l1xx.h
  • I2C_CCR_DUTY : stm32l1xx.h
  • I2C_CCR_FS : stm32l1xx.h
  • I2C_CR1_ACK : stm32l1xx.h
  • I2C_CR1_ALERT : stm32l1xx.h
  • I2C_CR1_ENARP : stm32l1xx.h
  • I2C_CR1_ENGC : stm32l1xx.h
  • I2C_CR1_ENPEC : stm32l1xx.h
  • I2C_CR1_NOSTRETCH : stm32l1xx.h
  • I2C_CR1_PE : stm32l1xx.h
  • I2C_CR1_PEC : stm32l1xx.h
  • I2C_CR1_POS : stm32l1xx.h
  • I2C_CR1_SMBTYPE : stm32l1xx.h
  • I2C_CR1_SMBUS : stm32l1xx.h
  • I2C_CR1_START : stm32l1xx.h
  • I2C_CR1_STOP : stm32l1xx.h
  • I2C_CR1_SWRST : stm32l1xx.h
  • I2C_CR2_DMAEN : stm32l1xx.h
  • I2C_CR2_FREQ : stm32l1xx.h
  • I2C_CR2_FREQ_0 : stm32l1xx.h
  • I2C_CR2_FREQ_1 : stm32l1xx.h
  • I2C_CR2_FREQ_2 : stm32l1xx.h
  • I2C_CR2_FREQ_3 : stm32l1xx.h
  • I2C_CR2_FREQ_4 : stm32l1xx.h
  • I2C_CR2_FREQ_5 : stm32l1xx.h
  • I2C_CR2_ITBUFEN : stm32l1xx.h
  • I2C_CR2_ITERREN : stm32l1xx.h
  • I2C_CR2_ITEVTEN : stm32l1xx.h
  • I2C_CR2_LAST : stm32l1xx.h
  • I2C_Direction_Receiver : stm32l1xx_i2c.h
  • I2C_Direction_Transmitter : stm32l1xx_i2c.h
  • I2C_DR_DR : stm32l1xx.h
  • I2C_DutyCycle_16_9 : stm32l1xx_i2c.h
  • I2C_DutyCycle_2 : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm32l1xx_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : stm32l1xx_i2c.h
  • I2C_FLAG_ADD10 : stm32l1xx_i2c.h
  • I2C_FLAG_ADDR : stm32l1xx_i2c.h
  • I2C_FLAG_AF : stm32l1xx_i2c.h
  • I2C_FLAG_ARLO : stm32l1xx_i2c.h
  • I2C_FLAG_BERR : stm32l1xx_i2c.h
  • I2C_FLAG_BTF : stm32l1xx_i2c.h
  • I2C_FLAG_BUSY : stm32l1xx_i2c.h
  • I2C_FLAG_DUALF : stm32l1xx_i2c.h
  • I2C_FLAG_GENCALL : stm32l1xx_i2c.h
  • I2C_FLAG_MSL : stm32l1xx_i2c.h
  • I2C_FLAG_OVR : stm32l1xx_i2c.h
  • I2C_FLAG_PECERR : stm32l1xx_i2c.h
  • I2C_FLAG_RXNE : stm32l1xx_i2c.h
  • I2C_FLAG_SB : stm32l1xx_i2c.h
  • I2C_FLAG_SMBALERT : stm32l1xx_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32l1xx_i2c.h
  • I2C_FLAG_SMBHOST : stm32l1xx_i2c.h
  • I2C_FLAG_STOPF : stm32l1xx_i2c.h
  • I2C_FLAG_TIMEOUT : stm32l1xx_i2c.h
  • I2C_FLAG_TRA : stm32l1xx_i2c.h
  • I2C_FLAG_TXE : stm32l1xx_i2c.h
  • I2C_IT_ADD10 : stm32l1xx_i2c.h
  • I2C_IT_ADDR : stm32l1xx_i2c.h
  • I2C_IT_AF : stm32l1xx_i2c.h
  • I2C_IT_ARLO : stm32l1xx_i2c.h
  • I2C_IT_BERR : stm32l1xx_i2c.h
  • I2C_IT_BTF : stm32l1xx_i2c.h
  • I2C_IT_BUF : stm32l1xx_i2c.h
  • I2C_IT_ERR : stm32l1xx_i2c.h
  • I2C_IT_EVT : stm32l1xx_i2c.h
  • I2C_IT_OVR : stm32l1xx_i2c.h
  • I2C_IT_PECERR : stm32l1xx_i2c.h
  • I2C_IT_RXNE : stm32l1xx_i2c.h
  • I2C_IT_SB : stm32l1xx_i2c.h
  • I2C_IT_SMBALERT : stm32l1xx_i2c.h
  • I2C_IT_STOPF : stm32l1xx_i2c.h
  • I2C_IT_TIMEOUT : stm32l1xx_i2c.h
  • I2C_IT_TXE : stm32l1xx_i2c.h
  • I2C_Mode_I2C : stm32l1xx_i2c.h
  • I2C_Mode_SMBusDevice : stm32l1xx_i2c.h
  • I2C_Mode_SMBusHost : stm32l1xx_i2c.h
  • I2C_NACKPosition_Current : stm32l1xx_i2c.h
  • I2C_NACKPosition_Next : stm32l1xx_i2c.h
  • I2C_OAR1_ADD0 : stm32l1xx.h
  • I2C_OAR1_ADD1 : stm32l1xx.h
  • I2C_OAR1_ADD1_7 : stm32l1xx.h
  • I2C_OAR1_ADD2 : stm32l1xx.h
  • I2C_OAR1_ADD3 : stm32l1xx.h
  • I2C_OAR1_ADD4 : stm32l1xx.h
  • I2C_OAR1_ADD5 : stm32l1xx.h
  • I2C_OAR1_ADD6 : stm32l1xx.h
  • I2C_OAR1_ADD7 : stm32l1xx.h
  • I2C_OAR1_ADD8 : stm32l1xx.h
  • I2C_OAR1_ADD8_9 : stm32l1xx.h
  • I2C_OAR1_ADD9 : stm32l1xx.h
  • I2C_OAR1_ADDMODE : stm32l1xx.h
  • I2C_OAR2_ADD2 : stm32l1xx.h
  • I2C_OAR2_ENDUAL : stm32l1xx.h
  • I2C_PECPosition_Current : stm32l1xx_i2c.h
  • I2C_PECPosition_Next : stm32l1xx_i2c.h
  • I2C_Register_CCR : stm32l1xx_i2c.h
  • I2C_Register_CR1 : stm32l1xx_i2c.h
  • I2C_Register_CR2 : stm32l1xx_i2c.h
  • I2C_Register_DR : stm32l1xx_i2c.h
  • I2C_Register_OAR1 : stm32l1xx_i2c.h
  • I2C_Register_OAR2 : stm32l1xx_i2c.h
  • I2C_Register_SR1 : stm32l1xx_i2c.h
  • I2C_Register_SR2 : stm32l1xx_i2c.h
  • I2C_Register_TRISE : stm32l1xx_i2c.h
  • I2C_SMBusAlert_High : stm32l1xx_i2c.h
  • I2C_SMBusAlert_Low : stm32l1xx_i2c.h
  • I2C_SR1_ADD10 : stm32l1xx.h
  • I2C_SR1_ADDR : stm32l1xx.h
  • I2C_SR1_AF : stm32l1xx.h
  • I2C_SR1_ARLO : stm32l1xx.h
  • I2C_SR1_BERR : stm32l1xx.h
  • I2C_SR1_BTF : stm32l1xx.h
  • I2C_SR1_OVR : stm32l1xx.h
  • I2C_SR1_PECERR : stm32l1xx.h
  • I2C_SR1_RXNE : stm32l1xx.h
  • I2C_SR1_SB : stm32l1xx.h
  • I2C_SR1_SMBALERT : stm32l1xx.h
  • I2C_SR1_STOPF : stm32l1xx.h
  • I2C_SR1_TIMEOUT : stm32l1xx.h
  • I2C_SR1_TXE : stm32l1xx.h
  • I2C_SR2_BUSY : stm32l1xx.h
  • I2C_SR2_DUALF : stm32l1xx.h
  • I2C_SR2_GENCALL : stm32l1xx.h
  • I2C_SR2_MSL : stm32l1xx.h
  • I2C_SR2_PEC : stm32l1xx.h
  • I2C_SR2_SMBDEFAULT : stm32l1xx.h
  • I2C_SR2_SMBHOST : stm32l1xx.h
  • I2C_SR2_TRA : stm32l1xx.h
  • I2C_TRISE_TRISE : stm32l1xx.h
  • I2S_AudioFreq_11k : stm32l1xx_spi.h
  • I2S_AudioFreq_16k : stm32l1xx_spi.h
  • I2S_AudioFreq_192k : stm32l1xx_spi.h
  • I2S_AudioFreq_22k : stm32l1xx_spi.h
  • I2S_AudioFreq_32k : stm32l1xx_spi.h
  • I2S_AudioFreq_44k : stm32l1xx_spi.h
  • I2S_AudioFreq_48k : stm32l1xx_spi.h
  • I2S_AudioFreq_8k : stm32l1xx_spi.h
  • I2S_AudioFreq_96k : stm32l1xx_spi.h
  • I2S_AudioFreq_Default : stm32l1xx_spi.h
  • I2S_CPOL_High : stm32l1xx_spi.h
  • I2S_CPOL_Low : stm32l1xx_spi.h
  • I2S_DataFormat_16b : stm32l1xx_spi.h
  • I2S_DataFormat_16bextended : stm32l1xx_spi.h
  • I2S_DataFormat_24b : stm32l1xx_spi.h
  • I2S_DataFormat_32b : stm32l1xx_spi.h
  • I2S_FLAG_CHSIDE : stm32l1xx_spi.h
  • I2S_FLAG_UDR : stm32l1xx_spi.h
  • I2S_IT_UDR : stm32l1xx_spi.h
  • I2S_MCLKOutput_Disable : stm32l1xx_spi.h
  • I2S_MCLKOutput_Enable : stm32l1xx_spi.h
  • I2S_Mode_MasterRx : stm32l1xx_spi.h
  • I2S_Mode_MasterTx : stm32l1xx_spi.h
  • I2S_Mode_SlaveRx : stm32l1xx_spi.h
  • I2S_Mode_SlaveTx : stm32l1xx_spi.h
  • I2S_Standard_LSB : stm32l1xx_spi.h
  • I2S_Standard_MSB : stm32l1xx_spi.h
  • I2S_Standard_PCMLong : stm32l1xx_spi.h
  • I2S_Standard_PCMShort : stm32l1xx_spi.h
  • I2S_Standard_Phillips : stm32l1xx_spi.h
  • I2SCFGR_CLEAR_Mask : stm32l1xx_spi.c
  • IC_ROUTING_MASK : stm32l1xx_syscfg.c
  • ICSCR_BYTE4_ADDRESS : stm32l1xx_rcc.c
  • IDCODE_DEVID_MASK : stm32l1xx_dbgmcu.c
  • INITMODE_TIMEOUT : stm32l1xx_rtc.c
  • IS_ADC_ALL_PERIPH : stm32l1xx_adc.h
  • IS_ADC_ANALOG_WATCHDOG : stm32l1xx_adc.h
  • IS_ADC_BANK : stm32l1xx_adc.h
  • IS_ADC_CHANNEL : stm32l1xx_adc.h
  • IS_ADC_CLEAR_FLAG : stm32l1xx_adc.h
  • IS_ADC_DATA_ALIGN : stm32l1xx_adc.h
  • IS_ADC_DELAY_LENGTH : stm32l1xx_adc.h
  • IS_ADC_DMA_PERIPH : stm32l1xx_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32l1xx_adc.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32l1xx_adc.h
  • IS_ADC_EXT_TRIG : stm32l1xx_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32l1xx_adc.h
  • IS_ADC_GET_FLAG : stm32l1xx_adc.h
  • IS_ADC_INJECTED_CHANNEL : stm32l1xx_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32l1xx_adc.h
  • IS_ADC_INJECTED_RANK : stm32l1xx_adc.h
  • IS_ADC_IT : stm32l1xx_adc.h
  • IS_ADC_OFFSET : stm32l1xx_adc.h
  • IS_ADC_POWER_DOWN : stm32l1xx_adc.h
  • IS_ADC_PRESCALER : stm32l1xx_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32l1xx_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32l1xx_adc.h
  • IS_ADC_REGULAR_RANK : stm32l1xx_adc.h
  • IS_ADC_RESOLUTION : stm32l1xx_adc.h
  • IS_ADC_SAMPLE_TIME : stm32l1xx_adc.h
  • IS_ADC_THRESHOLD : stm32l1xx_adc.h
  • IS_AES_CHAINING : stm32l1xx_aes.h
  • IS_AES_DATATYPE : stm32l1xx_aes.h
  • IS_AES_DMA_TRANSFER : stm32l1xx_aes.h
  • IS_AES_FLAG : stm32l1xx_aes.h
  • IS_AES_GET_IT : stm32l1xx_aes.h
  • IS_AES_IT : stm32l1xx_aes.h
  • IS_AES_MODE : stm32l1xx_aes.h
  • IS_ALARM_MASK : stm32l1xx_rtc.h
  • IS_COMP_ALL_PERIPH : stm32l1xx_comp.h
  • IS_COMP_INVERTING_INPUT : stm32l1xx_comp.h
  • IS_COMP_OUTPUT : stm32l1xx_comp.h
  • IS_COMP_SPEED : stm32l1xx_comp.h
  • IS_DAC_ALIGN : stm32l1xx_dac.h
  • IS_DAC_CHANNEL : stm32l1xx_dac.h
  • IS_DAC_DATA : stm32l1xx_dac.h
  • IS_DAC_FLAG : stm32l1xx_dac.h
  • IS_DAC_GENERATE_WAVE : stm32l1xx_dac.h
  • IS_DAC_IT : stm32l1xx_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32l1xx_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32l1xx_dac.h
  • IS_DAC_TRIGGER : stm32l1xx_dac.h
  • IS_DAC_WAVE : stm32l1xx_dac.h
  • IS_DBGMCU_APB1PERIPH : stm32l1xx_dbgmcu.h
  • IS_DBGMCU_APB2PERIPH : stm32l1xx_dbgmcu.h
  • IS_DBGMCU_PERIPH : stm32l1xx_dbgmcu.h
  • IS_DMA_ALL_PERIPH : stm32l1xx_dma.h
  • IS_DMA_BUFFER_SIZE : stm32l1xx_dma.h
  • IS_DMA_CLEAR_FLAG : stm32l1xx_dma.h
  • IS_DMA_CLEAR_IT : stm32l1xx_dma.h
  • IS_DMA_CONFIG_IT : stm32l1xx_dma.h
  • IS_DMA_DIR : stm32l1xx_dma.h
  • IS_DMA_GET_FLAG : stm32l1xx_dma.h
  • IS_DMA_GET_IT : stm32l1xx_dma.h
  • IS_DMA_M2M_STATE : stm32l1xx_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32l1xx_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32l1xx_dma.h
  • IS_DMA_MODE : stm32l1xx_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32l1xx_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32l1xx_dma.h
  • IS_DMA_PRIORITY : stm32l1xx_dma.h
  • IS_EXTI_LINE : stm32l1xx_exti.h
  • IS_EXTI_MODE : stm32l1xx_exti.h
  • IS_EXTI_PIN_SOURCE : stm32l1xx_syscfg.h
  • IS_EXTI_PORT_SOURCE : stm32l1xx_syscfg.h
  • IS_EXTI_TRIGGER : stm32l1xx_exti.h
  • IS_FLASH_CLEAR_FLAG : stm32l1xx_flash.h
  • IS_FLASH_DATA_ADDRESS : stm32l1xx_flash.h
  • IS_FLASH_GET_FLAG : stm32l1xx_flash.h
  • IS_FLASH_IT : stm32l1xx_flash.h
  • IS_FLASH_LATENCY : stm32l1xx_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32l1xx_flash.h
  • IS_FSMC_ACCESS_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_ADDRESS_HOLD_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_ADDRESS_SETUP_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_ASYNWAIT : stm32l1xx_fsmc.h
  • IS_FSMC_BURSTMODE : stm32l1xx_fsmc.h
  • IS_FSMC_CLK_DIV : stm32l1xx_fsmc.h
  • IS_FSMC_DATA_LATENCY : stm32l1xx_fsmc.h
  • IS_FSMC_DATASETUP_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_EXTENDED_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_MEMORY : stm32l1xx_fsmc.h
  • IS_FSMC_MEMORY_WIDTH : stm32l1xx_fsmc.h
  • IS_FSMC_MUX : stm32l1xx_fsmc.h
  • IS_FSMC_NORSRAM_BANK : stm32l1xx_fsmc.h
  • IS_FSMC_TURNAROUND_TIME : stm32l1xx_fsmc.h
  • IS_FSMC_WAIT_POLARITY : stm32l1xx_fsmc.h
  • IS_FSMC_WAIT_SIGNAL_ACTIVE : stm32l1xx_fsmc.h
  • IS_FSMC_WAITE_SIGNAL : stm32l1xx_fsmc.h
  • IS_FSMC_WRAP_MODE : stm32l1xx_fsmc.h
  • IS_FSMC_WRITE_BURST : stm32l1xx_fsmc.h
  • IS_FSMC_WRITE_OPERATION : stm32l1xx_fsmc.h
  • IS_FUNCTIONAL_STATE : stm32l1xx.h
  • IS_GET_EXTI_LINE : stm32l1xx_exti.h
  • IS_GET_GPIO_PIN : stm32l1xx_gpio.h
  • IS_GPIO_AF : stm32l1xx_gpio.h
  • IS_GPIO_ALL_PERIPH : stm32l1xx_gpio.h
  • IS_GPIO_BIT_ACTION : stm32l1xx_gpio.h
  • IS_GPIO_MODE : stm32l1xx_gpio.h
  • IS_GPIO_OTYPE : stm32l1xx_gpio.h
  • IS_GPIO_PIN : stm32l1xx_gpio.h
  • IS_GPIO_PIN_SOURCE : stm32l1xx_gpio.h
  • IS_GPIO_PUPD : stm32l1xx_gpio.h
  • IS_GPIO_SPEED : stm32l1xx_gpio.h
  • IS_I2C_ACK_STATE : stm32l1xx_i2c.h
  • IS_I2C_ACKNOWLEDGE_ADDRESS : stm32l1xx_i2c.h
  • IS_I2C_ALL_PERIPH : stm32l1xx_i2c.h
  • IS_I2C_CLEAR_FLAG : stm32l1xx_i2c.h
  • IS_I2C_CLEAR_IT : stm32l1xx_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32l1xx_i2c.h
  • IS_I2C_CONFIG_IT : stm32l1xx_i2c.h
  • IS_I2C_DIRECTION : stm32l1xx_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32l1xx_i2c.h
  • IS_I2C_EVENT : stm32l1xx_i2c.h
  • IS_I2C_GET_FLAG : stm32l1xx_i2c.h
  • IS_I2C_GET_IT : stm32l1xx_i2c.h
  • IS_I2C_MODE : stm32l1xx_i2c.h
  • IS_I2C_NACK_POSITION : stm32l1xx_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32l1xx_i2c.h
  • IS_I2C_PEC_POSITION : stm32l1xx_i2c.h
  • IS_I2C_REGISTER : stm32l1xx_i2c.h
  • IS_I2C_SMBUS_ALERT : stm32l1xx_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32l1xx_spi.h
  • IS_I2S_CPOL : stm32l1xx_spi.h
  • IS_I2S_DATA_FORMAT : stm32l1xx_spi.h
  • IS_I2S_MCLK_OUTPUT : stm32l1xx_spi.h
  • IS_I2S_MODE : stm32l1xx_spi.h
  • IS_I2S_STANDARD : stm32l1xx_spi.h
  • IS_IWDG_FLAG : stm32l1xx_iwdg.h
  • IS_IWDG_PRESCALER : stm32l1xx_iwdg.h
  • IS_IWDG_RELOAD : stm32l1xx_iwdg.h
  • IS_IWDG_WRITE_ACCESS : stm32l1xx_iwdg.h
  • IS_LCD_BIAS : stm32l1xx_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32l1xx_lcd.h
  • IS_LCD_BLINK_MODE : stm32l1xx_lcd.h
  • IS_LCD_CLEAR_FLAG : stm32l1xx_lcd.h
  • IS_LCD_CONTRAST : stm32l1xx_lcd.h
  • IS_LCD_DEAD_TIME : stm32l1xx_lcd.h
  • IS_LCD_DIVIDER : stm32l1xx_lcd.h
  • IS_LCD_DUTY : stm32l1xx_lcd.h
  • IS_LCD_GET_FLAG : stm32l1xx_lcd.h
  • IS_LCD_GET_IT : stm32l1xx_lcd.h
  • IS_LCD_IT : stm32l1xx_lcd.h
  • IS_LCD_PRESCALER : stm32l1xx_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32l1xx_lcd.h
  • IS_LCD_RAM_REGISTER : stm32l1xx_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32l1xx_lcd.h
  • IS_NVIC_LP : misc.h
  • IS_NVIC_OFFSET : misc.h
  • IS_NVIC_PREEMPTION_PRIORITY : misc.h
  • IS_NVIC_PRIORITY_GROUP : misc.h
  • IS_NVIC_SUB_PRIORITY : misc.h
  • IS_NVIC_VECTTAB : misc.h
  • IS_OB_BOOT_BANK : stm32l1xx_flash.h
  • IS_OB_BOR_LEVEL : stm32l1xx_flash.h
  • IS_OB_IWDG_SOURCE : stm32l1xx_flash.h
  • IS_OB_RDP : stm32l1xx_flash.h
  • IS_OB_STDBY_SOURCE : stm32l1xx_flash.h
  • IS_OB_STOP_SOURCE : stm32l1xx_flash.h
  • IS_OB_WRP : stm32l1xx_flash.h
  • IS_OPAMP_ALL_PERIPH : stm32l1xx_opamp.h
  • IS_OPAMP_INPUT : stm32l1xx_opamp.h
  • IS_OPAMP_RANGE : stm32l1xx_opamp.h
  • IS_OPAMP_SWITCH : stm32l1xx_opamp.h
  • IS_OPAMP_TRIMMING : stm32l1xx_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32l1xx_opamp.h
  • IS_PWR_CLEAR_FLAG : stm32l1xx_pwr.h
  • IS_PWR_GET_FLAG : stm32l1xx_pwr.h
  • IS_PWR_PVD_LEVEL : stm32l1xx_pwr.h
  • IS_PWR_REGULATOR : stm32l1xx_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32l1xx_pwr.h
  • IS_PWR_STOP_ENTRY : stm32l1xx_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32l1xx_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32l1xx_pwr.h
  • IS_RCC_AHB_LPMODE_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_AHB_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_APB1_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_APB2_PERIPH : stm32l1xx_rcc.h
  • IS_RCC_CLEAR_IT : stm32l1xx_rcc.h
  • IS_RCC_FLAG : stm32l1xx_rcc.h
  • IS_RCC_GET_IT : stm32l1xx_rcc.h
  • IS_RCC_HCLK : stm32l1xx_rcc.h
  • IS_RCC_HSE : stm32l1xx_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32l1xx_rcc.h
  • IS_RCC_IT : stm32l1xx_rcc.h
  • IS_RCC_LSE : stm32l1xx_rcc.h
  • IS_RCC_MCO_DIV : stm32l1xx_rcc.h
  • IS_RCC_MCO_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_MSI_CALIBRATION_VALUE : stm32l1xx_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32l1xx_rcc.h
  • IS_RCC_PCLK : stm32l1xx_rcc.h
  • IS_RCC_PLL_DIV : stm32l1xx_rcc.h
  • IS_RCC_PLL_MUL : stm32l1xx_rcc.h
  • IS_RCC_PLL_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_RTCCLK_SOURCE : stm32l1xx_rcc.h
  • IS_RCC_SYSCLK_SOURCE : stm32l1xx_rcc.h
  • IS_RI_CHANNEL : stm32l1xx_syscfg.h
  • IS_RI_CHANNELSPEED : stm32l1xx_syscfg.h
  • IS_RI_INPUTCAPTURE : stm32l1xx_syscfg.h
  • IS_RI_INPUTCAPTURE_ROUTING : stm32l1xx_syscfg.h
  • IS_RI_IOSWITCH : stm32l1xx_syscfg.h
  • IS_RI_PIN : stm32l1xx_syscfg.h
  • IS_RI_PORT : stm32l1xx_syscfg.h
  • IS_RI_RESISTOR : stm32l1xx_syscfg.h
  • IS_RI_TIM : stm32l1xx_syscfg.h
  • IS_RTC_ALARM : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32l1xx_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32l1xx_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32l1xx_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32l1xx_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32l1xx_rtc.h
  • IS_RTC_BKP : stm32l1xx_rtc.h
  • IS_RTC_CALIB_OUTPUT : stm32l1xx_rtc.h
  • IS_RTC_CALIB_SIGN : stm32l1xx_rtc.h
  • IS_RTC_CALIB_VALUE : stm32l1xx_rtc.h
  • IS_RTC_CLEAR_FLAG : stm32l1xx_rtc.h
  • IS_RTC_CLEAR_IT : stm32l1xx_rtc.h
  • IS_RTC_CMD_ALARM : stm32l1xx_rtc.h
  • IS_RTC_CONFIG_IT : stm32l1xx_rtc.h
  • IS_RTC_DATE : stm32l1xx_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32l1xx_rtc.h
  • IS_RTC_FORMAT : stm32l1xx_rtc.h
  • IS_RTC_GET_FLAG : stm32l1xx_rtc.h
  • IS_RTC_GET_IT : stm32l1xx_rtc.h
  • IS_RTC_H12 : stm32l1xx_rtc.h
  • IS_RTC_HOUR12 : stm32l1xx_rtc.h
  • IS_RTC_HOUR24 : stm32l1xx_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32l1xx_rtc.h
  • IS_RTC_MINUTES : stm32l1xx_rtc.h
  • IS_RTC_MONTH : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT_POL : stm32l1xx_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32l1xx_rtc.h
  • IS_RTC_SECONDS : stm32l1xx_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32l1xx_rtc.h
  • IS_RTC_SHIFT_SUBFS : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32l1xx_rtc.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32l1xx_rtc.h
  • IS_RTC_STORE_OPERATION : stm32l1xx_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32l1xx_rtc.h
  • IS_RTC_TAMPER : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_FILTER : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32l1xx_rtc.h
  • IS_RTC_TAMPER_TRIGGER : stm32l1xx_rtc.h
  • IS_RTC_TIMESTAMP_EDGE : stm32l1xx_rtc.h
  • IS_RTC_WAKEUP_CLOCK : stm32l1xx_rtc.h
  • IS_RTC_WAKEUP_COUNTER : stm32l1xx_rtc.h
  • IS_RTC_WEEKDAY : stm32l1xx_rtc.h
  • IS_RTC_YEAR : stm32l1xx_rtc.h
  • IS_SDIO_BLOCK_SIZE : stm32l1xx_sdio.h
  • IS_SDIO_BUS_WIDE : stm32l1xx_sdio.h
  • IS_SDIO_CLEAR_FLAG : stm32l1xx_sdio.h
  • IS_SDIO_CLEAR_IT : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_BYPASS : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_EDGE : stm32l1xx_sdio.h
  • IS_SDIO_CLOCK_POWER_SAVE : stm32l1xx_sdio.h
  • IS_SDIO_CMD_INDEX : stm32l1xx_sdio.h
  • IS_SDIO_CPSM : stm32l1xx_sdio.h
  • IS_SDIO_DATA_LENGTH : stm32l1xx_sdio.h
  • IS_SDIO_DPSM : stm32l1xx_sdio.h
  • IS_SDIO_FLAG : stm32l1xx_sdio.h
  • IS_SDIO_GET_IT : stm32l1xx_sdio.h
  • IS_SDIO_HARDWARE_FLOW_CONTROL : stm32l1xx_sdio.h
  • IS_SDIO_IT : stm32l1xx_sdio.h
  • IS_SDIO_POWER_STATE : stm32l1xx_sdio.h
  • IS_SDIO_READWAIT_MODE : stm32l1xx_sdio.h
  • IS_SDIO_RESP : stm32l1xx_sdio.h
  • IS_SDIO_RESPONSE : stm32l1xx_sdio.h
  • IS_SDIO_TRANSFER_DIR : stm32l1xx_sdio.h
  • IS_SDIO_TRANSFER_MODE : stm32l1xx_sdio.h
  • IS_SDIO_WAIT : stm32l1xx_sdio.h
  • IS_SPI_23_PERIPH : stm32l1xx_spi.h
  • IS_SPI_ALL_PERIPH : stm32l1xx_spi.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32l1xx_spi.h
  • IS_SPI_CPHA : stm32l1xx_spi.h
  • IS_SPI_CPOL : stm32l1xx_spi.h
  • IS_SPI_CRC : stm32l1xx_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32l1xx_spi.h
  • IS_SPI_DATASIZE : stm32l1xx_spi.h
  • IS_SPI_DIRECTION : stm32l1xx_spi.h
  • IS_SPI_DIRECTION_MODE : stm32l1xx_spi.h
  • IS_SPI_FIRST_BIT : stm32l1xx_spi.h
  • IS_SPI_I2S_CLEAR_FLAG : stm32l1xx_spi.h
  • IS_SPI_I2S_CLEAR_IT : stm32l1xx_spi.h
  • IS_SPI_I2S_CONFIG_IT : stm32l1xx_spi.h
  • IS_SPI_I2S_DMAREQ : stm32l1xx_spi.h
  • IS_SPI_I2S_GET_FLAG : stm32l1xx_spi.h
  • IS_SPI_I2S_GET_IT : stm32l1xx_spi.h
  • IS_SPI_MODE : stm32l1xx_spi.h
  • IS_SPI_NSS : stm32l1xx_spi.h
  • IS_SPI_NSS_INTERNAL : stm32l1xx_spi.h
  • IS_SYSCFG_MEMORY_REMAP_CONFING : stm32l1xx_syscfg.h
  • IS_SYSTICK_CLK_SOURCE : misc.h
  • IS_TIM_ALL_PERIPH : stm32l1xx_tim.h
  • IS_TIM_CCX : stm32l1xx_tim.h
  • IS_TIM_CHANNEL : stm32l1xx_tim.h
  • IS_TIM_CKD_DIV : stm32l1xx_tim.h
  • IS_TIM_CLEAR_FLAG : stm32l1xx_tim.h
  • IS_TIM_COUNTER_MODE : stm32l1xx_tim.h
  • IS_TIM_DMA_BASE : stm32l1xx_tim.h
  • IS_TIM_DMA_LENGTH : stm32l1xx_tim.h
  • IS_TIM_DMA_SOURCE : stm32l1xx_tim.h
  • IS_TIM_ENCODER_MODE : stm32l1xx_tim.h
  • IS_TIM_EVENT_SOURCE : stm32l1xx_tim.h
  • IS_TIM_EXT_FILTER : stm32l1xx_tim.h
  • IS_TIM_EXT_POLARITY : stm32l1xx_tim.h
  • IS_TIM_EXT_PRESCALER : stm32l1xx_tim.h
  • IS_TIM_FORCED_ACTION : stm32l1xx_tim.h
  • IS_TIM_GET_FLAG : stm32l1xx_tim.h
  • IS_TIM_GET_IT : stm32l1xx_tim.h
  • IS_TIM_IC_FILTER : stm32l1xx_tim.h
  • IS_TIM_IC_POLARITY : stm32l1xx_tim.h
  • IS_TIM_IC_PRESCALER : stm32l1xx_tim.h
  • IS_TIM_IC_SELECTION : stm32l1xx_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32l1xx_tim.h
  • IS_TIM_IT : stm32l1xx_tim.h
  • IS_TIM_LIST1_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST2_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST3_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST4_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST5_PERIPH : stm32l1xx_tim.h
  • IS_TIM_LIST6_PERIPH : stm32l1xx_tim.h
  • IS_TIM_MSM_STATE : stm32l1xx_tim.h
  • IS_TIM_OC_MODE : stm32l1xx_tim.h
  • IS_TIM_OC_POLARITY : stm32l1xx_tim.h
  • IS_TIM_OCCLEAR_STATE : stm32l1xx_tim.h
  • IS_TIM_OCFAST_STATE : stm32l1xx_tim.h
  • IS_TIM_OCM : stm32l1xx_tim.h
  • IS_TIM_OCPRELOAD_STATE : stm32l1xx_tim.h
  • IS_TIM_OPM_MODE : stm32l1xx_tim.h
  • IS_TIM_OUTPUT_STATE : stm32l1xx_tim.h
  • IS_TIM_PRESCALER_RELOAD : stm32l1xx_tim.h
  • IS_TIM_PWMI_CHANNEL : stm32l1xx_tim.h
  • IS_TIM_REMAP : stm32l1xx_tim.h
  • IS_TIM_SLAVE_MODE : stm32l1xx_tim.h
  • IS_TIM_TRGO_SOURCE : stm32l1xx_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32l1xx_tim.h
  • IS_TIM_UPDATE_SOURCE : stm32l1xx_tim.h
  • IS_USART_123_PERIPH : stm32l1xx_usart.h
  • IS_USART_ADDRESS : stm32l1xx_usart.h
  • IS_USART_ALL_PERIPH : stm32l1xx_usart.h
  • IS_USART_BAUDRATE : stm32l1xx_usart.h
  • IS_USART_CLEAR_FLAG : stm32l1xx_usart.h
  • IS_USART_CLEAR_IT : stm32l1xx_usart.h
  • IS_USART_CLOCK : stm32l1xx_usart.h
  • IS_USART_CONFIG_IT : stm32l1xx_usart.h
  • IS_USART_CPHA : stm32l1xx_usart.h
  • IS_USART_CPOL : stm32l1xx_usart.h
  • IS_USART_DATA : stm32l1xx_usart.h
  • IS_USART_DMAREQ : stm32l1xx_usart.h
  • IS_USART_FLAG : stm32l1xx_usart.h
  • IS_USART_GET_IT : stm32l1xx_usart.h
  • IS_USART_HARDWARE_FLOW_CONTROL : stm32l1xx_usart.h
  • IS_USART_IRDA_MODE : stm32l1xx_usart.h
  • IS_USART_LASTBIT : stm32l1xx_usart.h
  • IS_USART_LIN_BREAK_DETECT_LENGTH : stm32l1xx_usart.h
  • IS_USART_MODE : stm32l1xx_usart.h
  • IS_USART_PARITY : stm32l1xx_usart.h
  • IS_USART_STOPBITS : stm32l1xx_usart.h
  • IS_USART_WAKEUP : stm32l1xx_usart.h
  • IS_USART_WORD_LENGTH : stm32l1xx_usart.h
  • IS_WWDG_COUNTER : stm32l1xx_wwdg.h
  • IS_WWDG_PRESCALER : stm32l1xx_wwdg.h
  • IS_WWDG_WINDOW_VALUE : stm32l1xx_wwdg.h
  • IT_MASK : stm32l1xx_usart.c
  • ITEN_MASK : stm32l1xx_i2c.c
  • IWDG : stm32l1xx.h
  • IWDG_BASE : stm32l1xx.h
  • IWDG_FLAG_PVU : stm32l1xx_iwdg.h
  • IWDG_FLAG_RVU : stm32l1xx_iwdg.h
  • IWDG_KR_KEY : stm32l1xx.h
  • IWDG_PR_PR : stm32l1xx.h
  • IWDG_PR_PR_0 : stm32l1xx.h
  • IWDG_PR_PR_1 : stm32l1xx.h
  • IWDG_PR_PR_2 : stm32l1xx.h
  • IWDG_Prescaler_128 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_16 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_256 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_32 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_4 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_64 : stm32l1xx_iwdg.h
  • IWDG_Prescaler_8 : stm32l1xx_iwdg.h
  • IWDG_RLR_RL : stm32l1xx.h
  • IWDG_SR_PVU : stm32l1xx.h
  • IWDG_SR_RVU : stm32l1xx.h
  • IWDG_WriteAccess_Disable : stm32l1xx_iwdg.h
  • IWDG_WriteAccess_Enable : stm32l1xx_iwdg.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- p -

  • PERIPH_BASE : stm32l1xx.h
  • PERIPH_BB_BASE : stm32l1xx.h
  • PLLON_BitNumber : stm32l1xx_rcc.c
  • PON_MASK : stm32l1xx_lcd.c
  • PVDE_BitNumber : stm32l1xx_pwr.c
  • PWR : stm32l1xx.h
  • PWR_BASE : stm32l1xx.h
  • PWR_CR_CSBF : stm32l1xx.h
  • PWR_CR_CWUF : stm32l1xx.h
  • PWR_CR_DBP : stm32l1xx.h
  • PWR_CR_FWU : stm32l1xx.h
  • PWR_CR_LPRUN : stm32l1xx.h
  • PWR_CR_LPSDSR : stm32l1xx.h
  • PWR_CR_PDDS : stm32l1xx.h
  • PWR_CR_PLS : stm32l1xx.h
  • PWR_CR_PLS_0 : stm32l1xx.h
  • PWR_CR_PLS_1 : stm32l1xx.h
  • PWR_CR_PLS_2 : stm32l1xx.h
  • PWR_CR_PLS_LEV0 : stm32l1xx.h
  • PWR_CR_PLS_LEV1 : stm32l1xx.h
  • PWR_CR_PLS_LEV2 : stm32l1xx.h
  • PWR_CR_PLS_LEV3 : stm32l1xx.h
  • PWR_CR_PLS_LEV4 : stm32l1xx.h
  • PWR_CR_PLS_LEV5 : stm32l1xx.h
  • PWR_CR_PLS_LEV6 : stm32l1xx.h
  • PWR_CR_PLS_LEV7 : stm32l1xx.h
  • PWR_CR_PVDE : stm32l1xx.h
  • PWR_CR_ULP : stm32l1xx.h
  • PWR_CR_VOS : stm32l1xx.h
  • PWR_CR_VOS_0 : stm32l1xx.h
  • PWR_CR_VOS_1 : stm32l1xx.h
  • PWR_CSR_EWUP1 : stm32l1xx.h
  • PWR_CSR_EWUP2 : stm32l1xx.h
  • PWR_CSR_EWUP3 : stm32l1xx.h
  • PWR_CSR_PVDO : stm32l1xx.h
  • PWR_CSR_REGLPF : stm32l1xx.h
  • PWR_CSR_SBF : stm32l1xx.h
  • PWR_CSR_VOSF : stm32l1xx.h
  • PWR_CSR_VREFINTRDYF : stm32l1xx.h
  • PWR_CSR_WUF : stm32l1xx.h
  • PWR_FLAG_PVDO : stm32l1xx_pwr.h
  • PWR_FLAG_REGLP : stm32l1xx_pwr.h
  • PWR_FLAG_SB : stm32l1xx_pwr.h
  • PWR_FLAG_VOS : stm32l1xx_pwr.h
  • PWR_FLAG_VREFINTRDY : stm32l1xx_pwr.h
  • PWR_FLAG_WU : stm32l1xx_pwr.h
  • PWR_OFFSET : stm32l1xx_pwr.c
  • PWR_PVDLevel_0 : stm32l1xx_pwr.h
  • PWR_PVDLevel_1 : stm32l1xx_pwr.h
  • PWR_PVDLevel_2 : stm32l1xx_pwr.h
  • PWR_PVDLevel_3 : stm32l1xx_pwr.h
  • PWR_PVDLevel_4 : stm32l1xx_pwr.h
  • PWR_PVDLevel_5 : stm32l1xx_pwr.h
  • PWR_PVDLevel_6 : stm32l1xx_pwr.h
  • PWR_PVDLevel_7 : stm32l1xx_pwr.h
  • PWR_PWRCTRL_MASK : stm32l1xx_sdio.c
  • PWR_Regulator_LowPower : stm32l1xx_pwr.h
  • PWR_Regulator_ON : stm32l1xx_pwr.h
  • PWR_SLEEPEntry_WFE : stm32l1xx_pwr.h
  • PWR_SLEEPEntry_WFI : stm32l1xx_pwr.h
  • PWR_STOPEntry_WFE : stm32l1xx_pwr.h
  • PWR_STOPEntry_WFI : stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range1 : stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range2 : stm32l1xx_pwr.h
  • PWR_VoltageScaling_Range3 : stm32l1xx_pwr.h
  • PWR_WakeUpPin_1 : stm32l1xx_pwr.h
  • PWR_WakeUpPin_2 : stm32l1xx_pwr.h
  • PWR_WakeUpPin_3 : stm32l1xx_pwr.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- r -

  • RCC : stm32l1xx.h
  • RCC_AHBENR_AESEN : stm32l1xx.h
  • RCC_AHBENR_CRCEN : stm32l1xx.h
  • RCC_AHBENR_DMA1EN : stm32l1xx.h
  • RCC_AHBENR_DMA2EN : stm32l1xx.h
  • RCC_AHBENR_FLITFEN : stm32l1xx.h
  • RCC_AHBENR_FSMCEN : stm32l1xx.h
  • RCC_AHBENR_GPIOAEN : stm32l1xx.h
  • RCC_AHBENR_GPIOBEN : stm32l1xx.h
  • RCC_AHBENR_GPIOCEN : stm32l1xx.h
  • RCC_AHBENR_GPIODEN : stm32l1xx.h
  • RCC_AHBENR_GPIOEEN : stm32l1xx.h
  • RCC_AHBENR_GPIOFEN : stm32l1xx.h
  • RCC_AHBENR_GPIOGEN : stm32l1xx.h
  • RCC_AHBENR_GPIOHEN : stm32l1xx.h
  • RCC_AHBLPENR_AESLPEN : stm32l1xx.h
  • RCC_AHBLPENR_CRCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_DMA1LPEN : stm32l1xx.h
  • RCC_AHBLPENR_DMA2LPEN : stm32l1xx.h
  • RCC_AHBLPENR_FLITFLPEN : stm32l1xx.h
  • RCC_AHBLPENR_FSMCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOALPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOBLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOCLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIODLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOELPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOFLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOGLPEN : stm32l1xx.h
  • RCC_AHBLPENR_GPIOHLPEN : stm32l1xx.h
  • RCC_AHBLPENR_SRAMLPEN : stm32l1xx.h
  • RCC_AHBPeriph_AES : stm32l1xx_rcc.h
  • RCC_AHBPeriph_CRC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_DMA1 : stm32l1xx_rcc.h
  • RCC_AHBPeriph_DMA2 : stm32l1xx_rcc.h
  • RCC_AHBPeriph_FLITF : stm32l1xx_rcc.h
  • RCC_AHBPeriph_FSMC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOA : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOB : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOC : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOD : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOE : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOF : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOG : stm32l1xx_rcc.h
  • RCC_AHBPeriph_GPIOH : stm32l1xx_rcc.h
  • RCC_AHBPeriph_SRAM : stm32l1xx_rcc.h
  • RCC_AHBRSTR_AESRST : stm32l1xx.h
  • RCC_AHBRSTR_CRCRST : stm32l1xx.h
  • RCC_AHBRSTR_DMA1RST : stm32l1xx.h
  • RCC_AHBRSTR_DMA2RST : stm32l1xx.h
  • RCC_AHBRSTR_FLITFRST : stm32l1xx.h
  • RCC_AHBRSTR_FSMCRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOARST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOBRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOCRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIODRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOERST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOFRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOGRST : stm32l1xx.h
  • RCC_AHBRSTR_GPIOHRST : stm32l1xx.h
  • RCC_APB1ENR_COMPEN : stm32l1xx.h
  • RCC_APB1ENR_DACEN : stm32l1xx.h
  • RCC_APB1ENR_I2C1EN : stm32l1xx.h
  • RCC_APB1ENR_I2C2EN : stm32l1xx.h
  • RCC_APB1ENR_LCDEN : stm32l1xx.h
  • RCC_APB1ENR_PWREN : stm32l1xx.h
  • RCC_APB1ENR_SPI2EN : stm32l1xx.h
  • RCC_APB1ENR_SPI3EN : stm32l1xx.h
  • RCC_APB1ENR_TIM2EN : stm32l1xx.h
  • RCC_APB1ENR_TIM3EN : stm32l1xx.h
  • RCC_APB1ENR_TIM4EN : stm32l1xx.h
  • RCC_APB1ENR_TIM5EN : stm32l1xx.h
  • RCC_APB1ENR_TIM6EN : stm32l1xx.h
  • RCC_APB1ENR_TIM7EN : stm32l1xx.h
  • RCC_APB1ENR_UART4EN : stm32l1xx.h
  • RCC_APB1ENR_UART5EN : stm32l1xx.h
  • RCC_APB1ENR_USART2EN : stm32l1xx.h
  • RCC_APB1ENR_USART3EN : stm32l1xx.h
  • RCC_APB1ENR_USBEN : stm32l1xx.h
  • RCC_APB1ENR_WWDGEN : stm32l1xx.h
  • RCC_APB1LPENR_COMPLPEN : stm32l1xx.h
  • RCC_APB1LPENR_DACLPEN : stm32l1xx.h
  • RCC_APB1LPENR_I2C1LPEN : stm32l1xx.h
  • RCC_APB1LPENR_I2C2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_LCDLPEN : stm32l1xx.h
  • RCC_APB1LPENR_PWRLPEN : stm32l1xx.h
  • RCC_APB1LPENR_SPI2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_SPI3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM4LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM5LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM6LPEN : stm32l1xx.h
  • RCC_APB1LPENR_TIM7LPEN : stm32l1xx.h
  • RCC_APB1LPENR_UART4LPEN : stm32l1xx.h
  • RCC_APB1LPENR_UART5LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USART2LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USART3LPEN : stm32l1xx.h
  • RCC_APB1LPENR_USBLPEN : stm32l1xx.h
  • RCC_APB1LPENR_WWDGLPEN : stm32l1xx.h
  • RCC_APB1Periph_COMP : stm32l1xx_rcc.h
  • RCC_APB1Periph_DAC : stm32l1xx_rcc.h
  • RCC_APB1Periph_I2C1 : stm32l1xx_rcc.h
  • RCC_APB1Periph_I2C2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_LCD : stm32l1xx_rcc.h
  • RCC_APB1Periph_PWR : stm32l1xx_rcc.h
  • RCC_APB1Periph_SPI2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_SPI3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM4 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM5 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM6 : stm32l1xx_rcc.h
  • RCC_APB1Periph_TIM7 : stm32l1xx_rcc.h
  • RCC_APB1Periph_UART4 : stm32l1xx_rcc.h
  • RCC_APB1Periph_UART5 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USART2 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USART3 : stm32l1xx_rcc.h
  • RCC_APB1Periph_USB : stm32l1xx_rcc.h
  • RCC_APB1Periph_WWDG : stm32l1xx_rcc.h
  • RCC_APB1RSTR_COMPRST : stm32l1xx.h
  • RCC_APB1RSTR_DACRST : stm32l1xx.h
  • RCC_APB1RSTR_I2C1RST : stm32l1xx.h
  • RCC_APB1RSTR_I2C2RST : stm32l1xx.h
  • RCC_APB1RSTR_LCDRST : stm32l1xx.h
  • RCC_APB1RSTR_PWRRST : stm32l1xx.h
  • RCC_APB1RSTR_SPI2RST : stm32l1xx.h
  • RCC_APB1RSTR_SPI3RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM2RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM3RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM4RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM5RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM6RST : stm32l1xx.h
  • RCC_APB1RSTR_TIM7RST : stm32l1xx.h
  • RCC_APB1RSTR_UART4RST : stm32l1xx.h
  • RCC_APB1RSTR_UART5RST : stm32l1xx.h
  • RCC_APB1RSTR_USART2RST : stm32l1xx.h
  • RCC_APB1RSTR_USART3RST : stm32l1xx.h
  • RCC_APB1RSTR_USBRST : stm32l1xx.h
  • RCC_APB1RSTR_WWDGRST : stm32l1xx.h
  • RCC_APB2ENR_ADC1EN : stm32l1xx.h
  • RCC_APB2ENR_SDIOEN : stm32l1xx.h
  • RCC_APB2ENR_SPI1EN : stm32l1xx.h
  • RCC_APB2ENR_SYSCFGEN : stm32l1xx.h
  • RCC_APB2ENR_TIM10EN : stm32l1xx.h
  • RCC_APB2ENR_TIM11EN : stm32l1xx.h
  • RCC_APB2ENR_TIM9EN : stm32l1xx.h
  • RCC_APB2ENR_USART1EN : stm32l1xx.h
  • RCC_APB2LPENR_ADC1LPEN : stm32l1xx.h
  • RCC_APB2LPENR_SDIOLPEN : stm32l1xx.h
  • RCC_APB2LPENR_SPI1LPEN : stm32l1xx.h
  • RCC_APB2LPENR_SYSCFGLPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM10LPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM11LPEN : stm32l1xx.h
  • RCC_APB2LPENR_TIM9LPEN : stm32l1xx.h
  • RCC_APB2LPENR_USART1LPEN : stm32l1xx.h
  • RCC_APB2Periph_ADC1 : stm32l1xx_rcc.h
  • RCC_APB2Periph_SDIO : stm32l1xx_rcc.h
  • RCC_APB2Periph_SPI1 : stm32l1xx_rcc.h
  • RCC_APB2Periph_SYSCFG : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM10 : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM11 : stm32l1xx_rcc.h
  • RCC_APB2Periph_TIM9 : stm32l1xx_rcc.h
  • RCC_APB2Periph_USART1 : stm32l1xx_rcc.h
  • RCC_APB2RSTR_ADC1RST : stm32l1xx.h
  • RCC_APB2RSTR_SDIORST : stm32l1xx.h
  • RCC_APB2RSTR_SPI1RST : stm32l1xx.h
  • RCC_APB2RSTR_SYSCFGRST : stm32l1xx.h
  • RCC_APB2RSTR_TIM10RST : stm32l1xx.h
  • RCC_APB2RSTR_TIM11RST : stm32l1xx.h
  • RCC_APB2RSTR_TIM9RST : stm32l1xx.h
  • RCC_APB2RSTR_USART1RST : stm32l1xx.h
  • RCC_BASE : stm32l1xx.h
  • RCC_CFGR_HPRE : stm32l1xx.h
  • RCC_CFGR_HPRE_0 : stm32l1xx.h
  • RCC_CFGR_HPRE_1 : stm32l1xx.h
  • RCC_CFGR_HPRE_2 : stm32l1xx.h
  • RCC_CFGR_HPRE_3 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV1 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV128 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV16 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV2 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV256 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV4 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV512 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV64 : stm32l1xx.h
  • RCC_CFGR_HPRE_DIV8 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV1 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV16 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV2 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV4 : stm32l1xx.h
  • RCC_CFGR_MCO_DIV8 : stm32l1xx.h
  • RCC_CFGR_MCO_HSE : stm32l1xx.h
  • RCC_CFGR_MCO_HSI : stm32l1xx.h
  • RCC_CFGR_MCO_LSE : stm32l1xx.h
  • RCC_CFGR_MCO_LSI : stm32l1xx.h
  • RCC_CFGR_MCO_MSI : stm32l1xx.h
  • RCC_CFGR_MCO_NOCLOCK : stm32l1xx.h
  • RCC_CFGR_MCO_PLL : stm32l1xx.h
  • RCC_CFGR_MCO_SYSCLK : stm32l1xx.h
  • RCC_CFGR_MCOPRE : stm32l1xx.h
  • RCC_CFGR_MCOPRE_0 : stm32l1xx.h
  • RCC_CFGR_MCOPRE_1 : stm32l1xx.h
  • RCC_CFGR_MCOPRE_2 : stm32l1xx.h
  • RCC_CFGR_MCOSEL : stm32l1xx.h
  • RCC_CFGR_MCOSEL_0 : stm32l1xx.h
  • RCC_CFGR_MCOSEL_1 : stm32l1xx.h
  • RCC_CFGR_MCOSEL_2 : stm32l1xx.h
  • RCC_CFGR_PLLDIV : stm32l1xx.h
  • RCC_CFGR_PLLDIV1 : stm32l1xx.h
  • RCC_CFGR_PLLDIV2 : stm32l1xx.h
  • RCC_CFGR_PLLDIV3 : stm32l1xx.h
  • RCC_CFGR_PLLDIV4 : stm32l1xx.h
  • RCC_CFGR_PLLDIV_0 : stm32l1xx.h
  • RCC_CFGR_PLLDIV_1 : stm32l1xx.h
  • RCC_CFGR_PLLMUL : stm32l1xx.h
  • RCC_CFGR_PLLMUL12 : stm32l1xx.h
  • RCC_CFGR_PLLMUL16 : stm32l1xx.h
  • RCC_CFGR_PLLMUL24 : stm32l1xx.h
  • RCC_CFGR_PLLMUL3 : stm32l1xx.h
  • RCC_CFGR_PLLMUL32 : stm32l1xx.h
  • RCC_CFGR_PLLMUL4 : stm32l1xx.h
  • RCC_CFGR_PLLMUL48 : stm32l1xx.h
  • RCC_CFGR_PLLMUL6 : stm32l1xx.h
  • RCC_CFGR_PLLMUL8 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_0 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_1 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_2 : stm32l1xx.h
  • RCC_CFGR_PLLMUL_3 : stm32l1xx.h
  • RCC_CFGR_PLLSRC : stm32l1xx.h
  • RCC_CFGR_PLLSRC_HSE : stm32l1xx.h
  • RCC_CFGR_PLLSRC_HSI : stm32l1xx.h
  • RCC_CFGR_PPRE1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_0 : stm32l1xx.h
  • RCC_CFGR_PPRE1_1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_2 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV1 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV16 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV2 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV4 : stm32l1xx.h
  • RCC_CFGR_PPRE1_DIV8 : stm32l1xx.h
  • RCC_CFGR_PPRE2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_0 : stm32l1xx.h
  • RCC_CFGR_PPRE2_1 : stm32l1xx.h
  • RCC_CFGR_PPRE2_2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV1 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV16 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV2 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV4 : stm32l1xx.h
  • RCC_CFGR_PPRE2_DIV8 : stm32l1xx.h
  • RCC_CFGR_SW : stm32l1xx.h
  • RCC_CFGR_SW_0 : stm32l1xx.h
  • RCC_CFGR_SW_1 : stm32l1xx.h
  • RCC_CFGR_SW_HSE : stm32l1xx.h
  • RCC_CFGR_SW_HSI : stm32l1xx.h
  • RCC_CFGR_SW_MSI : stm32l1xx.h
  • RCC_CFGR_SW_PLL : stm32l1xx.h
  • RCC_CFGR_SWS : stm32l1xx.h
  • RCC_CFGR_SWS_0 : stm32l1xx.h
  • RCC_CFGR_SWS_1 : stm32l1xx.h
  • RCC_CFGR_SWS_HSE : stm32l1xx.h
  • RCC_CFGR_SWS_HSI : stm32l1xx.h
  • RCC_CFGR_SWS_MSI : stm32l1xx.h
  • RCC_CFGR_SWS_PLL : stm32l1xx.h
  • RCC_CIR_CSSC : stm32l1xx.h
  • RCC_CIR_CSSF : stm32l1xx.h
  • RCC_CIR_HSERDYC : stm32l1xx.h
  • RCC_CIR_HSERDYF : stm32l1xx.h
  • RCC_CIR_HSERDYIE : stm32l1xx.h
  • RCC_CIR_HSIRDYC : stm32l1xx.h
  • RCC_CIR_HSIRDYF : stm32l1xx.h
  • RCC_CIR_HSIRDYIE : stm32l1xx.h
  • RCC_CIR_LSECSS : stm32l1xx.h
  • RCC_CIR_LSECSSC : stm32l1xx.h
  • RCC_CIR_LSECSSIE : stm32l1xx.h
  • RCC_CIR_LSERDYC : stm32l1xx.h
  • RCC_CIR_LSERDYF : stm32l1xx.h
  • RCC_CIR_LSERDYIE : stm32l1xx.h
  • RCC_CIR_LSIRDYC : stm32l1xx.h
  • RCC_CIR_LSIRDYF : stm32l1xx.h
  • RCC_CIR_LSIRDYIE : stm32l1xx.h
  • RCC_CIR_MSIRDYC : stm32l1xx.h
  • RCC_CIR_MSIRDYF : stm32l1xx.h
  • RCC_CIR_MSIRDYIE : stm32l1xx.h
  • RCC_CIR_PLLRDYC : stm32l1xx.h
  • RCC_CIR_PLLRDYF : stm32l1xx.h
  • RCC_CIR_PLLRDYIE : stm32l1xx.h
  • RCC_CR_CSSON : stm32l1xx.h
  • RCC_CR_HSEBYP : stm32l1xx.h
  • RCC_CR_HSEON : stm32l1xx.h
  • RCC_CR_HSERDY : stm32l1xx.h
  • RCC_CR_HSION : stm32l1xx.h
  • RCC_CR_HSIRDY : stm32l1xx.h
  • RCC_CR_MSION : stm32l1xx.h
  • RCC_CR_MSIRDY : stm32l1xx.h
  • RCC_CR_PLLON : stm32l1xx.h
  • RCC_CR_PLLRDY : stm32l1xx.h
  • RCC_CR_RTCPRE : stm32l1xx.h
  • RCC_CR_RTCPRE_0 : stm32l1xx.h
  • RCC_CR_RTCPRE_1 : stm32l1xx.h
  • RCC_CSR_IWDGRSTF : stm32l1xx.h
  • RCC_CSR_LPWRRSTF : stm32l1xx.h
  • RCC_CSR_LSEBYP : stm32l1xx.h
  • RCC_CSR_LSECSSD : stm32l1xx.h
  • RCC_CSR_LSECSSON : stm32l1xx.h
  • RCC_CSR_LSEON : stm32l1xx.h
  • RCC_CSR_LSERDY : stm32l1xx.h
  • RCC_CSR_LSION : stm32l1xx.h
  • RCC_CSR_LSIRDY : stm32l1xx.h
  • RCC_CSR_OBLRSTF : stm32l1xx.h
  • RCC_CSR_PINRSTF : stm32l1xx.h
  • RCC_CSR_PORRSTF : stm32l1xx.h
  • RCC_CSR_RMVF : stm32l1xx.h
  • RCC_CSR_RTCEN : stm32l1xx.h
  • RCC_CSR_RTCRST : stm32l1xx.h
  • RCC_CSR_RTCSEL : stm32l1xx.h
  • RCC_CSR_RTCSEL_0 : stm32l1xx.h
  • RCC_CSR_RTCSEL_1 : stm32l1xx.h
  • RCC_CSR_RTCSEL_HSE : stm32l1xx.h
  • RCC_CSR_RTCSEL_LSE : stm32l1xx.h
  • RCC_CSR_RTCSEL_LSI : stm32l1xx.h
  • RCC_CSR_RTCSEL_NOCLOCK : stm32l1xx.h
  • RCC_CSR_SFTRSTF : stm32l1xx.h
  • RCC_CSR_WWDGRSTF : stm32l1xx.h
  • RCC_FLAG_HSERDY : stm32l1xx_rcc.h
  • RCC_FLAG_HSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_IWDGRST : stm32l1xx_rcc.h
  • RCC_FLAG_LPWRRST : stm32l1xx_rcc.h
  • RCC_FLAG_LSECSS : stm32l1xx_rcc.h
  • RCC_FLAG_LSERDY : stm32l1xx_rcc.h
  • RCC_FLAG_LSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_MSIRDY : stm32l1xx_rcc.h
  • RCC_FLAG_OBLRST : stm32l1xx_rcc.h
  • RCC_FLAG_PINRST : stm32l1xx_rcc.h
  • RCC_FLAG_PLLRDY : stm32l1xx_rcc.h
  • RCC_FLAG_PORRST : stm32l1xx_rcc.h
  • RCC_FLAG_SFTRST : stm32l1xx_rcc.h
  • RCC_FLAG_WWDGRST : stm32l1xx_rcc.h
  • RCC_HCLK_Div1 : stm32l1xx_rcc.h
  • RCC_HCLK_Div16 : stm32l1xx_rcc.h
  • RCC_HCLK_Div2 : stm32l1xx_rcc.h
  • RCC_HCLK_Div4 : stm32l1xx_rcc.h
  • RCC_HCLK_Div8 : stm32l1xx_rcc.h
  • RCC_HSE_Bypass : stm32l1xx_rcc.h
  • RCC_HSE_OFF : stm32l1xx_rcc.h
  • RCC_HSE_ON : stm32l1xx_rcc.h
  • RCC_ICSCR_HSICAL : stm32l1xx.h
  • RCC_ICSCR_HSITRIM : stm32l1xx.h
  • RCC_ICSCR_MSICAL : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_0 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_1 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_2 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_3 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_4 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_5 : stm32l1xx.h
  • RCC_ICSCR_MSIRANGE_6 : stm32l1xx.h
  • RCC_ICSCR_MSITRIM : stm32l1xx.h
  • RCC_IT_CSS : stm32l1xx_rcc.h
  • RCC_IT_HSERDY : stm32l1xx_rcc.h
  • RCC_IT_HSIRDY : stm32l1xx_rcc.h
  • RCC_IT_LSECSS : stm32l1xx_rcc.h
  • RCC_IT_LSERDY : stm32l1xx_rcc.h
  • RCC_IT_LSIRDY : stm32l1xx_rcc.h
  • RCC_IT_MSIRDY : stm32l1xx_rcc.h
  • RCC_IT_PLLRDY : stm32l1xx_rcc.h
  • RCC_LSE_Bypass : stm32l1xx_rcc.h
  • RCC_LSE_OFF : stm32l1xx_rcc.h
  • RCC_LSE_ON : stm32l1xx_rcc.h
  • RCC_MCODiv_1 : stm32l1xx_rcc.h
  • RCC_MCODiv_16 : stm32l1xx_rcc.h
  • RCC_MCODiv_2 : stm32l1xx_rcc.h
  • RCC_MCODiv_4 : stm32l1xx_rcc.h
  • RCC_MCODiv_8 : stm32l1xx_rcc.h
  • RCC_MCOSource_HSE : stm32l1xx_rcc.h
  • RCC_MCOSource_HSI : stm32l1xx_rcc.h
  • RCC_MCOSource_LSE : stm32l1xx_rcc.h
  • RCC_MCOSource_LSI : stm32l1xx_rcc.h
  • RCC_MCOSource_MSI : stm32l1xx_rcc.h
  • RCC_MCOSource_NoClock : stm32l1xx_rcc.h
  • RCC_MCOSource_PLLCLK : stm32l1xx_rcc.h
  • RCC_MCOSource_SYSCLK : stm32l1xx_rcc.h
  • RCC_MSIRange_0 : stm32l1xx_rcc.h
  • RCC_MSIRange_1 : stm32l1xx_rcc.h
  • RCC_MSIRange_2 : stm32l1xx_rcc.h
  • RCC_MSIRange_3 : stm32l1xx_rcc.h
  • RCC_MSIRange_4 : stm32l1xx_rcc.h
  • RCC_MSIRange_5 : stm32l1xx_rcc.h
  • RCC_MSIRange_6 : stm32l1xx_rcc.h
  • RCC_OFFSET : stm32l1xx_rcc.c
  • RCC_PLLDiv_2 : stm32l1xx_rcc.h
  • RCC_PLLDiv_3 : stm32l1xx_rcc.h
  • RCC_PLLDiv_4 : stm32l1xx_rcc.h
  • RCC_PLLMul_12 : stm32l1xx_rcc.h
  • RCC_PLLMul_16 : stm32l1xx_rcc.h
  • RCC_PLLMul_24 : stm32l1xx_rcc.h
  • RCC_PLLMul_3 : stm32l1xx_rcc.h
  • RCC_PLLMul_32 : stm32l1xx_rcc.h
  • RCC_PLLMul_4 : stm32l1xx_rcc.h
  • RCC_PLLMul_48 : stm32l1xx_rcc.h
  • RCC_PLLMul_6 : stm32l1xx_rcc.h
  • RCC_PLLMul_8 : stm32l1xx_rcc.h
  • RCC_PLLSource_HSE : stm32l1xx_rcc.h
  • RCC_PLLSource_HSI : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div16 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div2 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div4 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_HSE_Div8 : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_LSE : stm32l1xx_rcc.h
  • RCC_RTCCLKSource_LSI : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div1 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div128 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div16 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div2 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div256 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div4 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div512 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div64 : stm32l1xx_rcc.h
  • RCC_SYSCLK_Div8 : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_HSE : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_HSI : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_MSI : stm32l1xx_rcc.h
  • RCC_SYSCLKSource_PLLCLK : stm32l1xx_rcc.h
  • READ_BIT : stm32l1xx.h
  • READ_REG : stm32l1xx.h
  • RECALPF_TIMEOUT : stm32l1xx_rtc.c
  • RI : stm32l1xx.h
  • RI_ASCR1_CH : stm32l1xx.h
  • RI_ASCR1_CH_0 : stm32l1xx.h
  • RI_ASCR1_CH_1 : stm32l1xx.h
  • RI_ASCR1_CH_10 : stm32l1xx.h
  • RI_ASCR1_CH_11 : stm32l1xx.h
  • RI_ASCR1_CH_12 : stm32l1xx.h
  • RI_ASCR1_CH_13 : stm32l1xx.h
  • RI_ASCR1_CH_14 : stm32l1xx.h
  • RI_ASCR1_CH_15 : stm32l1xx.h
  • RI_ASCR1_CH_18 : stm32l1xx.h
  • RI_ASCR1_CH_19 : stm32l1xx.h
  • RI_ASCR1_CH_2 : stm32l1xx.h
  • RI_ASCR1_CH_20 : stm32l1xx.h
  • RI_ASCR1_CH_21 : stm32l1xx.h
  • RI_ASCR1_CH_22 : stm32l1xx.h
  • RI_ASCR1_CH_23 : stm32l1xx.h
  • RI_ASCR1_CH_24 : stm32l1xx.h
  • RI_ASCR1_CH_25 : stm32l1xx.h
  • RI_ASCR1_CH_27 : stm32l1xx.h
  • RI_ASCR1_CH_28 : stm32l1xx.h
  • RI_ASCR1_CH_29 : stm32l1xx.h
  • RI_ASCR1_CH_3 : stm32l1xx.h
  • RI_ASCR1_CH_30 : stm32l1xx.h
  • RI_ASCR1_CH_31 : stm32l1xx.h
  • RI_ASCR1_CH_4 : stm32l1xx.h
  • RI_ASCR1_CH_5 : stm32l1xx.h
  • RI_ASCR1_CH_6 : stm32l1xx.h
  • RI_ASCR1_CH_7 : stm32l1xx.h
  • RI_ASCR1_CH_8 : stm32l1xx.h
  • RI_ASCR1_CH_9 : stm32l1xx.h
  • RI_ASCR1_SCM : stm32l1xx.h
  • RI_ASCR1_VCOMP : stm32l1xx.h
  • RI_ASCR2_CH0b : stm32l1xx.h
  • RI_ASCR2_CH10b : stm32l1xx.h
  • RI_ASCR2_CH11b : stm32l1xx.h
  • RI_ASCR2_CH12b : stm32l1xx.h
  • RI_ASCR2_CH1b : stm32l1xx.h
  • RI_ASCR2_CH2b : stm32l1xx.h
  • RI_ASCR2_CH3b : stm32l1xx.h
  • RI_ASCR2_CH6b : stm32l1xx.h
  • RI_ASCR2_CH7b : stm32l1xx.h
  • RI_ASCR2_CH8b : stm32l1xx.h
  • RI_ASCR2_CH9b : stm32l1xx.h
  • RI_ASCR2_GR10_1 : stm32l1xx.h
  • RI_ASCR2_GR10_2 : stm32l1xx.h
  • RI_ASCR2_GR10_3 : stm32l1xx.h
  • RI_ASCR2_GR10_4 : stm32l1xx.h
  • RI_ASCR2_GR4_1 : stm32l1xx.h
  • RI_ASCR2_GR4_2 : stm32l1xx.h
  • RI_ASCR2_GR4_3 : stm32l1xx.h
  • RI_ASCR2_GR4_4 : stm32l1xx.h
  • RI_ASCR2_GR5_1 : stm32l1xx.h
  • RI_ASCR2_GR5_2 : stm32l1xx.h
  • RI_ASCR2_GR5_3 : stm32l1xx.h
  • RI_ASCR2_GR5_4 : stm32l1xx.h
  • RI_ASCR2_GR6_1 : stm32l1xx.h
  • RI_ASCR2_GR6_2 : stm32l1xx.h
  • RI_ASCR2_GR6_3 : stm32l1xx.h
  • RI_ASCR2_GR6_4 : stm32l1xx.h
  • RI_BASE : stm32l1xx.h
  • RI_Channel_13 : stm32l1xx_syscfg.h
  • RI_Channel_3 : stm32l1xx_syscfg.h
  • RI_Channel_8 : stm32l1xx_syscfg.h
  • RI_ChannelSpeed_Fast : stm32l1xx_syscfg.h
  • RI_ChannelSpeed_Slow : stm32l1xx_syscfg.h
  • RI_HYSCR1_PA : stm32l1xx.h
  • RI_HYSCR1_PA_0 : stm32l1xx.h
  • RI_HYSCR1_PA_1 : stm32l1xx.h
  • RI_HYSCR1_PA_10 : stm32l1xx.h
  • RI_HYSCR1_PA_11 : stm32l1xx.h
  • RI_HYSCR1_PA_12 : stm32l1xx.h
  • RI_HYSCR1_PA_13 : stm32l1xx.h
  • RI_HYSCR1_PA_14 : stm32l1xx.h
  • RI_HYSCR1_PA_15 : stm32l1xx.h
  • RI_HYSCR1_PA_2 : stm32l1xx.h
  • RI_HYSCR1_PA_3 : stm32l1xx.h
  • RI_HYSCR1_PA_4 : stm32l1xx.h
  • RI_HYSCR1_PA_5 : stm32l1xx.h
  • RI_HYSCR1_PA_6 : stm32l1xx.h
  • RI_HYSCR1_PA_7 : stm32l1xx.h
  • RI_HYSCR1_PA_8 : stm32l1xx.h
  • RI_HYSCR1_PA_9 : stm32l1xx.h
  • RI_HYSCR1_PB : stm32l1xx.h
  • RI_HYSCR1_PB_0 : stm32l1xx.h
  • RI_HYSCR1_PB_1 : stm32l1xx.h
  • RI_HYSCR1_PB_10 : stm32l1xx.h
  • RI_HYSCR1_PB_11 : stm32l1xx.h
  • RI_HYSCR1_PB_12 : stm32l1xx.h
  • RI_HYSCR1_PB_13 : stm32l1xx.h
  • RI_HYSCR1_PB_14 : stm32l1xx.h
  • RI_HYSCR1_PB_15 : stm32l1xx.h
  • RI_HYSCR1_PB_2 : stm32l1xx.h
  • RI_HYSCR1_PB_3 : stm32l1xx.h
  • RI_HYSCR1_PB_4 : stm32l1xx.h
  • RI_HYSCR1_PB_5 : stm32l1xx.h
  • RI_HYSCR1_PB_6 : stm32l1xx.h
  • RI_HYSCR1_PB_7 : stm32l1xx.h
  • RI_HYSCR1_PB_8 : stm32l1xx.h
  • RI_HYSCR1_PB_9 : stm32l1xx.h
  • RI_HYSCR2_PC : stm32l1xx.h
  • RI_HYSCR2_PC_0 : stm32l1xx.h
  • RI_HYSCR2_PC_1 : stm32l1xx.h
  • RI_HYSCR2_PC_10 : stm32l1xx.h
  • RI_HYSCR2_PC_11 : stm32l1xx.h
  • RI_HYSCR2_PC_12 : stm32l1xx.h
  • RI_HYSCR2_PC_13 : stm32l1xx.h
  • RI_HYSCR2_PC_14 : stm32l1xx.h
  • RI_HYSCR2_PC_15 : stm32l1xx.h
  • RI_HYSCR2_PC_2 : stm32l1xx.h
  • RI_HYSCR2_PC_3 : stm32l1xx.h
  • RI_HYSCR2_PC_4 : stm32l1xx.h
  • RI_HYSCR2_PC_5 : stm32l1xx.h
  • RI_HYSCR2_PC_6 : stm32l1xx.h
  • RI_HYSCR2_PC_7 : stm32l1xx.h
  • RI_HYSCR2_PC_8 : stm32l1xx.h
  • RI_HYSCR2_PC_9 : stm32l1xx.h
  • RI_HYSCR2_PD : stm32l1xx.h
  • RI_HYSCR2_PD_0 : stm32l1xx.h
  • RI_HYSCR2_PD_1 : stm32l1xx.h
  • RI_HYSCR2_PD_10 : stm32l1xx.h
  • RI_HYSCR2_PD_11 : stm32l1xx.h
  • RI_HYSCR2_PD_12 : stm32l1xx.h
  • RI_HYSCR2_PD_13 : stm32l1xx.h
  • RI_HYSCR2_PD_14 : stm32l1xx.h
  • RI_HYSCR2_PD_15 : stm32l1xx.h
  • RI_HYSCR2_PD_2 : stm32l1xx.h
  • RI_HYSCR2_PD_3 : stm32l1xx.h
  • RI_HYSCR2_PD_4 : stm32l1xx.h
  • RI_HYSCR2_PD_5 : stm32l1xx.h
  • RI_HYSCR2_PD_6 : stm32l1xx.h
  • RI_HYSCR2_PD_7 : stm32l1xx.h
  • RI_HYSCR2_PD_8 : stm32l1xx.h
  • RI_HYSCR2_PD_9 : stm32l1xx.h
  • RI_HYSCR2_PE : stm32l1xx.h
  • RI_HYSCR2_PE_0 : stm32l1xx.h
  • RI_HYSCR2_PE_1 : stm32l1xx.h
  • RI_HYSCR2_PE_10 : stm32l1xx.h
  • RI_HYSCR2_PE_11 : stm32l1xx.h
  • RI_HYSCR2_PE_12 : stm32l1xx.h
  • RI_HYSCR2_PE_13 : stm32l1xx.h
  • RI_HYSCR2_PE_14 : stm32l1xx.h
  • RI_HYSCR2_PE_15 : stm32l1xx.h
  • RI_HYSCR2_PE_2 : stm32l1xx.h
  • RI_HYSCR2_PE_3 : stm32l1xx.h
  • RI_HYSCR2_PE_4 : stm32l1xx.h
  • RI_HYSCR2_PE_5 : stm32l1xx.h
  • RI_HYSCR2_PE_6 : stm32l1xx.h
  • RI_HYSCR2_PE_7 : stm32l1xx.h
  • RI_HYSCR2_PE_8 : stm32l1xx.h
  • RI_HYSCR2_PE_9 : stm32l1xx.h
  • RI_HYSCR3_PF : stm32l1xx.h
  • RI_HYSCR3_PF_0 : stm32l1xx.h
  • RI_HYSCR3_PF_1 : stm32l1xx.h
  • RI_HYSCR3_PF_10 : stm32l1xx.h
  • RI_HYSCR3_PF_11 : stm32l1xx.h
  • RI_HYSCR3_PF_12 : stm32l1xx.h
  • RI_HYSCR3_PF_13 : stm32l1xx.h
  • RI_HYSCR3_PF_14 : stm32l1xx.h
  • RI_HYSCR3_PF_15 : stm32l1xx.h
  • RI_HYSCR3_PF_2 : stm32l1xx.h
  • RI_HYSCR3_PF_3 : stm32l1xx.h
  • RI_HYSCR3_PF_4 : stm32l1xx.h
  • RI_HYSCR3_PF_5 : stm32l1xx.h
  • RI_HYSCR3_PF_6 : stm32l1xx.h
  • RI_HYSCR3_PF_7 : stm32l1xx.h
  • RI_HYSCR3_PF_8 : stm32l1xx.h
  • RI_HYSCR3_PF_9 : stm32l1xx.h
  • RI_HYSCR4_PG : stm32l1xx.h
  • RI_HYSCR4_PG_0 : stm32l1xx.h
  • RI_HYSCR4_PG_1 : stm32l1xx.h
  • RI_HYSCR4_PG_10 : stm32l1xx.h
  • RI_HYSCR4_PG_11 : stm32l1xx.h
  • RI_HYSCR4_PG_12 : stm32l1xx.h
  • RI_HYSCR4_PG_13 : stm32l1xx.h
  • RI_HYSCR4_PG_14 : stm32l1xx.h
  • RI_HYSCR4_PG_15 : stm32l1xx.h
  • RI_HYSCR4_PG_2 : stm32l1xx.h
  • RI_HYSCR4_PG_3 : stm32l1xx.h
  • RI_HYSCR4_PG_4 : stm32l1xx.h
  • RI_HYSCR4_PG_5 : stm32l1xx.h
  • RI_HYSCR4_PG_6 : stm32l1xx.h
  • RI_HYSCR4_PG_7 : stm32l1xx.h
  • RI_HYSCR4_PG_8 : stm32l1xx.h
  • RI_HYSCR4_PG_9 : stm32l1xx.h
  • RI_ICR_IC1 : stm32l1xx.h
  • RI_ICR_IC1Z : stm32l1xx.h
  • RI_ICR_IC1Z_0 : stm32l1xx.h
  • RI_ICR_IC1Z_1 : stm32l1xx.h
  • RI_ICR_IC1Z_2 : stm32l1xx.h
  • RI_ICR_IC1Z_3 : stm32l1xx.h
  • RI_ICR_IC2 : stm32l1xx.h
  • RI_ICR_IC2Z : stm32l1xx.h
  • RI_ICR_IC2Z_0 : stm32l1xx.h
  • RI_ICR_IC2Z_1 : stm32l1xx.h
  • RI_ICR_IC2Z_2 : stm32l1xx.h
  • RI_ICR_IC2Z_3 : stm32l1xx.h
  • RI_ICR_IC3 : stm32l1xx.h
  • RI_ICR_IC3Z : stm32l1xx.h
  • RI_ICR_IC3Z_0 : stm32l1xx.h
  • RI_ICR_IC3Z_1 : stm32l1xx.h
  • RI_ICR_IC3Z_2 : stm32l1xx.h
  • RI_ICR_IC3Z_3 : stm32l1xx.h
  • RI_ICR_IC4 : stm32l1xx.h
  • RI_ICR_IC4Z : stm32l1xx.h
  • RI_ICR_IC4Z_0 : stm32l1xx.h
  • RI_ICR_IC4Z_1 : stm32l1xx.h
  • RI_ICR_IC4Z_2 : stm32l1xx.h
  • RI_ICR_IC4Z_3 : stm32l1xx.h
  • RI_ICR_TIM : stm32l1xx.h
  • RI_ICR_TIM_0 : stm32l1xx.h
  • RI_ICR_TIM_1 : stm32l1xx.h
  • RI_InputCapture_IC1 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC2 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC3 : stm32l1xx_syscfg.h
  • RI_InputCapture_IC4 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_0 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_1 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_10 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_11 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_12 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_13 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_14 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_15 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_2 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_3 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_4 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_5 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_6 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_7 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_8 : stm32l1xx_syscfg.h
  • RI_InputCaptureRouting_9 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH0 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH0b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH10 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH10b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH11 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH11b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH12 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH12b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH13 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH14 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH15 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH18 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH19 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH1b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH20 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH21 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH22 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH23 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH24 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH25 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH27 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH28 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH29 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH2b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH30 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH31 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH3b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH5 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH6 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH6b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH7 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH7b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH8 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH8b : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH9 : stm32l1xx_syscfg.h
  • RI_IOSwitch_CH9b : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR10_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR4_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR5_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_1 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_2 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_3 : stm32l1xx_syscfg.h
  • RI_IOSwitch_GR6_4 : stm32l1xx_syscfg.h
  • RI_IOSwitch_VCOMP : stm32l1xx_syscfg.h
  • RI_Pin_0 : stm32l1xx_syscfg.h
  • RI_Pin_1 : stm32l1xx_syscfg.h
  • RI_Pin_10 : stm32l1xx_syscfg.h
  • RI_Pin_11 : stm32l1xx_syscfg.h
  • RI_Pin_12 : stm32l1xx_syscfg.h
  • RI_Pin_13 : stm32l1xx_syscfg.h
  • RI_Pin_14 : stm32l1xx_syscfg.h
  • RI_Pin_15 : stm32l1xx_syscfg.h
  • RI_Pin_2 : stm32l1xx_syscfg.h
  • RI_Pin_3 : stm32l1xx_syscfg.h
  • RI_Pin_4 : stm32l1xx_syscfg.h
  • RI_Pin_5 : stm32l1xx_syscfg.h
  • RI_Pin_6 : stm32l1xx_syscfg.h
  • RI_Pin_7 : stm32l1xx_syscfg.h
  • RI_Pin_8 : stm32l1xx_syscfg.h
  • RI_Pin_9 : stm32l1xx_syscfg.h
  • RI_Pin_All : stm32l1xx_syscfg.h
  • RI_PortA : stm32l1xx_syscfg.h
  • RI_PortB : stm32l1xx_syscfg.h
  • RI_PortC : stm32l1xx_syscfg.h
  • RI_PortD : stm32l1xx_syscfg.h
  • RI_PortE : stm32l1xx_syscfg.h
  • RI_PortF : stm32l1xx_syscfg.h
  • RI_PortG : stm32l1xx_syscfg.h
  • RI_Resistor_10KPD : stm32l1xx_syscfg.h
  • RI_Resistor_10KPU : stm32l1xx_syscfg.h
  • RI_Resistor_400KPD : stm32l1xx_syscfg.h
  • RI_Resistor_400KPU : stm32l1xx_syscfg.h
  • RTC : stm32l1xx.h
  • RTC_Alarm_A : stm32l1xx_rtc.h
  • RTC_Alarm_B : stm32l1xx_rtc.h
  • RTC_AlarmDateWeekDaySel_Date : stm32l1xx_rtc.h
  • RTC_AlarmDateWeekDaySel_WeekDay : stm32l1xx_rtc.h
  • RTC_AlarmMask_All : stm32l1xx_rtc.h
  • RTC_AlarmMask_DateWeekDay : stm32l1xx_rtc.h
  • RTC_AlarmMask_Hours : stm32l1xx_rtc.h
  • RTC_AlarmMask_Minutes : stm32l1xx_rtc.h
  • RTC_AlarmMask_None : stm32l1xx_rtc.h
  • RTC_AlarmMask_Seconds : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_All : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_None : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_1 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_10 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_11 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_12 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_13 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_2 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_3 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_4 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_5 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_6 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_7 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_8 : stm32l1xx_rtc.h
  • RTC_AlarmSubSecondMask_SS14_9 : stm32l1xx_rtc.h
  • RTC_ALRMAR_DT : stm32l1xx.h
  • RTC_ALRMAR_DT_0 : stm32l1xx.h
  • RTC_ALRMAR_DT_1 : stm32l1xx.h
  • RTC_ALRMAR_DU : stm32l1xx.h
  • RTC_ALRMAR_DU_0 : stm32l1xx.h
  • RTC_ALRMAR_DU_1 : stm32l1xx.h
  • RTC_ALRMAR_DU_2 : stm32l1xx.h
  • RTC_ALRMAR_DU_3 : stm32l1xx.h
  • RTC_ALRMAR_HT : stm32l1xx.h
  • RTC_ALRMAR_HT_0 : stm32l1xx.h
  • RTC_ALRMAR_HT_1 : stm32l1xx.h
  • RTC_ALRMAR_HU : stm32l1xx.h
  • RTC_ALRMAR_HU_0 : stm32l1xx.h
  • RTC_ALRMAR_HU_1 : stm32l1xx.h
  • RTC_ALRMAR_HU_2 : stm32l1xx.h
  • RTC_ALRMAR_HU_3 : stm32l1xx.h
  • RTC_ALRMAR_MNT : stm32l1xx.h
  • RTC_ALRMAR_MNT_0 : stm32l1xx.h
  • RTC_ALRMAR_MNT_1 : stm32l1xx.h
  • RTC_ALRMAR_MNT_2 : stm32l1xx.h
  • RTC_ALRMAR_MNU : stm32l1xx.h
  • RTC_ALRMAR_MNU_0 : stm32l1xx.h
  • RTC_ALRMAR_MNU_1 : stm32l1xx.h
  • RTC_ALRMAR_MNU_2 : stm32l1xx.h
  • RTC_ALRMAR_MNU_3 : stm32l1xx.h
  • RTC_ALRMAR_MSK1 : stm32l1xx.h
  • RTC_ALRMAR_MSK2 : stm32l1xx.h
  • RTC_ALRMAR_MSK3 : stm32l1xx.h
  • RTC_ALRMAR_MSK4 : stm32l1xx.h
  • RTC_ALRMAR_PM : stm32l1xx.h
  • RTC_ALRMAR_ST : stm32l1xx.h
  • RTC_ALRMAR_ST_0 : stm32l1xx.h
  • RTC_ALRMAR_ST_1 : stm32l1xx.h
  • RTC_ALRMAR_ST_2 : stm32l1xx.h
  • RTC_ALRMAR_SU : stm32l1xx.h
  • RTC_ALRMAR_SU_0 : stm32l1xx.h
  • RTC_ALRMAR_SU_1 : stm32l1xx.h
  • RTC_ALRMAR_SU_2 : stm32l1xx.h
  • RTC_ALRMAR_SU_3 : stm32l1xx.h
  • RTC_ALRMAR_WDSEL : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_0 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_1 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_2 : stm32l1xx.h
  • RTC_ALRMASSR_MASKSS_3 : stm32l1xx.h
  • RTC_ALRMASSR_SS : stm32l1xx.h
  • RTC_ALRMBR_DT : stm32l1xx.h
  • RTC_ALRMBR_DT_0 : stm32l1xx.h
  • RTC_ALRMBR_DT_1 : stm32l1xx.h
  • RTC_ALRMBR_DU : stm32l1xx.h
  • RTC_ALRMBR_DU_0 : stm32l1xx.h
  • RTC_ALRMBR_DU_1 : stm32l1xx.h
  • RTC_ALRMBR_DU_2 : stm32l1xx.h
  • RTC_ALRMBR_DU_3 : stm32l1xx.h
  • RTC_ALRMBR_HT : stm32l1xx.h
  • RTC_ALRMBR_HT_0 : stm32l1xx.h
  • RTC_ALRMBR_HT_1 : stm32l1xx.h
  • RTC_ALRMBR_HU : stm32l1xx.h
  • RTC_ALRMBR_HU_0 : stm32l1xx.h
  • RTC_ALRMBR_HU_1 : stm32l1xx.h
  • RTC_ALRMBR_HU_2 : stm32l1xx.h
  • RTC_ALRMBR_HU_3 : stm32l1xx.h
  • RTC_ALRMBR_MNT : stm32l1xx.h
  • RTC_ALRMBR_MNT_0 : stm32l1xx.h
  • RTC_ALRMBR_MNT_1 : stm32l1xx.h
  • RTC_ALRMBR_MNT_2 : stm32l1xx.h
  • RTC_ALRMBR_MNU : stm32l1xx.h
  • RTC_ALRMBR_MNU_0 : stm32l1xx.h
  • RTC_ALRMBR_MNU_1 : stm32l1xx.h
  • RTC_ALRMBR_MNU_2 : stm32l1xx.h
  • RTC_ALRMBR_MNU_3 : stm32l1xx.h
  • RTC_ALRMBR_MSK1 : stm32l1xx.h
  • RTC_ALRMBR_MSK2 : stm32l1xx.h
  • RTC_ALRMBR_MSK3 : stm32l1xx.h
  • RTC_ALRMBR_MSK4 : stm32l1xx.h
  • RTC_ALRMBR_PM : stm32l1xx.h
  • RTC_ALRMBR_ST : stm32l1xx.h
  • RTC_ALRMBR_ST_0 : stm32l1xx.h
  • RTC_ALRMBR_ST_1 : stm32l1xx.h
  • RTC_ALRMBR_ST_2 : stm32l1xx.h
  • RTC_ALRMBR_SU : stm32l1xx.h
  • RTC_ALRMBR_SU_0 : stm32l1xx.h
  • RTC_ALRMBR_SU_1 : stm32l1xx.h
  • RTC_ALRMBR_SU_2 : stm32l1xx.h
  • RTC_ALRMBR_SU_3 : stm32l1xx.h
  • RTC_ALRMBR_WDSEL : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_0 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_1 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_2 : stm32l1xx.h
  • RTC_ALRMBSSR_MASKSS_3 : stm32l1xx.h
  • RTC_ALRMBSSR_SS : stm32l1xx.h
  • RTC_BASE : stm32l1xx.h
  • RTC_BKP0R : stm32l1xx.h
  • RTC_BKP10R : stm32l1xx.h
  • RTC_BKP11R : stm32l1xx.h
  • RTC_BKP12R : stm32l1xx.h
  • RTC_BKP13R : stm32l1xx.h
  • RTC_BKP14R : stm32l1xx.h
  • RTC_BKP15R : stm32l1xx.h
  • RTC_BKP16R : stm32l1xx.h
  • RTC_BKP17R : stm32l1xx.h
  • RTC_BKP18R : stm32l1xx.h
  • RTC_BKP19R : stm32l1xx.h
  • RTC_BKP1R : stm32l1xx.h
  • RTC_BKP20R : stm32l1xx.h
  • RTC_BKP21R : stm32l1xx.h
  • RTC_BKP22R : stm32l1xx.h
  • RTC_BKP23R : stm32l1xx.h
  • RTC_BKP24R : stm32l1xx.h
  • RTC_BKP25R : stm32l1xx.h
  • RTC_BKP26R : stm32l1xx.h
  • RTC_BKP27R : stm32l1xx.h
  • RTC_BKP28R : stm32l1xx.h
  • RTC_BKP29R : stm32l1xx.h
  • RTC_BKP2R : stm32l1xx.h
  • RTC_BKP30R : stm32l1xx.h
  • RTC_BKP31R : stm32l1xx.h
  • RTC_BKP3R : stm32l1xx.h
  • RTC_BKP4R : stm32l1xx.h
  • RTC_BKP5R : stm32l1xx.h
  • RTC_BKP6R : stm32l1xx.h
  • RTC_BKP7R : stm32l1xx.h
  • RTC_BKP8R : stm32l1xx.h
  • RTC_BKP9R : stm32l1xx.h
  • RTC_BKP_DR0 : stm32l1xx_rtc.h
  • RTC_BKP_DR1 : stm32l1xx_rtc.h
  • RTC_BKP_DR10 : stm32l1xx_rtc.h
  • RTC_BKP_DR11 : stm32l1xx_rtc.h
  • RTC_BKP_DR12 : stm32l1xx_rtc.h
  • RTC_BKP_DR13 : stm32l1xx_rtc.h
  • RTC_BKP_DR14 : stm32l1xx_rtc.h
  • RTC_BKP_DR15 : stm32l1xx_rtc.h
  • RTC_BKP_DR16 : stm32l1xx_rtc.h
  • RTC_BKP_DR17 : stm32l1xx_rtc.h
  • RTC_BKP_DR18 : stm32l1xx_rtc.h
  • RTC_BKP_DR19 : stm32l1xx_rtc.h
  • RTC_BKP_DR2 : stm32l1xx_rtc.h
  • RTC_BKP_DR20 : stm32l1xx_rtc.h
  • RTC_BKP_DR21 : stm32l1xx_rtc.h
  • RTC_BKP_DR22 : stm32l1xx_rtc.h
  • RTC_BKP_DR23 : stm32l1xx_rtc.h
  • RTC_BKP_DR24 : stm32l1xx_rtc.h
  • RTC_BKP_DR25 : stm32l1xx_rtc.h
  • RTC_BKP_DR26 : stm32l1xx_rtc.h
  • RTC_BKP_DR27 : stm32l1xx_rtc.h
  • RTC_BKP_DR28 : stm32l1xx_rtc.h
  • RTC_BKP_DR29 : stm32l1xx_rtc.h
  • RTC_BKP_DR3 : stm32l1xx_rtc.h
  • RTC_BKP_DR30 : stm32l1xx_rtc.h
  • RTC_BKP_DR31 : stm32l1xx_rtc.h
  • RTC_BKP_DR4 : stm32l1xx_rtc.h
  • RTC_BKP_DR5 : stm32l1xx_rtc.h
  • RTC_BKP_DR6 : stm32l1xx_rtc.h
  • RTC_BKP_DR7 : stm32l1xx_rtc.h
  • RTC_BKP_DR8 : stm32l1xx_rtc.h
  • RTC_BKP_DR9 : stm32l1xx_rtc.h
  • RTC_CalibOutput_1Hz : stm32l1xx_rtc.h
  • RTC_CalibOutput_512Hz : stm32l1xx_rtc.h
  • RTC_CALIBR_DC : stm32l1xx.h
  • RTC_CALIBR_DCS : stm32l1xx.h
  • RTC_CalibSign_Negative : stm32l1xx_rtc.h
  • RTC_CalibSign_Positive : stm32l1xx_rtc.h
  • RTC_CALR_CALM : stm32l1xx.h
  • RTC_CALR_CALM_0 : stm32l1xx.h
  • RTC_CALR_CALM_1 : stm32l1xx.h
  • RTC_CALR_CALM_2 : stm32l1xx.h
  • RTC_CALR_CALM_3 : stm32l1xx.h
  • RTC_CALR_CALM_4 : stm32l1xx.h
  • RTC_CALR_CALM_5 : stm32l1xx.h
  • RTC_CALR_CALM_6 : stm32l1xx.h
  • RTC_CALR_CALM_7 : stm32l1xx.h
  • RTC_CALR_CALM_8 : stm32l1xx.h
  • RTC_CALR_CALP : stm32l1xx.h
  • RTC_CALR_CALW16 : stm32l1xx.h
  • RTC_CALR_CALW8 : stm32l1xx.h
  • RTC_CR_ADD1H : stm32l1xx.h
  • RTC_CR_ALRAE : stm32l1xx.h
  • RTC_CR_ALRAIE : stm32l1xx.h
  • RTC_CR_ALRBE : stm32l1xx.h
  • RTC_CR_ALRBIE : stm32l1xx.h
  • RTC_CR_BCK : stm32l1xx.h
  • RTC_CR_BYPSHAD : stm32l1xx.h
  • RTC_CR_COE : stm32l1xx.h
  • RTC_CR_COSEL : stm32l1xx.h
  • RTC_CR_DCE : stm32l1xx.h
  • RTC_CR_FMT : stm32l1xx.h
  • RTC_CR_OSEL : stm32l1xx.h
  • RTC_CR_OSEL_0 : stm32l1xx.h
  • RTC_CR_OSEL_1 : stm32l1xx.h
  • RTC_CR_POL : stm32l1xx.h
  • RTC_CR_REFCKON : stm32l1xx.h
  • RTC_CR_SUB1H : stm32l1xx.h
  • RTC_CR_TSE : stm32l1xx.h
  • RTC_CR_TSEDGE : stm32l1xx.h
  • RTC_CR_TSIE : stm32l1xx.h
  • RTC_CR_WUCKSEL : stm32l1xx.h
  • RTC_CR_WUCKSEL_0 : stm32l1xx.h
  • RTC_CR_WUCKSEL_1 : stm32l1xx.h
  • RTC_CR_WUCKSEL_2 : stm32l1xx.h
  • RTC_CR_WUTE : stm32l1xx.h
  • RTC_CR_WUTIE : stm32l1xx.h
  • RTC_DayLightSaving_ADD1H : stm32l1xx_rtc.h
  • RTC_DayLightSaving_SUB1H : stm32l1xx_rtc.h
  • RTC_DigitalCalibCmd : stm32l1xx_rtc.h
  • RTC_DigitalCalibConfig : stm32l1xx_rtc.h
  • RTC_DR_DT : stm32l1xx.h
  • RTC_DR_DT_0 : stm32l1xx.h
  • RTC_DR_DT_1 : stm32l1xx.h
  • RTC_DR_DU : stm32l1xx.h
  • RTC_DR_DU_0 : stm32l1xx.h
  • RTC_DR_DU_1 : stm32l1xx.h
  • RTC_DR_DU_2 : stm32l1xx.h
  • RTC_DR_DU_3 : stm32l1xx.h
  • RTC_DR_MT : stm32l1xx.h
  • RTC_DR_MU : stm32l1xx.h
  • RTC_DR_MU_0 : stm32l1xx.h
  • RTC_DR_MU_1 : stm32l1xx.h
  • RTC_DR_MU_2 : stm32l1xx.h
  • RTC_DR_MU_3 : stm32l1xx.h
  • RTC_DR_RESERVED_MASK : stm32l1xx_rtc.c
  • RTC_DR_WDU : stm32l1xx.h
  • RTC_DR_WDU_0 : stm32l1xx.h
  • RTC_DR_WDU_1 : stm32l1xx.h
  • RTC_DR_WDU_2 : stm32l1xx.h
  • RTC_DR_YT : stm32l1xx.h
  • RTC_DR_YT_0 : stm32l1xx.h
  • RTC_DR_YT_1 : stm32l1xx.h
  • RTC_DR_YT_2 : stm32l1xx.h
  • RTC_DR_YT_3 : stm32l1xx.h
  • RTC_DR_YU : stm32l1xx.h
  • RTC_DR_YU_0 : stm32l1xx.h
  • RTC_DR_YU_1 : stm32l1xx.h
  • RTC_DR_YU_2 : stm32l1xx.h
  • RTC_DR_YU_3 : stm32l1xx.h
  • RTC_FLAG_ALRAF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRAWF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRBF : stm32l1xx_rtc.h
  • RTC_FLAG_ALRBWF : stm32l1xx_rtc.h
  • RTC_FLAG_INITF : stm32l1xx_rtc.h
  • RTC_FLAG_INITS : stm32l1xx_rtc.h
  • RTC_FLAG_RECALPF : stm32l1xx_rtc.h
  • RTC_FLAG_RSF : stm32l1xx_rtc.h
  • RTC_FLAG_SHPF : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP1F : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP2F : stm32l1xx_rtc.h
  • RTC_FLAG_TAMP3F : stm32l1xx_rtc.h
  • RTC_FLAG_TSF : stm32l1xx_rtc.h
  • RTC_FLAG_TSOVF : stm32l1xx_rtc.h
  • RTC_FLAG_WUTF : stm32l1xx_rtc.h
  • RTC_FLAG_WUTWF : stm32l1xx_rtc.h
  • RTC_FLAGS_MASK : stm32l1xx_rtc.c
  • RTC_Format_BCD : stm32l1xx_rtc.h
  • RTC_Format_BIN : stm32l1xx_rtc.h
  • RTC_H12_AM : stm32l1xx_rtc.h
  • RTC_H12_PM : stm32l1xx_rtc.h
  • RTC_HourFormat_12 : stm32l1xx_rtc.h
  • RTC_HourFormat_24 : stm32l1xx_rtc.h
  • RTC_INIT_MASK : stm32l1xx_rtc.c
  • RTC_ISR_ALRAF : stm32l1xx.h
  • RTC_ISR_ALRAWF : stm32l1xx.h
  • RTC_ISR_ALRBF : stm32l1xx.h
  • RTC_ISR_ALRBWF : stm32l1xx.h
  • RTC_ISR_INIT : stm32l1xx.h
  • RTC_ISR_INITF : stm32l1xx.h
  • RTC_ISR_INITS : stm32l1xx.h
  • RTC_ISR_RECALPF : stm32l1xx.h
  • RTC_ISR_RSF : stm32l1xx.h
  • RTC_ISR_SHPF : stm32l1xx.h
  • RTC_ISR_TAMP1F : stm32l1xx.h
  • RTC_ISR_TAMP2F : stm32l1xx.h
  • RTC_ISR_TAMP3F : stm32l1xx.h
  • RTC_ISR_TSF : stm32l1xx.h
  • RTC_ISR_TSOVF : stm32l1xx.h
  • RTC_ISR_WUTF : stm32l1xx.h
  • RTC_ISR_WUTWF : stm32l1xx.h
  • RTC_IT_ALRA : stm32l1xx_rtc.h
  • RTC_IT_ALRB : stm32l1xx_rtc.h
  • RTC_IT_TAMP : stm32l1xx_rtc.h
  • RTC_IT_TAMP1 : stm32l1xx_rtc.h
  • RTC_IT_TAMP2 : stm32l1xx_rtc.h
  • RTC_IT_TAMP3 : stm32l1xx_rtc.h
  • RTC_IT_TS : stm32l1xx_rtc.h
  • RTC_IT_WUT : stm32l1xx_rtc.h
  • RTC_Month_April : stm32l1xx_rtc.h
  • RTC_Month_August : stm32l1xx_rtc.h
  • RTC_Month_December : stm32l1xx_rtc.h
  • RTC_Month_February : stm32l1xx_rtc.h
  • RTC_Month_January : stm32l1xx_rtc.h
  • RTC_Month_July : stm32l1xx_rtc.h
  • RTC_Month_June : stm32l1xx_rtc.h
  • RTC_Month_March : stm32l1xx_rtc.h
  • RTC_Month_May : stm32l1xx_rtc.h
  • RTC_Month_November : stm32l1xx_rtc.h
  • RTC_Month_October : stm32l1xx_rtc.h
  • RTC_Month_September : stm32l1xx_rtc.h
  • RTC_Output_AlarmA : stm32l1xx_rtc.h
  • RTC_Output_AlarmB : stm32l1xx_rtc.h
  • RTC_Output_Disable : stm32l1xx_rtc.h
  • RTC_Output_WakeUp : stm32l1xx_rtc.h
  • RTC_OutputPolarity_High : stm32l1xx_rtc.h
  • RTC_OutputPolarity_Low : stm32l1xx_rtc.h
  • RTC_OutputType_OpenDrain : stm32l1xx_rtc.h
  • RTC_OutputType_PushPull : stm32l1xx_rtc.h
  • RTC_PRER_PREDIV_A : stm32l1xx.h
  • RTC_PRER_PREDIV_S : stm32l1xx.h
  • RTC_RSF_MASK : stm32l1xx_rtc.c
  • RTC_ShiftAdd1S_Reset : stm32l1xx_rtc.h
  • RTC_ShiftAdd1S_Set : stm32l1xx_rtc.h
  • RTC_SHIFTR_ADD1S : stm32l1xx.h
  • RTC_SHIFTR_SUBFS : stm32l1xx.h
  • RTC_SmoothCalibPeriod_16sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPeriod_32sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPeriod_8sec : stm32l1xx_rtc.h
  • RTC_SmoothCalibPlusPulses_Reset : stm32l1xx_rtc.h
  • RTC_SmoothCalibPlusPulses_Set : stm32l1xx_rtc.h
  • RTC_SSR_SS : stm32l1xx.h
  • RTC_StoreOperation_Reset : stm32l1xx_rtc.h
  • RTC_StoreOperation_Set : stm32l1xx_rtc.h
  • RTC_TAFCR_ALARMOUTTYPE : stm32l1xx.h
  • RTC_TAFCR_TAMP1E : stm32l1xx.h
  • RTC_TAFCR_TAMP1TRG : stm32l1xx.h
  • RTC_TAFCR_TAMP2E : stm32l1xx.h
  • RTC_TAFCR_TAMP2TRG : stm32l1xx.h
  • RTC_TAFCR_TAMP3E : stm32l1xx.h
  • RTC_TAFCR_TAMP3TRG : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPFLT_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPFREQ_2 : stm32l1xx.h
  • RTC_TAFCR_TAMPIE : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH_0 : stm32l1xx.h
  • RTC_TAFCR_TAMPPRCH_1 : stm32l1xx.h
  • RTC_TAFCR_TAMPPUDIS : stm32l1xx.h
  • RTC_TAFCR_TAMPTS : stm32l1xx.h
  • RTC_Tamper_1 : stm32l1xx_rtc.h
  • RTC_Tamper_2 : stm32l1xx_rtc.h
  • RTC_Tamper_3 : stm32l1xx_rtc.h
  • RTC_TamperFilter_2Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_4Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_8Sample : stm32l1xx_rtc.h
  • RTC_TamperFilter_Disable : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_1RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_2RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_4RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperPrechargeDuration_8RTCCLK : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div1024 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div16384 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div2048 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div256 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div32768 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div4096 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div512 : stm32l1xx_rtc.h
  • RTC_TamperSamplingFreq_RTCCLK_Div8192 : stm32l1xx_rtc.h
  • RTC_TamperTrigger_FallingEdge : stm32l1xx_rtc.h
  • RTC_TamperTrigger_HighLevel : stm32l1xx_rtc.h
  • RTC_TamperTrigger_LowLevel : stm32l1xx_rtc.h
  • RTC_TamperTrigger_RisingEdge : stm32l1xx_rtc.h
  • RTC_TimeStampEdge_Falling : stm32l1xx_rtc.h
  • RTC_TimeStampEdge_Rising : stm32l1xx_rtc.h
  • RTC_TR_HT : stm32l1xx.h
  • RTC_TR_HT_0 : stm32l1xx.h
  • RTC_TR_HT_1 : stm32l1xx.h
  • RTC_TR_HU : stm32l1xx.h
  • RTC_TR_HU_0 : stm32l1xx.h
  • RTC_TR_HU_1 : stm32l1xx.h
  • RTC_TR_HU_2 : stm32l1xx.h
  • RTC_TR_HU_3 : stm32l1xx.h
  • RTC_TR_MNT : stm32l1xx.h
  • RTC_TR_MNT_0 : stm32l1xx.h
  • RTC_TR_MNT_1 : stm32l1xx.h
  • RTC_TR_MNT_2 : stm32l1xx.h
  • RTC_TR_MNU : stm32l1xx.h
  • RTC_TR_MNU_0 : stm32l1xx.h
  • RTC_TR_MNU_1 : stm32l1xx.h
  • RTC_TR_MNU_2 : stm32l1xx.h
  • RTC_TR_MNU_3 : stm32l1xx.h
  • RTC_TR_PM : stm32l1xx.h
  • RTC_TR_RESERVED_MASK : stm32l1xx_rtc.c
  • RTC_TR_ST : stm32l1xx.h
  • RTC_TR_ST_0 : stm32l1xx.h
  • RTC_TR_ST_1 : stm32l1xx.h
  • RTC_TR_ST_2 : stm32l1xx.h
  • RTC_TR_SU : stm32l1xx.h
  • RTC_TR_SU_0 : stm32l1xx.h
  • RTC_TR_SU_1 : stm32l1xx.h
  • RTC_TR_SU_2 : stm32l1xx.h
  • RTC_TR_SU_3 : stm32l1xx.h
  • RTC_TSDR_DT : stm32l1xx.h
  • RTC_TSDR_DT_0 : stm32l1xx.h
  • RTC_TSDR_DT_1 : stm32l1xx.h
  • RTC_TSDR_DU : stm32l1xx.h
  • RTC_TSDR_DU_0 : stm32l1xx.h
  • RTC_TSDR_DU_1 : stm32l1xx.h
  • RTC_TSDR_DU_2 : stm32l1xx.h
  • RTC_TSDR_DU_3 : stm32l1xx.h
  • RTC_TSDR_MT : stm32l1xx.h
  • RTC_TSDR_MU : stm32l1xx.h
  • RTC_TSDR_MU_0 : stm32l1xx.h
  • RTC_TSDR_MU_1 : stm32l1xx.h
  • RTC_TSDR_MU_2 : stm32l1xx.h
  • RTC_TSDR_MU_3 : stm32l1xx.h
  • RTC_TSDR_WDU : stm32l1xx.h
  • RTC_TSDR_WDU_0 : stm32l1xx.h
  • RTC_TSDR_WDU_1 : stm32l1xx.h
  • RTC_TSDR_WDU_2 : stm32l1xx.h
  • RTC_TSSSR_SS : stm32l1xx.h
  • RTC_TSTR_HT : stm32l1xx.h
  • RTC_TSTR_HT_0 : stm32l1xx.h
  • RTC_TSTR_HT_1 : stm32l1xx.h
  • RTC_TSTR_HU : stm32l1xx.h
  • RTC_TSTR_HU_0 : stm32l1xx.h
  • RTC_TSTR_HU_1 : stm32l1xx.h
  • RTC_TSTR_HU_2 : stm32l1xx.h
  • RTC_TSTR_HU_3 : stm32l1xx.h
  • RTC_TSTR_MNT : stm32l1xx.h
  • RTC_TSTR_MNT_0 : stm32l1xx.h
  • RTC_TSTR_MNT_1 : stm32l1xx.h
  • RTC_TSTR_MNT_2 : stm32l1xx.h
  • RTC_TSTR_MNU : stm32l1xx.h
  • RTC_TSTR_MNU_0 : stm32l1xx.h
  • RTC_TSTR_MNU_1 : stm32l1xx.h
  • RTC_TSTR_MNU_2 : stm32l1xx.h
  • RTC_TSTR_MNU_3 : stm32l1xx.h
  • RTC_TSTR_PM : stm32l1xx.h
  • RTC_TSTR_ST : stm32l1xx.h
  • RTC_TSTR_ST_0 : stm32l1xx.h
  • RTC_TSTR_ST_1 : stm32l1xx.h
  • RTC_TSTR_ST_2 : stm32l1xx.h
  • RTC_TSTR_SU : stm32l1xx.h
  • RTC_TSTR_SU_0 : stm32l1xx.h
  • RTC_TSTR_SU_1 : stm32l1xx.h
  • RTC_TSTR_SU_2 : stm32l1xx.h
  • RTC_TSTR_SU_3 : stm32l1xx.h
  • RTC_WakeUpClock_CK_SPRE_16bits : stm32l1xx_rtc.h
  • RTC_WakeUpClock_CK_SPRE_17bits : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div16 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div2 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div4 : stm32l1xx_rtc.h
  • RTC_WakeUpClock_RTCCLK_Div8 : stm32l1xx_rtc.h
  • RTC_Weekday_Friday : stm32l1xx_rtc.h
  • RTC_Weekday_Monday : stm32l1xx_rtc.h
  • RTC_Weekday_Saturday : stm32l1xx_rtc.h
  • RTC_Weekday_Sunday : stm32l1xx_rtc.h
  • RTC_Weekday_Thursday : stm32l1xx_rtc.h
  • RTC_Weekday_Tuesday : stm32l1xx_rtc.h
  • RTC_Weekday_Wednesday : stm32l1xx_rtc.h
  • RTC_WPR_KEY : stm32l1xx.h
  • RTC_WUTR_WUT : stm32l1xx.h
  • RTCEN_BitNumber : stm32l1xx_rcc.c
  • RTCRST_BitNumber : stm32l1xx_rcc.c
  • RWMOD_BitNumber : stm32l1xx_sdio.c
  • RWSTART_BitNumber : stm32l1xx_sdio.c
  • RWSTOP_BitNumber : stm32l1xx_sdio.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
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- s -

  • SCB_AFSR_IMPDEF : stm32l1xx.h
  • SCB_AIRCR_ENDIANESS : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP0 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP1 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP2 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP3 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP4 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP5 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP6 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP7 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_0 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_1 : stm32l1xx.h
  • SCB_AIRCR_PRIGROUP_2 : stm32l1xx.h
  • SCB_AIRCR_SYSRESETREQ : stm32l1xx.h
  • SCB_AIRCR_VECTCLRACTIVE : stm32l1xx.h
  • SCB_AIRCR_VECTKEY : stm32l1xx.h
  • SCB_AIRCR_VECTRESET : stm32l1xx.h
  • SCB_BFAR_ADDRESS : stm32l1xx.h
  • SCB_CCR_BFHFNMIGN : stm32l1xx.h
  • SCB_CCR_DIV_0_TRP : stm32l1xx.h
  • SCB_CCR_NONBASETHRDENA : stm32l1xx.h
  • SCB_CCR_STKALIGN : stm32l1xx.h
  • SCB_CCR_UNALIGN_TRP : stm32l1xx.h
  • SCB_CCR_USERSETMPEND : stm32l1xx.h
  • SCB_CFSR_BFARVALID : stm32l1xx.h
  • SCB_CFSR_DACCVIOL : stm32l1xx.h
  • SCB_CFSR_DIVBYZERO : stm32l1xx.h
  • SCB_CFSR_IACCVIOL : stm32l1xx.h
  • SCB_CFSR_IBUSERR : stm32l1xx.h
  • SCB_CFSR_IMPRECISERR : stm32l1xx.h
  • SCB_CFSR_INVPC : stm32l1xx.h
  • SCB_CFSR_INVSTATE : stm32l1xx.h
  • SCB_CFSR_MMARVALID : stm32l1xx.h
  • SCB_CFSR_MSTKERR : stm32l1xx.h
  • SCB_CFSR_MUNSTKERR : stm32l1xx.h
  • SCB_CFSR_NOCP : stm32l1xx.h
  • SCB_CFSR_PRECISERR : stm32l1xx.h
  • SCB_CFSR_STKERR : stm32l1xx.h
  • SCB_CFSR_UNALIGNED : stm32l1xx.h
  • SCB_CFSR_UNDEFINSTR : stm32l1xx.h
  • SCB_CFSR_UNSTKERR : stm32l1xx.h
  • SCB_CPUID_Constant : stm32l1xx.h
  • SCB_CPUID_IMPLEMENTER : stm32l1xx.h
  • SCB_CPUID_PARTNO : stm32l1xx.h
  • SCB_CPUID_REVISION : stm32l1xx.h
  • SCB_CPUID_VARIANT : stm32l1xx.h
  • SCB_DFSR_BKPT : stm32l1xx.h
  • SCB_DFSR_DWTTRAP : stm32l1xx.h
  • SCB_DFSR_EXTERNAL : stm32l1xx.h
  • SCB_DFSR_HALTED : stm32l1xx.h
  • SCB_DFSR_VCATCH : stm32l1xx.h
  • SCB_HFSR_DEBUGEVT : stm32l1xx.h
  • SCB_HFSR_FORCED : stm32l1xx.h
  • SCB_HFSR_VECTTBL : stm32l1xx.h
  • SCB_ICSR_ISRPENDING : stm32l1xx.h
  • SCB_ICSR_ISRPREEMPT : stm32l1xx.h
  • SCB_ICSR_NMIPENDSET : stm32l1xx.h
  • SCB_ICSR_PENDSTCLR : stm32l1xx.h
  • SCB_ICSR_PENDSTSET : stm32l1xx.h
  • SCB_ICSR_PENDSVCLR : stm32l1xx.h
  • SCB_ICSR_PENDSVSET : stm32l1xx.h
  • SCB_ICSR_RETTOBASE : stm32l1xx.h
  • SCB_ICSR_VECTACTIVE : stm32l1xx.h
  • SCB_ICSR_VECTPENDING : stm32l1xx.h
  • SCB_MMFAR_ADDRESS : stm32l1xx.h
  • SCB_SCR_SEVONPEND : stm32l1xx.h
  • SCB_SCR_SLEEPDEEP : stm32l1xx.h
  • SCB_SCR_SLEEPONEXIT : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTACT : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTENA : stm32l1xx.h
  • SCB_SHCSR_BUSFAULTPENDED : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTACT : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTENA : stm32l1xx.h
  • SCB_SHCSR_MEMFAULTPENDED : stm32l1xx.h
  • SCB_SHCSR_MONITORACT : stm32l1xx.h
  • SCB_SHCSR_PENDSVACT : stm32l1xx.h
  • SCB_SHCSR_SVCALLACT : stm32l1xx.h
  • SCB_SHCSR_SVCALLPENDED : stm32l1xx.h
  • SCB_SHCSR_SYSTICKACT : stm32l1xx.h
  • SCB_SHCSR_USGFAULTACT : stm32l1xx.h
  • SCB_SHCSR_USGFAULTENA : stm32l1xx.h
  • SCB_SHCSR_USGFAULTPENDED : stm32l1xx.h
  • SCB_SHPR_PRI_N : stm32l1xx.h
  • SCB_SHPR_PRI_N1 : stm32l1xx.h
  • SCB_SHPR_PRI_N2 : stm32l1xx.h
  • SCB_SHPR_PRI_N3 : stm32l1xx.h
  • SCB_VTOR_TBLBASE : stm32l1xx.h
  • SCB_VTOR_TBLOFF : stm32l1xx.h
  • SDIO : stm32l1xx.h
  • SDIO_ARG_CMDARG : stm32l1xx.h
  • SDIO_BASE : stm32l1xx.h
  • SDIO_BusWide_1b : stm32l1xx_sdio.h
  • SDIO_BusWide_4b : stm32l1xx_sdio.h
  • SDIO_BusWide_8b : stm32l1xx_sdio.h
  • SDIO_CLKCR_BYPASS : stm32l1xx.h
  • SDIO_CLKCR_CLKDIV : stm32l1xx.h
  • SDIO_CLKCR_CLKEN : stm32l1xx.h
  • SDIO_CLKCR_HWFC_EN : stm32l1xx.h
  • SDIO_CLKCR_NEGEDGE : stm32l1xx.h
  • SDIO_CLKCR_PWRSAV : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS_0 : stm32l1xx.h
  • SDIO_CLKCR_WIDBUS_1 : stm32l1xx.h
  • SDIO_ClockBypass_Disable : stm32l1xx_sdio.h
  • SDIO_ClockBypass_Enable : stm32l1xx_sdio.h
  • SDIO_ClockEdge_Falling : stm32l1xx_sdio.h
  • SDIO_ClockEdge_Rising : stm32l1xx_sdio.h
  • SDIO_ClockPowerSave_Disable : stm32l1xx_sdio.h
  • SDIO_ClockPowerSave_Enable : stm32l1xx_sdio.h
  • SDIO_CMD_CEATACMD : stm32l1xx.h
  • SDIO_CMD_CMDINDEX : stm32l1xx.h
  • SDIO_CMD_CPSMEN : stm32l1xx.h
  • SDIO_CMD_ENCMDCOMPL : stm32l1xx.h
  • SDIO_CMD_NIEN : stm32l1xx.h
  • SDIO_CMD_SDIOSUSPEND : stm32l1xx.h
  • SDIO_CMD_WAITINT : stm32l1xx.h
  • SDIO_CMD_WAITPEND : stm32l1xx.h
  • SDIO_CMD_WAITRESP : stm32l1xx.h
  • SDIO_CMD_WAITRESP_0 : stm32l1xx.h
  • SDIO_CMD_WAITRESP_1 : stm32l1xx.h
  • SDIO_CPSM_Disable : stm32l1xx_sdio.h
  • SDIO_CPSM_Enable : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_1024b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_128b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_16384b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_16b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_1b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_2048b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_256b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_2b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_32b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_4096b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_4b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_512b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_64b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_8192b : stm32l1xx_sdio.h
  • SDIO_DataBlockSize_8b : stm32l1xx_sdio.h
  • SDIO_DCOUNT_DATACOUNT : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_0 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_1 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_2 : stm32l1xx.h
  • SDIO_DCTRL_DBLOCKSIZE_3 : stm32l1xx.h
  • SDIO_DCTRL_DMAEN : stm32l1xx.h
  • SDIO_DCTRL_DTDIR : stm32l1xx.h
  • SDIO_DCTRL_DTEN : stm32l1xx.h
  • SDIO_DCTRL_DTMODE : stm32l1xx.h
  • SDIO_DCTRL_RWMOD : stm32l1xx.h
  • SDIO_DCTRL_RWSTART : stm32l1xx.h
  • SDIO_DCTRL_RWSTOP : stm32l1xx.h
  • SDIO_DCTRL_SDIOEN : stm32l1xx.h
  • SDIO_DLEN_DATALENGTH : stm32l1xx.h
  • SDIO_DPSM_Disable : stm32l1xx_sdio.h
  • SDIO_DPSM_Enable : stm32l1xx_sdio.h
  • SDIO_DTIMER_DATATIME : stm32l1xx.h
  • SDIO_FIFO_FIFODATA : stm32l1xx.h
  • SDIO_FIFOCNT_FIFOCOUNT : stm32l1xx.h
  • SDIO_FLAG_CCRCFAIL : stm32l1xx_sdio.h
  • SDIO_FLAG_CEATAEND : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDACT : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDREND : stm32l1xx_sdio.h
  • SDIO_FLAG_CMDSENT : stm32l1xx_sdio.h
  • SDIO_FLAG_CTIMEOUT : stm32l1xx_sdio.h
  • SDIO_FLAG_DATAEND : stm32l1xx_sdio.h
  • SDIO_FLAG_DBCKEND : stm32l1xx_sdio.h
  • SDIO_FLAG_DCRCFAIL : stm32l1xx_sdio.h
  • SDIO_FLAG_DTIMEOUT : stm32l1xx_sdio.h
  • SDIO_FLAG_RXACT : stm32l1xx_sdio.h
  • SDIO_FLAG_RXDAVL : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOE : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOF : stm32l1xx_sdio.h
  • SDIO_FLAG_RXFIFOHF : stm32l1xx_sdio.h
  • SDIO_FLAG_RXOVERR : stm32l1xx_sdio.h
  • SDIO_FLAG_SDIOIT : stm32l1xx_sdio.h
  • SDIO_FLAG_STBITERR : stm32l1xx_sdio.h
  • SDIO_FLAG_TXACT : stm32l1xx_sdio.h
  • SDIO_FLAG_TXDAVL : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOE : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOF : stm32l1xx_sdio.h
  • SDIO_FLAG_TXFIFOHE : stm32l1xx_sdio.h
  • SDIO_FLAG_TXUNDERR : stm32l1xx_sdio.h
  • SDIO_HardwareFlowControl_Disable : stm32l1xx_sdio.h
  • SDIO_HardwareFlowControl_Enable : stm32l1xx_sdio.h
  • SDIO_ICR_CCRCFAILC : stm32l1xx.h
  • SDIO_ICR_CEATAENDC : stm32l1xx.h
  • SDIO_ICR_CMDRENDC : stm32l1xx.h
  • SDIO_ICR_CMDSENTC : stm32l1xx.h
  • SDIO_ICR_CTIMEOUTC : stm32l1xx.h
  • SDIO_ICR_DATAENDC : stm32l1xx.h
  • SDIO_ICR_DBCKENDC : stm32l1xx.h
  • SDIO_ICR_DCRCFAILC : stm32l1xx.h
  • SDIO_ICR_DTIMEOUTC : stm32l1xx.h
  • SDIO_ICR_RXOVERRC : stm32l1xx.h
  • SDIO_ICR_SDIOITC : stm32l1xx.h
  • SDIO_ICR_STBITERRC : stm32l1xx.h
  • SDIO_ICR_TXUNDERRC : stm32l1xx.h
  • SDIO_IT_CCRCFAIL : stm32l1xx_sdio.h
  • SDIO_IT_CEATAEND : stm32l1xx_sdio.h
  • SDIO_IT_CMDACT : stm32l1xx_sdio.h
  • SDIO_IT_CMDREND : stm32l1xx_sdio.h
  • SDIO_IT_CMDSENT : stm32l1xx_sdio.h
  • SDIO_IT_CTIMEOUT : stm32l1xx_sdio.h
  • SDIO_IT_DATAEND : stm32l1xx_sdio.h
  • SDIO_IT_DBCKEND : stm32l1xx_sdio.h
  • SDIO_IT_DCRCFAIL : stm32l1xx_sdio.h
  • SDIO_IT_DTIMEOUT : stm32l1xx_sdio.h
  • SDIO_IT_RXACT : stm32l1xx_sdio.h
  • SDIO_IT_RXDAVL : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOE : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOF : stm32l1xx_sdio.h
  • SDIO_IT_RXFIFOHF : stm32l1xx_sdio.h
  • SDIO_IT_RXOVERR : stm32l1xx_sdio.h
  • SDIO_IT_SDIOIT : stm32l1xx_sdio.h
  • SDIO_IT_STBITERR : stm32l1xx_sdio.h
  • SDIO_IT_TXACT : stm32l1xx_sdio.h
  • SDIO_IT_TXDAVL : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOE : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOF : stm32l1xx_sdio.h
  • SDIO_IT_TXFIFOHE : stm32l1xx_sdio.h
  • SDIO_IT_TXUNDERR : stm32l1xx_sdio.h
  • SDIO_MASK_CCRCFAILIE : stm32l1xx.h
  • SDIO_MASK_CEATAENDIE : stm32l1xx.h
  • SDIO_MASK_CMDACTIE : stm32l1xx.h
  • SDIO_MASK_CMDRENDIE : stm32l1xx.h
  • SDIO_MASK_CMDSENTIE : stm32l1xx.h
  • SDIO_MASK_CTIMEOUTIE : stm32l1xx.h
  • SDIO_MASK_DATAENDIE : stm32l1xx.h
  • SDIO_MASK_DBCKENDIE : stm32l1xx.h
  • SDIO_MASK_DCRCFAILIE : stm32l1xx.h
  • SDIO_MASK_DTIMEOUTIE : stm32l1xx.h
  • SDIO_MASK_RXACTIE : stm32l1xx.h
  • SDIO_MASK_RXDAVLIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOEIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOFIE : stm32l1xx.h
  • SDIO_MASK_RXFIFOHFIE : stm32l1xx.h
  • SDIO_MASK_RXOVERRIE : stm32l1xx.h
  • SDIO_MASK_SDIOITIE : stm32l1xx.h
  • SDIO_MASK_STBITERRIE : stm32l1xx.h
  • SDIO_MASK_TXACTIE : stm32l1xx.h
  • SDIO_MASK_TXDAVLIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOEIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOFIE : stm32l1xx.h
  • SDIO_MASK_TXFIFOHEIE : stm32l1xx.h
  • SDIO_MASK_TXUNDERRIE : stm32l1xx.h
  • SDIO_OFFSET : stm32l1xx_sdio.c
  • SDIO_POWER_PWRCTRL : stm32l1xx.h
  • SDIO_POWER_PWRCTRL_0 : stm32l1xx.h
  • SDIO_POWER_PWRCTRL_1 : stm32l1xx.h
  • SDIO_PowerState_OFF : stm32l1xx_sdio.h
  • SDIO_PowerState_ON : stm32l1xx_sdio.h
  • SDIO_ReadWaitMode_CLK : stm32l1xx_sdio.h
  • SDIO_ReadWaitMode_DATA2 : stm32l1xx_sdio.h
  • SDIO_RESP0_CARDSTATUS0 : stm32l1xx.h
  • SDIO_RESP1 : stm32l1xx_sdio.h
  • SDIO_RESP1_CARDSTATUS1 : stm32l1xx.h
  • SDIO_RESP2 : stm32l1xx_sdio.h
  • SDIO_RESP2_CARDSTATUS2 : stm32l1xx.h
  • SDIO_RESP3 : stm32l1xx_sdio.h
  • SDIO_RESP3_CARDSTATUS3 : stm32l1xx.h
  • SDIO_RESP4 : stm32l1xx_sdio.h
  • SDIO_RESP4_CARDSTATUS4 : stm32l1xx.h
  • SDIO_RESP_ADDR : stm32l1xx_sdio.c
  • SDIO_RESPCMD_RESPCMD : stm32l1xx.h
  • SDIO_Response_Long : stm32l1xx_sdio.h
  • SDIO_Response_No : stm32l1xx_sdio.h
  • SDIO_Response_Short : stm32l1xx_sdio.h
  • SDIO_STA_CCRCFAIL : stm32l1xx.h
  • SDIO_STA_CEATAEND : stm32l1xx.h
  • SDIO_STA_CMDACT : stm32l1xx.h
  • SDIO_STA_CMDREND : stm32l1xx.h
  • SDIO_STA_CMDSENT : stm32l1xx.h
  • SDIO_STA_CTIMEOUT : stm32l1xx.h
  • SDIO_STA_DATAEND : stm32l1xx.h
  • SDIO_STA_DBCKEND : stm32l1xx.h
  • SDIO_STA_DCRCFAIL : stm32l1xx.h
  • SDIO_STA_DTIMEOUT : stm32l1xx.h
  • SDIO_STA_RXACT : stm32l1xx.h
  • SDIO_STA_RXDAVL : stm32l1xx.h
  • SDIO_STA_RXFIFOE : stm32l1xx.h
  • SDIO_STA_RXFIFOF : stm32l1xx.h
  • SDIO_STA_RXFIFOHF : stm32l1xx.h
  • SDIO_STA_RXOVERR : stm32l1xx.h
  • SDIO_STA_SDIOIT : stm32l1xx.h
  • SDIO_STA_STBITERR : stm32l1xx.h
  • SDIO_STA_TXACT : stm32l1xx.h
  • SDIO_STA_TXDAVL : stm32l1xx.h
  • SDIO_STA_TXFIFOE : stm32l1xx.h
  • SDIO_STA_TXFIFOF : stm32l1xx.h
  • SDIO_STA_TXFIFOHE : stm32l1xx.h
  • SDIO_STA_TXUNDERR : stm32l1xx.h
  • SDIO_TransferDir_ToCard : stm32l1xx_sdio.h
  • SDIO_TransferDir_ToSDIO : stm32l1xx_sdio.h
  • SDIO_TransferMode_Block : stm32l1xx_sdio.h
  • SDIO_TransferMode_Stream : stm32l1xx_sdio.h
  • SDIO_Wait_IT : stm32l1xx_sdio.h
  • SDIO_Wait_No : stm32l1xx_sdio.h
  • SDIO_Wait_Pend : stm32l1xx_sdio.h
  • SDIOEN_BitNumber : stm32l1xx_sdio.c
  • SDIOSUSPEND_BitNumber : stm32l1xx_sdio.c
  • SET_BIT : stm32l1xx.h
  • SHPF_TIMEOUT : stm32l1xx_rtc.c
  • SMCR_ETR_MASK : stm32l1xx_tim.c
  • SMPR0_SMP_SET : stm32l1xx_adc.c
  • SMPR1_SMP_SET : stm32l1xx_adc.c
  • SMPR2_SMP_SET : stm32l1xx_adc.c
  • SMPR3_SMP_SET : stm32l1xx_adc.c
  • SPI1 : stm32l1xx.h
  • SPI1_BASE : stm32l1xx.h
  • SPI2 : stm32l1xx.h
  • SPI2_BASE : stm32l1xx.h
  • SPI3 : stm32l1xx.h
  • SPI3_BASE : stm32l1xx.h
  • SPI_BaudRatePrescaler_128 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_16 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_2 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_256 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_32 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_4 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_64 : stm32l1xx_spi.h
  • SPI_BaudRatePrescaler_8 : stm32l1xx_spi.h
  • SPI_ClearFlag : stm32l1xx_spi.h
  • SPI_ClearITPendingBit : stm32l1xx_spi.h
  • SPI_CPHA_1Edge : stm32l1xx_spi.h
  • SPI_CPHA_2Edge : stm32l1xx_spi.h
  • SPI_CPOL_High : stm32l1xx_spi.h
  • SPI_CPOL_Low : stm32l1xx_spi.h
  • SPI_CR1_BIDIMODE : stm32l1xx.h
  • SPI_CR1_BIDIOE : stm32l1xx.h
  • SPI_CR1_BR : stm32l1xx.h
  • SPI_CR1_BR_0 : stm32l1xx.h
  • SPI_CR1_BR_1 : stm32l1xx.h
  • SPI_CR1_BR_2 : stm32l1xx.h
  • SPI_CR1_CPHA : stm32l1xx.h
  • SPI_CR1_CPOL : stm32l1xx.h
  • SPI_CR1_CRCEN : stm32l1xx.h
  • SPI_CR1_CRCNEXT : stm32l1xx.h
  • SPI_CR1_DFF : stm32l1xx.h
  • SPI_CR1_LSBFIRST : stm32l1xx.h
  • SPI_CR1_MSTR : stm32l1xx.h
  • SPI_CR1_RXONLY : stm32l1xx.h
  • SPI_CR1_SPE : stm32l1xx.h
  • SPI_CR1_SSI : stm32l1xx.h
  • SPI_CR1_SSM : stm32l1xx.h
  • SPI_CR2_ERRIE : stm32l1xx.h
  • SPI_CR2_FRF : stm32l1xx.h
  • SPI_CR2_RXDMAEN : stm32l1xx.h
  • SPI_CR2_RXNEIE : stm32l1xx.h
  • SPI_CR2_SSOE : stm32l1xx.h
  • SPI_CR2_TXDMAEN : stm32l1xx.h
  • SPI_CR2_TXEIE : stm32l1xx.h
  • SPI_CRC_Rx : stm32l1xx_spi.h
  • SPI_CRC_Tx : stm32l1xx_spi.h
  • SPI_CRCPR_CRCPOLY : stm32l1xx.h
  • SPI_DataSize_16b : stm32l1xx_spi.h
  • SPI_DataSize_8b : stm32l1xx_spi.h
  • SPI_DeInit : stm32l1xx_spi.h
  • SPI_Direction_1Line_Rx : stm32l1xx_spi.h
  • SPI_Direction_1Line_Tx : stm32l1xx_spi.h
  • SPI_Direction_2Lines_FullDuplex : stm32l1xx_spi.h
  • SPI_Direction_2Lines_RxOnly : stm32l1xx_spi.h
  • SPI_Direction_Rx : stm32l1xx_spi.h
  • SPI_Direction_Tx : stm32l1xx_spi.h
  • SPI_DMACmd : stm32l1xx_spi.h
  • SPI_DMAReq_Rx : stm32l1xx_spi.h
  • SPI_DMAReq_Tx : stm32l1xx_spi.h
  • SPI_DR_DR : stm32l1xx.h
  • SPI_FirstBit_LSB : stm32l1xx_spi.h
  • SPI_FirstBit_MSB : stm32l1xx_spi.h
  • SPI_FLAG_BSY : stm32l1xx_spi.h
  • SPI_FLAG_CRCERR : stm32l1xx_spi.h
  • SPI_FLAG_MODF : stm32l1xx_spi.h
  • SPI_FLAG_OVR : stm32l1xx_spi.h
  • SPI_FLAG_RXNE : stm32l1xx_spi.h
  • SPI_FLAG_TXE : stm32l1xx_spi.h
  • SPI_GetFlagStatus : stm32l1xx_spi.h
  • SPI_GetITStatus : stm32l1xx_spi.h
  • SPI_I2S_DMAReq_Rx : stm32l1xx_spi.h
  • SPI_I2S_DMAReq_Tx : stm32l1xx_spi.h
  • SPI_I2S_FLAG_BSY : stm32l1xx_spi.h
  • SPI_I2S_FLAG_FRE : stm32l1xx_spi.h
  • SPI_I2S_FLAG_OVR : stm32l1xx_spi.h
  • SPI_I2S_FLAG_RXNE : stm32l1xx_spi.h
  • SPI_I2S_FLAG_TXE : stm32l1xx_spi.h
  • SPI_I2S_IT_ERR : stm32l1xx_spi.h
  • SPI_I2S_IT_FRE : stm32l1xx_spi.h
  • SPI_I2S_IT_OVR : stm32l1xx_spi.h
  • SPI_I2S_IT_RXNE : stm32l1xx_spi.h
  • SPI_I2S_IT_TXE : stm32l1xx_spi.h
  • SPI_I2SCFGR_CHLEN : stm32l1xx.h
  • SPI_I2SCFGR_CKPOL : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN_0 : stm32l1xx.h
  • SPI_I2SCFGR_DATLEN_1 : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG_0 : stm32l1xx.h
  • SPI_I2SCFGR_I2SCFG_1 : stm32l1xx.h
  • SPI_I2SCFGR_I2SE : stm32l1xx.h
  • SPI_I2SCFGR_I2SMOD : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD_0 : stm32l1xx.h
  • SPI_I2SCFGR_I2SSTD_1 : stm32l1xx.h
  • SPI_I2SCFGR_PCMSYNC : stm32l1xx.h
  • SPI_I2SPR_I2SDIV : stm32l1xx.h
  • SPI_I2SPR_MCKOE : stm32l1xx.h
  • SPI_I2SPR_ODD : stm32l1xx.h
  • SPI_IT_CRCERR : stm32l1xx_spi.h
  • SPI_IT_ERR : stm32l1xx_spi.h
  • SPI_IT_MODF : stm32l1xx_spi.h
  • SPI_IT_OVR : stm32l1xx_spi.h
  • SPI_IT_RXNE : stm32l1xx_spi.h
  • SPI_IT_TXE : stm32l1xx_spi.h
  • SPI_ITConfig : stm32l1xx_spi.h
  • SPI_Mode_Master : stm32l1xx_spi.h
  • SPI_Mode_Slave : stm32l1xx_spi.h
  • SPI_NSS_Hard : stm32l1xx_spi.h
  • SPI_NSS_Soft : stm32l1xx_spi.h
  • SPI_NSSInternalSoft_Reset : stm32l1xx_spi.h
  • SPI_NSSInternalSoft_Set : stm32l1xx_spi.h
  • SPI_ReceiveData : stm32l1xx_spi.h
  • SPI_RXCRCR_RXCRC : stm32l1xx.h
  • SPI_SendData : stm32l1xx_spi.h
  • SPI_SR_BSY : stm32l1xx.h
  • SPI_SR_CHSIDE : stm32l1xx.h
  • SPI_SR_CRCERR : stm32l1xx.h
  • SPI_SR_MODF : stm32l1xx.h
  • SPI_SR_OVR : stm32l1xx.h
  • SPI_SR_RXNE : stm32l1xx.h
  • SPI_SR_TXE : stm32l1xx.h
  • SPI_SR_UDR : stm32l1xx.h
  • SPI_TXCRCR_TXCRC : stm32l1xx.h
  • SQR1_L_RESET : stm32l1xx_adc.c
  • SQR1_SQ_SET : stm32l1xx_adc.c
  • SQR2_SQ_SET : stm32l1xx_adc.c
  • SQR3_SQ_SET : stm32l1xx_adc.c
  • SQR4_SQ_SET : stm32l1xx_adc.c
  • SQR5_SQ_SET : stm32l1xx_adc.c
  • SR_OFFSET : stm32l1xx_lcd.c
  • SR_UDR_BB : stm32l1xx_lcd.c
  • SRAM_BASE : stm32l1xx.h
  • SRAM_BB_BASE : stm32l1xx.h
  • STM32L1XX_HD : stm32l1xx.h
  • SYNCHRO_TIMEOUT : stm32l1xx_rtc.c
  • SYSCFG : stm32l1xx.h
  • SYSCFG_BASE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI0_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI1_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PG : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI2_PH : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3 : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PA : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PB : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PC : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PD : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PE : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PF : stm32l1xx.h
  • SYSCFG_EXTICR1_EXTI3_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI4_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI5_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI6_PG : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7 : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PA : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PB : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PC : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PD : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PE : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PF : stm32l1xx.h
  • SYSCFG_EXTICR2_EXTI7_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI10_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI11_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI8_PG : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9 : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PA : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PB : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PC : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PD : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PE : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PF : stm32l1xx.h
  • SYSCFG_EXTICR3_EXTI9_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI12_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI13_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI14_PG : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15 : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PA : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PB : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PC : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PD : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PE : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PF : stm32l1xx.h
  • SYSCFG_EXTICR4_EXTI15_PG : stm32l1xx.h
  • SYSCFG_MemoryRemap_Flash : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_FSMC : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_SRAM : stm32l1xx_syscfg.h
  • SYSCFG_MemoryRemap_SystemFlash : stm32l1xx_syscfg.h
  • SYSCFG_MEMRMP_BOOT_MODE : stm32l1xx.h
  • SYSCFG_MEMRMP_BOOT_MODE_0 : stm32l1xx.h
  • SYSCFG_MEMRMP_BOOT_MODE_1 : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE_0 : stm32l1xx.h
  • SYSCFG_MEMRMP_MEM_MODE_1 : stm32l1xx.h
  • SYSCFG_PMC_USB_PU : stm32l1xx.h
  • SysTick_CALIB_NOREF : stm32l1xx.h
  • SysTick_CALIB_SKEW : stm32l1xx.h
  • SysTick_CALIB_TENMS : stm32l1xx.h
  • SysTick_CLKSource_HCLK : misc.h
  • SysTick_CLKSource_HCLK_Div8 : misc.h
  • SysTick_CTRL_CLKSOURCE : stm32l1xx.h
  • SysTick_CTRL_COUNTFLAG : stm32l1xx.h
  • SysTick_CTRL_ENABLE : stm32l1xx.h
  • SysTick_CTRL_TICKINT : stm32l1xx.h
  • SysTick_LOAD_RELOAD : stm32l1xx.h
  • SysTick_VAL_CURRENT : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- t -

  • TIM10 : stm32l1xx.h
  • TIM10_BASE : stm32l1xx.h
  • TIM10_ETR_LSE : stm32l1xx_tim.h
  • TIM10_ETR_TIM9_TRGO : stm32l1xx_tim.h
  • TIM10_GPIO : stm32l1xx_tim.h
  • TIM10_LSE : stm32l1xx_tim.h
  • TIM10_LSI : stm32l1xx_tim.h
  • TIM10_RI : stm32l1xx_tim.h
  • TIM10_RTC : stm32l1xx_tim.h
  • TIM11 : stm32l1xx.h
  • TIM11_BASE : stm32l1xx.h
  • TIM11_ETR_LSE : stm32l1xx_tim.h
  • TIM11_ETR_TIM9_TRGO : stm32l1xx_tim.h
  • TIM11_GPIO : stm32l1xx_tim.h
  • TIM11_HSE_RTC : stm32l1xx_tim.h
  • TIM11_MSI : stm32l1xx_tim.h
  • TIM11_RI : stm32l1xx_tim.h
  • TIM2 : stm32l1xx.h
  • TIM2_BASE : stm32l1xx.h
  • TIM2_TIM10_OC : stm32l1xx_tim.h
  • TIM2_TIM5_TRGO : stm32l1xx_tim.h
  • TIM3 : stm32l1xx.h
  • TIM3_BASE : stm32l1xx.h
  • TIM3_TIM11_OC : stm32l1xx_tim.h
  • TIM3_TIM5_TRGO : stm32l1xx_tim.h
  • TIM4 : stm32l1xx.h
  • TIM4_BASE : stm32l1xx.h
  • TIM5 : stm32l1xx.h
  • TIM5_BASE : stm32l1xx.h
  • TIM6 : stm32l1xx.h
  • TIM6_BASE : stm32l1xx.h
  • TIM7 : stm32l1xx.h
  • TIM7_BASE : stm32l1xx.h
  • TIM9 : stm32l1xx.h
  • TIM9_BASE : stm32l1xx.h
  • TIM9_GPIO : stm32l1xx_tim.h
  • TIM9_LSE : stm32l1xx_tim.h
  • TIM9_TIM3_TRGO : stm32l1xx_tim.h
  • TIM9_TS_IO : stm32l1xx_tim.h
  • TIM_ARR_ARR : stm32l1xx.h
  • TIM_CCER_CC1E : stm32l1xx.h
  • TIM_CCER_CC1NP : stm32l1xx.h
  • TIM_CCER_CC1P : stm32l1xx.h
  • TIM_CCER_CC2E : stm32l1xx.h
  • TIM_CCER_CC2NP : stm32l1xx.h
  • TIM_CCER_CC2P : stm32l1xx.h
  • TIM_CCER_CC3E : stm32l1xx.h
  • TIM_CCER_CC3NP : stm32l1xx.h
  • TIM_CCER_CC3P : stm32l1xx.h
  • TIM_CCER_CC4E : stm32l1xx.h
  • TIM_CCER_CC4NP : stm32l1xx.h
  • TIM_CCER_CC4P : stm32l1xx.h
  • TIM_CCMR1_CC1S : stm32l1xx.h
  • TIM_CCMR1_CC1S_0 : stm32l1xx.h
  • TIM_CCMR1_CC1S_1 : stm32l1xx.h
  • TIM_CCMR1_CC2S : stm32l1xx.h
  • TIM_CCMR1_CC2S_0 : stm32l1xx.h
  • TIM_CCMR1_CC2S_1 : stm32l1xx.h
  • TIM_CCMR1_IC1F : stm32l1xx.h
  • TIM_CCMR1_IC1F_0 : stm32l1xx.h
  • TIM_CCMR1_IC1F_1 : stm32l1xx.h
  • TIM_CCMR1_IC1F_2 : stm32l1xx.h
  • TIM_CCMR1_IC1F_3 : stm32l1xx.h
  • TIM_CCMR1_IC1PSC : stm32l1xx.h
  • TIM_CCMR1_IC1PSC_0 : stm32l1xx.h
  • TIM_CCMR1_IC1PSC_1 : stm32l1xx.h
  • TIM_CCMR1_IC2F : stm32l1xx.h
  • TIM_CCMR1_IC2F_0 : stm32l1xx.h
  • TIM_CCMR1_IC2F_1 : stm32l1xx.h
  • TIM_CCMR1_IC2F_2 : stm32l1xx.h
  • TIM_CCMR1_IC2F_3 : stm32l1xx.h
  • TIM_CCMR1_IC2PSC : stm32l1xx.h
  • TIM_CCMR1_IC2PSC_0 : stm32l1xx.h
  • TIM_CCMR1_IC2PSC_1 : stm32l1xx.h
  • TIM_CCMR1_OC1CE : stm32l1xx.h
  • TIM_CCMR1_OC1FE : stm32l1xx.h
  • TIM_CCMR1_OC1M : stm32l1xx.h
  • TIM_CCMR1_OC1M_0 : stm32l1xx.h
  • TIM_CCMR1_OC1M_1 : stm32l1xx.h
  • TIM_CCMR1_OC1M_2 : stm32l1xx.h
  • TIM_CCMR1_OC1PE : stm32l1xx.h
  • TIM_CCMR1_OC2CE : stm32l1xx.h
  • TIM_CCMR1_OC2FE : stm32l1xx.h
  • TIM_CCMR1_OC2M : stm32l1xx.h
  • TIM_CCMR1_OC2M_0 : stm32l1xx.h
  • TIM_CCMR1_OC2M_1 : stm32l1xx.h
  • TIM_CCMR1_OC2M_2 : stm32l1xx.h
  • TIM_CCMR1_OC2PE : stm32l1xx.h
  • TIM_CCMR2_CC3S : stm32l1xx.h
  • TIM_CCMR2_CC3S_0 : stm32l1xx.h
  • TIM_CCMR2_CC3S_1 : stm32l1xx.h
  • TIM_CCMR2_CC4S : stm32l1xx.h
  • TIM_CCMR2_CC4S_0 : stm32l1xx.h
  • TIM_CCMR2_CC4S_1 : stm32l1xx.h
  • TIM_CCMR2_IC3F : stm32l1xx.h
  • TIM_CCMR2_IC3F_0 : stm32l1xx.h
  • TIM_CCMR2_IC3F_1 : stm32l1xx.h
  • TIM_CCMR2_IC3F_2 : stm32l1xx.h
  • TIM_CCMR2_IC3F_3 : stm32l1xx.h
  • TIM_CCMR2_IC3PSC : stm32l1xx.h
  • TIM_CCMR2_IC3PSC_0 : stm32l1xx.h
  • TIM_CCMR2_IC3PSC_1 : stm32l1xx.h
  • TIM_CCMR2_IC4F : stm32l1xx.h
  • TIM_CCMR2_IC4F_0 : stm32l1xx.h
  • TIM_CCMR2_IC4F_1 : stm32l1xx.h
  • TIM_CCMR2_IC4F_2 : stm32l1xx.h
  • TIM_CCMR2_IC4F_3 : stm32l1xx.h
  • TIM_CCMR2_IC4PSC : stm32l1xx.h
  • TIM_CCMR2_IC4PSC_0 : stm32l1xx.h
  • TIM_CCMR2_IC4PSC_1 : stm32l1xx.h
  • TIM_CCMR2_OC3CE : stm32l1xx.h
  • TIM_CCMR2_OC3FE : stm32l1xx.h
  • TIM_CCMR2_OC3M : stm32l1xx.h
  • TIM_CCMR2_OC3M_0 : stm32l1xx.h
  • TIM_CCMR2_OC3M_1 : stm32l1xx.h
  • TIM_CCMR2_OC3M_2 : stm32l1xx.h
  • TIM_CCMR2_OC3PE : stm32l1xx.h
  • TIM_CCMR2_OC4CE : stm32l1xx.h
  • TIM_CCMR2_OC4FE : stm32l1xx.h
  • TIM_CCMR2_OC4M : stm32l1xx.h
  • TIM_CCMR2_OC4M_0 : stm32l1xx.h
  • TIM_CCMR2_OC4M_1 : stm32l1xx.h
  • TIM_CCMR2_OC4M_2 : stm32l1xx.h
  • TIM_CCMR2_OC4PE : stm32l1xx.h
  • TIM_CCR1_CCR1 : stm32l1xx.h
  • TIM_CCR2_CCR2 : stm32l1xx.h
  • TIM_CCR3_CCR3 : stm32l1xx.h
  • TIM_CCR4_CCR4 : stm32l1xx.h
  • TIM_CCx_Disable : stm32l1xx_tim.h
  • TIM_CCx_Enable : stm32l1xx_tim.h
  • TIM_Channel_1 : stm32l1xx_tim.h
  • TIM_Channel_2 : stm32l1xx_tim.h
  • TIM_Channel_3 : stm32l1xx_tim.h
  • TIM_Channel_4 : stm32l1xx_tim.h
  • TIM_CKD_DIV1 : stm32l1xx_tim.h
  • TIM_CKD_DIV2 : stm32l1xx_tim.h
  • TIM_CKD_DIV4 : stm32l1xx_tim.h
  • TIM_CNT_CNT : stm32l1xx.h
  • TIM_CounterMode_CenterAligned1 : stm32l1xx_tim.h
  • TIM_CounterMode_CenterAligned2 : stm32l1xx_tim.h
  • TIM_CounterMode_CenterAligned3 : stm32l1xx_tim.h
  • TIM_CounterMode_Down : stm32l1xx_tim.h
  • TIM_CounterMode_Up : stm32l1xx_tim.h
  • TIM_CR1_ARPE : stm32l1xx.h
  • TIM_CR1_CEN : stm32l1xx.h
  • TIM_CR1_CKD : stm32l1xx.h
  • TIM_CR1_CKD_0 : stm32l1xx.h
  • TIM_CR1_CKD_1 : stm32l1xx.h
  • TIM_CR1_CMS : stm32l1xx.h
  • TIM_CR1_CMS_0 : stm32l1xx.h
  • TIM_CR1_CMS_1 : stm32l1xx.h
  • TIM_CR1_DIR : stm32l1xx.h
  • TIM_CR1_OPM : stm32l1xx.h
  • TIM_CR1_UDIS : stm32l1xx.h
  • TIM_CR1_URS : stm32l1xx.h
  • TIM_CR2_CCDS : stm32l1xx.h
  • TIM_CR2_MMS : stm32l1xx.h
  • TIM_CR2_MMS_0 : stm32l1xx.h
  • TIM_CR2_MMS_1 : stm32l1xx.h
  • TIM_CR2_MMS_2 : stm32l1xx.h
  • TIM_CR2_TI1S : stm32l1xx.h
  • TIM_DCR_DBA : stm32l1xx.h
  • TIM_DCR_DBA_0 : stm32l1xx.h
  • TIM_DCR_DBA_1 : stm32l1xx.h
  • TIM_DCR_DBA_2 : stm32l1xx.h
  • TIM_DCR_DBA_3 : stm32l1xx.h
  • TIM_DCR_DBA_4 : stm32l1xx.h
  • TIM_DCR_DBL : stm32l1xx.h
  • TIM_DCR_DBL_0 : stm32l1xx.h
  • TIM_DCR_DBL_1 : stm32l1xx.h
  • TIM_DCR_DBL_2 : stm32l1xx.h
  • TIM_DCR_DBL_3 : stm32l1xx.h
  • TIM_DCR_DBL_4 : stm32l1xx.h
  • TIM_DIER_CC1DE : stm32l1xx.h
  • TIM_DIER_CC1IE : stm32l1xx.h
  • TIM_DIER_CC2DE : stm32l1xx.h
  • TIM_DIER_CC2IE : stm32l1xx.h
  • TIM_DIER_CC3DE : stm32l1xx.h
  • TIM_DIER_CC3IE : stm32l1xx.h
  • TIM_DIER_CC4DE : stm32l1xx.h
  • TIM_DIER_CC4IE : stm32l1xx.h
  • TIM_DIER_TDE : stm32l1xx.h
  • TIM_DIER_TIE : stm32l1xx.h
  • TIM_DIER_UDE : stm32l1xx.h
  • TIM_DIER_UIE : stm32l1xx.h
  • TIM_DMA_CC1 : stm32l1xx_tim.h
  • TIM_DMA_CC2 : stm32l1xx_tim.h
  • TIM_DMA_CC3 : stm32l1xx_tim.h
  • TIM_DMA_CC4 : stm32l1xx_tim.h
  • TIM_DMA_Trigger : stm32l1xx_tim.h
  • TIM_DMA_Update : stm32l1xx_tim.h
  • TIM_DMABase_ARR : stm32l1xx_tim.h
  • TIM_DMABase_CCER : stm32l1xx_tim.h
  • TIM_DMABase_CCMR1 : stm32l1xx_tim.h
  • TIM_DMABase_CCMR2 : stm32l1xx_tim.h
  • TIM_DMABase_CCR1 : stm32l1xx_tim.h
  • TIM_DMABase_CCR2 : stm32l1xx_tim.h
  • TIM_DMABase_CCR3 : stm32l1xx_tim.h
  • TIM_DMABase_CCR4 : stm32l1xx_tim.h
  • TIM_DMABase_CNT : stm32l1xx_tim.h
  • TIM_DMABase_CR1 : stm32l1xx_tim.h
  • TIM_DMABase_CR2 : stm32l1xx_tim.h
  • TIM_DMABase_DCR : stm32l1xx_tim.h
  • TIM_DMABase_DIER : stm32l1xx_tim.h
  • TIM_DMABase_EGR : stm32l1xx_tim.h
  • TIM_DMABase_OR : stm32l1xx_tim.h
  • TIM_DMABase_PSC : stm32l1xx_tim.h
  • TIM_DMABase_SMCR : stm32l1xx_tim.h
  • TIM_DMABase_SR : stm32l1xx_tim.h
  • TIM_DMABurstLength_10Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_10Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_11Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_11Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_12Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_12Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_13Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_13Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_14Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_14Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_15Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_15Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_16Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_16Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_17Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_17Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_18Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_18Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_1Byte : stm32l1xx_tim.h
  • TIM_DMABurstLength_1Transfer : stm32l1xx_tim.h
  • TIM_DMABurstLength_2Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_2Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_3Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_3Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_4Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_4Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_5Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_5Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_6Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_6Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_7Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_7Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_8Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_8Transfers : stm32l1xx_tim.h
  • TIM_DMABurstLength_9Bytes : stm32l1xx_tim.h
  • TIM_DMABurstLength_9Transfers : stm32l1xx_tim.h
  • TIM_DMAR_DMAB : stm32l1xx.h
  • TIM_EGR_CC1G : stm32l1xx.h
  • TIM_EGR_CC2G : stm32l1xx.h
  • TIM_EGR_CC3G : stm32l1xx.h
  • TIM_EGR_CC4G : stm32l1xx.h
  • TIM_EGR_TG : stm32l1xx.h
  • TIM_EGR_UG : stm32l1xx.h
  • TIM_EncoderMode_TI1 : stm32l1xx_tim.h
  • TIM_EncoderMode_TI12 : stm32l1xx_tim.h
  • TIM_EncoderMode_TI2 : stm32l1xx_tim.h
  • TIM_EventSource_CC1 : stm32l1xx_tim.h
  • TIM_EventSource_CC2 : stm32l1xx_tim.h
  • TIM_EventSource_CC3 : stm32l1xx_tim.h
  • TIM_EventSource_CC4 : stm32l1xx_tim.h
  • TIM_EventSource_Trigger : stm32l1xx_tim.h
  • TIM_EventSource_Update : stm32l1xx_tim.h
  • TIM_ExtTRGPolarity_Inverted : stm32l1xx_tim.h
  • TIM_ExtTRGPolarity_NonInverted : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV2 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV4 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_DIV8 : stm32l1xx_tim.h
  • TIM_ExtTRGPSC_OFF : stm32l1xx_tim.h
  • TIM_FLAG_CC1 : stm32l1xx_tim.h
  • TIM_FLAG_CC1OF : stm32l1xx_tim.h
  • TIM_FLAG_CC2 : stm32l1xx_tim.h
  • TIM_FLAG_CC2OF : stm32l1xx_tim.h
  • TIM_FLAG_CC3 : stm32l1xx_tim.h
  • TIM_FLAG_CC3OF : stm32l1xx_tim.h
  • TIM_FLAG_CC4 : stm32l1xx_tim.h
  • TIM_FLAG_CC4OF : stm32l1xx_tim.h
  • TIM_FLAG_Trigger : stm32l1xx_tim.h
  • TIM_FLAG_Update : stm32l1xx_tim.h
  • TIM_ForcedAction_Active : stm32l1xx_tim.h
  • TIM_ForcedAction_InActive : stm32l1xx_tim.h
  • TIM_ICPolarity_BothEdge : stm32l1xx_tim.h
  • TIM_ICPolarity_Falling : stm32l1xx_tim.h
  • TIM_ICPolarity_Rising : stm32l1xx_tim.h
  • TIM_ICPSC_DIV1 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV2 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV4 : stm32l1xx_tim.h
  • TIM_ICPSC_DIV8 : stm32l1xx_tim.h
  • TIM_ICSelection_DirectTI : stm32l1xx_tim.h
  • TIM_ICSelection_IndirectTI : stm32l1xx_tim.h
  • TIM_ICSelection_TRC : stm32l1xx_tim.h
  • TIM_IT_CC1 : stm32l1xx_tim.h
  • TIM_IT_CC2 : stm32l1xx_tim.h
  • TIM_IT_CC3 : stm32l1xx_tim.h
  • TIM_IT_CC4 : stm32l1xx_tim.h
  • TIM_IT_Trigger : stm32l1xx_tim.h
  • TIM_IT_Update : stm32l1xx_tim.h
  • TIM_MasterSlaveMode_Disable : stm32l1xx_tim.h
  • TIM_MasterSlaveMode_Enable : stm32l1xx_tim.h
  • TIM_OCClear_Disable : stm32l1xx_tim.h
  • TIM_OCClear_Enable : stm32l1xx_tim.h
  • TIM_OCFast_Disable : stm32l1xx_tim.h
  • TIM_OCFast_Enable : stm32l1xx_tim.h
  • TIM_OCMode_Active : stm32l1xx_tim.h
  • TIM_OCMode_Inactive : stm32l1xx_tim.h
  • TIM_OCMode_PWM1 : stm32l1xx_tim.h
  • TIM_OCMode_PWM2 : stm32l1xx_tim.h
  • TIM_OCMode_Timing : stm32l1xx_tim.h
  • TIM_OCMode_Toggle : stm32l1xx_tim.h
  • TIM_OCPolarity_High : stm32l1xx_tim.h
  • TIM_OCPolarity_Low : stm32l1xx_tim.h
  • TIM_OCPreload_Disable : stm32l1xx_tim.h
  • TIM_OCPreload_Enable : stm32l1xx_tim.h
  • TIM_OCREFERENCECECLEAR_SOURCE : stm32l1xx_tim.h
  • TIM_OCReferenceClear_ETRF : stm32l1xx_tim.h
  • TIM_OCReferenceClear_OCREFCLR : stm32l1xx_tim.h
  • TIM_OPMode_Repetitive : stm32l1xx_tim.h
  • TIM_OPMode_Single : stm32l1xx_tim.h
  • TIM_OR_TI1RMP : stm32l1xx.h
  • TIM_OR_TI1RMP_0 : stm32l1xx.h
  • TIM_OR_TI1RMP_1 : stm32l1xx.h
  • TIM_OutputState_Disable : stm32l1xx_tim.h
  • TIM_OutputState_Enable : stm32l1xx_tim.h
  • TIM_PSC_PSC : stm32l1xx.h
  • TIM_PSCReloadMode_Immediate : stm32l1xx_tim.h
  • TIM_PSCReloadMode_Update : stm32l1xx_tim.h
  • TIM_SELECT_MASK : stm32l1xx_syscfg.c
  • TIM_Select_None : stm32l1xx_syscfg.h
  • TIM_Select_TIM2 : stm32l1xx_syscfg.h
  • TIM_Select_TIM3 : stm32l1xx_syscfg.h
  • TIM_Select_TIM4 : stm32l1xx_syscfg.h
  • TIM_SlaveMode_External1 : stm32l1xx_tim.h
  • TIM_SlaveMode_Gated : stm32l1xx_tim.h
  • TIM_SlaveMode_Reset : stm32l1xx_tim.h
  • TIM_SlaveMode_Trigger : stm32l1xx_tim.h
  • TIM_SMCR_ECE : stm32l1xx.h
  • TIM_SMCR_ETF : stm32l1xx.h
  • TIM_SMCR_ETF_0 : stm32l1xx.h
  • TIM_SMCR_ETF_1 : stm32l1xx.h
  • TIM_SMCR_ETF_2 : stm32l1xx.h
  • TIM_SMCR_ETF_3 : stm32l1xx.h
  • TIM_SMCR_ETP : stm32l1xx.h
  • TIM_SMCR_ETPS : stm32l1xx.h
  • TIM_SMCR_ETPS_0 : stm32l1xx.h
  • TIM_SMCR_ETPS_1 : stm32l1xx.h
  • TIM_SMCR_MSM : stm32l1xx.h
  • TIM_SMCR_OCCS : stm32l1xx.h
  • TIM_SMCR_SMS : stm32l1xx.h
  • TIM_SMCR_SMS_0 : stm32l1xx.h
  • TIM_SMCR_SMS_1 : stm32l1xx.h
  • TIM_SMCR_SMS_2 : stm32l1xx.h
  • TIM_SMCR_TS : stm32l1xx.h
  • TIM_SMCR_TS_0 : stm32l1xx.h
  • TIM_SMCR_TS_1 : stm32l1xx.h
  • TIM_SMCR_TS_2 : stm32l1xx.h
  • TIM_SR_CC1IF : stm32l1xx.h
  • TIM_SR_CC1OF : stm32l1xx.h
  • TIM_SR_CC2IF : stm32l1xx.h
  • TIM_SR_CC2OF : stm32l1xx.h
  • TIM_SR_CC3IF : stm32l1xx.h
  • TIM_SR_CC3OF : stm32l1xx.h
  • TIM_SR_CC4IF : stm32l1xx.h
  • TIM_SR_CC4OF : stm32l1xx.h
  • TIM_SR_TIF : stm32l1xx.h
  • TIM_SR_UIF : stm32l1xx.h
  • TIM_TIxExternalCLK1Source_TI1 : stm32l1xx_tim.h
  • TIM_TIxExternalCLK1Source_TI1ED : stm32l1xx_tim.h
  • TIM_TIxExternalCLK1Source_TI2 : stm32l1xx_tim.h
  • TIM_TRGOSource_Enable : stm32l1xx_tim.h
  • TIM_TRGOSource_OC1 : stm32l1xx_tim.h
  • TIM_TRGOSource_OC1Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC2Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC3Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_OC4Ref : stm32l1xx_tim.h
  • TIM_TRGOSource_Reset : stm32l1xx_tim.h
  • TIM_TRGOSource_Update : stm32l1xx_tim.h
  • TIM_TS_ETRF : stm32l1xx_tim.h
  • TIM_TS_ITR0 : stm32l1xx_tim.h
  • TIM_TS_ITR1 : stm32l1xx_tim.h
  • TIM_TS_ITR2 : stm32l1xx_tim.h
  • TIM_TS_ITR3 : stm32l1xx_tim.h
  • TIM_TS_TI1F_ED : stm32l1xx_tim.h
  • TIM_TS_TI1FP1 : stm32l1xx_tim.h
  • TIM_TS_TI2FP2 : stm32l1xx_tim.h
  • TIM_UpdateSource_Global : stm32l1xx_tim.h
  • TIM_UpdateSource_Regular : stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- u -

  • UART4 : stm32l1xx.h
  • UART4_BASE : stm32l1xx.h
  • UART5 : stm32l1xx.h
  • UART5_BASE : stm32l1xx.h
  • UDR_BitNumber : stm32l1xx_lcd.c
  • ULP_BitNumber : stm32l1xx_pwr.c
  • USART1 : stm32l1xx.h
  • USART1_BASE : stm32l1xx.h
  • USART2 : stm32l1xx.h
  • USART2_BASE : stm32l1xx.h
  • USART3 : stm32l1xx.h
  • USART3_BASE : stm32l1xx.h
  • USART_BRR_DIV_FRACTION : stm32l1xx.h
  • USART_BRR_DIV_MANTISSA : stm32l1xx.h
  • USART_Clock_Disable : stm32l1xx_usart.h
  • USART_Clock_Enable : stm32l1xx_usart.h
  • USART_CPHA_1Edge : stm32l1xx_usart.h
  • USART_CPHA_2Edge : stm32l1xx_usart.h
  • USART_CPOL_High : stm32l1xx_usart.h
  • USART_CPOL_Low : stm32l1xx_usart.h
  • USART_CR1_IDLEIE : stm32l1xx.h
  • USART_CR1_M : stm32l1xx.h
  • USART_CR1_OVER8 : stm32l1xx.h
  • USART_CR1_PCE : stm32l1xx.h
  • USART_CR1_PEIE : stm32l1xx.h
  • USART_CR1_PS : stm32l1xx.h
  • USART_CR1_RE : stm32l1xx.h
  • USART_CR1_RWU : stm32l1xx.h
  • USART_CR1_RXNEIE : stm32l1xx.h
  • USART_CR1_SBK : stm32l1xx.h
  • USART_CR1_TCIE : stm32l1xx.h
  • USART_CR1_TE : stm32l1xx.h
  • USART_CR1_TXEIE : stm32l1xx.h
  • USART_CR1_UE : stm32l1xx.h
  • USART_CR1_WAKE : stm32l1xx.h
  • USART_CR2_ADD : stm32l1xx.h
  • USART_CR2_CLKEN : stm32l1xx.h
  • USART_CR2_CPHA : stm32l1xx.h
  • USART_CR2_CPOL : stm32l1xx.h
  • USART_CR2_LBCL : stm32l1xx.h
  • USART_CR2_LBDIE : stm32l1xx.h
  • USART_CR2_LBDL : stm32l1xx.h
  • USART_CR2_LINEN : stm32l1xx.h
  • USART_CR2_STOP : stm32l1xx.h
  • USART_CR2_STOP_0 : stm32l1xx.h
  • USART_CR2_STOP_1 : stm32l1xx.h
  • USART_CR3_CTSE : stm32l1xx.h
  • USART_CR3_CTSIE : stm32l1xx.h
  • USART_CR3_DMAR : stm32l1xx.h
  • USART_CR3_DMAT : stm32l1xx.h
  • USART_CR3_EIE : stm32l1xx.h
  • USART_CR3_HDSEL : stm32l1xx.h
  • USART_CR3_IREN : stm32l1xx.h
  • USART_CR3_IRLP : stm32l1xx.h
  • USART_CR3_NACK : stm32l1xx.h
  • USART_CR3_ONEBIT : stm32l1xx.h
  • USART_CR3_RTSE : stm32l1xx.h
  • USART_CR3_SCEN : stm32l1xx.h
  • USART_DMAReq_Rx : stm32l1xx_usart.h
  • USART_DMAReq_Tx : stm32l1xx_usart.h
  • USART_DR_DR : stm32l1xx.h
  • USART_FLAG_CTS : stm32l1xx_usart.h
  • USART_FLAG_FE : stm32l1xx_usart.h
  • USART_FLAG_IDLE : stm32l1xx_usart.h
  • USART_FLAG_LBD : stm32l1xx_usart.h
  • USART_FLAG_NE : stm32l1xx_usart.h
  • USART_FLAG_ORE : stm32l1xx_usart.h
  • USART_FLAG_PE : stm32l1xx_usart.h
  • USART_FLAG_RXNE : stm32l1xx_usart.h
  • USART_FLAG_TC : stm32l1xx_usart.h
  • USART_FLAG_TXE : stm32l1xx_usart.h
  • USART_GTPR_GT : stm32l1xx.h
  • USART_GTPR_PSC : stm32l1xx.h
  • USART_GTPR_PSC_0 : stm32l1xx.h
  • USART_GTPR_PSC_1 : stm32l1xx.h
  • USART_GTPR_PSC_2 : stm32l1xx.h
  • USART_GTPR_PSC_3 : stm32l1xx.h
  • USART_GTPR_PSC_4 : stm32l1xx.h
  • USART_GTPR_PSC_5 : stm32l1xx.h
  • USART_GTPR_PSC_6 : stm32l1xx.h
  • USART_GTPR_PSC_7 : stm32l1xx.h
  • USART_HardwareFlowControl_CTS : stm32l1xx_usart.h
  • USART_HardwareFlowControl_None : stm32l1xx_usart.h
  • USART_HardwareFlowControl_RTS : stm32l1xx_usart.h
  • USART_HardwareFlowControl_RTS_CTS : stm32l1xx_usart.h
  • USART_IrDAMode_LowPower : stm32l1xx_usart.h
  • USART_IrDAMode_Normal : stm32l1xx_usart.h
  • USART_IT_CTS : stm32l1xx_usart.h
  • USART_IT_ERR : stm32l1xx_usart.h
  • USART_IT_FE : stm32l1xx_usart.h
  • USART_IT_IDLE : stm32l1xx_usart.h
  • USART_IT_LBD : stm32l1xx_usart.h
  • USART_IT_NE : stm32l1xx_usart.h
  • USART_IT_ORE : stm32l1xx_usart.h
  • USART_IT_ORE_ER : stm32l1xx_usart.h
  • USART_IT_ORE_RX : stm32l1xx_usart.h
  • USART_IT_PE : stm32l1xx_usart.h
  • USART_IT_RXNE : stm32l1xx_usart.h
  • USART_IT_TC : stm32l1xx_usart.h
  • USART_IT_TXE : stm32l1xx_usart.h
  • USART_LastBit_Disable : stm32l1xx_usart.h
  • USART_LastBit_Enable : stm32l1xx_usart.h
  • USART_LINBreakDetectLength_10b : stm32l1xx_usart.h
  • USART_LINBreakDetectLength_11b : stm32l1xx_usart.h
  • USART_Mode_Rx : stm32l1xx_usart.h
  • USART_Mode_Tx : stm32l1xx_usart.h
  • USART_Parity_Even : stm32l1xx_usart.h
  • USART_Parity_No : stm32l1xx_usart.h
  • USART_Parity_Odd : stm32l1xx_usart.h
  • USART_SR_CTS : stm32l1xx.h
  • USART_SR_FE : stm32l1xx.h
  • USART_SR_IDLE : stm32l1xx.h
  • USART_SR_LBD : stm32l1xx.h
  • USART_SR_NE : stm32l1xx.h
  • USART_SR_ORE : stm32l1xx.h
  • USART_SR_PE : stm32l1xx.h
  • USART_SR_RXNE : stm32l1xx.h
  • USART_SR_TC : stm32l1xx.h
  • USART_SR_TXE : stm32l1xx.h
  • USART_StopBits_0_5 : stm32l1xx_usart.h
  • USART_StopBits_1 : stm32l1xx_usart.h
  • USART_StopBits_1_5 : stm32l1xx_usart.h
  • USART_StopBits_2 : stm32l1xx_usart.h
  • USART_WakeUp_AddressMark : stm32l1xx_usart.h
  • USART_WakeUp_IdleLine : stm32l1xx_usart.h
  • USART_WordLength_8b : stm32l1xx_usart.h
  • USART_WordLength_9b : stm32l1xx_usart.h
  • USB_ADDR0_RX_ADDR0_RX : stm32l1xx.h
  • USB_ADDR0_TX_ADDR0_TX : stm32l1xx.h
  • USB_ADDR1_RX_ADDR1_RX : stm32l1xx.h
  • USB_ADDR1_TX_ADDR1_TX : stm32l1xx.h
  • USB_ADDR2_RX_ADDR2_RX : stm32l1xx.h
  • USB_ADDR2_TX_ADDR2_TX : stm32l1xx.h
  • USB_ADDR3_RX_ADDR3_RX : stm32l1xx.h
  • USB_ADDR3_TX_ADDR3_TX : stm32l1xx.h
  • USB_ADDR4_RX_ADDR4_RX : stm32l1xx.h
  • USB_ADDR4_TX_ADDR4_TX : stm32l1xx.h
  • USB_ADDR5_RX_ADDR5_RX : stm32l1xx.h
  • USB_ADDR5_TX_ADDR5_TX : stm32l1xx.h
  • USB_ADDR6_RX_ADDR6_RX : stm32l1xx.h
  • USB_ADDR6_TX_ADDR6_TX : stm32l1xx.h
  • USB_ADDR7_RX_ADDR7_RX : stm32l1xx.h
  • USB_ADDR7_TX_ADDR7_TX : stm32l1xx.h
  • USB_BTABLE_BTABLE : stm32l1xx.h
  • USB_CNTR_CTRM : stm32l1xx.h
  • USB_CNTR_ERRM : stm32l1xx.h
  • USB_CNTR_ESOFM : stm32l1xx.h
  • USB_CNTR_FRES : stm32l1xx.h
  • USB_CNTR_FSUSP : stm32l1xx.h
  • USB_CNTR_LP_MODE : stm32l1xx.h
  • USB_CNTR_PDWN : stm32l1xx.h
  • USB_CNTR_PMAOVRM : stm32l1xx.h
  • USB_CNTR_RESETM : stm32l1xx.h
  • USB_CNTR_RESUME : stm32l1xx.h
  • USB_CNTR_SOFM : stm32l1xx.h
  • USB_CNTR_SUSPM : stm32l1xx.h
  • USB_CNTR_WKUPM : stm32l1xx.h
  • USB_COUNT0_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_COUNT0_RX_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT0_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_COUNT0_RX_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT0_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT0_RX_COUNT0_RX : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT0_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT0_TX_0_COUNT0_TX_0 : stm32l1xx.h
  • USB_COUNT0_TX_1_COUNT0_TX_1 : stm32l1xx.h
  • USB_COUNT0_TX_COUNT0_TX : stm32l1xx.h
  • USB_COUNT1_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_COUNT1_RX_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT1_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_COUNT1_RX_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT1_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT1_RX_COUNT1_RX : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT1_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT1_TX_0_COUNT1_TX_0 : stm32l1xx.h
  • USB_COUNT1_TX_1_COUNT1_TX_1 : stm32l1xx.h
  • USB_COUNT1_TX_COUNT1_TX : stm32l1xx.h
  • USB_COUNT2_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_COUNT2_RX_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT2_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_COUNT2_RX_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT2_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT2_RX_COUNT2_RX : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT2_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT2_TX_0_COUNT2_TX_0 : stm32l1xx.h
  • USB_COUNT2_TX_1_COUNT2_TX_1 : stm32l1xx.h
  • USB_COUNT2_TX_COUNT2_TX : stm32l1xx.h
  • USB_COUNT3_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_COUNT3_RX_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT3_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_COUNT3_RX_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT3_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT3_RX_COUNT3_RX : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT3_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT3_TX_0_COUNT3_TX_0 : stm32l1xx.h
  • USB_COUNT3_TX_1_COUNT3_TX_1 : stm32l1xx.h
  • USB_COUNT3_TX_COUNT3_TX : stm32l1xx.h
  • USB_COUNT4_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_COUNT4_RX_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT4_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_COUNT4_RX_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT4_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT4_RX_COUNT4_RX : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT4_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT4_TX_0_COUNT4_TX_0 : stm32l1xx.h
  • USB_COUNT4_TX_1_COUNT4_TX_1 : stm32l1xx.h
  • USB_COUNT4_TX_COUNT4_TX : stm32l1xx.h
  • USB_COUNT5_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_COUNT5_RX_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT5_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_COUNT5_RX_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT5_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT5_RX_COUNT5_RX : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT5_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT5_TX_0_COUNT5_TX_0 : stm32l1xx.h
  • USB_COUNT5_TX_1_COUNT5_TX_1 : stm32l1xx.h
  • USB_COUNT5_TX_COUNT5_TX : stm32l1xx.h
  • USB_COUNT6_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_COUNT6_RX_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT6_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_COUNT6_RX_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT6_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT6_RX_COUNT6_RX : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT6_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT6_TX_0_COUNT6_TX_0 : stm32l1xx.h
  • USB_COUNT6_TX_1_COUNT6_TX_1 : stm32l1xx.h
  • USB_COUNT6_TX_COUNT6_TX : stm32l1xx.h
  • USB_COUNT7_RX_0_BLSIZE_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_COUNT7_RX_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_0 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_1 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_2 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_3 : stm32l1xx.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_4 : stm32l1xx.h
  • USB_COUNT7_RX_1_BLSIZE_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_COUNT7_RX_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_0 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_1 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_2 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_3 : stm32l1xx.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_4 : stm32l1xx.h
  • USB_COUNT7_RX_BLSIZE : stm32l1xx.h
  • USB_COUNT7_RX_COUNT7_RX : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_0 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_1 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_2 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_3 : stm32l1xx.h
  • USB_COUNT7_RX_NUM_BLOCK_4 : stm32l1xx.h
  • USB_COUNT7_TX_0_COUNT7_TX_0 : stm32l1xx.h
  • USB_COUNT7_TX_1_COUNT7_TX_1 : stm32l1xx.h
  • USB_COUNT7_TX_COUNT7_TX : stm32l1xx.h
  • USB_DADDR_ADD : stm32l1xx.h
  • USB_DADDR_ADD0 : stm32l1xx.h
  • USB_DADDR_ADD1 : stm32l1xx.h
  • USB_DADDR_ADD2 : stm32l1xx.h
  • USB_DADDR_ADD3 : stm32l1xx.h
  • USB_DADDR_ADD4 : stm32l1xx.h
  • USB_DADDR_ADD5 : stm32l1xx.h
  • USB_DADDR_ADD6 : stm32l1xx.h
  • USB_DADDR_EF : stm32l1xx.h
  • USB_EP0R_CTR_RX : stm32l1xx.h
  • USB_EP0R_CTR_TX : stm32l1xx.h
  • USB_EP0R_DTOG_RX : stm32l1xx.h
  • USB_EP0R_DTOG_TX : stm32l1xx.h
  • USB_EP0R_EA : stm32l1xx.h
  • USB_EP0R_EP_KIND : stm32l1xx.h
  • USB_EP0R_EP_TYPE : stm32l1xx.h
  • USB_EP0R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP0R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP0R_SETUP : stm32l1xx.h
  • USB_EP0R_STAT_RX : stm32l1xx.h
  • USB_EP0R_STAT_RX_0 : stm32l1xx.h
  • USB_EP0R_STAT_RX_1 : stm32l1xx.h
  • USB_EP0R_STAT_TX : stm32l1xx.h
  • USB_EP0R_STAT_TX_0 : stm32l1xx.h
  • USB_EP0R_STAT_TX_1 : stm32l1xx.h
  • USB_EP1R_CTR_RX : stm32l1xx.h
  • USB_EP1R_CTR_TX : stm32l1xx.h
  • USB_EP1R_DTOG_RX : stm32l1xx.h
  • USB_EP1R_DTOG_TX : stm32l1xx.h
  • USB_EP1R_EA : stm32l1xx.h
  • USB_EP1R_EP_KIND : stm32l1xx.h
  • USB_EP1R_EP_TYPE : stm32l1xx.h
  • USB_EP1R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP1R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP1R_SETUP : stm32l1xx.h
  • USB_EP1R_STAT_RX : stm32l1xx.h
  • USB_EP1R_STAT_RX_0 : stm32l1xx.h
  • USB_EP1R_STAT_RX_1 : stm32l1xx.h
  • USB_EP1R_STAT_TX : stm32l1xx.h
  • USB_EP1R_STAT_TX_0 : stm32l1xx.h
  • USB_EP1R_STAT_TX_1 : stm32l1xx.h
  • USB_EP2R_CTR_RX : stm32l1xx.h
  • USB_EP2R_CTR_TX : stm32l1xx.h
  • USB_EP2R_DTOG_RX : stm32l1xx.h
  • USB_EP2R_DTOG_TX : stm32l1xx.h
  • USB_EP2R_EA : stm32l1xx.h
  • USB_EP2R_EP_KIND : stm32l1xx.h
  • USB_EP2R_EP_TYPE : stm32l1xx.h
  • USB_EP2R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP2R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP2R_SETUP : stm32l1xx.h
  • USB_EP2R_STAT_RX : stm32l1xx.h
  • USB_EP2R_STAT_RX_0 : stm32l1xx.h
  • USB_EP2R_STAT_RX_1 : stm32l1xx.h
  • USB_EP2R_STAT_TX : stm32l1xx.h
  • USB_EP2R_STAT_TX_0 : stm32l1xx.h
  • USB_EP2R_STAT_TX_1 : stm32l1xx.h
  • USB_EP3R_CTR_RX : stm32l1xx.h
  • USB_EP3R_CTR_TX : stm32l1xx.h
  • USB_EP3R_DTOG_RX : stm32l1xx.h
  • USB_EP3R_DTOG_TX : stm32l1xx.h
  • USB_EP3R_EA : stm32l1xx.h
  • USB_EP3R_EP_KIND : stm32l1xx.h
  • USB_EP3R_EP_TYPE : stm32l1xx.h
  • USB_EP3R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP3R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP3R_SETUP : stm32l1xx.h
  • USB_EP3R_STAT_RX : stm32l1xx.h
  • USB_EP3R_STAT_RX_0 : stm32l1xx.h
  • USB_EP3R_STAT_RX_1 : stm32l1xx.h
  • USB_EP3R_STAT_TX : stm32l1xx.h
  • USB_EP3R_STAT_TX_0 : stm32l1xx.h
  • USB_EP3R_STAT_TX_1 : stm32l1xx.h
  • USB_EP4R_CTR_RX : stm32l1xx.h
  • USB_EP4R_CTR_TX : stm32l1xx.h
  • USB_EP4R_DTOG_RX : stm32l1xx.h
  • USB_EP4R_DTOG_TX : stm32l1xx.h
  • USB_EP4R_EA : stm32l1xx.h
  • USB_EP4R_EP_KIND : stm32l1xx.h
  • USB_EP4R_EP_TYPE : stm32l1xx.h
  • USB_EP4R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP4R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP4R_SETUP : stm32l1xx.h
  • USB_EP4R_STAT_RX : stm32l1xx.h
  • USB_EP4R_STAT_RX_0 : stm32l1xx.h
  • USB_EP4R_STAT_RX_1 : stm32l1xx.h
  • USB_EP4R_STAT_TX : stm32l1xx.h
  • USB_EP4R_STAT_TX_0 : stm32l1xx.h
  • USB_EP4R_STAT_TX_1 : stm32l1xx.h
  • USB_EP5R_CTR_RX : stm32l1xx.h
  • USB_EP5R_CTR_TX : stm32l1xx.h
  • USB_EP5R_DTOG_RX : stm32l1xx.h
  • USB_EP5R_DTOG_TX : stm32l1xx.h
  • USB_EP5R_EA : stm32l1xx.h
  • USB_EP5R_EP_KIND : stm32l1xx.h
  • USB_EP5R_EP_TYPE : stm32l1xx.h
  • USB_EP5R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP5R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP5R_SETUP : stm32l1xx.h
  • USB_EP5R_STAT_RX : stm32l1xx.h
  • USB_EP5R_STAT_RX_0 : stm32l1xx.h
  • USB_EP5R_STAT_RX_1 : stm32l1xx.h
  • USB_EP5R_STAT_TX : stm32l1xx.h
  • USB_EP5R_STAT_TX_0 : stm32l1xx.h
  • USB_EP5R_STAT_TX_1 : stm32l1xx.h
  • USB_EP6R_CTR_RX : stm32l1xx.h
  • USB_EP6R_CTR_TX : stm32l1xx.h
  • USB_EP6R_DTOG_RX : stm32l1xx.h
  • USB_EP6R_DTOG_TX : stm32l1xx.h
  • USB_EP6R_EA : stm32l1xx.h
  • USB_EP6R_EP_KIND : stm32l1xx.h
  • USB_EP6R_EP_TYPE : stm32l1xx.h
  • USB_EP6R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP6R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP6R_SETUP : stm32l1xx.h
  • USB_EP6R_STAT_RX : stm32l1xx.h
  • USB_EP6R_STAT_RX_0 : stm32l1xx.h
  • USB_EP6R_STAT_RX_1 : stm32l1xx.h
  • USB_EP6R_STAT_TX : stm32l1xx.h
  • USB_EP6R_STAT_TX_0 : stm32l1xx.h
  • USB_EP6R_STAT_TX_1 : stm32l1xx.h
  • USB_EP7R_CTR_RX : stm32l1xx.h
  • USB_EP7R_CTR_TX : stm32l1xx.h
  • USB_EP7R_DTOG_RX : stm32l1xx.h
  • USB_EP7R_DTOG_TX : stm32l1xx.h
  • USB_EP7R_EA : stm32l1xx.h
  • USB_EP7R_EP_KIND : stm32l1xx.h
  • USB_EP7R_EP_TYPE : stm32l1xx.h
  • USB_EP7R_EP_TYPE_0 : stm32l1xx.h
  • USB_EP7R_EP_TYPE_1 : stm32l1xx.h
  • USB_EP7R_SETUP : stm32l1xx.h
  • USB_EP7R_STAT_RX : stm32l1xx.h
  • USB_EP7R_STAT_RX_0 : stm32l1xx.h
  • USB_EP7R_STAT_RX_1 : stm32l1xx.h
  • USB_EP7R_STAT_TX : stm32l1xx.h
  • USB_EP7R_STAT_TX_0 : stm32l1xx.h
  • USB_EP7R_STAT_TX_1 : stm32l1xx.h
  • USB_FNR_FN : stm32l1xx.h
  • USB_FNR_LCK : stm32l1xx.h
  • USB_FNR_LSOF : stm32l1xx.h
  • USB_FNR_RXDM : stm32l1xx.h
  • USB_FNR_RXDP : stm32l1xx.h
  • USB_ISTR_CTR : stm32l1xx.h
  • USB_ISTR_DIR : stm32l1xx.h
  • USB_ISTR_EP_ID : stm32l1xx.h
  • USB_ISTR_ERR : stm32l1xx.h
  • USB_ISTR_ESOF : stm32l1xx.h
  • USB_ISTR_PMAOVR : stm32l1xx.h
  • USB_ISTR_RESET : stm32l1xx.h
  • USB_ISTR_SOF : stm32l1xx.h
  • USB_ISTR_SUSP : stm32l1xx.h
  • USB_ISTR_WKUP : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
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  • a
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- v -

  • VECT_TAB_OFFSET : system_stm32l1xx.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
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  • d
  • e
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  • g
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- w -

  • WRITE_REG : stm32l1xx.h
  • WRP01_MASK : stm32l1xx_flash.c
  • WRP1011_MASK : stm32l1xx_flash.c
  • WRP23_MASK : stm32l1xx_flash.c
  • WRP45_MASK : stm32l1xx_flash.c
  • WRP67_MASK : stm32l1xx_flash.c
  • WRP89_MASK : stm32l1xx_flash.c
  • WWDG : stm32l1xx.h
  • WWDG_BASE : stm32l1xx.h
  • WWDG_CFR_EWI : stm32l1xx.h
  • WWDG_CFR_W : stm32l1xx.h
  • WWDG_CFR_W0 : stm32l1xx.h
  • WWDG_CFR_W1 : stm32l1xx.h
  • WWDG_CFR_W2 : stm32l1xx.h
  • WWDG_CFR_W3 : stm32l1xx.h
  • WWDG_CFR_W4 : stm32l1xx.h
  • WWDG_CFR_W5 : stm32l1xx.h
  • WWDG_CFR_W6 : stm32l1xx.h
  • WWDG_CFR_WDGTB : stm32l1xx.h
  • WWDG_CFR_WDGTB0 : stm32l1xx.h
  • WWDG_CFR_WDGTB1 : stm32l1xx.h
  • WWDG_CR_T : stm32l1xx.h
  • WWDG_CR_T0 : stm32l1xx.h
  • WWDG_CR_T1 : stm32l1xx.h
  • WWDG_CR_T2 : stm32l1xx.h
  • WWDG_CR_T3 : stm32l1xx.h
  • WWDG_CR_T4 : stm32l1xx.h
  • WWDG_CR_T5 : stm32l1xx.h
  • WWDG_CR_T6 : stm32l1xx.h
  • WWDG_CR_WDGA : stm32l1xx.h
  • WWDG_OFFSET : stm32l1xx_wwdg.c
  • WWDG_Prescaler_1 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_2 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_4 : stm32l1xx_wwdg.h
  • WWDG_Prescaler_8 : stm32l1xx_wwdg.h
  • WWDG_SR_EWIF : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • BitAction : stm32l1xx_gpio.h
  • ErrorStatus : stm32l1xx.h
  • EXTIMode_TypeDef : stm32l1xx_exti.h
  • EXTITrigger_TypeDef : stm32l1xx_exti.h
  • FlagStatus : stm32l1xx.h
  • FLASH_Status : stm32l1xx_flash.h
  • FunctionalState : stm32l1xx.h
  • GPIOMode_TypeDef : stm32l1xx_gpio.h
  • GPIOOType_TypeDef : stm32l1xx_gpio.h
  • GPIOPuPd_TypeDef : stm32l1xx_gpio.h
  • GPIOSpeed_TypeDef : stm32l1xx_gpio.h
  • IRQn : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
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- a -

  • ADC1_IRQn : stm32l1xx.h
  • AES_IRQn : stm32l1xx.h

- b -

  • Bit_RESET : stm32l1xx_gpio.h
  • Bit_SET : stm32l1xx_gpio.h
  • BusFault_IRQn : stm32l1xx.h

- c -

  • COMP_ACQ_IRQn : stm32l1xx.h
  • COMP_IRQn : stm32l1xx.h

- d -

  • DAC_IRQn : stm32l1xx.h
  • DebugMonitor_IRQn : stm32l1xx.h
  • DISABLE : stm32l1xx.h
  • DMA1_Channel1_IRQn : stm32l1xx.h
  • DMA1_Channel2_IRQn : stm32l1xx.h
  • DMA1_Channel3_IRQn : stm32l1xx.h
  • DMA1_Channel4_IRQn : stm32l1xx.h
  • DMA1_Channel5_IRQn : stm32l1xx.h
  • DMA1_Channel6_IRQn : stm32l1xx.h
  • DMA1_Channel7_IRQn : stm32l1xx.h
  • DMA2_Channel1_IRQn : stm32l1xx.h
  • DMA2_Channel2_IRQn : stm32l1xx.h
  • DMA2_Channel3_IRQn : stm32l1xx.h
  • DMA2_Channel4_IRQn : stm32l1xx.h
  • DMA2_Channel5_IRQn : stm32l1xx.h

- e -

  • ENABLE : stm32l1xx.h
  • ERROR : stm32l1xx.h
  • EXTI0_IRQn : stm32l1xx.h
  • EXTI15_10_IRQn : stm32l1xx.h
  • EXTI1_IRQn : stm32l1xx.h
  • EXTI2_IRQn : stm32l1xx.h
  • EXTI3_IRQn : stm32l1xx.h
  • EXTI4_IRQn : stm32l1xx.h
  • EXTI9_5_IRQn : stm32l1xx.h
  • EXTI_Mode_Event : stm32l1xx_exti.h
  • EXTI_Mode_Interrupt : stm32l1xx_exti.h
  • EXTI_Trigger_Falling : stm32l1xx_exti.h
  • EXTI_Trigger_Rising : stm32l1xx_exti.h
  • EXTI_Trigger_Rising_Falling : stm32l1xx_exti.h

- f -

  • FLASH_BUSY : stm32l1xx_flash.h
  • FLASH_COMPLETE : stm32l1xx_flash.h
  • FLASH_ERROR_PROGRAM : stm32l1xx_flash.h
  • FLASH_ERROR_WRP : stm32l1xx_flash.h
  • FLASH_IRQn : stm32l1xx.h
  • FLASH_TIMEOUT : stm32l1xx_flash.h

- g -

  • GPIO_Mode_AF : stm32l1xx_gpio.h
  • GPIO_Mode_AN : stm32l1xx_gpio.h
  • GPIO_Mode_IN : stm32l1xx_gpio.h
  • GPIO_Mode_OUT : stm32l1xx_gpio.h
  • GPIO_OType_OD : stm32l1xx_gpio.h
  • GPIO_OType_PP : stm32l1xx_gpio.h
  • GPIO_PuPd_DOWN : stm32l1xx_gpio.h
  • GPIO_PuPd_NOPULL : stm32l1xx_gpio.h
  • GPIO_PuPd_UP : stm32l1xx_gpio.h
  • GPIO_Speed_10MHz : stm32l1xx_gpio.h
  • GPIO_Speed_2MHz : stm32l1xx_gpio.h
  • GPIO_Speed_400KHz : stm32l1xx_gpio.h
  • GPIO_Speed_40MHz : stm32l1xx_gpio.h

- i -

  • I2C1_ER_IRQn : stm32l1xx.h
  • I2C1_EV_IRQn : stm32l1xx.h
  • I2C2_ER_IRQn : stm32l1xx.h
  • I2C2_EV_IRQn : stm32l1xx.h

- l -

  • LCD_IRQn : stm32l1xx.h

- m -

  • MemoryManagement_IRQn : stm32l1xx.h

- n -

  • NonMaskableInt_IRQn : stm32l1xx.h

- p -

  • PendSV_IRQn : stm32l1xx.h
  • PVD_IRQn : stm32l1xx.h

- r -

  • RCC_IRQn : stm32l1xx.h
  • RESET : stm32l1xx.h
  • RTC_Alarm_IRQn : stm32l1xx.h
  • RTC_WKUP_IRQn : stm32l1xx.h

- s -

  • SDIO_IRQn : stm32l1xx.h
  • SET : stm32l1xx.h
  • SPI1_IRQn : stm32l1xx.h
  • SPI2_IRQn : stm32l1xx.h
  • SPI3_IRQn : stm32l1xx.h
  • SUCCESS : stm32l1xx.h
  • SVC_IRQn : stm32l1xx.h
  • SysTick_IRQn : stm32l1xx.h

- t -

  • TAMPER_STAMP_IRQn : stm32l1xx.h
  • TIM10_IRQn : stm32l1xx.h
  • TIM11_IRQn : stm32l1xx.h
  • TIM2_IRQn : stm32l1xx.h
  • TIM3_IRQn : stm32l1xx.h
  • TIM4_IRQn : stm32l1xx.h
  • TIM5_IRQn : stm32l1xx.h
  • TIM6_IRQn : stm32l1xx.h
  • TIM7_IRQn : stm32l1xx.h
  • TIM9_IRQn : stm32l1xx.h

- u -

  • UART4_IRQn : stm32l1xx.h
  • UART5_IRQn : stm32l1xx.h
  • UsageFault_IRQn : stm32l1xx.h
  • USART1_IRQn : stm32l1xx.h
  • USART2_IRQn : stm32l1xx.h
  • USART3_IRQn : stm32l1xx.h
  • USB_FS_WKUP_IRQn : stm32l1xx.h
  • USB_HP_IRQn : stm32l1xx.h
  • USB_LP_IRQn : stm32l1xx.h

- w -

  • WWDG_IRQn : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Variables
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- a -

  • ADC_AnalogWatchdogCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_AnalogWatchdogSingleChannelConfig() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_AnalogWatchdogThresholdsConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_AutoInjectedConvCmd() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_BankSelection() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ClearFlag() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ClearITPendingBit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Cmd() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_CommonInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_CommonStructInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ContinuousModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DeInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DelaySelectionConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DiscModeChannelCountConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DiscModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_DMACmd() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_DMARequestAfterLastTransferCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_EOCOnEachRegularChannelCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ExternalTrigInjectedConvConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ExternalTrigInjectedConvEdgeConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetConversionValue() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetFlagStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetInjectedConversionValue() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetITStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetSoftwareStartConvStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_GetSoftwareStartInjectedConvCmdStatus() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_Init() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedChannelConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedDiscModeCmd() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_InjectedSequencerLengthConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_ITConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_PowerDownCmd() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_RegularChannelConfig() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_SetInjectedOffset() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_SoftwareStartConv() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_SoftwareStartInjectedConv() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • ADC_StructInit() : stm32l1xx_adc.h , stm32l1xx_adc.c
  • ADC_TempSensorVrefintCmd() : stm32l1xx_adc.c , stm32l1xx_adc.h
  • AES_CBC_Decrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_CBC_Encrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_ClearFlag() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ClearITPendingBit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_Cmd() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_CTR_Decrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_CTR_Encrypt() : stm32l1xx_aes.h , stm32l1xx_aes_util.c
  • AES_DeInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_DMAConfig() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ECB_Decrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_ECB_Encrypt() : stm32l1xx_aes_util.c , stm32l1xx_aes.h
  • AES_GetFlagStatus() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_GetITStatus() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_Init() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_ITConfig() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_IVInit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_IVStructInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_KeyInit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_KeyStructInit() : stm32l1xx_aes.c , stm32l1xx_aes.h
  • AES_ReadIV() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ReadKey() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_ReadSubData() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_StructInit() : stm32l1xx_aes.h , stm32l1xx_aes.c
  • AES_WriteSubData() : stm32l1xx_aes.h , stm32l1xx_aes.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- l -

  • LCD_BlinkConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_ClearFlag() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_ClearITPendingBit() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Cmd() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_ContrastConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_DeadTimeConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_DeInit() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_GetFlagStatus() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_GetITStatus() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_HighDriveCmd() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Init() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_ITConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_MuxSegmentCmd() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_PulseOnDurationConfig() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_StructInit() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_UpdateDisplayRequest() : stm32l1xx_lcd.c , stm32l1xx_lcd.h
  • LCD_WaitForSynchro() : stm32l1xx_lcd.h , stm32l1xx_lcd.c
  • LCD_Write() : stm32l1xx_lcd.c , stm32l1xx_lcd.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- n -

  • NVIC_Init() : misc.h , misc.c
  • NVIC_PriorityGroupConfig() : misc.c , misc.h
  • NVIC_SetVectorTable() : misc.h , misc.c
  • NVIC_SystemLPConfig() : misc.c , misc.h


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- o -

  • OPAMP_Cmd() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_DeInit() : stm32l1xx_opamp.c , stm32l1xx_opamp.h
  • OPAMP_GetFlagStatus() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_LowPowerCmd() : stm32l1xx_opamp.c , stm32l1xx_opamp.h
  • OPAMP_OffsetTrimConfig() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_OffsetTrimLowPowerConfig() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_OffsetTrimmingModeSelect() : stm32l1xx_opamp.h , stm32l1xx_opamp.c
  • OPAMP_PowerRangeSelect() : stm32l1xx_opamp.c , stm32l1xx_opamp.h
  • OPAMP_SwitchCmd() : stm32l1xx_opamp.c , stm32l1xx_opamp.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- c -

  • COMP_Cmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_DeInit() : stm32l1xx_comp.c , stm32l1xx_comp.h
  • COMP_GetOutputLevel() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_Init() : stm32l1xx_comp.c , stm32l1xx_comp.h
  • COMP_SW1SwitchConfig() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_VrefintOutputCmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • COMP_WindowCmd() : stm32l1xx_comp.h , stm32l1xx_comp.c
  • CRC_CalcBlockCRC() : stm32l1xx_crc.c , stm32l1xx_crc.h
  • CRC_CalcCRC() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_GetCRC() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_GetIDRegister() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_ResetDR() : stm32l1xx_crc.h , stm32l1xx_crc.c
  • CRC_SetIDRegister() : stm32l1xx_crc.c , stm32l1xx_crc.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- d -

  • DAC_ClearFlag() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_ClearITPendingBit() : stm32l1xx_dac.c , stm32l1xx_dac.h
  • DAC_Cmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_DeInit() : stm32l1xx_dac.c , stm32l1xx_dac.h
  • DAC_DMACmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_DualSoftwareTriggerCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_GetDataOutputValue() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_GetFlagStatus() : stm32l1xx_dac.c , stm32l1xx_dac.h
  • DAC_GetITStatus() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_Init() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_ITConfig() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SetChannel1Data() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SetChannel2Data() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SetDualChannelData() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_SoftwareTriggerCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DAC_StructInit() : stm32l1xx_dac.c , stm32l1xx_dac.h
  • DAC_WaveGenerationCmd() : stm32l1xx_dac.h , stm32l1xx_dac.c
  • DATA_EEPROM_EraseByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_EraseDoubleWord() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • DATA_EEPROM_EraseHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_EraseWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FastProgramWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_FixedTimeProgramCmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_Lock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramByte() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramDoubleWord() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • DATA_EEPROM_ProgramHalfWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_ProgramWord() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DATA_EEPROM_Unlock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • DBGMCU_APB1PeriphConfig() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_APB2PeriphConfig() : stm32l1xx_dbgmcu.h , stm32l1xx_dbgmcu.c
  • DBGMCU_Config() : stm32l1xx_dbgmcu.c , stm32l1xx_dbgmcu.h
  • DBGMCU_GetDEVID() : stm32l1xx_dbgmcu.c , stm32l1xx_dbgmcu.h
  • DBGMCU_GetREVID() : stm32l1xx_dbgmcu.c , stm32l1xx_dbgmcu.h
  • DMA_ClearFlag() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_ClearITPendingBit() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_Cmd() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_DeInit() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_GetCurrDataCounter() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_GetFlagStatus() : stm32l1xx_dma.h , stm32l1xx_dma.c
  • DMA_GetITStatus() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_Init() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_ITConfig() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_SetCurrDataCounter() : stm32l1xx_dma.c , stm32l1xx_dma.h
  • DMA_StructInit() : stm32l1xx_dma.c , stm32l1xx_dma.h


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- e -

  • EXTI_ClearFlag() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_ClearITPendingBit() : stm32l1xx_exti.c , stm32l1xx_exti.h
  • EXTI_DeInit() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_GenerateSWInterrupt() : stm32l1xx_exti.c , stm32l1xx_exti.h
  • EXTI_GetFlagStatus() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_GetITStatus() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_Init() : stm32l1xx_exti.h , stm32l1xx_exti.c
  • EXTI_StructInit() : stm32l1xx_exti.h , stm32l1xx_exti.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- f -

  • FLASH_ClearFlag() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_ErasePage() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_EraseParallelPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_FastProgramWord() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_GetFlagStatus() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_GetStatus() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_ITConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_Lock() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_OB_BootConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_BORConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetBOR() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetRDP() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetUser() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP1() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_GetWRP2() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_OB_Launch() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_Lock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_RDPConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_Unlock() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_UserConfig() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRP1Config() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRP2Config() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_OB_WRPConfig() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_PrefetchBufferCmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_ProgramHalfPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_ProgramParallelHalfPage() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_ReadAccess64Cmd() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_RUNPowerDownCmd() : stm32l1xx_flash.h , stm32l1xx_flash_ramfunc.c
  • FLASH_SetLatency() : stm32l1xx_flash.h , stm32l1xx_flash.c
  • FLASH_SLEEPPowerDownCmd() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_Unlock() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FLASH_WaitForLastOperation() : stm32l1xx_flash.c , stm32l1xx_flash.h
  • FSMC_NORSRAMCmd() : stm32l1xx_fsmc.c , stm32l1xx_fsmc.h
  • FSMC_NORSRAMDeInit() : stm32l1xx_fsmc.h , stm32l1xx_fsmc.c
  • FSMC_NORSRAMInit() : stm32l1xx_fsmc.h , stm32l1xx_fsmc.c
  • FSMC_NORSRAMStructInit() : stm32l1xx_fsmc.h , stm32l1xx_fsmc.c


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- g -

  • GetStatus() : stm32l1xx_flash_ramfunc.c
  • GPIO_DeInit() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_Init() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_PinAFConfig() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_PinLockConfig() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadInputData() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadInputDataBit() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadOutputData() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ReadOutputDataBit() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_ResetBits() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_SetBits() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_StructInit() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_ToggleBits() : stm32l1xx_gpio.c , stm32l1xx_gpio.h
  • GPIO_Write() : stm32l1xx_gpio.h , stm32l1xx_gpio.c
  • GPIO_WriteBit() : stm32l1xx_gpio.c , stm32l1xx_gpio.h


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- i -

  • I2C_AcknowledgeConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ARPCmd() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_CalculatePEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_CheckEvent() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_ClearFlag() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ClearITPendingBit() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Cmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DeInit() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_DMACmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DMALastTransferCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_DualAddressCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_FastModeDutyCycleConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GeneralCallCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GenerateSTART() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GenerateSTOP() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetFlagStatus() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_GetITStatus() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetLastEvent() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_GetPEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Init() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ITConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_NACKPositionConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_OwnAddress2Config() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_PECPositionConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ReadRegister() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_ReceiveData() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_Send7bitAddress() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SendData() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SMBusAlertConfig() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_SoftwareResetCmd() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_StretchClockCmd() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2C_StructInit() : stm32l1xx_i2c.c , stm32l1xx_i2c.h
  • I2C_TransmitPEC() : stm32l1xx_i2c.h , stm32l1xx_i2c.c
  • I2S_Cmd() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • I2S_Init() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • I2S_StructInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • IWDG_Enable() : stm32l1xx_iwdg.h , stm32l1xx_iwdg.c
  • IWDG_GetFlagStatus() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_ReloadCounter() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_SetPrescaler() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_SetReload() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h
  • IWDG_WriteAccessCmd() : stm32l1xx_iwdg.c , stm32l1xx_iwdg.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- p -

  • PWR_ClearFlag() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_DeInit() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_EnterLowPowerRunMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterSleepMode() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_EnterSTANDBYMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_EnterSTOPMode() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_FastWakeUpCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_GetFlagStatus() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_PVDCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_PVDLevelConfig() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_RTCAccessCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_UltraLowPowerCmd() : stm32l1xx_pwr.h , stm32l1xx_pwr.c
  • PWR_VoltageScalingConfig() : stm32l1xx_pwr.c , stm32l1xx_pwr.h
  • PWR_WakeUpPinCmd() : stm32l1xx_pwr.c , stm32l1xx_pwr.h


STM32L1xx Standard Peripherals Firmware Library: Globals

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- r -

  • RCC_AdjustHSICalibrationValue() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AdjustMSICalibrationValue() : stm32l1xx_rcc.c , stm32l1xx_rcc.h
  • RCC_AHBPeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_AHBPeriphClockLPModeCmd() : stm32l1xx_rcc.c , stm32l1xx_rcc.h
  • RCC_AHBPeriphResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1PeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1PeriphClockLPModeCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB1PeriphResetCmd() : stm32l1xx_rcc.c , stm32l1xx_rcc.h
  • RCC_APB2PeriphClockCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB2PeriphClockLPModeCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_APB2PeriphResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ClearFlag() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ClearITPendingBit() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ClockSecuritySystemCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_DeInit() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetClocksFreq() : stm32l1xx_rcc.c , stm32l1xx_rcc.h
  • RCC_GetFlagStatus() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetITStatus() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_GetSYSCLKSource() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HSEConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_HSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_ITConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSEClockSecuritySystemCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSEConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_LSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MCOConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MSICmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_MSIRangeConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PCLK1Config() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PCLK2Config() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_PLLCmd() : stm32l1xx_rcc.c , stm32l1xx_rcc.h
  • RCC_PLLConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_RTCCLKCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_RTCCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_RTCResetCmd() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_SYSCLKConfig() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RCC_WaitForHSEStartUp() : stm32l1xx_rcc.h , stm32l1xx_rcc.c
  • RTC_AlarmCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_AlarmStructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_AlarmSubSecondConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_Bcd2ToByte() : stm32l1xx_rtc.c
  • RTC_BypassShadowCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ByteToBcd2() : stm32l1xx_rtc.c
  • RTC_CalibOutputCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_CalibOutputConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ClearFlag() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ClearITPendingBit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_CoarseCalibCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_CoarseCalibConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_DateStructInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_DayLightSavingConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_DeInit() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_EnterInitMode() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ExitInitMode() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetAlarm() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetAlarmSubSecond() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetDate() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetFlagStatus() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetITStatus() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetStoreOperation() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetSubSecond() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetTime() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetTimeStamp() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_GetTimeStampSubSecond() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_GetWakeUpCounter() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_Init() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_ITConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_OutputConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_OutputTypeConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_ReadBackupRegister() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_RefClockCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_SetAlarm() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SetDate() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_SetTime() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SetWakeUpCounter() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SmoothCalibConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_StructInit() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_SynchroShiftConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TamperCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperFilterConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperPinsPrechargeDuration() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TamperPullUpCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperSamplingFreqConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TamperTriggerConfig() : stm32l1xx_rtc.h , stm32l1xx_rtc.c
  • RTC_TimeStampCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TimeStampOnTamperDetectionCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_TimeStructInit() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WaitForSynchro() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WakeUpClockConfig() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WakeUpCmd() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WriteBackupRegister() : stm32l1xx_rtc.c , stm32l1xx_rtc.h
  • RTC_WriteProtectionCmd() : stm32l1xx_rtc.h , stm32l1xx_rtc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- s -

  • SDIO_CEATAITCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ClearFlag() : stm32l1xx_sdio.c , stm32l1xx_sdio.h
  • SDIO_ClearITPendingBit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ClockCmd() : stm32l1xx_sdio.c , stm32l1xx_sdio.h
  • SDIO_CmdStructInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_CommandCompletionCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DataConfig() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DataStructInit() : stm32l1xx_sdio.c , stm32l1xx_sdio.h
  • SDIO_DeInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_DMACmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetCommandResponse() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetDataCounter() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetFIFOCount() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetFlagStatus() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetITStatus() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_GetPowerState() : stm32l1xx_sdio.c , stm32l1xx_sdio.h
  • SDIO_GetResponse() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_Init() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ITConfig() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_ReadData() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SendCEATACmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SendCommand() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SendSDIOSuspendCmd() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetPowerState() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetSDIOOperation() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_SetSDIOReadWaitMode() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_StartSDIOReadWait() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_StopSDIOReadWait() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_StructInit() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SDIO_WriteData() : stm32l1xx_sdio.h , stm32l1xx_sdio.c
  • SetSysClock() : system_stm32l1xx.c
  • SPI_BiDirectionalLineConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_CalculateCRC() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_Cmd() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_DataSizeConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_GetCRC() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_GetCRCPolynomial() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ClearFlag() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ClearITPendingBit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_DeInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_DMACmd() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_GetFlagStatus() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_GetITStatus() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ITConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_ReceiveData() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_I2S_SendData() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_Init() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SPI_NSSInternalSoftwareConfig() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_SSOutputCmd() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_StructInit() : stm32l1xx_spi.h , stm32l1xx_spi.c
  • SPI_TransmitCRC() : stm32l1xx_spi.c , stm32l1xx_spi.h
  • SYSCFG_DeInit() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_EXTILineConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_GetBootMode() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_MemoryRemapConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RIChannelSpeedConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RIDeInit() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RIHysteresisConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RIIOSwitchConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RIResistorConfig() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RISwitchControlModeCmd() : stm32l1xx_syscfg.c , stm32l1xx_syscfg.h
  • SYSCFG_RITIMInputCaptureConfig() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_RITIMSelect() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SYSCFG_USBPuCmd() : stm32l1xx_syscfg.h , stm32l1xx_syscfg.c
  • SystemCoreClockUpdate() : system_stm32l1xx.h , system_stm32l1xx.c
  • SystemInit() : system_stm32l1xx.h , system_stm32l1xx.c
  • SysTick_CLKSourceConfig() : misc.h , misc.c


STM32L1xx Standard Peripherals Firmware Library: Globals

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- t -

  • TI1_Config() : stm32l1xx_tim.c
  • TI2_Config() : stm32l1xx_tim.c
  • TI3_Config() : stm32l1xx_tim.c
  • TI4_Config() : stm32l1xx_tim.c
  • TIM_ARRPreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_CCxCmd() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ClearFlag() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearITPendingBit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC1Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC2Ref() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ClearOC3Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ClearOC4Ref() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_Cmd() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_CounterModeConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DeInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DMACmd() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_DMAConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_EncoderInterfaceConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ETRClockMode1Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ETRClockMode2Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ETRConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC1Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC2Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC3Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ForcedOC4Config() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GenerateEvent() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture1() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture2() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture3() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCapture4() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetCounter() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetFlagStatus() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetITStatus() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_GetPrescaler() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_ICInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ICStructInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_InternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ITConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_ITRxExternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC1PreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC2PreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC3PreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4FastConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4Init() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4PolarityConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OC4PreloadConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_OCStructInit() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_PrescalerConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_PWMIConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_RemapConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectCCDMA() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectHallSensor() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectInputTrigger() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectMasterSlaveMode() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectOCREFClear() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectOCxM() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectOnePulseMode() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SelectOutputTrigger() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SelectSlaveMode() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetAutoreload() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetClockDivision() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCompare1() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetCompare2() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCompare3() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetCompare4() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetCounter() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetIC1Prescaler() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetIC2Prescaler() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_SetIC3Prescaler() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_SetIC4Prescaler() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_TimeBaseInit() : stm32l1xx_tim.c , stm32l1xx_tim.h
  • TIM_TimeBaseStructInit() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_TIxExternalClockConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_UpdateDisableConfig() : stm32l1xx_tim.h , stm32l1xx_tim.c
  • TIM_UpdateRequestConfig() : stm32l1xx_tim.c , stm32l1xx_tim.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
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  • s
  • t
  • u
  • w

- u -

  • USART_ClearFlag() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ClearITPendingBit() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_ClockInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ClockStructInit() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_Cmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_DeInit() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_DMACmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_GetFlagStatus() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_GetITStatus() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_HalfDuplexCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_Init() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_IrDACmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_IrDAConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ITConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_LINBreakDetectLengthConfig() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_LINCmd() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_OneBitMethodCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_OverSampling8Cmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ReceiveData() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_ReceiverWakeUpCmd() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_SendBreak() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_SendData() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_SetAddress() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SetGuardTime() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_SetPrescaler() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_SmartCardCmd() : stm32l1xx_usart.h , stm32l1xx_usart.c
  • USART_SmartCardNACKCmd() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_StructInit() : stm32l1xx_usart.c , stm32l1xx_usart.h
  • USART_WakeUpConfig() : stm32l1xx_usart.c , stm32l1xx_usart.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
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  • i
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  • r
  • s
  • t
  • u
  • w

- w -

  • WaitForLastOperation() : stm32l1xx_flash_ramfunc.c
  • WWDG_ClearFlag() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_DeInit() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_Enable() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_EnableIT() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_GetFlagStatus() : stm32l1xx_wwdg.c , stm32l1xx_wwdg.h
  • WWDG_SetCounter() : stm32l1xx_wwdg.c , stm32l1xx_wwdg.h
  • WWDG_SetPrescaler() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c
  • WWDG_SetWindowValue() : stm32l1xx_wwdg.h , stm32l1xx_wwdg.c


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • IRQn_Type : stm32l1xx.h
  • ITStatus : stm32l1xx.h


STM32L1xx Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • AHBPrescTable : system_stm32l1xx.c
  • APBAHBPrescTable : stm32l1xx_rcc.c
  • PLLMulTable : system_stm32l1xx.c , stm32l1xx_rcc.c
  • SystemCoreClock : system_stm32l1xx.h , system_stm32l1xx.c


STM32L1xx Standard Peripherals Firmware Library: ADC_Private_Functions

Modules

ADC_Private_Functions

ADC

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Power saving functions

Power saving functions.

Analog Watchdog configuration functions

Analog Watchdog configuration functions.

Temperature Sensor & Vrefint (Voltage Reference internal) management function

Temperature Sensor & Vrefint (Voltage Reference internal) management function.

Regular Channels Configuration functions

Regular Channels Configuration functions.

Regular Channels DMA Configuration functions

Regular Channels DMA Configuration functions.

Injected channels Configuration functions

Injected channels Configuration functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: AES_Exported_Constants

Modules

AES_Exported_Constants

AES

Modules

AES_possible_Operation_modes
AES_possible_chaining_modes
AES_Data_Types
AES_Flags
AES_Interrupts
AES_DMA_Transfer_modes


STM32L1xx Standard Peripherals Firmware Library: AES_Private_Functions

Modules

AES_Private_Functions

AES

Modules

Initialization and configuration

Initialization and configuration.

Structures initialization functions

Structures initialization.

AES Read and Write

AES Read and Write.

DMA transfers management functions

DMA transfers management function.

Interrupts and flags management functions

Interrupts and flags management functions.

High Level AES functions

High Level AES functions.


STM32L1xx Standard Peripherals Firmware Library: CMSIS

Modules

CMSIS

Modules

Stm32l1xx
Stm32l1xx_system


STM32L1xx Standard Peripherals Firmware Library: COMP_Private_Functions

Modules

COMP_Private_Functions

COMP

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Window mode control function

Window mode control function.

Internal Reference Voltage output function

Internal Reference Voltage (VREFINT) output function.


STM32L1xx Standard Peripherals Firmware Library: DAC_Exported_Constants

Modules

DAC_Exported_Constants

DAC

Modules

DAC_trigger_selection
DAC_wave_generation
DAC_lfsrunmask_triangleamplitude
DAC_output_buffer
DAC_Channel_selection
DAC_data_alignment
DAC_data
DAC_interrupts_definition
DAC_flags_definition


STM32L1xx Standard Peripherals Firmware Library: DAC_Private_Functions

Modules

DAC_Private_Functions

DAC

Modules

DAC channels configuration

DAC channels configuration: trigger, output buffer, data format.

DMA management functions

DMA management functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: DMA_Private_Functions

Modules

DMA_Private_Functions

DMA

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Data Counter functions

Data Counter functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: Exported_constants

Modules

Exported_constants

Stm32l1xx

Modules

Peripheral_Registers_Bits_Definition


STM32L1xx Standard Peripherals Firmware Library: EXTI_Exported_Constants

Modules

EXTI_Exported_Constants

EXTI

Modules

EXTI_Lines


STM32L1xx Standard Peripherals Firmware Library: EXTI_Private_Functions

Modules

EXTI_Private_Functions

EXTI

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: FLASH_Exported_Constants

Modules

FLASH_Exported_Constants

FLASH

Modules

FLASH_Latency
FLASH_Interrupts
FLASH_Address
Option_Bytes_Write_Protection
Option_Bytes_Read_Protection
Option_Bytes_IWatchdog
Option_Bytes_nRST_STOP
Option_Bytes_nRST_STDBY
Option_Bytes_BOOT
Option_Bytes_BOR_Level
FLASH_Flags
FLASH_Keys
Timeout_definition
CMSIS_Legacy


STM32L1xx Standard Peripherals Firmware Library: FSMC_Exported_Constants

Modules

FSMC_Exported_Constants

FSMC

Modules

FSMC_NORSRAM_Bank
NOR_SRAM_Controller


STM32L1xx Standard Peripherals Firmware Library: FSMC_Private_Functions

Modules

FSMC_Private_Functions

FSMC

Modules

NOR/SRAM Controller functions

NOR/SRAM Controller functions.


STM32L1xx Standard Peripherals Firmware Library: GPIO_Exported_Constants

Modules

GPIO_Exported_Constants

GPIO

Modules

GPIO_pins_define
GPIO_Pin_sources
GPIO_Alternat_function_selection_define
GPIO_Legacy


STM32L1xx Standard Peripherals Firmware Library: GPIO_Private_Functions

Modules

GPIO_Private_Functions

GPIO

Modules

Initialization and Configuration

Initialization and Configuration.

GPIO Read and Write

GPIO Read and Write.

GPIO Alternate functions configuration functions

GPIO Alternate functions configuration functions.


STM32L1xx Standard Peripherals Firmware Library: I2C_Private_Functions

Modules

I2C_Private_Functions

I2C

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Data transfers functions

Data transfers functions.

PEC management functions

PEC management functions.

DMA transfers management functions

DMA transfers management functions.

Interrupts events and flags management functions

Interrupts, events and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: IWDG_Exported_Constants

Modules

IWDG_Exported_Constants

IWDG

Modules

IWDG_WriteAccess
IWDG_prescaler
IWDG_Flag


STM32L1xx Standard Peripherals Firmware Library: IWDG_Private_Functions

Modules

IWDG_Private_Functions

IWDG

Modules

Prescaler and Counter configuration functions

Prescaler and Counter configuration functions.

IWDG activation function

IWDG activation function.

Flag management function

Flag management function.


STM32L1xx Standard Peripherals Firmware Library: LCD_Exported_Constants

Modules

LCD_Exported_Constants

LCD

Modules

LCD_Prescaler
LCD_Divider
LCD_Duty
LCD_Bias
LCD_Voltage_Source
LCD_Interrupts
LCD_PulseOnDuration
LCD_DeadTime
LCD_BlinkMode
LCD_BlinkFrequency
LCD_Contrast
LCD_Flag
LCD_RAMRegister


STM32L1xx Standard Peripherals Firmware Library: LCD_Private_Functions

Modules

LCD_Private_Functions

LCD

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

LCD RAM memory write functions

LCD RAM memory write functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: MISC_Exported_Constants

Modules

MISC_Exported_Constants

MISC

Modules

Vector_Table_Base
System_Low_Power
Preemption_Priority_Group
SysTick_clock_source

Detailed Description

 The table below gives the allowed values of the pre-emption priority and subpriority according
 to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
  ============================================================================================================================
    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
  ============================================================================================================================
   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
                         |                                   |                             |   4 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
                         |                                   |                             |   3 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
                         |                                   |                             |   2 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
                         |                                   |                             |   1 bits for subpriority
  ----------------------------------------------------------------------------------------------------------------------------
   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
                         |                                   |                             |   0 bits for subpriority
  ============================================================================================================================


STM32L1xx Standard Peripherals Firmware Library: NOR_SRAM_Controller

Modules

NOR_SRAM_Controller

FSMC_Exported_Constants

Modules

FSMC_Data_Address_Bus_Multiplexing
FSMC_Memory_Type
FSMC_Data_Width
FSMC_Burst_Access_Mode
FSMC_AsynchronousWait
FSMC_Wait_Signal_Polarity
FSMC_Wrap_Mode
FSMC_Wait_Timing
FSMC_Write_Operation
FSMC_Wait_Signal
FSMC_Extended_Mode
FSMC_Write_Burst
FSMC_Address_Setup_Time
FSMC_Address_Hold_Time
FSMC_Data_Setup_Time
FSMC_Bus_Turn_around_Duration
FSMC_CLK_Division
FSMC_Data_Latency
FSMC_Access_Mode


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Exported_Constants

Modules

OPAMP_Exported_Constants

OPAMP

Modules

OPAMP_Selection
OPAMP_Switches
OPAMP_Trimming
OPAMP_Input
OPAMP_TrimValue
OPAMP_PowerRange


STM32L1xx Standard Peripherals Firmware Library: OPAMP_Private_Functions

Modules

OPAMP_Private_Functions

OPAMP

Modules

Initialization and configuration

Initialization and configuration.

Calibration functions

Calibration functions.


STM32L1xx Standard Peripherals Firmware Library: Peripheral_registers_structures

Data Structures

Peripheral_registers_structures

Stm32l1xx

Data Structures

struct | ADC_Common_TypeDef
struct | ADC_TypeDef
Analog to Digital Converter. More...
struct | AES_TypeDef
AES hardware accelerator. More...
struct | COMP_TypeDef
Comparator. More...
struct | CRC_TypeDef
CRC calculation unit. More...
struct | DAC_TypeDef
Digital to Analog Converter. More...
struct | DBGMCU_TypeDef
Debug MCU. More...
struct | DMA_Channel_TypeDef
DMA Controller. More...
struct | DMA_TypeDef
struct | EXTI_TypeDef
External Interrupt/Event Controller. More...
struct | FLASH_TypeDef
FLASH Registers. More...
struct | FSMC_Bank1_TypeDef
Flexible Static Memory Controller. More...
struct | FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E. More...
struct | GPIO_TypeDef
General Purpose IO. More...
struct | I2C_TypeDef
Inter-integrated Circuit Interface. More...
struct | IWDG_TypeDef
Independent WATCHDOG. More...
struct | LCD_TypeDef
LCD. More...
struct | OB_TypeDef
Option Bytes Registers. More...
struct | OPAMP_TypeDef
Operational Amplifier (OPAMP) More...
struct | PWR_TypeDef
Power Control. More...
struct | RCC_TypeDef
Reset and Clock Control. More...
struct | RI_TypeDef
Routing Interface. More...
struct | RTC_TypeDef
Real-Time Clock. More...
struct | SDIO_TypeDef
SD host Interface. More...
struct | SPI_TypeDef
Serial Peripheral Interface. More...
struct | SYSCFG_TypeDef
SysTem Configuration. More...
struct | TIM_TypeDef
TIM. More...
struct | USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter. More...
struct | WWDG_TypeDef
Window WATCHDOG. More...


STM32L1xx Standard Peripherals Firmware Library: PWR_Exported_Constants

Modules

PWR_Exported_Constants

PWR

Modules

PWR_PVD_detection_level
PWR_WakeUp_Pins
PWR_Voltage_Scaling_Ranges
PWR_Regulator_state_is_Sleep_STOP_mode
PWR_SLEEP_mode_entry
PWR_STOP_mode_entry
PWR_Flag


STM32L1xx Standard Peripherals Firmware Library: PWR_Private_Functions

Modules

PWR_Private_Functions

PWR

Modules

RTC Domain Access function

RTC Domain Access function.

PVD configuration functions

PVD configuration functions.

WakeUp pins configuration functions

WakeUp pins configuration functions.

Ultra Low Power mode configuration functions

Ultra Low Power mode configuration functions.

Voltage Scaling configuration functions

Voltage Scaling configuration functions.

Low Power modes configuration functions

Low Power modes configuration functions.

Flags management functions

Flags management functions.


STM32L1xx Standard Peripherals Firmware Library: RCC_Exported_Constants

Modules

RCC_Exported_Constants

RCC

Modules

RCC_HSE_configuration
RCC_MSI_Clock_Range
RCC_PLL_Clock_Source
RCC_PLL_Multiplication_Factor
RCC_PLL_Divider_Factor
RCC_System_Clock_Source
RCC_AHB_Clock_Source
RCC_APB1_APB2_Clock_Source
RCC_Interrupt_Source
RCC_LSE_Configuration
RCC_RTC_Clock_Source
RCC_AHB_Peripherals
RCC_APB2_Peripherals
RCC_APB1_Peripherals
RCC_MCO_Clock_Source
RCC_MCO_Output_Divider
RCC_Flag


STM32L1xx Standard Peripherals Firmware Library: RCC_Private_Functions

Modules

RCC_Private_Functions

RCC

Modules

Internal and external clocks, PLL, CSS and MCO configuration functions

Internal and external clocks, PLL, CSS and MCO configuration functions.

System AHB and APB busses clocks configuration functions

System, AHB and APB busses clocks configuration functions.

Peripheral clocks configuration functions

Peripheral clocks configuration functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: RTC_Exported_Constants

Modules

RTC_Exported_Constants

RTC

Modules

RTC_Hour_Formats
RTC_Asynchronous_Predivider
RTC_Synchronous_Predivider
RTC_Time_Definitions
RTC_AM_PM_Definitions
RTC_Year_Date_Definitions
RTC_Month_Date_Definitions
RTC_WeekDay_Definitions
RTC_Alarm_Definitions
RTC_AlarmDateWeekDay_Definitions
RTC_AlarmMask_Definitions
RTC_Alarms_Definitions
RTC_Alarm_Sub_Seconds_Masks_Definitions
RTC_Alarm_Sub_Seconds_Value
RTC_Wakeup_Timer_Definitions
RTC_Time_Stamp_Edges_definitions
RTC_Output_selection_Definitions
RTC_Output_Polarity_Definitions
RTC_Coarse_Calibration_Definitions
RTC_Calib_Output_selection_Definitions
RTC_Smooth_calib_period_Definitions
RTC_Smooth_calib_Plus_pulses_Definitions
RTC_Smooth_calib_Minus_pulses_Definitions
RTC_DayLightSaving_Definitions
RTC_Tamper_Trigger_Definitions
RTC_Tamper_Filter_Definitions
RTC_Tamper_Sampling_Frequencies_Definitions
RTC_Tamper_Pin_Precharge_Duration_Definitions
RTC_Tamper_Pins_Definitions
RTC_Output_Type_ALARM_OUT
RTC_Add_1_Second_Parameter_Definitions
RTC_Substract_Fraction_Of_Second_Value
RTC_Backup_Registers_Definitions
RTC_Input_parameter_format_definitions
RTC_Flags_Definitions
RTC_Interrupts_Definitions
RTC_Legacy


STM32L1xx Standard Peripherals Firmware Library: SDIO_Exported_Constants

Modules

SDIO_Exported_Constants

SDIO

Modules

SDIO_Clock_Edge
SDIO_Clock_Bypass
SDIO_Clock_Power_Save
SDIO_Bus_Wide
SDIO_Hardware_Flow_Control
SDIO_Power_State
SDIO_Interrupt_soucres
SDIO_Command_Index
SDIO_Response_Type
SDIO_Wait_Interrupt_State
SDIO_CPSM_State
SDIO_Response_Registers
SDIO_Data_Length
SDIO_Data_Block_Size
SDIO_Transfer_Direction
SDIO_Transfer_Type
SDIO_DPSM_State
SDIO_Flags
SDIO_Read_Wait_Mode


STM32L1xx Standard Peripherals Firmware Library: SDIO_Private_Functions

Modules

SDIO_Private_Functions

SDIO

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

DMA transfers management functions

DMA transfers management functions.

Command path state machine (CPSM) management functions

Command path state machine (CPSM) management functions.

Data path state machine (DPSM) management functions

Data path state machine (DPSM) management functions.

SDIO IO Cards mode management functions

SDIO IO Cards mode management functions.

CE-ATA mode management functions

CE-ATA mode management functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: SPI_Private_Functions

Modules

SPI_Private_Functions

SPI

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Data transfers functions

Data transfers functions.

Hardware CRC Calculation functions

Hardware CRC Calculation functions.

DMA transfers management functions

DMA transfers management functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: Stm32l1xx

Modules

Stm32l1xx

CMSIS

Modules

Library_configuration_section
Configuration_section_for_CMSIS
Exported_types
Peripheral_registers_structures
Peripheral_memory_map
Peripheral_declaration
Exported_constants
Exported_macro


STM32L1xx Standard Peripherals Firmware Library: STM32L1xx_StdPeriph_Driver

Modules

STM32L1xx_StdPeriph_Driver

Modules

MISC

MISC driver modules.

ADC

ADC driver modules.

AES

AES driver modules.

COMP

COMP driver modules.

CRC

CRC driver modules.

DAC

DAC driver modules.

DBGMCU

DBGMCU driver modules.

DMA

DMA driver modules.

EXTI

EXTI driver modules.

FLASH

FLASH driver modules.

FSMC

FSMC driver modules.

GPIO

GPIO driver modules.

I2C

I2C driver modules.

IWDG

IWDG driver modules.

LCD

LCD driver modules.

OPAMP

OPAMP driver modules.

PWR

PWR driver modules.

RCC

RCC driver modules.

RTC

RTC driver modules.

SDIO

SDIO driver modules.

SPI

SPI driver modules.

SYSCFG

SYSCFG driver modules.

TIM

TIM driver modules.

USART

USART driver modules.

WWDG

WWDG driver modules.

Detailed Description

< Define to prevent recursive inclusion -------------------------------------

< Includes ------------------------------------------------------------------


STM32L1xx Standard Peripherals Firmware Library: Stm32l1xx_system

Modules

Stm32l1xx_system

CMSIS

Modules

STM32L1xx_System_Includes

Define to prevent recursive inclusion.

STM32L1xx_System_Exported_types
STM32L1xx_System_Exported_Constants
STM32L1xx_System_Exported_Macros
STM32L1xx_System_Exported_Functions
STM32L1xx_System_Private_Includes
STM32L1xx_System_Private_TypesDefinitions
STM32L1xx_System_Private_Defines
STM32L1xx_System_Private_Macros
STM32L1xx_System_Private_Variables
STM32L1xx_System_Private_FunctionPrototypes
STM32L1xx_System_Private_Functions


STM32L1xx Standard Peripherals Firmware Library: SYSCFG_Exported_Constants

Modules

SYSCFG_Exported_Constants

SYSCFG

Modules

EXTI_Port_Sources
EXTI_Pin_sources
SYSCFG_Memory_Remap_Config
RI_Resistor
RI_Channel
RI_ChannelSpeed
RI_InputCapture
TIM_Select
RI_InputCaptureRouting
RI_IOSwitch
RI_Port
define


STM32L1xx Standard Peripherals Firmware Library: SYSCFG_Private_Functions

Modules

SYSCFG_Private_Functions

SYSCFG

Modules

SYSCFG Initialization and Configuration functions

SYSCFG Initialization and Configuration functions.

RI Initialization and Configuration functions

RI Initialization and Configuration functions.


STM32L1xx Standard Peripherals Firmware Library: USART_Private_Functions

Modules

USART_Private_Functions

USART

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Data transfers functions

Data transfers functions.

MultiProcessor Communication functions

Multi-Processor Communication functions.

LIN mode functions

LIN mode functions.

Halfduplex mode function

Half-duplex mode function.

Smartcard mode functions

Smartcard mode functions.

IrDA mode functions

IrDA mode functions.

DMA transfers management functions

DMA transfers management functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Firmware Library: WWDG_Exported_Constants

Modules

WWDG_Exported_Constants

WWDG

Modules

WWDG_Prescaler


STM32L1xx Standard Peripherals Firmware Library: WWDG_Private_Functions

Modules

WWDG_Private_Functions

WWDG

Modules

Prescaler, Refresh window and Counter configuration functions

Prescaler, Refresh window and Counter configuration functions.

WWDG activation functions

WWDG activation functions.

Interrupts and flags management functions

Interrupts and flags management functions.


STM32L1xx Standard Peripherals Library: Supported devices and toolchains

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STM32L1xx Standard Peripherals Library

Supported devices and toolchains

Copyright 2012 STMicroelectronics

STM32L1xx devices peripherals Overview

The following table presents the available peripherals set for each STM32L devices.
Glossary
  • Ultra Low Power Medium density devices are STM32L151xx and STM32L152xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
  • Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx microcontrollers where the Flash memory density is 384 Kbytes.
 | STM32F family | STM32L Medium-density | STM32L Medium-density Plus | STM32L High-density
ADC | X | X | X | X
COMP | NA | x | X | X
CRC | X | X | X | X
DAC | NA | X | X | X
DBGMCU | X | X | X | X
DMA | X | X | X | X
EXTI | X | X | X | X
FLASH | X | X | X | X
GPIO | X | X | X | X
I2C | X | X | X | X
IWDG | X | X | X | X
LCD | NA | X | X | X
PWR | X | X | X | X
RCC | X | X | X | X
RTC | X | X | X | X
SPI | X | X | X | X
SYSCFG | NA | X | X | X
TIM | X | X | X | X
USART | X | X | X | X
USB FS Device | X | X | X | X
WWDG | X | X | X | X
AES | NA | NA | X | X
SDIO | X | NA | NA | X
FSMC | X | NA | NA | X
I2S | X | NA | X | X
OPAMP | NA | NA | X | X

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Supported STM32L1xx devices

The Standard Peripherals Library supports all STM32L1xx family products: Ultra Low Power High-, Medium-density and Medium-density Plus devices. By using this library it becomes straightforward to move the application firmware from one STM32L1xx device to another.

User has only to select which device he will use by controlling preprocessor define declared in stm32l1xx.h file (No selected device by default) then the library will be configured accordingly:

stm32l1xx.h

...

/* Uncomment the line below according to the target STM32L device used in your
   application
  */

#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)

  /* #define STM32L1XX_MD */           /*!< STM32L Ultra Low Power Medium density devices */

  /* #define STM32L1XX_MDP */          /*!< STM32L Ultra Low Power Medium density Plus devices */
  /* #define STM32L1XX_HD */           /*!< STM32L Ultra Low Power High density devices */
#endif

#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
 #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
#endif

/*  Tip: To avoid modifying this file each time you need to switch between these
        devices, you can define the device in your toolchain compiler preprocessor.

 - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
 - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and
   STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
 - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx
   microcontrollers where the Flash memory density is 384 Kbytes.

  */

...

This define will control the declaration of the following part of the Standard Peripherals library:

IRQ channel definition

Peripheral memory mapping and physical registers address definition

Peripheral pointer declaration and driver header file inclusion

Product miscellaneous configuration: external quartz (HSE) value…

Peripheral with Features w/ different/incompatible implementation across the family

Note: This define doesn’t apply to peripheral drivers, these drivers are always supporting features of the family’s superset.

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Supported toolchains

The Standard Peripherals Library supports the following toolchains:

RealView Microcontroller Development Kit MDK-ARM
Embedded Workbench for ARM EWARM

Raisonance Integrated Development Environment RIDE

TASKING Development Tools TASKING

Atolic TrueSTUDIO

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STM32L1xx Standard Peripherals Library: Peripheral’s examples

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STM32L1xx Standard Peripherals Library: Peripheral’s examples

Copyright 2012 STMicroelectronics

The STM32L1xx Standard Peripherals library provides a rich set of examples covering the main features of each peripheral. All the examples are independent from the software toolchain. These examples run on STMicroelectronics STM32L152D-EVAL (Ultra Low Power High-density) and STM32L152-EVAL (Ultra Low Power Medium-density) evaluations boards and can be easily tailored to any other supported device and development board. Only source files are provided for each example and user can tailor the provided project template to run the selected example with his preferred toolchain.

Contents

  1. STM32L1xx StdPeriph_Lib Examples
  2. What do I need to start successfully with Examples?
  3. How to proceed?

STM32L1xx StdPeriph_Lib Examples

The package contains the following examples:

ADC - AES - COMP - CortexM3 - CRC - DAC - DMA - EXTI - FLASH - FSMC - GPIO - I2C - IWDG - LCD - Lib_DEBUG - NVIC - OPAMP - PWR - RCC - RTC - SDIO - SPI - SysTick - TIM - USART - WWDG

IP Module | Example
 | Name | Brief Description
ADC | AnalogWatchdog | This example describes how to use the ADC analog watchdog to guard continuously an ADC channel.
 | ADC_DMA | This example describes how to use the ADC1 and DMA to transfer continuously converted data from ADC1 to memory.
 | ADC_Freeze | This example provides a short description of how to use the ADC peripheral Freeze and PowerDown modes. The System is clocked by a 512kHz frequency (fsystem) (see system_stm32l1xx.c file). Since the ADC is clocked by a HSI (16MHz) frequency, and the sampling time is 4 Cycles, so the ADC conversion frequency (fADCconv) is 1MHz.
 | IDDMeas | This example provides a short description of how to use the ADC peripheral to measure IDD in Run mode. The Measured IDD value is displayed continuously on LCD GLASS in mA.
AES | AES_MODES | This example provides a short description of how to configure the AES hardware accelerator to encrypt then to decrypt text with the different modes ECB, CBC et CTR.
 | AES_TwoBoards | This is a typical example of how to use the AES software library to encrypt data in master board and decrypt it in slave board using I2C and interrupts.
 | EncryptDecrypt | This example provides a short description of how to configure the AES hardware accelerator to encrypt then to decrypt text.
COMP | AnalogVoltageMonitoring | In this example, COMP2 is used to monitor the analog voltage while the MCU is in stop mode and to wake-up the system if a predefined threshold is crossed. When the analog voltage crosses the threshold, the COMP2 is powered-off and ADC1 is powered-on to perform continuous conversion.
 | COMP_AnalogWatchdog | This example shows how to make an analog watchdog using the STM32L1xx COMPs peripherals in window mode: If the input voltage is above the higher threshold, LD3 and LD1 are turned On. If the input voltage is under the lower threshold, LD2 and LD4 are turned On. If the input voltage is within the thresholds, the MCU remains in STOP mode and all leds are turned Off.
 | COMP_Interrupt | This example shows how to configure the COMP peripheral to compare the external voltage applied on PB12 with the Internal Voltage Reference. And when the comparator 1 non inverting input (which is connected to PB12) crosses (either rising or falling edges) the internal reference voltage VREFINT (1.22V), the comparator 1 generates an interrupt and toggles LED1.
 | PulseWidthMeasurement | This example shows how to configure the COMP2 peripheral to measure pulse width. This method (measuring signal pulse using comparator is interesting when external signal doesn't respect the VIL and VIH levels).
 | PWMSignalControl | This example shows how to configure COMP2 peripheral to hold on safe state (low level) TIM2 channels as soon as COMP2 output is set at high level.
CortexM3 | BitBand | This example shows how to use CortexM3 Bit-Band access to perform atomic read-modify-write and read operations on a variable in SRAM.
 | Mode_Privilege | This example shows how to modify CortexM3 Thread mode privilege access and stack. CortexM3 Thread mode is entered on Reset, and can be entered as a result of an exception return.
 | MPU | This example presents the MPU features on STM32L1xx Ultra Low Medium-density devices and it can be easily ported to any other STM32 device supporting MPU. The example purpose (ACCESS_PERMISSION) is to configure a memory region as privileged read only region and tries to perform read and write operation in different mode.
CRC | CRC_Calculation | This example shows how to use CRC (cyclic redundancy check) calculation unit to get a CRC code of a given buffer of data word (32-bit), based on a fixed generator polynomial (0x4C11DB7).
DAC | DAC_ADC | This example describes how to use the ADC1 and DAC to output on DAC_OUT1 sampled values of ADC1. The ADC1 is configured to convert continuously ADC1 channel18 (PB12). The End Of Conversion (EOC) interrupt is enabled and the conversion is triggered by software.
 | DAC_SignalsGeneration | This example provides a short description of how to use the DAC peripheral to generate several signals using DMA controller. When the user presses the KEY push-button, DMA transfers the two selected waveforms to DAC.
DMA | ADC_TIM2 | This example provides a description of how to use a DMA channel to transfer continuously a data from a peripheral (ADC1) to another peripheral (TIM2) supporting DMA transfer.
 | FLASH_RAM | This example provides a description of how to use a DMA channel to transfer a word data buffer from FLASH memory to embedded SRAM memory.
 | RAM_DAC | This example provides a description of how to use a DMA channel to transfer data buffer from RAM memory to DAC.
 | FSMC | This example provides a description of how to use two DMA channels to transfer a word data buffer from Flash memory to external SRAM memory and to recuperate the written data from external SRAM to be stored in internal SRAM.
EXTI | Example | This example shows how to configure an external interrupt line. In this example, an EXTI line is configured to generate an interrupt on each falling edge. In the interrupt routine a led connected to a specific GPIO pin is toggled.
FLASH | Data_ Program | This example provides a description of how to program the STM32L1xx data memory.
 | HalfPage | This example provides a description of how to program the STM32L1xx FLASH program memory using half page write operation. The Halfpage operation is possible only from SRAM.
 | Write_Protection | This example provides a description of how to enable and disable the write protection for the STM32L1xx FLASH.
 | ParallelHalfPage | This example provides a description of how to program the STM32L1xx FLASH program memory using parallel page erase and parallel half page write operations. The parallel page erase and parallel halfpage write operations are possible onlyfrom internal SRAM.
 | Dual_Boot | This example demonstrates the dual Flash boot capability of STM32L1xx High-density devices: boot from Flash memory Bank1 or Bank2.
FSMC | NOR | This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform erase/read/write operations on the M29W128GL NORmemory mounted on the STM32L152D-EVAL board.
 | SRAM | This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform read/write operations on the IS61WV51216BLL SRAMmemory mounted on STM32L152D-EVAL board.
 | Data_Memory | This example shows how to use the external SRAM mounted on STM32L152D-EVAL as program data memory (including heap and stack).
GPIO | IOToggle | This example describes how to use GPIO BSRR (Port bit set/reset register) for IO toggling max frequency.
I2C | I2C_EEPROM | This firmware provides a basic example of how to use the I2C firmware library and an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the example is interfacing with M24C64 EEPROM)
 | I2C_TSENSOR | This example provides a description of how to use the I2C to communicate with an STLM75 (or a compatible device) I2C temperature sensor is mounted on the STM32L152-EVAL board and used to get instantaneous external temperature (-55°C to +125°C).
 | DataExchangeDMA | This is a typical example of how to use the I2C software library to ensure the steps of an I2C communication between slave Receiver/transmitter and master transmitter/receiver using DMA.
 | DataExchangeInterrupt | This is a typical example of how to use the I2C software library to ensure the steps of an I2C communication between slave Receiver/transmitter and master transmitter/receiver using interrupt.
 | MasterReceiverInterrupt | This is a typical example of how to use the I2C software library to ensure the steps of an I2C communication between slave transmitter and master receiver using interrupt.
 | MasterTransmitterInterrupt | This example provides a small application in which joystick buttons are used to trigger I2C communication and though using I2C firmware library.
IWDG | Example | This example shows how to update at regular period the IWDG reload counter and how to simulate a software fault generating an MCU IWDG reset on expiry of a programmed time period.
LCD | Blink Frequency | This example provides a description of how to use the STM32L1xx embedded LCD controller and how to configure the LCD Blink mode and Blink frequency.
 | Contrast Control | This example provides a description of how to use the STM32L1xx embedded LCD controller and how to Configure the LCD Contrast.
 | Segments Drive | This example provides a description of how to use the STM32L1xx LCD embedded controller to drive the Pacific Display LCD glass (PD-878) mounted on STM32L152-EVAL board.
LIB_DEBUG | Example | This example demonstrates how to declare dynamic peripherals pointers used for Debug mode.
NVIC | DMA_WFIMode | This example shows how to enter the system to WFI mode with DMA transfer enabled and wake-up from this mode by the DMA End of Transfer interrupt.
 | IRQ_Mask | This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC) IRQ Channels configuration and how to mask/activate different IRQs.
 | IRQ_Priority | This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC).
 | VectorTable_Relocation | This example describes how to set the CortexM3 vector table in a specific address other than default using the NVIC_SetVectorTable function from the misc.h/.c driver.
OPAMP | InternalFollower | This example provides a short description of how to configure the OPAMP2 in internal follower and how to use OPAMP2 output as ADC input.
 | OPAMP_NonInverting | This example shows how to configure the operational amplifier OPAMP2 built in STM32L1xx devices to make a non inverting ampifier.
PWR | STANDBY | This example shows how to enter the system to STANDBY mode and wake-up from this mode using: external RESET, RTC Alarm or WKUP pin.
 | STOP | This example shows how to enter the system to STOP mode and wake-up using EXTI Line interrupts. The EXTI Line sources are PC.13 and RTC Alarm.
 | BOR | This example shows how to configure the programmable BOR thresholds using the FLASH option bytes.
 | CurrentConsumption | This example shows how to configure the STM32L1xx system to measure different Ultra Low Power modes current consumption.
 | PVD | This example shows how to configure the programmable voltage detector using an external interrupt line. In this example, EXTI line 16 is configured to generate an interrupt on each rising or falling edge of the PVD output signal (which indicates that the Vdd voltage is below the PVD threshold).
RCC | Example | This example demonstrates how to switch the System clock from one source to another.
RTC | Calendar | This example provides a short description of how to use the RTC peripheral. By default, the Calendar Time (initialized in main.c file) is displayed on LCD glass. When the user press KEY button, the Calendar Date (initialized in main.c file) is displayed on LCD glass. After each switch between Calendar time and Calendar date, the LED 1 toggle.
 | TimeStamp | This example provides a short description of how to use the RTC peripheral and the timeStamp Feature.
 | Tamper | This example shows how to write/read data to/from RTC Backup data registers and demonstrates the Tamper detection feature.
 | RTC_LSI | This example demonstrates and explains how to use the LSI clock source auto calibration to get a precise RTC clock.
 | RTC_StopWatch | This example illustrates how to use the STM32L1xx new RTC's sub-seconds and Tamper feature (Filter, sampling) features. It simulates a precise chronometer with 5 record times possibilities stored in the Backup registers (5 registers for time (second, minutes and hours) and 5 registers for subsecond).
 | RTC_Timer | This example provides a short description of how to use the RTC peripheral’s with Alarm sub seconds feature to simulate a timer with refresh time equal to 250 ms (1 second/ 8) * 2).
SDIO | uSDCard | This example provides a basic example of how to use the SDIO firmware library and an associate driver to perform read/write operations on the SD Card memory (SD Card V1.0, V1.1, V2.0 and SDHC (High Capacity) protocol)that could be mounted on theSTM32L152D-EVAL board.
SPI | MSD | This example provides a basic example of how to use the SPI firmware library and an associate SPI SDcard driver to communicate with an SDcard available on The eval board.
 | DataExchangeDMA | This example provides a small application in which joystick buttons are used to trigger SPI communication and though using SPI firmware library.
 | DataExchangeInterrupt | This example provides a small application in which joystick buttons are used to trigger SPI communication and though using SPI firmware library.
 | SPI_EEPROM | This firmware provides a basic example of how to use the SPI firmware library and an associate SPI EEPROM driver to communicate with an I2C EEPROM device (here theexample is interfacing with M95xxx EEPROM)
SysTick | Example | This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 32 MHz, the SysTick is clocked by the AHB clock (HCLK).
TIM | InputCapture | This example shows how to use the TIM peripheral to measure the frequency of an external signal, The measured Frequency is displayed on the LCD Glass.
 | InputCaptureRouting | This example shows how configure the Routing Interface to map TIM4 channel 2 to PE13 in order to measure the frequency of an external signal, the measured frequency is displayed on the LCD Glass.
 | TIM9_ETR_LSE | This example explains how to configure TIM9 time base that works completely independently of the system clock. This allows the scheduling of tasks without having to take into account the processor state (the processor may be stopped or executing at low, medium or full speed). For this purpose, the LSE clock is internally redirected to the TIM9 ETR input.
 | TIM9_OCToggle | This example shows how to configure the TIM9 peripheral to generate two different signals with two different frequencies.
 | TIM11_PWM_Output | This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) mode. The TIM11CLK frequency is set to SystemCoreClock.
 | TimeBase | This example shows how to configure the TIM peripheral in Output Compare Timing mode with the corresponding Interrupt requests for each channel in order to generate 4 different time bases.
 | ExternalTrigger_Synchro | This example shows how to synchronize TIM peripherals in cascade mode with an external trigger.
 | Cascade_Synchro | This example shows how to synchronize TIM peripherals in cascade mode.
 | Parallel_Synchro | This example shows how to synchronize TIM peripherals in parallel mode.
 | PWM_Input | This example shows how to use the TIM peripheral to measure the frequency and duty cycle of an external signal.
 | OnePulse | This example shows how to use the TIM peripheral to generate a One pulse Mode after a Rising edge of an external signal is received in Timer Input pin.
 | OCActive | This example shows how to configure the TIM peripheral to generate four different signals with four different delays.
 | OCInactive | This example shows how to configure the TIM peripheral in Output Compare Inactive mode with the corresponding Interrupt requests for each channel.
 | OCToggle | This example shows how to configure the TIM3 peripheral to generate four different signals with four different frequencies.
 | PWM_Output | This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) mode.
USART | Printf | This example shows how to retarget the C library printf function to the USART. This implementation output the printf message on the HyperTerminal using USARTx. USARTx can be USART2 or USART3 depending on the EVAL board you are using.
 | Hyperterminal_Interrupt | This example provides a description of how to use the EVAL_COM1 Transmit and Receive interrupts to communicate with the HyperTerminal. EVAL_COM1 can be USART2 or USART3 depending on the STMicroelectronics EVAL board you are using.
 | DataExchangeDMA | This example provides a small application in which joystick buttons are used to trigger UART communication and though using UART firmware library.
 | DataExchangeInterrupt | This example provides a small application in which joystick buttons are used to trigger UART communication and though using UART firmware library.
WWDG | Example | This example shows how to update at regular period the WWDG counter and how to simulate a software fault generating an MCU WWDG reset on expiry of a programmed time period.

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What do I need to start successfully with Examples?

Evaluation Board: STMicroelectronics STM32L152D-EVAL (Ultra Low Power High-density) and STMicroelectronics STM32L152-EVAL (Ultra Low Power Medium-density) evaluations boards or any other compatible hardware. To use your own specific hardware, you need simply to adapt the examples hardware configuration to your platform.

Tool chain:

Use your preferred toolchain. MDK-ARM (Keil), EWARM (IAR), RIDE (Raisonance), TASKING (Altium) or TrueSTUDIO (Atollic)

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How to proceed?

Copy the files main.c, main.h (if exists), stm32l1xx_it.c, system_stm32l1xx.c, platform_config.h (if exists), stm32l1xx_it.h, stm32l1xx_conf.h and any other source files from the specified example to your toolchain folder under Project\STM32L1xx_StdPeriph_Template. This project folder contains already all toolchain files needed for creating projects for STM32L1xx microcontrollers.

Open your preferred toolchain and Set active the project related to the used STM32L1xx device and hardware platform:

STM32L152-EVAL: to configure the project for STM32L1xx Ultra Low Power Medium-density devices

STM32L152D-EVAL: to configure the project for STM32L1xx Ultra Low Power High-density devices

Finally compile, load and run the example

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For complete documentation on STM32L(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Library: Peripheral’s Drivers Description

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STM32L1xx Standard Peripherals Library

Peripheral’s Drivers Description

Copyright 2012 STMicroelectronics

STM32L1xx Standard Peripheral's Library Architecture

The following figure provides a global view of the STM32L1xx Standard Peripherals Library usage and interaction with other firmware conponents.

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Description of the STM32L1xx Standard Peripheral's Drivers files

The Standard Peripherals library file inclusions relationship is shown in the following figure:

Each peripheral has a source code file stm32l1xx_ppp.c and a header file stm32l1xx_ppp.h. The stm32l1xx_ppp.c file contains all the firmware functions required to use the PPP peripheral.
A single memory mapping file, stm32l1xx.h, is supplied for all peripherals. It contains all the register declarations and bits definition. This is the only file that needs to be included in the user application to interface with the library.
The stm32l1xx_conf.h file is used to specify the set of parameters to interface with the library drivers before running any application.

The table bellow lists and describes the different files used by the Standard Peripherals library:

File name | Description
stm32l1xx_conf.h | Peripheral’s drivers configuration file The user can enable or disable peripheral header file inclusion by using the template This file can also be used to enable or disable the Library run-time failure detection before compiling the firmware library drivers, through the preprocessor define USE_FULL_ASSERT
stm32l1xx_ppp.h | Header file of PPP peripheral This file includes the PPP peripheral function and variable definitions used within these functions.
stm32l1xx_ppp.c | Driver source code file of PPP peripheral written in C language
stm32l1xx_it.h | Header file including all interrupt handlers prototypes
stm32l1xx_it.c | Template source file containing the interrupt service routine (ISR) for CortexM3 exceptions. User can add additional ISR(s) for the used peripheral(s) (for the available peripheral interrupt handler's name, please refer to the startup file startup_stm32l1xx_md.s).

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Description of the STM32L1xx CMSIS files

The table below lists and describes the different STM32L1xx CMSIS files:

File name

Description

stm32l1xx.h

CMSIS Cortex-M3 STM32L1xxxx device peripheral access layer header file.

The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:

  • configuration section that allows to select:

- the device used in the target application

- to use or not the peripheral’s drivers in application code (i.e. code will be based on direct
access to peripheral’s registers rather than drivers API) , this option is controlled by the
#define USE_STDPERIPH_DRIVER
- to change few application-specific parameters such as the HSE crystal frequency

  • data structures and the address mapping for all peripherals
  • peripheral's registers declarations and bits definition
  • macros to access peripheral’s registers hardware

system.stm32l1xx.h

CMSIS Cortex-M3 STM32F10xxx device peripheral access layer system header file.

system.stm32l1xx.c

CMSIS Cortex-M3 STM32F10xxx device peripheral access layer system source file.

startup_stm32l1xx_md.s

Ultra Low Power Medium density devices startup file.
startup_stm32l1xx_mdp.s | Ultra Low Power Medium density Plus devices startup file.
startup_stm32l1xx_hd.s | Ultra Low Power High density devices startup file.

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For more details please refer to CMSIS documentation.


STM32L1xx Standard Peripherals Drivers MISRA-C 2004 Compliance

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STM32L1xx Standard Peripherals Drivers MISRA-C 2004 Compliance

Copyright 2012 STMicroelectronics

The C programming language is growing in importance and use for embedded systems, but when it comes to developing code for safety-critical systems, the language has many drawbacks. There are several unspecified, implementation-defined, and undefined aspects of the C language that make it unsuited for use when developing safety-critical systems.
The Motor Industry Software Reliability Association’s Guidelines for the use of the C language in critical systems MISRA-C 2004 [1] describe a subset of C, suited for use when developing safety-critical systems.
The STM32L1xx Standard Peripherals Drivers (STM32L1xx_StdPeriph_Driver) has been developed to be MISRA-C 2004 compliant.

The following section details how the StdPeriph_Driver complies with MISRA-C 2004 (as described in section 4.4 Claiming compliance of the standard [1]):

  • A compliance matrix has been completed which shows how compliance has been enforced.
  • All the STM32L1xx_StdPeriph_Driver C code is compliant with the rules of MISRA-C 2004 or subject documented deviations.
  • A list of all instances of rules not being followed is being maintained, and for each instance there is an appropriately signed-off deviation.
  • All issues listed in the section "4.2 The programming language and coding context of the standard" [1], that has to be checked during the phase of the firmware development process, have been addressed during the development of the STM32L1xx Standard Peripherals Drivers and appropriate measures have been taken.

Contents

  1. STM32L1xx Standard Peripherals Drivers Compliance
  2. How to check your code for MISRA-C 2004 Compliance?

STM32L1xx Standard Peripherals Drivers Compliance

The STM32L1xx Standard Peripherals Drivers (STM32L1xx_StdPeriph_Driver) has been checked for MISRA-C 2004 compliance using the IAR C/C++ Compiler for ARM. MISRA compliancy applies only to STM32L1xx Standard Peripherals Drivers source file, examples and project files are not MISRA compliant.

For the checking tool two options are available:

  • The compiler: IAR C/C++ Compiler for ARM V6.30
  • Manual Checking (code review)

The following table lists the MISRA-C 2004 rules that are violated frequently in the code.

MISRA-C 2004 Rule No | Required/Advisory | Summary | Reason
1.1 | Required | Compiler is configured to allow extensions - all code shall conform to ISO 9899 standard C, with no extensions permitted | IAR compiler extensions are enabled. This was allowed to support new CMSIS types.
5.1 | Required | Identifiers (internal and external) shall not rely on significance of more than 31 characters | Some long parameters names are defined for code readability.
10.1 | Required | The value of an expression of integer type shall not be implicitly converted to a different underlying type. | Complexity
10.3 | Required | The value of a complex expression of integer type shall only be cast to a type that is not wider and of the same signedness as the underlying type of the expression. | Complexity (violated only on stm32l1xx_flash_ramfunc.c file)
10.6 | Required | A 'U' suffix shall be applied to all constants of 'unsigned' type | The "stdint.h" defined types are used to be CMSIS compliant.
11.2 | Required | Conversions shall not be performed between a pointer to object and any type other than an integral type, another pointer to object type or a pointer to void. | Needed when addressing memory mapped registers
11.3 | Advisory | A cast should not be performed between a pointer type and an integral type. | Needed when addressing memory mapped registers
12.13 | Required | The increment (++) and decrement (--) operators should not be mixed with other operators in an expression. | Complexity (violated only on stm32l1xx_flash_ramfunc.c file)
19.1 | Advisory | #include statements in a file shall only be preceded by other preprocessor directives or comments | This rule was violated to be inline with the CMSIS architecture.
17.4 | Required | Array indexing shall be the only allowed form of pointer arithmetic. | Complexity (violated only on stm32l1xx_flash_ramfunc.c file)

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How to check your code for MISRA-C 2004 Compliance?

The default IAR project template provided with the STM32L1xx Standard Peripherals Library is already pre-configured for MISRA-C 2004 Compliance. Then, user has to enable the MISRA-C 2004 checker if needed.

To enable the IAR MISRA-C 2004 Checker, go to Project->Options (ALT+F7) and then in "General Options" Category select the "MISRA-C:2004" tab and check the "Enable MISRA-C" box. With the default EWARM template project, all violated rules described above are unchecked.

To check your code for MISRA-C 2004 compliance using the IAR MISRA-C Checker, please follow the following steps

Enable the IAR MISRA-C 2004 Checker

Uncomment the "USE_FULL_ASSERT" inside the stm32l1xx_conf.h file

Note: Only the STM32L1xx Standard Peripherals Drivers are MISRA-C 2004 Compliant.

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[1] MISRA-C 2004 Guidelines for the use of the C language in critical systems, Motor Industry Software Reliability Association, October 2004


STM32L1xx Standard Peripherals Library: Overview

Copyright 2012 STMicroelectronics

The STM32L1xx Standard Peripherals library covers 3 abstraction levels, and includes:

A complete register address mapping with all bits, bit fields and registers declared in C. This avoids a cumbersome task and more important, it brings the benefits of a bug free reference mapping file, speeding up the early project phase.

A collection of routines and data structures which covers all peripheral functions (drivers with common API). It can directly be used as a reference framework, since it also includes macros for supporting core-related intrinsic features and common constants and data types definition.

A set of examples covering all available peripherals with template projects for the most common development toolchains. With the appropriate hardware evaluation board, this allows to get started with a brand new micro within few hours.

Each driver consists of a set of functions covering all peripheral functionalities. The development of each driver is driven by a common API (application programming interface) which standardizes the driver structure, the functions and the parameter names.
The driver source code is developed in ‘Strict ANSI-C’ (relaxed ANSI-C for projects and example files). It is fully documented and is MISRA-C 2004 compliant. Writing the whole library in ‘Strict ANSI-C’ makes it independent from the software toolchain. Only the start-up files depend on the toolchain.

The Standard Peripherals Library implements run-time failure detection by checking the input values for all library functions. Such dynamic checking contributes towards enhancing the robustness of the software. Run-time detection is suitable for user application development and debugging. It adds an overhead which can be removed from the final application code to minimize code size and execution speed. For more details refer to Section Run-time checking.

Since the Standard Peripherals Library is generic and covers all peripheral functionalities, the size and/or execution speed of the application code may not be optimized. For many applications, the library may be used as is. However, for applications having tough constraints in terms of code size and/or execution speed, the library drivers should be used as a reference on how to configure the peripheral and tailor them to specific application requirements.

Note: The performance of application code, in terms of size and/or speed, depends also from the C compiler optimization settings. To help make the application code smaller, faster or balanced between size and speed you should consider fine-tuning the optimizations according to your application needs. For more information please refer to your C compiler documentation.

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STM32L1xx Standard Peripherals Library: Coding rules and conventions

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STM32L1xx Standard Peripherals Library: Coding rules and conventions

Copyright 2012 STMicroelectronics

The STM32L1xx Standard Peripherals Library uses rules and conventions described in the sections below.

Acronyms

The Table below describes the acronyms used in the firmware library.

Acronym | Peripheral/unit
ADC | Analog/digital converter
COMP | Analog Comparators
CRC | CRC calculation unit
DAC | Digital to analog converter
DBGMCU | Debug MCU
DMA | DMA controller
EXTI | External interrupt/event controller
FLASH | Flash memory
GPIO | General purpose I/O
I2C | Inter-integrated circuit
IWDG | Independent watchdog
LCD | LCD Glass Controller
NVIC | Nested vectored interrupt controller
PWR | Power controller
RCC | Reset and clock controller
RI | Routing Interface
RTC | Reset and clock controller
SPI | Serial peripheral interface
SYSCFG | System Configuration
SysTick | System tick timer
TIM | Advanced-control, general-purpose or basic timer
USART | Universal synchronous asynchronous receiver transmitter
WWDG | Window watchdog
FSMC | Flexible static memory controller
AES | AES hardware accelerator
SDIO | Secure digital input/output interface
I2S | Integrated Interchip Sound
OPAMP | Operational amplifiers

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Naming conventions

The STM32L1xx Standard Peripherals Library uses the following naming conventions:

  • PPP refers to any peripheral acronym, for example ADC.
  • System and source/header file names are preceded by the prefix ‘stm32l1xx_’.
  • Constants used in one file are defined within this file. A constant used in more than one file is defined in a header file. All constants are written in upper case.
  • Registers are considered as constants. Their names are in upper case. In most cases, the same acronyms as in the STM32L1xx reference manual document are used.
  • Names of peripheral’s functions are preceded by the corresponding peripheral acronym in upper case followed by an underscore. The first letter in each word is in upper case, for example USART_SendData. Only one underscore is allowed in a function name to separate the peripheral acronym from the rest of the function name.
  • Functions used to initialize the PPP peripheral according to parameters specified in PPP_InitTypeDef are named PPP_Init, for example TIM_Init.
  • Functions used to reset the PPP peripheral registers to their default values are named PPP_DeInit, for example TIM_DeInit.
  • Functions used to fill the PPP_InitTypeDef structure with the reset values of each member are named PPP_StructInit, for example USART_StructInit.
  • Functions used to enable or disable the specified PPP peripheral are named PPP_Cmd, for example USART_Cmd.
  • Functions used to enable or disable an interrupt source of the specified PPP peripheral are named PPP_ITConfig, for example RCC_ITConfig.
  • Functions used to enable or disable the DMA interface of the specified PPP peripheral are named PPP_DMAConfig, for example TIM_DMAConfig.
  • Functions used to configure a peripheral function always end with the string ‘Config’, for example GPIO_PinAFConfig.
  • Functions used to check whether the specified PPP flag is set or reset are named PPP_GetFlagStatus, for example I2C_GetFlagStatus.
  • Functions used to clear a PPP flag are named PPP_ClearFlag, for example I2C_ClearFlag.
  • Functions used to check whether the specified PPP interrupt has occurred or not are named PPP_GetITStatus, for example I2C_GetITStatus.
  • Functions used to clear a PPP interrupt pending bit are named PPP_ClearITPendingBit, for example I2C_ClearITPendingBit.

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Coding rules

This section describes the coding rules used in the Standard Peripherals library.

Variable types

Specific variable types are already defined with a fixed type and size. These types are defined in the file stm32l1xx.h

typedef enum
{
  FALSE = 0,
  TRUE = !FALSE
}
bool;

typedef enum {
  RESET = 0,
  SET = !RESET
}
FlagStatus, ITStatus, BitStatus;

typedef enum {
  DISABLE = 0,
  ENABLE = !DISABLE
}
FunctionalState;

typedef enum {
  ERROR = 0,
  SUCCESS = !ERROR
}
ErrorStatus;

Peripheral’s registers

Peripheral’s registers are accessed through a pointer of structure. Each peripheral has its own structure and pointer. All the structures and declarations are defined in the stm32l1xx.h file.

Registers structure
The example below illustrates the Serial Peripheral Interface (SPI) registers structure declaration:

/**
  * @brief Serial Peripheral Interface
  */

typedef struct
{
  __IO uint16_t CR1;
  uint16_t  RESERVED0;
  __IO uint16_t CR2;
  uint16_t  RESERVED1;
  __IO uint16_t SR;
  uint16_t  RESERVED2;
  __IO uint16_t DR;
  uint16_t  RESERVED3;
  __IO uint16_t CRCPR;
  uint16_t  RESERVED4;
  __IO uint16_t RXCRCR;
  uint16_t  RESERVED5;
  __IO uint16_t TXCRCR;
  uint16_t  RESERVED6;
} SPI_TypeDef;

Register names are the register acronyms written in upper case for each peripheral.
RESERVEDi indicates a reserved field (i being an integer that indexes the reserved field).

Peripheral declaration
The following example shows the declaration of the SPI peripheral:

#define PERIPH_BASE ((u32)0x40000000)
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
...
/* SPI2 Base Address definition*/
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)

The peripheral registers are accessed as follows:

SPI1->CR1 = 0x0001;

Each peripheral has several dedicated registers which contain different flags. Registers are defined within a dedicated structure for each peripheral. Flags are defined as acronyms written in upper case and preceded by ‘PPP_FLAG_’. Flag definition is adapted to each peripheral case and defined in stm32l1xx_ppp.h file.

Registers bits
All the peripheral registers bits are defined as constants in the stm32l1xx.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_<bit_name>

Example:

#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)  /*!<Rx Buffer DMA Enable */
#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)  /*!<Tx Buffer DMA Enable */
#define  SPI_CR2_SSOE                        ((uint8_t)0x04)  /*!<SS Output Enable */
#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)  /*!<Error Interrupt Enable */
#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)  /*!<RX buffer Not Empty Interrupt Enable */
#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)  /*!<Tx buffer Empty Interrupt Enable */

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Bit-Banding

The Cortex-M3 memory map includes two bit-band memory regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

All the STM32L1xx peripheral registers are mapped in a bit-band region. This feature is consequently intensively used in functions which perform single bit set/reset in order to reduce and optimize code size.

  1. Mapping formula

The mapping formula shows how to link each word in the alias region to a corresponding target bit in the bit-band region. The mapping formula is given below:

bit_word_offset = (byte_offset x 32) + (bit_number × 4)
bit_word_addr = bit_band_base + bit_word_offse t

where:

  • bit_word_offset is the position of the target bit in the bit-band memory region
  • bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
  • bit_band_base is the starting address of the alias region
  • byte_offset is the number of the byte in the bit-band region that contains the targeted bit
  • bit_number is the bit position (0-7) of the targeted bit.

  2. Example of implementation

The following example shows how to map the PLLON[24] bit of RCC_CR register in the alias region:

/* Peripheral base address in the bit-band region */
#define PERIPH_BASE ((u32)0x40000000)
/* Peripheral address in the alias region */
#define PERIPH_BB_BASE ((u32)0x42000000)
/* ----- RCC registers bit address in the alias region ------ */
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of PLLON bit */
#define CR_OFFSET (RCC_OFFSET + 0x00)
#define PLLON_BitNumber 0x18
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32
(PLLON_BitNumber * 4))
To code a function which enables/disables the PLL, the usual method is the following:
...
#define CR_PLLON_Set ((u32)0x01000000)
#define CR_PLLON_Reset ((u32)0xFEFFFFFF)
...
void RCC_PLLCmd(FunctionalState NewState)
{
if (NewState != DISABLE)
{ /* Enable PLL */
RCC->CR |= CR_PLLON_Set;
}
else
{ /* Disable PLL */
RCC->CR &= CR_PLLON_Reset;
}
}
Using bit-band access this function will be coded as follows:
void RCC_PLLCmd(FunctionalState NewState)
{
*(vu32 *) CR_PLLON_BB = (u32)NewState;
}

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Run-time checking

The firmware library implements run-time failure detection by checking the input values of all library functions. The run-time checking is achieved by using an assert_param macro. This macro is used in all library functions which have at least an input parameter. It allows the user to check that the input value lies within the defined parameter values.

EXTI_Init function example

stm32l1xx_exti.c
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
  /* Check the parameters */
  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
...
}

stm32l1xx_exti.h
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))

#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))

If the expression passed to the assert_param macro is false, the assert_failed function is called, otherwise nothing happens.

Two implementation of assert_failed function are provided, depending on USE_FULL_ASSERT define (declared in stm32l1xx_conf.h file).

  • "#define USE_FULL_ASSERT 1" line is uncommented, if the expression passed to the assert_param macro is false, the assert_failed function will have as input the name of the source file and the source line number of the call that failed.
  • "#define FULL_ASSERT 1" line is commented, if the expression passed to the assert_param macro is true, the assert_failed function will have takes no does not returns the name of the source file and the source line number of the call that failed.

The assert_param macro is implemented in stm32l1xx_conf.h as follows:

#ifdef  USE_FULL_ASSERT
/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param  expr: If expr is false, it calls assert_failed function
  *         which reports the name of the source file and the source
  *         line number of the call that failed. If expr is true, it returns no value.
  * @retval None
  */
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
#else
   #define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

The assert_failed function is implemented in the main.c file or in any other user C files and can be modified by the user in order to take action when an error occurs.

#ifdef  USE_FULL_ASSERT
/**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param  file: pointer to the source file name
  * @param  line: assert_param error line source number
  * @retval None
  */
void assert_failed(uint8_t* file, uint32_t line)
{
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

  /* Infinite loop */
  while (1)
  {
  }
}
#endif

It is recommended to use run-time checking during application code development and debugging, and to remove it from the final application to improve code size and speed (because of the overhead it introduces).
However if the user wants to keep this functionality in his final application, he can re-use the assert_param macro defined within the library to test the parameter values before calling the library functions.

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STM32L1xx Standard Peripherals Library: How to use the Library

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STM32L1xx Standard Peripherals Library

How to use the Library

Copyright 2012 STMicroelectronics

How to use the Standard Peripherals Library

Create a project and setup all your toolchain's start-up files (or use the template project provided within the Library, under
Project\STM32L1xx_StdPeriph_Template)

Select the corresponding startup file depending of the used device:

- startup_stm32l1xx_md.s: for STM32L Ultra Low Power Medium density devices

- startup_stm32l1xx_mdp.s: for STM32L Ultra Low Power Medium density Plus devices
- startup_stm32l1xx_hd.s: for STM32L Ultra Low Power High density devices

The Library entry point is stm32l1xx.h (under Libraries\CMSIS\Device\ST\STM32L1xx\Include), user has to include it in the application main and configure it:

Select the target product family to be used, comment/uncomment the right define:

#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
/* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */

/* #define STM32L1XX_MDP  */
     /*!< STM32L1XX_MD: STM32L Ultra Low Power  Medium-density Plus devices */
#define STM32L1XX_HD
     /*!< STM32L1XX_HD: STM32L Ultra Low Power  High-density devices */

#endif

Then user has the choice to use or not the Peripheral’s Drivers

- Case1: application code based on Standard Peripheral’s drivers API (files under Libraries\STM32L1xx_StdPeriph_Driver)

- Uncomment #define USE_PERIPH_LIBRARY (default)

- In stm32l1xx_conf.h file, select the peripherals to include their header file

- Use Peripheral’s drivers API to build the application; refer to next section for more information.

- In addition to the Peripheral’s drivers you can reuse/adapt the rich set of examples available within the Library to speed

your development, this allow you to started within few hours. Refer to the complete list of available examples

- Case2: application code based on Peripheral’s registers direct access

- Comment #define USE_PERIPH_LIBRARY

- Use Peripheral’s registers structure and bits definition available within stm32l1xx.h to build the application

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Peripheral initialization and configuration

This section describes step-by-step how to initialize and configure a peripheral using the Peripheral’s Drivers. The peripheral will be referred to as PPP.

  1. In the main application file, declare a PPP_InitTypeDef structure, for example: PPP_InitTypeDef PPP_InitStructure;

The PPP_InitStructure is a working variable located in data memory area. It allows initializing one or more PPP instances.

  2. Fill the PPP_InitStructure variable with the allowed values of the structure member.

There are two ways of doing this:

  • Configuring the whole structure by following the procedure described below:

PPP_InitStructure.member1
= val1;
PPP_InitStructure.member2 = val2;
PPP_InitStructure.memberN = valN; /* where N is the number of the
structure members */

The previous initialization step can be merged in one single line to optimize the code size:

PPP_InitTypeDef PPP_InitStructure = { val1, val2,.., valN}

  • Configuring only a few members of the structure: in this case the user should modify the PPP_InitStructure variable that has been already filled by a call to the PPP_StructInit(..) function. This ensures that the other members of the PPP_InitStructure variable are initialized to the appropriate values (in most cases their default values).

PPP_StructInit(&PPP_InitStructure);
PP_InitStructure.memberX = valX;
PPP_InitStructure.memberY = valY; /*where X and Y are the members the
user wants to configure*/

  3. Initialize the PPP peripheral by calling the PPP_Init(..) function.

PPP_Init(PPP, &PPP_InitStructure);

  4. At this stage the PPP peripheral is initialized and can be enabled by making a call to PPP_Cmd(..) function.

PPP_Cmd(PPP, ENABLE);

The PPP peripheral can then be used through a set of dedicated functions. These functions are specific to the peripheral.

Note:

  1. Before configuring a peripheral, its clock must be enabled by calling one of the following functions:

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx, ENABLE);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx, ENABLE);

  2. PPP_DeInit(..) function can be used to set all PPP peripheral registers to their default values:

PPP_DeInit(PPP);

  3. To modify the peripheral settings after configuring the peripheral, the user can proceed as follows:

PPP_InitStucture.memberX = valX;
PPP_InitStructure.memberY = valY; /* where X and Y are the only members that user wants to modify*/
PPP_Init(PPP, &PPP_InitStructure);

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STM32L1xx Standard Peripherals Library: Limitation

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STM32L1xx Standard Peripherals Library: Limitations

Copyright 2012 STMicroelectronics

Limitations

No known limitation in this version.


STM32L1xx Standard Peripherals Firmware Library: main_page.txt File Reference

  • File List
  • Globals

main_page.txt File Reference

STM32L1xx Standard Peripherals Library: Footer

For complete documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: misc.c Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src

misc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    misc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides all the miscellaneous firmware functions (add-on
00008   *          to CMSIS functions).
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "misc.h"
00028
00029 /** @addtogroup STM32L1xx_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /** @defgroup MISC
00034   * @brief MISC driver modules
00035   * @{
00036   */
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
00041
00042 /* Private macro -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /* Private function prototypes -----------------------------------------------*/
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /** @defgroup MISC_Private_Functions
00048   * @{
00049   */
00050 /**
00051   *
00052 @verbatim
00053  *******************************************************************************
00054                    ##### Interrupts configuration functions #####
00055  *******************************************************************************
00056     [..] This section provide functions allowing to configure the NVIC interrupts
00057          (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
00058          (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
00059              function according to the following table.
00060              The table below gives the allowed values of the preemption priority
00061              and subpriority according to the Priority Grouping configuration
00062              performed by NVIC_PriorityGroupConfig function.
00063   ============================================================================================================================
00064     NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
00065   ============================================================================================================================
00066    NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for preemption priority
00067                          |                                   |                             |   4 bits for subpriority
00068   ----------------------------------------------------------------------------------------------------------------------------
00069    NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for preemption priority
00070                          |                                   |                             |   3 bits for subpriority
00071   ----------------------------------------------------------------------------------------------------------------------------
00072    NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for preemption priority
00073                          |                                   |                             |   2 bits for subpriority
00074   ----------------------------------------------------------------------------------------------------------------------------
00075    NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for preemption priority
00076                          |                                   |                             |   1 bits for subpriority
00077   ----------------------------------------------------------------------------------------------------------------------------
00078    NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for preemption priority
00079                          |                                   |                             |   0 bits for subpriority
00080   ============================================================================================================================
00081
00082
00083          (#) Enable and Configure the priority of the selected IRQ Channels.
00084
00085         -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
00086             the IRQ priority will be managed only by subpriority.
00087             The sub-priority is only used to sort pending exception priorities,
00088             and does not affect active exceptions.
00089         -@- Lower priority values gives higher priority.
00090         -@- Priority Order:
00091             (#@) Lowest Preemption priority.
00092             (#@) Lowest Subpriority.
00093             (#@) Lowest hardware priority (IRQn position).
00094
00095 @endverbatim
00096 */
00097
00098 /**
00099   * @brief  Configures the priority grouping: preemption priority and subpriority.
00100   * @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
00101   *   This parameter can be one of the following values:
00102   *     @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
00103   *                                4 bits for subpriority.
00104   *     @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
00105   *           interrupt. This interrupts priority is managed only with subpriority.
00106   *     @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
00107   *                                3 bits for subpriority.
00108   *     @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
00109   *                                2 bits for subpriority.
00110   *     @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
00111   *                                1 bits for subpriority.
00112   *     @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
00113   *                                0 bits for subpriority.
00114   * @retval None
00115   */
00116 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
00117 {
00118   /* Check the parameters */
00119   assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
00120
00121   /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
00122   SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
00123 }
00124
00125 /**
00126   * @brief  Initializes the NVIC peripheral according to the specified
00127   *         parameters in the NVIC_InitStruct.
00128   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00129   *         function should be called before.
00130   * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
00131   *         the configuration information for the specified NVIC peripheral.
00132   * @retval None
00133   */
00134 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
00135 {
00136   uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
00137
00138   /* Check the parameters */
00139   assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
00140   assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
00141   assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
00142
00143   if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
00144   {
00145     /* Compute the Corresponding IRQ Priority --------------------------------*/
00146     tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
00147     tmppre = (0x4 - tmppriority);
00148     tmpsub = tmpsub >> tmppriority;
00149
00150     tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
00151     tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
00152     tmppriority = tmppriority << 0x04;
00153
00154     NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
00155
00156     /* Enable the Selected IRQ Channels --------------------------------------*/
00157     NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00158       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
00159   }
00160   else
00161   {
00162     /* Disable the Selected IRQ Channels -------------------------------------*/
00163     NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00164       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
00165   }
00166 }
00167
00168 /**
00169   * @brief  Sets the vector table location and Offset.
00170   * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
00171   *   This parameter can be one of the following values:
00172   *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
00173   *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
00174   * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
00175   * @retval None
00176   */
00177 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
00178 {
00179   /* Check the parameters */
00180   assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
00181   assert_param(IS_NVIC_OFFSET(Offset));
00182
00183   SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
00184 }
00185
00186 /**
00187   * @brief  Selects the condition for the system to enter low power mode.
00188   * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
00189   *   This parameter can be one of the following values:
00190   *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
00191   *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
00192   *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
00193   * @param  NewState: new state of LP condition.
00194   *         This parameter can be: ENABLE or DISABLE.
00195   * @retval None
00196   */
00197 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
00198 {
00199   /* Check the parameters */
00200   assert_param(IS_NVIC_LP(LowPowerMode));
00201   assert_param(IS_FUNCTIONAL_STATE(NewState));
00202
00203   if (NewState != DISABLE)
00204   {
00205     SCB->SCR |= LowPowerMode;
00206   }
00207   else
00208   {
00209     SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
00210   }
00211 }
00212
00213 /**
00214   * @brief  Configures the SysTick clock source.
00215   * @param  SysTick_CLKSource: specifies the SysTick clock source.
00216   *   This parameter can be one of the following values:
00217   *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
00218   *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
00219   * @retval None
00220   */
00221 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
00222 {
00223   /* Check the parameters */
00224   assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
00225
00226   if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
00227   {
00228     SysTick->CTRL |= SysTick_CLKSource_HCLK;
00229   }
00230   else
00231   {
00232     SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
00233   }
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /**
00245   * @}
00246   */
00247
00248 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: misc.h Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

misc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    misc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the miscellaneous
00008   *          firmware library functions (add-on to CMSIS functions).
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __MISC_H
00028 #define __MISC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup MISC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  NVIC Init Structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
00054                                                    This parameter can be a value of @ref IRQn_Type
00055                                                    (For the complete STM32 Devices IRQ Channels list, please
00056                                                     refer to stm32l1xx.h file) */
00057
00058   uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
00059                                                    specified in NVIC_IRQChannel. This parameter can be a value
00060                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
00061
00062   uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
00063                                                    in NVIC_IRQChannel. This parameter can be a value
00064                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
00065
00066   FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
00067                                                    will be enabled or disabled.
00068                                                    This parameter can be set either to ENABLE or DISABLE */
00069 } NVIC_InitTypeDef;
00070
00071 /**
00072   *
00073 @verbatim
00074  The table below gives the allowed values of the pre-emption priority and subpriority according
00075  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
00076   ============================================================================================================================
00077     NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
00078   ============================================================================================================================
00079    NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
00080                          |                                   |                             |   4 bits for subpriority
00081   ----------------------------------------------------------------------------------------------------------------------------
00082    NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
00083                          |                                   |                             |   3 bits for subpriority
00084   ----------------------------------------------------------------------------------------------------------------------------
00085    NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
00086                          |                                   |                             |   2 bits for subpriority
00087   ----------------------------------------------------------------------------------------------------------------------------
00088    NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
00089                          |                                   |                             |   1 bits for subpriority
00090   ----------------------------------------------------------------------------------------------------------------------------
00091    NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
00092                          |                                   |                             |   0 bits for subpriority
00093   ============================================================================================================================
00094 @endverbatim
00095 */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098
00099 /** @defgroup MISC_Exported_Constants
00100   * @{
00101   */
00102
00103 /** @defgroup Vector_Table_Base
00104   * @{
00105   */
00106
00107 #define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
00108 #define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
00109 #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
00110                                   ((VECTTAB) == NVIC_VectTab_FLASH))
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup System_Low_Power
00116   * @{
00117   */
00118
00119 #define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
00120 #define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
00121 #define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
00122 #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
00123                         ((LP) == NVIC_LP_SLEEPDEEP) || \
00124                         ((LP) == NVIC_LP_SLEEPONEXIT))
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup Preemption_Priority_Group
00130   * @{
00131   */
00132
00133 #define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
00134                                                             4 bits for subpriority */
00135 #define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
00136                                                             3 bits for subpriority */
00137 #define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
00138                                                             2 bits for subpriority */
00139 #define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
00140                                                             1 bits for subpriority */
00141 #define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
00142                                                             0 bits for subpriority */
00143
00144 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
00145                                        ((GROUP) == NVIC_PriorityGroup_1) || \
00146                                        ((GROUP) == NVIC_PriorityGroup_2) || \
00147                                        ((GROUP) == NVIC_PriorityGroup_3) || \
00148                                        ((GROUP) == NVIC_PriorityGroup_4))
00149
00150 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00151
00152 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00153
00154 #define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0005FFFF)
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup SysTick_clock_source
00161   * @{
00162   */
00163
00164 #define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
00165 #define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
00166 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
00167                                        ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
00168 /**
00169   * @}
00170   */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Exported macro ------------------------------------------------------------*/
00177 /* Exported functions ------------------------------------------------------- */
00178
00179 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
00180 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
00181 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
00182 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
00183 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
00184
00185 #ifdef __cplusplus
00186 }
00187 #endif
00188
00189 #endif /* __MISC_H */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: Modules

Modules

Here is a list of all modules:
  • CMSIS
    • Stm32l1xx
      • Library_configuration_section
      • Configuration_section_for_CMSIS
      • Exported_types
      • Peripheral_registers_structures
      • Peripheral_memory_map
      • Peripheral_declaration
      • Exported_constants
        • Peripheral_Registers_Bits_Definition
      • Exported_macro
    • Stm32l1xx_system
      • STM32L1xx_System_Includes
      • STM32L1xx_System_Exported_types
      • STM32L1xx_System_Exported_Constants
      • STM32L1xx_System_Exported_Macros
      • STM32L1xx_System_Exported_Functions
      • STM32L1xx_System_Private_Includes
      • STM32L1xx_System_Private_TypesDefinitions
      • STM32L1xx_System_Private_Defines
      • STM32L1xx_System_Private_Macros
      • STM32L1xx_System_Private_Variables
      • STM32L1xx_System_Private_FunctionPrototypes
      • STM32L1xx_System_Private_Functions
  • STM32L1xx_StdPeriph_Driver
    • MISC
      • MISC_Exported_Constants
        • Vector_Table_Base
        • System_Low_Power
        • Preemption_Priority_Group
        • SysTick_clock_source
      • MISC_Private_Functions
    • ADC
      • ADC_Exported_Constants
        • ADC_Power_down_during_Idle_and_or_Delay_phase
        • ADC_Prescaler
        • ADC_Resolution
        • ADC_external_trigger_edge_for_regular_channels_conversion
        • ADC_external_trigger_sources_for_regular_channels_conversion
        • ADC_data_align
        • ADC_channels
        • ADC_sampling_times
        • ADC_Delay_length
        • ADC_external_trigger_edge_for_injected_channels_conversion
        • ADC_external_trigger_sources_for_injected_channels_conversion
        • ADC_injected_channel_selection
        • ADC_analog_watchdog_selection
        • ADC_interrupts_definition
        • ADC_flags_definition
        • ADC_thresholds
        • ADC_injected_offset
        • ADC_injected_length
        • ADC_injected_rank
        • ADC_regular_length
        • ADC_regular_rank
        • ADC_regular_discontinuous_mode_number
        • ADC_Bank_Selection
      • ADC_Private_Functions
        • Initialization and Configuration functions
        • Power saving functions
        • Analog Watchdog configuration functions
        • Temperature Sensor & Vrefint (Voltage Reference internal) management function
        • Regular Channels Configuration functions
        • Regular Channels DMA Configuration functions
        • Injected channels Configuration functions
        • Interrupts and flags management functions
    • AES
      • AES_Exported_Constants
        • AES_possible_Operation_modes
        • AES_possible_chaining_modes
        • AES_Data_Types
        • AES_Flags
        • AES_Interrupts
        • AES_DMA_Transfer_modes
      • AES_Private_Functions
        • Initialization and configuration
        • Structures initialization functions
        • AES Read and Write
        • DMA transfers management functions
        • Interrupts and flags management functions
        • High Level AES functions
    • COMP
      • COMP_Exported_Constants
        • COMP_Selection
        • COMP_InvertingInput
        • COMP_OutputSelect
        • COMP_Speed
      • COMP_Private_Functions
        • Initialization and Configuration functions
        • Window mode control function
        • Internal Reference Voltage output function
    • CRC
      • CRC_Exported_Constants
      • CRC_Private_Functions
    • DAC
      • DAC_Exported_Constants
        • DAC_trigger_selection
        • DAC_wave_generation
        • DAC_lfsrunmask_triangleamplitude
        • DAC_output_buffer
        • DAC_Channel_selection
        • DAC_data_alignment
        • DAC_data
        • DAC_interrupts_definition
        • DAC_flags_definition
      • DAC_Private_Functions
        • DAC channels configuration
        • DMA management functions
        • Interrupts and flags management functions
    • DBGMCU
      • DBGMCU_Exported_Constants
      • DBGMCU_Private_Functions
    • DMA
      • DMA_Exported_Constants
        • DMA_data_transfer_direction
        • DMA_peripheral_incremented_mode
        • DMA_memory_incremented_mode
        • DMA_peripheral_data_size
        • DMA_memory_data_size
        • DMA_circular_normal_mode
        • DMA_priority_level
        • DMA_memory_to_memory
        • DMA_interrupts_definition
        • DMA_flags_definition
        • DMA_Buffer_Size
      • DMA_Private_Functions
        • Initialization and Configuration functions
        • Data Counter functions
        • Interrupts and flags management functions
    • EXTI
      • EXTI_Exported_Constants
        • EXTI_Lines
      • EXTI_Private_Functions
        • Initialization and Configuration functions
        • Interrupts and flags management functions
    • FLASH
      • FLASH_Exported_Constants
        • FLASH_Latency
        • FLASH_Interrupts
        • FLASH_Address
        • Option_Bytes_Write_Protection
        • Option_Bytes_Read_Protection
        • Option_Bytes_IWatchdog
        • Option_Bytes_nRST_STOP
        • Option_Bytes_nRST_STDBY
        • Option_Bytes_BOOT
        • Option_Bytes_BOR_Level
        • FLASH_Flags
        • FLASH_Keys
        • Timeout_definition
        • CMSIS_Legacy
      • FLASH_Private_Functions
        • FLASH Interface configuration functions
        • FLASH Memory Programming functions
        • DATA EEPROM Programming functions
        • Option Bytes Programming functions
        • Interrupts and flags management functions
    • FSMC
      • FSMC_Exported_Constants
        • FSMC_NORSRAM_Bank
        • NOR_SRAM_Controller
          • FSMC_Data_Address_Bus_Multiplexing
          • FSMC_Memory_Type
          • FSMC_Data_Width
          • FSMC_Burst_Access_Mode
          • FSMC_AsynchronousWait
          • FSMC_Wait_Signal_Polarity
          • FSMC_Wrap_Mode
          • FSMC_Wait_Timing
          • FSMC_Write_Operation
          • FSMC_Wait_Signal
          • FSMC_Extended_Mode
          • FSMC_Write_Burst
          • FSMC_Address_Setup_Time
          • FSMC_Address_Hold_Time
          • FSMC_Data_Setup_Time
          • FSMC_Bus_Turn_around_Duration
          • FSMC_CLK_Division
          • FSMC_Data_Latency
          • FSMC_Access_Mode
      • FSMC_Private_Functions
        • NOR/SRAM Controller functions
    • GPIO
      • Configuration_Mode_enumeration
      • Output_type_enumeration
      • Output_Maximum_frequency_enumeration
      • Configuration_Pull-Up_Pull-Down_enumeration
      • Bit_SET_and_Bit_RESET_enumeration
      • GPIO_Exported_Constants
        • GPIO_pins_define
        • GPIO_Pin_sources
        • GPIO_Alternat_function_selection_define
        • GPIO_Legacy
      • GPIO_Private_Functions
        • Initialization and Configuration
        • GPIO Read and Write
        • GPIO Alternate functions configuration functions
    • I2C
      • I2C_Exported_Constants
        • I2C_mode
        • I2C_duty_cycle_in_fast_mode
        • I2C_acknowledgement
        • I2C_transfer_direction
        • I2C_acknowledged_address
        • I2C_registers
        • I2C_SMBus_alert_pin_level
        • I2C_PEC_position
        • I2C_NACK_position
        • I2C_interrupts_definition
        • I2C_flags_definition
        • I2C_Events
        • I2C_own_address1
        • I2C_clock_speed
      • I2C_Private_Functions
        • Initialization and Configuration functions
        • Data transfers functions
        • PEC management functions
        • DMA transfers management functions
        • Interrupts events and flags management functions
    • IWDG
      • IWDG_Exported_Constants
        • IWDG_WriteAccess
        • IWDG_prescaler
        • IWDG_Flag
      • IWDG_Private_Functions
        • Prescaler and Counter configuration functions
        • IWDG activation function
        • Flag management function
    • LCD
      • LCD_Exported_Constants
        • LCD_Prescaler
        • LCD_Divider
        • LCD_Duty
        • LCD_Bias
        • LCD_Voltage_Source
        • LCD_Interrupts
        • LCD_PulseOnDuration
        • LCD_DeadTime
        • LCD_BlinkMode
        • LCD_BlinkFrequency
        • LCD_Contrast
        • LCD_Flag
        • LCD_RAMRegister
      • LCD_Private_Functions
        • Initialization and Configuration functions
        • LCD RAM memory write functions
        • Interrupts and flags management functions
    • OPAMP
      • OPAMP_Exported_Constants
        • OPAMP_Selection
        • OPAMP_Switches
        • OPAMP_Trimming
        • OPAMP_Input
        • OPAMP_TrimValue
        • OPAMP_PowerRange
      • OPAMP_Private_Functions
        • Initialization and configuration
        • Calibration functions
    • PWR
      • PWR_Exported_Constants
        • PWR_PVD_detection_level
        • PWR_WakeUp_Pins
        • PWR_Voltage_Scaling_Ranges
        • PWR_Regulator_state_is_Sleep_STOP_mode
        • PWR_SLEEP_mode_entry
        • PWR_STOP_mode_entry
        • PWR_Flag
      • PWR_Private_Functions
        • RTC Domain Access function
        • PVD configuration functions
        • WakeUp pins configuration functions
        • Ultra Low Power mode configuration functions
        • Voltage Scaling configuration functions
        • Low Power modes configuration functions
        • Flags management functions
    • RCC
      • RCC_Exported_Constants
        • RCC_HSE_configuration
        • RCC_MSI_Clock_Range
        • RCC_PLL_Clock_Source
        • RCC_PLL_Multiplication_Factor
        • RCC_PLL_Divider_Factor
        • RCC_System_Clock_Source
        • RCC_AHB_Clock_Source
        • RCC_APB1_APB2_Clock_Source
        • RCC_Interrupt_Source
        • RCC_LSE_Configuration
        • RCC_RTC_Clock_Source
        • RCC_AHB_Peripherals
        • RCC_APB2_Peripherals
        • RCC_APB1_Peripherals
        • RCC_MCO_Clock_Source
        • RCC_MCO_Output_Divider
        • RCC_Flag
      • RCC_Private_Functions
        • Internal and external clocks, PLL, CSS and MCO configuration functions
        • System AHB and APB busses clocks configuration functions
        • Peripheral clocks configuration functions
        • Interrupts and flags management functions
    • RTC
      • RTC_Exported_Constants
        • RTC_Hour_Formats
        • RTC_Asynchronous_Predivider
        • RTC_Synchronous_Predivider
        • RTC_Time_Definitions
        • RTC_AM_PM_Definitions
        • RTC_Year_Date_Definitions
        • RTC_Month_Date_Definitions
        • RTC_WeekDay_Definitions
        • RTC_Alarm_Definitions
        • RTC_AlarmDateWeekDay_Definitions
        • RTC_AlarmMask_Definitions
        • RTC_Alarms_Definitions
        • RTC_Alarm_Sub_Seconds_Masks_Definitions
        • RTC_Alarm_Sub_Seconds_Value
        • RTC_Wakeup_Timer_Definitions
        • RTC_Time_Stamp_Edges_definitions
        • RTC_Output_selection_Definitions
        • RTC_Output_Polarity_Definitions
        • RTC_Coarse_Calibration_Definitions
        • RTC_Calib_Output_selection_Definitions
        • RTC_Smooth_calib_period_Definitions
        • RTC_Smooth_calib_Plus_pulses_Definitions
        • RTC_Smooth_calib_Minus_pulses_Definitions
        • RTC_DayLightSaving_Definitions
        • RTC_Tamper_Trigger_Definitions
        • RTC_Tamper_Filter_Definitions
        • RTC_Tamper_Sampling_Frequencies_Definitions
        • RTC_Tamper_Pin_Precharge_Duration_Definitions
        • RTC_Tamper_Pins_Definitions
        • RTC_Output_Type_ALARM_OUT
        • RTC_Add_1_Second_Parameter_Definitions
        • RTC_Substract_Fraction_Of_Second_Value
        • RTC_Backup_Registers_Definitions
        • RTC_Input_parameter_format_definitions
        • RTC_Flags_Definitions
        • RTC_Interrupts_Definitions
        • RTC_Legacy
      • RTC_Private_Functions
        • Initialization and Configuration functions
        • Time and Date configuration functions
        • Alarms configuration functions
        • WakeUp Timer configuration functions
        • Daylight Saving configuration functions
        • Output pin Configuration function
        • Coarse and Smooth Calibrations configuration functions
        • TimeStamp configuration functions
        • Tampers configuration functions
        • Backup Data Registers configuration functions
        • Output Type Config configuration functions
        • Shift control synchronisation functions
        • Interrupts and flags management functions
    • SDIO
      • SDIO_Exported_Constants
        • SDIO_Clock_Edge
        • SDIO_Clock_Bypass
        • SDIO_Clock_Power_Save
        • SDIO_Bus_Wide
        • SDIO_Hardware_Flow_Control
        • SDIO_Power_State
        • SDIO_Interrupt_soucres
        • SDIO_Command_Index
        • SDIO_Response_Type
        • SDIO_Wait_Interrupt_State
        • SDIO_CPSM_State
        • SDIO_Response_Registers
        • SDIO_Data_Length
        • SDIO_Data_Block_Size
        • SDIO_Transfer_Direction
        • SDIO_Transfer_Type
        • SDIO_DPSM_State
        • SDIO_Flags
        • SDIO_Read_Wait_Mode
      • SDIO_Private_Functions
        • Initialization and Configuration functions
        • DMA transfers management functions
        • Command path state machine (CPSM) management functions
        • Data path state machine (DPSM) management functions
        • SDIO IO Cards mode management functions
        • CE-ATA mode management functions
        • Interrupts and flags management functions
    • SPI
      • SPI_Exported_Constants
        • SPI_data_direction
        • SPI_mode
        • SPI_data_size
        • SPI_Clock_Polarity
        • SPI_Clock_Phase
        • SPI_Slave_Select_management
        • SPI_BaudRate_Prescaler
        • SPI_MSB_LSB_transmission
        • SPI_I2S_Mode
        • SPI_I2S_Standard
        • SPI_I2S_Data_Format
        • SPI_I2S_MCLK_Output
        • SPI_I2S_Audio_Frequency
        • SPI_I2S_Clock_Polarity
        • SPI_I2S_DMA_transfer_requests
        • SPI_NSS_internal_software_management
        • SPI_CRC_Transmit_Receive
        • SPI_direction_transmit_receive
        • SPI_I2S_interrupts_definition
        • SPI_I2S_flags_definition
        • SPI_CRC_polynomial
        • SPI_I2S_Legacy
      • SPI_Private_Functions
        • Initialization and Configuration functions
        • Data transfers functions
        • Hardware CRC Calculation functions
        • DMA transfers management functions
        • Interrupts and flags management functions
    • SYSCFG
      • SYSCFG_Exported_Constants
        • EXTI_Port_Sources
        • EXTI_Pin_sources
        • SYSCFG_Memory_Remap_Config
        • RI_Resistor
        • RI_Channel
        • RI_ChannelSpeed
        • RI_InputCapture
        • TIM_Select
        • RI_InputCaptureRouting
        • RI_IOSwitch
        • RI_Port
        • define
      • SYSCFG_Private_Functions
        • SYSCFG Initialization and Configuration functions
        • RI Initialization and Configuration functions
    • TIM
      • TIM_Exported_constants
        • TIM_Output_Compare_and_PWM_modes
        • TIM_One_Pulse_Mode
        • TIM_Channel
        • TIM_Clock_Division_CKD
        • TIM_Counter_Mode
        • TIM_Output_Compare_Polarity
        • TIM_Output_Compare_state
        • TIM_Capture_Compare_state
        • TIM_Input_Capture_Polarity
        • TIM_Input_Capture_Selection
        • TIM_Input_Capture_Prescaler
        • TIM_interrupt_sources
        • TIM_DMA_Base_address
        • TIM_DMA_Burst_Length
        • TIM_DMA_sources
        • TIM_External_Trigger_Prescaler
        • TIM_Internal_Trigger_Selection
        • TIM_TIx_External_Clock_Source
        • TIM_External_Trigger_Polarity
        • TIM_Prescaler_Reload_Mode
        • TIM_Forced_Action
        • TIM_Encoder_Mode
        • TIM_Event_Source
        • TIM_Update_Source
        • TIM_Output_Compare_Preload_State
        • TIM_Output_Compare_Fast_State
        • TIM_Output_Compare_Clear_State
        • TIM_Trigger_Output_Source
        • TIM_Slave_Mode
        • TIM_Master_Slave_Mode
        • TIM_Flags
        • TIM_Input_Capture_Filer_Value
        • TIM_External_Trigger_Filter
        • TIM_OCReferenceClear
        • TIM_Remap
        • TIM_Legacy
      • TIM_Private_Functions
        • TimeBase management functions
        • Output Compare management functions
        • Input Capture management functions
        • Interrupts DMA and flags management functions
        • Clocks management functions
        • Synchronization management functions
        • Specific interface management functions
        • Specific remapping management function
    • USART
      • USART_Exported_Constants
        • USART_Word_Length
        • USART_Stop_Bits
        • USART_Parity
        • USART_Mode
        • USART_Hardware_Flow_Control
        • USART_Clock
        • USART_Clock_Polarity
        • USART_Clock_Phase
        • USART_Last_Bit
        • USART_Interrupt_definition
          • USART_Legacy
        • USART_DMA_Requests
        • USART_WakeUp_methods
        • USART_LIN_Break_Detection_Length
        • USART_IrDA_Low_Power
        • USART_Flags
      • USART_Private_Functions
        • Initialization and Configuration functions
        • Data transfers functions
        • MultiProcessor Communication functions
        • LIN mode functions
        • Halfduplex mode function
        • Smartcard mode functions
        • IrDA mode functions
        • DMA transfers management functions
        • Interrupts and flags management functions
    • WWDG
      • WWDG_Exported_Constants
        • WWDG_Prescaler
      • WWDG_Private_Functions
        • Prescaler, Refresh window and Counter configuration functions
        • WWDG activation functions
        • Interrupts and flags management functions


STM32L1xx Standard Peripherals Firmware Library: Related Pages

Related Pages

Here is a list of all related documentation pages:
  • STM32L1xx Standard Peripheral's Drivers


Release Notes for STM32L1xx Standard Peripherals Library

Release Notes for STM32L1xx Standard Peripherals Library (StdPeriph_Lib)

Copyright © 2012 STMicroelectronics

Contents

  1. STM32L1xx Standard Peripherals Library update history
  2. License

STM32L1xx Standard Peripherals Library update history

V1.1.0 / 24-January-2012

Main Changes

  • Official version for STM32L1xx Ultra Low Power High-density and Medium-density Plus devices.

Contents

  • Cortex-M CMSIS V2.1 (release notes)
  • STM32L1xx CMSIS V1.1.0 (release notes)
  • STM32L1xx_StdPeriph_Driver V1.1.0 (release notes)

Development Toolchains

  • IAR Embedded Workbench for ARM (EWARM) toolchain V6.30
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V4.23
  • TASKING VX-toolset for ARM Cortex-M (TASKING) toolchain v4.1r1
  • STM32 TrueSTUDIO software (TrueSTUDIO) toolchain v2.3.0
  • Raisonance RIDE7 software (RIDE) toolchain (RIDE7 IDE:7.36, RKitARM for RIDE7:1.38)

V1.0.0 / 31-December-2010

Main Changes

  • First official release for STM32L1xx Ultra Low Power Medium-density devices.

Contents

  • STM32L1xx CMSIS V1.0.0 (release notes)
  • STM32L1xx_StdPeriph_Driver V1.0.0 (release notes)
  • STM32L1xx_StdPeriph_Examples V1.0.0 (release notes)
  • STM32L1xx_StdPeriph_Template V1.0.0 (release notes)
  • STM32_EVAL V4.4.0 (release notes)

Development Toolchains

  • IAR Embedded Workbench for ARM (EWARM) toolchain V5.50.5
  • Hitex IDE/Debugger (HiTOP) toolchain V5.40.0051
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V4.13
  • Raisonance IDE RIDE7 (RIDE) toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)

  • Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain V1.4.0
    • A software patch is needed to use STM32L1xx Ultra Low Power Medium-density devices with this version, click here to download.

    License

    The use of this STM32 Firmware is governed by the terms and conditions of the License Agreement available in the root of this package.

    For complete documentation on STMicroelectronics Microcontrollers visit www.st.com


STM32L1xx Standard Peripherals Firmware Library: stdperiphlib_drivers.txt File Reference

  • File List
  • Globals

stdperiphlib_drivers.txt File Reference

STM32L1xx Standard Peripherals Library: Footer

For complete documentation on STM32L (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32L


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx.h Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx
  • Include

stm32l1xx.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
00008   *          This file contains all the peripheral register's definitions, bits
00009   *          definitions and memory mapping for STM32L1xx High-, Medium-density
00010   *          and Medium-density Plus devices.
00011   *
00012   *          The file is the unique include file that the application programmer
00013   *          is using in the C source code, usually in main.c. This file contains:
00014   *           - Configuration section that allows to select:
00015   *              - The device used in the target application
00016   *              - To use or not the peripheral’s drivers in application code(i.e.
00017   *                code will be based on direct access to peripheral’s registers
00018   *                rather than drivers API), this option is controlled by
00019   *                "#define USE_STDPERIPH_DRIVER"
00020   *              - To change few application-specific parameters such as the HSE
00021   *                crystal frequency
00022   *           - Data structures and the address mapping for all peripherals
00023   *           - Peripheral's registers declarations and bits definition
00024   *           - Macros to access peripheral’s registers hardware
00025   *
00026   ******************************************************************************
00027   * @attention
00028   *
00029   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00030   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00031   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00032   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00033   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00034   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00035   *
00036   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00037   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00038   *
00039   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00040   ******************************************************************************
00041   */
00042
00043 /** @addtogroup CMSIS
00044   * @{
00045   */
00046
00047 /** @addtogroup stm32l1xx
00048   * @{
00049   */
00050
00051 #ifndef __STM32L1XX_H
00052 #define __STM32L1XX_H
00053
00054 #ifdef __cplusplus
00055  extern "C" {
00056 #endif
00057
00058 /** @addtogroup Library_configuration_section
00059   * @{
00060   */
00061
00062 /* Uncomment the line below according to the target STM32L device used in your
00063    application
00064   */
00065
00066 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
00067   /* #define STM32L1XX_MD  */   /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
00068   /* #define STM32L1XX_MDP */   /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */
00069   #define STM32L1XX_HD    /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */
00070 #endif
00071 /*  Tip: To avoid modifying this file each time you need to switch between these
00072         devices, you can define the device in your toolchain compiler preprocessor.
00073
00074  - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
00075    microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
00076  - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and
00077    STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
00078  - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx
00079    microcontrollers where the Flash memory density is 384 Kbytes.
00080   */
00081
00082 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
00083  #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
00084 #endif
00085
00086 #if !defined  USE_STDPERIPH_DRIVER
00087 /**
00088  * @brief Comment the line below if you will not use the peripherals drivers.
00089    In this case, these drivers will not be included and the application code will
00090    be based on direct access to peripherals registers
00091    */
00092   /*#define USE_STDPERIPH_DRIVER*/
00093 #endif
00094
00095 /**
00096  * @brief In the following line adjust the value of External High Speed oscillator (HSE)
00097    used in your application
00098
00099    Tip: To avoid modifying this file each time you need to use different HSE, you
00100         can define the HSE value in your toolchain compiler preprocessor.
00101   */
00102 #if !defined  (HSE_VALUE)
00103 #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
00104 #endif
00105
00106 /**
00107  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
00108    Timeout value
00109    */
00110 #if !defined  (HSE_STARTUP_TIMEOUT)
00111 #define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
00112 #endif
00113
00114 /**
00115  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
00116    Timeout value
00117    */
00118 #if !defined  (HSI_STARTUP_TIMEOUT)
00119 #define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
00120 #endif
00121
00122 #if !defined  (HSI_VALUE)
00123 #define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
00124                                              The real value may vary depending on the variations
00125                                              in voltage and temperature.  */
00126 #endif
00127
00128 #if !defined  (LSI_VALUE)
00129 #define LSI_VALUE  ((uint32_t)37000)    /*!< Value of the Internal Low Speed oscillator in Hz
00130                                              The real value may vary depending on the variations
00131                                              in voltage and temperature.  */
00132 #endif
00133
00134 #if !defined  (LSE_VALUE)
00135 #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
00136 #endif
00137
00138 /**
00139  * @brief STM32L1xx Standard Peripheral Library version number V1.1.0
00140    */
00141 #define __STM32L1XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
00142 #define __STM32L1XX_STDPERIPH_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
00143 #define __STM32L1XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
00144 #define __STM32L1XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00145 #define __STM32L1XX_STDPERIPH_VERSION       ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
00146                                              |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
00147                                              |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
00148                                              |(__STM32L1XX_STDPERIPH_VERSION_RC))
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @addtogroup Configuration_section_for_CMSIS
00155   * @{
00156   */
00157
00158 /**
00159  * @brief STM32L1xx Interrupt Number Definition, according to the selected device
00160  *        in @ref Library_configuration_section
00161  */
00162 #define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
00163 #define __MPU_PRESENT             1 /*!< STM32L provides MPU                          */
00164 #define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
00165 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
00166
00167 /*!< Interrupt Number Definition */
00168 typedef enum IRQn
00169 {
00170 /******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
00171   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
00172   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
00173   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
00174   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
00175   SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
00176   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
00177   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
00178   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
00179
00180 /******  STM32L specific Interrupt Numbers ***********************************************************/
00181   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
00182   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
00183   TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and Time Stamp through EXTI Line Interrupts      */
00184   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
00185   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
00186   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
00187   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
00188   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
00189   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
00190   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
00191   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
00192   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
00193   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
00194   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
00195   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
00196   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
00197   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
00198   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
00199   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
00200   USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
00201   USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
00202   DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
00203   COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
00204   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
00205   LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
00206   TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
00207   TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
00208   TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
00209   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
00210   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
00211   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
00212   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
00213   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
00214   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
00215   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
00216   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
00217   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
00218   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
00219   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
00220   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
00221   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
00222   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
00223   USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
00224   TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
00225 #ifdef STM32L1XX_MD
00226   TIM7_IRQn                   = 44      /*!< TIM7 global Interrupt                                   */
00227 #endif
00228
00229 #ifdef STM32L1XX_MDP
00230   TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
00231   TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
00232   SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
00233   DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
00234   DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
00235   DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
00236   DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
00237   DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
00238   AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
00239   COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
00240 #endif
00241
00242 #ifdef STM32L1XX_HD
00243   TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
00244   SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
00245   TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
00246   SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
00247   UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
00248   UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
00249   DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
00250   DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
00251   DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
00252   DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
00253   DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
00254   AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
00255   COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
00256 #endif
00257 } IRQn_Type;
00258
00259 /**
00260   * @}
00261   */
00262
00263 #include "core_cm3.h"
00264 #include "system_stm32l1xx.h"
00265 #include <stdint.h>
00266
00267 /** @addtogroup Exported_types
00268   * @{
00269   */
00270
00271 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
00272
00273 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00274 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
00275
00276 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
00277
00278 /**
00279   * @brief  __RAM_FUNC definition
00280   */
00281 #if defined ( __CC_ARM   )
00282 /* ARM Compiler
00283    ------------
00284    RAM functions are defined using the toolchain options.
00285    Functions that are executed in RAM should reside in a separate source
00286    module. Using the 'Options for File' dialog you can simply change the
00287    'Code / Const' area of a module to a memory space in physical RAM.
00288    Available memory areas are declared in the 'Target' tab of the
00289    'Options for Target' dialog.
00290 */
00291  #define __RAM_FUNC FLASH_Status
00292
00293 #elif defined ( __ICCARM__ )
00294 /* ICCARM Compiler
00295    ---------------
00296    RAM functions are defined using a specific toolchain keyword "__ramfunc".
00297 */
00298  #define __RAM_FUNC __ramfunc FLASH_Status
00299
00300 #elif defined   (  __GNUC__  )
00301 /* GNU Compiler
00302    ------------
00303    RAM functions are defined using a specific toolchain attribute
00304    "__attribute__((section(".data")))".
00305 */
00306  #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
00307
00308 #elif defined   (  __TASKING__  )
00309 /* TASKING Compiler
00310    ----------------
00311    RAM functions are defined using a specific toolchain pragma. This pragma is
00312    defined in the stm32l1xx_flash_ramfunc.c
00313 */
00314  #define __RAM_FUNC  FLASH_Status
00315
00316 #endif
00317
00318 /**
00319   * @}
00320   */
00321
00322 /** @addtogroup Peripheral_registers_structures
00323   * @{
00324   */
00325
00326 /**
00327   * @brief Analog to Digital Converter
00328   */
00329
00330 typedef struct
00331 {
00332   __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
00333   __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
00334   __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
00335   __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
00336   __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
00337   __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
00338   __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
00339   __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
00340   __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
00341   __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
00342   __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
00343   __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
00344   __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
00345   __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
00346   __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
00347   __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
00348   __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
00349   __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
00350   __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
00351   __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
00352   __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
00353   __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
00354   __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
00355   __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
00356 } ADC_TypeDef;
00357
00358 typedef struct
00359 {
00360   __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
00361   __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
00362 } ADC_Common_TypeDef;
00363
00364
00365 /**
00366   * @brief AES hardware accelerator
00367   */
00368
00369 typedef struct
00370 {
00371   __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
00372   __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
00373   __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
00374   __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
00375   __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
00376   __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
00377   __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
00378   __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
00379   __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
00380   __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
00381   __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
00382   __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
00383 } AES_TypeDef;
00384
00385 /**
00386   * @brief Comparator
00387   */
00388
00389 typedef struct
00390 {
00391   __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
00392 } COMP_TypeDef;
00393
00394 /**
00395   * @brief CRC calculation unit
00396   */
00397
00398 typedef struct
00399 {
00400   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
00401   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
00402   uint8_t   RESERVED0;        /*!< Reserved,                                    0x05                 */
00403   uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
00404   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
00405 } CRC_TypeDef;
00406
00407 /**
00408   * @brief Digital to Analog Converter
00409   */
00410
00411 typedef struct
00412 {
00413   __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
00414   __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
00415   __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
00416   __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
00417   __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
00418   __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
00419   __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
00420   __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
00421   __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
00422   __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
00423   __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
00424   __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
00425   __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
00426   __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
00427 } DAC_TypeDef;
00428
00429 /**
00430   * @brief Debug MCU
00431   */
00432
00433 typedef struct
00434 {
00435   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
00436   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
00437   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
00438   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
00439 }DBGMCU_TypeDef;
00440
00441 /**
00442   * @brief DMA Controller
00443   */
00444
00445 typedef struct
00446 {
00447   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
00448   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
00449   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
00450   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
00451 } DMA_Channel_TypeDef;
00452
00453 typedef struct
00454 {
00455   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
00456   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
00457 } DMA_TypeDef;
00458
00459 /**
00460   * @brief External Interrupt/Event Controller
00461   */
00462
00463 typedef struct
00464 {
00465   __IO uint32_t IMR;          /*!< EXTI interrupt mask register,                 Address offset: 0x00 */
00466   __IO uint32_t EMR;          /*!< EXTI event mask register,                     Address offset: 0x04 */
00467   __IO uint32_t RTSR;         /*!< EXTI rising edge trigger selection register,  Address offset: 0x08 */
00468   __IO uint32_t FTSR;         /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
00469   __IO uint32_t SWIER;        /*!< EXTI software interrupt event register,       Address offset: 0x10 */
00470   __IO uint32_t PR;           /*!< EXTI pending register,                        Address offset: 0x14 */
00471 } EXTI_TypeDef;
00472
00473 /**
00474   * @brief FLASH Registers
00475   */
00476
00477 typedef struct
00478 {
00479   __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
00480   __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
00481   __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
00482   __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
00483   __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
00484   __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
00485   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
00486   __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
00487   __IO uint32_t WRPR;         /*!< Write protection register,                   Address offset: 0x20 */
00488   uint32_t   RESERVED[23];    /*!< Reserved,                                    0x24                 */
00489   __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x28 */
00490   __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x2C */
00491 } FLASH_TypeDef;
00492
00493 /**
00494   * @brief Option Bytes Registers
00495   */
00496
00497 typedef struct
00498 {
00499   __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
00500   __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
00501   __IO uint32_t WRP01;             /*!< write protection register 0 1,          Address offset: 0x08 */
00502   __IO uint32_t WRP23;             /*!< write protection register 2 3,          Address offset: 0x0C */
00503   __IO uint32_t WRP45;             /*!< write protection register 4 5,          Address offset: 0x10 */
00504   __IO uint32_t WRP67;             /*!< write protection register 6 7,          Address offset: 0x14 */
00505   __IO uint32_t WRP89;             /*!< write protection register 8 9,          Address offset: 0x18 */
00506   __IO uint32_t WRP1011;           /*!< write protection register 10 11,        Address offset: 0x1C */
00507 } OB_TypeDef;
00508
00509 /**
00510   * @brief Operational Amplifier (OPAMP)
00511   */
00512
00513 typedef struct
00514 {
00515   __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
00516   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
00517   __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
00518 } OPAMP_TypeDef;
00519
00520 /**
00521   * @brief Flexible Static Memory Controller
00522   */
00523
00524 typedef struct
00525 {
00526   __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
00527 } FSMC_Bank1_TypeDef;
00528
00529 /**
00530   * @brief Flexible Static Memory Controller Bank1E
00531   */
00532
00533 typedef struct
00534 {
00535   __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
00536 } FSMC_Bank1E_TypeDef;
00537
00538 /**
00539   * @brief General Purpose IO
00540   */
00541
00542 typedef struct
00543 {
00544   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
00545   __IO uint16_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
00546   uint16_t RESERVED0;         /*!< Reserved,                                    0x06                      */
00547   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
00548   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
00549   __IO uint16_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
00550   uint16_t RESERVED1;         /*!< Reserved,                                    0x12                      */
00551   __IO uint16_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
00552   uint16_t RESERVED2;         /*!< Reserved,                                    0x16                      */
00553   __IO uint16_t BSRRL;        /*!< GPIO port bit set/reset low registerBSRR,    Address offset: 0x18      */
00554   __IO uint16_t BSRRH;        /*!< GPIO port bit set/reset high registerBSRR,   Address offset: 0x1A      */
00555   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
00556   __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,        Address offset: 0x20-0x24 */
00557   __IO uint16_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
00558   uint16_t RESERVED3;         /*!< Reserved,                                    0x2A                      */
00559 } GPIO_TypeDef;
00560
00561 /**
00562   * @brief SysTem Configuration
00563   */
00564
00565 typedef struct
00566 {
00567   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
00568   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
00569   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
00570 } SYSCFG_TypeDef;
00571
00572 /**
00573   * @brief Inter-integrated Circuit Interface
00574   */
00575
00576 typedef struct
00577 {
00578   __IO uint16_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
00579   uint16_t  RESERVED0;        /*!< Reserved,                                    0x02                 */
00580   __IO uint16_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
00581   uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
00582   __IO uint16_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
00583   uint16_t  RESERVED2;        /*!< Reserved,                                    0x0A                 */
00584   __IO uint16_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
00585   uint16_t  RESERVED3;        /*!< Reserved,                                    0x0E                 */
00586   __IO uint16_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
00587   uint16_t  RESERVED4;        /*!< Reserved,                                    0x12                 */
00588   __IO uint16_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
00589   uint16_t  RESERVED5;        /*!< Reserved,                                    0x16                 */
00590   __IO uint16_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
00591   uint16_t  RESERVED6;        /*!< Reserved,                                    0x1A                 */
00592   __IO uint16_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
00593   uint16_t  RESERVED7;        /*!< Reserved,                                    0x1E                 */
00594   __IO uint16_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
00595   uint16_t  RESERVED8;        /*!< Reserved,                                    0x22                 */
00596 } I2C_TypeDef;
00597
00598 /**
00599   * @brief Independent WATCHDOG
00600   */
00601
00602 typedef struct
00603 {
00604   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
00605   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
00606   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
00607   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
00608 } IWDG_TypeDef;
00609
00610
00611 /**
00612   * @brief LCD
00613   */
00614
00615 typedef struct
00616 {
00617   __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
00618   __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
00619   __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
00620   __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
00621   uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
00622   __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */
00623 } LCD_TypeDef;
00624
00625 /**
00626   * @brief Power Control
00627   */
00628
00629 typedef struct
00630 {
00631   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
00632   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
00633 } PWR_TypeDef;
00634
00635 /**
00636   * @brief Reset and Clock Control
00637   */
00638
00639 typedef struct
00640 {
00641   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
00642   __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
00643   __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
00644   __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
00645   __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
00646   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
00647   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
00648   __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
00649   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
00650   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
00651   __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
00652   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
00653   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
00654   __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
00655 } RCC_TypeDef;
00656
00657 /**
00658   * @brief Routing Interface
00659   */
00660
00661 typedef struct
00662 {
00663   __IO uint32_t ICR;       /*!< RI input capture register,             Address offset: 0x00 */
00664   __IO uint32_t ASCR1;     /*!< RI analog switches control register,   Address offset: 0x04 */
00665   __IO uint32_t ASCR2;     /*!< RI analog switch control register 2,   Address offset: 0x08 */
00666   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,       Address offset: 0x0C */
00667   __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,       Address offset: 0x10 */
00668   __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,       Address offset: 0x14 */
00669   __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,       Address offset: 0x18 */
00670 } RI_TypeDef;
00671
00672 /**
00673   * @brief Real-Time Clock
00674   */
00675
00676 typedef struct
00677 {
00678   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
00679   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
00680   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
00681   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
00682   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
00683   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
00684   __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
00685   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
00686   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
00687   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
00688   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
00689   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
00690   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
00691   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
00692   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
00693   __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
00694   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
00695   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
00696   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
00697   uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
00698   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
00699   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
00700   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
00701   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
00702   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
00703   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
00704   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
00705   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
00706   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
00707   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
00708   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
00709   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
00710   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
00711   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
00712   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
00713   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
00714   __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
00715   __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
00716   __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
00717   __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
00718   __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
00719   __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
00720   __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
00721   __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
00722   __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
00723   __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
00724   __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
00725   __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
00726   __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
00727   __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
00728   __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
00729   __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
00730 } RTC_TypeDef;
00731
00732 /**
00733   * @brief SD host Interface
00734   */
00735
00736 typedef struct
00737 {
00738   __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
00739   __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
00740   __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
00741   __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
00742   __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
00743   __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
00744   __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
00745   __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
00746   __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
00747   __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
00748   __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
00749   __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
00750   __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
00751   __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
00752   __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
00753   __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
00754   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
00755   __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
00756   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
00757   __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
00758 } SDIO_TypeDef;
00759
00760 /**
00761   * @brief Serial Peripheral Interface
00762   */
00763
00764 typedef struct
00765 {
00766   __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
00767   uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
00768   __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
00769   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
00770   __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
00771   uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
00772   __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
00773   uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
00774   __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
00775   uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
00776   __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
00777   uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
00778   __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
00779   uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
00780   __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
00781   uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
00782   __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
00783   uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
00784 } SPI_TypeDef;
00785
00786 /**
00787   * @brief TIM
00788   */
00789
00790 typedef struct
00791 {
00792   __IO uint16_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
00793   uint16_t      RESERVED0;    /*!< Reserved, 0x02                                            */
00794   __IO uint16_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
00795   uint16_t      RESERVED1;    /*!< Reserved, 0x06                                            */
00796   __IO uint16_t SMCR;         /*!< TIM slave mode control register,     Address offset: 0x08 */
00797   uint16_t      RESERVED2;    /*!< Reserved, 0x0A                                            */
00798   __IO uint16_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
00799   uint16_t      RESERVED3;    /*!< Reserved, 0x0E                                            */
00800   __IO uint16_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
00801   uint16_t      RESERVED4;    /*!< Reserved, 0x12                                            */
00802   __IO uint16_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
00803   uint16_t      RESERVED5;    /*!< Reserved, 0x16                                            */
00804   __IO uint16_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
00805   uint16_t      RESERVED6;    /*!< Reserved, 0x1A                                            */
00806   __IO uint16_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
00807   uint16_t      RESERVED7;    /*!< Reserved, 0x1E                                            */
00808   __IO uint16_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
00809   uint16_t      RESERVED8;    /*!< Reserved, 0x22                                            */
00810   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
00811   __IO uint16_t PSC;          /*!< TIM prescaler,                       Address offset: 0x28 */
00812   uint16_t      RESERVED10;   /*!< Reserved, 0x2A                                            */
00813   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
00814   uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
00815   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
00816   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
00817   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
00818   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
00819   uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
00820   __IO uint16_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
00821   uint16_t      RESERVED18;   /*!< Reserved, 0x4A                                            */
00822   __IO uint16_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
00823   uint16_t      RESERVED19;   /*!< Reserved, 0x4E                                            */
00824   __IO uint16_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
00825   uint16_t      RESERVED20;   /*!< Reserved, 0x52                                            */
00826 } TIM_TypeDef;
00827
00828 /**
00829   * @brief Universal Synchronous Asynchronous Receiver Transmitter
00830   */
00831
00832 typedef struct
00833 {
00834   __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
00835   uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
00836   __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
00837   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
00838   __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
00839   uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
00840   __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
00841   uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
00842   __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
00843   uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
00844   __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
00845   uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
00846   __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
00847   uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
00848 } USART_TypeDef;
00849
00850 /**
00851   * @brief Window WATCHDOG
00852   */
00853
00854 typedef struct
00855 {
00856   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
00857   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
00858   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
00859 } WWDG_TypeDef;
00860
00861 /**
00862   * @}
00863   */
00864
00865 /** @addtogroup Peripheral_memory_map
00866   * @{
00867   */
00868
00869 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
00870 #define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
00871 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
00872
00873 #define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
00874 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
00875
00876 #define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
00877
00878 /*!< Peripheral memory map */
00879 #define APB1PERIPH_BASE       PERIPH_BASE
00880 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
00881 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
00882
00883 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
00884 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
00885 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
00886 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
00887 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
00888 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
00889 #define LCD_BASE              (APB1PERIPH_BASE + 0x2400)
00890 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
00891 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
00892 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
00893 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
00894 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
00895 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
00896 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
00897 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
00898 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
00899 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
00900 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
00901 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
00902 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
00903 #define COMP_BASE             (APB1PERIPH_BASE + 0x7C00)
00904 #define RI_BASE               (APB1PERIPH_BASE + 0x7C04)
00905 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x7C5C)
00906
00907 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
00908 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
00909 #define TIM9_BASE             (APB2PERIPH_BASE + 0x0800)
00910 #define TIM10_BASE            (APB2PERIPH_BASE + 0x0C00)
00911 #define TIM11_BASE            (APB2PERIPH_BASE + 0x1000)
00912 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
00913 #define ADC_BASE              (APB2PERIPH_BASE + 0x2700)
00914 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
00915 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
00916 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
00917
00918 #define GPIOA_BASE            (AHBPERIPH_BASE + 0x0000)
00919 #define GPIOB_BASE            (AHBPERIPH_BASE + 0x0400)
00920 #define GPIOC_BASE            (AHBPERIPH_BASE + 0x0800)
00921 #define GPIOD_BASE            (AHBPERIPH_BASE + 0x0C00)
00922 #define GPIOE_BASE            (AHBPERIPH_BASE + 0x1000)
00923 #define GPIOH_BASE            (AHBPERIPH_BASE + 0x1400)
00924 #define GPIOF_BASE            (AHBPERIPH_BASE + 0x1800)
00925 #define GPIOG_BASE            (AHBPERIPH_BASE + 0x1C00)
00926 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
00927 #define RCC_BASE              (AHBPERIPH_BASE + 0x3800)
00928
00929
00930 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
00931 #define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
00932
00933 #define DMA1_BASE             (AHBPERIPH_BASE + 0x6000)
00934 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008)
00935 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001C)
00936 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030)
00937 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044)
00938 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058)
00939 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006C)
00940 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080)
00941
00942 #define DMA2_BASE             (AHBPERIPH_BASE + 0x6400)
00943 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008)
00944 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001C)
00945 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030)
00946 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044)
00947 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058)
00948
00949 #define AES_BASE              ((uint32_t)0x50060000)
00950
00951 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
00952 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
00953
00954 #define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
00955
00956 /**
00957   * @}
00958   */
00959
00960 /** @addtogroup Peripheral_declaration
00961   * @{
00962   */
00963
00964 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
00965 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
00966 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
00967 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
00968 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
00969 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
00970 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
00971 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
00972 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
00973 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
00974 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
00975 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
00976 #define USART2              ((USART_TypeDef *) USART2_BASE)
00977 #define USART3              ((USART_TypeDef *) USART3_BASE)
00978 #define UART4               ((USART_TypeDef *) UART4_BASE)
00979 #define UART5               ((USART_TypeDef *) UART5_BASE)
00980 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
00981 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
00982 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
00983 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
00984 #define COMP                ((COMP_TypeDef *) COMP_BASE)
00985 #define RI                  ((RI_TypeDef *) RI_BASE)
00986 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
00987 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
00988 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
00989
00990 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
00991 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
00992 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
00993 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
00994 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
00995 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
00996 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
00997 #define USART1              ((USART_TypeDef *) USART1_BASE)
00998 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
00999 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
01000 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
01001 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
01002 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
01003 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
01004 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
01005 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
01006
01007 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
01008 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
01009 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
01010 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
01011 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
01012 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
01013
01014 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
01015 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
01016
01017 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
01018 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
01019 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
01020 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
01021 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
01022 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
01023 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
01024 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
01025
01026 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
01027 #define OB                  ((OB_TypeDef *) OB_BASE)
01028
01029 #define AES                 ((AES_TypeDef *) AES_BASE)
01030
01031 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
01032 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
01033
01034 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
01035
01036 /**
01037   * @}
01038   */
01039
01040 /** @addtogroup Exported_constants
01041   * @{
01042   */
01043
01044 /** @addtogroup Peripheral_Registers_Bits_Definition
01045   * @{
01046   */
01047
01048 /******************************************************************************/
01049 /*                         Peripheral Registers Bits Definition               */
01050 /******************************************************************************/
01051 /******************************************************************************/
01052 /*                                                                            */
01053 /*                      Analog to Digital Converter (ADC)                     */
01054 /*                                                                            */
01055 /******************************************************************************/
01056
01057 /********************  Bit definition for ADC_SR register  ********************/
01058 #define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
01059 #define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
01060 #define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
01061 #define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
01062 #define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
01063 #define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
01064 #define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
01065 #define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
01066 #define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
01067
01068 /*******************  Bit definition for ADC_CR1 register  ********************/
01069 #define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
01070 #define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
01071 #define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
01072 #define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
01073 #define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
01074 #define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
01075
01076 #define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
01077 #define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
01078 #define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
01079 #define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
01080 #define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
01081 #define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
01082 #define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
01083 #define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
01084
01085 #define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
01086 #define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
01087 #define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
01088 #define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
01089
01090 #define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
01091 #define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
01092
01093 #define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
01094 #define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
01095
01096 #define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
01097 #define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
01098 #define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
01099
01100 #define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
01101
01102 /*******************  Bit definition for ADC_CR2 register  ********************/
01103 #define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
01104 #define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
01105 #define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
01106
01107 #define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
01108 #define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
01109 #define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
01110 #define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
01111
01112 #define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
01113 #define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
01114 #define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
01115 #define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
01116
01117 #define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
01118 #define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
01119 #define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
01120 #define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
01121 #define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
01122
01123 #define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
01124 #define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
01125 #define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
01126
01127 #define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
01128
01129 #define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
01130 #define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
01131 #define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
01132 #define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
01133 #define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
01134
01135 #define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
01136 #define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
01137 #define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
01138
01139 #define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
01140
01141 /******************  Bit definition for ADC_SMPR1 register  *******************/
01142 #define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
01143 #define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
01144 #define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
01145 #define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
01146
01147 #define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
01148 #define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
01149 #define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
01150 #define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
01151
01152 #define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
01153 #define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
01154 #define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
01155 #define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
01156
01157 #define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
01158 #define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
01159 #define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
01160 #define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
01161
01162 #define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
01163 #define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
01164 #define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
01165 #define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
01166
01167 #define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
01168 #define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
01169 #define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
01170 #define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
01171
01172 #define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
01173 #define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
01174 #define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
01175 #define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
01176
01177 #define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
01178 #define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
01179 #define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
01180 #define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
01181
01182 #define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
01183 #define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
01184 #define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
01185 #define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
01186
01187 #define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
01188 #define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
01189 #define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
01190 #define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
01191
01192 /******************  Bit definition for ADC_SMPR2 register  *******************/
01193 #define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
01194 #define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
01195 #define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
01196 #define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
01197
01198 #define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
01199 #define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
01200 #define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
01201 #define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
01202
01203 #define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
01204 #define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
01205 #define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
01206 #define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
01207
01208 #define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
01209 #define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
01210 #define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
01211 #define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
01212
01213 #define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
01214 #define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
01215 #define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
01216 #define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
01217
01218 #define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
01219 #define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
01220 #define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
01221 #define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
01222
01223 #define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
01224 #define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
01225 #define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
01226 #define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
01227
01228 #define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
01229 #define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
01230 #define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
01231 #define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
01232
01233 #define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
01234 #define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
01235 #define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
01236 #define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
01237
01238 #define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
01239 #define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
01240 #define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
01241 #define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
01242
01243 /******************  Bit definition for ADC_SMPR3 register  *******************/
01244 #define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
01245 #define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
01246 #define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
01247 #define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
01248
01249 #define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
01250 #define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
01251 #define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
01252 #define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
01253
01254 #define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
01255 #define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
01256 #define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
01257 #define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
01258
01259 #define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
01260 #define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
01261 #define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
01262 #define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
01263
01264 #define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
01265 #define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
01266 #define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
01267 #define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
01268
01269 #define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
01270 #define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
01271 #define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
01272 #define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
01273
01274 #define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
01275 #define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
01276 #define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
01277 #define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
01278
01279 #define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
01280 #define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
01281 #define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
01282 #define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
01283
01284 #define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
01285 #define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
01286 #define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
01287 #define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
01288
01289 #define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
01290 #define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
01291 #define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
01292 #define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
01293
01294 /******************  Bit definition for ADC_JOFR1 register  *******************/
01295 #define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
01296
01297 /******************  Bit definition for ADC_JOFR2 register  *******************/
01298 #define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
01299
01300 /******************  Bit definition for ADC_JOFR3 register  *******************/
01301 #define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
01302
01303 /******************  Bit definition for ADC_JOFR4 register  *******************/
01304 #define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
01305
01306 /*******************  Bit definition for ADC_HTR register  ********************/
01307 #define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
01308
01309 /*******************  Bit definition for ADC_LTR register  ********************/
01310 #define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
01311
01312 /*******************  Bit definition for ADC_SQR1 register  *******************/
01313 #define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
01314 #define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
01315 #define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
01316 #define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
01317 #define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
01318
01319 #define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
01320 #define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
01321 #define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
01322 #define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
01323 #define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
01324 #define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
01325
01326 #define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
01327 #define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
01328 #define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
01329 #define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
01330 #define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
01331 #define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
01332
01333 #define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
01334 #define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
01335 #define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
01336 #define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
01337 #define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
01338 #define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
01339
01340 #define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
01341 #define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
01342 #define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
01343 #define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
01344 #define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
01345 #define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
01346
01347 /*******************  Bit definition for ADC_SQR2 register  *******************/
01348 #define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
01349 #define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
01350 #define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
01351 #define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
01352 #define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
01353 #define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
01354
01355 #define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
01356 #define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
01357 #define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
01358 #define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
01359 #define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
01360 #define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
01361
01362 #define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
01363 #define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
01364 #define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
01365 #define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
01366 #define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
01367 #define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
01368
01369 #define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
01370 #define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
01371 #define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
01372 #define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
01373 #define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
01374 #define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
01375
01376 #define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
01377 #define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
01378 #define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
01379 #define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
01380 #define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
01381 #define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
01382
01383 #define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
01384 #define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
01385 #define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
01386 #define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
01387 #define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
01388 #define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
01389
01390 /*******************  Bit definition for ADC_SQR3 register  *******************/
01391 #define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
01392 #define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
01393 #define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
01394 #define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
01395 #define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
01396 #define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
01397
01398 #define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
01399 #define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
01400 #define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
01401 #define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
01402 #define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
01403 #define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
01404
01405 #define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
01406 #define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
01407 #define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
01408 #define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
01409 #define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
01410 #define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
01411
01412 #define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
01413 #define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
01414 #define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
01415 #define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
01416 #define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
01417 #define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
01418
01419 #define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
01420 #define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
01421 #define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
01422 #define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
01423 #define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
01424 #define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
01425
01426 #define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
01427 #define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
01428 #define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
01429 #define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
01430 #define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
01431 #define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
01432
01433 /*******************  Bit definition for ADC_SQR4 register  *******************/
01434 #define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
01435 #define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
01436 #define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
01437 #define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
01438 #define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
01439 #define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
01440
01441 #define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
01442 #define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
01443 #define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
01444 #define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
01445 #define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
01446 #define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
01447
01448 #define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
01449 #define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
01450 #define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
01451 #define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
01452 #define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
01453 #define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
01454
01455 #define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
01456 #define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
01457 #define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
01458 #define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
01459 #define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
01460 #define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
01461
01462 #define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
01463 #define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
01464 #define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
01465 #define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
01466 #define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
01467 #define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
01468
01469 #define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
01470 #define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
01471 #define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
01472 #define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
01473 #define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
01474 #define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
01475
01476 /*******************  Bit definition for ADC_SQR5 register  *******************/
01477 #define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
01478 #define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
01479 #define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
01480 #define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
01481 #define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
01482 #define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
01483
01484 #define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
01485 #define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
01486 #define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
01487 #define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
01488 #define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
01489 #define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
01490
01491 #define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
01492 #define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
01493 #define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
01494 #define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
01495 #define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
01496 #define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
01497
01498 #define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
01499 #define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
01500 #define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
01501 #define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
01502 #define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
01503 #define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
01504
01505 #define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
01506 #define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
01507 #define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
01508 #define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
01509 #define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
01510 #define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
01511
01512 #define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
01513 #define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
01514 #define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
01515 #define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
01516 #define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
01517 #define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
01518
01519
01520 /*******************  Bit definition for ADC_JSQR register  *******************/
01521 #define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
01522 #define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
01523 #define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
01524 #define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
01525 #define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
01526 #define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
01527
01528 #define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
01529 #define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
01530 #define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
01531 #define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
01532 #define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
01533 #define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
01534
01535 #define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
01536 #define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
01537 #define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
01538 #define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
01539 #define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
01540 #define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
01541
01542 #define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
01543 #define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
01544 #define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
01545 #define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
01546 #define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
01547 #define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
01548
01549 #define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
01550 #define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
01551 #define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
01552
01553 /*******************  Bit definition for ADC_JDR1 register  *******************/
01554 #define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
01555
01556 /*******************  Bit definition for ADC_JDR2 register  *******************/
01557 #define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
01558
01559 /*******************  Bit definition for ADC_JDR3 register  *******************/
01560 #define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
01561
01562 /*******************  Bit definition for ADC_JDR4 register  *******************/
01563 #define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
01564
01565 /********************  Bit definition for ADC_DR register  ********************/
01566 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
01567
01568 /******************  Bit definition for ADC_SMPR0 register  *******************/
01569 #define  ADC_SMPR3_SMP30                     ((uint32_t)0x00000007)        /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
01570 #define  ADC_SMPR3_SMP30_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
01571 #define  ADC_SMPR3_SMP30_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
01572 #define  ADC_SMPR3_SMP30_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
01573
01574 #define  ADC_SMPR3_SMP31                     ((uint32_t)0x00000038)        /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
01575 #define  ADC_SMPR3_SMP31_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
01576 #define  ADC_SMPR3_SMP31_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
01577 #define  ADC_SMPR3_SMP31_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
01578
01579 /*******************  Bit definition for ADC_CSR register  ********************/
01580 #define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
01581 #define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
01582 #define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
01583 #define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
01584 #define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
01585 #define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
01586 #define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
01587
01588 /*******************  Bit definition for ADC_CCR register  ********************/
01589 #define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
01590 #define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
01591 #define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
01592 #define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
01593
01594 /******************************************************************************/
01595 /*                                                                            */
01596 /*                       Advanced Encryption Standard (AES)                   */
01597 /*                                                                            */
01598 /******************************************************************************/
01599 /*******************  Bit definition for AES_CR register  *********************/
01600 #define  AES_CR_EN                           ((uint32_t)0x00000001)        /*!< AES Enable */
01601 #define  AES_CR_DATATYPE                     ((uint32_t)0x00000006)        /*!< Data type selection */
01602 #define  AES_CR_DATATYPE_0                   ((uint32_t)0x00000002)        /*!< Bit 0 */
01603 #define  AES_CR_DATATYPE_1                   ((uint32_t)0x00000004)        /*!< Bit 1 */
01604
01605 #define  AES_CR_MODE                         ((uint32_t)0x00000018)        /*!< AES Mode Of Operation */
01606 #define  AES_CR_MODE_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
01607 #define  AES_CR_MODE_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
01608
01609 #define  AES_CR_CHMOD                        ((uint32_t)0x00000060)        /*!< AES Chaining Mode */
01610 #define  AES_CR_CHMOD_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
01611 #define  AES_CR_CHMOD_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
01612
01613 #define  AES_CR_CCFC                         ((uint32_t)0x00000080)        /*!< Computation Complete Flag Clear */
01614 #define  AES_CR_ERRC                         ((uint32_t)0x00000100)        /*!< Error Clear */
01615 #define  AES_CR_CCIE                         ((uint32_t)0x00000200)        /*!< Computation Complete Interrupt Enable */
01616 #define  AES_CR_ERRIE                        ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
01617 #define  AES_CR_DMAINEN                      ((uint32_t)0x00000800)        /*!< DMA ENable managing the data input phase */
01618 #define  AES_CR_DMAOUTEN                     ((uint32_t)0x00001000)        /*!< DMA Enable managing the data output phase */
01619
01620 /*******************  Bit definition for AES_SR register  *********************/
01621 #define  AES_SR_CCF                          ((uint32_t)0x00000001)        /*!< Computation Complete Flag */
01622 #define  AES_SR_RDERR                        ((uint32_t)0x00000002)        /*!< Read Error Flag */
01623 #define  AES_SR_WRERR                        ((uint32_t)0x00000004)        /*!< Write Error Flag */
01624
01625 /*******************  Bit definition for AES_DINR register  *******************/
01626 #define  AES_DINR                            ((uint32_t)0x0000FFFF)        /*!< AES Data Input Register */
01627
01628 /*******************  Bit definition for AES_DOUTR register  ******************/
01629 #define  AES_DOUTR                           ((uint32_t)0x0000FFFF)        /*!< AES Data Output Register */
01630
01631 /*******************  Bit definition for AES_KEYR0 register  ******************/
01632 #define  AES_KEYR0                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 0 */
01633
01634 /*******************  Bit definition for AES_KEYR1 register  ******************/
01635 #define  AES_KEYR1                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 1 */
01636
01637 /*******************  Bit definition for AES_KEYR2 register  ******************/
01638 #define  AES_KEYR2                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 2 */
01639
01640 /*******************  Bit definition for AES_KEYR3 register  ******************/
01641 #define  AES_KEYR3                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 3 */
01642
01643 /*******************  Bit definition for AES_IVR0 register  *******************/
01644 #define  AES_IVR0                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 0 */
01645
01646 /*******************  Bit definition for AES_IVR1 register  *******************/
01647 #define  AES_IVR1                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 1 */
01648
01649 /*******************  Bit definition for AES_IVR2 register  *******************/
01650 #define  AES_IVR2                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 2 */
01651
01652 /*******************  Bit definition for AES_IVR3 register  *******************/
01653 #define  AES_IVR3                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 3 */
01654
01655 /******************************************************************************/
01656 /*                                                                            */
01657 /*                      Analog Comparators (COMP)                             */
01658 /*                                                                            */
01659 /******************************************************************************/
01660
01661 /******************  Bit definition for COMP_CSR register  ********************/
01662 #define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
01663 #define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
01664 #define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
01665 #define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
01666
01667 #define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
01668 #define  COMP_CSR_SW1                        ((uint32_t)0x00000020)        /*!< SW1 analog switch enable */
01669 #define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
01670
01671 #define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
01672 #define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
01673
01674 #define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
01675 #define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
01676
01677 #define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
01678 #define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
01679 #define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
01680 #define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
01681
01682 #define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
01683 #define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
01684 #define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
01685 #define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
01686
01687 #define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
01688 #define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
01689 #define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
01690
01691 #define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
01692 #define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
01693 #define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
01694
01695 /******************************************************************************/
01696 /*                                                                            */
01697 /*                         Operational Amplifier (OPAMP)                      */
01698 /*                                                                            */
01699 /******************************************************************************/
01700 /*******************  Bit definition for OPAMP_CSR register  ******************/
01701 #define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
01702 #define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
01703 #define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
01704 #define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
01705 #define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
01706 #define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
01707 #define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
01708 #define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
01709 #define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
01710 #define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
01711 #define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
01712 #define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
01713 #define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
01714 #define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
01715 #define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
01716 #define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
01717 #define OPAMP_CSR_OPA3PD                     ((uint32_t)0x00010000)        /*!< OPAMP3 disable */
01718 #define OPAMP_CSR_S3SEL3                     ((uint32_t)0x00020000)        /*!< Switch 3 for OPAMP3 Enable */
01719 #define OPAMP_CSR_S4SEL3                     ((uint32_t)0x00040000)        /*!< Switch 4 for OPAMP3 Enable */
01720 #define OPAMP_CSR_S5SEL3                     ((uint32_t)0x00080000)        /*!< Switch 5 for OPAMP3 Enable */
01721 #define OPAMP_CSR_S6SEL3                     ((uint32_t)0x00100000)        /*!< Switch 6 for OPAMP3 Enable */
01722 #define OPAMP_CSR_OPA3CAL_L                  ((uint32_t)0x00200000)        /*!< OPAMP3 Offset calibration for P differential pair */
01723 #define OPAMP_CSR_OPA3CAL_H                  ((uint32_t)0x00400000)        /*!< OPAMP3 Offset calibration for N differential pair */
01724 #define OPAMP_CSR_OPA3LPM                    ((uint32_t)0x00800000)        /*!< OPAMP3 Low power enable */
01725 #define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */
01726 #define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
01727 #define OPAMP_CSR_ANAWSEL3                   ((uint32_t)0x04000000)        /*!< Switch ANA Enable for OPAMP3 */
01728 #define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
01729 #define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
01730 #define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
01731 #define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
01732 #define OPAMP_CSR_OPA3CALOUT                 ((uint32_t)0x80000000)        /*!< OPAMP3 calibration output */
01733
01734 /*******************  Bit definition for OPAMP_OTR register  ******************/
01735 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM        ((uint32_t)0x000003FF)        /*!< Offset trim for OPAMP1 */
01736 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM        ((uint32_t)0x000FFC00)        /*!< Offset trim for OPAMP2 */
01737 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM        ((uint32_t)0x3FF00000)        /*!< Offset trim for OPAMP2 */
01738 #define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
01739
01740 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
01741 #define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000003FF)        /*!< Offset trim in low power for OPAMP1 */
01742 #define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000FFC00)        /*!< Offset trim in low power for OPAMP2 */
01743 #define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP  ((uint32_t)0x3FF00000)        /*!< Offset trim in low power for OPAMP3 */
01744
01745 /******************************************************************************/
01746 /*                                                                            */
01747 /*                       CRC calculation unit (CRC)                           */
01748 /*                                                                            */
01749 /******************************************************************************/
01750
01751 /*******************  Bit definition for CRC_DR register  *********************/
01752 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
01753
01754 /*******************  Bit definition for CRC_IDR register  ********************/
01755 #define  CRC_IDR_IDR                         ((uint8_t)0xFF)               /*!< General-purpose 8-bit data register bits */
01756
01757 /********************  Bit definition for CRC_CR register  ********************/
01758 #define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
01759
01760 /******************************************************************************/
01761 /*                                                                            */
01762 /*                    Digital to Analog Converter (DAC)                       */
01763 /*                                                                            */
01764 /******************************************************************************/
01765
01766 /********************  Bit definition for DAC_CR register  ********************/
01767 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
01768 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
01769 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
01770
01771 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
01772 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
01773 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
01774 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
01775
01776 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
01777 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
01778 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
01779
01780 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
01781 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
01782 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
01783 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
01784 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
01785
01786 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
01787 #define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun interrupt enable */
01788 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
01789 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
01790 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
01791
01792 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
01793 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
01794 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
01795 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
01796
01797 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
01798 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
01799 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
01800
01801 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
01802 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
01803 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
01804 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
01805 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
01806
01807 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
01808 #define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
01809 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
01810 #define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
01811 #define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
01812
01813 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
01814 #define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
01815
01816 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
01817 #define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
01818
01819 /******************  Bit definition for DAC_DHR8R1 register  ******************/
01820 #define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
01821
01822 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
01823 #define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
01824
01825 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
01826 #define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
01827
01828 /******************  Bit definition for DAC_DHR8R2 register  ******************/
01829 #define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
01830
01831 /*****************  Bit definition for DAC_DHR12RD register  ******************/
01832 #define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
01833 #define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
01834
01835 /*****************  Bit definition for DAC_DHR12LD register  ******************/
01836 #define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
01837 #define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
01838
01839 /******************  Bit definition for DAC_DHR8RD register  ******************/
01840 #define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
01841 #define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
01842
01843 /*******************  Bit definition for DAC_DOR1 register  *******************/
01844 #define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
01845
01846 /*******************  Bit definition for DAC_DOR2 register  *******************/
01847 #define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
01848
01849 /********************  Bit definition for DAC_SR register  ********************/
01850 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
01851 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
01852
01853 /******************************************************************************/
01854 /*                                                                            */
01855 /*                           Debug MCU (DBGMCU)                               */
01856 /*                                                                            */
01857 /******************************************************************************/
01858
01859 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
01860 #define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
01861
01862 #define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
01863 #define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
01864 #define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
01865 #define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
01866 #define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
01867 #define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
01868 #define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
01869 #define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
01870 #define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
01871 #define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
01872 #define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
01873 #define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
01874 #define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
01875 #define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
01876 #define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
01877 #define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
01878 #define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
01879
01880 /******************  Bit definition for DBGMCU_CR register  *******************/
01881 #define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
01882 #define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
01883 #define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
01884 #define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
01885
01886 #define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
01887 #define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
01888 #define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
01889
01890 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
01891
01892 #define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
01893 #define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
01894 #define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
01895 #define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
01896 #define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
01897 #define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
01898 #define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
01899 #define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
01900 #define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
01901 #define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
01902 #define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
01903
01904 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
01905
01906 #define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
01907 #define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
01908 #define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
01909
01910 /******************************************************************************/
01911 /*                                                                            */
01912 /*                           DMA Controller (DMA)                             */
01913 /*                                                                            */
01914 /******************************************************************************/
01915
01916 /*******************  Bit definition for DMA_ISR register  ********************/
01917 #define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
01918 #define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
01919 #define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
01920 #define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
01921 #define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
01922 #define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
01923 #define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
01924 #define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
01925 #define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
01926 #define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
01927 #define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
01928 #define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
01929 #define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
01930 #define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
01931 #define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
01932 #define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
01933 #define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
01934 #define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
01935 #define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
01936 #define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
01937 #define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
01938 #define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
01939 #define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
01940 #define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
01941 #define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
01942 #define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
01943 #define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
01944 #define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
01945
01946 /*******************  Bit definition for DMA_IFCR register  *******************/
01947 #define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
01948 #define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
01949 #define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
01950 #define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
01951 #define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
01952 #define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
01953 #define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
01954 #define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
01955 #define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
01956 #define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
01957 #define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
01958 #define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
01959 #define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
01960 #define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
01961 #define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
01962 #define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
01963 #define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
01964 #define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
01965 #define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
01966 #define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
01967 #define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
01968 #define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
01969 #define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
01970 #define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
01971 #define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
01972 #define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
01973 #define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
01974 #define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
01975
01976 /*******************  Bit definition for DMA_CCR1 register  *******************/
01977 #define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
01978 #define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
01979 #define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
01980 #define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
01981 #define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
01982 #define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
01983 #define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
01984 #define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
01985
01986 #define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
01987 #define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
01988 #define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
01989
01990 #define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
01991 #define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
01992 #define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
01993
01994 #define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
01995 #define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
01996 #define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
01997
01998 #define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
01999
02000 /*******************  Bit definition for DMA_CCR2 register  *******************/
02001 #define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02002 #define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
02003 #define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02004 #define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02005 #define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02006 #define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02007 #define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02008 #define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02009
02010 #define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02011 #define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02012 #define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02013
02014 #define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02015 #define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02016 #define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02017
02018 #define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02019 #define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02020 #define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02021
02022 #define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
02023
02024 /*******************  Bit definition for DMA_CCR3 register  *******************/
02025 #define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02026 #define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
02027 #define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02028 #define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02029 #define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02030 #define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02031 #define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02032 #define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02033
02034 #define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02035 #define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02036 #define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02037
02038 #define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02039 #define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02040 #define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02041
02042 #define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02043 #define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02044 #define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02045
02046 #define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
02047
02048 /*!<******************  Bit definition for DMA_CCR4 register  *******************/
02049 #define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02050 #define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
02051 #define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02052 #define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02053 #define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02054 #define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02055 #define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02056 #define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02057
02058 #define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02059 #define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02060 #define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02061
02062 #define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02063 #define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02064 #define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02065
02066 #define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02067 #define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02068 #define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02069
02070 #define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
02071
02072 /******************  Bit definition for DMA_CCR5 register  *******************/
02073 #define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02074 #define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
02075 #define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02076 #define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02077 #define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02078 #define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02079 #define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02080 #define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02081
02082 #define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02083 #define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02084 #define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02085
02086 #define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02087 #define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02088 #define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02089
02090 #define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02091 #define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02092 #define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02093
02094 #define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
02095
02096 /*******************  Bit definition for DMA_CCR6 register  *******************/
02097 #define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02098 #define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
02099 #define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02100 #define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02101 #define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02102 #define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02103 #define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02104 #define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02105
02106 #define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02107 #define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02108 #define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02109
02110 #define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02111 #define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02112 #define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02113
02114 #define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02115 #define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02116 #define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02117
02118 #define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
02119
02120 /*******************  Bit definition for DMA_CCR7 register  *******************/
02121 #define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
02122 #define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
02123 #define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
02124 #define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
02125 #define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
02126 #define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
02127 #define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
02128 #define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
02129
02130 #define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
02131 #define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
02132 #define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
02133
02134 #define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
02135 #define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
02136 #define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
02137
02138 #define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
02139 #define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
02140 #define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
02141
02142 #define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
02143
02144 /******************  Bit definition for DMA_CNDTR1 register  ******************/
02145 #define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02146
02147 /******************  Bit definition for DMA_CNDTR2 register  ******************/
02148 #define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02149
02150 /******************  Bit definition for DMA_CNDTR3 register  ******************/
02151 #define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02152
02153 /******************  Bit definition for DMA_CNDTR4 register  ******************/
02154 #define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02155
02156 /******************  Bit definition for DMA_CNDTR5 register  ******************/
02157 #define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02158
02159 /******************  Bit definition for DMA_CNDTR6 register  ******************/
02160 #define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02161
02162 /******************  Bit definition for DMA_CNDTR7 register  ******************/
02163 #define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
02164
02165 /******************  Bit definition for DMA_CPAR1 register  *******************/
02166 #define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02167
02168 /******************  Bit definition for DMA_CPAR2 register  *******************/
02169 #define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02170
02171 /******************  Bit definition for DMA_CPAR3 register  *******************/
02172 #define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02173
02174
02175 /******************  Bit definition for DMA_CPAR4 register  *******************/
02176 #define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02177
02178 /******************  Bit definition for DMA_CPAR5 register  *******************/
02179 #define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02180
02181 /******************  Bit definition for DMA_CPAR6 register  *******************/
02182 #define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02183
02184
02185 /******************  Bit definition for DMA_CPAR7 register  *******************/
02186 #define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
02187
02188 /******************  Bit definition for DMA_CMAR1 register  *******************/
02189 #define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02190
02191 /******************  Bit definition for DMA_CMAR2 register  *******************/
02192 #define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02193
02194 /******************  Bit definition for DMA_CMAR3 register  *******************/
02195 #define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02196
02197
02198 /******************  Bit definition for DMA_CMAR4 register  *******************/
02199 #define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02200
02201 /******************  Bit definition for DMA_CMAR5 register  *******************/
02202 #define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02203
02204 /******************  Bit definition for DMA_CMAR6 register  *******************/
02205 #define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02206
02207 /******************  Bit definition for DMA_CMAR7 register  *******************/
02208 #define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
02209
02210 /******************************************************************************/
02211 /*                                                                            */
02212 /*                  External Interrupt/Event Controller (EXTI)                */
02213 /*                                                                            */
02214 /******************************************************************************/
02215
02216 /*******************  Bit definition for EXTI_IMR register  *******************/
02217 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
02218 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
02219 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
02220 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
02221 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
02222 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
02223 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
02224 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
02225 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
02226 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
02227 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
02228 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
02229 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
02230 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
02231 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
02232 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
02233 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
02234 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
02235 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
02236 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
02237 #define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
02238 #define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
02239 #define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
02240 #define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
02241
02242 /*******************  Bit definition for EXTI_EMR register  *******************/
02243 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
02244 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
02245 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
02246 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
02247 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
02248 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
02249 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
02250 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
02251 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
02252 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
02253 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
02254 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
02255 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
02256 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
02257 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
02258 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
02259 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
02260 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
02261 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
02262 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
02263 #define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
02264 #define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
02265 #define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
02266 #define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
02267
02268 /******************  Bit definition for EXTI_RTSR register  *******************/
02269 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
02270 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
02271 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
02272 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
02273 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
02274 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
02275 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
02276 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
02277 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
02278 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
02279 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
02280 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
02281 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
02282 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
02283 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
02284 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
02285 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
02286 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
02287 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
02288 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
02289 #define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
02290 #define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
02291 #define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
02292 #define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
02293
02294 /******************  Bit definition for EXTI_FTSR register  *******************/
02295 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
02296 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
02297 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
02298 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
02299 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
02300 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
02301 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
02302 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
02303 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
02304 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
02305 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
02306 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
02307 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
02308 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
02309 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
02310 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
02311 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
02312 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
02313 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
02314 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
02315 #define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
02316 #define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
02317 #define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
02318 #define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
02319
02320 /******************  Bit definition for EXTI_SWIER register  ******************/
02321 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
02322 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
02323 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
02324 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
02325 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
02326 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
02327 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
02328 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
02329 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
02330 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
02331 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
02332 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
02333 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
02334 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
02335 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
02336 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
02337 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
02338 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
02339 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
02340 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
02341 #define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
02342 #define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
02343 #define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
02344 #define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
02345
02346 /*******************  Bit definition for EXTI_PR register  ********************/
02347 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
02348 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
02349 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
02350 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
02351 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
02352 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
02353 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
02354 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
02355 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
02356 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
02357 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
02358 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
02359 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
02360 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
02361 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
02362 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
02363 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
02364 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
02365 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
02366 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
02367 #define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
02368 #define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
02369 #define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
02370 #define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
02371
02372 /******************************************************************************/
02373 /*                                                                            */
02374 /*                FLASH, DATA EEPROM and Option Bytes Registers               */
02375 /*                        (FLASH, DATA_EEPROM, OB)                            */
02376 /*                                                                            */
02377 /******************************************************************************/
02378
02379 /*******************  Bit definition for FLASH_ACR register  ******************/
02380 #define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
02381 #define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
02382 #define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
02383 #define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
02384 #define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
02385
02386 /*******************  Bit definition for FLASH_PECR register  ******************/
02387 #define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
02388 #define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
02389 #define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
02390 #define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
02391 #define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
02392 #define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
02393 #define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
02394 #define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
02395 #define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
02396 #define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */
02397 #define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */
02398 #define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */
02399
02400 /******************  Bit definition for FLASH_PDKEYR register  ******************/
02401 #define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
02402
02403 /******************  Bit definition for FLASH_PEKEYR register  ******************/
02404 #define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
02405
02406 /******************  Bit definition for FLASH_PRGKEYR register  ******************/
02407 #define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
02408
02409 /******************  Bit definition for FLASH_OPTKEYR register  ******************/
02410 #define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
02411
02412 /******************  Bit definition for FLASH_SR register  *******************/
02413 #define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
02414 #define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
02415 #define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
02416 #define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
02417
02418 #define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
02419 #define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
02420 #define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
02421 #define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
02422 #define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
02423
02424 /******************  Bit definition for FLASH_OBR register  *******************/
02425 #define  FLASH_OBR_RDPRT                     ((uint16_t)0x000000AA)        /*!< Read Protection */
02426 #define  FLASH_OBR_BOR_LEV                   ((uint16_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
02427 #define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */
02428 #define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
02429 #define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
02430 #define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
02431 #define  FLASH_OBR_nRST_BFB2                 ((uint32_t)0x00800000)        /*!< BFB2 */
02432
02433 /******************  Bit definition for FLASH_WRPR register  ******************/
02434 #define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
02435
02436 /******************  Bit definition for FLASH_WRPR1 register  *****************/
02437 #define  FLASH_WRPR1_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
02438
02439 /******************  Bit definition for FLASH_WRPR2 register  *****************/
02440 #define  FLASH_WRPR2_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
02441 /******************************************************************************/
02442 /*                                                                            */
02443 /*                       Flexible Static Memory Controller                    */
02444 /*                                                                            */
02445 /******************************************************************************/
02446 /******************  Bit definition for FSMC_BCR1 register  *******************/
02447 #define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
02448 #define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
02449
02450 #define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
02451 #define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
02452 #define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
02453
02454 #define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
02455 #define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02456 #define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02457
02458 #define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
02459 #define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
02460 #define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
02461 #define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
02462 #define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
02463 #define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
02464 #define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
02465 #define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
02466 #define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
02467 #define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
02468
02469 /******************  Bit definition for FSMC_BCR2 register  *******************/
02470 #define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
02471 #define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
02472
02473 #define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
02474 #define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
02475 #define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
02476
02477 #define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
02478 #define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02479 #define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02480
02481 #define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
02482 #define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
02483 #define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
02484 #define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
02485 #define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
02486 #define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
02487 #define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
02488 #define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
02489 #define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
02490 #define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
02491
02492 /******************  Bit definition for FSMC_BCR3 register  *******************/
02493 #define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
02494 #define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
02495
02496 #define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
02497 #define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
02498 #define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
02499
02500 #define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
02501 #define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02502 #define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02503
02504 #define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
02505 #define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
02506 #define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
02507 #define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
02508 #define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
02509 #define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
02510 #define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
02511 #define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
02512 #define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
02513 #define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
02514
02515 /******************  Bit definition for FSMC_BCR4 register  *******************/
02516 #define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
02517 #define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
02518
02519 #define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
02520 #define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
02521 #define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
02522
02523 #define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
02524 #define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02525 #define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02526
02527 #define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
02528 #define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
02529 #define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
02530 #define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
02531 #define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
02532 #define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
02533 #define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
02534 #define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
02535 #define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
02536 #define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
02537
02538 /******************  Bit definition for FSMC_BTR1 register  ******************/
02539 #define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02540 #define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
02541 #define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
02542 #define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
02543 #define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
02544
02545 #define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02546 #define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
02547 #define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
02548 #define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
02549 #define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
02550
02551 #define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02552 #define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
02553 #define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
02554 #define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
02555 #define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
02556
02557 #define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
02558 #define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
02559 #define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
02560 #define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
02561 #define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
02562
02563 #define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02564 #define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
02565 #define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
02566 #define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
02567 #define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
02568
02569 #define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02570 #define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02571 #define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02572 #define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02573 #define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
02574
02575 #define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02576 #define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
02577 #define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
02578
02579 /******************  Bit definition for FSMC_BTR2 register  *******************/
02580 #define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02581 #define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
02582 #define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
02583 #define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
02584 #define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
02585
02586 #define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02587 #define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
02588 #define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
02589 #define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
02590 #define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
02591
02592 #define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02593 #define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
02594 #define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
02595 #define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
02596 #define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
02597
02598 #define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
02599 #define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
02600 #define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
02601 #define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
02602 #define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
02603
02604 #define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02605 #define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
02606 #define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
02607 #define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
02608 #define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
02609
02610 #define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02611 #define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02612 #define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02613 #define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02614 #define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
02615
02616 #define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02617 #define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
02618 #define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
02619
02620 /*******************  Bit definition for FSMC_BTR3 register  *******************/
02621 #define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02622 #define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
02623 #define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
02624 #define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
02625 #define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
02626
02627 #define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02628 #define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
02629 #define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
02630 #define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
02631 #define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
02632
02633 #define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02634 #define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
02635 #define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
02636 #define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
02637 #define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
02638
02639 #define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
02640 #define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
02641 #define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
02642 #define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
02643 #define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
02644
02645 #define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02646 #define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
02647 #define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
02648 #define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
02649 #define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
02650
02651 #define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02652 #define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02653 #define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02654 #define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02655 #define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
02656
02657 #define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02658 #define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
02659 #define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
02660
02661 /******************  Bit definition for FSMC_BTR4 register  *******************/
02662 #define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02663 #define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
02664 #define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
02665 #define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
02666 #define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
02667
02668 #define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02669 #define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
02670 #define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
02671 #define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
02672 #define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
02673
02674 #define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02675 #define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
02676 #define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
02677 #define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
02678 #define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
02679
02680 #define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
02681 #define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
02682 #define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
02683 #define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
02684 #define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
02685
02686 #define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02687 #define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
02688 #define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
02689 #define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
02690 #define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
02691
02692 #define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02693 #define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02694 #define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02695 #define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02696 #define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
02697
02698 #define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02699 #define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
02700 #define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
02701
02702 /******************  Bit definition for FSMC_BWTR1 register  ******************/
02703 #define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02704 #define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
02705 #define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
02706 #define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
02707 #define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
02708
02709 #define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02710 #define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
02711 #define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
02712 #define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
02713 #define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
02714
02715 #define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02716 #define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
02717 #define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
02718 #define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
02719 #define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
02720
02721 #define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02722 #define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
02723 #define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
02724 #define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
02725 #define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
02726
02727 #define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02728 #define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
02729 #define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
02730 #define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
02731 #define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
02732
02733 #define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02734 #define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
02735 #define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
02736
02737 /******************  Bit definition for FSMC_BWTR2 register  ******************/
02738 #define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02739 #define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
02740 #define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
02741 #define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
02742 #define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
02743
02744 #define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02745 #define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
02746 #define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
02747 #define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
02748 #define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
02749
02750 #define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02751 #define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
02752 #define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
02753 #define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
02754 #define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
02755
02756 #define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02757 #define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
02758 #define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
02759 #define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
02760 #define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
02761
02762 #define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02763 #define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
02764 #define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
02765 #define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
02766 #define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
02767
02768 #define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02769 #define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
02770 #define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
02771
02772 /******************  Bit definition for FSMC_BWTR3 register  ******************/
02773 #define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02774 #define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
02775 #define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
02776 #define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
02777 #define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
02778
02779 #define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02780 #define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
02781 #define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
02782 #define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
02783 #define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
02784
02785 #define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02786 #define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
02787 #define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
02788 #define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
02789 #define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
02790
02791 #define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02792 #define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
02793 #define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
02794 #define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
02795 #define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
02796
02797 #define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02798 #define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
02799 #define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
02800 #define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
02801 #define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
02802
02803 #define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02804 #define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
02805 #define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
02806
02807 /******************  Bit definition for FSMC_BWTR4 register  ******************/
02808 #define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
02809 #define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
02810 #define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
02811 #define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
02812 #define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
02813
02814 #define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
02815 #define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
02816 #define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
02817 #define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
02818 #define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
02819
02820 #define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
02821 #define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
02822 #define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
02823 #define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
02824 #define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
02825
02826 #define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
02827 #define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
02828 #define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
02829 #define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
02830 #define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
02831
02832 #define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
02833 #define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
02834 #define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
02835 #define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
02836 #define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
02837
02838 #define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
02839 #define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
02840 #define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
02841
02842 /******************************************************************************/
02843 /*                                                                            */
02844 /*                      General Purpose IOs (GPIO)                            */
02845 /*                                                                            */
02846 /******************************************************************************/
02847 /*******************  Bit definition for GPIO_MODER register  *****************/
02848 #define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
02849 #define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
02850 #define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
02851 #define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
02852 #define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
02853 #define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
02854 #define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
02855 #define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
02856 #define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
02857 #define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
02858 #define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
02859 #define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
02860 #define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
02861 #define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
02862 #define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
02863 #define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
02864 #define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
02865 #define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
02866 #define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
02867 #define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
02868 #define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
02869 #define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
02870 #define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
02871 #define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
02872 #define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
02873 #define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
02874 #define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
02875 #define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
02876 #define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
02877 #define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
02878 #define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
02879 #define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
02880 #define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
02881 #define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
02882 #define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
02883 #define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
02884 #define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
02885 #define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
02886 #define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
02887 #define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
02888 #define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
02889 #define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
02890 #define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
02891 #define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
02892 #define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
02893 #define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
02894 #define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
02895 #define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
02896
02897 /*******************  Bit definition for GPIO_OTYPER register  ****************/
02898 #define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
02899 #define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
02900 #define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
02901 #define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
02902 #define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
02903 #define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
02904 #define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
02905 #define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
02906 #define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
02907 #define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
02908 #define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
02909 #define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
02910 #define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
02911 #define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
02912 #define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
02913 #define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
02914
02915 /*******************  Bit definition for GPIO_OSPEEDR register  ***************/
02916 #define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
02917 #define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
02918 #define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
02919 #define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
02920 #define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
02921 #define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
02922 #define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
02923 #define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
02924 #define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
02925 #define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
02926 #define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
02927 #define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
02928 #define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
02929 #define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
02930 #define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
02931 #define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
02932 #define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
02933 #define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
02934 #define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
02935 #define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
02936 #define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
02937 #define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
02938 #define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
02939 #define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
02940 #define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
02941 #define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
02942 #define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
02943 #define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
02944 #define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
02945 #define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
02946 #define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
02947 #define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
02948 #define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
02949 #define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
02950 #define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
02951 #define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
02952 #define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
02953 #define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
02954 #define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
02955 #define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
02956 #define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
02957 #define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
02958 #define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
02959 #define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
02960 #define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
02961 #define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
02962 #define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
02963 #define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
02964
02965 /*******************  Bit definition for GPIO_PUPDR register  *****************/
02966 #define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
02967 #define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
02968 #define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
02969 #define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
02970 #define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
02971 #define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
02972 #define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
02973 #define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
02974 #define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
02975 #define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
02976 #define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
02977 #define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
02978 #define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
02979 #define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
02980 #define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
02981 #define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
02982 #define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
02983 #define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
02984 #define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
02985 #define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
02986 #define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
02987 #define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
02988 #define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
02989 #define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
02990 #define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
02991 #define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
02992 #define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
02993 #define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
02994 #define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
02995 #define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
02996 #define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
02997 #define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
02998 #define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
02999 #define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
03000 #define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
03001 #define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
03002 #define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
03003 #define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
03004 #define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
03005 #define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
03006 #define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
03007 #define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
03008 #define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
03009 #define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
03010 #define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
03011 #define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
03012 #define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
03013 #define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
03014
03015 /******************  Bits definition for GPIO_IDR register  *******************/
03016 #define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
03017 #define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
03018 #define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
03019 #define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
03020 #define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
03021 #define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
03022 #define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
03023 #define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
03024 #define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
03025 #define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
03026 #define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
03027 #define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
03028 #define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
03029 #define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
03030 #define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
03031 #define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
03032 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
03033 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
03034 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
03035 #define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
03036 #define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
03037 #define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
03038 #define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
03039 #define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
03040 #define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
03041 #define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
03042 #define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
03043 #define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
03044 #define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
03045 #define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
03046 #define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
03047 #define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
03048 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
03049
03050 /******************  Bits definition for GPIO_ODR register  *******************/
03051 #define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
03052 #define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
03053 #define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
03054 #define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
03055 #define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
03056 #define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
03057 #define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
03058 #define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
03059 #define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
03060 #define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
03061 #define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
03062 #define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
03063 #define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
03064 #define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
03065 #define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
03066 #define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
03067 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
03068 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
03069 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
03070 #define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
03071 #define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
03072 #define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
03073 #define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
03074 #define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
03075 #define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
03076 #define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
03077 #define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
03078 #define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
03079 #define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
03080 #define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
03081 #define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
03082 #define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
03083 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
03084
03085 /*******************  Bit definition for GPIO_BSRR register  ******************/
03086 #define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
03087 #define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
03088 #define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
03089 #define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
03090 #define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
03091 #define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
03092 #define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
03093 #define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
03094 #define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
03095 #define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
03096 #define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
03097 #define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
03098 #define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
03099 #define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
03100 #define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
03101 #define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
03102 #define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
03103 #define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
03104 #define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
03105 #define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
03106 #define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
03107 #define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
03108 #define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
03109 #define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
03110 #define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
03111 #define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
03112 #define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
03113 #define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
03114 #define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
03115 #define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
03116 #define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
03117 #define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
03118
03119 /*******************  Bit definition for GPIO_LCKR register  ******************/
03120 #define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
03121 #define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
03122 #define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
03123 #define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
03124 #define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
03125 #define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
03126 #define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
03127 #define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
03128 #define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
03129 #define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
03130 #define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
03131 #define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
03132 #define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
03133 #define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
03134 #define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
03135 #define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
03136 #define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
03137
03138 /*******************  Bit definition for GPIO_AFRL register  ******************/
03139 #define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
03140 #define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
03141 #define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
03142 #define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
03143 #define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
03144 #define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
03145 #define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
03146 #define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
03147
03148 /*******************  Bit definition for GPIO_AFRH register  ******************/
03149 #define GPIO_AFRH_AFRH8            ((uint32_t)0x0000000F)
03150 #define GPIO_AFRH_AFRH9            ((uint32_t)0x000000F0)
03151 #define GPIO_AFRH_AFRH10           ((uint32_t)0x00000F00)
03152 #define GPIO_AFRH_AFRH11           ((uint32_t)0x0000F000)
03153 #define GPIO_AFRH_AFRH12           ((uint32_t)0x000F0000)
03154 #define GPIO_AFRH_AFRH13           ((uint32_t)0x00F00000)
03155 #define GPIO_AFRH_AFRH14           ((uint32_t)0x0F000000)
03156 #define GPIO_AFRH_AFRH15           ((uint32_t)0xF0000000)
03157
03158 /******************************************************************************/
03159 /*                                                                            */
03160 /*                   Inter-integrated Circuit Interface (I2C)                 */
03161 /*                                                                            */
03162 /******************************************************************************/
03163
03164 /*******************  Bit definition for I2C_CR1 register  ********************/
03165 #define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
03166 #define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
03167 #define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
03168 #define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
03169 #define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
03170 #define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
03171 #define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
03172 #define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
03173 #define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
03174 #define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
03175 #define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
03176 #define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
03177 #define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
03178 #define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
03179
03180 /*******************  Bit definition for I2C_CR2 register  ********************/
03181 #define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
03182 #define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
03183 #define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
03184 #define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
03185 #define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
03186 #define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
03187 #define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
03188
03189 #define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
03190 #define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
03191 #define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
03192 #define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
03193 #define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
03194
03195 /*******************  Bit definition for I2C_OAR1 register  *******************/
03196 #define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
03197 #define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
03198
03199 #define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
03200 #define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
03201 #define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
03202 #define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
03203 #define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
03204 #define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
03205 #define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
03206 #define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
03207 #define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
03208 #define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
03209
03210 #define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
03211
03212 /*******************  Bit definition for I2C_OAR2 register  *******************/
03213 #define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
03214 #define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
03215
03216 /********************  Bit definition for I2C_DR register  ********************/
03217 #define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
03218
03219 /*******************  Bit definition for I2C_SR1 register  ********************/
03220 #define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
03221 #define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
03222 #define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
03223 #define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
03224 #define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
03225 #define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
03226 #define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
03227 #define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
03228 #define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
03229 #define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
03230 #define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
03231 #define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
03232 #define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
03233 #define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
03234
03235 /*******************  Bit definition for I2C_SR2 register  ********************/
03236 #define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
03237 #define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
03238 #define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
03239 #define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
03240 #define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
03241 #define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
03242 #define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
03243 #define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
03244
03245 /*******************  Bit definition for I2C_CCR register  ********************/
03246 #define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
03247 #define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
03248 #define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
03249
03250 /******************  Bit definition for I2C_TRISE register  *******************/
03251 #define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
03252
03253 /******************************************************************************/
03254 /*                                                                            */
03255 /*                        Independent WATCHDOG (IWDG)                         */
03256 /*                                                                            */
03257 /******************************************************************************/
03258
03259 /*******************  Bit definition for IWDG_KR register  ********************/
03260 #define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
03261
03262 /*******************  Bit definition for IWDG_PR register  ********************/
03263 #define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
03264 #define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
03265 #define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
03266 #define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
03267
03268 /*******************  Bit definition for IWDG_RLR register  *******************/
03269 #define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
03270
03271 /*******************  Bit definition for IWDG_SR register  ********************/
03272 #define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
03273 #define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
03274
03275 /******************************************************************************/
03276 /*                                                                            */
03277 /*                          LCD Controller (LCD)                              */
03278 /*                                                                            */
03279 /******************************************************************************/
03280
03281 /*******************  Bit definition for LCD_CR register  *********************/
03282 #define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
03283 #define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
03284
03285 #define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
03286 #define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
03287 #define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
03288 #define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
03289
03290 #define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
03291 #define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
03292 #define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
03293
03294 #define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
03295
03296 /*******************  Bit definition for LCD_FCR register  ********************/
03297 #define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
03298 #define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
03299 #define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
03300
03301 #define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
03302 #define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
03303 #define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
03304 #define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
03305
03306 #define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
03307 #define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
03308 #define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
03309 #define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
03310
03311 #define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
03312 #define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
03313 #define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
03314 #define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
03315
03316 #define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
03317 #define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
03318 #define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
03319 #define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
03320
03321 #define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
03322 #define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
03323 #define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
03324
03325 #define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
03326 #define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
03327
03328 /*******************  Bit definition for LCD_SR register  *********************/
03329 #define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
03330 #define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
03331 #define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
03332 #define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
03333 #define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
03334 #define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
03335
03336 /*******************  Bit definition for LCD_CLR register  ********************/
03337 #define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
03338 #define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
03339
03340 /*******************  Bit definition for LCD_RAM register  ********************/
03341 #define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
03342
03343 /******************************************************************************/
03344 /*                                                                            */
03345 /*                          Power Control (PWR)                               */
03346 /*                                                                            */
03347 /******************************************************************************/
03348
03349 /********************  Bit definition for PWR_CR register  ********************/
03350 #define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
03351 #define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
03352 #define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
03353 #define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
03354 #define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
03355
03356 #define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
03357 #define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
03358 #define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
03359 #define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
03360
03361 /*!< PVD level configuration */
03362 #define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
03363 #define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
03364 #define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
03365 #define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
03366 #define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
03367 #define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
03368 #define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
03369 #define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
03370
03371 #define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
03372 #define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */
03373 #define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */
03374
03375 #define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
03376 #define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */
03377 #define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */
03378 #define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */
03379
03380 /*******************  Bit definition for PWR_CSR register  ********************/
03381 #define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
03382 #define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
03383 #define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
03384 #define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
03385 #define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */
03386 #define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */
03387
03388 #define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
03389 #define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
03390 #define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
03391
03392 /******************************************************************************/
03393 /*                                                                            */
03394 /*                      Reset and Clock Control (RCC)                         */
03395 /*                                                                            */
03396 /******************************************************************************/
03397 /********************  Bit definition for RCC_CR register  ********************/
03398 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
03399 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
03400
03401 #define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
03402 #define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
03403
03404 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
03405 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
03406 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
03407
03408 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
03409 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
03410 #define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
03411
03412 #define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
03413 #define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
03414 #define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
03415
03416 /********************  Bit definition for RCC_ICSCR register  *****************/
03417 #define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
03418 #define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
03419
03420 #define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
03421 #define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
03422 #define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
03423 #define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
03424 #define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
03425 #define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
03426 #define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
03427 #define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
03428 #define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
03429 #define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
03430
03431 /********************  Bit definition for RCC_CFGR register  ******************/
03432 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
03433 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
03434 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
03435
03436 /*!< SW configuration */
03437 #define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
03438 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
03439 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
03440 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
03441
03442 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
03443 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
03444 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
03445
03446 /*!< SWS configuration */
03447 #define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
03448 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
03449 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
03450 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
03451
03452 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
03453 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
03454 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
03455 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
03456 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
03457
03458 /*!< HPRE configuration */
03459 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
03460 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
03461 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
03462 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
03463 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
03464 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
03465 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
03466 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
03467 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
03468
03469 #define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
03470 #define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
03471 #define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
03472 #define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
03473
03474 /*!< PPRE1 configuration */
03475 #define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
03476 #define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
03477 #define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
03478 #define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
03479 #define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
03480
03481 #define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
03482 #define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
03483 #define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
03484 #define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
03485
03486 /*!< PPRE2 configuration */
03487 #define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
03488 #define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
03489 #define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
03490 #define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
03491 #define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
03492
03493 /*!< PLL entry clock source*/
03494 #define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
03495
03496 #define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
03497 #define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
03498
03499
03500 #define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
03501 #define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
03502 #define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
03503 #define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
03504 #define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
03505
03506 /*!< PLLMUL configuration */
03507 #define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
03508 #define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
03509 #define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
03510 #define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
03511 #define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
03512 #define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
03513 #define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
03514 #define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
03515 #define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
03516
03517 /*!< PLLDIV configuration */
03518 #define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
03519 #define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
03520 #define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
03521
03522
03523 /*!< PLLDIV configuration */
03524 #define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
03525 #define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
03526 #define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
03527 #define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
03528
03529
03530 #define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
03531 #define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
03532 #define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
03533 #define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
03534
03535 /*!< MCO configuration */
03536 #define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
03537 #define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
03538 #define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
03539 #define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
03540 #define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
03541 #define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
03542 #define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
03543 #define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
03544
03545 #define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
03546 #define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
03547 #define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
03548 #define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
03549
03550 /*!< MCO Prescaler configuration */
03551 #define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
03552 #define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
03553 #define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
03554 #define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
03555 #define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
03556
03557 /*!<******************  Bit definition for RCC_CIR register  ********************/
03558 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
03559 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
03560 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
03561 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
03562 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
03563 #define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
03564 #define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
03565 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
03566
03567 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
03568 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
03569 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
03570 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
03571 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
03572 #define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
03573 #define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
03574
03575 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
03576 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
03577 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
03578 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
03579 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
03580 #define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
03581 #define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
03582 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
03583
03584
03585 /*****************  Bit definition for RCC_AHBRSTR register  ******************/
03586 #define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
03587 #define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
03588 #define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
03589 #define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
03590 #define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
03591 #define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
03592 #define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00000040)        /*!< GPIO port F reset */
03593 #define  RCC_AHBRSTR_GPIOGRST                ((uint32_t)0x00000080)        /*!< GPIO port G reset */
03594 #define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
03595 #define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
03596 #define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
03597 #define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
03598 #define  RCC_AHBRSTR_AESRST                  ((uint32_t)0x08000000)        /*!< AES reset */
03599 #define  RCC_AHBRSTR_FSMCRST                 ((uint32_t)0x40000000)        /*!< FSMC reset */
03600
03601 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
03602 #define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
03603 #define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
03604 #define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
03605 #define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
03606 #define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
03607 #define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)        /*!< SDIO reset */
03608 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
03609 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
03610
03611 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
03612 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
03613 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
03614 #define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
03615 #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
03616 #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
03617 #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
03618 #define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
03619 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
03620 #define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
03621 #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
03622 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
03623 #define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
03624 #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
03625 #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
03626 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
03627 #define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
03628 #define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
03629 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
03630 #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
03631 #define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
03632
03633 /******************  Bit definition for RCC_AHBENR register  ******************/
03634 #define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
03635 #define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
03636 #define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
03637 #define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
03638 #define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
03639 #define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
03640 #define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00000040)        /*!< GPIO port F clock enable */
03641 #define  RCC_AHBENR_GPIOGEN                  ((uint32_t)0x00000080)        /*!< GPIO port G clock enable */
03642 #define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
03643 #define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
03644                                                                                 the Flash memory is in power down mode) */
03645 #define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
03646 #define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
03647 #define  RCC_AHBENR_AESEN                    ((uint32_t)0x08000000)        /*!< AES clock enable */
03648 #define  RCC_AHBENR_FSMCEN                   ((uint32_t)0x40000000)        /*!< FSMC clock enable */
03649
03650
03651 /******************  Bit definition for RCC_APB2ENR register  *****************/
03652 #define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
03653 #define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
03654 #define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
03655 #define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
03656 #define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
03657 #define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)         /*!< SDIO clock enable */
03658 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
03659 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
03660
03661
03662 /*****************  Bit definition for RCC_APB1ENR register  ******************/
03663 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
03664 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
03665 #define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
03666 #define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
03667 #define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
03668 #define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
03669 #define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
03670 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
03671 #define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
03672 #define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
03673 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
03674 #define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
03675 #define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
03676 #define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
03677 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
03678 #define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
03679 #define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
03680 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
03681 #define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
03682 #define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
03683
03684 /******************  Bit definition for RCC_AHBLPENR register  ****************/
03685 #define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
03686 #define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
03687 #define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
03688 #define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
03689 #define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
03690 #define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
03691 #define  RCC_AHBLPENR_GPIOFLPEN              ((uint32_t)0x00000040)        /*!< GPIO port F clock enabled in sleep mode */
03692 #define  RCC_AHBLPENR_GPIOGLPEN              ((uint32_t)0x00000080)        /*!< GPIO port G clock enabled in sleep mode */
03693 #define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
03694 #define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
03695                                                                                 (has effect only when the Flash memory is
03696                                                                                  in power down mode) */
03697 #define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
03698 #define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
03699 #define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
03700 #define  RCC_AHBLPENR_AESLPEN                ((uint32_t)0x08000000)        /*!< AES clock enabled in sleep mode */
03701 #define  RCC_AHBLPENR_FSMCLPEN               ((uint32_t)0x40000000)        /*!< FSMC clock enabled in sleep mode */
03702
03703 /******************  Bit definition for RCC_APB2LPENR register  ***************/
03704 #define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
03705 #define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
03706 #define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
03707 #define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
03708 #define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
03709 #define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)         /*!< SDIO clock enabled in sleep mode */
03710 #define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
03711 #define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
03712
03713 /*****************  Bit definition for RCC_APB1LPENR register  ****************/
03714 #define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
03715 #define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
03716 #define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
03717 #define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
03718 #define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
03719 #define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
03720 #define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
03721 #define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
03722 #define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
03723 #define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
03724 #define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
03725 #define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
03726 #define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)        /*!< UART 4 clock enabled in sleep mode */
03727 #define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)        /*!< UART 5 clock enabled in sleep mode */
03728 #define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
03729 #define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
03730 #define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
03731 #define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
03732 #define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
03733 #define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
03734
03735 /*******************  Bit definition for RCC_CSR register  ********************/
03736 #define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
03737 #define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
03738
03739 #define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
03740 #define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
03741 #define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
03742 #define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
03743 #define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
03744
03745 #define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
03746 #define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
03747 #define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
03748
03749 /*!< RTC congiguration */
03750 #define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
03751 #define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
03752 #define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
03753 #define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
03754
03755 #define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
03756 #define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
03757
03758 #define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
03759 #define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
03760 #define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
03761 #define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
03762 #define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
03763 #define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
03764 #define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
03765 #define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
03766
03767
03768 /******************************************************************************/
03769 /*                                                                            */
03770 /*                           Real-Time Clock (RTC)                            */
03771 /*                                                                            */
03772 /******************************************************************************/
03773 /********************  Bits definition for RTC_TR register  *******************/
03774 #define RTC_TR_PM                            ((uint32_t)0x00400000)
03775 #define RTC_TR_HT                            ((uint32_t)0x00300000)
03776 #define RTC_TR_HT_0                          ((uint32_t)0x00100000)
03777 #define RTC_TR_HT_1                          ((uint32_t)0x00200000)
03778 #define RTC_TR_HU                            ((uint32_t)0x000F0000)
03779 #define RTC_TR_HU_0                          ((uint32_t)0x00010000)
03780 #define RTC_TR_HU_1                          ((uint32_t)0x00020000)
03781 #define RTC_TR_HU_2                          ((uint32_t)0x00040000)
03782 #define RTC_TR_HU_3                          ((uint32_t)0x00080000)
03783 #define RTC_TR_MNT                           ((uint32_t)0x00007000)
03784 #define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
03785 #define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
03786 #define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
03787 #define RTC_TR_MNU                           ((uint32_t)0x00000F00)
03788 #define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
03789 #define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
03790 #define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
03791 #define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
03792 #define RTC_TR_ST                            ((uint32_t)0x00000070)
03793 #define RTC_TR_ST_0                          ((uint32_t)0x00000010)
03794 #define RTC_TR_ST_1                          ((uint32_t)0x00000020)
03795 #define RTC_TR_ST_2                          ((uint32_t)0x00000040)
03796 #define RTC_TR_SU                            ((uint32_t)0x0000000F)
03797 #define RTC_TR_SU_0                          ((uint32_t)0x00000001)
03798 #define RTC_TR_SU_1                          ((uint32_t)0x00000002)
03799 #define RTC_TR_SU_2                          ((uint32_t)0x00000004)
03800 #define RTC_TR_SU_3                          ((uint32_t)0x00000008)
03801
03802 /********************  Bits definition for RTC_DR register  *******************/
03803 #define RTC_DR_YT                            ((uint32_t)0x00F00000)
03804 #define RTC_DR_YT_0                          ((uint32_t)0x00100000)
03805 #define RTC_DR_YT_1                          ((uint32_t)0x00200000)
03806 #define RTC_DR_YT_2                          ((uint32_t)0x00400000)
03807 #define RTC_DR_YT_3                          ((uint32_t)0x00800000)
03808 #define RTC_DR_YU                            ((uint32_t)0x000F0000)
03809 #define RTC_DR_YU_0                          ((uint32_t)0x00010000)
03810 #define RTC_DR_YU_1                          ((uint32_t)0x00020000)
03811 #define RTC_DR_YU_2                          ((uint32_t)0x00040000)
03812 #define RTC_DR_YU_3                          ((uint32_t)0x00080000)
03813 #define RTC_DR_WDU                           ((uint32_t)0x0000E000)
03814 #define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
03815 #define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
03816 #define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
03817 #define RTC_DR_MT                            ((uint32_t)0x00001000)
03818 #define RTC_DR_MU                            ((uint32_t)0x00000F00)
03819 #define RTC_DR_MU_0                          ((uint32_t)0x00000100)
03820 #define RTC_DR_MU_1                          ((uint32_t)0x00000200)
03821 #define RTC_DR_MU_2                          ((uint32_t)0x00000400)
03822 #define RTC_DR_MU_3                          ((uint32_t)0x00000800)
03823 #define RTC_DR_DT                            ((uint32_t)0x00000030)
03824 #define RTC_DR_DT_0                          ((uint32_t)0x00000010)
03825 #define RTC_DR_DT_1                          ((uint32_t)0x00000020)
03826 #define RTC_DR_DU                            ((uint32_t)0x0000000F)
03827 #define RTC_DR_DU_0                          ((uint32_t)0x00000001)
03828 #define RTC_DR_DU_1                          ((uint32_t)0x00000002)
03829 #define RTC_DR_DU_2                          ((uint32_t)0x00000004)
03830 #define RTC_DR_DU_3                          ((uint32_t)0x00000008)
03831
03832 /********************  Bits definition for RTC_CR register  *******************/
03833 #define RTC_CR_COE                           ((uint32_t)0x00800000)
03834 #define RTC_CR_OSEL                          ((uint32_t)0x00600000)
03835 #define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
03836 #define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
03837 #define RTC_CR_POL                           ((uint32_t)0x00100000)
03838 #define RTC_CR_COSEL                         ((uint32_t)0x00080000)
03839 #define RTC_CR_BCK                           ((uint32_t)0x00040000)
03840 #define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
03841 #define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
03842 #define RTC_CR_TSIE                          ((uint32_t)0x00008000)
03843 #define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
03844 #define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
03845 #define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
03846 #define RTC_CR_TSE                           ((uint32_t)0x00000800)
03847 #define RTC_CR_WUTE                          ((uint32_t)0x00000400)
03848 #define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
03849 #define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
03850 #define RTC_CR_DCE                           ((uint32_t)0x00000080)
03851 #define RTC_CR_FMT                           ((uint32_t)0x00000040)
03852 #define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
03853 #define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
03854 #define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
03855 #define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
03856 #define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
03857 #define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
03858 #define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
03859
03860 /********************  Bits definition for RTC_ISR register  ******************/
03861 #define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
03862 #define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
03863 #define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
03864 #define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
03865 #define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
03866 #define RTC_ISR_TSF                          ((uint32_t)0x00000800)
03867 #define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
03868 #define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
03869 #define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
03870 #define RTC_ISR_INIT                         ((uint32_t)0x00000080)
03871 #define RTC_ISR_INITF                        ((uint32_t)0x00000040)
03872 #define RTC_ISR_RSF                          ((uint32_t)0x00000020)
03873 #define RTC_ISR_INITS                        ((uint32_t)0x00000010)
03874 #define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
03875 #define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
03876 #define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
03877 #define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
03878
03879 /********************  Bits definition for RTC_PRER register  *****************/
03880 #define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
03881 #define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
03882
03883 /********************  Bits definition for RTC_WUTR register  *****************/
03884 #define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
03885
03886 /********************  Bits definition for RTC_CALIBR register  ***************/
03887 #define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
03888 #define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
03889
03890 /********************  Bits definition for RTC_ALRMAR register  ***************/
03891 #define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
03892 #define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
03893 #define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
03894 #define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
03895 #define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
03896 #define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
03897 #define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
03898 #define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
03899 #define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
03900 #define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
03901 #define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
03902 #define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
03903 #define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
03904 #define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
03905 #define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
03906 #define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
03907 #define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
03908 #define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
03909 #define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
03910 #define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
03911 #define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
03912 #define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
03913 #define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
03914 #define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
03915 #define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
03916 #define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
03917 #define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
03918 #define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
03919 #define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
03920 #define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
03921 #define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
03922 #define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
03923 #define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
03924 #define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
03925 #define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
03926 #define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
03927 #define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
03928 #define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
03929 #define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
03930 #define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
03931
03932 /********************  Bits definition for RTC_ALRMBR register  ***************/
03933 #define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
03934 #define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
03935 #define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
03936 #define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
03937 #define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
03938 #define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
03939 #define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
03940 #define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
03941 #define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
03942 #define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
03943 #define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
03944 #define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
03945 #define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
03946 #define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
03947 #define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
03948 #define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
03949 #define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
03950 #define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
03951 #define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
03952 #define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
03953 #define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
03954 #define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
03955 #define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
03956 #define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
03957 #define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
03958 #define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
03959 #define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
03960 #define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
03961 #define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
03962 #define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
03963 #define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
03964 #define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
03965 #define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
03966 #define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
03967 #define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
03968 #define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
03969 #define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
03970 #define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
03971 #define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
03972 #define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
03973
03974 /********************  Bits definition for RTC_WPR register  ******************/
03975 #define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
03976
03977 /********************  Bits definition for RTC_SSR register  ******************/
03978 #define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
03979
03980 /********************  Bits definition for RTC_SHIFTR register  ***************/
03981 #define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
03982 #define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
03983
03984 /********************  Bits definition for RTC_TSTR register  *****************/
03985 #define RTC_TSTR_PM                          ((uint32_t)0x00400000)
03986 #define RTC_TSTR_HT                          ((uint32_t)0x00300000)
03987 #define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
03988 #define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
03989 #define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
03990 #define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
03991 #define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
03992 #define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
03993 #define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
03994 #define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
03995 #define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
03996 #define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
03997 #define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
03998 #define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
03999 #define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
04000 #define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
04001 #define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
04002 #define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
04003 #define RTC_TSTR_ST                          ((uint32_t)0x00000070)
04004 #define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
04005 #define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
04006 #define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
04007 #define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
04008 #define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
04009 #define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
04010 #define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
04011 #define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
04012
04013 /********************  Bits definition for RTC_TSDR register  *****************/
04014 #define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
04015 #define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
04016 #define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
04017 #define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
04018 #define RTC_TSDR_MT                          ((uint32_t)0x00001000)
04019 #define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
04020 #define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
04021 #define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
04022 #define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
04023 #define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
04024 #define RTC_TSDR_DT                          ((uint32_t)0x00000030)
04025 #define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
04026 #define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
04027 #define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
04028 #define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
04029 #define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
04030 #define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
04031 #define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
04032
04033 /********************  Bits definition for RTC_TSSSR register  ****************/
04034 #define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
04035
04036 /********************  Bits definition for RTC_CAL register  *****************/
04037 #define RTC_CALR_CALP                        ((uint32_t)0x00008000)
04038 #define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
04039 #define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
04040 #define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
04041 #define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
04042 #define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
04043 #define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
04044 #define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
04045 #define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
04046 #define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
04047 #define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
04048 #define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
04049 #define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
04050
04051 /********************  Bits definition for RTC_TAFCR register  ****************/
04052 #define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
04053 #define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
04054 #define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
04055 #define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
04056 #define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
04057 #define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
04058 #define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
04059 #define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
04060 #define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
04061 #define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
04062 #define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
04063 #define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
04064 #define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
04065 #define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
04066 #define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
04067 #define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
04068 #define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
04069 #define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
04070 #define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
04071 #define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
04072
04073 /********************  Bits definition for RTC_ALRMASSR register  *************/
04074 #define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
04075 #define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
04076 #define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
04077 #define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
04078 #define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
04079 #define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
04080
04081 /********************  Bits definition for RTC_ALRMBSSR register  *************/
04082 #define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
04083 #define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
04084 #define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
04085 #define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
04086 #define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
04087 #define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
04088
04089 /********************  Bits definition for RTC_BKP0R register  ****************/
04090 #define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
04091
04092 /********************  Bits definition for RTC_BKP1R register  ****************/
04093 #define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
04094
04095 /********************  Bits definition for RTC_BKP2R register  ****************/
04096 #define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
04097
04098 /********************  Bits definition for RTC_BKP3R register  ****************/
04099 #define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
04100
04101 /********************  Bits definition for RTC_BKP4R register  ****************/
04102 #define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
04103
04104 /********************  Bits definition for RTC_BKP5R register  ****************/
04105 #define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
04106
04107 /********************  Bits definition for RTC_BKP6R register  ****************/
04108 #define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
04109
04110 /********************  Bits definition for RTC_BKP7R register  ****************/
04111 #define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
04112
04113 /********************  Bits definition for RTC_BKP8R register  ****************/
04114 #define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
04115
04116 /********************  Bits definition for RTC_BKP9R register  ****************/
04117 #define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
04118
04119 /********************  Bits definition for RTC_BKP10R register  ***************/
04120 #define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
04121
04122 /********************  Bits definition for RTC_BKP11R register  ***************/
04123 #define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
04124
04125 /********************  Bits definition for RTC_BKP12R register  ***************/
04126 #define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
04127
04128 /********************  Bits definition for RTC_BKP13R register  ***************/
04129 #define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
04130
04131 /********************  Bits definition for RTC_BKP14R register  ***************/
04132 #define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
04133
04134 /********************  Bits definition for RTC_BKP15R register  ***************/
04135 #define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
04136
04137 /********************  Bits definition for RTC_BKP16R register  ***************/
04138 #define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
04139
04140 /********************  Bits definition for RTC_BKP17R register  ***************/
04141 #define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
04142
04143 /********************  Bits definition for RTC_BKP18R register  ***************/
04144 #define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
04145
04146 /********************  Bits definition for RTC_BKP19R register  ***************/
04147 #define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
04148
04149 /********************  Bits definition for RTC_BKP20R register  ***************/
04150 #define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
04151
04152 /********************  Bits definition for RTC_BKP21R register  ***************/
04153 #define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
04154
04155 /********************  Bits definition for RTC_BKP22R register  ***************/
04156 #define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
04157
04158 /********************  Bits definition for RTC_BKP23R register  ***************/
04159 #define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
04160
04161 /********************  Bits definition for RTC_BKP24R register  ***************/
04162 #define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
04163
04164 /********************  Bits definition for RTC_BKP25R register  ***************/
04165 #define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
04166
04167 /********************  Bits definition for RTC_BKP26R register  ***************/
04168 #define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
04169
04170 /********************  Bits definition for RTC_BKP27R register  ***************/
04171 #define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
04172
04173 /********************  Bits definition for RTC_BKP28R register  ***************/
04174 #define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
04175
04176 /********************  Bits definition for RTC_BKP29R register  ***************/
04177 #define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
04178
04179 /********************  Bits definition for RTC_BKP30R register  ***************/
04180 #define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
04181
04182 /********************  Bits definition for RTC_BKP31R register  ***************/
04183 #define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
04184
04185 /******************************************************************************/
04186 /*                                                                            */
04187 /*                          SD host Interface                                 */
04188 /*                                                                            */
04189 /******************************************************************************/
04190
04191 /******************  Bit definition for SDIO_POWER register  ******************/
04192 #define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
04193 #define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
04194 #define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
04195
04196 /******************  Bit definition for SDIO_CLKCR register  ******************/
04197 #define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
04198 #define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
04199 #define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
04200 #define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
04201
04202 #define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
04203 #define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
04204 #define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
04205
04206 #define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
04207 #define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
04208
04209 /*******************  Bit definition for SDIO_ARG register  *******************/
04210 #define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
04211
04212 /*******************  Bit definition for SDIO_CMD register  *******************/
04213 #define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
04214
04215 #define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
04216 #define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
04217 #define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
04218
04219 #define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
04220 #define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
04221 #define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
04222 #define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
04223 #define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
04224 #define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
04225 #define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
04226
04227 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
04228 #define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
04229
04230 /******************  Bit definition for SDIO_RESP0 register  ******************/
04231 #define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
04232
04233 /******************  Bit definition for SDIO_RESP1 register  ******************/
04234 #define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
04235
04236 /******************  Bit definition for SDIO_RESP2 register  ******************/
04237 #define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
04238
04239 /******************  Bit definition for SDIO_RESP3 register  ******************/
04240 #define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
04241
04242 /******************  Bit definition for SDIO_RESP4 register  ******************/
04243 #define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
04244
04245 /******************  Bit definition for SDIO_DTIMER register  *****************/
04246 #define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
04247
04248 /******************  Bit definition for SDIO_DLEN register  *******************/
04249 #define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
04250
04251 /******************  Bit definition for SDIO_DCTRL register  ******************/
04252 #define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
04253 #define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
04254 #define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
04255 #define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
04256
04257 #define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
04258 #define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
04259 #define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
04260 #define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
04261 #define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
04262
04263 #define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
04264 #define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
04265 #define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
04266 #define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
04267
04268 /******************  Bit definition for SDIO_DCOUNT register  *****************/
04269 #define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
04270
04271 /******************  Bit definition for SDIO_STA register  ********************/
04272 #define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
04273 #define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
04274 #define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
04275 #define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
04276 #define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
04277 #define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
04278 #define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
04279 #define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
04280 #define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
04281 #define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
04282 #define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
04283 #define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
04284 #define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
04285 #define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
04286 #define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
04287 #define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
04288 #define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
04289 #define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
04290 #define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
04291 #define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
04292 #define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
04293 #define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
04294 #define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
04295 #define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
04296
04297 /*******************  Bit definition for SDIO_ICR register  *******************/
04298 #define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
04299 #define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
04300 #define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
04301 #define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
04302 #define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
04303 #define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
04304 #define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
04305 #define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
04306 #define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
04307 #define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
04308 #define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
04309 #define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
04310 #define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
04311
04312 /******************  Bit definition for SDIO_MASK register  *******************/
04313 #define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
04314 #define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
04315 #define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
04316 #define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
04317 #define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
04318 #define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
04319 #define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
04320 #define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
04321 #define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
04322 #define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
04323 #define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
04324 #define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
04325 #define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
04326 #define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
04327 #define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
04328 #define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
04329 #define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
04330 #define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
04331 #define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
04332 #define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
04333 #define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
04334 #define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
04335 #define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
04336 #define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
04337
04338 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
04339 #define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
04340
04341 /******************  Bit definition for SDIO_FIFO register  *******************/
04342 #define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
04343
04344 /******************************************************************************/
04345 /*                                                                            */
04346 /*                     Serial Peripheral Interface (SPI)                      */
04347 /*                                                                            */
04348 /******************************************************************************/
04349
04350 /*******************  Bit definition for SPI_CR1 register  ********************/
04351 #define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
04352 #define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
04353 #define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
04354
04355 #define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
04356 #define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
04357 #define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
04358 #define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
04359
04360 #define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
04361 #define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
04362 #define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
04363 #define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
04364 #define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
04365 #define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
04366 #define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
04367 #define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
04368 #define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
04369 #define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
04370
04371 /*******************  Bit definition for SPI_CR2 register  ********************/
04372 #define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
04373 #define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
04374 #define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
04375 #define  SPI_CR2_FRF                         ((uint8_t)0x08)               /*!< Frame format */
04376 #define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
04377 #define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
04378 #define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
04379
04380 /********************  Bit definition for SPI_SR register  ********************/
04381 #define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
04382 #define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
04383 #define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
04384 #define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
04385 #define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
04386 #define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
04387 #define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
04388 #define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
04389
04390 /********************  Bit definition for SPI_DR register  ********************/
04391 #define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
04392
04393 /*******************  Bit definition for SPI_CRCPR register  ******************/
04394 #define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
04395
04396 /******************  Bit definition for SPI_RXCRCR register  ******************/
04397 #define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
04398
04399 /******************  Bit definition for SPI_TXCRCR register  ******************/
04400 #define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
04401
04402 /******************  Bit definition for SPI_I2SCFGR register  *****************/
04403 #define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
04404
04405 #define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
04406 #define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
04407 #define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
04408
04409 #define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
04410
04411 #define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
04412 #define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
04413 #define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
04414
04415 #define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
04416
04417 #define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
04418 #define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
04419 #define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
04420
04421 #define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
04422 #define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
04423
04424 /******************  Bit definition for SPI_I2SPR register  *******************/
04425 #define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
04426 #define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
04427 #define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
04428
04429 /******************************************************************************/
04430 /*                                                                            */
04431 /*                       System Configuration (SYSCFG)                        */
04432 /*                                                                            */
04433 /******************************************************************************/
04434 /*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
04435 #define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
04436 #define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
04437 #define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
04438 #define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
04439 #define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
04440 #define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
04441
04442 /*****************  Bit definition for SYSCFG_PMC register  *******************/
04443 #define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
04444
04445 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
04446 #define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
04447 #define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
04448 #define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
04449 #define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
04450
04451 /**
04452   * @brief  EXTI0 configuration
04453   */
04454 #define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
04455 #define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
04456 #define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
04457 #define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
04458 #define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
04459 #define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */
04460 #define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0006) /*!< PF[0] pin */
04461 #define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0007) /*!< PG[0] pin */
04462
04463 /**
04464   * @brief  EXTI1 configuration
04465   */
04466 #define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
04467 #define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
04468 #define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
04469 #define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
04470 #define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
04471 #define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */
04472 #define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0060) /*!< PF[1] pin */
04473 #define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0070) /*!< PG[1] pin */
04474
04475 /**
04476   * @brief  EXTI2 configuration
04477   */
04478 #define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
04479 #define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
04480 #define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
04481 #define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
04482 #define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
04483 #define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0500) /*!< PH[2] pin */
04484 #define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0600) /*!< PF[2] pin */
04485 #define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0700) /*!< PG[2] pin */
04486
04487 /**
04488   * @brief  EXTI3 configuration
04489   */
04490 #define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
04491 #define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
04492 #define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
04493 #define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
04494 #define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
04495 #define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x3000) /*!< PF[3] pin */
04496 #define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x4000) /*!< PG[3] pin */
04497
04498 /*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
04499 #define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
04500 #define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
04501 #define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
04502 #define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
04503
04504 /**
04505   * @brief  EXTI4 configuration
04506   */
04507 #define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
04508 #define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
04509 #define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
04510 #define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
04511 #define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
04512 #define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0006) /*!< PF[4] pin */
04513 #define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0007) /*!< PG[4] pin */
04514
04515 /**
04516   * @brief  EXTI5 configuration
04517   */
04518 #define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
04519 #define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
04520 #define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
04521 #define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
04522 #define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
04523 #define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0060) /*!< PF[5] pin */
04524 #define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0070) /*!< PG[5] pin */
04525
04526 /**
04527   * @brief  EXTI6 configuration
04528   */
04529 #define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
04530 #define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
04531 #define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
04532 #define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
04533 #define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
04534 #define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0600) /*!< PF[6] pin */
04535 #define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0700) /*!< PG[6] pin */
04536
04537 /**
04538   * @brief  EXTI7 configuration
04539   */
04540 #define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
04541 #define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
04542 #define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
04543 #define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
04544 #define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
04545 #define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x6000) /*!< PF[7] pin */
04546 #define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x7000) /*!< PG[7] pin */
04547
04548 /*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
04549 #define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
04550 #define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
04551 #define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
04552 #define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
04553
04554 /**
04555   * @brief  EXTI8 configuration
04556   */
04557 #define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
04558 #define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
04559 #define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
04560 #define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
04561 #define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
04562 #define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0006) /*!< PF[8] pin */
04563 #define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0007) /*!< PG[8] pin */
04564
04565 /**
04566   * @brief  EXTI9 configuration
04567   */
04568 #define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
04569 #define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
04570 #define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
04571 #define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
04572 #define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
04573 #define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0060) /*!< PF[9] pin */
04574 #define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0070) /*!< PG[9] pin */
04575
04576 /**
04577   * @brief  EXTI10 configuration
04578   */
04579 #define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
04580 #define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
04581 #define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
04582 #define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
04583 #define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
04584 #define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0600) /*!< PF[10] pin */
04585 #define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0700) /*!< PG[10] pin */
04586
04587 /**
04588   * @brief  EXTI11 configuration
04589   */
04590 #define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
04591 #define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
04592 #define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
04593 #define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
04594 #define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
04595 #define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x6000) /*!< PF[11] pin */
04596 #define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x7000) /*!< PG[11] pin */
04597
04598 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
04599 #define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
04600 #define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
04601 #define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
04602 #define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
04603
04604 /**
04605   * @brief  EXTI12 configuration
04606   */
04607 #define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
04608 #define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
04609 #define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
04610 #define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
04611 #define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
04612 #define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0006) /*!< PF[12] pin */
04613 #define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0007) /*!< PG[12] pin */
04614
04615 /**
04616   * @brief  EXTI13 configuration
04617   */
04618 #define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
04619 #define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
04620 #define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
04621 #define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
04622 #define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
04623 #define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0060) /*!< PF[13] pin */
04624 #define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0070) /*!< PG[13] pin */
04625
04626 /**
04627   * @brief  EXTI14 configuration
04628   */
04629 #define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
04630 #define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
04631 #define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
04632 #define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
04633 #define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
04634 #define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0600) /*!< PF[14] pin */
04635 #define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0700) /*!< PG[14] pin */
04636
04637 /**
04638   * @brief  EXTI15 configuration
04639   */
04640 #define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
04641 #define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
04642 #define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
04643 #define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
04644 #define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
04645 #define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x6000) /*!< PF[15] pin */
04646 #define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x7000) /*!< PG[15] pin */
04647
04648 /******************************************************************************/
04649 /*                                                                            */
04650 /*                       Routing Interface (RI)                               */
04651 /*                                                                            */
04652 /******************************************************************************/
04653
04654 /********************  Bit definition for RI_ICR register  ********************/
04655 #define  RI_ICR_IC1Z                    ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
04656 #define  RI_ICR_IC1Z_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
04657 #define  RI_ICR_IC1Z_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
04658 #define  RI_ICR_IC1Z_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
04659 #define  RI_ICR_IC1Z_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
04660
04661 #define  RI_ICR_IC2Z                    ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
04662 #define  RI_ICR_IC2Z_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
04663 #define  RI_ICR_IC2Z_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
04664 #define  RI_ICR_IC2Z_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
04665 #define  RI_ICR_IC2Z_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
04666
04667 #define  RI_ICR_IC3Z                    ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
04668 #define  RI_ICR_IC3Z_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
04669 #define  RI_ICR_IC3Z_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
04670 #define  RI_ICR_IC3Z_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
04671 #define  RI_ICR_IC3Z_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
04672
04673 #define  RI_ICR_IC4Z                    ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
04674 #define  RI_ICR_IC4Z_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
04675 #define  RI_ICR_IC4Z_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
04676 #define  RI_ICR_IC4Z_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
04677 #define  RI_ICR_IC4Z_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
04678
04679 #define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
04680 #define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
04681 #define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
04682
04683 #define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
04684 #define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
04685 #define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
04686 #define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
04687
04688 /********************  Bit definition for RI_ASCR1 register  ********************/
04689 #define  RI_ASCR1_CH                    ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
04690 #define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
04691 #define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
04692 #define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
04693 #define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
04694 #define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
04695 #define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
04696 #define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
04697 #define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
04698 #define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
04699 #define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
04700 #define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
04701 #define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
04702 #define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
04703 #define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
04704 #define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
04705 #define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
04706 #define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
04707 #define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
04708 #define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
04709 #define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
04710 #define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
04711 #define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
04712 #define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
04713 #define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
04714 #define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
04715 #define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
04716 #define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
04717 #define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
04718 #define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
04719 #define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
04720 #define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
04721
04722 /********************  Bit definition for RI_ASCR2 register  ********************/
04723 #define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
04724 #define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
04725 #define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
04726 #define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
04727 #define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
04728 #define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
04729 #define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
04730 #define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
04731 #define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
04732 #define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
04733 #define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
04734 #define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
04735 #define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
04736 #define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
04737 #define  RI_ASCR2_CH1b                  ((uint32_t)0x00020000) /*!< CH1b selection bit */
04738 #define  RI_ASCR2_CH2b                  ((uint32_t)0x00040000) /*!< CH2b selection bit */
04739 #define  RI_ASCR2_CH3b                  ((uint32_t)0x00080000) /*!< CH3b selection bit */
04740 #define  RI_ASCR2_CH6b                  ((uint32_t)0x00100000) /*!< CH6b selection bit */
04741 #define  RI_ASCR2_CH7b                  ((uint32_t)0x00200000) /*!< CH7b selection bit */
04742 #define  RI_ASCR2_CH8b                  ((uint32_t)0x00400000) /*!< CH8b selection bit */
04743 #define  RI_ASCR2_CH9b                  ((uint32_t)0x00800000) /*!< CH9b selection bit */
04744 #define  RI_ASCR2_CH10b                 ((uint32_t)0x01000000) /*!< CH10b selection bit */
04745 #define  RI_ASCR2_CH11b                 ((uint32_t)0x02000000) /*!< CH11b selection bit */
04746 #define  RI_ASCR2_CH12b                 ((uint32_t)0x04000000) /*!< CH12b selection bit */
04747 #define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
04748 #define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
04749 #define  RI_ASCR2_GR5_4                 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
04750
04751 /********************  Bit definition for RI_HYSCR1 register  ********************/
04752 #define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
04753 #define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
04754 #define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
04755 #define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
04756 #define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
04757 #define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
04758 #define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
04759 #define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
04760 #define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
04761 #define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
04762 #define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
04763 #define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
04764 #define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
04765 #define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
04766 #define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
04767 #define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
04768 #define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
04769
04770 #define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
04771 #define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
04772 #define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
04773 #define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
04774 #define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
04775 #define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
04776 #define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
04777 #define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
04778 #define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
04779 #define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
04780 #define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
04781 #define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
04782 #define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
04783 #define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
04784 #define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
04785 #define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
04786 #define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
04787
04788 /********************  Bit definition for RI_HYSCR2 register  ********************/
04789 #define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
04790 #define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
04791 #define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
04792 #define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
04793 #define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
04794 #define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
04795 #define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
04796 #define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
04797 #define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
04798 #define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
04799 #define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
04800 #define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
04801 #define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
04802 #define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
04803 #define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
04804 #define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
04805 #define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
04806
04807 #define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
04808 #define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
04809 #define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
04810 #define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
04811 #define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
04812 #define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
04813 #define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
04814 #define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
04815 #define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
04816 #define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
04817 #define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
04818 #define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
04819 #define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
04820 #define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
04821 #define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
04822 #define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
04823 #define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
04824
04825 /********************  Bit definition for RI_HYSCR3 register  ********************/
04826 #define  RI_HYSCR2_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
04827 #define  RI_HYSCR2_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
04828 #define  RI_HYSCR2_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
04829 #define  RI_HYSCR2_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
04830 #define  RI_HYSCR2_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
04831 #define  RI_HYSCR2_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
04832 #define  RI_HYSCR2_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
04833 #define  RI_HYSCR2_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
04834 #define  RI_HYSCR2_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
04835 #define  RI_HYSCR2_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
04836 #define  RI_HYSCR2_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
04837 #define  RI_HYSCR2_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
04838 #define  RI_HYSCR2_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
04839 #define  RI_HYSCR2_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
04840 #define  RI_HYSCR2_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
04841 #define  RI_HYSCR2_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
04842 #define  RI_HYSCR2_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
04843
04844 #define  RI_HYSCR3_PF                   ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
04845 #define  RI_HYSCR3_PF_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
04846 #define  RI_HYSCR3_PF_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
04847 #define  RI_HYSCR3_PF_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
04848 #define  RI_HYSCR3_PF_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
04849 #define  RI_HYSCR3_PF_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
04850 #define  RI_HYSCR3_PF_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
04851 #define  RI_HYSCR3_PF_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
04852 #define  RI_HYSCR3_PF_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
04853 #define  RI_HYSCR3_PF_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
04854 #define  RI_HYSCR3_PF_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
04855 #define  RI_HYSCR3_PF_10                ((uint32_t)0x04000000) /*!< Bit 10 */
04856 #define  RI_HYSCR3_PF_11                ((uint32_t)0x08000000) /*!< Bit 11 */
04857 #define  RI_HYSCR3_PF_12                ((uint32_t)0x10000000) /*!< Bit 12 */
04858 #define  RI_HYSCR3_PF_13                ((uint32_t)0x20000000) /*!< Bit 13 */
04859 #define  RI_HYSCR3_PF_14                ((uint32_t)0x40000000) /*!< Bit 14 */
04860 #define  RI_HYSCR3_PF_15                ((uint32_t)0x80000000) /*!< Bit 15 */
04861
04862 /********************  Bit definition for RI_HYSCR4 register  ********************/
04863 #define  RI_HYSCR4_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
04864 #define  RI_HYSCR4_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
04865 #define  RI_HYSCR4_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
04866 #define  RI_HYSCR4_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
04867 #define  RI_HYSCR4_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
04868 #define  RI_HYSCR4_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
04869 #define  RI_HYSCR4_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
04870 #define  RI_HYSCR4_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
04871 #define  RI_HYSCR4_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
04872 #define  RI_HYSCR4_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
04873 #define  RI_HYSCR4_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
04874 #define  RI_HYSCR4_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
04875 #define  RI_HYSCR4_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
04876 #define  RI_HYSCR4_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
04877 #define  RI_HYSCR4_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
04878 #define  RI_HYSCR4_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
04879 #define  RI_HYSCR4_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
04880
04881 /******************************************************************************/
04882 /*                                                                            */
04883 /*                               Timers (TIM)                                 */
04884 /*                                                                            */
04885 /******************************************************************************/
04886
04887 /*******************  Bit definition for TIM_CR1 register  ********************/
04888 #define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
04889 #define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
04890 #define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
04891 #define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
04892 #define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
04893
04894 #define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
04895 #define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
04896 #define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
04897
04898 #define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
04899
04900 #define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
04901 #define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
04902 #define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
04903
04904 /*******************  Bit definition for TIM_CR2 register  ********************/
04905 #define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
04906
04907 #define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
04908 #define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
04909 #define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
04910 #define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
04911
04912 #define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
04913
04914 /*******************  Bit definition for TIM_SMCR register  *******************/
04915 #define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
04916 #define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
04917 #define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
04918 #define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
04919
04920 #define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!<OCCS bits (OCref Clear Selection) */
04921
04922 #define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
04923 #define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
04924 #define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
04925 #define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
04926
04927 #define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
04928
04929 #define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
04930 #define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
04931 #define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
04932 #define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
04933 #define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
04934
04935 #define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
04936 #define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
04937 #define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
04938
04939 #define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
04940 #define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
04941
04942 /*******************  Bit definition for TIM_DIER register  *******************/
04943 #define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
04944 #define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
04945 #define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
04946 #define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
04947 #define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
04948 #define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
04949 #define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
04950 #define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
04951 #define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
04952 #define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
04953 #define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
04954 #define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
04955
04956 /********************  Bit definition for TIM_SR register  ********************/
04957 #define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
04958 #define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
04959 #define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
04960 #define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
04961 #define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
04962 #define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
04963 #define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
04964 #define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
04965 #define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
04966 #define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
04967
04968 /*******************  Bit definition for TIM_EGR register  ********************/
04969 #define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
04970 #define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
04971 #define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
04972 #define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
04973 #define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
04974 #define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
04975
04976 /******************  Bit definition for TIM_CCMR1 register  *******************/
04977 #define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
04978 #define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
04979 #define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
04980
04981 #define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
04982 #define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
04983
04984 #define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
04985 #define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
04986 #define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
04987 #define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
04988
04989 #define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
04990
04991 #define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
04992 #define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
04993 #define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
04994
04995 #define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
04996 #define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
04997
04998 #define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
04999 #define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
05000 #define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
05001 #define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
05002
05003 #define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
05004
05005 /*----------------------------------------------------------------------------*/
05006
05007 #define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
05008 #define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
05009 #define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
05010
05011 #define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
05012 #define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
05013 #define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
05014 #define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
05015 #define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
05016
05017 #define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
05018 #define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
05019 #define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
05020
05021 #define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
05022 #define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
05023 #define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
05024 #define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
05025 #define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
05026
05027 /******************  Bit definition for TIM_CCMR2 register  *******************/
05028 #define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
05029 #define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
05030 #define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
05031
05032 #define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
05033 #define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
05034
05035 #define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
05036 #define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
05037 #define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
05038 #define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
05039
05040 #define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
05041
05042 #define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
05043 #define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
05044 #define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
05045
05046 #define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
05047 #define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
05048
05049 #define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
05050 #define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
05051 #define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
05052 #define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
05053
05054 #define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
05055
05056 /*----------------------------------------------------------------------------*/
05057
05058 #define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
05059 #define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
05060 #define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
05061
05062 #define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
05063 #define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
05064 #define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
05065 #define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
05066 #define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
05067
05068 #define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
05069 #define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
05070 #define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
05071
05072 #define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
05073 #define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
05074 #define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
05075 #define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
05076 #define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
05077
05078 /*******************  Bit definition for TIM_CCER register  *******************/
05079 #define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
05080 #define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
05081 #define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
05082 #define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
05083 #define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
05084 #define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
05085 #define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
05086 #define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
05087 #define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
05088 #define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
05089 #define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
05090 #define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
05091
05092 /*******************  Bit definition for TIM_CNT register  ********************/
05093 #define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
05094
05095 /*******************  Bit definition for TIM_PSC register  ********************/
05096 #define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
05097
05098 /*******************  Bit definition for TIM_ARR register  ********************/
05099 #define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
05100
05101 /*******************  Bit definition for TIM_CCR1 register  *******************/
05102 #define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
05103
05104 /*******************  Bit definition for TIM_CCR2 register  *******************/
05105 #define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
05106
05107 /*******************  Bit definition for TIM_CCR3 register  *******************/
05108 #define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
05109
05110 /*******************  Bit definition for TIM_CCR4 register  *******************/
05111 #define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
05112
05113 /*******************  Bit definition for TIM_DCR register  ********************/
05114 #define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
05115 #define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
05116 #define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
05117 #define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
05118 #define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
05119 #define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
05120
05121 #define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
05122 #define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
05123 #define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
05124 #define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
05125 #define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
05126 #define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
05127
05128 /*******************  Bit definition for TIM_DMAR register  *******************/
05129 #define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
05130
05131 /*******************  Bit definition for TIM_OR register  *********************/
05132 #define  TIM_OR_TI1RMP                       ((uint16_t)0x0003)            /*!<Option register for TI1 Remapping */
05133 #define  TIM_OR_TI1RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
05134 #define  TIM_OR_TI1RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
05135
05136 /******************************************************************************/
05137 /*                                                                            */
05138 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
05139 /*                                                                            */
05140 /******************************************************************************/
05141
05142 /*******************  Bit definition for USART_SR register  *******************/
05143 #define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
05144 #define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
05145 #define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
05146 #define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
05147 #define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
05148 #define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
05149 #define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
05150 #define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
05151 #define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
05152 #define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
05153
05154 /*******************  Bit definition for USART_DR register  *******************/
05155 #define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
05156
05157 /******************  Bit definition for USART_BRR register  *******************/
05158 #define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
05159 #define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
05160
05161 /******************  Bit definition for USART_CR1 register  *******************/
05162 #define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
05163 #define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
05164 #define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
05165 #define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
05166 #define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
05167 #define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
05168 #define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
05169 #define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
05170 #define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
05171 #define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
05172 #define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
05173 #define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
05174 #define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
05175 #define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
05176 #define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< Oversampling by 8-bit mode */
05177
05178 /******************  Bit definition for USART_CR2 register  *******************/
05179 #define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
05180 #define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
05181 #define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
05182 #define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
05183 #define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
05184 #define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
05185 #define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
05186
05187 #define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
05188 #define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
05189 #define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
05190
05191 #define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
05192
05193 /******************  Bit definition for USART_CR3 register  *******************/
05194 #define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
05195 #define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
05196 #define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
05197 #define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
05198 #define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
05199 #define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
05200 #define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
05201 #define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
05202 #define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
05203 #define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
05204 #define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
05205 #define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One sample bit method enable */
05206
05207 /******************  Bit definition for USART_GTPR register  ******************/
05208 #define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
05209 #define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
05210 #define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
05211 #define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
05212 #define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
05213 #define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
05214 #define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
05215 #define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
05216 #define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
05217
05218 #define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
05219
05220 /******************************************************************************/
05221 /*                                                                            */
05222 /*                     Universal Serial Bus (USB)                             */
05223 /*                                                                            */
05224 /******************************************************************************/
05225
05226 /*!<Endpoint-specific registers */
05227 /*******************  Bit definition for USB_EP0R register  *******************/
05228 #define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05229
05230 #define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05231 #define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05232 #define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05233
05234 #define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05235 #define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05236 #define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05237
05238 #define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05239 #define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05240 #define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05241
05242 #define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05243
05244 #define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05245 #define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05246 #define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05247
05248 #define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05249 #define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05250
05251 /*******************  Bit definition for USB_EP1R register  *******************/
05252 #define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05253
05254 #define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05255 #define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05256 #define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05257
05258 #define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05259 #define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05260 #define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05261
05262 #define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05263 #define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05264 #define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05265
05266 #define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05267
05268 #define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05269 #define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05270 #define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05271
05272 #define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05273 #define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05274
05275 /*******************  Bit definition for USB_EP2R register  *******************/
05276 #define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05277
05278 #define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05279 #define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05280 #define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05281
05282 #define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05283 #define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05284 #define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05285
05286 #define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05287 #define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05288 #define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05289
05290 #define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05291
05292 #define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05293 #define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05294 #define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05295
05296 #define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05297 #define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05298
05299 /*******************  Bit definition for USB_EP3R register  *******************/
05300 #define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05301
05302 #define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05303 #define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05304 #define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05305
05306 #define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05307 #define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05308 #define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05309
05310 #define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05311 #define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05312 #define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05313
05314 #define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05315
05316 #define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05317 #define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05318 #define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05319
05320 #define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05321 #define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05322
05323 /*******************  Bit definition for USB_EP4R register  *******************/
05324 #define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05325
05326 #define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05327 #define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05328 #define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05329
05330 #define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05331 #define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05332 #define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05333
05334 #define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05335 #define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05336 #define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05337
05338 #define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05339
05340 #define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05341 #define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05342 #define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05343
05344 #define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05345 #define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05346
05347 /*******************  Bit definition for USB_EP5R register  *******************/
05348 #define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05349
05350 #define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05351 #define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05352 #define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05353
05354 #define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05355 #define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05356 #define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05357
05358 #define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05359 #define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05360 #define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05361
05362 #define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05363
05364 #define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05365 #define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05366 #define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05367
05368 #define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05369 #define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05370
05371 /*******************  Bit definition for USB_EP6R register  *******************/
05372 #define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05373
05374 #define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05375 #define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05376 #define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05377
05378 #define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05379 #define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05380 #define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05381
05382 #define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05383 #define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05384 #define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05385
05386 #define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05387
05388 #define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05389 #define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05390 #define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05391
05392 #define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05393 #define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05394
05395 /*******************  Bit definition for USB_EP7R register  *******************/
05396 #define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
05397
05398 #define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05399 #define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
05400 #define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
05401
05402 #define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
05403 #define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
05404 #define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
05405
05406 #define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
05407 #define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
05408 #define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
05409
05410 #define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
05411
05412 #define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
05413 #define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
05414 #define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
05415
05416 #define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
05417 #define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
05418
05419 /*!<Common registers */
05420 /*******************  Bit definition for USB_CNTR register  *******************/
05421 #define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!<Force USB Reset */
05422 #define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!<Power down */
05423 #define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!<Low-power mode */
05424 #define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!<Force suspend */
05425 #define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!<Resume request */
05426 #define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!<Expected Start Of Frame Interrupt Mask */
05427 #define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!<Start Of Frame Interrupt Mask */
05428 #define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!<RESET Interrupt Mask */
05429 #define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!<Suspend mode Interrupt Mask */
05430 #define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!<Wakeup Interrupt Mask */
05431 #define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!<Error Interrupt Mask */
05432 #define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
05433 #define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!<Correct Transfer Interrupt Mask */
05434
05435 /*******************  Bit definition for USB_ISTR register  *******************/
05436 #define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!<Endpoint Identifier */
05437 #define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!<Direction of transaction */
05438 #define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!<Expected Start Of Frame */
05439 #define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!<Start Of Frame */
05440 #define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!<USB RESET request */
05441 #define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!<Suspend mode request */
05442 #define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!<Wake up */
05443 #define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!<Error */
05444 #define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun */
05445 #define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!<Correct Transfer */
05446
05447 /*******************  Bit definition for USB_FNR register  ********************/
05448 #define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!<Frame Number */
05449 #define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!<Lost SOF */
05450 #define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!<Locked */
05451 #define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!<Receive Data - Line Status */
05452 #define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!<Receive Data + Line Status */
05453
05454 /******************  Bit definition for USB_DADDR register  *******************/
05455 #define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!<ADD[6:0] bits (Device Address) */
05456 #define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!<Bit 0 */
05457 #define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!<Bit 1 */
05458 #define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!<Bit 2 */
05459 #define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!<Bit 3 */
05460 #define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!<Bit 4 */
05461 #define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!<Bit 5 */
05462 #define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!<Bit 6 */
05463
05464 #define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!<Enable Function */
05465
05466 /******************  Bit definition for USB_BTABLE register  ******************/
05467 #define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!<Buffer Table */
05468
05469 /*!< Buffer descriptor table */
05470 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
05471 #define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
05472
05473 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
05474 #define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
05475
05476 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
05477 #define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
05478
05479 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
05480 #define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
05481
05482 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
05483 #define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
05484
05485 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
05486 #define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
05487
05488 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
05489 #define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
05490
05491 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
05492 #define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
05493
05494 /*----------------------------------------------------------------------------*/
05495
05496 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
05497 #define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
05498
05499 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
05500 #define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
05501
05502 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
05503 #define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
05504
05505 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
05506 #define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
05507
05508 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
05509 #define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
05510
05511 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
05512 #define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
05513
05514 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
05515 #define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
05516
05517 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
05518 #define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
05519
05520 /*----------------------------------------------------------------------------*/
05521
05522 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
05523 #define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
05524
05525 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
05526 #define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
05527
05528 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
05529 #define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
05530
05531 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
05532 #define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
05533
05534 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
05535 #define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
05536
05537 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
05538 #define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
05539
05540 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
05541 #define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
05542
05543 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
05544 #define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
05545
05546 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
05547 #define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
05548
05549 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
05550 #define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
05551
05552 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
05553 #define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
05554
05555 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
05556 #define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
05557
05558 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
05559 #define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
05560
05561 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
05562 #define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
05563
05564 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
05565 #define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
05566
05567 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
05568 #define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
05569
05570 /*----------------------------------------------------------------------------*/
05571
05572 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
05573 #define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
05574
05575 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
05576 #define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
05577
05578 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
05579 #define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
05580
05581 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
05582 #define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
05583
05584 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
05585 #define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
05586
05587 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
05588 #define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
05589
05590 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
05591 #define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
05592
05593 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
05594 #define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
05595
05596 /*----------------------------------------------------------------------------*/
05597
05598 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
05599 #define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05600
05601 #define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05602 #define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05603 #define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05604 #define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05605 #define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05606 #define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05607
05608 #define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05609
05610 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
05611 #define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05612
05613 #define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05614 #define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05615 #define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05616 #define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05617 #define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05618 #define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05619
05620 #define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05621
05622 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
05623 #define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05624
05625 #define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05626 #define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05627 #define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05628 #define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05629 #define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05630 #define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05631
05632 #define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05633
05634 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
05635 #define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05636
05637 #define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05638 #define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05639 #define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05640 #define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05641 #define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05642 #define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05643
05644 #define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05645
05646 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
05647 #define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05648
05649 #define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05650 #define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05651 #define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05652 #define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05653 #define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05654 #define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05655
05656 #define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05657
05658 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
05659 #define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05660
05661 #define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05662 #define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05663 #define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05664 #define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05665 #define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05666 #define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05667
05668 #define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05669
05670 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
05671 #define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05672
05673 #define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05674 #define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05675 #define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05676 #define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05677 #define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05678 #define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05679
05680 #define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05681
05682 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
05683 #define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05684
05685 #define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05686 #define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05687 #define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05688 #define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05689 #define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05690 #define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05691
05692 #define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05693
05694 /*----------------------------------------------------------------------------*/
05695
05696 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
05697 #define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05698
05699 #define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05700 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05701 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05702 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05703 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05704 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05705
05706 #define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05707
05708 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
05709 #define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05710
05711 #define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05712 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
05713 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05714 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05715 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05716 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05717
05718 #define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05719
05720 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
05721 #define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05722
05723 #define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05724 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05725 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05726 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05727 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05728 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05729
05730 #define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05731
05732 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
05733 #define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05734
05735 #define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05736 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05737 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05738 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05739 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05740 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05741
05742 #define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05743
05744 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
05745 #define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05746
05747 #define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05748 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05749 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05750 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05751 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05752 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05753
05754 #define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05755
05756 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
05757 #define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05758
05759 #define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05760 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05761 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05762 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05763 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05764 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05765
05766 #define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05767
05768 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
05769 #define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05770
05771 #define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05772 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05773 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05774 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05775 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05776 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05777
05778 #define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05779
05780 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
05781 #define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05782
05783 #define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05784 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05785 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05786 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05787 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05788 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05789
05790 #define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05791
05792 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
05793 #define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05794
05795 #define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05796 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
05797 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
05798 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
05799 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
05800 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
05801
05802 #define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05803
05804 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
05805 #define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05806
05807 #define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05808 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05809 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05810 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05811 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05812 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05813
05814 #define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05815
05816 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
05817 #define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05818
05819 #define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05820 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05821 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05822 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05823 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05824 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05825
05826 #define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05827
05828 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
05829 #define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05830
05831 #define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05832 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05833 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05834 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05835 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05836 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05837
05838 #define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05839
05840 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
05841 #define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05842
05843 #define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05844 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05845 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05846 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05847 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05848 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05849
05850 #define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05851
05852 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
05853 #define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05854
05855 #define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05856 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05857 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05858 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05859 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05860 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05861
05862 #define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05863
05864 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
05865 #define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
05866
05867 #define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05868 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
05869 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
05870 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
05871 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
05872 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
05873
05874 #define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
05875
05876 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
05877 #define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
05878
05879 #define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05880 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
05881 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
05882 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
05883 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
05884 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
05885
05886 #define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
05887
05888 /******************************************************************************/
05889 /*                                                                            */
05890 /*                         Window WATCHDOG (WWDG)                             */
05891 /*                                                                            */
05892 /******************************************************************************/
05893
05894 /*******************  Bit definition for WWDG_CR register  ********************/
05895 #define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
05896 #define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
05897 #define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
05898 #define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
05899 #define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
05900 #define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
05901 #define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
05902 #define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
05903
05904 #define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
05905
05906 /*******************  Bit definition for WWDG_CFR register  *******************/
05907 #define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
05908 #define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
05909 #define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
05910 #define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
05911 #define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
05912 #define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
05913 #define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
05914 #define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
05915
05916 #define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
05917 #define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
05918 #define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
05919
05920 #define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
05921
05922 /*******************  Bit definition for WWDG_SR register  ********************/
05923 #define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
05924
05925 /******************************************************************************/
05926 /*                                                                            */
05927 /*                        SystemTick (SysTick)                                */
05928 /*                                                                            */
05929 /******************************************************************************/
05930
05931 /*****************  Bit definition for SysTick_CTRL register  *****************/
05932 #define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
05933 #define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
05934 #define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
05935 #define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
05936
05937 /*****************  Bit definition for SysTick_LOAD register  *****************/
05938 #define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
05939
05940 /*****************  Bit definition for SysTick_VAL register  ******************/
05941 #define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
05942
05943 /*****************  Bit definition for SysTick_CALIB register  ****************/
05944 #define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
05945 #define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
05946 #define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
05947
05948 /******************************************************************************/
05949 /*                                                                            */
05950 /*               Nested Vectored Interrupt Controller (NVIC)                  */
05951 /*                                                                            */
05952 /******************************************************************************/
05953
05954 /******************  Bit definition for NVIC_ISER register  *******************/
05955 #define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
05956 #define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
05957 #define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
05958 #define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
05959 #define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
05960 #define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
05961 #define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
05962 #define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
05963 #define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
05964 #define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
05965 #define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
05966 #define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
05967 #define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
05968 #define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
05969 #define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
05970 #define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
05971 #define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
05972 #define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
05973 #define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
05974 #define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
05975 #define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
05976 #define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
05977 #define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
05978 #define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
05979 #define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
05980 #define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
05981 #define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
05982 #define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
05983 #define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
05984 #define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
05985 #define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
05986 #define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
05987 #define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
05988
05989 /******************  Bit definition for NVIC_ICER register  *******************/
05990 #define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
05991 #define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
05992 #define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
05993 #define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
05994 #define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
05995 #define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
05996 #define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
05997 #define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
05998 #define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
05999 #define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
06000 #define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
06001 #define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
06002 #define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
06003 #define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
06004 #define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
06005 #define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
06006 #define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
06007 #define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
06008 #define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
06009 #define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
06010 #define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
06011 #define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
06012 #define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
06013 #define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
06014 #define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
06015 #define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
06016 #define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
06017 #define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
06018 #define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
06019 #define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
06020 #define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
06021 #define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
06022 #define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
06023
06024 /******************  Bit definition for NVIC_ISPR register  *******************/
06025 #define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
06026 #define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
06027 #define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
06028 #define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
06029 #define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
06030 #define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
06031 #define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
06032 #define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
06033 #define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
06034 #define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
06035 #define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
06036 #define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
06037 #define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
06038 #define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
06039 #define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
06040 #define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
06041 #define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
06042 #define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
06043 #define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
06044 #define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
06045 #define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
06046 #define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
06047 #define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
06048 #define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
06049 #define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
06050 #define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
06051 #define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
06052 #define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
06053 #define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
06054 #define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
06055 #define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
06056 #define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
06057 #define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
06058
06059 /******************  Bit definition for NVIC_ICPR register  *******************/
06060 #define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
06061 #define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
06062 #define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
06063 #define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
06064 #define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
06065 #define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
06066 #define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
06067 #define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
06068 #define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
06069 #define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
06070 #define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
06071 #define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
06072 #define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
06073 #define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
06074 #define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
06075 #define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
06076 #define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
06077 #define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
06078 #define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
06079 #define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
06080 #define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
06081 #define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
06082 #define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
06083 #define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
06084 #define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
06085 #define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
06086 #define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
06087 #define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
06088 #define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
06089 #define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
06090 #define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
06091 #define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
06092 #define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
06093
06094 /******************  Bit definition for NVIC_IABR register  *******************/
06095 #define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
06096 #define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
06097 #define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
06098 #define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
06099 #define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
06100 #define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
06101 #define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
06102 #define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
06103 #define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
06104 #define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
06105 #define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
06106 #define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
06107 #define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
06108 #define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
06109 #define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
06110 #define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
06111 #define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
06112 #define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
06113 #define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
06114 #define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
06115 #define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
06116 #define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
06117 #define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
06118 #define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
06119 #define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
06120 #define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
06121 #define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
06122 #define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
06123 #define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
06124 #define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
06125 #define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
06126 #define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
06127 #define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
06128
06129 /******************  Bit definition for NVIC_PRI0 register  *******************/
06130 #define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
06131 #define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
06132 #define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
06133 #define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
06134
06135 /******************  Bit definition for NVIC_PRI1 register  *******************/
06136 #define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
06137 #define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
06138 #define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
06139 #define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
06140
06141 /******************  Bit definition for NVIC_PRI2 register  *******************/
06142 #define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
06143 #define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
06144 #define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
06145 #define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
06146
06147 /******************  Bit definition for NVIC_PRI3 register  *******************/
06148 #define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
06149 #define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
06150 #define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
06151 #define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
06152
06153 /******************  Bit definition for NVIC_PRI4 register  *******************/
06154 #define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
06155 #define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
06156 #define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
06157 #define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
06158
06159 /******************  Bit definition for NVIC_PRI5 register  *******************/
06160 #define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
06161 #define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
06162 #define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
06163 #define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
06164
06165 /******************  Bit definition for NVIC_PRI6 register  *******************/
06166 #define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
06167 #define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
06168 #define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
06169 #define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
06170
06171 /******************  Bit definition for NVIC_PRI7 register  *******************/
06172 #define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
06173 #define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
06174 #define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
06175 #define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
06176
06177 /******************  Bit definition for SCB_CPUID register  *******************/
06178 #define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
06179 #define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
06180 #define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
06181 #define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
06182 #define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
06183
06184 /*******************  Bit definition for SCB_ICSR register  *******************/
06185 #define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
06186 #define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
06187 #define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
06188 #define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
06189 #define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
06190 #define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
06191 #define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
06192 #define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
06193 #define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
06194 #define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
06195
06196 /*******************  Bit definition for SCB_VTOR register  *******************/
06197 #define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
06198 #define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
06199
06200 /*!<*****************  Bit definition for SCB_AIRCR register  *******************/
06201 #define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
06202 #define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
06203 #define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
06204
06205 #define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
06206 #define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
06207 #define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
06208 #define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
06209
06210 /* prority group configuration */
06211 #define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
06212 #define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
06213 #define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
06214 #define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
06215 #define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
06216 #define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
06217 #define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
06218 #define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
06219
06220 #define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
06221 #define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
06222
06223 /*******************  Bit definition for SCB_SCR register  ********************/
06224 #define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
06225 #define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
06226 #define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
06227
06228 /********************  Bit definition for SCB_CCR register  *******************/
06229 #define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
06230 #define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
06231 #define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
06232 #define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
06233 #define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
06234 #define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
06235
06236 /*******************  Bit definition for SCB_SHPR register ********************/
06237 #define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
06238 #define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
06239 #define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
06240 #define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
06241
06242 /******************  Bit definition for SCB_SHCSR register  *******************/
06243 #define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
06244 #define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
06245 #define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
06246 #define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
06247 #define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
06248 #define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
06249 #define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
06250 #define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
06251 #define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
06252 #define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
06253 #define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
06254 #define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
06255 #define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
06256 #define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
06257
06258 /*******************  Bit definition for SCB_CFSR register  *******************/
06259 /*!< MFSR */
06260 #define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
06261 #define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
06262 #define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
06263 #define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
06264 #define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
06265 /*!< BFSR */
06266 #define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
06267 #define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
06268 #define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
06269 #define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
06270 #define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
06271 #define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
06272 /*!< UFSR */
06273 #define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
06274 #define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
06275 #define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
06276 #define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
06277 #define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
06278 #define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
06279
06280 /*******************  Bit definition for SCB_HFSR register  *******************/
06281 #define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
06282 #define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
06283 #define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
06284
06285 /*******************  Bit definition for SCB_DFSR register  *******************/
06286 #define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
06287 #define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
06288 #define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
06289 #define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
06290 #define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
06291
06292 /*******************  Bit definition for SCB_MMFAR register  ******************/
06293 #define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
06294
06295 /*******************  Bit definition for SCB_BFAR register  *******************/
06296 #define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
06297
06298 /*******************  Bit definition for SCB_afsr register  *******************/
06299 #define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
06300 /**
06301   * @}
06302   */
06303
06304  /**
06305   * @}
06306   */
06307
06308 #ifdef USE_STDPERIPH_DRIVER
06309   #include "stm32l1xx_conf.h"
06310 #endif
06311
06312 /** @addtogroup Exported_macro
06313   * @{
06314   */
06315
06316 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
06317
06318 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
06319
06320 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
06321
06322 #define CLEAR_REG(REG)        ((REG) = (0x0))
06323
06324 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
06325
06326 #define READ_REG(REG)         ((REG))
06327
06328 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
06329
06330 /**
06331   * @}
06332   */
06333
06334 #ifdef __cplusplus
06335 }
06336 #endif
06337
06338 #endif /* __STM32L1XX_H */
06339
06340 /**
06341   * @}
06342   */
06343
06344   /**
06345   * @}
06346   */
06347
06348 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_adc.c Source File

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stm32l1xx_adc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_adc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
00009   *           + Initialization and Configuration
00010   *           + Power saving
00011   *           + Analog Watchdog configuration
00012   *           + Temperature Sensor & Vrefint (Voltage Reference internal) management
00013   *           + Regular Channels Configuration
00014   *           + Regular Channels DMA Configuration
00015   *           + Injected channels Configuration
00016   *           + Interrupts and flags management
00017   *
00018   *  @verbatim
00019 ================================================================================
00020                       ##### How to use this driver #####
00021 ================================================================================
00022     [..]
00023     (#) Configure the ADC Prescaler, conversion resolution and data alignment
00024         using the ADC_Init() function.
00025     (#) Activate the ADC peripheral using ADC_Cmd() function.
00026
00027     *** Regular channels group configuration ***
00028     ============================================
00029     [..]
00030     (+) To configure the ADC regular channels group features, use
00031         ADC_Init() and ADC_RegularChannelConfig() functions.
00032     (+) To activate the continuous mode, use the ADC_continuousModeCmd()
00033         function.
00034     (+) To configurate and activate the Discontinuous mode, use the
00035         ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
00036     (+) To read the ADC converted values, use the ADC_GetConversionValue()
00037         function.
00038
00039     *** DMA for Regular channels group features configuration ***
00040     =============================================================
00041     [..]
00042     (+) To enable the DMA mode for regular channels group, use the
00043                ADC_DMACmd() function.
00044     (+) To enable the generation of DMA requests continuously at the end
00045                of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
00046                function.
00047
00048     *** Injected channels group configuration ***
00049     =============================================
00050     [..]
00051     (+) To configure the ADC Injected channels group features, use
00052         ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
00053         functions.
00054     (+) To activate the continuous mode, use the ADC_continuousModeCmd()
00055         function.
00056     (+) To activate the Injected Discontinuous mode, use the
00057         ADC_InjectedDiscModeCmd() function.
00058     (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
00059         function.
00060     (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
00061         function.
00062
00063   @endverbatim
00064   *
00065   *****************************************************************************
00066   * @attention
00067   *
00068   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00069   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00070   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00071   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00072   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00073   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00074   *
00075   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00076   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00077   *
00078   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32l1xx_adc.h"
00084 #include "stm32l1xx_rcc.h"
00085
00086 /** @addtogroup STM32L1xx_StdPeriph_Driver
00087   * @{
00088   */
00089
00090 /** @defgroup ADC
00091   * @brief ADC driver modules
00092   * @{
00093   */
00094
00095 /* Private typedef -----------------------------------------------------------*/
00096 /* Private define ------------------------------------------------------------*/
00097 /* ADC DISCNUM mask */
00098 #define CR1_DISCNUM_RESET         ((uint32_t)0xFFFF1FFF)
00099
00100 /* ADC AWDCH mask */
00101 #define CR1_AWDCH_RESET           ((uint32_t)0xFFFFFFE0)
00102
00103 /* ADC Analog watchdog enable mode mask */
00104 #define CR1_AWDMODE_RESET         ((uint32_t)0xFF3FFDFF)
00105
00106 /* CR1 register Mask */
00107 #define CR1_CLEAR_MASK            ((uint32_t)0xFCFFFEFF)
00108
00109 /* ADC DELAY mask */
00110 #define CR2_DELS_RESET            ((uint32_t)0xFFFFFF0F)
00111
00112 /* ADC JEXTEN mask */
00113 #define CR2_JEXTEN_RESET          ((uint32_t)0xFFCFFFFF)
00114
00115 /* ADC JEXTSEL mask */
00116 #define CR2_JEXTSEL_RESET         ((uint32_t)0xFFF0FFFF)
00117
00118 /* CR2 register Mask */
00119 #define CR2_CLEAR_MASK            ((uint32_t)0xC0FFF7FD)
00120
00121 /* ADC SQx mask */
00122 #define SQR5_SQ_SET               ((uint32_t)0x0000001F)
00123 #define SQR4_SQ_SET               ((uint32_t)0x0000001F)
00124 #define SQR3_SQ_SET               ((uint32_t)0x0000001F)
00125 #define SQR2_SQ_SET               ((uint32_t)0x0000001F)
00126 #define SQR1_SQ_SET               ((uint32_t)0x0000001F)
00127
00128 /* ADC L Mask */
00129 #define SQR1_L_RESET              ((uint32_t)0xFE0FFFFF)
00130
00131 /* ADC JSQx mask */
00132 #define JSQR_JSQ_SET              ((uint32_t)0x0000001F)
00133
00134 /* ADC JL mask */
00135 #define JSQR_JL_SET               ((uint32_t)0x00300000)
00136 #define JSQR_JL_RESET             ((uint32_t)0xFFCFFFFF)
00137
00138 /* ADC SMPx mask */
00139 #define SMPR1_SMP_SET             ((uint32_t)0x00000007)
00140 #define SMPR2_SMP_SET             ((uint32_t)0x00000007)
00141 #define SMPR3_SMP_SET             ((uint32_t)0x00000007)
00142 #define SMPR0_SMP_SET             ((uint32_t)0x00000007)
00143
00144 /* ADC JDRx registers offset */
00145 #define JDR_OFFSET                ((uint8_t)0x30)
00146
00147 /* ADC CCR register Mask */
00148 #define CR_CLEAR_MASK             ((uint32_t)0xFFFCFFFF)
00149
00150 /* Private macro -------------------------------------------------------------*/
00151 /* Private variables ---------------------------------------------------------*/
00152 /* Private function prototypes -----------------------------------------------*/
00153 /* Private functions ---------------------------------------------------------*/
00154
00155 /** @defgroup ADC_Private_Functions
00156   * @{
00157   */
00158
00159 /** @defgroup ADC_Group1 Initialization and Configuration functions
00160  *  @brief   Initialization and Configuration functions.
00161  *
00162 @verbatim
00163  ===============================================================================
00164           ##### Initialization and Configuration functions #####
00165  ===============================================================================
00166     [..] This section provides functions allowing to:
00167         (+) Initialize and configure the ADC Prescaler.
00168         (+) ADC Conversion Resolution (12bit..6bit).
00169         (+) Scan Conversion Mode (multichannel or one channel) for regular group.
00170         (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
00171             regular group.
00172         (+) External trigger Edge and source of regular group.
00173         (+) Converted data alignment (left or right).
00174         (+) The number of ADC conversions that will be done using the sequencer
00175             for regular channel group.
00176         (+) Enable or disable the ADC peripheral.
00177
00178 @endverbatim
00179   * @{
00180   */
00181
00182 /**
00183   * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
00184   * @param  None
00185   * @retval None
00186   */
00187 void ADC_DeInit(ADC_TypeDef* ADCx)
00188 {
00189   /* Check the parameters */
00190   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00191
00192   if(ADCx == ADC1)
00193   {
00194     /* Enable ADC1 reset state */
00195     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
00196     /* Release ADC1 from reset state */
00197     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
00198   }
00199 }
00200
00201 /**
00202   * @brief  Initializes the ADCx peripheral according to the specified parameters
00203   *         in the ADC_InitStruct.
00204   * @note   This function is used to configure the global features of the ADC (
00205   *         Resolution and Data Alignment), however, the rest of the configuration
00206   *         parameters are specific to the regular channels group (scan mode
00207   *         activation, continuous mode activation, External trigger source and
00208   *         edge, number of conversion in the regular channels group sequencer).
00209   * @param  ADCx: where x can be 1 to select the ADC peripheral.
00210   * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
00211   *         the configuration information for the specified ADC peripheral.
00212   * @retval None
00213   */
00214 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
00215 {
00216   uint32_t tmpreg1 = 0;
00217   uint8_t tmpreg2 = 0;
00218
00219   /* Check the parameters */
00220   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00221   assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
00222   assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
00223   assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
00224   assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
00225   assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
00226   assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
00227   assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
00228
00229   /*---------------------------- ADCx CR1 Configuration -----------------*/
00230   /* Get the ADCx CR1 value */
00231   tmpreg1 = ADCx->CR1;
00232   /* Clear RES and SCAN bits */
00233   tmpreg1 &= CR1_CLEAR_MASK;
00234   /* Configure ADCx: scan conversion mode and resolution */
00235   /* Set SCAN bit according to ADC_ScanConvMode value */
00236   /* Set RES bit according to ADC_Resolution value */
00237   tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);
00238   /* Write to ADCx CR1 */
00239   ADCx->CR1 = tmpreg1;
00240
00241   /*---------------------------- ADCx CR2 Configuration -----------------*/
00242   /* Get the ADCx CR2 value */
00243   tmpreg1 = ADCx->CR2;
00244   /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
00245   tmpreg1 &= CR2_CLEAR_MASK;
00246   /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */
00247   /* Set ALIGN bit according to ADC_DataAlign value */
00248   /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
00249   /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
00250   /* Set CONT bit according to ADC_ContinuousConvMode value */
00251   tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
00252               ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
00253   /* Write to ADCx CR2 */
00254   ADCx->CR2 = tmpreg1;
00255
00256   /*---------------------------- ADCx SQR1 Configuration -----------------*/
00257   /* Get the ADCx SQR1 value */
00258   tmpreg1 = ADCx->SQR1;
00259   /* Clear L bits */
00260   tmpreg1 &= SQR1_L_RESET;
00261   /* Configure ADCx: regular channel sequence length */
00262   /* Set L bits according to ADC_NbrOfConversion value */
00263   tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
00264   tmpreg1 |= ((uint32_t)tmpreg2 << 20);
00265   /* Write to ADCx SQR1 */
00266   ADCx->SQR1 = tmpreg1;
00267 }
00268
00269 /**
00270   * @brief  Fills each ADC_InitStruct member with its default value.
00271   * @note   This function is used to initialize the global features of the ADC (
00272   *         Resolution and Data Alignment), however, the rest of the configuration
00273   *         parameters are specific to the regular channels group (scan mode
00274   *         activation, continuous mode activation, External trigger source and
00275   *         edge, number of conversion in the regular channels group sequencer).
00276   * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
00277   *         be initialized.
00278   * @retval None
00279   */
00280 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
00281 {
00282   /* Reset ADC init structure parameters values */
00283   /* Initialize the ADC_Resolution member */
00284   ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
00285
00286   /* Initialize the ADC_ScanConvMode member */
00287   ADC_InitStruct->ADC_ScanConvMode = DISABLE;
00288
00289   /* Initialize the ADC_ContinuousConvMode member */
00290   ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
00291
00292   /* Initialize the ADC_ExternalTrigConvEdge member */
00293   ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
00294
00295   /* Initialize the ADC_ExternalTrigConv member */
00296   ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;
00297
00298   /* Initialize the ADC_DataAlign member */
00299   ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
00300
00301   /* Initialize the ADC_NbrOfConversion member */
00302   ADC_InitStruct->ADC_NbrOfConversion = 1;
00303 }
00304
00305 /**
00306   * @brief  Initializes the ADCs peripherals according to the specified parameters
00307   *          in the ADC_CommonInitStruct.
00308   * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
00309   *         that contains the configuration information (Prescaler) for ADC1 peripheral.
00310   * @retval None
00311   */
00312 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
00313 {
00314   uint32_t tmpreg = 0;
00315
00316   /* Check the parameters */
00317   assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
00318
00319   /*---------------------------- ADC CCR Configuration -----------------*/
00320   /* Get the ADC CCR value */
00321   tmpreg = ADC->CCR;
00322
00323   /* Clear ADCPRE bit */
00324   tmpreg &= CR_CLEAR_MASK;
00325
00326   /* Configure ADCx: ADC prescaler according to ADC_Prescaler */
00327   tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler);
00328
00329   /* Write to ADC CCR */
00330   ADC->CCR = tmpreg;
00331 }
00332
00333 /**
00334   * @brief  Fills each ADC_CommonInitStruct member with its default value.
00335   * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
00336   *         which will be initialized.
00337   * @retval None
00338   */
00339 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
00340 {
00341   /* Reset ADC init structure parameters values */
00342   /* Initialize the ADC_Prescaler member */
00343   ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;
00344 }
00345
00346 /**
00347   * @brief  Enables or disables the specified ADC peripheral.
00348   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00349   * @param  NewState: new state of the ADCx peripheral.
00350   *         This parameter can be: ENABLE or DISABLE.
00351   * @retval None
00352   */
00353 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00354 {
00355   /* Check the parameters */
00356   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00357   assert_param(IS_FUNCTIONAL_STATE(NewState));
00358
00359   if (NewState != DISABLE)
00360   {
00361     /* Set the ADON bit to wake up the ADC from power down mode */
00362     ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
00363   }
00364   else
00365   {
00366     /* Disable the selected ADC peripheral */
00367     ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
00368   }
00369 }
00370
00371 /**
00372   * @brief  Selects the specified ADC Channels Bank.
00373   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00374   * @param  ADC_Bank: ADC Channels Bank.
00375   *     @arg ADC_Bank_A: ADC Channels Bank A.
00376   *     @arg ADC_Bank_B: ADC Channels Bank B.
00377   * @retval None
00378   */
00379 void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank)
00380 {
00381   /* Check the parameters */
00382   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00383   assert_param(IS_ADC_BANK(ADC_Bank));
00384
00385   if (ADC_Bank != ADC_Bank_A)
00386   {
00387     /* Set the ADC_CFG bit to select the ADC Bank B channels */
00388     ADCx->CR2 |= (uint32_t)ADC_CR2_CFG;
00389   }
00390   else
00391   {
00392     /* Reset the ADC_CFG bit to select the ADC Bank A channels */
00393     ADCx->CR2 &= (uint32_t)(~ADC_CR2_CFG);
00394   }
00395 }
00396
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup ADC_Group2 Power saving functions
00402  *  @brief   Power saving functions
00403  *
00404 @verbatim
00405  ===============================================================================
00406                     ##### Power saving functions #####
00407  ===============================================================================
00408     [..] This section provides functions allowing to reduce power consumption.
00409     [..] The two function must be combined to get the maximal benefits:
00410          When the ADC frequency is higher than the CPU one, it is recommended to:
00411          (#) Insert a freeze delay :
00412              ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze).
00413          (#) Enable the power down in Idle and Delay phases :
00414              ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE).
00415
00416 @endverbatim
00417   * @{
00418   */
00419
00420 /**
00421   * @brief  Enables or disables the ADC Power Down during Delay and/or Idle phase.
00422   * @note   ADC power-on and power-off can be managed by hardware to cut the
00423   *         consumption when the ADC is not converting.
00424   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00425   * @param  ADC_PowerDown: The ADC power down configuration.
00426   *         This parameter can be one of the following values:
00427   *     @arg ADC_PowerDown_Delay:      ADC is powered down during delay phase.
00428   *     @arg ADC_PowerDown_Idle:       ADC is powered down during Idle phase.
00429   *     @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.
00430   * @note   The ADC can be powered down:
00431   * @note   During the hardware delay insertion (using the ADC_PowerDown_Delay
00432   *           parameter).
00433   *           => The ADC is powered up again at the end of the delay.
00434   * @note   During the ADC is waiting for a trigger event ( using the
00435   *           ADC_PowerDown_Idle parameter).
00436   *           => The ADC is powered up at the next trigger event.
00437   * @note   During the hardware delay insertion or the ADC is waiting for a
00438   *           trigger event (using the ADC_PowerDown_Idle_Delay parameter).
00439   *            => The ADC is powered up only at the end of the delay and at the
00440   *              next trigger event.
00441   * @param  NewState: new state of the ADCx power down.
00442   *         This parameter can be: ENABLE or DISABLE.
00443   * @retval None
00444   */
00445 void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
00446 {
00447   /* Check the parameters */
00448   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00449   assert_param(IS_FUNCTIONAL_STATE(NewState));
00450   assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));
00451
00452   if (NewState != DISABLE)
00453   {
00454     /* Enable the ADC power-down during Delay and/or Idle phase */
00455     ADCx->CR1 |= ADC_PowerDown;
00456   }
00457   else
00458   {
00459     /* Disable The ADC power-down during Delay and/or Idle phase */
00460     ADCx->CR1 &= (uint32_t)~ADC_PowerDown;
00461   }
00462 }
00463
00464 /**
00465   * @brief  Defines the length of the delay which is applied after a conversion
00466   *         or a sequence of conversion.
00467   * @note   When the CPU clock is not fast enough to manage the data rate, a
00468   *         Hardware delay can be introduced between ADC conversions to reduce
00469   *         this data rate.
00470   * @note   The Hardware delay is inserted after :
00471   *         - each regular conversion.
00472   *         - after each sequence of injected conversions.
00473   * @note   No Hardware delay is inserted between conversions of different groups.
00474   * @note   When the hardware delay is not enough, the Freeze Delay Mode can be
00475   *         selected and a new conversion can start only if all the previous data
00476   *         of the same group have been treated:
00477   *         - for a regular conversion: once the ADC conversion data register has
00478   *           been read (using ADC_GetConversionValue() function) or if the EOC
00479   *           Flag has been cleared (using ADC_ClearFlag() function).
00480   *         - for an injected conversion: when the JEOC bit has been cleared
00481   *           (using ADC_ClearFlag() function).
00482   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00483   * @param  ADC_DelayLength: The length of delay which is applied after a
00484   *         conversion or a sequence of conversion.
00485   *   This parameter can be one of the following values:
00486   *     @arg ADC_DelayLength_None: No delay.
00487   *     @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.
00488   *     @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.
00489   *     @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles
00490   *     @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles
00491   *     @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles
00492   *     @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles
00493   *     @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles
00494   * @retval None
00495   */
00496 void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)
00497 {
00498   uint32_t tmpreg = 0;
00499
00500   /* Check the parameters */
00501   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00502   assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));
00503
00504   /* Get the old register value */
00505   tmpreg = ADCx->CR2;
00506   /* Clear the old delay length */
00507   tmpreg &= CR2_DELS_RESET;
00508   /* Set the delay length */
00509   tmpreg |= ADC_DelayLength;
00510   /* Store the new register value */
00511   ADCx->CR2 = tmpreg;
00512
00513 }
00514
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup ADC_Group3 Analog Watchdog configuration functions
00520  *  @brief   Analog Watchdog configuration functions.
00521  *
00522 @verbatim
00523  ===============================================================================
00524                    ##### Analog Watchdog configuration functions #####
00525  ===============================================================================
00526     [..] This section provides functions allowing to configure the Analog Watchdog
00527          (AWD) feature in the ADC.
00528     [..] A typical configuration Analog Watchdog is done following these steps :
00529          (#) the ADC guarded channel(s) is (are) selected using the
00530              ADC_AnalogWatchdogSingleChannelConfig() function.
00531          (#) The Analog watchdog lower and higher threshold are configured using
00532              the ADC_AnalogWatchdogThresholdsConfig() function.
00533          (#) The Analog watchdog is enabled and configured to enable the check,
00534              on one or more channels, using the  ADC_AnalogWatchdogCmd() function.
00535
00536 @endverbatim
00537   * @{
00538   */
00539
00540 /**
00541   * @brief  Enables or disables the analog watchdog on single/all regular
00542   *         or injected channels.
00543   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00544   * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
00545   *   This parameter can be one of the following values:
00546   *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single
00547   *          regular channel.
00548   *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single
00549   *          injected channel.
00550   *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a
00551   *          single regular or injected channel.
00552   *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular
00553   *          channel.
00554   *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected
00555   *          channel.
00556   *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all
00557   *           regular and injected channels.
00558   *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.
00559   * @retval None
00560   */
00561 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
00562 {
00563   uint32_t tmpreg = 0;
00564
00565   /* Check the parameters */
00566   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00567   assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
00568
00569   /* Get the old register value */
00570   tmpreg = ADCx->CR1;
00571   /* Clear AWDEN, JAWDEN and AWDSGL bits */
00572   tmpreg &= CR1_AWDMODE_RESET;
00573   /* Set the analog watchdog enable mode */
00574   tmpreg |= ADC_AnalogWatchdog;
00575   /* Store the new register value */
00576   ADCx->CR1 = tmpreg;
00577 }
00578
00579 /**
00580   * @brief  Configures the high and low thresholds of the analog watchdog.
00581   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00582   * @param  HighThreshold: the ADC analog watchdog High threshold value.
00583   *         This parameter must be a 12bit value.
00584   * @param  LowThreshold: the ADC analog watchdog Low threshold value.
00585   *         This parameter must be a 12bit value.
00586   * @retval None
00587   */
00588 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
00589                                         uint16_t LowThreshold)
00590 {
00591   /* Check the parameters */
00592   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00593   assert_param(IS_ADC_THRESHOLD(HighThreshold));
00594   assert_param(IS_ADC_THRESHOLD(LowThreshold));
00595
00596   /* Set the ADCx high threshold */
00597   ADCx->HTR = HighThreshold;
00598   /* Set the ADCx low threshold */
00599   ADCx->LTR = LowThreshold;
00600 }
00601
00602 /**
00603   * @brief  Configures the analog watchdog guarded single channel.
00604   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00605   * @param  ADC_Channel: the ADC channel to configure for the analog watchdog.
00606   *   This parameter can be one of the following values:
00607   *     @arg ADC_Channel_0: ADC Channel0 selected
00608   *     @arg ADC_Channel_1: ADC Channel1 selected
00609   *     @arg ADC_Channel_2: ADC Channel2 selected
00610   *     @arg ADC_Channel_3: ADC Channel3 selected
00611   *     @arg ADC_Channel_4: ADC Channel4 selected
00612   *     @arg ADC_Channel_5: ADC Channel5 selected
00613   *     @arg ADC_Channel_6: ADC Channel6 selected
00614   *     @arg ADC_Channel_7: ADC Channel7 selected
00615   *     @arg ADC_Channel_8: ADC Channel8 selected
00616   *     @arg ADC_Channel_9: ADC Channel9 selected
00617   *     @arg ADC_Channel_10: ADC Channel10 selected
00618   *     @arg ADC_Channel_11: ADC Channel11 selected
00619   *     @arg ADC_Channel_12: ADC Channel12 selected
00620   *     @arg ADC_Channel_13: ADC Channel13 selected
00621   *     @arg ADC_Channel_14: ADC Channel14 selected
00622   *     @arg ADC_Channel_15: ADC Channel15 selected
00623   *     @arg ADC_Channel_16: ADC Channel16 selected
00624   *     @arg ADC_Channel_17: ADC Channel17 selected
00625   *     @arg ADC_Channel_18: ADC Channel18 selected
00626   *     @arg ADC_Channel_19: ADC Channel19 selected
00627   *     @arg ADC_Channel_20: ADC Channel20 selected
00628   *     @arg ADC_Channel_21: ADC Channel21 selected
00629   *     @arg ADC_Channel_22: ADC Channel22 selected
00630   *     @arg ADC_Channel_23: ADC Channel23 selected
00631   *     @arg ADC_Channel_24: ADC Channel24 selected
00632   *     @arg ADC_Channel_25: ADC Channel25 selected
00633   *     @arg ADC_Channel_27: ADC Channel27 selected
00634   *     @arg ADC_Channel_28: ADC Channel28 selected
00635   *     @arg ADC_Channel_29: ADC Channel29 selected
00636   *     @arg ADC_Channel_30: ADC Channel30 selected
00637   *     @arg ADC_Channel_31: ADC Channel31 selected
00638   *     @arg ADC_Channel_0b: ADC Channel0b selected
00639   *     @arg ADC_Channel_1b: ADC Channel1b selected
00640   *     @arg ADC_Channel_2b: ADC Channel2b selected
00641   *     @arg ADC_Channel_3b: ADC Channel3b selected
00642   *     @arg ADC_Channel_6b: ADC Channel6b selected
00643   *     @arg ADC_Channel_7b: ADC Channel7b selected
00644   *     @arg ADC_Channel_8b: ADC Channel8b selected
00645   *     @arg ADC_Channel_9b: ADC Channel9b selected
00646   *     @arg ADC_Channel_10b: ADC Channel10b selected
00647   *     @arg ADC_Channel_11b: ADC Channel11b selected
00648   *     @arg ADC_Channel_12b: ADC Channel12b selected
00649   * @retval None
00650   */
00651 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
00652 {
00653   uint32_t tmpreg = 0;
00654
00655   /* Check the parameters */
00656   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00657   assert_param(IS_ADC_CHANNEL(ADC_Channel));
00658
00659   /* Get the old register value */
00660   tmpreg = ADCx->CR1;
00661   /* Clear the Analog watchdog channel select bits */
00662   tmpreg &= CR1_AWDCH_RESET;
00663   /* Set the Analog watchdog channel */
00664   tmpreg |= ADC_Channel;
00665   /* Store the new register value */
00666   ADCx->CR1 = tmpreg;
00667 }
00668
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function
00674  *  @brief   Temperature Sensor & Vrefint (Voltage Reference internal) management function.
00675  *
00676 @verbatim
00677  =========================================================================================
00678  ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####
00679  =========================================================================================
00680     [..] This section provides a function allowing to enable/ disable the internal
00681          connections between the ADC and the Temperature Sensor and the Vrefint
00682          source.
00683     [..] A typical configuration to get the Temperature sensor and Vrefint channels
00684          voltages is done following these steps :
00685          (#) Enable the internal connection of Temperature sensor and Vrefint sources
00686              with the ADC channels using ADC_TempSensorVrefintCmd() function.
00687          (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
00688              ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions.
00689          (#) Get the voltage values, using ADC_GetConversionValue() or
00690              ADC_GetInjectedConversionValue().
00691 @endverbatim
00692   * @{
00693   */
00694
00695 /**
00696   * @brief  Enables or disables the temperature sensor and Vrefint channel.
00697   * @param  NewState: new state of the temperature sensor and Vref int channels.
00698   *         This parameter can be: ENABLE or DISABLE.
00699   * @retval None
00700   */
00701 void ADC_TempSensorVrefintCmd(FunctionalState NewState)
00702 {
00703   /* Check the parameters */
00704   assert_param(IS_FUNCTIONAL_STATE(NewState));
00705
00706   if (NewState != DISABLE)
00707   {
00708     /* Enable the temperature sensor and Vrefint channel*/
00709     ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
00710   }
00711   else
00712   {
00713     /* Disable the temperature sensor and Vrefint channel*/
00714     ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
00715   }
00716 }
00717
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup ADC_Group5 Regular Channels Configuration functions
00723  *  @brief   Regular Channels Configuration functions.
00724  *
00725 @verbatim
00726  ===============================================================================
00727             ##### Regular Channels Configuration functions #####
00728  ===============================================================================
00729     [..] This section provides functions allowing to manage the ADC regular channels,
00730          it is composed of 2 sub sections :
00731          (#) Configuration and management functions for regular channels: This
00732              subsection provides functions allowing to configure the ADC regular
00733              channels :
00734              (++) Configure the rank in the regular group sequencer for each channel.
00735              (++) Configure the sampling time for each channel.
00736              (++) select the conversion Trigger for regular channels.
00737              (++) select the desired EOC event behavior configuration.
00738              (++) Activate the continuous Mode  (*).
00739              (++) Activate the Discontinuous Mode.
00740              -@@- Please Note that the following features for regular channels are
00741                   configurated using the ADC_Init() function :
00742                   (+@@) scan mode activation.
00743                   (+@@) continuous mode activation (**).
00744                   (+@@) External trigger source.
00745                   (+@@) External trigger edge.
00746                   (+@@) number of conversion in the regular channels group sequencer.
00747              -@@- (*) and (**) are performing the same configuration.
00748          (#) Get the conversion data: This subsection provides an important function
00749              in the ADC peripheral since it returns the converted data of the current
00750              regular channel. When the Conversion value is read, the EOC Flag is
00751              automatically cleared.
00752 @endverbatim
00753   * @{
00754   */
00755
00756 /**
00757   * @brief  Configures for the selected ADC regular channel its corresponding
00758   *         rank in the sequencer and its sampling time.
00759   * @param  ADCx: where x can be 1 to select the ADC peripheral.
00760   * @param  ADC_Channel: the ADC channel to configure.
00761   *   This parameter can be one of the following values:
00762   *     @arg ADC_Channel_0: ADC Channel0 selected
00763   *     @arg ADC_Channel_1: ADC Channel1 selected
00764   *     @arg ADC_Channel_2: ADC Channel2 selected
00765   *     @arg ADC_Channel_3: ADC Channel3 selected
00766   *     @arg ADC_Channel_4: ADC Channel4 selected
00767   *     @arg ADC_Channel_5: ADC Channel5 selected
00768   *     @arg ADC_Channel_6: ADC Channel6 selected
00769   *     @arg ADC_Channel_7: ADC Channel7 selected
00770   *     @arg ADC_Channel_8: ADC Channel8 selected
00771   *     @arg ADC_Channel_9: ADC Channel9 selected
00772   *     @arg ADC_Channel_10: ADC Channel10 selected
00773   *     @arg ADC_Channel_11: ADC Channel11 selected
00774   *     @arg ADC_Channel_12: ADC Channel12 selected
00775   *     @arg ADC_Channel_13: ADC Channel13 selected
00776   *     @arg ADC_Channel_14: ADC Channel14 selected
00777   *     @arg ADC_Channel_15: ADC Channel15 selected
00778   *     @arg ADC_Channel_16: ADC Channel16 selected
00779   *     @arg ADC_Channel_17: ADC Channel17 selected
00780   *     @arg ADC_Channel_18: ADC Channel18 selected
00781   *     @arg ADC_Channel_19: ADC Channel19 selected
00782   *     @arg ADC_Channel_20: ADC Channel20 selected
00783   *     @arg ADC_Channel_21: ADC Channel21 selected
00784   *     @arg ADC_Channel_22: ADC Channel22 selected
00785   *     @arg ADC_Channel_23: ADC Channel23 selected
00786   *     @arg ADC_Channel_24: ADC Channel24 selected
00787   *     @arg ADC_Channel_25: ADC Channel25 selected
00788   *     @arg ADC_Channel_27: ADC Channel27 selected
00789   *     @arg ADC_Channel_28: ADC Channel28 selected
00790   *     @arg ADC_Channel_29: ADC Channel29 selected
00791   *     @arg ADC_Channel_30: ADC Channel30 selected
00792   *     @arg ADC_Channel_31: ADC Channel31 selected
00793   *     @arg ADC_Channel_0b: ADC Channel0b selected
00794   *     @arg ADC_Channel_1b: ADC Channel1b selected
00795   *     @arg ADC_Channel_2b: ADC Channel2b selected
00796   *     @arg ADC_Channel_3b: ADC Channel3b selected
00797   *     @arg ADC_Channel_6b: ADC Channel6b selected
00798   *     @arg ADC_Channel_7b: ADC Channel7b selected
00799   *     @arg ADC_Channel_8b: ADC Channel8b selected
00800   *     @arg ADC_Channel_9b: ADC Channel9b selected
00801   *     @arg ADC_Channel_10b: ADC Channel10b selected
00802   *     @arg ADC_Channel_11b: ADC Channel11b selected
00803   *     @arg ADC_Channel_12b: ADC Channel12b selected
00804   * @param  Rank: The rank in the regular group sequencer. This parameter
00805   *               must be between 1 to 28.
00806   * @param  ADC_SampleTime: The sample time value to be set for the selected
00807   *         channel.
00808   *   This parameter can be one of the following values:
00809   *     @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
00810   *     @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
00811   *     @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
00812   *     @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
00813   *     @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
00814   *     @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
00815   *     @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
00816   *     @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
00817   * @retval None
00818   */
00819 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
00820 {
00821   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00822
00823   /* Check the parameters */
00824   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00825   assert_param(IS_ADC_CHANNEL(ADC_Channel));
00826   assert_param(IS_ADC_REGULAR_RANK(Rank));
00827   assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
00828
00829   /* If ADC_Channel_30 or ADC_Channel_31 is selected */
00830   if (ADC_Channel > ADC_Channel_29)
00831   {
00832     /* Get the old register value */
00833     tmpreg1 = ADCx->SMPR0;
00834     /* Calculate the mask to clear */
00835     tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));
00836     /* Clear the old sample time */
00837     tmpreg1 &= ~tmpreg2;
00838     /* Calculate the mask to set */
00839     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));
00840     /* Set the new sample time */
00841     tmpreg1 |= tmpreg2;
00842     /* Store the new register value */
00843     ADCx->SMPR0 = tmpreg1;
00844   }
00845   /* If ADC_Channel_20 ... ADC_Channel_29 is selected */
00846   else if (ADC_Channel > ADC_Channel_19)
00847   {
00848     /* Get the old register value */
00849     tmpreg1 = ADCx->SMPR1;
00850     /* Calculate the mask to clear */
00851     tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
00852     /* Clear the old sample time */
00853     tmpreg1 &= ~tmpreg2;
00854     /* Calculate the mask to set */
00855     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
00856     /* Set the new sample time */
00857     tmpreg1 |= tmpreg2;
00858     /* Store the new register value */
00859     ADCx->SMPR1 = tmpreg1;
00860   }
00861   /* If ADC_Channel_10 ... ADC_Channel_19 is selected */
00862   else if (ADC_Channel > ADC_Channel_9)
00863   {
00864     /* Get the old register value */
00865     tmpreg1 = ADCx->SMPR2;
00866     /* Calculate the mask to clear */
00867     tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
00868     /* Clear the old sample time */
00869     tmpreg1 &= ~tmpreg2;
00870     /* Calculate the mask to set */
00871     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
00872     /* Set the new sample time */
00873     tmpreg1 |= tmpreg2;
00874     /* Store the new register value */
00875     ADCx->SMPR2 = tmpreg1;
00876   }
00877   else /* ADC_Channel include in ADC_Channel_[0..9] */
00878   {
00879     /* Get the old register value */
00880     tmpreg1 = ADCx->SMPR3;
00881     /* Calculate the mask to clear */
00882     tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
00883     /* Clear the old sample time */
00884     tmpreg1 &= ~tmpreg2;
00885     /* Calculate the mask to set */
00886     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
00887     /* Set the new sample time */
00888     tmpreg1 |= tmpreg2;
00889     /* Store the new register value */
00890     ADCx->SMPR3 = tmpreg1;
00891   }
00892   /* For Rank 1 to 6 */
00893   if (Rank < 7)
00894   {
00895     /* Get the old register value */
00896     tmpreg1 = ADCx->SQR5;
00897     /* Calculate the mask to clear */
00898     tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));
00899     /* Clear the old SQx bits for the selected rank */
00900     tmpreg1 &= ~tmpreg2;
00901     /* Calculate the mask to set */
00902     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
00903     /* Set the SQx bits for the selected rank */
00904     tmpreg1 |= tmpreg2;
00905     /* Store the new register value */
00906     ADCx->SQR5 = tmpreg1;
00907   }
00908   /* For Rank 7 to 12 */
00909   else if (Rank < 13)
00910   {
00911     /* Get the old register value */
00912     tmpreg1 = ADCx->SQR4;
00913     /* Calculate the mask to clear */
00914     tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));
00915     /* Clear the old SQx bits for the selected rank */
00916     tmpreg1 &= ~tmpreg2;
00917     /* Calculate the mask to set */
00918     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
00919     /* Set the SQx bits for the selected rank */
00920     tmpreg1 |= tmpreg2;
00921     /* Store the new register value */
00922     ADCx->SQR4 = tmpreg1;
00923   }
00924   /* For Rank 13 to 18 */
00925   else if (Rank < 19)
00926   {
00927     /* Get the old register value */
00928     tmpreg1 = ADCx->SQR3;
00929     /* Calculate the mask to clear */
00930     tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));
00931     /* Clear the old SQx bits for the selected rank */
00932     tmpreg1 &= ~tmpreg2;
00933     /* Calculate the mask to set */
00934     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
00935     /* Set the SQx bits for the selected rank */
00936     tmpreg1 |= tmpreg2;
00937     /* Store the new register value */
00938     ADCx->SQR3 = tmpreg1;
00939   }
00940
00941   /* For Rank 19 to 24 */
00942   else if (Rank < 25)
00943   {
00944     /* Get the old register value */
00945     tmpreg1 = ADCx->SQR2;
00946     /* Calculate the mask to clear */
00947     tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));
00948     /* Clear the old SQx bits for the selected rank */
00949     tmpreg1 &= ~tmpreg2;
00950     /* Calculate the mask to set */
00951     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));
00952     /* Set the SQx bits for the selected rank */
00953     tmpreg1 |= tmpreg2;
00954     /* Store the new register value */
00955     ADCx->SQR2 = tmpreg1;
00956   }
00957
00958   /* For Rank 25 to 28 */
00959   else
00960   {
00961     /* Get the old register value */
00962     tmpreg1 = ADCx->SQR1;
00963     /* Calculate the mask to clear */
00964     tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));
00965     /* Clear the old SQx bits for the selected rank */
00966     tmpreg1 &= ~tmpreg2;
00967     /* Calculate the mask to set */
00968     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));
00969     /* Set the SQx bits for the selected rank */
00970     tmpreg1 |= tmpreg2;
00971     /* Store the new register value */
00972     ADCx->SQR1 = tmpreg1;
00973   }
00974 }
00975
00976 /**
00977   * @brief  Enables the selected ADC software start conversion of the regular channels.
00978   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00979   * @retval None
00980   */
00981 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
00982 {
00983   /* Check the parameters */
00984   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00985
00986   /* Enable the selected ADC conversion for regular group */
00987   ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00988 }
00989
00990 /**
00991   * @brief  Gets the selected ADC Software start regular conversion Status.
00992   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
00993   * @retval The new state of ADC software start conversion (SET or RESET).
00994   */
00995 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
00996 {
00997   FlagStatus bitstatus = RESET;
00998
00999   /* Check the parameters */
01000   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01001
01002   /* Check the status of SWSTART bit */
01003   if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
01004   {
01005     /* SWSTART bit is set */
01006     bitstatus = SET;
01007   }
01008   else
01009   {
01010     /* SWSTART bit is reset */
01011     bitstatus = RESET;
01012   }
01013   /* Return the SWSTART bit status */
01014   return  bitstatus;
01015 }
01016
01017 /**
01018   * @brief  Enables or disables the EOC on each regular channel conversion.
01019   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01020   * @param  NewState: new state of the selected ADC EOC flag rising
01021   *    This parameter can be: ENABLE or DISABLE.
01022   * @retval None
01023   */
01024 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01025 {
01026   /* Check the parameters */
01027   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01028   assert_param(IS_FUNCTIONAL_STATE(NewState));
01029
01030   if (NewState != DISABLE)
01031   {
01032     /* Enable the selected ADC EOC rising on each regular channel conversion */
01033     ADCx->CR2 |= ADC_CR2_EOCS;
01034   }
01035   else
01036   {
01037     /* Disable the selected ADC EOC rising on each regular channel conversion */
01038     ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;
01039   }
01040 }
01041
01042 /**
01043   * @brief  Enables or disables the ADC continuous conversion mode.
01044   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01045   * @param  NewState: new state of the selected ADC continuous conversion mode.
01046   *         This parameter can be: ENABLE or DISABLE.
01047   * @retval None
01048   */
01049 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01050 {
01051   /* Check the parameters */
01052   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01053   assert_param(IS_FUNCTIONAL_STATE(NewState));
01054
01055   if (NewState != DISABLE)
01056   {
01057     /* Enable the selected ADC continuous conversion mode */
01058     ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
01059   }
01060   else
01061   {
01062     /* Disable the selected ADC continuous conversion mode */
01063     ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
01064   }
01065 }
01066
01067 /**
01068   * @brief  Configures the discontinuous mode for the selected ADC regular
01069   *         group channel.
01070   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01071   * @param  Number: specifies the discontinuous mode regular channel count value.
01072   *         This number must be between 1 and 8.
01073   * @retval None
01074   */
01075 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
01076 {
01077   uint32_t tmpreg1 = 0;
01078   uint32_t tmpreg2 = 0;
01079
01080   /* Check the parameters */
01081   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01082   assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
01083
01084   /* Get the old register value */
01085   tmpreg1 = ADCx->CR1;
01086   /* Clear the old discontinuous mode channel count */
01087   tmpreg1 &= CR1_DISCNUM_RESET;
01088   /* Set the discontinuous mode channel count */
01089   tmpreg2 = Number - 1;
01090   tmpreg1 |= tmpreg2 << 13;
01091   /* Store the new register value */
01092   ADCx->CR1 = tmpreg1;
01093 }
01094
01095 /**
01096   * @brief  Enables or disables the discontinuous mode on regular group
01097   *         channel for the specified ADC.
01098   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01099   * @param  NewState: new state of the selected ADC discontinuous mode on regular
01100   *         group channel.
01101   *         This parameter can be: ENABLE or DISABLE.
01102   * @retval None
01103   */
01104 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01105 {
01106   /* Check the parameters */
01107   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01108   assert_param(IS_FUNCTIONAL_STATE(NewState));
01109
01110   if (NewState != DISABLE)
01111   {
01112     /* Enable the selected ADC regular discontinuous mode */
01113     ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
01114   }
01115   else
01116   {
01117     /* Disable the selected ADC regular discontinuous mode */
01118     ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
01119   }
01120 }
01121
01122 /**
01123   * @brief  Returns the last ADCx conversion result data for regular channel.
01124   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01125   * @retval The Data conversion value.
01126   */
01127 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
01128 {
01129   /* Check the parameters */
01130   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01131
01132   /* Return the selected ADC conversion value */
01133   return (uint16_t) ADCx->DR;
01134 }
01135
01136 /**
01137   * @}
01138   */
01139
01140 /** @defgroup ADC_Group6 Regular Channels DMA Configuration functions
01141  *  @brief   Regular Channels DMA Configuration functions.
01142  *
01143 @verbatim
01144  ===============================================================================
01145           ##### Regular Channels DMA Configuration functions #####
01146  ===============================================================================
01147     [..] This section provides functions allowing to configure the DMA for ADC regular
01148          channels.Since converted regular channel values are stored into a unique
01149          data register, it is useful to use DMA for conversion of more than one
01150          regular channel. This avoids the loss of the data already stored in the
01151          ADC Data register.
01152          When the DMA mode is enabled (using the ADC_DMACmd() function), after each
01153          conversion of a regular channel, a DMA request is generated.
01154     [..] Depending on the "DMA disable selection" configuration (using the
01155          ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA
01156          transfer, two possibilities are allowed:
01157          (+) No new DMA request is issued to the DMA controller (feature DISABLED).
01158          (+) Requests can continue to be generated (feature ENABLED).
01159
01160 @endverbatim
01161   * @{
01162   */
01163
01164 /**
01165   * @brief  Enables or disables the specified ADC DMA request.
01166   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01167   * @param  NewState: new state of the selected ADC DMA transfer.
01168   *         This parameter can be: ENABLE or DISABLE.
01169   * @retval None
01170   */
01171 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01172 {
01173   /* Check the parameters */
01174   assert_param(IS_ADC_DMA_PERIPH(ADCx));
01175   assert_param(IS_FUNCTIONAL_STATE(NewState));
01176
01177   if (NewState != DISABLE)
01178   {
01179     /* Enable the selected ADC DMA request */
01180     ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
01181   }
01182   else
01183   {
01184     /* Disable the selected ADC DMA request */
01185     ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
01186   }
01187 }
01188
01189
01190 /**
01191   * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode).
01192   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01193   * @param  NewState: new state of the selected ADC EOC flag rising
01194   *         This parameter can be: ENABLE or DISABLE.
01195   * @retval None
01196   */
01197 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01198 {
01199   /* Check the parameters */
01200   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01201   assert_param(IS_FUNCTIONAL_STATE(NewState));
01202
01203   if (NewState != DISABLE)
01204   {
01205     /* Enable the selected ADC DMA request after last transfer */
01206     ADCx->CR2 |= ADC_CR2_DDS;
01207   }
01208   else
01209   {
01210     /* Disable the selected ADC DMA request after last transfer */
01211     ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;
01212   }
01213 }
01214
01215 /**
01216   * @}
01217   */
01218
01219 /** @defgroup ADC_Group7 Injected channels Configuration functions
01220  *  @brief   Injected channels Configuration functions.
01221  *
01222 @verbatim
01223  ===============================================================================
01224             ##### Injected channels Configuration functions #####
01225  ===============================================================================
01226     [..] This section provide functions allowing to configure the ADC Injected channels,
01227          it is composed of 2 sub sections :
01228          (#) Configuration functions for Injected channels: This subsection provides
01229              functions allowing to configure the ADC injected channels :
01230              (++) Configure the rank in the injected group sequencer for each channel.
01231              (++) Configure the sampling time for each channel.
01232              (++) Activate the Auto injected Mode.
01233              (++) Activate the Discontinuous Mode.
01234              (++) scan mode activation.
01235              (++) External/software trigger source.
01236              (++) External trigger edge.
01237              (++) injected channels sequencer.
01238
01239          (#) Get the Specified Injected channel conversion data: This subsection
01240              provides an important function in the ADC peripheral since it returns
01241              the converted data of the specific injected channel.
01242
01243 @endverbatim
01244   * @{
01245   */
01246
01247 /**
01248   * @brief  Configures for the selected ADC injected channel its corresponding
01249   *         rank in the sequencer and its sample time.
01250   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01251   * @param  ADC_Channel: the ADC channel to configure.
01252   *   This parameter can be one of the following values:
01253   *     @arg ADC_Channel_0: ADC Channel0 selected
01254   *     @arg ADC_Channel_1: ADC Channel1 selected
01255   *     @arg ADC_Channel_2: ADC Channel2 selected
01256   *     @arg ADC_Channel_3: ADC Channel3 selected
01257   *     @arg ADC_Channel_4: ADC Channel4 selected
01258   *     @arg ADC_Channel_5: ADC Channel5 selected
01259   *     @arg ADC_Channel_6: ADC Channel6 selected
01260   *     @arg ADC_Channel_7: ADC Channel7 selected
01261   *     @arg ADC_Channel_8: ADC Channel8 selected
01262   *     @arg ADC_Channel_9: ADC Channel9 selected
01263   *     @arg ADC_Channel_10: ADC Channel10 selected
01264   *     @arg ADC_Channel_11: ADC Channel11 selected
01265   *     @arg ADC_Channel_12: ADC Channel12 selected
01266   *     @arg ADC_Channel_13: ADC Channel13 selected
01267   *     @arg ADC_Channel_14: ADC Channel14 selected
01268   *     @arg ADC_Channel_15: ADC Channel15 selected
01269   *     @arg ADC_Channel_16: ADC Channel16 selected
01270   *     @arg ADC_Channel_17: ADC Channel17 selected
01271   *     @arg ADC_Channel_18: ADC Channel18 selected
01272   *     @arg ADC_Channel_19: ADC Channel19 selected
01273   *     @arg ADC_Channel_20: ADC Channel20 selected
01274   *     @arg ADC_Channel_21: ADC Channel21 selected
01275   *     @arg ADC_Channel_22: ADC Channel22 selected
01276   *     @arg ADC_Channel_23: ADC Channel23 selected
01277   *     @arg ADC_Channel_24: ADC Channel24 selected
01278   *     @arg ADC_Channel_25: ADC Channel25 selected
01279   *     @arg ADC_Channel_27: ADC Channel27 selected
01280   *     @arg ADC_Channel_28: ADC Channel28 selected
01281   *     @arg ADC_Channel_29: ADC Channel29 selected
01282   *     @arg ADC_Channel_30: ADC Channel30 selected
01283   *     @arg ADC_Channel_31: ADC Channel31 selected
01284   *     @arg ADC_Channel_0b: ADC Channel0b selected
01285   *     @arg ADC_Channel_1b: ADC Channel1b selected
01286   *     @arg ADC_Channel_2b: ADC Channel2b selected
01287   *     @arg ADC_Channel_3b: ADC Channel3b selected
01288   *     @arg ADC_Channel_6b: ADC Channel6b selected
01289   *     @arg ADC_Channel_7b: ADC Channel7b selected
01290   *     @arg ADC_Channel_8b: ADC Channel8b selected
01291   *     @arg ADC_Channel_9b: ADC Channel9b selected
01292   *     @arg ADC_Channel_10b: ADC Channel10b selected
01293   *     @arg ADC_Channel_11b: ADC Channel11b selected
01294   *     @arg ADC_Channel_12b: ADC Channel12b selected
01295   * @param  Rank: The rank in the injected group sequencer. This parameter
01296   *         must be between 1 to 4.
01297   * @param  ADC_SampleTime: The sample time value to be set for the selected
01298   *         channel. This parameter can be one of the following values:
01299   *     @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
01300   *     @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
01301   *     @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
01302   *     @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
01303   *     @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
01304   *     @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
01305   *     @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
01306   *     @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
01307   * @retval None
01308   */
01309 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
01310 {
01311   uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
01312
01313   /* Check the parameters */
01314   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01315   assert_param(IS_ADC_CHANNEL(ADC_Channel));
01316   assert_param(IS_ADC_INJECTED_RANK(Rank));
01317   assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
01318
01319   /* If ADC_Channel_30 or ADC_Channel_31 is selected */
01320   if (ADC_Channel > ADC_Channel_29)
01321   {
01322     /* Get the old register value */
01323     tmpreg1 = ADCx->SMPR0;
01324     /* Calculate the mask to clear */
01325     tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));
01326     /* Clear the old sample time */
01327     tmpreg1 &= ~tmpreg2;
01328     /* Calculate the mask to set */
01329     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));
01330     /* Set the new sample time */
01331     tmpreg1 |= tmpreg2;
01332     /* Store the new register value */
01333     ADCx->SMPR0 = tmpreg1;
01334   }
01335   /* If ADC_Channel_20 ... ADC_Channel_29 is selected */
01336   else if (ADC_Channel > ADC_Channel_19)
01337   {
01338     /* Get the old register value */
01339     tmpreg1 = ADCx->SMPR1;
01340     /* Calculate the mask to clear */
01341     tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
01342     /* Clear the old sample time */
01343     tmpreg1 &= ~tmpreg2;
01344     /* Calculate the mask to set */
01345     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
01346     /* Set the new sample time */
01347     tmpreg1 |= tmpreg2;
01348     /* Store the new register value */
01349     ADCx->SMPR1 = tmpreg1;
01350   }
01351   /* If ADC_Channel_10 ... ADC_Channel_19 is selected */
01352   else if (ADC_Channel > ADC_Channel_9)
01353   {
01354     /* Get the old register value */
01355     tmpreg1 = ADCx->SMPR2;
01356     /* Calculate the mask to clear */
01357     tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
01358     /* Clear the old sample time */
01359     tmpreg1 &= ~tmpreg2;
01360     /* Calculate the mask to set */
01361     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
01362     /* Set the new sample time */
01363     tmpreg1 |= tmpreg2;
01364     /* Store the new register value */
01365     ADCx->SMPR2 = tmpreg1;
01366   }
01367   else /* ADC_Channel include in ADC_Channel_[0..9] */
01368   {
01369     /* Get the old register value */
01370     tmpreg1 = ADCx->SMPR3;
01371     /* Calculate the mask to clear */
01372     tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
01373     /* Clear the old sample time */
01374     tmpreg1 &= ~tmpreg2;
01375     /* Calculate the mask to set */
01376     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
01377     /* Set the new sample time */
01378     tmpreg1 |= tmpreg2;
01379     /* Store the new register value */
01380     ADCx->SMPR3 = tmpreg1;
01381   }
01382
01383   /* Rank configuration */
01384   /* Get the old register value */
01385   tmpreg1 = ADCx->JSQR;
01386   /* Get JL value: Number = JL+1 */
01387   tmpreg3 =  (tmpreg1 & JSQR_JL_SET)>> 20;
01388   /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */
01389   tmpreg2 = (uint32_t)(JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));
01390   /* Clear the old JSQx bits for the selected rank */
01391   tmpreg1 &= ~tmpreg2;
01392   /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */
01393   tmpreg2 = (uint32_t)(((uint32_t)(ADC_Channel)) << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));
01394   /* Set the JSQx bits for the selected rank */
01395   tmpreg1 |= tmpreg2;
01396   /* Store the new register value */
01397   ADCx->JSQR = tmpreg1;
01398 }
01399
01400 /**
01401   * @brief  Configures the sequencer length for injected channels.
01402   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01403   * @param  Length: The sequencer length.
01404   *         This parameter must be a number between 1 to 4.
01405   * @retval None
01406   */
01407 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
01408 {
01409   uint32_t tmpreg1 = 0;
01410   uint32_t tmpreg2 = 0;
01411
01412   /* Check the parameters */
01413   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01414   assert_param(IS_ADC_INJECTED_LENGTH(Length));
01415
01416   /* Get the old register value */
01417   tmpreg1 = ADCx->JSQR;
01418   /* Clear the old injected sequence length JL bits */
01419   tmpreg1 &= JSQR_JL_RESET;
01420   /* Set the injected sequence length JL bits */
01421   tmpreg2 = Length - 1;
01422   tmpreg1 |= tmpreg2 << 20;
01423   /* Store the new register value */
01424   ADCx->JSQR = tmpreg1;
01425 }
01426
01427 /**
01428   * @brief  Set the injected channels conversion value offset.
01429   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01430   * @param  ADC_InjectedChannel: the ADC injected channel to set its offset.
01431   *   This parameter can be one of the following values:
01432   *     @arg ADC_InjectedChannel_1: Injected Channel1 selected.
01433   *     @arg ADC_InjectedChannel_2: Injected Channel2 selected.
01434   *     @arg ADC_InjectedChannel_3: Injected Channel3 selected.
01435   *     @arg ADC_InjectedChannel_4: Injected Channel4 selected.
01436   * @param  Offset: the offset value for the selected ADC injected channel
01437   *         This parameter must be a 12bit value.
01438   * @retval None
01439   */
01440 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
01441 {
01442   __IO uint32_t tmp = 0;
01443
01444   /* Check the parameters */
01445   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01446   assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
01447   assert_param(IS_ADC_OFFSET(Offset));
01448
01449   tmp = (uint32_t)ADCx;
01450   tmp += ADC_InjectedChannel;
01451
01452   /* Set the selected injected channel data offset */
01453   *(__IO uint32_t *) tmp = (uint32_t)Offset;
01454 }
01455
01456 /**
01457   * @brief  Configures the ADCx external trigger for injected channels conversion.
01458   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01459   * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected
01460   *    conversion. This parameter can be one of the following values:
01461   *     @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected
01462   *     @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected
01463   *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
01464   *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
01465   *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
01466   *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
01467   *     @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
01468   *     @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
01469   *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
01470   *     @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected
01471   *     @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected
01472   *     @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
01473   * @retval None
01474   */
01475 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
01476 {
01477   uint32_t tmpreg = 0;
01478
01479   /* Check the parameters */
01480   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01481   assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
01482
01483   /* Get the old register value */
01484   tmpreg = ADCx->CR2;
01485   /* Clear the old external event selection for injected group */
01486   tmpreg &= CR2_JEXTSEL_RESET;
01487   /* Set the external event selection for injected group */
01488   tmpreg |= ADC_ExternalTrigInjecConv;
01489   /* Store the new register value */
01490   ADCx->CR2 = tmpreg;
01491 }
01492
01493 /**
01494   * @brief  Configures the ADCx external trigger edge for injected channels conversion.
01495   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01496   * @param  ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger
01497   *         edge to start injected conversion.
01498   *   This parameter can be one of the following values:
01499   *     @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for
01500   *          injected conversion.
01501   *     @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge
01502   *     @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge
01503   *     @arg ADC_ExternalTrigConvEdge_RisingFalling: detection on
01504   *          both rising and falling edge
01505   * @retval None
01506   */
01507 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
01508 {
01509   uint32_t tmpreg = 0;
01510
01511   /* Check the parameters */
01512   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01513   assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
01514
01515   /* Get the old register value */
01516   tmpreg = ADCx->CR2;
01517   /* Clear the old external trigger edge for injected group */
01518   tmpreg &= CR2_JEXTEN_RESET;
01519   /* Set the new external trigger edge for injected group */
01520   tmpreg |= ADC_ExternalTrigInjecConvEdge;
01521   /* Store the new register value */
01522   ADCx->CR2 = tmpreg;
01523 }
01524
01525 /**
01526   * @brief  Enables the selected ADC software start conversion of the injected
01527   *         channels.
01528   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01529   * @retval None
01530   */
01531 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
01532 {
01533   /* Check the parameters */
01534   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01535   /* Enable the selected ADC conversion for injected group */
01536   ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
01537 }
01538
01539 /**
01540   * @brief  Gets the selected ADC Software start injected conversion Status.
01541   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01542   * @retval The new state of ADC software start injected conversion (SET or RESET).
01543   */
01544 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
01545 {
01546   FlagStatus bitstatus = RESET;
01547
01548   /* Check the parameters */
01549   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01550
01551   /* Check the status of JSWSTART bit */
01552   if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
01553   {
01554     /* JSWSTART bit is set */
01555     bitstatus = SET;
01556   }
01557   else
01558   {
01559     /* JSWSTART bit is reset */
01560     bitstatus = RESET;
01561   }
01562   /* Return the JSWSTART bit status */
01563   return  bitstatus;
01564 }
01565
01566 /**
01567   * @brief  Enables or disables the selected ADC automatic injected group
01568   *         conversion after regular one.
01569   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01570   * @param  NewState: new state of the selected ADC auto injected
01571   *         conversion.
01572   *         This parameter can be: ENABLE or DISABLE.
01573   * @retval None
01574   */
01575 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01576 {
01577   /* Check the parameters */
01578   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01579   assert_param(IS_FUNCTIONAL_STATE(NewState));
01580
01581   if (NewState != DISABLE)
01582   {
01583     /* Enable the selected ADC automatic injected group conversion */
01584     ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
01585   }
01586   else
01587   {
01588     /* Disable the selected ADC automatic injected group conversion */
01589     ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
01590   }
01591 }
01592
01593 /**
01594   * @brief  Enables or disables the discontinuous mode for injected group
01595   *         channel for the specified ADC.
01596   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01597   * @param  NewState: new state of the selected ADC discontinuous mode
01598   *         on injected group channel. This parameter can be: ENABLE or DISABLE.
01599   * @retval None
01600   */
01601 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
01602 {
01603   /* Check the parameters */
01604   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01605   assert_param(IS_FUNCTIONAL_STATE(NewState));
01606
01607   if (NewState != DISABLE)
01608   {
01609     /* Enable the selected ADC injected discontinuous mode */
01610     ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
01611   }
01612   else
01613   {
01614     /* Disable the selected ADC injected discontinuous mode */
01615     ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
01616   }
01617 }
01618
01619 /**
01620   * @brief  Returns the ADC injected channel conversion result.
01621   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01622   * @param  ADC_InjectedChannel: the converted ADC injected channel.
01623   *   This parameter can be one of the following values:
01624   *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
01625   *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
01626   *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
01627   *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
01628   * @retval The Data conversion value.
01629   */
01630 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
01631 {
01632   __IO uint32_t tmp = 0;
01633
01634   /* Check the parameters */
01635   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01636   assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
01637
01638   tmp = (uint32_t)ADCx;
01639   tmp += ADC_InjectedChannel + JDR_OFFSET;
01640
01641   /* Returns the selected injected channel conversion data value */
01642   return (uint16_t) (*(__IO uint32_t*)  tmp);
01643 }
01644
01645 /**
01646   * @}
01647   */
01648
01649 /** @defgroup ADC_Group8 Interrupts and flags management functions
01650  *  @brief   Interrupts and flags management functions.
01651  *
01652 @verbatim
01653  ===============================================================================
01654             ##### Interrupts and flags management functions #####
01655  ===============================================================================
01656     [..] This section provides functions allowing to configure the ADC Interrupts
01657          and get the status and clear flags and Interrupts pending bits.
01658
01659     [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into
01660          3 groups:
01661   *** Flags and Interrupts for ADC regular channels ***
01662   =====================================================
01663     [..]
01664         (+)Flags :
01665            (##) ADC_FLAG_OVR : Overrun detection when regular converted data are
01666                 lost.
01667            (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate
01668                 (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
01669                 the end of :
01670                 (+++) a regular CHANNEL conversion.
01671                 (+++) sequence of regular GROUP conversions.
01672
01673
01674            (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular
01675                 CHANNEL conversion starts.
01676            (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new
01677                 regular conversion can be launched.
01678         (+)Interrupts :
01679            (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
01680                 event.
01681            (##) ADC_IT_EOC : specifies the interrupt source for Regular channel
01682                 end of conversion event.
01683
01684   *** Flags and Interrupts for ADC Injected channels ***
01685   ======================================================
01686         (+)Flags :
01687            (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at
01688                 the end of injected GROUP conversion.
01689            (##) ADC_FLAG_JSTRT: Injected channel start +  to indicate hardware when
01690                 injected GROUP conversion starts.
01691            (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new
01692                 injected conversion can be launched.
01693         (+)Interrupts
01694            (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
01695                 end of conversion event.
01696   *** General Flags and Interrupts for the ADC ***
01697   ================================================
01698         (+)Flags :
01699            (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage
01700                 crosses the programmed thresholds values.
01701            (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready
01702                 to convert.
01703         (+)Interrupts :
01704            (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog
01705                 event.
01706
01707     [..] The user should identify which mode will be used in his application to
01708          manage the ADC controller events: Polling mode or Interrupt mode.
01709
01710     [..] In the Polling Mode it is advised to use the following functions:
01711          (+) ADC_GetFlagStatus() : to check if flags events occur.
01712          (+) ADC_ClearFlag()     : to clear the flags events.
01713
01714     [..] In the Interrupt Mode it is advised to use the following functions:
01715          (+) ADC_ITConfig()       : to enable or disable the interrupt source.
01716          (+) ADC_GetITStatus()    : to check if Interrupt occurs.
01717          (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
01718              (corresponding Flag).
01719 @endverbatim
01720   * @{
01721   */
01722
01723 /**
01724   * @brief  Enables or disables the specified ADC interrupts.
01725   * @param  ADCx: where x can be 1 to select the ADC peripheral.
01726   * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
01727   *   This parameter can be one of the following values:
01728   *     @arg ADC_IT_EOC: End of conversion interrupt
01729   *     @arg ADC_IT_AWD: Analog watchdog interrupt
01730   *     @arg ADC_IT_JEOC: End of injected conversion interrupt
01731   *     @arg ADC_IT_OVR: overrun interrupt
01732   * @param  NewState: new state of the specified ADC interrupts.
01733   *         This parameter can be: ENABLE or DISABLE.
01734   * @retval None
01735   */
01736 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
01737 {
01738   uint32_t itmask = 0;
01739
01740   /* Check the parameters */
01741   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01742   assert_param(IS_FUNCTIONAL_STATE(NewState));
01743   assert_param(IS_ADC_IT(ADC_IT));
01744
01745   /* Get the ADC IT index */
01746   itmask = (uint8_t)ADC_IT;
01747   itmask = (uint32_t)0x01 << itmask;
01748
01749   if (NewState != DISABLE)
01750   {
01751     /* Enable the selected ADC interrupts */
01752     ADCx->CR1 |= itmask;
01753   }
01754   else
01755   {
01756     /* Disable the selected ADC interrupts */
01757     ADCx->CR1 &= (~(uint32_t)itmask);
01758   }
01759 }
01760
01761 /**
01762   * @brief  Checks whether the specified ADC flag is set or not.
01763   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01764   * @param  ADC_FLAG: specifies the flag to check.
01765   *   This parameter can be one of the following values:
01766   *     @arg ADC_FLAG_AWD: Analog watchdog flag
01767   *     @arg ADC_FLAG_EOC: End of conversion flag
01768   *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
01769   *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
01770   *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
01771   *     @arg ADC_FLAG_OVR: Overrun flag
01772   *     @arg ADC_FLAG_ADONS: ADC ON status
01773   *     @arg ADC_FLAG_RCNR: Regular channel not ready
01774   *     @arg ADC_FLAG_JCNR: Injected channel not ready
01775   * @retval The new state of ADC_FLAG (SET or RESET).
01776   */
01777 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
01778 {
01779   FlagStatus bitstatus = RESET;
01780
01781   /* Check the parameters */
01782   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01783   assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
01784
01785   /* Check the status of the specified ADC flag */
01786   if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
01787   {
01788     /* ADC_FLAG is set */
01789     bitstatus = SET;
01790   }
01791   else
01792   {
01793     /* ADC_FLAG is reset */
01794     bitstatus = RESET;
01795   }
01796   /* Return the ADC_FLAG status */
01797   return  bitstatus;
01798 }
01799
01800 /**
01801   * @brief  Clears the ADCx's pending flags.
01802   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01803   * @param  ADC_FLAG: specifies the flag to clear.
01804   *   This parameter can be any combination of the following values:
01805   *     @arg ADC_FLAG_AWD: Analog watchdog flag
01806   *     @arg ADC_FLAG_EOC: End of conversion flag
01807   *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
01808   *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
01809   *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
01810   *     @arg ADC_FLAG_OVR: overrun flag
01811   * @retval None
01812   */
01813 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
01814 {
01815   /* Check the parameters */
01816   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01817   assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
01818
01819   /* Clear the selected ADC flags */
01820   ADCx->SR = ~(uint32_t)ADC_FLAG;
01821 }
01822
01823 /**
01824   * @brief  Checks whether the specified ADC interrupt has occurred or not.
01825   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01826   * @param  ADC_IT: specifies the ADC interrupt source to check.
01827   *   This parameter can be one of the following values:
01828   *     @arg ADC_IT_EOC: End of conversion interrupt
01829   *     @arg ADC_IT_AWD: Analog watchdog interrupt
01830   *     @arg ADC_IT_JEOC: End of injected conversion interrupt
01831   *     @arg ADC_IT_OVR: Overrun interrupt
01832   * @retval The new state of ADC_IT (SET or RESET).
01833   */
01834 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
01835 {
01836   ITStatus bitstatus = RESET;
01837   uint32_t itmask = 0, enablestatus = 0;
01838
01839   /* Check the parameters */
01840   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01841   assert_param(IS_ADC_IT(ADC_IT));
01842
01843   /* Get the ADC IT index */
01844   itmask = (uint32_t)((uint32_t)ADC_IT >> 8);
01845
01846   /* Get the ADC_IT enable bit status */
01847   enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT));
01848
01849   /* Check the status of the specified ADC interrupt */
01850   if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
01851   {
01852     /* ADC_IT is set */
01853     bitstatus = SET;
01854   }
01855   else
01856   {
01857     /* ADC_IT is reset */
01858     bitstatus = RESET;
01859   }
01860   /* Return the ADC_IT status */
01861   return  bitstatus;
01862 }
01863
01864 /**
01865   * @brief  Clears the ADCx's interrupt pending bits.
01866   * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
01867   * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
01868   *   This parameter can be one of the following values:
01869   *     @arg ADC_IT_EOC: End of conversion interrupt
01870   *     @arg ADC_IT_AWD: Analog watchdog interrupt
01871   *     @arg ADC_IT_JEOC: End of injected conversion interrupt
01872   *     @arg ADC_IT_OVR: Overrun interrupt
01873   * @retval None
01874   */
01875 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
01876 {
01877   uint8_t itmask = 0;
01878
01879   /* Check the parameters */
01880   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01881   assert_param(IS_ADC_IT(ADC_IT));
01882
01883   /* Get the ADC IT index */
01884   itmask = (uint8_t)(ADC_IT >> 8);
01885
01886   /* Clear the selected ADC interrupt pending bits */
01887   ADCx->SR = ~(uint32_t)itmask;
01888 }
01889
01890 /**
01891   * @}
01892   */
01893
01894 /**
01895   * @}
01896   */
01897
01898 /**
01899   * @}
01900   */
01901
01902 /**
01903   * @}
01904   */
01905
01906 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_adc.h Source File

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stm32l1xx_adc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the ADC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_ADC_H
00028 #define __STM32L1xx_ADC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup ADC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  ADC Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t ADC_Resolution;                /*!< Selects the resolution of the conversion.
00054                                                This parameter can be a value of @ref ADC_Resolution */
00055
00056   FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
00057                                                Scan (multichannel) or Single (one channel) mode.
00058                                                This parameter can be set to ENABLE or DISABLE */
00059
00060   FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
00061                                                Continuous or Single mode.
00062                                                This parameter can be set to ENABLE or DISABLE. */
00063
00064   uint32_t ADC_ExternalTrigConvEdge;      /*!< Selects the external trigger Edge and enables the
00065                                                trigger of a regular group. This parameter can be a value
00066                                                of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
00067
00068   uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
00069                                                to digital conversion of regular channels. This parameter
00070                                                can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
00071
00072   uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
00073                                                This parameter can be a value of @ref ADC_data_align */
00074
00075   uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions that will be done
00076                                                using the sequencer for regular channel group.
00077                                                This parameter must range from 1 to 27. */
00078 }ADC_InitTypeDef;
00079
00080 typedef struct
00081 {
00082   uint32_t ADC_Prescaler;                 /*!< Selects the ADC prescaler.
00083                                                This parameter can be a value
00084                                                of @ref ADC_Prescaler */
00085 }ADC_CommonInitTypeDef;
00086
00087 /* Exported constants --------------------------------------------------------*/
00088
00089 /** @defgroup ADC_Exported_Constants
00090   * @{
00091   */
00092 #define IS_ADC_ALL_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
00093 #define IS_ADC_DMA_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
00094
00095 /** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
00096   * @{
00097   */
00098 #define ADC_PowerDown_Delay                        ((uint32_t)0x00010000)
00099 #define ADC_PowerDown_Idle                         ((uint32_t)0x00020000)
00100 #define ADC_PowerDown_Idle_Delay                   ((uint32_t)0x00030000)
00101
00102 #define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
00103                                  ((DWON) == ADC_PowerDown_Idle) || \
00104                                  ((DWON) == ADC_PowerDown_Idle_Delay))
00105 /**
00106   * @}
00107   */
00108
00109
00110 /** @defgroup ADC_Prescaler
00111   * @{
00112   */
00113 #define ADC_Prescaler_Div1                         ((uint32_t)0x00000000)
00114 #define ADC_Prescaler_Div2                         ((uint32_t)0x00010000)
00115 #define ADC_Prescaler_Div4                         ((uint32_t)0x00020000)
00116
00117 #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
00118                                      ((PRESCALER) == ADC_Prescaler_Div2) || \
00119                                      ((PRESCALER) == ADC_Prescaler_Div4))
00120 /**
00121   * @}
00122   */
00123
00124
00125
00126 /** @defgroup ADC_Resolution
00127   * @{
00128   */
00129 #define ADC_Resolution_12b                         ((uint32_t)0x00000000)
00130 #define ADC_Resolution_10b                         ((uint32_t)0x01000000)
00131 #define ADC_Resolution_8b                          ((uint32_t)0x02000000)
00132 #define ADC_Resolution_6b                          ((uint32_t)0x03000000)
00133
00134 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
00135                                        ((RESOLUTION) == ADC_Resolution_10b) || \
00136                                        ((RESOLUTION) == ADC_Resolution_8b) || \
00137                                        ((RESOLUTION) == ADC_Resolution_6b))
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
00144   * @{
00145   */
00146 #define ADC_ExternalTrigConvEdge_None              ((uint32_t)0x00000000)
00147 #define ADC_ExternalTrigConvEdge_Rising            ((uint32_t)0x10000000)
00148 #define ADC_ExternalTrigConvEdge_Falling           ((uint32_t)0x20000000)
00149 #define ADC_ExternalTrigConvEdge_RisingFalling     ((uint32_t)0x30000000)
00150
00151 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
00152                                     ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
00153                                     ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
00154                                     ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
00160   * @{
00161   */
00162
00163 /* TIM2 */
00164 #define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x02000000)
00165 #define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
00166 #define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
00167
00168 /* TIM3 */
00169 #define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
00170 #define ADC_ExternalTrigConv_T3_CC3                ((uint32_t)0x08000000)
00171 #define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x04000000)
00172
00173 /* TIM4 */
00174 #define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x05000000)
00175 #define ADC_ExternalTrigConv_T4_TRGO               ((uint32_t)0x09000000)
00176
00177 /* TIM6 */
00178 #define ADC_ExternalTrigConv_T6_TRGO               ((uint32_t)0x0A000000)
00179
00180 /* TIM9 */
00181 #define ADC_ExternalTrigConv_T9_CC2                ((uint32_t)0x00000000)
00182 #define ADC_ExternalTrigConv_T9_TRGO               ((uint32_t)0x01000000)
00183
00184 /* EXTI */
00185 #define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
00186
00187 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2)  || \
00188                                   ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
00189                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3)  || \
00190                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2)  || \
00191                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
00192                                   ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4)  || \
00193                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
00194                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1)  || \
00195                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3)  || \
00196                                   ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
00197                                   ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
00198                                   ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup ADC_data_align
00204   * @{
00205   */
00206
00207 #define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
00208 #define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
00209
00210 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
00211                                   ((ALIGN) == ADC_DataAlign_Left))
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup ADC_channels
00217   * @{
00218   */
00219 /* ADC Bank A Channels -------------------------------------------------------*/
00220 #define ADC_Channel_0                              ((uint8_t)0x00)
00221 #define ADC_Channel_1                              ((uint8_t)0x01)
00222 #define ADC_Channel_2                              ((uint8_t)0x02)
00223 #define ADC_Channel_3                              ((uint8_t)0x03)
00224
00225 #define ADC_Channel_6                              ((uint8_t)0x06)
00226 #define ADC_Channel_7                              ((uint8_t)0x07)
00227 #define ADC_Channel_8                              ((uint8_t)0x08)
00228 #define ADC_Channel_9                              ((uint8_t)0x09)
00229 #define ADC_Channel_10                             ((uint8_t)0x0A)
00230 #define ADC_Channel_11                             ((uint8_t)0x0B)
00231 #define ADC_Channel_12                             ((uint8_t)0x0C)
00232
00233
00234 /* ADC Bank B Channels -------------------------------------------------------*/
00235 #define ADC_Channel_0b                             ADC_Channel_0
00236 #define ADC_Channel_1b                             ADC_Channel_1
00237 #define ADC_Channel_2b                             ADC_Channel_2
00238 #define ADC_Channel_3b                             ADC_Channel_3
00239
00240 #define ADC_Channel_6b                             ADC_Channel_6
00241 #define ADC_Channel_7b                             ADC_Channel_7
00242 #define ADC_Channel_8b                             ADC_Channel_8
00243 #define ADC_Channel_9b                             ADC_Channel_9
00244 #define ADC_Channel_10b                            ADC_Channel_10
00245 #define ADC_Channel_11b                            ADC_Channel_11
00246 #define ADC_Channel_12b                            ADC_Channel_12
00247
00248 /* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
00249 #define ADC_Channel_4                              ((uint8_t)0x04)
00250 #define ADC_Channel_5                              ((uint8_t)0x05)
00251
00252 #define ADC_Channel_13                             ((uint8_t)0x0D)
00253 #define ADC_Channel_14                             ((uint8_t)0x0E)
00254 #define ADC_Channel_15                             ((uint8_t)0x0F)
00255 #define ADC_Channel_16                             ((uint8_t)0x10)
00256 #define ADC_Channel_17                             ((uint8_t)0x11)
00257 #define ADC_Channel_18                             ((uint8_t)0x12)
00258 #define ADC_Channel_19                             ((uint8_t)0x13)
00259 #define ADC_Channel_20                             ((uint8_t)0x14)
00260 #define ADC_Channel_21                             ((uint8_t)0x15)
00261 #define ADC_Channel_22                             ((uint8_t)0x16)
00262 #define ADC_Channel_23                             ((uint8_t)0x17)
00263 #define ADC_Channel_24                             ((uint8_t)0x18)
00264 #define ADC_Channel_25                             ((uint8_t)0x19)
00265
00266 #define ADC_Channel_27                             ((uint8_t)0x1B)
00267 #define ADC_Channel_28                             ((uint8_t)0x1C)
00268 #define ADC_Channel_29                             ((uint8_t)0x1D)
00269 #define ADC_Channel_30                             ((uint8_t)0x1E)
00270 #define ADC_Channel_31                             ((uint8_t)0x1F)
00271
00272 #define ADC_Channel_TempSensor                     ((uint8_t)ADC_Channel_16)
00273 #define ADC_Channel_Vrefint                        ((uint8_t)ADC_Channel_17)
00274
00275 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0)  || ((CHANNEL) == ADC_Channel_1)  || \
00276                                  ((CHANNEL) == ADC_Channel_2)  || ((CHANNEL) == ADC_Channel_3)  || \
00277                                  ((CHANNEL) == ADC_Channel_4)  || ((CHANNEL) == ADC_Channel_5)  || \
00278                                  ((CHANNEL) == ADC_Channel_6)  || ((CHANNEL) == ADC_Channel_7)  || \
00279                                  ((CHANNEL) == ADC_Channel_8)  || ((CHANNEL) == ADC_Channel_9)  || \
00280                                  ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
00281                                  ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
00282                                  ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
00283                                  ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
00284                                  ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
00285                                  ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
00286                                  ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
00287                                  ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
00288                                  ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
00289                                  ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
00290                                  ((CHANNEL) == ADC_Channel_31))
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup ADC_sampling_times
00296   * @{
00297   */
00298
00299 #define ADC_SampleTime_4Cycles                     ((uint8_t)0x00)
00300 #define ADC_SampleTime_9Cycles                     ((uint8_t)0x01)
00301 #define ADC_SampleTime_16Cycles                    ((uint8_t)0x02)
00302 #define ADC_SampleTime_24Cycles                    ((uint8_t)0x03)
00303 #define ADC_SampleTime_48Cycles                    ((uint8_t)0x04)
00304 #define ADC_SampleTime_96Cycles                    ((uint8_t)0x05)
00305 #define ADC_SampleTime_192Cycles                   ((uint8_t)0x06)
00306 #define ADC_SampleTime_384Cycles                   ((uint8_t)0x07)
00307
00308 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles)   || \
00309                                   ((TIME) == ADC_SampleTime_9Cycles)   || \
00310                                   ((TIME) == ADC_SampleTime_16Cycles)  || \
00311                                   ((TIME) == ADC_SampleTime_24Cycles)  || \
00312                                   ((TIME) == ADC_SampleTime_48Cycles)  || \
00313                                   ((TIME) == ADC_SampleTime_96Cycles)  || \
00314                                   ((TIME) == ADC_SampleTime_192Cycles) || \
00315                                   ((TIME) == ADC_SampleTime_384Cycles))
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup ADC_Delay_length
00321   * @{
00322   */
00323
00324 #define ADC_DelayLength_None                       ((uint8_t)0x00)
00325 #define ADC_DelayLength_Freeze                     ((uint8_t)0x10)
00326 #define ADC_DelayLength_7Cycles                    ((uint8_t)0x20)
00327 #define ADC_DelayLength_15Cycles                   ((uint8_t)0x30)
00328 #define ADC_DelayLength_31Cycles                   ((uint8_t)0x40)
00329 #define ADC_DelayLength_63Cycles                   ((uint8_t)0x50)
00330 #define ADC_DelayLength_127Cycles                  ((uint8_t)0x60)
00331 #define ADC_DelayLength_255Cycles                  ((uint8_t)0x70)
00332
00333 #define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None)      || \
00334                                      ((LENGTH) == ADC_DelayLength_Freeze)    || \
00335                                      ((LENGTH) == ADC_DelayLength_7Cycles)   || \
00336                                      ((LENGTH) == ADC_DelayLength_15Cycles)  || \
00337                                      ((LENGTH) == ADC_DelayLength_31Cycles)  || \
00338                                      ((LENGTH) == ADC_DelayLength_63Cycles)  || \
00339                                      ((LENGTH) == ADC_DelayLength_127Cycles) || \
00340                                      ((LENGTH) == ADC_DelayLength_255Cycles))
00341
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
00347   * @{
00348   */
00349 #define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
00350 #define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
00351 #define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
00352 #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
00353
00354 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None)    || \
00355                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising)  || \
00356                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
00357                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
00358 /**
00359   * @}
00360   */
00361
00362
00363 /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
00364   * @{
00365   */
00366
00367
00368 /* TIM2 */
00369 #define ADC_ExternalTrigInjecConv_T2_TRGO          ((uint32_t)0x00020000)
00370 #define ADC_ExternalTrigInjecConv_T2_CC1           ((uint32_t)0x00030000)
00371
00372 /* TIM3 */
00373 #define ADC_ExternalTrigInjecConv_T3_CC4           ((uint32_t)0x00040000)
00374
00375 /* TIM4 */
00376 #define ADC_ExternalTrigInjecConv_T4_TRGO          ((uint32_t)0x00050000)
00377 #define ADC_ExternalTrigInjecConv_T4_CC1           ((uint32_t)0x00060000)
00378 #define ADC_ExternalTrigInjecConv_T4_CC2           ((uint32_t)0x00070000)
00379 #define ADC_ExternalTrigInjecConv_T4_CC3           ((uint32_t)0x00080000)
00380
00381 /* TIM7 */
00382 #define ADC_ExternalTrigInjecConv_T7_TRGO          ((uint32_t)0x000A0000)
00383
00384 /* TIM9 */
00385 #define ADC_ExternalTrigInjecConv_T9_CC1           ((uint32_t)0x00000000)
00386 #define ADC_ExternalTrigInjecConv_T9_TRGO          ((uint32_t)0x00010000)
00387
00388 /* TIM10 */
00389 #define ADC_ExternalTrigInjecConv_T10_CC1          ((uint32_t)0x00090000)
00390
00391 /* EXTI */
00392 #define ADC_ExternalTrigInjecConv_Ext_IT15         ((uint32_t)0x000F0000)
00393
00394 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1)  || \
00395                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
00396                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
00397                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1)  || \
00398                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4)  || \
00399                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
00400                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1)  || \
00401                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2)  || \
00402                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3)  || \
00403                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
00404                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
00405                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup ADC_injected_channel_selection
00411   * @{
00412   */
00413 #define ADC_InjectedChannel_1                      ((uint8_t)0x18)
00414 #define ADC_InjectedChannel_2                      ((uint8_t)0x1C)
00415 #define ADC_InjectedChannel_3                      ((uint8_t)0x20)
00416 #define ADC_InjectedChannel_4                      ((uint8_t)0x24)
00417
00418 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
00419                                           ((CHANNEL) == ADC_InjectedChannel_2) || \
00420                                           ((CHANNEL) == ADC_InjectedChannel_3) || \
00421                                           ((CHANNEL) == ADC_InjectedChannel_4))
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup ADC_analog_watchdog_selection
00427   * @{
00428   */
00429
00430 #define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
00431 #define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
00432 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
00433 #define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
00434 #define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
00435 #define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
00436 #define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
00437
00438 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable)        || \
00439                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable)      || \
00440                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
00441                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable)           || \
00442                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable)         || \
00443                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable)   || \
00444                                           ((WATCHDOG) == ADC_AnalogWatchdog_None))
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup ADC_interrupts_definition
00450   * @{
00451   */
00452
00453 #define ADC_IT_AWD                                 ((uint16_t)0x0106)
00454 #define ADC_IT_EOC                                 ((uint16_t)0x0205)
00455 #define ADC_IT_JEOC                                ((uint16_t)0x0407)
00456 #define ADC_IT_OVR                                 ((uint16_t)0x201A)
00457
00458 #define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
00459                        ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup ADC_flags_definition
00465   * @{
00466   */
00467
00468 #define ADC_FLAG_AWD                               ((uint16_t)0x0001)
00469 #define ADC_FLAG_EOC                               ((uint16_t)0x0002)
00470 #define ADC_FLAG_JEOC                              ((uint16_t)0x0004)
00471 #define ADC_FLAG_JSTRT                             ((uint16_t)0x0008)
00472 #define ADC_FLAG_STRT                              ((uint16_t)0x0010)
00473 #define ADC_FLAG_OVR                               ((uint16_t)0x0020)
00474 #define ADC_FLAG_ADONS                             ((uint16_t)0x0040)
00475 #define ADC_FLAG_RCNR                              ((uint16_t)0x0100)
00476 #define ADC_FLAG_JCNR                              ((uint16_t)0x0200)
00477
00478 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
00479
00480 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD)   || ((FLAG) == ADC_FLAG_EOC)  || \
00481                                ((FLAG) == ADC_FLAG_JEOC)  || ((FLAG)== ADC_FLAG_JSTRT) || \
00482                                ((FLAG) == ADC_FLAG_STRT)  || ((FLAG)== ADC_FLAG_OVR)   || \
00483                                ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR)  || \
00484                                ((FLAG) == ADC_FLAG_JCNR))
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup ADC_thresholds
00490   * @{
00491   */
00492
00493 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup ADC_injected_offset
00500   * @{
00501   */
00502
00503 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
00504
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup ADC_injected_length
00510   * @{
00511   */
00512
00513 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
00514
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup ADC_injected_rank
00520   * @{
00521   */
00522
00523 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
00524
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup ADC_regular_length
00530   * @{
00531   */
00532
00533 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
00534
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup ADC_regular_rank
00540   * @{
00541   */
00542
00543 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
00544
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup ADC_regular_discontinuous_mode_number
00550   * @{
00551   */
00552
00553 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
00554
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup ADC_Bank_Selection
00560   * @{
00561   */
00562 #define ADC_Bank_A                                 ((uint8_t)0x00)
00563 #define ADC_Bank_B                                 ((uint8_t)0x01)
00564 #define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A)   || ((BANK) == ADC_Bank_B))
00565
00566 /**
00567   * @}
00568   */
00569
00570 /**
00571   * @}
00572   */
00573
00574 /* Exported macro ------------------------------------------------------------*/
00575 /* Exported functions ------------------------------------------------------- */
00576
00577 /*  Function used to set the ADC configuration to the default reset state *****/
00578 void ADC_DeInit(ADC_TypeDef* ADCx);
00579
00580 /* Initialization and Configuration functions *********************************/
00581 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
00582 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
00583 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
00584 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
00585 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00586 void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
00587
00588 /* Power saving functions *****************************************************/
00589 void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
00590 void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
00591
00592 /* Analog Watchdog configuration functions ************************************/
00593 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
00594 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
00595 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
00596
00597 /* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
00598 void ADC_TempSensorVrefintCmd(FunctionalState NewState);
00599
00600 /* Regular Channels Configuration functions ***********************************/
00601 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
00602 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
00603 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
00604 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00605 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00606 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
00607 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00608 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
00609
00610 /* Regular Channels DMA Configuration functions *******************************/
00611 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00612 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00613
00614 /* Injected channels Configuration functions **********************************/
00615 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
00616 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
00617 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
00618 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
00619 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
00620 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
00621 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
00622 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00623 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00624 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
00625
00626 /* Interrupts and flags management functions **********************************/
00627 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
00628 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
00629 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
00630 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
00631 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
00632
00633 #ifdef __cplusplus
00634 }
00635 #endif
00636
00637 #endif /*__STM32L1xx_ADC_H */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /**
00644   * @}
00645   */
00646
00647 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes.c Source File

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stm32l1xx_aes.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_aes.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the AES peripheral:
00009   *           + Configuration
00010   *           + Read/Write operations
00011   *           + DMA transfers management
00012   *           + Interrupts and flags management
00013   *
00014   *  @verbatim
00015  ===============================================================================
00016                         ##### AES Peripheral features #####
00017  ===============================================================================
00018 ....[..]
00019    (#) The Advanced Encryption Standard hardware accelerator (AES) can be used
00020        to both encipher and decipher data using AES algorithm.
00021    (#) The AES supports 4 operation modes:
00022        (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
00023        (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
00024        (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
00025        (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
00026    (#) Moreover 3 chaining modes are supported:
00027        (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
00028        (++) Cipher block chaining (CBC): Each block is XORed with the previous block
00029        (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
00030           plain text to give the cipher text
00031   (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
00032   (#) The AES peripheral supports write/read error handling with interrupt capability.
00033   (#) Automatic data flow control with support of direct memory access (DMA) using
00034       2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
00035       (DMA2 Channel3).
00036
00037                       ##### How to use this driver #####
00038  ===============================================================================
00039     [..]
00040         (#) AES AHB clock must be enabled to get write access to AES registers
00041             using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
00042         (#) Initialize the key using AES_KeyInit().
00043         (#) Configure the AES operation mode using AES_Init().
00044         (#) If required, enable interrupt source using AES_ITConfig() and
00045             enable the AES interrupt vector using NVIC_Init().
00046         (#) If required, when using the DMA mode.
00047             (##) Configure the DMA using DMA_Init().
00048             (##) Enable DMA requests using AES_DMAConfig().
00049         (#) Enable the AES peripheral using AES_Cmd().
00050     @endverbatim
00051
00052   ******************************************************************************
00053   * @attention
00054   *
00055   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00056   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00057   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00058   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00059   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00060   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00061   *
00062   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00063   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00064   *
00065   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00066   ******************************************************************************
00067   */
00068
00069 /* Includes ------------------------------------------------------------------*/
00070 #include "stm32l1xx_aes.h"
00071 #include "stm32l1xx_rcc.h"
00072
00073 /** @addtogroup STM32L1xx_StdPeriph_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup AES
00078   * @brief AES driver modules
00079   * @{
00080   */
00081
00082 /* Private typedef -----------------------------------------------------------*/
00083 /* Private define ------------------------------------------------------------*/
00084 #define CR_CLEAR_MASK  ((uint32_t)0xFFFFFF81)
00085
00086 /* Private macro -------------------------------------------------------------*/
00087 /* Private variables ---------------------------------------------------------*/
00088 /* Private function prototypes -----------------------------------------------*/
00089 /* Private functions ---------------------------------------------------------*/
00090
00091 /** @defgroup AES_Private_Functions
00092   * @{
00093   */
00094
00095 /** @defgroup AES_Group1 Initialization and configuration
00096  *  @brief   Initialization and configuration.
00097  *
00098 @verbatim
00099  ===============================================================================
00100                 ##### Initialization and configuration #####
00101  ===============================================================================
00102
00103 @endverbatim
00104   * @{
00105   */
00106
00107   /**
00108   * @brief  Deinitializes AES peripheral registers to their default reset values.
00109   * @param  None
00110   * @retval None
00111   */
00112 void AES_DeInit(void)
00113 {
00114   /* Enable AES reset state */
00115   RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
00116   /* Release AES from reset state */
00117   RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
00118 }
00119
00120 /**
00121   * @brief  Initializes the AES peripheral according to the specified parameters
00122   *         in the AES_InitStruct:
00123   *           - AES_Operation: specifies the operation mode (encryption, decryption...).
00124   *           - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
00125   *           - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
00126   * @note   If AES is already enabled, use AES_Cmd(DISABLE) before setting the new
00127   *         configuration (When AES is enabled, setting configuration is forbidden).
00128   * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure that contains
00129   *         the configuration information for AES peripheral.
00130   * @retval None
00131   */
00132 void AES_Init(AES_InitTypeDef* AES_InitStruct)
00133 {
00134   uint32_t tmpreg = 0;
00135
00136   /* Check the parameters */
00137   assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
00138   assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
00139   assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));
00140
00141   /* Get AES CR register value */
00142   tmpreg = AES->CR;
00143
00144   /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
00145   tmpreg &= (uint32_t)CR_CLEAR_MASK;
00146
00147   tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);
00148
00149   AES->CR = (uint32_t) tmpreg;
00150 }
00151
00152 /**
00153   * @brief  Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
00154   * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
00155   *         contains the configuration information for the specified AES Keys.
00156   * @note   This function must be called while the AES is disabled.
00157   * @note   In encryption, key derivation and key derivation + decryption modes,
00158   *         AES_KeyInitStruct must contain the encryption key.
00159   *         In decryption mode, AES_KeyInitStruct must contain the decryption key.
00160   * @retval None
00161   */
00162 void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
00163 {
00164   AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
00165   AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
00166   AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
00167   AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
00168 }
00169
00170 /**
00171   * @brief  Initializes the AES Initialization Vector IV according to
00172   *         the specified parameters in the AES_IVInitStruct.
00173   * @param  AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
00174   *         contains the configuration information for the specified AES IV.
00175   * @note   When ECB chaining mode is selected, Initialization Vector IV has no
00176   *         meaning.
00177   *         When CTR chaining mode is selected, AES_IV0 contains the CTR value.
00178   *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
00179   * @retval None
00180   */
00181 void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
00182 {
00183   AES->IVR0 = AES_IVInitStruct->AES_IV0;
00184   AES->IVR1 = AES_IVInitStruct->AES_IV1;
00185   AES->IVR2 = AES_IVInitStruct->AES_IV2;
00186   AES->IVR3 = AES_IVInitStruct->AES_IV3;
00187 }
00188
00189 /**
00190   * @brief  Enable or disable the AES peripheral.
00191   * @param  NewState: new state of the AES peripheral.
00192   *         This parameter can be: ENABLE or DISABLE.
00193   * @note   The key must be written while AES is disabled.
00194   * @retval None
00195   */
00196 void AES_Cmd(FunctionalState NewState)
00197 {
00198   /* Check the parameter */
00199   assert_param(IS_FUNCTIONAL_STATE(NewState));
00200
00201   if (NewState != DISABLE)
00202   {
00203     /* Enable the AES peripheral */
00204     AES->CR |= (uint32_t) AES_CR_EN;   /**< AES Enable */
00205   }
00206   else
00207   {
00208     /* Disable the AES peripheral */
00209     AES->CR &= (uint32_t)(~AES_CR_EN);  /**< AES Disable */
00210   }
00211 }
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup AES_Group2 Structures initialization functions
00218  *  @brief   Structures initialization.
00219  *
00220 @verbatim
00221  ===============================================================================
00222               ##### Structures initialization functions #####
00223  ===============================================================================
00224
00225 @endverbatim
00226   * @{
00227   */
00228
00229 /**
00230   * @brief  Fills each AES_InitStruct member with its default value.
00231   * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure which will
00232   *         be initialized.
00233   * @retval None
00234   */
00235 void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
00236 {
00237   AES_InitStruct->AES_Operation = AES_Operation_Encryp;
00238   AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
00239   AES_InitStruct->AES_DataType = AES_DataType_32b;
00240 }
00241
00242 /**
00243   * @brief  Fills each AES_KeyInitStruct member with its default value.
00244   * @param  AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which
00245   *         will be initialized.
00246   * @retval None
00247   */
00248 void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
00249 {
00250   AES_KeyInitStruct->AES_Key0 = 0x00000000;
00251   AES_KeyInitStruct->AES_Key1 = 0x00000000;
00252   AES_KeyInitStruct->AES_Key2 = 0x00000000;
00253   AES_KeyInitStruct->AES_Key3 = 0x00000000;
00254 }
00255
00256 /**
00257   * @brief  Fills each AES_IVInitStruct member with its default value.
00258   * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
00259   *         will be initialized.
00260   * @retval None
00261   */
00262 void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
00263 {
00264   AES_IVInitStruct->AES_IV0 = 0x00000000;
00265   AES_IVInitStruct->AES_IV1 = 0x00000000;
00266   AES_IVInitStruct->AES_IV2 = 0x00000000;
00267   AES_IVInitStruct->AES_IV3 = 0x00000000;
00268 }
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup AES_Group3 AES Read and Write
00275  *  @brief   AES Read and Write.
00276  *
00277 @verbatim
00278  ===============================================================================
00279                   ##### AES Read and Write functions #####
00280  ===============================================================================
00281
00282 @endverbatim
00283   * @{
00284   */
00285
00286 /**
00287   * @brief  Write data in DINR register to be processed by AES peripheral.
00288   * @note   To process 128-bit data (4 * 32-bit), this function must be called
00289   *         four times to write the 128-bit data in the 32-bit register DINR.
00290   * @note   When an unexpected write to DOUTR register is detected, WRERR flag is
00291   *         set.
00292   * @param  Data: The data to be processed.
00293   * @retval None
00294   */
00295 void AES_WriteSubData(uint32_t Data)
00296 {
00297   /* Write Data */
00298   AES->DINR = Data;
00299 }
00300
00301 /**
00302   * @brief  Returns the data in DOUTR register processed by AES peripheral.
00303   * @note   This function must be called four times to get the 128-bit data.
00304   * @note   When an unexpected read of DINR register is detected, RDERR flag is
00305   *         set.
00306   * @retval The processed data.
00307   */
00308 uint32_t AES_ReadSubData(void)
00309 {
00310   /* Read Data */
00311   return AES->DOUTR;
00312 }
00313
00314 /**
00315   * @brief  Read the Key value.
00316   * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
00317   *         will contain the key.
00318   * @note   When the key derivation mode is selected, AES must be disabled
00319   *         (AES_Cmd(DISABLE)) before reading the decryption key.
00320   *         Reading the key while the AES is enabled will return unpredictable
00321   *         value.
00322   * @retval None
00323   */
00324 void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
00325 {
00326   AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
00327   AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
00328   AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
00329   AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
00330 }
00331
00332 /**
00333   * @brief  Read the Initialization Vector IV value.
00334   * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
00335   *         will contain the Initialization Vector IV.
00336   * @note   When the AES is enabled Reading the Initialization Vector IV value
00337   *         will return 0. The AES must be disabled using AES_Cmd(DISABLE)
00338   *         to get the right value.
00339   * @note   When ECB chaining mode is selected, Initialization Vector IV has no
00340   *         meaning.
00341   *         When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
00342   *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
00343   * @retval None
00344   */
00345 void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
00346 {
00347   AES_IVInitStruct->AES_IV0 = AES->IVR0;
00348   AES_IVInitStruct->AES_IV1 = AES->IVR1;
00349   AES_IVInitStruct->AES_IV2 = AES->IVR2;
00350   AES_IVInitStruct->AES_IV3 = AES->IVR3;
00351 }
00352
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup AES_Group4 DMA transfers management functions
00358  *  @brief   DMA transfers management function.
00359  *
00360 @verbatim
00361  ===============================================================================
00362                ##### DMA transfers management functions #####
00363  ===============================================================================
00364
00365 @endverbatim
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Configures the AES DMA interface.
00371   * @param  AES_DMATransfer: Specifies the AES DMA transfer.
00372   *   This parameter can be one of the following values:
00373   *     @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
00374   *     @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
00375   *     @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
00376   * @param  NewState Indicates the new state of the AES DMA interface.
00377   *           This parameter can be: ENABLE or DISABLE.
00378   * @note   The DMA has no action in key derivation mode.
00379   * @retval None
00380   */
00381 void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
00382 {
00383   /* Check the parameter */
00384   assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));
00385
00386   if (NewState != DISABLE)
00387   {
00388     /* Enable the DMA transfer */
00389     AES->CR |= (uint32_t) AES_DMATransfer;
00390   }
00391   else
00392   {
00393     /* Disable the DMA transfer */
00394     AES->CR &= (uint32_t)(~AES_DMATransfer);
00395   }
00396 }
00397
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup AES_Group5 Interrupts and flags management functions
00403  *  @brief   Interrupts and flags management functions.
00404  *
00405 @verbatim
00406
00407  ===============================================================================
00408            ##### Interrupts and flags management functions #####
00409  ===============================================================================
00410 @endverbatim
00411   * @{
00412   */
00413
00414 /**
00415   * @brief  Enables or disables the specified AES interrupt.
00416   * @param  AES_IT: Specifies the AES interrupt source to enable/disable.
00417   *     This parameter can be any combinations of the following values:
00418   *     @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF
00419   *                     flag is set an interrupt is generated.
00420   *     @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
00421   *                      flags (RDERR) or write error flag (WRERR) is set,
00422   *                      an interrupt is generated.
00423   * @param  NewState: The new state of the AES interrupt source.
00424   *                   This parameter can be: ENABLE or DISABLE.
00425   * @retval None
00426   */
00427 void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_FUNCTIONAL_STATE(NewState));
00431   assert_param(IS_AES_IT(AES_IT));
00432
00433   if (NewState != DISABLE)
00434   {
00435     AES->CR |= (uint32_t) AES_IT;    /**< AES_IT Enable */
00436   }
00437   else
00438   {
00439     AES->CR &= (uint32_t)(~AES_IT);  /**< AES_IT Disable */
00440   }
00441 }
00442
00443 /**
00444   * @brief  Checks whether the specified AES flag is set or not.
00445   * @param  AES_FLAG specifies the flag to check.
00446   *   This parameter can be one of the following values:
00447   *     @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
00448   *                        he computation phase is completed.
00449   *     @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
00450   *                          operation of DOUTR register is detected.
00451   *     @arg AES_FLAG_WRERR: Write Error Flag  is set when an unexpected write
00452   *                          operation in DINR is detected.
00453   * @retval FlagStatus (SET or RESET)
00454   */
00455 FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
00456 {
00457   FlagStatus bitstatus = RESET;
00458
00459   /* Check parameters */
00460   assert_param(IS_AES_FLAG(AES_FLAG));
00461
00462   if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
00463   {
00464     bitstatus = SET;
00465   }
00466   else
00467   {
00468     bitstatus = RESET;
00469   }
00470
00471   /* Return the AES_FLAG status */
00472   return  bitstatus;
00473 }
00474
00475 /**
00476   * @brief  Clears the AES flags.
00477   * @param  AES_FLAG: specifies the flag to clear.
00478   *         This parameter can be:
00479   *     @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
00480   *                        bit in CR register.
00481   *     @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in
00482   *                          CR register.
00483   *     @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
00484   *                          CR register.
00485   * @retval None
00486   */
00487 void AES_ClearFlag(uint32_t AES_FLAG)
00488 {
00489   /* Check the parameters */
00490   assert_param(IS_AES_FLAG(AES_FLAG));
00491
00492   /* Check if AES_FLAG is AES_FLAG_CCF */
00493   if (AES_FLAG == AES_FLAG_CCF)
00494   {
00495     /* Clear CCF flag by setting CCFC bit */
00496     AES->CR |= (uint32_t) AES_CR_CCFC;
00497   }
00498   else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
00499   {
00500     /* Clear RDERR and WRERR flags by setting ERRC bit */
00501     AES->CR |= (uint32_t) AES_CR_ERRC;
00502   }
00503 }
00504
00505 /**
00506   * @brief  Checks whether the specified AES interrupt has occurred or not.
00507   * @param  AES_IT: Specifies the AES interrupt pending bit to check.
00508   *         This parameter can be:
00509   *     @arg AES_IT_CC: Computation Complete Interrupt.
00510   *     @arg AES_IT_ERR: Error Interrupt.
00511   * @retval ITStatus The new state of AES_IT (SET or RESET).
00512   */
00513 ITStatus AES_GetITStatus(uint32_t AES_IT)
00514 {
00515   ITStatus itstatus = RESET;
00516   uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;
00517
00518   /* Check parameters */
00519   assert_param(IS_AES_GET_IT(AES_IT));
00520
00521   cciebitstatus = AES->CR & AES_CR_CCIE;
00522   ccfbitstatus =  AES->SR & AES_SR_CCF;
00523
00524   /* Check if AES_IT is AES_IT_CC */
00525   if (AES_IT == AES_IT_CC)
00526   {
00527     /* Check the status of the specified AES interrupt */
00528     if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
00529     {
00530       /* Interrupt occurred */
00531       itstatus = SET;
00532     }
00533     else
00534     {
00535       /* Interrupt didn't occur */
00536       itstatus = RESET;
00537     }
00538   }
00539   else /* AES_IT is AES_IT_ERR */
00540   {
00541     /* Check the status of the specified AES interrupt */
00542     if ((AES->CR & AES_CR_ERRIE) != RESET)
00543     {
00544       /* Check if WRERR or RDERR flags are set */
00545       if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
00546       {
00547         /* Interrupt occurred */
00548         itstatus = SET;
00549       }
00550       else
00551       {
00552         /* Interrupt didn't occur */
00553         itstatus = RESET;
00554       }
00555     }
00556     else
00557     {
00558       /* Interrupt didn't occur */
00559       itstatus = (ITStatus) RESET;
00560     }
00561   }
00562
00563   /* Return the AES_IT status */
00564   return itstatus;
00565 }
00566
00567 /**
00568   * @brief  Clears the AES's interrupt pending bits.
00569   * @param  AES_IT: specifies the interrupt pending bit to clear.
00570   *   This parameter can be any combinations of the following values:
00571   *     @arg AES_IT_CC: Computation Complete Interrupt.
00572   *     @arg AES_IT_ERR: Error Interrupt.
00573   * @retval None
00574   */
00575 void AES_ClearITPendingBit(uint32_t AES_IT)
00576 {
00577   /* Check the parameters */
00578   assert_param(IS_AES_IT(AES_IT));
00579
00580   /* Clear the interrupt pending bit */
00581   AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
00582 }
00583
00584 /**
00585   * @}
00586   */
00587
00588 /**
00589   * @}
00590   */
00591
00592 /**
00593   * @}
00594   */
00595
00596 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes.h Source File

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stm32l1xx_aes.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_aes.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the AES firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_AES_H
00028 #define __STM32L1xx_AES_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup AES
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief   AES Init structure definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
00053                                This parameter can be a value of @ref AES_possible_Operation_modes */
00054   uint32_t AES_Chaining;  /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
00055                                This parameter can be a value of @ref AES_possible_chaining_modes */
00056   uint32_t AES_DataType;  /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
00057                                This parameter can be a value of @ref AES_Data_Types */
00058 }AES_InitTypeDef;
00059
00060 /**
00061   * @brief   AES Key(s) structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t AES_Key0;  /*!< Key[31:0]   */
00066   uint32_t AES_Key1;  /*!< Key[63:32]  */
00067   uint32_t AES_Key2;  /*!< Key[95:64]  */
00068   uint32_t AES_Key3;  /*!< Key[127:96] */
00069 }AES_KeyInitTypeDef;
00070
00071 /**
00072   * @brief   AES Initialization Vectors (IV) structure definition
00073   */
00074 typedef struct
00075 {
00076   uint32_t AES_IV0;  /*!< Init Vector IV[31:0]   */
00077   uint32_t AES_IV1;  /*!< Init Vector IV[63:32]  */
00078   uint32_t AES_IV2;  /*!< Init Vector IV[95:64]  */
00079   uint32_t AES_IV3;  /*!< Init Vector IV[127:96] */
00080 }AES_IVInitTypeDef;
00081
00082 /* Exported constants --------------------------------------------------------*/
00083
00084 /** @defgroup AES_Exported_Constants
00085   * @{
00086   */
00087
00088 /** @defgroup AES_possible_Operation_modes
00089   * @{
00090   */
00091 #define AES_Operation_Encryp               ((uint32_t)0x00000000) /*!< AES in Encryption mode */
00092 #define AES_Operation_KeyDeriv             AES_CR_MODE_0          /*!< AES in Key Derivation mode */
00093 #define AES_Operation_Decryp               AES_CR_MODE_1          /*!< AES in Decryption mode */
00094 #define AES_Operation_KeyDerivAndDecryp    AES_CR_MODE            /*!< AES in Key Derivation and Decryption mode */
00095
00096 #define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp)    || \
00097                                 ((OPERATION) == AES_Operation_KeyDeriv)  || \
00098                                 ((OPERATION) == AES_Operation_Decryp)    || \
00099                                 ((OPERATION) == AES_Operation_KeyDerivAndDecryp))
00100
00101 /**
00102   * @}
00103   */
00104
00105 /** @defgroup AES_possible_chaining_modes
00106   * @{
00107   */
00108 #define AES_Chaining_ECB                   ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
00109 #define AES_Chaining_CBC                   AES_CR_CHMOD_0         /*!< AES in CBC chaining mode */
00110 #define AES_Chaining_CTR                   AES_CR_CHMOD_1         /*!< AES in CTR chaining mode */
00111
00112 #define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
00113                                    ((CHAINING) == AES_Chaining_CBC) || \
00114                                    ((CHAINING) == AES_Chaining_CTR))
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup AES_Data_Types
00120   * @{
00121   */
00122 #define AES_DataType_32b                   ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
00123 #define AES_DataType_16b                   AES_CR_DATATYPE_0      /*!< 16-bit data. Each half word is swapped */
00124 #define AES_DataType_8b                    AES_CR_DATATYPE_1      /*!< 8-bit data. All bytes are swapped */
00125 #define AES_DataType_1b                    AES_CR_DATATYPE        /*!< 1-bit data. In the word all bits are swapped */
00126
00127 #define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
00128                                     ((DATATYPE) == AES_DataType_16b)|| \
00129                                     ((DATATYPE) == AES_DataType_8b) || \
00130                                     ((DATATYPE) == AES_DataType_1b))
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup AES_Flags
00136   * @{
00137   */
00138 #define AES_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
00139 #define AES_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
00140 #define AES_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
00141
00142 #define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF)    || \
00143                            ((FLAG) == AES_FLAG_RDERR)  || \
00144                            ((FLAG) == AES_FLAG_WRERR))
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup AES_Interrupts
00150   * @{
00151   */
00152 #define AES_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
00153 #define AES_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
00154
00155 #define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
00156 #define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
00157
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup AES_DMA_Transfer_modes
00163   * @{
00164   */
00165 #define AES_DMATransfer_In                 AES_CR_DMAINEN                     /*!< DMA requests enabled for input transfer phase */
00166 #define AES_DMATransfer_Out                AES_CR_DMAOUTEN                    /*!< DMA requests enabled for input transfer phase */
00167 #define AES_DMATransfer_InOut              (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
00168
00169 #define IS_AES_DMA_TRANSFER(TRANSFER)   (((TRANSFER) == AES_DMATransfer_In)  || \
00170                                          ((TRANSFER) == AES_DMATransfer_Out)  || \
00171                                          ((TRANSFER) == AES_DMATransfer_InOut))
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported macro ------------------------------------------------------------*/
00181 /* Exported functions ------------------------------------------------------- */
00182
00183 /* Initialization and configuration functions *********************************/
00184 void AES_DeInit(void);
00185 void AES_Init(AES_InitTypeDef* AES_InitStruct);
00186 void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
00187 void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
00188 void AES_Cmd(FunctionalState NewState);
00189
00190 /* Structures initialization functions ****************************************/
00191 void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
00192 void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
00193 void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
00194
00195 /* AES Read and Write functions **********************************************/
00196 void AES_WriteSubData(uint32_t Data);
00197 uint32_t AES_ReadSubData(void);
00198 void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
00199 void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
00200
00201 /* DMA transfers management function ******************************************/
00202 void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
00203
00204 /* Interrupts and flags management functions **********************************/
00205 void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
00206 FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
00207 void AES_ClearFlag(uint32_t AES_FLAG);
00208 ITStatus AES_GetITStatus(uint32_t AES_IT);
00209 void AES_ClearITPendingBit(uint32_t AES_IT);
00210
00211 /* High Level AES functions **************************************************/
00212 ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00213 ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00214 ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00215 ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00216 ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00217 ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
00218
00219 #ifdef __cplusplus
00220 }
00221 #endif
00222
00223 #endif /*__STM32L1xx_AES_H */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_aes_util.c Source File

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stm32l1xx_aes_util.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_aes_util.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides high level functions to encrypt and decrypt an
00008   *          input message using AES in ECB/CBC/CTR modes.
00009   *
00010   *  @verbatim
00011
00012 ================================================================================
00013                         ##### How to use this driver #####
00014 ================================================================================
00015           [..]
00016            (#) Enable The AES controller clock using
00017                RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.
00018
00019            (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
00020            (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.
00021
00022            (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
00023            (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.
00024
00025            (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
00026            (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.
00027
00028   *  @endverbatim
00029   *
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00034   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00035   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00036   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00037   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00038   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00039   *
00040   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00041   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00042   *
00043   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00044   ******************************************************************************
00045   */
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32l1xx_aes.h"
00049
00050 /** @addtogroup STM32L1xx_StdPeriph_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup AES
00055   * @brief AES driver modules
00056   * @{
00057   */
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 #define AES_CC_TIMEOUT    ((uint32_t) 0x00010000)
00062
00063 /* Private macro -------------------------------------------------------------*/
00064 /* Private variables ---------------------------------------------------------*/
00065 /* Private function prototypes -----------------------------------------------*/
00066 /* Private functions ---------------------------------------------------------*/
00067
00068 /** @defgroup AES_Private_Functions
00069   * @{
00070   */
00071
00072 /** @defgroup AES_Group6 High Level AES functions
00073  *  @brief   High Level AES functions
00074  *
00075 @verbatim
00076 ================================================================================
00077                          ##### High Level AES functions #####
00078 ================================================================================
00079
00080 @endverbatim
00081   * @{
00082   */
00083
00084 /**
00085   * @brief  Encrypt using AES in ECB Mode
00086   * @param  Key: Key used for AES algorithm.
00087   * @param  Input: pointer to the Input buffer.
00088   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00089   * @param  Output: pointer to the returned buffer.
00090   * @retval An ErrorStatus enumeration value:
00091   *          - SUCCESS: Operation done
00092   *          - ERROR: Operation failed
00093   */
00094 ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00095 {
00096   AES_InitTypeDef AES_InitStructure;
00097   AES_KeyInitTypeDef  AES_KeyInitStructure;
00098   ErrorStatus status = SUCCESS;
00099   uint32_t keyaddr    = (uint32_t)Key;
00100   uint32_t inputaddr  = (uint32_t)Input;
00101   uint32_t outputaddr = (uint32_t)Output;
00102   __IO uint32_t counter = 0;
00103   uint32_t ccstatus = 0;
00104   uint32_t i = 0;
00105
00106   /* AES Key initialisation */
00107   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00108   keyaddr += 4;
00109   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00110   keyaddr += 4;
00111   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00112   keyaddr += 4;
00113   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00114   AES_KeyInit(&AES_KeyInitStructure);
00115
00116   /* AES configuration */
00117   AES_InitStructure.AES_Operation = AES_Operation_Encryp;
00118   AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
00119   AES_InitStructure.AES_DataType = AES_DataType_8b;
00120   AES_Init(&AES_InitStructure);
00121
00122   /* Enable AES */
00123   AES_Cmd(ENABLE);
00124
00125   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00126   {
00127     AES_WriteSubData(*(uint32_t*)(inputaddr));
00128     inputaddr += 4;
00129     AES_WriteSubData(*(uint32_t*)(inputaddr));
00130     inputaddr += 4;
00131     AES_WriteSubData(*(uint32_t*)(inputaddr));
00132     inputaddr += 4;
00133     AES_WriteSubData(*(uint32_t*)(inputaddr));
00134     inputaddr += 4;
00135
00136     /* Wait for CCF flag to be set */
00137     counter = 0;
00138     do
00139     {
00140       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00141       counter++;
00142     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00143
00144     if (ccstatus == RESET)
00145     {
00146       status = ERROR;
00147     }
00148     else
00149     {
00150       /* Clear CCF flag */
00151       AES_ClearFlag(AES_FLAG_CCF);
00152       /* Read cipher text */
00153       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00154       outputaddr += 4;
00155       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00156       outputaddr += 4;
00157       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00158       outputaddr += 4;
00159       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00160       outputaddr += 4;
00161     }
00162   }
00163
00164   /* Disable AES before starting new processing */
00165   AES_Cmd(DISABLE);
00166
00167   return status;
00168 }
00169
00170 /**
00171   * @brief  Decrypt using AES in ECB Mode
00172   * @param  Key: Key used for AES algorithm.
00173   * @param  Input: pointer to the Input buffer.
00174   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00175   * @param  Output: pointer to the returned buffer.
00176   * @retval An ErrorStatus enumeration value:
00177   *          - SUCCESS: Operation done
00178   *          - ERROR: Operation failed
00179   */
00180 ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00181 {
00182   AES_InitTypeDef AES_InitStructure;
00183   AES_KeyInitTypeDef  AES_KeyInitStructure;
00184   ErrorStatus status = SUCCESS;
00185   uint32_t keyaddr    = (uint32_t)Key;
00186   uint32_t inputaddr  = (uint32_t)Input;
00187   uint32_t outputaddr = (uint32_t)Output;
00188   __IO uint32_t counter = 0;
00189   uint32_t ccstatus = 0;
00190   uint32_t i = 0;
00191
00192   /* AES Key initialisation */
00193   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00194   keyaddr += 4;
00195   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00196   keyaddr += 4;
00197   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00198   keyaddr += 4;
00199   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00200   AES_KeyInit(&AES_KeyInitStructure);
00201
00202   /* AES configuration */
00203   AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
00204   AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
00205   AES_InitStructure.AES_DataType = AES_DataType_8b;
00206   AES_Init(&AES_InitStructure);
00207
00208   /* Enable AES */
00209   AES_Cmd(ENABLE);
00210
00211   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00212   {
00213     AES_WriteSubData(*(uint32_t*)(inputaddr));
00214     inputaddr += 4;
00215     AES_WriteSubData(*(uint32_t*)(inputaddr));
00216     inputaddr += 4;
00217     AES_WriteSubData(*(uint32_t*)(inputaddr));
00218     inputaddr += 4;
00219     AES_WriteSubData(*(uint32_t*)(inputaddr));
00220     inputaddr += 4;
00221
00222      /* Wait for CCF flag to be set */
00223     counter = 0;
00224     do
00225     {
00226       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00227       counter++;
00228     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00229
00230     if (ccstatus == RESET)
00231     {
00232       status = ERROR;
00233     }
00234     else
00235     {
00236       /* Clear CCF flag */
00237       AES_ClearFlag(AES_FLAG_CCF);
00238
00239       /* Read cipher text */
00240       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00241       outputaddr += 4;
00242       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00243       outputaddr += 4;
00244       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00245       outputaddr += 4;
00246       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00247       outputaddr += 4;
00248     }
00249   }
00250
00251   /* Disable AES before starting new processing */
00252   AES_Cmd(DISABLE);
00253
00254   return status;
00255 }
00256
00257 /**
00258   * @brief  Encrypt using AES in CBC Mode
00259   * @param  InitVectors: Initialisation Vectors used for AES algorithm.
00260   * @param  Key: Key used for AES algorithm.
00261   * @param  Input: pointer to the Input buffer.
00262   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00263   * @param  Output: pointer to the returned buffer.
00264   * @retval An ErrorStatus enumeration value:
00265   *          - SUCCESS: Operation done
00266   *          - ERROR: Operation failed
00267   */
00268 ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00269 {
00270   AES_InitTypeDef AES_InitStructure;
00271   AES_KeyInitTypeDef  AES_KeyInitStructure;
00272   AES_IVInitTypeDef AES_IVInitStructure;
00273   ErrorStatus status = SUCCESS;
00274   uint32_t keyaddr    = (uint32_t)Key;
00275   uint32_t inputaddr  = (uint32_t)Input;
00276   uint32_t outputaddr = (uint32_t)Output;
00277   uint32_t ivaddr     = (uint32_t)InitVectors;
00278   __IO uint32_t counter = 0;
00279   uint32_t ccstatus = 0;
00280   uint32_t i = 0;
00281
00282   /* AES Key initialisation*/
00283   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00284   keyaddr += 4;
00285   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00286   keyaddr += 4;
00287   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00288   keyaddr += 4;
00289   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00290   AES_KeyInit(&AES_KeyInitStructure);
00291
00292   /* AES Initialization Vectors */
00293   AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
00294   ivaddr += 4;
00295   AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
00296   ivaddr += 4;
00297   AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
00298   ivaddr += 4;
00299   AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
00300   AES_IVInit(&AES_IVInitStructure);
00301
00302   /* AES configuration */
00303   AES_InitStructure.AES_Operation = AES_Operation_Encryp;
00304   AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
00305   AES_InitStructure.AES_DataType = AES_DataType_8b;
00306   AES_Init(&AES_InitStructure);
00307
00308   /* Enable AES */
00309   AES_Cmd(ENABLE);
00310
00311   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00312   {
00313     AES_WriteSubData(*(uint32_t*)(inputaddr));
00314     inputaddr += 4;
00315     AES_WriteSubData(*(uint32_t*)(inputaddr));
00316     inputaddr += 4;
00317     AES_WriteSubData(*(uint32_t*)(inputaddr));
00318     inputaddr += 4;
00319     AES_WriteSubData(*(uint32_t*)(inputaddr));
00320     inputaddr += 4;
00321
00322     /* Wait for CCF flag to be set */
00323     counter = 0;
00324     do
00325     {
00326       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00327       counter++;
00328     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00329
00330     if (ccstatus == RESET)
00331     {
00332       status = ERROR;
00333     }
00334     else
00335     {
00336       /* Clear CCF flag */
00337       AES_ClearFlag(AES_FLAG_CCF);
00338
00339       /* Read cipher text */
00340       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00341       outputaddr += 4;
00342       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00343       outputaddr += 4;
00344       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00345       outputaddr += 4;
00346       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00347       outputaddr += 4;
00348     }
00349   }
00350
00351   /* Disable AES before starting new processing */
00352   AES_Cmd(DISABLE);
00353
00354   return status;
00355 }
00356
00357 /**
00358   * @brief  Decrypt using AES in CBC Mode
00359   * @param  InitVectors: Initialisation Vectors used for AES algorithm.
00360   * @param  Key: Key used for AES algorithm.
00361   * @param  Input: pointer to the Input buffer.
00362   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00363   * @param  Output: pointer to the returned buffer.
00364   * @retval An ErrorStatus enumeration value:
00365   *          - SUCCESS: Operation done
00366   *          - ERROR: Operation failed
00367   */
00368 ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00369 {
00370   AES_InitTypeDef AES_InitStructure;
00371   AES_KeyInitTypeDef  AES_KeyInitStructure;
00372   AES_IVInitTypeDef AES_IVInitStructure;
00373   ErrorStatus status = SUCCESS;
00374   uint32_t keyaddr    = (uint32_t)Key;
00375   uint32_t inputaddr  = (uint32_t)Input;
00376   uint32_t outputaddr = (uint32_t)Output;
00377   uint32_t ivaddr     = (uint32_t)InitVectors;
00378   __IO uint32_t counter = 0;
00379   uint32_t ccstatus = 0;
00380   uint32_t i = 0;
00381
00382   /* AES Key initialisation*/
00383   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00384   keyaddr += 4;
00385   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00386   keyaddr += 4;
00387   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00388   keyaddr += 4;
00389   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00390   AES_KeyInit(&AES_KeyInitStructure);
00391
00392   /* AES Initialization Vectors */
00393   AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
00394   ivaddr += 4;
00395   AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
00396   ivaddr += 4;
00397   AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
00398   ivaddr += 4;
00399   AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
00400   AES_IVInit(&AES_IVInitStructure);
00401
00402   /* AES configuration */
00403   AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
00404   AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
00405   AES_InitStructure.AES_DataType = AES_DataType_8b;
00406   AES_Init(&AES_InitStructure);
00407
00408   /* Enable AES */
00409   AES_Cmd(ENABLE);
00410
00411   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00412   {
00413     AES_WriteSubData(*(uint32_t*)(inputaddr));
00414     inputaddr += 4;
00415     AES_WriteSubData(*(uint32_t*)(inputaddr));
00416     inputaddr += 4;
00417     AES_WriteSubData(*(uint32_t*)(inputaddr));
00418     inputaddr += 4;
00419     AES_WriteSubData(*(uint32_t*)(inputaddr));
00420     inputaddr += 4;
00421
00422     /* Wait for CCF flag to be set */
00423     counter = 0;
00424     do
00425     {
00426       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00427       counter++;
00428     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00429
00430     if (ccstatus == RESET)
00431     {
00432       status = ERROR;
00433     }
00434     else
00435     {
00436       /* Clear CCF flag */
00437       AES_ClearFlag(AES_FLAG_CCF);
00438
00439       /* Read cipher text */
00440       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00441       outputaddr += 4;
00442       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00443       outputaddr += 4;
00444       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00445       outputaddr += 4;
00446       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00447       outputaddr += 4;
00448     }
00449   }
00450
00451   /* Disable AES before starting new processing */
00452   AES_Cmd(DISABLE);
00453
00454   return status;
00455 }
00456
00457 /**
00458   * @brief  Encrypt using AES in CTR Mode
00459   * @param  InitVectors: Initialisation Vectors used for AES algorithm.
00460   * @param  Key: Key used for AES algorithm.
00461   * @param  Input: pointer to the Input buffer.
00462   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00463   * @param  Output: pointer to the returned buffer.
00464   * @retval An ErrorStatus enumeration value:
00465   *          - SUCCESS: Operation done
00466   *          - ERROR: Operation failed
00467   */
00468 ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00469 {
00470   AES_InitTypeDef AES_InitStructure;
00471   AES_KeyInitTypeDef  AES_KeyInitStructure;
00472   AES_IVInitTypeDef AES_IVInitStructure;
00473
00474   ErrorStatus status = SUCCESS;
00475   uint32_t keyaddr    = (uint32_t)Key;
00476   uint32_t inputaddr  = (uint32_t)Input;
00477   uint32_t outputaddr = (uint32_t)Output;
00478   uint32_t ivaddr     = (uint32_t)InitVectors;
00479   __IO uint32_t counter = 0;
00480   uint32_t ccstatus = 0;
00481   uint32_t i = 0;
00482
00483   /* AES key initialisation*/
00484   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00485   keyaddr += 4;
00486   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00487   keyaddr += 4;
00488   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00489   keyaddr += 4;
00490   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00491   AES_KeyInit(&AES_KeyInitStructure);
00492
00493   /* AES Initialization Vectors */
00494   AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
00495   ivaddr += 4;
00496   AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));
00497   ivaddr += 4;
00498   AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
00499   ivaddr += 4;
00500   AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));
00501   AES_IVInit(&AES_IVInitStructure);
00502
00503   /* AES configuration */
00504   AES_InitStructure.AES_Operation = AES_Operation_Encryp;
00505   AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
00506   AES_InitStructure.AES_DataType = AES_DataType_8b;
00507   AES_Init(&AES_InitStructure);
00508
00509   /* Enable AES */
00510   AES_Cmd(ENABLE);
00511
00512   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00513   {
00514     AES_WriteSubData(*(uint32_t*)(inputaddr));
00515     inputaddr += 4;
00516     AES_WriteSubData(*(uint32_t*)(inputaddr));
00517     inputaddr += 4;
00518     AES_WriteSubData(*(uint32_t*)(inputaddr));
00519     inputaddr += 4;
00520     AES_WriteSubData(*(uint32_t*)(inputaddr));
00521     inputaddr += 4;
00522
00523     /* Wait for CCF flag to be set */
00524     counter = 0;
00525     do
00526     {
00527       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00528       counter++;
00529     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00530
00531     if (ccstatus == RESET)
00532     {
00533       status = ERROR;
00534     }
00535     else
00536     {
00537       /* Clear CCF flag */
00538       AES_ClearFlag(AES_FLAG_CCF);
00539
00540       /* Read cipher text */
00541       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00542       outputaddr += 4;
00543       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00544       outputaddr += 4;
00545       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00546       outputaddr += 4;
00547       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00548       outputaddr += 4;
00549     }
00550   }
00551
00552   /* Disable AES before starting new processing */
00553   AES_Cmd(DISABLE);
00554
00555   return status;
00556 }
00557
00558 /**
00559   * @brief  Decrypt using AES in CTR Mode
00560   * @param  InitVectors: Initialisation Vectors used for AES algorithm.
00561   * @param  Key: Key used for AES algorithm.
00562   * @param  Input: pointer to the Input buffer.
00563   * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
00564   * @param  Output: pointer to the returned buffer.
00565   * @retval An ErrorStatus enumeration value:
00566   *          - SUCCESS: Operation done
00567   *          - ERROR: Operation failed
00568   */
00569 ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
00570 {
00571   AES_InitTypeDef AES_InitStructure;
00572   AES_KeyInitTypeDef  AES_KeyInitStructure;
00573   AES_IVInitTypeDef AES_IVInitStructure;
00574
00575   ErrorStatus status = SUCCESS;
00576   uint32_t keyaddr    = (uint32_t)Key;
00577   uint32_t inputaddr  = (uint32_t)Input;
00578   uint32_t outputaddr = (uint32_t)Output;
00579   uint32_t ivaddr     = (uint32_t)InitVectors;
00580   __IO uint32_t counter = 0;
00581   uint32_t ccstatus = 0;
00582   uint32_t i = 0;
00583
00584   /* AES Key initialisation*/
00585   AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
00586   keyaddr += 4;
00587   AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
00588   keyaddr += 4;
00589   AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
00590   keyaddr += 4;
00591   AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
00592   AES_KeyInit(&AES_KeyInitStructure);
00593
00594   /* AES Initialization Vectors */
00595   AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
00596   ivaddr += 4;
00597   AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
00598   ivaddr += 4;
00599   AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
00600   ivaddr += 4;
00601   AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
00602   AES_IVInit(&AES_IVInitStructure);
00603
00604   /* AES configuration */
00605   AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
00606   AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
00607   AES_InitStructure.AES_DataType = AES_DataType_8b;
00608   AES_Init(&AES_InitStructure);
00609
00610   /* Enable AES */
00611   AES_Cmd(ENABLE);
00612
00613   for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
00614   {
00615     AES_WriteSubData(*(uint32_t*)(inputaddr));
00616     inputaddr += 4;
00617     AES_WriteSubData(*(uint32_t*)(inputaddr));
00618     inputaddr += 4;
00619     AES_WriteSubData(*(uint32_t*)(inputaddr));
00620     inputaddr += 4;
00621     AES_WriteSubData(*(uint32_t*)(inputaddr));
00622     inputaddr += 4;
00623
00624     /* Wait for CCF flag to be set */
00625     counter = 0;
00626     do
00627     {
00628       ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
00629       counter++;
00630     }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
00631
00632     if (ccstatus == RESET)
00633     {
00634       status = ERROR;
00635     }
00636     else
00637     {
00638       /* Clear CCF flag */
00639       AES_ClearFlag(AES_FLAG_CCF);
00640
00641       /* Read cipher text */
00642       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00643       outputaddr += 4;
00644       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00645       outputaddr += 4;
00646       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00647       outputaddr += 4;
00648       *(uint32_t*)(outputaddr) = AES_ReadSubData();
00649       outputaddr += 4;
00650     }
00651   }
00652
00653   /* Disable AES before starting new processing */
00654   AES_Cmd(DISABLE);
00655
00656   return status;
00657 }
00658
00659 /**
00660   * @}
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 /**
00668   * @}
00669   */
00670
00671 /**
00672   * @}
00673   */
00674
00675 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
00676


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_comp.c Source File

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stm32l1xx_comp.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_comp.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the comparators (COMP1 and COMP2) peripheral:
00009   *           + Comparators configuration
00010   *           + Window mode control
00011   *           + Internal Reference Voltage (VREFINT) output
00012   *
00013   *  @verbatim
00014  ===============================================================================
00015                      ##### How to use this driver #####
00016  ===============================================================================
00017     [..] The device integrates two analog comparators COMP1 and COMP2:
00018          (+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting
00019              input with the ADC channels.
00020          (+) COMP2 is a rail-to-rail comparator whose the inverting input can be
00021              selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4
00022              VREFINT, VREFINT, PB3 and whose the output can be redirected to
00023              embedded timers: TIM2, TIM3, TIM4, TIM10.
00024
00025          (+) The two comparators COMP1 and COMP2 can be combined in window mode.
00026
00027          -@-
00028             (#@) Comparator APB clock must be enabled to get write access
00029                  to comparator register using
00030                  RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
00031
00032             (#@) COMP1 comparator and ADC can't be used at the same time since
00033                  they share the same ADC switch matrix (analog switches).
00034
00035             (#@) When an I/O is used as comparator input, the corresponding GPIO
00036                  registers should be configured in analog mode.
00037
00038             (#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
00039                  GPIO pin. They are only internal.
00040                  To get the comparator output level, use COMP_GetOutputLevel().
00041
00042             (#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21
00043                  and EXTI Line 22 respectively.
00044                  Interrupts can be used by configuring the EXTI Line using the
00045                  EXTI peripheral driver.
00046
00047             (#@) After enabling the comparator (COMP1 or COMP2), user should wait
00048                  for start-up time (tSTART) to get right output levels.
00049                  Please refer to product datasheet for more information on tSTART.
00050
00051             (#@) Comparators cannot be used to exit the device from Sleep or Stop
00052                  mode when the internal reference voltage is switched off using
00053                  the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).
00054
00055     @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00060   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00061   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00062   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00063   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00064   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00065   *
00066   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00067   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00068   *
00069   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00070   ******************************************************************************
00071   */
00072
00073 /* Includes ------------------------------------------------------------------*/
00074 #include "stm32l1xx_comp.h"
00075
00076 /** @addtogroup STM32L1xx_StdPeriph_Driver
00077   * @{
00078   */
00079
00080 /** @defgroup COMP
00081   * @brief COMP driver modules.
00082   * @{
00083   */
00084
00085 /* Private typedef -----------------------------------------------------------*/
00086 /* Private define ------------------------------------------------------------*/
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /* Private function prototypes -----------------------------------------------*/
00090 /* Private functions ---------------------------------------------------------*/
00091
00092 /** @defgroup COMP_Private_Functions
00093   * @{
00094   */
00095
00096 /** @defgroup COMP_Group1 Initialization and Configuration functions
00097  *  @brief   Initialization and Configuration functions.
00098  *
00099 @verbatim
00100  ===============================================================================
00101               ##### Initialization and Configuration functions #####
00102  ===============================================================================
00103
00104 @endverbatim
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  Deinitializes COMP peripheral registers to their default reset values.
00110   * @param  None
00111   * @retval None
00112   */
00113 void COMP_DeInit(void)
00114 {
00115   COMP->CSR = ((uint32_t)0x00000000);    /*!< Set COMP->CSR to reset value */
00116 }
00117
00118 /**
00119   * @brief  Initializes the COMP2 peripheral according to the specified parameters
00120   *         in the COMP_InitStruct.
00121   * @note   This function configures only COMP2.
00122   * @note   COMP2 comparator is enabled as soon as the INSEL[2:0] bits are
00123   *         different from "000".
00124   * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
00125   *         the configuration information for the specified COMP peripheral.
00126   * @retval None
00127   */
00128 void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)
00129 {
00130   uint32_t tmpreg = 0;
00131
00132   /* Check the parameters */
00133   assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
00134   assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));
00135   assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));
00136
00137   /*!< Get the COMP CSR value */
00138   tmpreg = COMP->CSR;
00139
00140   /*!< Clear the  INSEL[2:0], OUTSEL[1:0] and SPEED bits */
00141   tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));
00142
00143   /*!< Configure COMP: speed, inversion input selection and output redirection */
00144   /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */
00145   /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
00146   /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */
00147   tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput
00148                         | COMP_InitStruct->COMP_OutputSelect));
00149
00150   /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are
00151      different from "000" */
00152   /*!< Write to COMP_CSR register */
00153   COMP->CSR = tmpreg;
00154 }
00155
00156 /**
00157   * @brief  Enable or disable the COMP1 peripheral.
00158   * @note   After enabling COMP1, the following functions should be called to
00159   *         connect the selected GPIO input to COMP1 non inverting input:
00160   * @note   Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
00161   * @note   Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
00162   * @note   Close the I/O switch number n corresponding to the I/O
00163   *         using SYSCFG_RIIOSwitchConfig()
00164   * @param  NewState: new state of the COMP1 peripheral.
00165   *         This parameter can be: ENABLE or DISABLE.
00166   * @note   This function enables/disables only the COMP1.
00167   * @retval None
00168   */
00169 void COMP_Cmd(FunctionalState NewState)
00170 {
00171   /* Check the parameter */
00172   assert_param(IS_FUNCTIONAL_STATE(NewState));
00173
00174   if (NewState != DISABLE)
00175   {
00176     /* Enable the COMP1 */
00177     COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;
00178   }
00179   else
00180   {
00181     /* Disable the COMP1  */
00182     COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);
00183   }
00184 }
00185
00186 /**
00187   * @brief  Return the output level (high or low) of the selected comparator.
00188   * @note   Comparator output is low when the noninverting input is at a lower
00189   *         voltage than the inverting input.
00190   * @note   Comparator output is high when the noninverting input is at a higher
00191   *         voltage than the inverting input.
00192   * @note   Comparators outputs aren't available on GPIO (outputs levels are
00193   *         only internal). The COMP1 and COMP2 outputs are connected internally
00194   *         to the EXTI Line 21 and Line 22 respectively.
00195   * @param  COMP_Selection: the selected comparator.
00196   *   This parameter can be one of the following values:
00197   *     @arg COMP_Selection_COMP1: COMP1 selected
00198   *     @arg COMP_Selection_COMP2: COMP2 selected
00199   * @retval Returns the selected comparator output level.
00200   */
00201 uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)
00202 {
00203   uint8_t compout = 0x0;
00204
00205   /* Check the parameters */
00206   assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
00207
00208   /* Check if Comparator 1 is selected */
00209   if(COMP_Selection == COMP_Selection_COMP1)
00210   {
00211     /* Check if comparator 1 output level is high */
00212     if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)
00213     {
00214       /* Get Comparator 1 output level */
00215       compout = (uint8_t) COMP_OutputLevel_High;
00216     }
00217     /* comparator 1 output level is low */
00218     else
00219     {
00220       /* Get Comparator 1 output level */
00221       compout = (uint8_t) COMP_OutputLevel_Low;
00222     }
00223   }
00224   /* Comparator 2 is selected */
00225   else
00226   {
00227     /* Check if comparator 2 output level is high */
00228     if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)
00229     {
00230       /* Get Comparator output level */
00231       compout = (uint8_t) COMP_OutputLevel_High;
00232     }
00233     /* comparator 2 output level is low */
00234     else
00235     {
00236       /* Get Comparator 2 output level */
00237       compout = (uint8_t) COMP_OutputLevel_Low;
00238     }
00239   }
00240   /* Return the comparator output level */
00241   return (uint8_t)(compout);
00242 }
00243
00244 /**
00245   * @brief  Close or Open the SW1 switch.
00246   * @param  NewState: new state of the SW1 switch.
00247   *         This parameter can be: ENABLE or DISABLE.
00248   * @note   ENABLE to close the SW1 switch
00249   * @note   DISABLE to open the SW1 switch
00250   * @retval None.
00251   */
00252 void COMP_SW1SwitchConfig(FunctionalState NewState)
00253 {
00254   /* Check the parameters */
00255   assert_param(IS_FUNCTIONAL_STATE(NewState));
00256
00257   if (NewState != DISABLE)
00258   {
00259     /* Close SW1 switch */
00260     COMP->CSR |= (uint32_t) COMP_CSR_SW1;
00261   }
00262   else
00263   {
00264     /* Open SW1 switch */
00265     COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);
00266   }
00267 }
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup COMP_Group2 Window mode control function
00274  *  @brief   Window mode control function.
00275  *
00276 @verbatim
00277  ===============================================================================
00278                   ##### Window mode control function #####
00279  ===============================================================================
00280
00281 @endverbatim
00282   * @{
00283   */
00284
00285 /**
00286   * @brief  Enables or disables the window mode.
00287   *         In window mode:
00288   * @note   COMP1 inverting input is fixed to VREFINT defining the first
00289   *         threshold.
00290   * @note   COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT
00291   *         sub-multiples, PB3) defining the second threshold.
00292   * @note   COMP1 and COMP2 non inverting inputs are connected together.
00293   * @note   In window mode, only the Group 6 (PB4 or PB5) can be used as
00294   *         noninverting inputs.
00295   * @param   NewState: new state of the window mode.
00296   *   This parameter can be ENABLE or DISABLE.
00297   * @retval None
00298   */
00299 void COMP_WindowCmd(FunctionalState NewState)
00300 {
00301   /* Check the parameters */
00302   assert_param(IS_FUNCTIONAL_STATE(NewState));
00303
00304   if (NewState != DISABLE)
00305   {
00306     /* Enable the window mode */
00307     COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;
00308   }
00309   else
00310   {
00311     /* Disable the window mode */
00312     COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);
00313   }
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup COMP_Group3 Internal Reference Voltage output function
00321  *  @brief   Internal Reference Voltage (VREFINT) output function.
00322  *
00323 @verbatim
00324  ===============================================================================
00325       ##### Internal Reference Voltage (VREFINT) output function #####
00326  ===============================================================================
00327
00328 @endverbatim
00329   * @{
00330   */
00331
00332 /**
00333   * @brief  Enables or disables the output of internal reference voltage (VREFINT).
00334   *         The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or
00335   *         CH9 (PB1).
00336   *         To correctly use this function, the SYSCFG_RIIOSwitchConfig() function
00337   *         should be called after.
00338   * @param  NewState: new state of the Vrefint output.
00339   *         This parameter can be: ENABLE or DISABLE.
00340   * @retval None
00341   */
00342 void COMP_VrefintOutputCmd(FunctionalState NewState)
00343 {
00344   /* Check the parameters */
00345   assert_param(IS_FUNCTIONAL_STATE(NewState));
00346
00347   if (NewState != DISABLE)
00348   {
00349     /* Enable the output of internal reference voltage */
00350     COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;
00351   }
00352   else
00353   {
00354     /* Disable the output of internal reference voltage */
00355     COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);
00356   }
00357 }
00358
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_comp.h Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_comp.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_comp.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the COMP firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_COMP_H
00028 #define __STM32L1xx_COMP_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup COMP
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  COMP Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t COMP_Speed;               /*!< Defines the speed of comparator 2.
00054                                           This parameter can be a value of @ref COMP_Speed */
00055   uint32_t COMP_InvertingInput;      /*!< Selects the inverting input of the comparator 2.
00056                                           This parameter can be a value of @ref COMP_InvertingInput */
00057   uint32_t COMP_OutputSelect;        /*!< Selects the output redirection of the comparator 2.
00058                                           This parameter can be a value of @ref COMP_OutputSelect */
00059
00060 }COMP_InitTypeDef;
00061
00062 /* Exported constants --------------------------------------------------------*/
00063
00064 /** @defgroup COMP_Exported_Constants
00065   * @{
00066   */
00067
00068 #define COMP_OutputLevel_High                   ((uint32_t)0x00000001)
00069 #define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
00070
00071 /** @defgroup COMP_Selection
00072   * @{
00073   */
00074
00075 #define COMP_Selection_COMP1                    ((uint32_t)0x00000001)
00076 #define COMP_Selection_COMP2                    ((uint32_t)0x00000002)
00077
00078 #define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
00079                                     ((PERIPH) == COMP_Selection_COMP2))
00080
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup COMP_InvertingInput
00086   * @{
00087   */
00088
00089 #define COMP_InvertingInput_None                ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
00090 #define COMP_InvertingInput_IO                  ((uint32_t)0x00040000)
00091 #define COMP_InvertingInput_VREFINT             ((uint32_t)0x00080000)
00092 #define COMP_InvertingInput_3_4VREFINT          ((uint32_t)0x000C0000)
00093 #define COMP_InvertingInput_1_2VREFINT          ((uint32_t)0x00100000)
00094 #define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00140000)
00095 #define COMP_InvertingInput_DAC1                ((uint32_t)0x00180000)
00096 #define COMP_InvertingInput_DAC2                ((uint32_t)0x001C0000)
00097
00098 #define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
00099                                         ((INPUT) == COMP_InvertingInput_IO) || \
00100                                         ((INPUT) == COMP_InvertingInput_VREFINT) || \
00101                                         ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
00102                                         ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
00103                                         ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
00104                                         ((INPUT) == COMP_InvertingInput_DAC1) || \
00105                                         ((INPUT) == COMP_InvertingInput_DAC2))
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup COMP_OutputSelect
00111   * @{
00112   */
00113
00114 #define COMP_OutputSelect_TIM2IC4               ((uint32_t)0x00000000)
00115 #define COMP_OutputSelect_TIM2OCREFCLR          ((uint32_t)0x00200000)
00116 #define COMP_OutputSelect_TIM3IC4               ((uint32_t)0x00400000)
00117 #define COMP_OutputSelect_TIM3OCREFCLR          ((uint32_t)0x00600000)
00118 #define COMP_OutputSelect_TIM4IC4               ((uint32_t)0x00800000)
00119 #define COMP_OutputSelect_TIM4OCREFCLR          ((uint32_t)0x00A00000)
00120 #define COMP_OutputSelect_TIM10IC1              ((uint32_t)0x00C00000)
00121 #define COMP_OutputSelect_None                  ((uint32_t)0x00E00000)
00122
00123 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
00124                                 ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
00125                                 ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
00126                                 ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
00127                                 ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
00128                                 ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
00129                                 ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
00130                                 ((OUTPUT) == COMP_OutputSelect_None))
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup COMP_Speed
00136   * @{
00137   */
00138
00139 #define COMP_Speed_Slow                         ((uint32_t)0x00000000)
00140 #define COMP_Speed_Fast                         ((uint32_t)0x00001000)
00141
00142 #define IS_COMP_SPEED(SPEED)    (((SPEED) == COMP_Speed_Slow) || \
00143                                  ((SPEED) == COMP_Speed_Fast))
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /* Exported macro ------------------------------------------------------------*/
00153 /* Exported functions ------------------------------------------------------- */
00154
00155 /*  Function used to set the COMP configuration to the default reset state ****/
00156 void COMP_DeInit(void);
00157
00158 /* Initialization and Configuration functions *********************************/
00159 void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
00160 void COMP_Cmd(FunctionalState NewState);
00161 uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
00162 void COMP_SW1SwitchConfig(FunctionalState NewState);
00163
00164 /* Window mode control function ***********************************************/
00165 void COMP_WindowCmd(FunctionalState NewState);
00166
00167 /* Internal Reference Voltage (VREFINT) output function ***********************/
00168 void COMP_VrefintOutputCmd(FunctionalState NewState);
00169
00170 #ifdef __cplusplus
00171 }
00172 #endif
00173
00174 #endif /*__STM32L1xx_COMP_H */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_crc.c Source File

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  • Libraries
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  • src

stm32l1xx_crc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides all the CRC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00019   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00020   *
00021   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32l1xx_crc.h"
00027
00028 /** @addtogroup STM32L1xx_StdPeriph_Driver
00029   * @{
00030   */
00031
00032 /** @defgroup CRC
00033   * @brief CRC driver modules
00034   * @{
00035   */
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private function prototypes -----------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /** @defgroup CRC_Private_Functions
00045   * @{
00046   */
00047
00048 /**
00049   * @brief  Resets the CRC Data register (DR).
00050   * @param  None
00051   * @retval None
00052   */
00053 void CRC_ResetDR(void)
00054 {
00055   /* Reset CRC generator */
00056   CRC->CR = CRC_CR_RESET;
00057 }
00058
00059 /**
00060   * @brief  Computes the 32-bit CRC of a given data word(32-bit).
00061   * @param  Data: data word(32-bit) to compute its CRC.
00062   * @retval 32-bit CRC
00063   */
00064 uint32_t CRC_CalcCRC(uint32_t Data)
00065 {
00066   CRC->DR = Data;
00067
00068   return (CRC->DR);
00069 }
00070
00071 /**
00072   * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
00073   * @param  pBuffer: pointer to the buffer containing the data to be computed.
00074   * @param  BufferLength: length of the buffer to be computed
00075   * @retval 32-bit CRC
00076   */
00077 uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
00078 {
00079   uint32_t index = 0;
00080
00081   for(index = 0; index < BufferLength; index++)
00082   {
00083     CRC->DR = pBuffer[index];
00084   }
00085   return (CRC->DR);
00086 }
00087
00088 /**
00089   * @brief  Returns the current CRC value.
00090   * @param  None
00091   * @retval 32-bit CRC
00092   */
00093 uint32_t CRC_GetCRC(void)
00094 {
00095   return (CRC->DR);
00096 }
00097
00098 /**
00099   * @brief  Stores a 8-bit data in the Independent Data(ID) register.
00100   * @param  IDValue: 8-bit value to be stored in the ID register
00101   * @retval None
00102   */
00103 void CRC_SetIDRegister(uint8_t IDValue)
00104 {
00105   CRC->IDR = IDValue;
00106 }
00107
00108 /**
00109   * @brief  Returns the 8-bit data stored in the Independent Data(ID) register.
00110   * @param  None
00111   * @retval 8-bit value of the ID register
00112   */
00113 uint8_t CRC_GetIDRegister(void)
00114 {
00115   return (CRC->IDR);
00116 }
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129
00130 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_crc.h Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_crc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the CRC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_CRC_H
00028 #define __STM32L1xx_CRC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup CRC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup CRC_Exported_Constants
00049   * @{
00050   */
00051
00052 /**
00053   * @}
00054   */
00055
00056 /* Exported macro ------------------------------------------------------------*/
00057 /* Exported functions ------------------------------------------------------- */
00058
00059 void CRC_ResetDR(void);
00060 uint32_t CRC_CalcCRC(uint32_t Data);
00061 uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
00062 uint32_t CRC_GetCRC(void);
00063 void CRC_SetIDRegister(uint8_t IDValue);
00064 uint8_t CRC_GetIDRegister(void);
00065
00066 #ifdef __cplusplus
00067 }
00068 #endif
00069
00070 #endif /* __STM32L1xx_CRC_H */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dac.c Source File

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  • src

stm32l1xx_dac.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Digital-to-Analog Converter (DAC) peripheral:
00009   *          + DAC channels configuration: trigger, output buffer, data format
00010   *          + DMA management
00011   *          + Interrupts and flags management
00012
00013   * @verbatim
00014   *
00015  ===============================================================================
00016                         ##### DAC Peripheral features #####
00017  ===============================================================================
00018     [..] The device integrates two 12-bit Digital Analog Converters that can
00019          be used independently or simultaneously (dual mode):
00020          (#) DAC channel1 with DAC_OUT1 (PA4) as output.
00021          (#) DAC channel2 with DAC_OUT2 (PA5) as output.
00022
00023     [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
00024          and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
00025          DAC_SetChannel1Data()/DAC_SetChannel2Data.
00026
00027     [..] Digital to Analog conversion can be triggered by:
00028          (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
00029              The used pin (GPIOx_Pin9) must be configured in input mode.
00030          (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9
00031              (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
00032              The timer TRGO event should be selected using TIM_SelectOutputTrigger()
00033          (#) Software using DAC_Trigger_Software.
00034
00035     [..] Each DAC channel integrates an output buffer that can be used to
00036          reduce the output impedance, and to drive external loads directly
00037          without having to add an external operational amplifier.
00038          To enable, the output buffer use
00039          DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
00040
00041     [..] Refer to the device datasheet for more details about output impedance
00042          value with and without output buffer.
00043
00044     [..] Both DAC channels can be used to generate:
00045          (#) Noise wave using DAC_WaveGeneration_Noise
00046          (#) Triangle wave using DAC_WaveGeneration_Triangle
00047
00048     [..] Wave generation can be disabled using DAC_WaveGeneration_None.
00049
00050     [..] The DAC data format can be:
00051          (#) 8-bit right alignment using DAC_Align_8b_R
00052          (#) 12-bit left alignment using DAC_Align_12b_L
00053          (#) 12-bit right alignment using DAC_Align_12b_R
00054
00055     [..] The analog output voltage on each DAC channel pin is determined
00056          by the following equation: DAC_OUTx = VREF+ * DOR / 4095
00057          with  DOR is the Data Output Register.
00058          VEF+ is the input voltage reference (refer to the device datasheet)
00059          e.g. To set DAC_OUT1 to 0.7V, use
00060          DAC_SetChannel1Data(DAC_Align_12b_R, 868);
00061          Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.
00062
00063     [..] A DMA1 request can be generated when an external trigger (but not
00064          a software trigger) occurs if DMA1 requests are enabled using
00065          DAC_DMACmd()
00066     [..] DMA1 requests are mapped as following:
00067          (#) DAC channel1 is mapped on DMA1 channel3 which must be already
00068              configured.
00069          (#) DAC channel2 is mapped on DMA1 channel4 which must be already
00070              configured.
00071
00072                       ##### How to use this driver #####
00073  ===============================================================================
00074     [..]
00075         (+) DAC APB clock must be enabled to get write access to DAC registers using
00076             RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
00077         (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00078         (+) Configure the DAC channel using DAC_Init()
00079         (+) Enable the DAC channel using DAC_Cmd()
00080
00081    @endverbatim
00082   *
00083   ******************************************************************************
00084   * @attention
00085   *
00086   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00087   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00088   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00089   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00090   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00091   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00092   *
00093   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00094   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00095   *
00096   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32l1xx_dac.h"
00102 #include "stm32l1xx_rcc.h"
00103
00104 /** @addtogroup STM32L1xx_StdPeriph_Driver
00105   * @{
00106   */
00107
00108 /** @defgroup DAC
00109   * @brief DAC driver modules
00110   * @{
00111   */
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* CR register Mask */
00116 #define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
00117
00118 /* DAC Dual Channels SWTRIG masks */
00119 #define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
00120 #define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
00121
00122 /* DHR registers offsets */
00123 #define DHR12R1_OFFSET             ((uint32_t)0x00000008)
00124 #define DHR12R2_OFFSET             ((uint32_t)0x00000014)
00125 #define DHR12RD_OFFSET             ((uint32_t)0x00000020)
00126
00127 /* DOR register offset */
00128 #define DOR_OFFSET                 ((uint32_t)0x0000002C)
00129
00130 /* Private macro -------------------------------------------------------------*/
00131 /* Private variables ---------------------------------------------------------*/
00132 /* Private function prototypes -----------------------------------------------*/
00133 /* Private functions ---------------------------------------------------------*/
00134
00135 /** @defgroup DAC_Private_Functions
00136   * @{
00137   */
00138
00139 /** @defgroup DAC_Group1 DAC channels configuration
00140  *  @brief   DAC channels configuration: trigger, output buffer, data format.
00141  *
00142 @verbatim
00143  ===============================================================================
00144   ##### DAC channels configuration: trigger, output buffer, data format #####
00145  ===============================================================================
00146
00147 @endverbatim
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00153   * @param  None
00154   * @retval None
00155   */
00156 void DAC_DeInit(void)
00157 {
00158   /* Enable DAC reset state */
00159   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
00160   /* Release DAC from reset state */
00161   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00162 }
00163
00164 /**
00165   * @brief  Initializes the DAC peripheral according to the specified
00166   *         parameters in the DAC_InitStruct.
00167   * @param  DAC_Channel: the selected DAC channel.
00168   *   This parameter can be one of the following values:
00169   *     @arg DAC_Channel_1: DAC Channel1 selected.
00170   *     @arg DAC_Channel_2: DAC Channel2 selected.
00171   * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
00172   *         contains the configuration information for the specified DAC channel.
00173   * @retval None
00174   */
00175 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
00176 {
00177   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00178
00179   /* Check the DAC parameters */
00180   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00181   assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
00182   assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
00183   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
00184   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
00185
00186 /*---------------------------- DAC CR Configuration --------------------------*/
00187   /* Get the DAC CR value */
00188   tmpreg1 = DAC->CR;
00189   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00190   tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
00191   /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
00192      mask/amplitude for wave generation */
00193   /* Set TSELx and TENx bits according to DAC_Trigger value */
00194   /* Set WAVEx bits according to DAC_WaveGeneration value */
00195   /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
00196   /* Set BOFFx bit according to DAC_OutputBuffer value */
00197   tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
00198              DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
00199   /* Calculate CR register value depending on DAC_Channel */
00200   tmpreg1 |= tmpreg2 << DAC_Channel;
00201   /* Write to DAC CR */
00202   DAC->CR = tmpreg1;
00203 }
00204
00205 /**
00206   * @brief  Fills each DAC_InitStruct member with its default value.
00207   * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
00208   *         be initialized.
00209   * @retval None
00210   */
00211 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
00212 {
00213 /*--------------- Reset DAC init structure parameters values -----------------*/
00214   /* Initialize the DAC_Trigger member */
00215   DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
00216   /* Initialize the DAC_WaveGeneration member */
00217   DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
00218   /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
00219   DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
00220   /* Initialize the DAC_OutputBuffer member */
00221   DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
00222 }
00223
00224 /**
00225   * @brief  Enables or disables the specified DAC channel.
00226   * @param  DAC_Channel: The selected DAC channel.
00227   *   This parameter can be one of the following values:
00228   *     @arg DAC_Channel_1: DAC Channel1 selected
00229   *     @arg DAC_Channel_2: DAC Channel2 selected
00230   * @param  NewState: new state of the DAC channel.
00231   *      This parameter can be: ENABLE or DISABLE.
00232   * @note When the DAC channel is enabled the trigger source can no more
00233   *       be modified.
00234   * @retval None
00235   */
00236 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
00237 {
00238   /* Check the parameters */
00239   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00240   assert_param(IS_FUNCTIONAL_STATE(NewState));
00241
00242   if (NewState != DISABLE)
00243   {
00244     /* Enable the selected DAC channel */
00245     DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
00246   }
00247   else
00248   {
00249     /* Disable the selected DAC channel */
00250     DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
00251   }
00252 }
00253
00254 /**
00255   * @brief  Enables or disables the selected DAC channel software trigger.
00256   * @param  DAC_Channel: the selected DAC channel.
00257   *   This parameter can be one of the following values:
00258   *     @arg DAC_Channel_1: DAC Channel1 selected
00259   *     @arg DAC_Channel_2: DAC Channel2 selected
00260   * @param  NewState: new state of the selected DAC channel software trigger.
00261   *   This parameter can be: ENABLE or DISABLE.
00262   * @retval None
00263   */
00264 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
00265 {
00266   /* Check the parameters */
00267   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00268   assert_param(IS_FUNCTIONAL_STATE(NewState));
00269
00270   if (NewState != DISABLE)
00271   {
00272     /* Enable software trigger for the selected DAC channel */
00273     DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
00274   }
00275   else
00276   {
00277     /* Disable software trigger for the selected DAC channel */
00278     DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
00279   }
00280 }
00281
00282 /**
00283   * @brief  Enables or disables simultaneously the two DAC channels software
00284   *         triggers.
00285   * @param  NewState: new state of the DAC channels software triggers.
00286   *   This parameter can be: ENABLE or DISABLE.
00287   * @retval None
00288   */
00289 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
00290 {
00291   /* Check the parameters */
00292   assert_param(IS_FUNCTIONAL_STATE(NewState));
00293
00294   if (NewState != DISABLE)
00295   {
00296     /* Enable software trigger for both DAC channels */
00297     DAC->SWTRIGR |= DUAL_SWTRIG_SET;
00298   }
00299   else
00300   {
00301     /* Disable software trigger for both DAC channels */
00302     DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
00303   }
00304 }
00305
00306 /**
00307   * @brief  Enables or disables the selected DAC channel wave generation.
00308   * @param  DAC_Channel: the selected DAC channel.
00309   *   This parameter can be one of the following values:
00310   *     @arg DAC_Channel_1: DAC Channel1 selected
00311   *     @arg DAC_Channel_2: DAC Channel2 selected
00312   * @param  DAC_Wave: Specifies the wave type to enable or disable.
00313   *   This parameter can be one of the following values:
00314   *     @arg DAC_Wave_Noise: noise wave generation
00315   *     @arg DAC_Wave_Triangle: triangle wave generation
00316   * @param  NewState: new state of the selected DAC channel wave generation.
00317   *   This parameter can be: ENABLE or DISABLE.
00318   * @note
00319   * @retval None
00320   */
00321 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
00322 {
00323   /* Check the parameters */
00324   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00325   assert_param(IS_DAC_WAVE(DAC_Wave));
00326   assert_param(IS_FUNCTIONAL_STATE(NewState));
00327
00328   if (NewState != DISABLE)
00329   {
00330     /* Enable the selected wave generation for the selected DAC channel */
00331     DAC->CR |= DAC_Wave << DAC_Channel;
00332   }
00333   else
00334   {
00335     /* Disable the selected wave generation for the selected DAC channel */
00336     DAC->CR &= ~(DAC_Wave << DAC_Channel);
00337   }
00338 }
00339
00340 /**
00341   * @brief  Set the specified data holding register value for DAC channel1.
00342   * @param  DAC_Align: Specifies the data alignment for DAC channel1.
00343   *   This parameter can be one of the following values:
00344   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00345   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00346   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00347   * @param  Data : Data to be loaded in the selected data holding register.
00348   * @retval None
00349   */
00350 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
00351 {
00352   __IO uint32_t tmp = 0;
00353
00354   /* Check the parameters */
00355   assert_param(IS_DAC_ALIGN(DAC_Align));
00356   assert_param(IS_DAC_DATA(Data));
00357
00358   tmp = (uint32_t)DAC_BASE;
00359   tmp += DHR12R1_OFFSET + DAC_Align;
00360
00361   /* Set the DAC channel1 selected data holding register */
00362   *(__IO uint32_t *) tmp = Data;
00363 }
00364
00365 /**
00366   * @brief  Set the specified data holding register value for DAC channel2.
00367   * @param  DAC_Align: Specifies the data alignment for DAC channel2.
00368   *   This parameter can be one of the following values:
00369   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00370   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00371   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00372   * @param  Data : Data to be loaded in the selected data holding register.
00373   * @retval None
00374   */
00375 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
00376 {
00377   __IO uint32_t tmp = 0;
00378
00379   /* Check the parameters */
00380   assert_param(IS_DAC_ALIGN(DAC_Align));
00381   assert_param(IS_DAC_DATA(Data));
00382
00383   tmp = (uint32_t)DAC_BASE;
00384   tmp += DHR12R2_OFFSET + DAC_Align;
00385
00386   /* Set the DAC channel2 selected data holding register */
00387   *(__IO uint32_t *)tmp = Data;
00388 }
00389
00390 /**
00391   * @brief  Set the specified data holding register value for dual channel DAC.
00392   * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
00393   *   This parameter can be one of the following values:
00394   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00395   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00396   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00397   * @param  Data2: Data for DAC Channel2 to be loaded in the selected data
00398   *         holding register.
00399   * @param  Data1: Data for DAC Channel1 to be loaded in the selected data
00400   *         holding register.
00401   * @note In dual mode, a unique register access is required to write in both
00402   *       DAC channels at the same time.
00403   * @retval None
00404   */
00405 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
00406 {
00407   uint32_t data = 0, tmp = 0;
00408
00409   /* Check the parameters */
00410   assert_param(IS_DAC_ALIGN(DAC_Align));
00411   assert_param(IS_DAC_DATA(Data1));
00412   assert_param(IS_DAC_DATA(Data2));
00413
00414   /* Calculate and set dual DAC data holding register value */
00415   if (DAC_Align == DAC_Align_8b_R)
00416   {
00417     data = ((uint32_t)Data2 << 8) | Data1;
00418   }
00419   else
00420   {
00421     data = ((uint32_t)Data2 << 16) | Data1;
00422   }
00423
00424   tmp = (uint32_t)DAC_BASE;
00425   tmp += DHR12RD_OFFSET + DAC_Align;
00426
00427   /* Set the dual DAC selected data holding register */
00428   *(__IO uint32_t *)tmp = data;
00429 }
00430
00431 /**
00432   * @brief  Returns the last data output value of the selected DAC channel.
00433   * @param  DAC_Channel: the selected DAC channel.
00434   *   This parameter can be one of the following values:
00435   *     @arg DAC_Channel_1: DAC Channel1 selected
00436   *     @arg DAC_Channel_2: DAC Channel2 selected
00437   * @retval The selected DAC channel data output value.
00438   */
00439 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
00440 {
00441   __IO uint32_t tmp = 0;
00442
00443   /* Check the parameters */
00444   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00445
00446   tmp = (uint32_t) DAC_BASE ;
00447   tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
00448
00449   /* Returns the DAC channel data output register value */
00450   return (uint16_t) (*(__IO uint32_t*) tmp);
00451 }
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup DAC_Group2 DMA management functions
00458  *  @brief   DMA management functions
00459  *
00460 @verbatim
00461  ===============================================================================
00462                     ##### DMA management functions #####
00463  ===============================================================================
00464
00465 @endverbatim
00466   * @{
00467   */
00468
00469 /**
00470   * @brief  Enables or disables the specified DAC channel DMA request.
00471   *         When enabled DMA1 is generated when an external trigger (EXTI Line9,
00472   *         TIM2, TIM4, TIM6, TIM7 or TIM9  but not a software trigger) occurs.
00473   * @param  DAC_Channel: the selected DAC channel.
00474   *   This parameter can be one of the following values:
00475   *     @arg DAC_Channel_1: DAC Channel1 selected
00476   *     @arg DAC_Channel_2: DAC Channel2 selected
00477   * @param  NewState: new state of the selected DAC channel DMA request.
00478   *         This parameter can be: ENABLE or DISABLE.
00479   * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
00480   *  must be already configured.
00481   * @retval None
00482   */
00483 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
00484 {
00485   /* Check the parameters */
00486   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00487   assert_param(IS_FUNCTIONAL_STATE(NewState));
00488
00489   if (NewState != DISABLE)
00490   {
00491     /* Enable the selected DAC channel DMA request */
00492     DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
00493   }
00494   else
00495   {
00496     /* Disable the selected DAC channel DMA request */
00497     DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
00498   }
00499 }
00500
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup DAC_Group3 Interrupts and flags management functions
00506  *  @brief   Interrupts and flags management functions
00507  *
00508 @verbatim
00509  ===============================================================================
00510             ##### Interrupts and flags management functions #####
00511  ===============================================================================
00512
00513 @endverbatim
00514   * @{
00515   */
00516
00517 /**
00518   * @brief  Enables or disables the specified DAC interrupts.
00519   * @param  DAC_Channel: the selected DAC channel.
00520   *   This parameter can be one of the following values:
00521   *     @arg DAC_Channel_1: DAC Channel1 selected
00522   *     @arg DAC_Channel_2: DAC Channel2 selected
00523   * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
00524   *   This parameter can be the following value:
00525   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00526   * @note The DMA underrun occurs when a second external trigger arrives before
00527   *       the acknowledgement for the first external trigger is received (first request).
00528   * @param  NewState: new state of the specified DAC interrupts.
00529   *         This parameter can be: ENABLE or DISABLE.
00530   * @retval None
00531   */
00532 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
00533 {
00534   /* Check the parameters */
00535   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00536   assert_param(IS_FUNCTIONAL_STATE(NewState));
00537   assert_param(IS_DAC_IT(DAC_IT));
00538
00539   if (NewState != DISABLE)
00540   {
00541     /* Enable the selected DAC interrupts */
00542     DAC->CR |=  (DAC_IT << DAC_Channel);
00543   }
00544   else
00545   {
00546     /* Disable the selected DAC interrupts */
00547     DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
00548   }
00549 }
00550
00551 /**
00552   * @brief  Checks whether the specified DAC flag is set or not.
00553   * @param  DAC_Channel: thee selected DAC channel.
00554   *   This parameter can be one of the following values:
00555   *     @arg DAC_Channel_1: DAC Channel1 selected
00556   *     @arg DAC_Channel_2: DAC Channel2 selected
00557   * @param  DAC_FLAG: specifies the flag to check.
00558   *   This parameter can be only of the following value:
00559   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
00560   * @note The DMA underrun occurs when a second external trigger arrives before
00561   *       the acknowledgement for the first external trigger is received (first request).
00562   * @retval The new state of DAC_FLAG (SET or RESET).
00563   */
00564 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00565 {
00566   FlagStatus bitstatus = RESET;
00567   /* Check the parameters */
00568   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00569   assert_param(IS_DAC_FLAG(DAC_FLAG));
00570
00571   /* Check the status of the specified DAC flag */
00572   if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
00573   {
00574     /* DAC_FLAG is set */
00575     bitstatus = SET;
00576   }
00577   else
00578   {
00579     /* DAC_FLAG is reset */
00580     bitstatus = RESET;
00581   }
00582   /* Return the DAC_FLAG status */
00583   return  bitstatus;
00584 }
00585
00586 /**
00587   * @brief  Clears the DAC channel's pending flags.
00588   * @param  DAC_Channel: the selected DAC channel.
00589   *   This parameter can be one of the following values:
00590   *     @arg DAC_Channel_1: DAC Channel1 selected
00591   *     @arg DAC_Channel_2: DAC Channel2 selected
00592   * @param  DAC_FLAG: specifies the flag to clear.
00593   *   This parameter can be the following value:
00594   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
00595   * @retval None
00596   */
00597 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00598 {
00599   /* Check the parameters */
00600   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00601   assert_param(IS_DAC_FLAG(DAC_FLAG));
00602
00603   /* Clear the selected DAC flags */
00604   DAC->SR = (DAC_FLAG << DAC_Channel);
00605 }
00606
00607 /**
00608   * @brief  Checks whether the specified DAC interrupt has occurred or not.
00609   * @param  DAC_Channel: the selected DAC channel.
00610   *   This parameter can be one of the following values:
00611   *     @arg DAC_Channel_1: DAC Channel1 selected
00612   *     @arg DAC_Channel_2: DAC Channel2 selected
00613   * @param  DAC_IT: specifies the DAC interrupt source to check.
00614   *   This parameter can be the following values:
00615   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00616   * @note The DMA underrun occurs when a second external trigger arrives before
00617   *       the acknowledgement for the first external trigger is received (first request).
00618   * @retval The new state of DAC_IT (SET or RESET).
00619   */
00620 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
00621 {
00622   ITStatus bitstatus = RESET;
00623   uint32_t enablestatus = 0;
00624
00625   /* Check the parameters */
00626   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00627   assert_param(IS_DAC_IT(DAC_IT));
00628
00629   /* Get the DAC_IT enable bit status */
00630   enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
00631
00632   /* Check the status of the specified DAC interrupt */
00633   if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
00634   {
00635     /* DAC_IT is set */
00636     bitstatus = SET;
00637   }
00638   else
00639   {
00640     /* DAC_IT is reset */
00641     bitstatus = RESET;
00642   }
00643   /* Return the DAC_IT status */
00644   return  bitstatus;
00645 }
00646
00647 /**
00648   * @brief  Clears the DAC channel's interrupt pending bits.
00649   * @param  DAC_Channel: the selected DAC channel.
00650   *   This parameter can be one of the following values:
00651   *     @arg DAC_Channel_1: DAC Channel1 selected
00652   *     @arg DAC_Channel_2: DAC Channel2 selected
00653   * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
00654   *   This parameter can be the following values:
00655   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00656   * @retval None
00657   */
00658 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
00659 {
00660   /* Check the parameters */
00661   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00662   assert_param(IS_DAC_IT(DAC_IT));
00663
00664   /* Clear the selected DAC interrupt pending bits */
00665   DAC->SR = (DAC_IT << DAC_Channel);
00666 }
00667
00668 /**
00669   * @}
00670   */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dac.h Source File

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  • inc

stm32l1xx_dac.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the DAC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_DAC_H
00028 #define __STM32L1xx_DAC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup DAC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  DAC Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
00054                                                   This parameter can be a value of @ref DAC_trigger_selection */
00055
00056   uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
00057                                                   are generated, or whether no wave is generated.
00058                                                   This parameter can be a value of @ref DAC_wave_generation */
00059
00060   uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
00061                                                   the maximum amplitude triangle generation for the DAC channel.
00062                                                   This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
00063
00064   uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00065                                                   This parameter can be a value of @ref DAC_output_buffer */
00066 }DAC_InitTypeDef;
00067
00068 /* Exported constants --------------------------------------------------------*/
00069
00070 /** @defgroup DAC_Exported_Constants
00071   * @{
00072   */
00073
00074 /** @defgroup DAC_trigger_selection
00075   * @{
00076   */
00077
00078 #define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00079                                                                        has been loaded, and not by external trigger */
00080 #define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00081 #define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00082 #define DAC_Trigger_T9_TRGO                ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
00083 #define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00084 #define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00085 #define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00086 #define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
00087
00088 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
00089                                  ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
00090                                  ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
00091                                  ((TRIGGER) == DAC_Trigger_T9_TRGO) || \
00092                                  ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
00093                                  ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
00094                                  ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
00095                                  ((TRIGGER) == DAC_Trigger_Software))
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup DAC_wave_generation
00102   * @{
00103   */
00104
00105 #define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
00106 #define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
00107 #define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
00108 #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
00109                                     ((WAVE) == DAC_WaveGeneration_Noise) || \
00110                                     ((WAVE) == DAC_WaveGeneration_Triangle))
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup DAC_lfsrunmask_triangleamplitude
00116   * @{
00117   */
00118
00119 #define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00120 #define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00121 #define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00122 #define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00123 #define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00124 #define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00125 #define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00126 #define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00127 #define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00128 #define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00129 #define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00130 #define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00131 #define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
00132 #define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
00133 #define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
00134 #define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
00135 #define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
00136 #define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
00137 #define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
00138 #define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
00139 #define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
00140 #define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
00141 #define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
00142 #define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
00143
00144 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
00145                                                       ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
00146                                                       ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
00147                                                       ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
00148                                                       ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
00149                                                       ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
00150                                                       ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
00151                                                       ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
00152                                                       ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
00153                                                       ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
00154                                                       ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
00155                                                       ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
00156                                                       ((VALUE) == DAC_TriangleAmplitude_1) || \
00157                                                       ((VALUE) == DAC_TriangleAmplitude_3) || \
00158                                                       ((VALUE) == DAC_TriangleAmplitude_7) || \
00159                                                       ((VALUE) == DAC_TriangleAmplitude_15) || \
00160                                                       ((VALUE) == DAC_TriangleAmplitude_31) || \
00161                                                       ((VALUE) == DAC_TriangleAmplitude_63) || \
00162                                                       ((VALUE) == DAC_TriangleAmplitude_127) || \
00163                                                       ((VALUE) == DAC_TriangleAmplitude_255) || \
00164                                                       ((VALUE) == DAC_TriangleAmplitude_511) || \
00165                                                       ((VALUE) == DAC_TriangleAmplitude_1023) || \
00166                                                       ((VALUE) == DAC_TriangleAmplitude_2047) || \
00167                                                       ((VALUE) == DAC_TriangleAmplitude_4095))
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup DAC_output_buffer
00173   * @{
00174   */
00175
00176 #define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
00177 #define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
00178 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
00179                                            ((STATE) == DAC_OutputBuffer_Disable))
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup DAC_Channel_selection
00185   * @{
00186   */
00187
00188 #define DAC_Channel_1                      ((uint32_t)0x00000000)
00189 #define DAC_Channel_2                      ((uint32_t)0x00000010)
00190 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
00191                                  ((CHANNEL) == DAC_Channel_2))
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup DAC_data_alignment
00197   * @{
00198   */
00199
00200 #define DAC_Align_12b_R                    ((uint32_t)0x00000000)
00201 #define DAC_Align_12b_L                    ((uint32_t)0x00000004)
00202 #define DAC_Align_8b_R                     ((uint32_t)0x00000008)
00203 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
00204                              ((ALIGN) == DAC_Align_12b_L) || \
00205                              ((ALIGN) == DAC_Align_8b_R))
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup DAC_wave_generation
00211   * @{
00212   */
00213
00214 #define DAC_Wave_Noise                     ((uint32_t)0x00000040)
00215 #define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
00216 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
00217                            ((WAVE) == DAC_Wave_Triangle))
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup DAC_data
00223   * @{
00224   */
00225
00226 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
00227
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup DAC_interrupts_definition
00233   * @{
00234   */
00235
00236 #define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)
00237 #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
00238
00239 /**
00240   * @}
00241   */
00242
00243
00244 /** @defgroup DAC_flags_definition
00245   * @{
00246   */
00247
00248 #define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)
00249
00250 #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
00251
00252 /**
00253   * @}
00254   */
00255
00256 /**
00257   * @}
00258   */
00259
00260 /* Exported macro ------------------------------------------------------------*/
00261 /* Exported functions ------------------------------------------------------- */
00262
00263 /*  Function used to set the DAC configuration to the default reset state *****/
00264 void DAC_DeInit(void);
00265
00266 /*  DAC channels configuration: trigger, output buffer, data format functions */
00267 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
00268 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
00269 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
00270 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
00271 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
00272 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
00273 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
00274 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
00275 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
00276 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
00277
00278 /* DMA management functions ***************************************************/
00279 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
00280
00281 /* Interrupts and flags management functions **********************************/
00282 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
00283 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
00284 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
00285 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
00286 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
00287
00288 #ifdef __cplusplus
00289 }
00290 #endif
00291
00292 #endif /*__STM32L1xx_DAC_H */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dbgmcu.c Source File

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stm32l1xx_dbgmcu.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dbgmcu.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides all the DBGMCU firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00019   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00020   *
00021   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32l1xx_dbgmcu.h"
00027
00028 /** @addtogroup STM32L1xx_StdPeriph_Driver
00029   * @{
00030   */
00031
00032 /** @defgroup DBGMCU
00033   * @brief DBGMCU driver modules
00034   * @{
00035   */
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /** @defgroup DBGMCU_Private_Functions
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  Returns the device revision identifier.
00052   * @param  None
00053   * @retval Device revision identifier
00054   */
00055 uint32_t DBGMCU_GetREVID(void)
00056 {
00057    return(DBGMCU->IDCODE >> 16);
00058 }
00059
00060 /**
00061   * @brief  Returns the device identifier.
00062   * @param  None
00063   * @retval Device identifier
00064   */
00065 uint32_t DBGMCU_GetDEVID(void)
00066 {
00067    return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
00068 }
00069
00070 /**
00071   * @brief  Configures low power mode behavior when the MCU is in Debug mode.
00072   * @param  DBGMCU_Periph: specifies the low power mode.
00073   *   This parameter can be any combination of the following values:
00074   *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
00075   *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode
00076   *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
00077   * @param  NewState: new state of the specified low power mode in Debug mode.
00078   *   This parameter can be: ENABLE or DISABLE.
00079   * @retval None
00080   */
00081 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
00082 {
00083   /* Check the parameters */
00084   assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
00085   assert_param(IS_FUNCTIONAL_STATE(NewState));
00086
00087   if (NewState != DISABLE)
00088   {
00089     DBGMCU->CR |= DBGMCU_Periph;
00090   }
00091   else
00092   {
00093     DBGMCU->CR &= ~DBGMCU_Periph;
00094   }
00095 }
00096
00097
00098 /**
00099   * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
00100   * @param  DBGMCU_Periph: specifies the APB1 peripheral.
00101   *   This parameter can be any combination of the following values:
00102   *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
00103   *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
00104   *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
00105   *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
00106   *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
00107   *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
00108   *     @arg DBGMCU_RTC_STOP:
00109   *       + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when
00110   *         Core is halted.
00111   *       + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar
00112   *         and Wakeup counter stopped when Core is halted.
00113   *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
00114   *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
00115   *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is
00116   *                                     halted
00117   *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is
00118   *                                     halted
00119   * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
00120   *   This parameter can be: ENABLE or DISABLE.
00121   * @retval None
00122   */
00123 void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
00124 {
00125   /* Check the parameters */
00126   assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
00127   assert_param(IS_FUNCTIONAL_STATE(NewState));
00128
00129   if (NewState != DISABLE)
00130   {
00131     DBGMCU->APB1FZ |= DBGMCU_Periph;
00132   }
00133   else
00134   {
00135     DBGMCU->APB1FZ &= ~DBGMCU_Periph;
00136   }
00137 }
00138
00139 /**
00140   * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
00141   * @param  DBGMCU_Periph: specifies the APB2 peripheral.
00142   *   This parameter can be any combination of the following values:
00143   *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
00144   *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
00145   *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
00146   * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
00147   *   This parameter can be: ENABLE or DISABLE.
00148   * @retval None
00149   */
00150 void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
00151 {
00152   /* Check the parameters */
00153   assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
00154   assert_param(IS_FUNCTIONAL_STATE(NewState));
00155
00156   if (NewState != DISABLE)
00157   {
00158     DBGMCU->APB2FZ |= DBGMCU_Periph;
00159   }
00160   else
00161   {
00162     DBGMCU->APB2FZ &= ~DBGMCU_Periph;
00163   }
00164 }
00165
00166 /**
00167   * @}
00168   */
00169
00170 /**
00171   * @}
00172   */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dbgmcu.h Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_dbgmcu.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dbgmcu.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the DBGMCU
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_DBGMCU_H
00028 #define __STM32L1xx_DBGMCU_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup DBGMCU
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup DBGMCU_Exported_Constants
00049   * @{
00050   */
00051
00052 #define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
00053 #define DBGMCU_STOP                  ((uint32_t)0x00000002)
00054 #define DBGMCU_STANDBY               ((uint32_t)0x00000004)
00055 #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
00056
00057 #define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
00058 #define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
00059 #define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
00060 #define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
00061 #define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
00062 #define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
00063 #define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
00064 #define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
00065 #define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
00066 #define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
00067 #define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
00068 #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
00069
00070 #define DBGMCU_TIM9_STOP             ((uint32_t)0x00000004)
00071 #define DBGMCU_TIM10_STOP            ((uint32_t)0x00000008)
00072 #define DBGMCU_TIM11_STOP            ((uint32_t)0x00000010)
00073 #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /* Exported functions ------------------------------------------------------- */
00081
00082 uint32_t DBGMCU_GetREVID(void);
00083 uint32_t DBGMCU_GetDEVID(void);
00084 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
00085 void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
00086 void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
00087
00088 #ifdef __cplusplus
00089 }
00090 #endif
00091
00092 #endif /* __STM32L1xx_DBGMCU_H */
00093
00094 /**
00095   * @}
00096   */
00097
00098 /**
00099   * @}
00100   */
00101
00102 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dma.c Source File

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  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src

stm32l1xx_dma.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Direct Memory Access controller (DMA):
00009   *           + Initialization and Configuration
00010   *           + Data Counter
00011   *           + Interrupts and flags management
00012   *
00013   *  @verbatim
00014   ==============================================================================
00015                       ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     (#) Enable The DMA controller clock using
00019         RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
00020         using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
00021     (#) Enable and configure the peripheral to be connected to the DMA channel
00022                (except for internal SRAM / FLASH memories: no initialization is
00023                necessary).
00024     (#) For a given Channel, program the Source and Destination addresses,
00025         the transfer Direction, the Buffer Size, the Peripheral and Memory
00026         Incrementation mode and Data Size, the Circular or Normal mode,
00027         the channel transfer Priority and the Memory-to-Memory transfer
00028         mode (if needed) using the DMA_Init() function.
00029     (#) Enable the NVIC and the corresponding interrupt(s) using the function
00030         DMA_ITConfig() if you need to use DMA interrupts.
00031     (#) Enable the DMA channel using the DMA_Cmd() function.
00032     (#) Activate the needed channel Request using PPP_DMACmd() function for
00033         any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
00034         The function allowing this operation is provided in each PPP peripheral
00035         driver (ie. SPI_DMACmd for SPI peripheral).
00036     (#) Optionally, you can configure the number of data to be transferred
00037         when the channel is disabled (ie. after each Transfer Complete event
00038         or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
00039         And you can get the number of remaining data to be transferred using
00040         the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
00041         enabled and running).
00042     (#) To control DMA events you can use one of the following two methods:
00043         (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
00044         (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
00045              phase and DMA_GetITStatus() function into interrupt routines in
00046              communication phase.
00047              After checking on a flag you should clear it using DMA_ClearFlag()
00048              function. And after checking on an interrupt event you should
00049              clear it using DMA_ClearITPendingBit() function.
00050     @endverbatim
00051
00052   ******************************************************************************
00053   * @attention
00054   *
00055   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00056   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00057   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00058   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00059   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00060   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00061   *
00062   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00063   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00064   *
00065   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00066   ******************************************************************************
00067   */
00068
00069 /* Includes ------------------------------------------------------------------*/
00070 #include "stm32l1xx_dma.h"
00071 #include "stm32l1xx_rcc.h"
00072
00073 /** @addtogroup STM32L1xx_StdPeriph_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup DMA
00078   * @brief DMA driver modules
00079   * @{
00080   */
00081
00082 /* Private typedef -----------------------------------------------------------*/
00083 /* Private define ------------------------------------------------------------*/
00084
00085 /* DMA1 Channelx interrupt pending bit masks */
00086 #define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00087 #define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00088 #define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00089 #define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00090 #define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00091 #define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
00092 #define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
00093
00094 /* DMA2 Channelx interrupt pending bit masks */
00095 #define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00096 #define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00097 #define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00098 #define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00099 #define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00100
00101 /* DMA FLAG mask */
00102 #define FLAG_MASK                ((uint32_t)0x10000000)
00103
00104 /* DMA registers Masks */
00105 #define CCR_CLEAR_MASK           ((uint32_t)0xFFFF800F)
00106
00107 /* Private macro -------------------------------------------------------------*/
00108 /* Private variables ---------------------------------------------------------*/
00109 /* Private function prototypes -----------------------------------------------*/
00110 /* Private functions ---------------------------------------------------------*/
00111
00112
00113 /** @defgroup DMA_Private_Functions
00114   * @{
00115   */
00116
00117 /** @defgroup DMA_Group1 Initialization and Configuration functions
00118  *  @brief   Initialization and Configuration functions
00119  *
00120 @verbatim
00121  ===============================================================================
00122             ##### Initialization and Configuration functions #####
00123  ===============================================================================
00124     [..] This subsection provides functions allowing to initialize the DMA channel
00125          source and destination addresses, incrementation and data sizes, transfer
00126          direction, buffer size, circular/normal mode selection, memory-to-memory
00127          mode selection and channel priority value.
00128     [..] The DMA_Init() function follows the DMA configuration procedures as described
00129          in reference manual (RM0038).
00130 @endverbatim
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Deinitializes the DMAy Channelx registers to their default reset
00136   *         values.
00137   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00138   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00139   * @retval None
00140   */
00141 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
00142 {
00143   /* Check the parameters */
00144   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00145
00146   /* Disable the selected DMAy Channelx */
00147   DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00148
00149   /* Reset DMAy Channelx control register */
00150   DMAy_Channelx->CCR  = 0;
00151
00152   /* Reset DMAy Channelx remaining bytes register */
00153   DMAy_Channelx->CNDTR = 0;
00154
00155   /* Reset DMAy Channelx peripheral address register */
00156   DMAy_Channelx->CPAR  = 0;
00157
00158   /* Reset DMAy Channelx memory address register */
00159   DMAy_Channelx->CMAR = 0;
00160
00161   if (DMAy_Channelx == DMA1_Channel1)
00162   {
00163     /* Reset interrupt pending bits for DMA1 Channel1 */
00164     DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
00165   }
00166   else if (DMAy_Channelx == DMA1_Channel2)
00167   {
00168     /* Reset interrupt pending bits for DMA1 Channel2 */
00169     DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
00170   }
00171   else if (DMAy_Channelx == DMA1_Channel3)
00172   {
00173     /* Reset interrupt pending bits for DMA1 Channel3 */
00174     DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
00175   }
00176   else if (DMAy_Channelx == DMA1_Channel4)
00177   {
00178     /* Reset interrupt pending bits for DMA1 Channel4 */
00179     DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
00180   }
00181   else if (DMAy_Channelx == DMA1_Channel5)
00182   {
00183     /* Reset interrupt pending bits for DMA1 Channel5 */
00184     DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
00185   }
00186   else if (DMAy_Channelx == DMA1_Channel6)
00187   {
00188     /* Reset interrupt pending bits for DMA1 Channel6 */
00189     DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
00190   }
00191   else if (DMAy_Channelx == DMA1_Channel7)
00192   {
00193     /* Reset interrupt pending bits for DMA1 Channel7 */
00194     DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
00195   }
00196   else if (DMAy_Channelx == DMA2_Channel1)
00197   {
00198     /* Reset interrupt pending bits for DMA2 Channel1 */
00199     DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
00200   }
00201   else if (DMAy_Channelx == DMA2_Channel2)
00202   {
00203     /* Reset interrupt pending bits for DMA2 Channel2 */
00204     DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
00205   }
00206   else if (DMAy_Channelx == DMA2_Channel3)
00207   {
00208     /* Reset interrupt pending bits for DMA2 Channel3 */
00209     DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
00210   }
00211   else if (DMAy_Channelx == DMA2_Channel4)
00212   {
00213     /* Reset interrupt pending bits for DMA2 Channel4 */
00214     DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
00215   }
00216   else
00217   {
00218     if (DMAy_Channelx == DMA2_Channel5)
00219     {
00220       /* Reset interrupt pending bits for DMA2 Channel5 */
00221       DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
00222     }
00223   }
00224 }
00225
00226 /**
00227   * @brief  Initializes the DMAy Channelx according to the specified
00228   *         parameters in the DMA_InitStruct.
00229   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00230   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00231   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
00232   *         contains the configuration information for the specified DMA Channel.
00233   * @retval None
00234   */
00235 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
00236 {
00237   uint32_t tmpreg = 0;
00238
00239   /* Check the parameters */
00240   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00241   assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
00242   assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
00243   assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
00244   assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
00245   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
00246   assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
00247   assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
00248   assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
00249   assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
00250
00251 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
00252   /* Get the DMAy_Channelx CCR value */
00253   tmpreg = DMAy_Channelx->CCR;
00254   /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00255   tmpreg &= CCR_CLEAR_MASK;
00256   /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
00257   /* Set DIR bit according to DMA_DIR value */
00258   /* Set CIRC bit according to DMA_Mode value */
00259   /* Set PINC bit according to DMA_PeripheralInc value */
00260   /* Set MINC bit according to DMA_MemoryInc value */
00261   /* Set PSIZE bits according to DMA_PeripheralDataSize value */
00262   /* Set MSIZE bits according to DMA_MemoryDataSize value */
00263   /* Set PL bits according to DMA_Priority value */
00264   /* Set the MEM2MEM bit according to DMA_M2M value */
00265   tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00266             DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
00267             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
00268             DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
00269
00270   /* Write to DMAy Channelx CCR */
00271   DMAy_Channelx->CCR = tmpreg;
00272
00273 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00274   /* Write to DMAy Channelx CNDTR */
00275   DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00276
00277 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
00278   /* Write to DMAy Channelx CPAR */
00279   DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
00280
00281 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
00282   /* Write to DMAy Channelx CMAR */
00283   DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
00284 }
00285
00286 /**
00287   * @brief  Fills each DMA_InitStruct member with its default value.
00288   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
00289   *         be initialized.
00290   * @retval None
00291   */
00292 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
00293 {
00294 /*-------------- Reset DMA init structure parameters values ------------------*/
00295   /* Initialize the DMA_PeripheralBaseAddr member */
00296   DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
00297   /* Initialize the DMA_MemoryBaseAddr member */
00298   DMA_InitStruct->DMA_MemoryBaseAddr = 0;
00299   /* Initialize the DMA_DIR member */
00300   DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
00301   /* Initialize the DMA_BufferSize member */
00302   DMA_InitStruct->DMA_BufferSize = 0;
00303   /* Initialize the DMA_PeripheralInc member */
00304   DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00305   /* Initialize the DMA_MemoryInc member */
00306   DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00307   /* Initialize the DMA_PeripheralDataSize member */
00308   DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00309   /* Initialize the DMA_MemoryDataSize member */
00310   DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00311   /* Initialize the DMA_Mode member */
00312   DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
00313   /* Initialize the DMA_Priority member */
00314   DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
00315   /* Initialize the DMA_M2M member */
00316   DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
00317 }
00318
00319 /**
00320   * @brief  Enables or disables the specified DMAy Channelx.
00321   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00322   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00323   * @param  NewState: new state of the DMAy Channelx.
00324   *         This parameter can be: ENABLE or DISABLE.
00325   * @retval None
00326   */
00327 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
00328 {
00329   /* Check the parameters */
00330   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00331   assert_param(IS_FUNCTIONAL_STATE(NewState));
00332
00333   if (NewState != DISABLE)
00334   {
00335     /* Enable the selected DMAy Channelx */
00336     DMAy_Channelx->CCR |= DMA_CCR1_EN;
00337   }
00338   else
00339   {
00340     /* Disable the selected DMAy Channelx */
00341     DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00342   }
00343 }
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup DMA_Group2 Data Counter functions
00350  *  @brief   Data Counter functions
00351  *
00352 @verbatim
00353  ===============================================================================
00354                       ##### Data Counter functions #####
00355  ===============================================================================
00356     [..] This subsection provides function allowing to configure and read the buffer
00357          size (number of data to be transferred).The DMA data counter can be written
00358          only when the DMA channel is disabled (ie. after transfer complete event).
00359     [..] The following function can be used to write the Channel data counter value:
00360          (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
00361              DataNumber).
00362     -@- It is advised to use this function rather than DMA_Init() in situations
00363         where only the Data buffer needs to be reloaded.
00364     [..] The DMA data counter can be read to indicate the number of remaining transfers
00365          for the relative DMA channel. This counter is decremented at the end of each
00366          data transfer and when the transfer is complete:
00367          (+) If Normal mode is selected: the counter is set to 0.
00368          (+) If Circular mode is selected: the counter is reloaded with the initial
00369          value(configured before enabling the DMA channel).
00370     [..] The following function can be used to read the Channel data counter value:
00371          (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
00372
00373 @endverbatim
00374   * @{
00375   */
00376
00377 /**
00378   * @brief  Sets the number of data units in the current DMAy Channelx transfer.
00379   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00380   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00381   * @param  DataNumber: The number of data units in the current DMAy Channelx
00382   *         transfer.
00383   * @note   This function can only be used when the DMAy_Channelx is disabled.
00384   * @retval None.
00385   */
00386 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00390
00391 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00392   /* Write to DMAy Channelx CNDTR */
00393   DMAy_Channelx->CNDTR = DataNumber;
00394 }
00395
00396 /**
00397   * @brief  Returns the number of remaining data units in the current
00398   *         DMAy Channelx transfer.
00399   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00400   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00401   * @retval The number of remaining data units in the current DMAy Channelx
00402   *         transfer.
00403   */
00404 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
00405 {
00406   /* Check the parameters */
00407   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00408   /* Return the number of remaining data units for DMAy Channelx */
00409   return ((uint16_t)(DMAy_Channelx->CNDTR));
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup DMA_Group3 Interrupts and flags management functions
00417  *  @brief   Interrupts and flags management functions
00418  *
00419 @verbatim
00420  ===============================================================================
00421           ##### Interrupts and flags management functions #####
00422  ===============================================================================
00423     [..] This subsection provides functions allowing to configure the DMA Interrupts
00424          sources and check or clear the flags or pending bits status.
00425          The user should identify which mode will be used in his application to manage
00426          the DMA controller events: Polling mode or Interrupt mode.
00427   *** Polling Mode ***
00428   ====================
00429     [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
00430          number  x : DMA channel number ).
00431          (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
00432          (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
00433          (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
00434          (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
00435              above occurred.
00436     -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
00437         same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
00438     [..]In this Mode it is advised to use the following functions:
00439         (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
00440         (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
00441
00442   *** Interrupt Mode ***
00443   ======================
00444     [..] Each DMA channel can be managed through 4 Interrupts:
00445     (+) Interrupt Source
00446        (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
00447             event.
00448        (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
00449             event.
00450        (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
00451        (##) DMA_IT_GL : to indicate that at least one of the interrupts described
00452             above occurred.
00453     -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
00454         the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
00455     [..]In this Mode it is advised to use the following functions:
00456         (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
00457             FunctionalState NewState);
00458         (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
00459         (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
00460
00461 @endverbatim
00462   * @{
00463   */
00464
00465 /**
00466   * @brief  Enables or disables the specified DMAy Channelx interrupts.
00467   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
00468   *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00469   * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
00470   *         or disabled.
00471   *   This parameter can be any combination of the following values:
00472   *     @arg DMA_IT_TC: Transfer complete interrupt mask
00473   *     @arg DMA_IT_HT: Half transfer interrupt mask
00474   *     @arg DMA_IT_TE: Transfer error interrupt mask
00475   * @param  NewState: new state of the specified DMA interrupts.
00476   *         This parameter can be: ENABLE or DISABLE.
00477   * @retval None
00478   */
00479 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
00480 {
00481   /* Check the parameters */
00482   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00483   assert_param(IS_DMA_CONFIG_IT(DMA_IT));
00484   assert_param(IS_FUNCTIONAL_STATE(NewState));
00485
00486   if (NewState != DISABLE)
00487   {
00488     /* Enable the selected DMA interrupts */
00489     DMAy_Channelx->CCR |= DMA_IT;
00490   }
00491   else
00492   {
00493     /* Disable the selected DMA interrupts */
00494     DMAy_Channelx->CCR &= ~DMA_IT;
00495   }
00496 }
00497
00498 /**
00499   * @brief  Checks whether the specified DMAy Channelx flag is set or not.
00500   * @param  DMAy_FLAG: specifies the flag to check.
00501   *   This parameter can be one of the following values:
00502   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00503   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00504   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00505   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00506   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00507   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00508   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00509   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00510   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00511   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00512   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00513   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00514   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00515   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00516   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00517   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00518   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00519   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00520   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00521   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00522   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00523   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00524   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00525   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00526   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00527   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00528   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00529   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00530   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00531   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00532   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00533   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00534   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00535   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00536   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00537   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00538   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00539   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00540   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00541   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00542   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00543   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00544   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00545   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00546   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00547   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00548   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00549   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00550   *
00551   * @note
00552   *    The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
00553   *    relative to the same channel is set (Transfer Complete, Half-transfer
00554   *    Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
00555   *    DMAy_FLAG_TEx).
00556   *
00557   * @retval The new state of DMAy_FLAG (SET or RESET).
00558   */
00559 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
00560 {
00561   FlagStatus bitstatus = RESET;
00562   uint32_t tmpreg = 0;
00563
00564   /* Check the parameters */
00565   assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
00566
00567   /* Calculate the used DMAy */
00568   if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
00569   {
00570     /* Get DMA1 ISR register value */
00571     tmpreg = DMA1->ISR;
00572   }
00573   else
00574   {
00575     /* Get DMA2 ISR register value */
00576     tmpreg = DMA2->ISR;
00577   }
00578
00579   /* Check the status of the specified DMAy flag */
00580   if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
00581   {
00582     /* DMAy_FLAG is set */
00583     bitstatus = SET;
00584   }
00585   else
00586   {
00587     /* DMAy_FLAG is reset */
00588     bitstatus = RESET;
00589   }
00590
00591   /* Return the DMAy_FLAG status */
00592   return  bitstatus;
00593 }
00594
00595 /**
00596   * @brief  Clears the DMAy Channelx's pending flags.
00597   * @param  DMAy_FLAG: specifies the flag to clear.
00598   *   This parameter can be any combination (for the same DMA) of the following values:
00599   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00600   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00601   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00602   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00603   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00604   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00605   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00606   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00607   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00608   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00609   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00610   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00611   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00612   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00613   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00614   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00615   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00616   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00617   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00618   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00619   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00620   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00621   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00622   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00623   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00624   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00625   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00626   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00627   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00628   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00629   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00630   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00631   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00632   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00633   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00634   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00635   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00636   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00637   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00638   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00639   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00640   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00641   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00642   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00643   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00644   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00645   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00646   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00647   *
00648   * @note
00649   *    Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
00650   *    relative to the same channel (Transfer Complete, Half-transfer Complete and
00651   *    Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
00652   *
00653   * @retval None
00654   */
00655 void DMA_ClearFlag(uint32_t DMAy_FLAG)
00656 {
00657   /* Check the parameters */
00658   assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
00659
00660   if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
00661   {
00662     /* Clear the selected DMAy flags */
00663     DMA1->IFCR = DMAy_FLAG;
00664   }
00665   else
00666   {
00667     /* Clear the selected DMAy flags */
00668     DMA2->IFCR = DMAy_FLAG;
00669   }
00670 }
00671
00672 /**
00673   * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
00674   * @param  DMAy_IT: specifies the DMAy interrupt source to check.
00675   *   This parameter can be one of the following values:
00676   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00677   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00678   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00679   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00680   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00681   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00682   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00683   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00684   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00685   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00686   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00687   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00688   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00689   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00690   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00691   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00692   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00693   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00694   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00695   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00696   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00697   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00698   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00699   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00700   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00701   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00702   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00703   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00704   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00705   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00706   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00707   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00708   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00709   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00710   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00711   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00712   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00713   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00714   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00715   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00716   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00717   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00718   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00719   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00720   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00721   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00722   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00723   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00724   *
00725   * @note
00726   *    The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
00727   *    interrupts relative to the same channel is set (Transfer Complete,
00728   *    Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
00729   *    DMAy_IT_HTx or DMAy_IT_TEx).
00730   *
00731   * @retval The new state of DMAy_IT (SET or RESET).
00732   */
00733 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
00734 {
00735   ITStatus bitstatus = RESET;
00736   uint32_t tmpreg = 0;
00737
00738   /* Check the parameters */
00739   assert_param(IS_DMA_GET_IT(DMAy_IT));
00740
00741   /* Calculate the used DMAy */
00742   if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
00743   {
00744     /* Get DMA1 ISR register value */
00745     tmpreg = DMA1->ISR;
00746   }
00747   else
00748   {
00749     /* Get DMA2 ISR register value */
00750     tmpreg = DMA2->ISR;
00751   }
00752
00753   /* Check the status of the specified DMAy interrupt */
00754   if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
00755   {
00756     /* DMAy_IT is set */
00757     bitstatus = SET;
00758   }
00759   else
00760   {
00761     /* DMAy_IT is reset */
00762     bitstatus = RESET;
00763   }
00764   /* Return the DMAy_IT status */
00765   return  bitstatus;
00766 }
00767
00768 /**
00769   * @brief  Clears the DMAy Channelx's interrupt pending bits.
00770   * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
00771   *   This parameter can be any combination (for the same DMA) of the following values:
00772   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00773   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00774   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00775   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00776   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00777   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00778   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00779   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00780   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00781   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00782   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00783   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00784   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00785   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00786   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00787   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00788   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00789   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00790   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00791   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00792   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00793   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00794   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00795   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00796   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00797   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00798   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00799   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00800   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00801   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00802   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00803   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00804   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00805   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00806   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00807   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00808   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00809   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00810   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00811   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00812   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00813   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00814   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00815   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00816   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00817   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00818   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00819   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00820   *
00821   * @note
00822   *    Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
00823   *    interrupts relative to the same channel (Transfer Complete, Half-transfer
00824   *    Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
00825   *    DMAy_IT_TEx).
00826   *
00827   * @retval None
00828   */
00829 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
00830 {
00831   /* Check the parameters */
00832   assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
00833
00834   /* Calculate the used DMAy */
00835   if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
00836   {
00837     /* Clear the selected DMAy interrupt pending bits */
00838     DMA1->IFCR = DMAy_IT;
00839   }
00840   else
00841   {
00842     /* Clear the selected DMAy interrupt pending bits */
00843     DMA2->IFCR = DMAy_IT;
00844   }
00845 }
00846
00847 /**
00848   * @}
00849   */
00850
00851 /**
00852   * @}
00853   */
00854
00855 /**
00856   * @}
00857   */
00858
00859 /**
00860   * @}
00861   */
00862
00863 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_dma.h Source File

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stm32l1xx_dma.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the DMA firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_DMA_H
00028 #define __STM32L1xx_DMA_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup DMA
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  DMA Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
00054
00055   uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
00056
00057   uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
00058                                         This parameter can be a value of @ref DMA_data_transfer_direction */
00059
00060   uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel.
00061                                         The data unit is equal to the configuration set in DMA_PeripheralDataSize
00062                                         or DMA_MemoryDataSize members depending in the transfer direction. */
00063
00064   uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
00065                                         This parameter can be a value of @ref DMA_peripheral_incremented_mode */
00066
00067   uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
00068                                         This parameter can be a value of @ref DMA_memory_incremented_mode */
00069
00070   uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
00071                                         This parameter can be a value of @ref DMA_peripheral_data_size */
00072
00073   uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
00074                                         This parameter can be a value of @ref DMA_memory_data_size */
00075
00076   uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
00077                                         This parameter can be a value of @ref DMA_circular_normal_mode
00078                                         @note: The circular buffer mode cannot be used if the memory-to-memory
00079                                               data transfer is configured on the selected Channel */
00080
00081   uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
00082                                         This parameter can be a value of @ref DMA_priority_level */
00083
00084   uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
00085                                         This parameter can be a value of @ref DMA_memory_to_memory */
00086 }DMA_InitTypeDef;
00087
00088 /* Exported constants --------------------------------------------------------*/
00089
00090 /** @defgroup DMA_Exported_Constants
00091   * @{
00092   */
00093
00094 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
00095                                    ((PERIPH) == DMA1_Channel2) || \
00096                                    ((PERIPH) == DMA1_Channel3) || \
00097                                    ((PERIPH) == DMA1_Channel4) || \
00098                                    ((PERIPH) == DMA1_Channel5) || \
00099                                    ((PERIPH) == DMA1_Channel6) || \
00100                                    ((PERIPH) == DMA1_Channel7) || \
00101                                    ((PERIPH) == DMA2_Channel1) || \
00102                                    ((PERIPH) == DMA2_Channel2) || \
00103                                    ((PERIPH) == DMA2_Channel3) || \
00104                                    ((PERIPH) == DMA2_Channel4) || \
00105                                    ((PERIPH) == DMA2_Channel5))
00106
00107 /** @defgroup DMA_data_transfer_direction
00108   * @{
00109   */
00110
00111 #define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
00112 #define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
00113 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
00114                          ((DIR) == DMA_DIR_PeripheralSRC))
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup DMA_peripheral_incremented_mode
00120   * @{
00121   */
00122
00123 #define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
00124 #define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
00125 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
00126                                             ((STATE) == DMA_PeripheralInc_Disable))
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup DMA_memory_incremented_mode
00132   * @{
00133   */
00134
00135 #define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
00136 #define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
00137 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
00138                                         ((STATE) == DMA_MemoryInc_Disable))
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup DMA_peripheral_data_size
00144   * @{
00145   */
00146
00147 #define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
00148 #define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
00149 #define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
00150 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
00151                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
00152                                            ((SIZE) == DMA_PeripheralDataSize_Word))
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup DMA_memory_data_size
00158   * @{
00159   */
00160
00161 #define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
00162 #define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
00163 #define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
00164 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
00165                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
00166                                        ((SIZE) == DMA_MemoryDataSize_Word))
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup DMA_circular_normal_mode
00172   * @{
00173   */
00174
00175 #define DMA_Mode_Circular                  ((uint32_t)0x00000020)
00176 #define DMA_Mode_Normal                    ((uint32_t)0x00000000)
00177 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup DMA_priority_level
00183   * @{
00184   */
00185
00186 #define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
00187 #define DMA_Priority_High                  ((uint32_t)0x00002000)
00188 #define DMA_Priority_Medium                ((uint32_t)0x00001000)
00189 #define DMA_Priority_Low                   ((uint32_t)0x00000000)
00190 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
00191                                    ((PRIORITY) == DMA_Priority_High) || \
00192                                    ((PRIORITY) == DMA_Priority_Medium) || \
00193                                    ((PRIORITY) == DMA_Priority_Low))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup DMA_memory_to_memory
00199   * @{
00200   */
00201
00202 #define DMA_M2M_Enable                     ((uint32_t)0x00004000)
00203 #define DMA_M2M_Disable                    ((uint32_t)0x00000000)
00204 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup DMA_interrupts_definition
00211   * @{
00212   */
00213
00214 #define DMA_IT_TC                          ((uint32_t)0x00000002)
00215 #define DMA_IT_HT                          ((uint32_t)0x00000004)
00216 #define DMA_IT_TE                          ((uint32_t)0x00000008)
00217 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
00218
00219 #define DMA1_IT_GL1                        ((uint32_t)0x00000001)
00220 #define DMA1_IT_TC1                        ((uint32_t)0x00000002)
00221 #define DMA1_IT_HT1                        ((uint32_t)0x00000004)
00222 #define DMA1_IT_TE1                        ((uint32_t)0x00000008)
00223 #define DMA1_IT_GL2                        ((uint32_t)0x00000010)
00224 #define DMA1_IT_TC2                        ((uint32_t)0x00000020)
00225 #define DMA1_IT_HT2                        ((uint32_t)0x00000040)
00226 #define DMA1_IT_TE2                        ((uint32_t)0x00000080)
00227 #define DMA1_IT_GL3                        ((uint32_t)0x00000100)
00228 #define DMA1_IT_TC3                        ((uint32_t)0x00000200)
00229 #define DMA1_IT_HT3                        ((uint32_t)0x00000400)
00230 #define DMA1_IT_TE3                        ((uint32_t)0x00000800)
00231 #define DMA1_IT_GL4                        ((uint32_t)0x00001000)
00232 #define DMA1_IT_TC4                        ((uint32_t)0x00002000)
00233 #define DMA1_IT_HT4                        ((uint32_t)0x00004000)
00234 #define DMA1_IT_TE4                        ((uint32_t)0x00008000)
00235 #define DMA1_IT_GL5                        ((uint32_t)0x00010000)
00236 #define DMA1_IT_TC5                        ((uint32_t)0x00020000)
00237 #define DMA1_IT_HT5                        ((uint32_t)0x00040000)
00238 #define DMA1_IT_TE5                        ((uint32_t)0x00080000)
00239 #define DMA1_IT_GL6                        ((uint32_t)0x00100000)
00240 #define DMA1_IT_TC6                        ((uint32_t)0x00200000)
00241 #define DMA1_IT_HT6                        ((uint32_t)0x00400000)
00242 #define DMA1_IT_TE6                        ((uint32_t)0x00800000)
00243 #define DMA1_IT_GL7                        ((uint32_t)0x01000000)
00244 #define DMA1_IT_TC7                        ((uint32_t)0x02000000)
00245 #define DMA1_IT_HT7                        ((uint32_t)0x04000000)
00246 #define DMA1_IT_TE7                        ((uint32_t)0x08000000)
00247
00248 #define DMA2_IT_GL1                        ((uint32_t)0x10000001)
00249 #define DMA2_IT_TC1                        ((uint32_t)0x10000002)
00250 #define DMA2_IT_HT1                        ((uint32_t)0x10000004)
00251 #define DMA2_IT_TE1                        ((uint32_t)0x10000008)
00252 #define DMA2_IT_GL2                        ((uint32_t)0x10000010)
00253 #define DMA2_IT_TC2                        ((uint32_t)0x10000020)
00254 #define DMA2_IT_HT2                        ((uint32_t)0x10000040)
00255 #define DMA2_IT_TE2                        ((uint32_t)0x10000080)
00256 #define DMA2_IT_GL3                        ((uint32_t)0x10000100)
00257 #define DMA2_IT_TC3                        ((uint32_t)0x10000200)
00258 #define DMA2_IT_HT3                        ((uint32_t)0x10000400)
00259 #define DMA2_IT_TE3                        ((uint32_t)0x10000800)
00260 #define DMA2_IT_GL4                        ((uint32_t)0x10001000)
00261 #define DMA2_IT_TC4                        ((uint32_t)0x10002000)
00262 #define DMA2_IT_HT4                        ((uint32_t)0x10004000)
00263 #define DMA2_IT_TE4                        ((uint32_t)0x10008000)
00264 #define DMA2_IT_GL5                        ((uint32_t)0x10010000)
00265 #define DMA2_IT_TC5                        ((uint32_t)0x10020000)
00266 #define DMA2_IT_HT5                        ((uint32_t)0x10040000)
00267 #define DMA2_IT_TE5                        ((uint32_t)0x10080000)
00268
00269 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
00270
00271 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
00272                            ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
00273                            ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
00274                            ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
00275                            ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
00276                            ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
00277                            ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
00278                            ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
00279                            ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
00280                            ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
00281                            ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
00282                            ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
00283                            ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
00284                            ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
00285                            ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
00286                            ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
00287                            ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
00288                            ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
00289                            ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
00290                            ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
00291                            ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
00292                            ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
00293                            ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
00294                            ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup DMA_flags_definition
00300   * @{
00301   */
00302 #define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
00303 #define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
00304 #define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
00305 #define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
00306 #define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
00307 #define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
00308 #define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
00309 #define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
00310 #define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
00311 #define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
00312 #define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
00313 #define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
00314 #define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
00315 #define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
00316 #define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
00317 #define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
00318 #define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
00319 #define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
00320 #define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
00321 #define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
00322 #define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
00323 #define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
00324 #define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
00325 #define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
00326 #define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
00327 #define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
00328 #define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
00329 #define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
00330
00331 #define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
00332 #define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
00333 #define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
00334 #define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
00335 #define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
00336 #define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
00337 #define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
00338 #define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
00339 #define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
00340 #define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
00341 #define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
00342 #define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
00343 #define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
00344 #define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
00345 #define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
00346 #define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
00347 #define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
00348 #define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
00349 #define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
00350 #define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
00351
00352 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
00353
00354 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
00355                                ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
00356                                ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
00357                                ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
00358                                ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
00359                                ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
00360                                ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
00361                                ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
00362                                ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
00363                                ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
00364                                ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
00365                                ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
00366                                ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
00367                                ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
00368                                ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
00369                                ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
00370                                ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
00371                                ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
00372                                ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
00373                                ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
00374                                ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
00375                                ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
00376                                ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
00377                                ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup DMA_Buffer_Size
00383   * @{
00384   */
00385
00386 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00387
00388 /**
00389   * @}
00390   */
00391
00392 /**
00393   * @}
00394   */
00395
00396 /* Exported macro ------------------------------------------------------------*/
00397 /* Exported functions ------------------------------------------------------- */
00398
00399 /*  Function used to set the DMA configuration to the default reset state *****/
00400 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
00401
00402 /* Initialization and Configuration functions *********************************/
00403 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
00404 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
00405 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
00406
00407 /* Data Counter functions *****************************************************/
00408 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
00409 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
00410
00411 /* Interrupts and flags management functions **********************************/
00412 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00413 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
00414 void DMA_ClearFlag(uint32_t DMAy_FLAG);
00415 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
00416 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
00417
00418 #ifdef __cplusplus
00419 }
00420 #endif
00421
00422 #endif /*__STM32L1xx_DMA_H */
00423
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_exti.c Source File

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  • src

stm32l1xx_exti.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_exti.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the EXTI peripheral:
00009   *           + Initialization and Configuration
00010   *           + Interrupts and flags management
00011   *
00012   *  @verbatim
00013   ==============================================================================
00014                             ##### EXTI features #####
00015   ==============================================================================
00016     [..] External interrupt/event lines are mapped as following:
00017          (#) All available GPIO pins are connected to the 16 external
00018              interrupt/event lines from EXTI0 to EXTI15.
00019          (#) EXTI line 16 is connected to the PVD output.
00020          (#) EXTI line 17 is connected to the RTC Alarm event.
00021          (#) EXTI line 18 is connected to the USB Device FS wakeup event.
00022          (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
00023          (#) EXTI line 20 is connected to the RTC Wakeup event.
00024          (#) EXTI line 21 is connected to the Comparator 1 wakeup event.
00025          (#) EXTI line 22 is connected to the Comparator 2 wakeup event.
00026          (#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.
00027
00028
00029                        ##### How to use this driver #####
00030   ==============================================================================
00031     [..] In order to use an I/O pin as an external interrupt source, follow
00032          steps below:
00033     (#) Configure the I/O in input mode using GPIO_Init()
00034     (#) Select the input source pin for the EXTI line using
00035         SYSCFG_EXTILineConfig()
00036     (#) Select the mode(interrupt, event) and configure the trigger
00037         selection (Rising, falling or both) using EXTI_Init()
00038     (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
00039     [..]
00040         (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
00041       registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00042
00043   *  @endverbatim
00044   *
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00049   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00050   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00051   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00052   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00053   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00054   *
00055   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00056   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00057   *
00058   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00059   ******************************************************************************
00060   */
00061
00062 /* Includes ------------------------------------------------------------------*/
00063 #include "stm32l1xx_exti.h"
00064
00065 /** @addtogroup STM32L1xx_StdPeriph_Driver
00066   * @{
00067   */
00068
00069 /** @defgroup EXTI
00070   * @brief EXTI driver modules
00071   * @{
00072   */
00073
00074 /* Private typedef -----------------------------------------------------------*/
00075 /* Private define ------------------------------------------------------------*/
00076 #define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
00077
00078 /* Private macro -------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private function prototypes -----------------------------------------------*/
00081 /* Private functions ---------------------------------------------------------*/
00082
00083 /** @defgroup EXTI_Private_Functions
00084   * @{
00085   */
00086
00087 /** @defgroup EXTI_Group1 Initialization and Configuration functions
00088  *  @brief   Initialization and Configuration functions
00089  *
00090 @verbatim
00091   ==============================================================================
00092             ##### Initialization and Configuration functions #####
00093   ==============================================================================
00094
00095 @endverbatim
00096   * @{
00097   */
00098
00099 /**
00100   * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
00101   * @param  None
00102   * @retval None
00103   */
00104 void EXTI_DeInit(void)
00105 {
00106   EXTI->IMR = 0x00000000;
00107   EXTI->EMR = 0x00000000;
00108   EXTI->RTSR = 0x00000000;
00109   EXTI->FTSR = 0x00000000;
00110   EXTI->PR = 0x00FFFFFF;
00111 }
00112
00113 /**
00114   * @brief  Initializes the EXTI peripheral according to the specified
00115   *   parameters in the EXTI_InitStruct.
00116   *    EXTI_Line specifies the EXTI line (EXTI0....EXTI23).
00117   *    EXTI_Mode specifies which EXTI line is used as interrupt or an event.
00118   *    EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
00119   *                 pending bit will be set.
00120   *    EXTI_LineCmd controls (Enable/Disable) the EXTI line.
00121   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
00122   *   that contains the configuration information for the EXTI peripheral.
00123   * @retval None
00124   */
00125 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
00126 {
00127   uint32_t tmp = 0;
00128
00129   /* Check the parameters */
00130   assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
00131   assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
00132   assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
00133   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
00134
00135   tmp = (uint32_t)EXTI_BASE;
00136
00137   if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
00138   {
00139     /* Clear EXTI line configuration */
00140     EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
00141     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
00142
00143     tmp += EXTI_InitStruct->EXTI_Mode;
00144
00145     *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
00146
00147     /* Clear Rising Falling edge configuration */
00148     EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
00149     EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
00150
00151     /* Select the trigger for the selected external interrupts */
00152     if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
00153     {
00154       /* Rising Falling edge */
00155       EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
00156       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
00157     }
00158     else
00159     {
00160       tmp = (uint32_t)EXTI_BASE;
00161       tmp += EXTI_InitStruct->EXTI_Trigger;
00162
00163       *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
00164     }
00165   }
00166   else
00167   {
00168     tmp += EXTI_InitStruct->EXTI_Mode;
00169
00170     /* Disable the selected external lines */
00171     *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
00172   }
00173 }
00174
00175 /**
00176   * @brief  Fills each EXTI_InitStruct member with its reset value.
00177   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
00178   *   be initialized.
00179   * @retval None
00180   */
00181 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
00182 {
00183   EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
00184   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
00185   EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
00186   EXTI_InitStruct->EXTI_LineCmd = DISABLE;
00187 }
00188
00189 /**
00190   * @brief  Generates a Software interrupt on selected EXTI line.
00191   * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
00192   *         will be generated.
00193   *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
00194   * @retval None
00195   */
00196 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
00197 {
00198   /* Check the parameters */
00199   assert_param(IS_EXTI_LINE(EXTI_Line));
00200
00201   EXTI->SWIER |= EXTI_Line;
00202 }
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup EXTI_Group2 Interrupts and flags management functions
00209  *  @brief   Interrupts and flags management functions
00210  *
00211 @verbatim
00212   ==============================================================================
00213              ##### Interrupts and flags management functions #####
00214   ==============================================================================
00215
00216 @endverbatim
00217   * @{
00218   */
00219
00220 /**
00221   * @brief  Checks whether the specified EXTI line flag is set or not.
00222   * @param  EXTI_Line: specifies the EXTI line flag to check.
00223   *   This parameter can be:
00224   *   EXTI_Linex: External interrupt line x where x(0..23).
00225   * @retval The new state of EXTI_Line (SET or RESET).
00226   */
00227 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
00228 {
00229   FlagStatus bitstatus = RESET;
00230   /* Check the parameters */
00231   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
00232
00233   if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
00234   {
00235     bitstatus = SET;
00236   }
00237   else
00238   {
00239     bitstatus = RESET;
00240   }
00241   return bitstatus;
00242 }
00243
00244 /**
00245   * @brief  Clears the EXTI's line pending flags.
00246   * @param  EXTI_Line: specifies the EXTI lines flags to clear.
00247   *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
00248   * @retval None
00249   */
00250 void EXTI_ClearFlag(uint32_t EXTI_Line)
00251 {
00252   /* Check the parameters */
00253   assert_param(IS_EXTI_LINE(EXTI_Line));
00254
00255   EXTI->PR = EXTI_Line;
00256 }
00257
00258 /**
00259   * @brief  Checks whether the specified EXTI line is asserted or not.
00260   * @param  EXTI_Line: specifies the EXTI line to check.
00261   *   This parameter can be:
00262   *   EXTI_Linex: External interrupt line x where x(0..23).
00263   * @retval The new state of EXTI_Line (SET or RESET).
00264   */
00265 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
00266 {
00267   ITStatus bitstatus = RESET;
00268   uint32_t enablestatus = 0;
00269   /* Check the parameters */
00270   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
00271
00272   enablestatus =  EXTI->IMR & EXTI_Line;
00273   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
00274   {
00275     bitstatus = SET;
00276   }
00277   else
00278   {
00279     bitstatus = RESET;
00280   }
00281   return bitstatus;
00282 }
00283
00284 /**
00285   * @brief  Clears the EXTI's line pending bits.
00286   * @param  EXTI_Line: specifies the EXTI lines to clear.
00287   *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
00288   * @retval None
00289   */
00290 void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
00291 {
00292   /* Check the parameters */
00293   assert_param(IS_EXTI_LINE(EXTI_Line));
00294
00295   EXTI->PR = EXTI_Line;
00296 }
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_exti.h Source File

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stm32l1xx_exti.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_exti.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the EXTI firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_EXTI_H
00028 #define __STM32L1xx_EXTI_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup EXTI
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  EXTI mode enumeration
00049   */
00050
00051 typedef enum
00052 {
00053   EXTI_Mode_Interrupt = 0x00,
00054   EXTI_Mode_Event = 0x04
00055 }EXTIMode_TypeDef;
00056
00057 #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
00058
00059 /**
00060   * @brief  EXTI Trigger enumeration
00061   */
00062
00063 typedef enum
00064 {
00065   EXTI_Trigger_Rising = 0x08,
00066   EXTI_Trigger_Falling = 0x0C,
00067   EXTI_Trigger_Rising_Falling = 0x10
00068 }EXTITrigger_TypeDef;
00069
00070 #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
00071                                   ((TRIGGER) == EXTI_Trigger_Falling) || \
00072                                   ((TRIGGER) == EXTI_Trigger_Rising_Falling))
00073 /**
00074   * @brief  EXTI Init Structure definition
00075   */
00076
00077 typedef struct
00078 {
00079   uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
00080                                          This parameter can be any combination of @ref EXTI_Lines */
00081
00082   EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
00083                                          This parameter can be a value of @ref EXTIMode_TypeDef */
00084
00085   EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
00086                                          This parameter can be a value of @ref EXTITrigger_TypeDef */
00087
00088   FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
00089                                          This parameter can be set either to ENABLE or DISABLE */
00090 }EXTI_InitTypeDef;
00091
00092 /* Exported constants --------------------------------------------------------*/
00093
00094 /** @defgroup EXTI_Exported_Constants
00095   * @{
00096   */
00097
00098 /** @defgroup EXTI_Lines
00099   * @{
00100   */
00101
00102 #define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0 */
00103 #define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1 */
00104 #define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2 */
00105 #define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3 */
00106 #define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4 */
00107 #define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5 */
00108 #define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6 */
00109 #define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7 */
00110 #define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8 */
00111 #define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9 */
00112 #define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
00113 #define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
00114 #define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
00115 #define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
00116 #define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
00117 #define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
00118 #define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16
00119                                                       Connected to the PVD Output */
00120 #define EXTI_Line17      ((uint32_t)0x00020000)  /*!< External interrupt line 17
00121                                                       Connected to the RTC Alarm
00122                                                       event */
00123 #define EXTI_Line18      ((uint32_t)0x00040000)  /*!< External interrupt line 18
00124                                                       Connected to the USB Device
00125                                                       FS Wakeup from suspend event */
00126 #define EXTI_Line19      ((uint32_t)0x00080000)  /*!< External interrupt line 19
00127                                                       Connected to the RTC Tamper
00128                                                       and Time Stamp events */
00129 #define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20
00130                                                       Connected to the RTC Wakeup
00131                                                       event */
00132 #define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21
00133                                                       Connected to the Comparator 1
00134                                                       event */
00135
00136 #define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22
00137                                                       Connected to the Comparator 2
00138                                                       event */
00139
00140 #define EXTI_Line23      ((uint32_t)0x00800000)  /*!< External interrupt line 23
00141                                                       Comparator channel acquisition event */
00142
00143 #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
00144
00145 #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
00146                                 ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
00147                                 ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
00148                                 ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
00149                                 ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
00150                                 ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
00151                                 ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
00152                                 ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
00153                                 ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
00154                                 ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
00155                                 ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
00156                                 ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
00157
00158 /**
00159   * @}
00160   */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported macro ------------------------------------------------------------*/
00167 /* Exported functions ------------------------------------------------------- */
00168 /*  Function used to set the EXTI configuration to the default reset state *****/
00169 void EXTI_DeInit(void);
00170
00171 /* Initialization and Configuration functions *********************************/
00172 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
00173 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
00174 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
00175
00176 /* Interrupts and flags management functions **********************************/
00177 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
00178 void EXTI_ClearFlag(uint32_t EXTI_Line);
00179 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
00180 void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
00181
00182 #ifdef __cplusplus
00183 }
00184 #endif
00185
00186 #endif /* __STM32L1xx_EXTI_H */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /**
00193   * @}
00194   */
00195
00196 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash.c Source File

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stm32l1xx_flash.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides all the Flash firmware functions. These functions
00008   *          can be executed from Internal FLASH or Internal SRAM memories.
00009   *          The functions that should be called from SRAM are defined inside
00010   *          the "stm32l1xx_flash_ramfunc.c" file.
00011   *          This file provides firmware functions to manage the following
00012   *          functionalities of the FLASH peripheral:
00013   *            + FLASH Interface configuration
00014   *            + FLASH Memory Programming
00015   *            + DATA EEPROM Programming
00016   *            + Option Bytes Programming
00017   *            + Interrupts and flags management
00018   *
00019   *  @verbatim
00020
00021   ==============================================================================
00022                         ##### How to use this driver #####
00023   ==============================================================================
00024     [..] This driver provides functions to configure and program the Flash
00025          memory of all STM32L1xx devices.
00026     [..] These functions are split in 5 groups:
00027          (#) FLASH Interface configuration functions: this group includes
00028              the management of following features:
00029              (++) Set the latency.
00030              (++) Enable/Disable the prefetch buffer.
00031              (++) Enable/Disable the 64 bit Read Access.
00032              (++) Enable/Disable the RUN PowerDown mode.
00033              (++) Enable/Disable the SLEEP PowerDown mode.
00034
00035          (#) FLASH Memory Programming functions: this group includes all
00036              needed functions to erase and program the main memory:
00037              (++) Lock and Unlock the Flash interface.
00038              (++) Erase function: Erase Page.
00039              (++) Program functions: Fast Word and Half Page(should be
00040                   executed from internal SRAM).
00041
00042          (#) DATA EEPROM Programming functions: this group includes all
00043              needed functions to erase and program the DATA EEPROM memory:
00044              (++) Lock and Unlock the DATA EEPROM interface.
00045              (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
00046              (++) Double Word (should be executed from internal SRAM).
00047              (++) Program functions: Fast Program Byte, Fast Program Half-Word,
00048                   FastProgramWord, Program Byte, Program Half-Word,
00049                   Program Word and Program Double-Word (should be executed
00050                   from internal SRAM).
00051
00052          (#) FLASH Option Bytes Programming functions: this group includes
00053              all needed functions to:
00054              (++) Lock and Unlock the Flash Option bytes.
00055              (++) Set/Reset the write protection.
00056              (++) Set the Read protection Level.
00057              (++) Set the BOR level.
00058              (++) rogram the user option Bytes.
00059              (++) Launch the Option Bytes loader.
00060              (++) Get the Write protection.
00061              (++) Get the read protection status.
00062              (++) Get the BOR level.
00063              (++) Get the user option bytes.
00064
00065          (#) FLASH Interrupts and flag management functions: this group
00066              includes all needed functions to:
00067              (++) Enable/Disable the flash interrupt sources.
00068              (++) Get flags status.
00069              (++) Clear flags.
00070              (++) Get Flash operation status.
00071              (++) Wait for last flash operation.
00072
00073   *  @endverbatim
00074   *
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00079   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00080   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00081   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00082   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00083   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00084   *
00085   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00086   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00087   *
00088   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00089   ******************************************************************************
00090   */
00091
00092 /* Includes ------------------------------------------------------------------*/
00093 #include "stm32l1xx_flash.h"
00094
00095 /** @addtogroup STM32L1xx_StdPeriph_Driver
00096   * @{
00097   */
00098
00099 /** @defgroup FLASH
00100   * @brief FLASH driver modules
00101   * @{
00102   */
00103
00104 /* Private typedef -----------------------------------------------------------*/
00105 /* Private define ------------------------------------------------------------*/
00106
00107 /* FLASH Mask */
00108 #define WRP01_MASK                 ((uint32_t)0x0000FFFF)
00109 #define WRP23_MASK                 ((uint32_t)0xFFFF0000)
00110 #define WRP45_MASK                 ((uint32_t)0x0000FFFF)
00111 #define WRP67_MASK                 ((uint32_t)0xFFFF0000)
00112 #define WRP89_MASK                 ((uint32_t)0x0000FFFF)
00113 #define WRP1011_MASK               ((uint32_t)0xFFFF0000)
00114
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119
00120 /** @defgroup FLASH_Private_Functions
00121   * @{
00122   */
00123
00124 /** @defgroup FLASH_Group1 FLASH Interface configuration functions
00125   *  @brief   FLASH Interface configuration functions
00126  *
00127 @verbatim
00128   ==============================================================================
00129              ##### FLASH Interface configuration functions #####
00130   ==============================================================================
00131
00132     [..] FLASH_Interface configuration_Functions, includes the following functions:
00133      (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
00134     [..] To correctly read data from Flash memory, the number of wait states (LATENCY)
00135          must be correctly programmed according to the frequency of the CPU clock
00136         (HCLK) and the supply voltage of the device.
00137   [..]
00138   ----------------------------------------------------------------
00139  |  Wait states  |                HCLK clock frequency (MHz)      |
00140  |               |------------------------------------------------|
00141  |   (Latency)   |            voltage range       | voltage range |
00142  |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
00143  |               |----------------|---------------|---------------|
00144  |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
00145  |-------------- |----------------|---------------|---------------|
00146  |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
00147  |---------------|----------------|---------------|---------------|
00148  |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
00149   ----------------------------------------------------------------
00150   [..]
00151      (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
00152      (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState);
00153      (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState);
00154      (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
00155      (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
00156   [..]
00157   Here below the allowed configuration of Latency, 64Bit access and prefetch buffer
00158   [..]
00159   --------------------------------------------------------------------------------
00160  |               |              ACC64 = 0         |              ACC64 = 1        |
00161  |   Latency     |----------------|---------------|---------------|---------------|
00162  |               |   PRFTEN = 0   |   PRFTEN = 1  |   PRFTEN = 0  |   PRFTEN = 1  |
00163  |---------------|----------------|---------------|---------------|---------------|
00164  |0WS(1CPU cycle)|     YES        |     NO        |     YES       |     YES       |
00165  |---------------|----------------|---------------|---------------|---------------|
00166  |1WS(2CPU cycle)|     NO         |     NO        |     YES       |     YES       |
00167   --------------------------------------------------------------------------------
00168   [..]
00169    All these functions don't need the unlock sequence.
00170
00171 @endverbatim
00172   * @{
00173   */
00174
00175 /**
00176   * @brief  Sets the code latency value.
00177   * @param  FLASH_Latency: specifies the FLASH Latency value.
00178   *   This parameter can be one of the following values:
00179   *     @arg FLASH_Latency_0: FLASH Zero Latency cycle.
00180   *     @arg FLASH_Latency_1: FLASH One Latency cycle.
00181   * @retval None
00182   */
00183 void FLASH_SetLatency(uint32_t FLASH_Latency)
00184 {
00185    uint32_t tmpreg = 0;
00186
00187   /* Check the parameters */
00188   assert_param(IS_FLASH_LATENCY(FLASH_Latency));
00189
00190   /* Read the ACR register */
00191   tmpreg = FLASH->ACR;
00192
00193   /* Sets the Latency value */
00194   tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
00195   tmpreg |= FLASH_Latency;
00196
00197   /* Write the ACR register */
00198   FLASH->ACR = tmpreg;
00199 }
00200
00201 /**
00202   * @brief  Enables or disables the Prefetch Buffer.
00203   * @param  NewState: new state of the FLASH prefetch buffer.
00204   *              This parameter can be: ENABLE or DISABLE.
00205   * @retval None
00206   */
00207 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
00208 {
00209   /* Check the parameters */
00210   assert_param(IS_FUNCTIONAL_STATE(NewState));
00211
00212   if(NewState != DISABLE)
00213   {
00214     FLASH->ACR |= FLASH_ACR_PRFTEN;
00215   }
00216   else
00217   {
00218     FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));
00219   }
00220 }
00221
00222 /**
00223   * @brief  Enables or disables read access to flash by 64 bits.
00224   * @param  NewState: new state of the FLASH read access mode.
00225   *              This parameter can be: ENABLE or DISABLE.
00226   * @note    If this bit is set, the Read access 64 bit is used.
00227   *          If this bit is reset, the Read access 32 bit is used.
00228   * @note    This bit cannot be written at the same time as the LATENCY and
00229   *          PRFTEN bits.
00230   *          To reset this bit, the LATENCY should be zero wait state and the
00231   *          prefetch off.
00232   * @retval None
00233   */
00234 void FLASH_ReadAccess64Cmd(FunctionalState NewState)
00235 {
00236   /* Check the parameters */
00237   assert_param(IS_FUNCTIONAL_STATE(NewState));
00238
00239   if(NewState != DISABLE)
00240   {
00241     FLASH->ACR |= FLASH_ACR_ACC64;
00242   }
00243   else
00244   {
00245     FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));
00246   }
00247 }
00248
00249 /**
00250   * @brief  Enable or disable the power down mode during Sleep mode.
00251   * @note   This function is used to power down the FLASH when the system is in SLEEP LP mode.
00252   * @param  NewState: new state of the power down mode during sleep mode.
00253   *   This parameter can be: ENABLE or DISABLE.
00254   * @retval None
00255   */
00256 void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)
00257 {
00258   /* Check the parameters */
00259   assert_param(IS_FUNCTIONAL_STATE(NewState));
00260
00261   if (NewState != DISABLE)
00262   {
00263     /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */
00264     FLASH->ACR |= FLASH_ACR_SLEEP_PD;
00265   }
00266   else
00267   {
00268     /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */
00269     FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));
00270   }
00271 }
00272
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup FLASH_Group2 FLASH Memory Programming functions
00278  *  @brief   FLASH Memory Programming functions
00279  *
00280 @verbatim
00281   ==============================================================================
00282                 ##### FLASH Memory Programming functions #####
00283   ==============================================================================
00284
00285     [..] The FLASH Memory Programming functions, includes the following functions:
00286     (+) void FLASH_Unlock(void);
00287     (+) void FLASH_Lock(void);
00288     (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
00289     (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
00290
00291     [..] Any operation of erase or program should follow these steps:
00292     (#) Call the FLASH_Unlock() function to enable the flash control register and
00293         program memory access.
00294     (#) Call the desired function to erase page or program data.
00295     (#) Call the FLASH_Lock() to disable the flash program memory access
00296        (recommended to protect the FLASH memory against possible unwanted operation).
00297
00298 @endverbatim
00299   * @{
00300   */
00301
00302 /**
00303   * @brief  Unlocks the FLASH control register and program memory access.
00304   * @param  None
00305   * @retval None
00306   */
00307 void FLASH_Unlock(void)
00308 {
00309   if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)
00310   {
00311     /* Unlocking the data memory and FLASH_PECR register access */
00312     DATA_EEPROM_Unlock();
00313
00314     /* Unlocking the program memory access */
00315     FLASH->PRGKEYR = FLASH_PRGKEY1;
00316     FLASH->PRGKEYR = FLASH_PRGKEY2;
00317   }
00318 }
00319
00320 /**
00321   * @brief  Locks the Program memory access.
00322   * @param  None
00323   * @retval None
00324   */
00325 void FLASH_Lock(void)
00326 {
00327   /* Set the PRGLOCK Bit to lock the program memory access */
00328   FLASH->PECR |= FLASH_PECR_PRGLOCK;
00329 }
00330
00331 /**
00332   * @brief  Erases a specified page in program memory.
00333   * @note   To correctly run this function, the FLASH_Unlock() function
00334   *         must be called before.
00335   *         Call the FLASH_Lock() to disable the flash memory access
00336   *         (recommended to protect the FLASH memory against possible unwanted operation)
00337   * @param  Page_Address: The page address in program memory to be erased.
00338   * @note   A Page is erased in the Program memory only if the address to load
00339   *         is the start address of a page (multiple of 256 bytes).
00340   * @retval FLASH Status: The returned value can be:
00341   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00342   */
00343 FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
00344 {
00345   FLASH_Status status = FLASH_COMPLETE;
00346
00347   /* Check the parameters */
00348   assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
00349
00350   /* Wait for last operation to be completed */
00351   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00352
00353   if(status == FLASH_COMPLETE)
00354   {
00355     /* If the previous operation is completed, proceed to erase the page */
00356
00357     /* Set the ERASE bit */
00358     FLASH->PECR |= FLASH_PECR_ERASE;
00359
00360     /* Set PROG bit */
00361     FLASH->PECR |= FLASH_PECR_PROG;
00362
00363     /* Write 00000000h to the first word of the program page to erase */
00364     *(__IO uint32_t *)Page_Address = 0x00000000;
00365
00366     /* Wait for last operation to be completed */
00367     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00368
00369     /* If the erase operation is completed, disable the ERASE and PROG bits */
00370     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
00371     FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
00372   }
00373   /* Return the Erase Status */
00374   return status;
00375 }
00376
00377 /**
00378   * @brief  Programs a word at a specified address in program memory.
00379   * @note   To correctly run this function, the FLASH_Unlock() function
00380   *         must be called before.
00381   *         Call the FLASH_Lock() to disable the flash memory access
00382   *         (recommended to protect the FLASH memory against possible unwanted operation).
00383   * @param  Address: specifies the address to be written.
00384   * @param  Data: specifies the data to be written.
00385   * @retval FLASH Status: The returned value can be:
00386   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00387   */
00388 FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)
00389 {
00390   FLASH_Status status = FLASH_COMPLETE;
00391
00392   /* Check the parameters */
00393   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00394
00395   /* Wait for last operation to be completed */
00396   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00397
00398   if(status == FLASH_COMPLETE)
00399   {
00400     /* If the previous operation is completed, proceed to program the new  word */
00401     *(__IO uint32_t *)Address = Data;
00402
00403     /* Wait for last operation to be completed */
00404     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00405   }
00406   /* Return the Write Status */
00407   return status;
00408 }
00409
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup FLASH_Group3 DATA EEPROM Programming functions
00415  *  @brief   DATA EEPROM Programming functions
00416  *
00417 @verbatim
00418  ===============================================================================
00419                      ##### DATA EEPROM Programming functions #####
00420  ===============================================================================
00421
00422     [..] The DATA_EEPROM Programming_Functions, includes the following functions:
00423         (+) void DATA_EEPROM_Unlock(void);
00424         (+) void DATA_EEPROM_Lock(void);
00425         (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
00426         (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
00427         (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
00428         (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
00429         (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
00430         (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
00431         (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
00432         (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
00433         (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
00434
00435     [..] Any operation of erase or program should follow these steps:
00436     (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access
00437         and Flash program erase control register access.
00438     (#) Call the desired function to erase or program data.
00439     (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access
00440         and Flash program erase control register access(recommended
00441         to protect the DATA_EEPROM against possible unwanted operation).
00442
00443 @endverbatim
00444   * @{
00445   */
00446
00447 /**
00448   * @brief  Unlocks the data memory and FLASH_PECR register access.
00449   * @param  None
00450   * @retval None
00451   */
00452 void DATA_EEPROM_Unlock(void)
00453 {
00454   if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
00455   {
00456     /* Unlocking the Data memory and FLASH_PECR register access*/
00457     FLASH->PEKEYR = FLASH_PEKEY1;
00458     FLASH->PEKEYR = FLASH_PEKEY2;
00459   }
00460 }
00461
00462 /**
00463   * @brief  Locks the Data memory and FLASH_PECR register access.
00464   * @param  None
00465   * @retval None
00466   */
00467 void DATA_EEPROM_Lock(void)
00468 {
00469   /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
00470   FLASH->PECR |= FLASH_PECR_PELOCK;
00471 }
00472
00473 /**
00474   * @brief  Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
00475   * @param  NewState: new state of the DATA EEPROM fixed Time programming mode.
00476   *         This parameter can be: ENABLE or DISABLE.
00477   * @retval None
00478   */
00479 void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)
00480 {
00481   /* Check the parameters */
00482   assert_param(IS_FUNCTIONAL_STATE(NewState));
00483
00484   if(NewState != DISABLE)
00485   {
00486     FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;
00487   }
00488   else
00489   {
00490     FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
00491   }
00492 }
00493
00494 /**
00495   * @brief  Erase a byte in data memory.
00496   * @param  Address: specifies the address to be erased.
00497   * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
00498   *         density devices.
00499   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00500   *         must be called before.
00501   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00502   *         and Flash program erase control register access(recommended to protect
00503   *         the DATA_EEPROM against possible unwanted operation).
00504   * @retval FLASH Status: The returned value can be:
00505   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00506   */
00507 FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address)
00508 {
00509   FLASH_Status status = FLASH_COMPLETE;
00510
00511   /* Check the parameters */
00512   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00513
00514   /* Wait for last operation to be completed */
00515   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00516
00517   if(status == FLASH_COMPLETE)
00518   {
00519     /* Write "00h" to valid address in the data memory" */
00520     *(__IO uint8_t *) Address = (uint8_t)0x00;
00521   }
00522
00523   /* Return the erase status */
00524   return status;
00525 }
00526
00527 /**
00528   * @brief  Erase a halfword in data memory.
00529   * @param  Address: specifies the address to be erased.
00530   * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
00531   *         density devices.
00532   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00533   *         must be called before.
00534   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00535   *         and Flash program erase control register access(recommended to protect
00536   *         the DATA_EEPROM against possible unwanted operation).
00537   * @retval FLASH Status: The returned value can be:
00538   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00539   */
00540 FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address)
00541 {
00542   FLASH_Status status = FLASH_COMPLETE;
00543
00544   /* Check the parameters */
00545   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00546
00547   /* Wait for last operation to be completed */
00548   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00549
00550   if(status == FLASH_COMPLETE)
00551   {
00552     /* Write "0000h" to valid address in the data memory" */
00553     *(__IO uint16_t *) Address = (uint16_t)0x0000;
00554   }
00555
00556   /* Return the erase status */
00557   return status;
00558 }
00559
00560 /**
00561   * @brief  Erase a word in data memory.
00562   * @param  Address: specifies the address to be erased.
00563   * @note   For STM32L1XX_MD, A data memory word is erased in the data memory only
00564   *         if the address to load is the start address of a word (multiple of a word).
00565   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00566   *         must be called before.
00567   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00568   *         and Flash program erase control register access(recommended to protect
00569   *         the DATA_EEPROM against possible unwanted operation).
00570   * @retval FLASH Status: The returned value can be:
00571   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00572   */
00573 FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)
00574 {
00575   FLASH_Status status = FLASH_COMPLETE;
00576
00577   /* Check the parameters */
00578   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00579
00580   /* Wait for last operation to be completed */
00581   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00582
00583   if(status == FLASH_COMPLETE)
00584   {
00585     /* Write "00000000h" to valid address in the data memory" */
00586     *(__IO uint32_t *) Address = 0x00000000;
00587   }
00588
00589   /* Return the erase status */
00590   return status;
00591 }
00592
00593 /**
00594   * @brief  Write a Byte at a specified address in data memory.
00595   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00596   *         must be called before.
00597   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00598   *         and Flash program erase control register access(recommended to protect
00599   *         the DATA_EEPROM against possible unwanted operation).
00600   * @param  Address: specifies the address to be written.
00601   * @param  Data: specifies the data to be written.
00602   * @note   This function assumes that the is data word is already erased.
00603   * @retval FLASH Status: The returned value can be:
00604   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00605   */
00606 FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
00607 {
00608   FLASH_Status status = FLASH_COMPLETE;
00609 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00610   uint32_t tmp = 0, tmpaddr = 0;
00611 #endif
00612
00613   /* Check the parameters */
00614   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00615
00616   /* Wait for last operation to be completed */
00617   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00618
00619   if(status == FLASH_COMPLETE)
00620   {
00621     /* Clear the FTDW bit */
00622     FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
00623
00624 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00625     if(Data != (uint8_t)0x00)
00626     {
00627       /* If the previous operation is completed, proceed to write the new Data */
00628       *(__IO uint8_t *)Address = Data;
00629
00630       /* Wait for last operation to be completed */
00631       status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00632     }
00633     else
00634     {
00635       tmpaddr = Address & 0xFFFFFFFC;
00636       tmp = * (__IO uint32_t *) tmpaddr;
00637       tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
00638       tmp &= ~tmpaddr;
00639       status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
00640       status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
00641     }
00642 #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
00643     /* If the previous operation is completed, proceed to write the new Data */
00644     *(__IO uint8_t *)Address = Data;
00645
00646     /* Wait for last operation to be completed */
00647     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00648 #endif
00649   }
00650   /* Return the Write Status */
00651   return status;
00652 }
00653
00654 /**
00655   * @brief  Writes a half word at a specified address in data memory.
00656   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00657   *         must be called before.
00658   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00659   *         and Flash program erase control register access(recommended to protect
00660   *         the DATA_EEPROM against possible unwanted operation).
00661   * @param  Address: specifies the address to be written.
00662   * @param  Data: specifies the data to be written.
00663   * @note   This function assumes that the is data word is already erased.
00664   * @retval FLASH Status: The returned value can be:
00665   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or  FLASH_TIMEOUT.
00666   */
00667 FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
00668 {
00669   FLASH_Status status = FLASH_COMPLETE;
00670 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00671   uint32_t tmp = 0, tmpaddr = 0;
00672 #endif
00673
00674   /* Check the parameters */
00675   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00676
00677   /* Wait for last operation to be completed */
00678   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00679
00680   if(status == FLASH_COMPLETE)
00681   {
00682     /* Clear the FTDW bit */
00683     FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
00684
00685 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00686     if(Data != (uint16_t)0x0000)
00687     {
00688       /* If the previous operation is completed, proceed to write the new data */
00689       *(__IO uint16_t *)Address = Data;
00690
00691       /* Wait for last operation to be completed */
00692       status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00693     }
00694     else
00695     {
00696       if((Address & 0x3) != 0x3)
00697       {
00698         tmpaddr = Address & 0xFFFFFFFC;
00699         tmp = * (__IO uint32_t *) tmpaddr;
00700         tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
00701         tmp &= ~tmpaddr;
00702         status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
00703         status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
00704       }
00705       else
00706       {
00707         DATA_EEPROM_FastProgramByte(Address, 0x00);
00708         DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
00709       }
00710     }
00711 #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
00712     /* If the previous operation is completed, proceed to write the new data */
00713     *(__IO uint16_t *)Address = Data;
00714
00715     /* Wait for last operation to be completed */
00716     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00717 #endif
00718   }
00719   /* Return the Write Status */
00720   return status;
00721 }
00722
00723 /**
00724   * @brief  Programs a word at a specified address in data memory.
00725   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00726   *         must be called before.
00727   *         Call the DATA_EEPROM_Lock() to the data EEPROM access
00728   *         and Flash program erase control register access(recommended to protect
00729   *         the DATA_EEPROM against possible unwanted operation).
00730   * @param  Address: specifies the address to be written.
00731   * @param  Data: specifies the data to be written.
00732   * @note   This function assumes that the is data word is already erased.
00733   * @retval FLASH Status: The returned value can be:
00734   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00735   */
00736 FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)
00737 {
00738   FLASH_Status status = FLASH_COMPLETE;
00739
00740   /* Check the parameters */
00741   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00742
00743   /* Wait for last operation to be completed */
00744   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00745
00746   if(status == FLASH_COMPLETE)
00747   {
00748     /* Clear the FTDW bit */
00749     FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
00750
00751     /* If the previous operation is completed, proceed to program the new data */
00752     *(__IO uint32_t *)Address = Data;
00753
00754     /* Wait for last operation to be completed */
00755     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00756   }
00757   /* Return the Write Status */
00758   return status;
00759 }
00760
00761 /**
00762   * @brief  Write a Byte at a specified address in data memory without erase.
00763   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00764   *         must be called before.
00765   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00766   *         and Flash program erase control register access(recommended to protect
00767   *         the DATA_EEPROM against possible unwanted operation).
00768   * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before
00769   *         this function to configure the Fixed Time Programming.
00770   * @param  Address: specifies the address to be written.
00771   * @param  Data: specifies the data to be written.
00772   * @retval FLASH Status: The returned value can be:
00773   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00774   */
00775 FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)
00776 {
00777   FLASH_Status status = FLASH_COMPLETE;
00778 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00779   uint32_t tmp = 0, tmpaddr = 0;
00780 #endif
00781
00782   /* Check the parameters */
00783   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00784
00785   /* Wait for last operation to be completed */
00786   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00787
00788   if(status == FLASH_COMPLETE)
00789   {
00790 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00791     if(Data != (uint8_t) 0x00)
00792     {
00793       *(__IO uint8_t *)Address = Data;
00794
00795       /* Wait for last operation to be completed */
00796       status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00797
00798     }
00799     else
00800     {
00801       tmpaddr = Address & 0xFFFFFFFC;
00802       tmp = * (__IO uint32_t *) tmpaddr;
00803       tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
00804       tmp &= ~tmpaddr;
00805       status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
00806       status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
00807     }
00808 #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
00809     *(__IO uint8_t *)Address = Data;
00810
00811     /* Wait for last operation to be completed */
00812     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00813 #endif
00814   }
00815   /* Return the Write Status */
00816   return status;
00817 }
00818
00819 /**
00820   * @brief  Writes a half word at a specified address in data memory without erase.
00821   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00822   *         must be called before.
00823   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00824   *         and Flash program erase control register access(recommended to protect
00825   *         the DATA_EEPROM against possible unwanted operation).
00826   * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before
00827   *         this function to configure the Fixed Time Programming
00828   * @param  Address: specifies the address to be written.
00829   * @param  Data: specifies the data to be written.
00830   * @retval FLASH Status: The returned value can be:
00831   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00832   */
00833 FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
00834 {
00835   FLASH_Status status = FLASH_COMPLETE;
00836 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00837   uint32_t tmp = 0, tmpaddr = 0;
00838 #endif
00839
00840   /* Check the parameters */
00841   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00842
00843   /* Wait for last operation to be completed */
00844   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00845
00846   if(status == FLASH_COMPLETE)
00847   {
00848 #if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
00849     if(Data != (uint16_t)0x0000)
00850     {
00851       *(__IO uint16_t *)Address = Data;
00852
00853       /* Wait for last operation to be completed */
00854       status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00855     }
00856     else
00857     {
00858       if((Address & 0x3) != 0x3)
00859       {
00860         tmpaddr = Address & 0xFFFFFFFC;
00861         tmp = * (__IO uint32_t *) tmpaddr;
00862         tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
00863         tmp &= ~tmpaddr;
00864         status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
00865         status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
00866       }
00867       else
00868       {
00869         DATA_EEPROM_FastProgramByte(Address, 0x00);
00870         DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
00871       }
00872     }
00873 #elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
00874     *(__IO uint16_t *)Address = Data;
00875
00876     /* Wait for last operation to be completed */
00877     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00878 #endif
00879   }
00880   /* Return the Write Status */
00881   return status;
00882 }
00883
00884 /**
00885   * @brief  Programs a word at a specified address in data memory without erase.
00886   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00887   *         must be called before.
00888   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00889   *         and Flash program erase control register access(recommended to protect
00890   *         the DATA_EEPROM against possible unwanted operation).
00891   * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before
00892   *         this function to configure the Fixed Time Programming.
00893   * @param  Address: specifies the address to be written.
00894   * @param  Data: specifies the data to be written.
00895   * @retval FLASH Status: The returned value can be:
00896   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or  FLASH_TIMEOUT.
00897   */
00898 FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)
00899 {
00900   FLASH_Status status = FLASH_COMPLETE;
00901
00902   /* Check the parameters */
00903   assert_param(IS_FLASH_DATA_ADDRESS(Address));
00904
00905   /* Wait for last operation to be completed */
00906   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00907
00908   if(status == FLASH_COMPLETE)
00909   {
00910     *(__IO uint32_t *)Address = Data;
00911
00912     /* Wait for last operation to be completed */
00913     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00914   }
00915   /* Return the Write Status */
00916   return status;
00917 }
00918
00919 /**
00920   * @}
00921   */
00922
00923 /** @defgroup FLASH_Group4 Option Bytes Programming functions
00924  *  @brief   Option Bytes Programming functions
00925  *
00926 @verbatim
00927   ==============================================================================
00928                 ##### Option Bytes Programming functions #####
00929   ==============================================================================
00930
00931     [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
00932     (+) void FLASH_OB_Unlock(void);
00933     (+) void FLASH_OB_Lock(void);
00934     (+) void FLASH_OB_Launch(void);
00935     (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
00936     (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
00937     (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
00938     (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
00939     (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
00940     (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
00941     (+) uint8_t FLASH_OB_GetUser(void);
00942     (+) uint32_t FLASH_OB_GetWRP(void);
00943     (+) uint32_t FLASH_OB_GetWRP1(void);
00944     (+) uint32_t FLASH_OB_GetWRP2(void);
00945     (+) FlagStatus FLASH_OB_GetRDP(void);
00946     (+) uint8_t FLASH_OB_GetBOR(void);
00947     (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT);
00948
00949     [..] Any operation of erase or program should follow these steps:
00950     (#) Call the FLASH_OB_Unlock() function to enable the Flash option control
00951         register access.
00952     (#) Call one or several functions to program the desired option bytes.
00953         (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable
00954              the desired sector write protection.
00955         (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level.
00956         (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure
00957              the user option Bytes: IWDG, STOP and the Standby.
00958         (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level.
00959         (++) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes                 .
00960     (#) Once all needed option bytes to be programmed are correctly written, call the
00961         FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
00962     (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended
00963         to protect the option Bytes against possible unwanted operations).
00964
00965 @endverbatim
00966   * @{
00967   */
00968
00969 /**
00970   * @brief  Unlocks the option bytes block access.
00971   * @param  None
00972   * @retval None
00973   */
00974 void FLASH_OB_Unlock(void)
00975 {
00976   if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)
00977   {
00978     /* Unlocking the data memory and FLASH_PECR register access */
00979     DATA_EEPROM_Unlock();
00980
00981     /* Unlocking the option bytes block access */
00982     FLASH->OPTKEYR = FLASH_OPTKEY1;
00983     FLASH->OPTKEYR = FLASH_OPTKEY2;
00984   }
00985 }
00986
00987 /**
00988   * @brief  Locks the option bytes block access.
00989   * @param  None
00990   * @retval None
00991   */
00992 void FLASH_OB_Lock(void)
00993 {
00994   /* Set the OPTLOCK Bit to lock the option bytes block access */
00995   FLASH->PECR |= FLASH_PECR_OPTLOCK;
00996 }
00997
00998 /**
00999   * @brief  Launch the option byte loading.
01000   * @param  None
01001   * @retval None
01002   */
01003 void FLASH_OB_Launch(void)
01004 {
01005   /* Set the OBL_Launch bit to lauch the option byte loading */
01006   FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;
01007 }
01008
01009 /**
01010   * @brief  Write protects the desired pages.
01011   * @note   To correctly run this function, the FLASH_OB_Unlock() function
01012   *         must be called before.
01013   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01014   *        (recommended to protect the FLASH memory against possible unwanted operation).
01015   * @param  OB_WRP: specifies the address of the pages to be write protected.
01016   *   This parameter can be:
01017   * @param  value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511
01018   * @param  OB_WRP_AllPages
01019   * @param  NewState: new state of the specified FLASH Pages Wtite protection.
01020   *   This parameter can be: ENABLE or DISABLE.
01021   * @retval FLASH Status: The returned value can be:
01022   * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01023   */
01024 FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
01025 {
01026   uint32_t WRP01_Data = 0, WRP23_Data = 0;
01027
01028   FLASH_Status status = FLASH_COMPLETE;
01029   uint32_t tmp1 = 0, tmp2 = 0;
01030
01031   /* Check the parameters */
01032   assert_param(IS_OB_WRP(OB_WRP));
01033   assert_param(IS_FUNCTIONAL_STATE(NewState));
01034
01035   /* Wait for last operation to be completed */
01036   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01037
01038   if(status == FLASH_COMPLETE)
01039   {
01040     if (NewState != DISABLE)
01041     {
01042       WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));
01043       WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23)));
01044       tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);
01045       OB->WRP01 = tmp1;
01046
01047       tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);
01048       OB->WRP23 = tmp2;
01049     }
01050
01051     else
01052     {
01053       WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));
01054       WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23)));
01055
01056       tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);
01057       OB->WRP01 = tmp1;
01058
01059       tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);
01060       OB->WRP23 = tmp2;
01061     }
01062     /* Wait for last operation to be completed */
01063     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01064   }
01065
01066   /* Return the write protection operation Status */
01067   return status;
01068 }
01069
01070 /**
01071   * @brief  Write protects the desired pages.
01072   * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
01073   *         density devices.
01074   *         To correctly run this function, the FLASH_OB_Unlock() function
01075   *         must be called before.
01076   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01077   *         (recommended to protect the FLASH memory against possible unwanted operation).
01078   * @param  OB_WRP1: specifies the address of the pages to be write protected.
01079   *   This parameter can be:
01080   *     @arg  value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023
01081   *     @arg OB_WRP_AllPages
01082   * @param  NewState: new state of the specified FLASH Pages Wtite protection.
01083   *         This parameter can be: ENABLE or DISABLE.
01084   * @retval FLASH Status: The returned value can be:
01085   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01086   */
01087 FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState)
01088 {
01089   uint32_t WRP45_Data = 0, WRP67_Data = 0;
01090
01091   FLASH_Status status = FLASH_COMPLETE;
01092   uint32_t tmp1 = 0, tmp2 = 0;
01093
01094   /* Check the parameters */
01095   assert_param(IS_OB_WRP(OB_WRP1));
01096   assert_param(IS_FUNCTIONAL_STATE(NewState));
01097
01098   /* Wait for last operation to be completed */
01099   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01100
01101   if(status == FLASH_COMPLETE)
01102   {
01103     if (NewState != DISABLE)
01104     {
01105       WRP45_Data = (uint16_t)(((OB_WRP1 & WRP45_MASK) | OB->WRP45));
01106       WRP67_Data = (uint16_t)((((OB_WRP1 & WRP67_MASK)>>16 | OB->WRP67)));
01107       tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data);
01108       OB->WRP45 = tmp1;
01109
01110       tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data);
01111       OB->WRP67 = tmp2;
01112     }
01113
01114     else
01115     {
01116       WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45));
01117       WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67)));
01118
01119       tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data);
01120       OB->WRP45 = tmp1;
01121
01122       tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data);
01123       OB->WRP67 = tmp2;
01124     }
01125     /* Wait for last operation to be completed */
01126     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01127   }
01128
01129   /* Return the write protection operation Status */
01130   return status;
01131 }
01132
01133 /**
01134   * @brief  Write protects the desired pages.
01135   * @note   This function can be used only for STM32L1XX_HD density devices.
01136   *         To correctly run this function, the FLASH_OB_Unlock() function
01137   *         must be called before.
01138   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01139   *         (recommended to protect the FLASH memory against possible unwanted operation).
01140   * @param  OB_WRP2: specifies the address of the pages to be write protected.
01141   *   This parameter can be:
01142   *     @arg  value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535
01143   *     @arg OB_WRP_AllPages
01144   * @param  NewState: new state of the specified FLASH Pages Wtite protection.
01145   *         This parameter can be: ENABLE or DISABLE.
01146   * @retval FLASH Status: The returned value can be:
01147   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01148   */
01149 FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState)
01150 {
01151   uint32_t WRP89_Data = 0, WRP1011_Data = 0;
01152
01153   FLASH_Status status = FLASH_COMPLETE;
01154   uint32_t tmp1 = 0, tmp2 = 0;
01155
01156   /* Check the parameters */
01157   assert_param(IS_OB_WRP(OB_WRP2));
01158   assert_param(IS_FUNCTIONAL_STATE(NewState));
01159
01160   /* Wait for last operation to be completed */
01161   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01162
01163   if(status == FLASH_COMPLETE)
01164   {
01165     if (NewState != DISABLE)
01166     {
01167       WRP89_Data = (uint16_t)(((OB_WRP2 & WRP89_MASK) | OB->WRP89));
01168       WRP1011_Data = (uint16_t)((((OB_WRP2 & WRP1011_MASK)>>16 | OB->WRP1011)));
01169       tmp1 = (uint32_t)(~(WRP89_Data) << 16)|(WRP89_Data);
01170       OB->WRP89 = tmp1;
01171
01172       tmp2 = (uint32_t)(~(WRP1011_Data) << 16)|(WRP1011_Data);
01173       OB->WRP1011 = tmp2;
01174     }
01175
01176     else
01177     {
01178       WRP89_Data = (uint16_t)(~OB_WRP2 & (WRP89_MASK & OB->WRP89));
01179       WRP1011_Data = (uint16_t)((((~OB_WRP2 & WRP1011_MASK)>>16 & OB->WRP1011)));
01180
01181       tmp1 = (uint32_t)((~WRP89_Data) << 16)|(WRP89_Data);
01182       OB->WRP89 = tmp1;
01183
01184       tmp2 = (uint32_t)((~WRP1011_Data) << 16)|(WRP1011_Data);
01185       OB->WRP1011 = tmp2;
01186     }
01187     /* Wait for last operation to be completed */
01188     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01189   }
01190
01191   /* Return the write protection operation Status */
01192   return status;
01193 }
01194
01195 /**
01196   * @brief  Enables or disables the read out protection.
01197   * @note   To correctly run this function, the FLASH_OB_Unlock() function
01198   *         must be called before.
01199   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01200   *         (recommended to protect the FLASH memory against possible unwanted operation).
01201   * @param  FLASH_ReadProtection_Level: specifies the read protection level.
01202   *   This parameter can be:
01203   *     @arg OB_RDP_Level_0: No protection
01204   *     @arg OB_RDP_Level_1: Read protection of the memory
01205   *     @arg OB_RDP_Level_2: Chip protection
01206   *     @retval FLASH Status: The returned value can be:
01207   * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01208   */
01209 FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
01210 {
01211   FLASH_Status status = FLASH_COMPLETE;
01212   uint8_t tmp1 = 0;
01213   uint32_t tmp2 = 0;
01214
01215   /* Check the parameters */
01216   assert_param(IS_OB_RDP(OB_RDP));
01217   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01218
01219   /* calculate the option byte to write */
01220   tmp1 = (uint8_t)(~(OB_RDP ));
01221   tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));
01222
01223   if(status == FLASH_COMPLETE)
01224   {
01225    /* program read protection level */
01226     OB->RDP = tmp2;
01227   }
01228
01229   /* Wait for last operation to be completed */
01230     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01231
01232   /* Return the Read protection operation Status */
01233   return status;
01234 }
01235
01236 /**
01237   * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
01238   * @note   To correctly run this function, the FLASH_OB_Unlock() function
01239   *         must be called before.
01240   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01241   *         (recommended to protect the FLASH memory against possible unwanted operation).
01242   * @param  OB_IWDG: Selects the WDG mode.
01243   *   This parameter can be one of the following values:
01244   *     @arg OB_IWDG_SW: Software WDG selected
01245   *     @arg OB_IWDG_HW: Hardware WDG selected
01246   * @param  OB_STOP: Reset event when entering STOP mode.
01247   *   This parameter can be one of the following values:
01248   *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
01249   *     @arg OB_STOP_RST: Reset generated when entering in STOP
01250   * @param  OB_STDBY: Reset event when entering Standby mode.
01251   *   This parameter can be one of the following values:
01252   *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
01253   *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
01254   * @retval FLASH Status: The returned value can be:
01255   * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01256   */
01257 FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
01258 {
01259   FLASH_Status status = FLASH_COMPLETE;
01260   uint32_t tmp = 0, tmp1 = 0;
01261
01262   /* Check the parameters */
01263   assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
01264   assert_param(IS_OB_STOP_SOURCE(OB_STOP));
01265   assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
01266
01267   /* Get the User Option byte register */
01268   tmp1 = (FLASH->OBR & 0x000F0000) >> 16;
01269
01270   /* Calculate the user option byte to write */
01271   tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));
01272   tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
01273
01274   /* Wait for last operation to be completed */
01275   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01276
01277   if(status == FLASH_COMPLETE)
01278   {
01279     /* Write the User Option Byte */
01280     OB->USER = tmp;
01281   }
01282
01283   /* Wait for last operation to be completed */
01284     status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01285
01286   /* Return the Option Byte program Status */
01287   return status;
01288 }
01289
01290 /**
01291   * @brief  Programs the FLASH brownout reset threshold level Option Byte.
01292   * @note   To correctly run this function, the FLASH_OB_Unlock() function
01293   *         must be called before.
01294   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01295   *         (recommended to protect the FLASH memory against possible unwanted operation).
01296   * @param  OB_BOR: Selects the brownout reset threshold level.
01297   *   This parameter can be one of the following values:
01298   *     @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD
01299   *                      power supply reaches the PDR(Power Down Reset) threshold (1.5V)
01300   *     @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
01301   *     @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
01302   *     @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
01303   *     @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
01304   *     @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
01305   * @retval FLASH Status: The returned value can be:
01306   * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01307   */
01308 FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)
01309 {
01310   FLASH_Status status = FLASH_COMPLETE;
01311   uint32_t tmp = 0, tmp1 = 0;
01312
01313   /* Check the parameters */
01314   assert_param(IS_OB_BOR_LEVEL(OB_BOR));
01315
01316   /* Get the User Option byte register */
01317   tmp1 = (FLASH->OBR & 0x00F00000) >> 16;
01318
01319   /* Calculate the option byte to write */
01320   tmp = (uint32_t)~(OB_BOR | tmp1)<<16;
01321   tmp |= (OB_BOR | tmp1);
01322
01323   /* Wait for last operation to be completed */
01324   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01325
01326   if(status == FLASH_COMPLETE)
01327   {
01328     /* Write the BOR Option Byte */
01329     OB->USER = tmp;
01330   }
01331
01332   /* Wait for last operation to be completed */
01333   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01334
01335   /* Return the Option Byte program Status */
01336   return status;
01337 }
01338
01339 /**
01340   * @brief  Configures to boot from Bank1 or Bank2.
01341   * @note   This function can be used only for STM32L1XX_HD density devices.
01342   *         To correctly run this function, the FLASH_OB_Unlock() function
01343   *         must be called before.
01344   *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
01345   *         (recommended to protect the FLASH memory against possible unwanted operation).
01346   * @param  OB_BOOT: select the FLASH Bank to boot from.
01347   *   This parameter can be one of the following values:
01348   *     @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash
01349   *        position and this parameter is selected the device will boot from Bank2 or Bank1,
01350   *        depending on the activation of the bank. The active banks are checked in
01351   *        the following order: Bank2, followed by Bank1.
01352   *        The active bank is recognized by the value programmed at the base address
01353   *        of the respective bank (corresponding to the initial stack pointer value
01354   *        in the interrupt vector table).
01355   *     @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash
01356   *        position and this parameter is selected the device will boot from Bank1(Default).
01357   *        For more information, please refer to AN2606 from www.st.com.
01358   * @retval FLASH Status: The returned value can be:
01359   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01360   */
01361 FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT)
01362 {
01363   FLASH_Status status = FLASH_COMPLETE;
01364   uint32_t tmp = 0, tmp1 = 0;
01365
01366   /* Check the parameters */
01367   assert_param(IS_OB_BOOT_BANK(OB_BOOT));
01368
01369   /* Get the User Option byte register */
01370   tmp1 = (FLASH->OBR & 0x007F0000) >> 16;
01371
01372   /* Calculate the option byte to write */
01373   tmp = (uint32_t)~(OB_BOOT | tmp1)<<16;
01374   tmp |= (OB_BOOT | tmp1);
01375
01376   /* Wait for last operation to be completed */
01377   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01378
01379   if(status == FLASH_COMPLETE)
01380   {
01381     /* Write the BOOT Option Byte */
01382     OB->USER = tmp;
01383   }
01384
01385   /* Wait for last operation to be completed */
01386   status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
01387
01388   /* Return the Option Byte program Status */
01389   return status;
01390 }
01391
01392 /**
01393   * @brief  Returns the FLASH User Option Bytes values.
01394   * @param  None
01395   * @retval The FLASH User Option Bytes.
01396   */
01397 uint8_t FLASH_OB_GetUser(void)
01398 {
01399   /* Return the User Option Byte */
01400   return (uint8_t)(FLASH->OBR >> 20);
01401 }
01402
01403 /**
01404   * @brief  Returns the FLASH Write Protection Option Bytes value.
01405   * @param  None
01406   * @retval The FLASH Write Protection Option Bytes value.
01407   */
01408 uint32_t FLASH_OB_GetWRP(void)
01409 {
01410   /* Return the FLASH write protection Register value */
01411   return (uint32_t)(FLASH->WRPR);
01412 }
01413
01414 /**
01415   * @brief  Returns the FLASH Write Protection Option Bytes value.
01416   * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
01417   *         density devices.
01418   * @param  None
01419   * @retval The FLASH Write Protection Option Bytes value.
01420   */
01421 uint32_t FLASH_OB_GetWRP1(void)
01422 {
01423   /* Return the FLASH write protection Register value */
01424   return (uint32_t)(FLASH->WRPR1);
01425 }
01426
01427 /**
01428   * @brief  Returns the FLASH Write Protection Option Bytes value.
01429   * @note   This function can be used only for STM32L1XX_HD density devices.
01430   * @param  None
01431   * @retval The FLASH Write Protection Option Bytes value.
01432   */
01433 uint32_t FLASH_OB_GetWRP2(void)
01434 {
01435   /* Return the FLASH write protection Register value */
01436   return (uint32_t)(FLASH->WRPR2);
01437 }
01438
01439 /**
01440   * @brief  Checks whether the FLASH Read out Protection Status is set or not.
01441   * @param  None
01442   * @retval FLASH ReadOut Protection Status(SET or RESET).
01443   */
01444 FlagStatus FLASH_OB_GetRDP(void)
01445 {
01446   FlagStatus readstatus = RESET;
01447
01448   if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)
01449   {
01450     readstatus = SET;
01451   }
01452   else
01453   {
01454     readstatus = RESET;
01455   }
01456   return readstatus;
01457 }
01458
01459 /**
01460   * @brief  Returns the FLASH BOR level.
01461   * @param  None
01462   * @retval The FLASH User Option Bytes.
01463   */
01464 uint8_t FLASH_OB_GetBOR(void)
01465 {
01466   /* Return the BOR level */
01467   return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);
01468 }
01469
01470 /**
01471   * @}
01472   */
01473
01474 /** @defgroup FLASH_Group5 Interrupts and flags management functions
01475  *  @brief   Interrupts and flags management functions
01476  *
01477 @verbatim
01478   ==============================================================================
01479               ##### Interrupts and flags management functions #####
01480   ==============================================================================
01481
01482 @endverbatim
01483   * @{
01484   */
01485
01486 /**
01487   * @brief  Enables or disables the specified FLASH interrupts.
01488   * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or
01489   *         disabled.
01490   *   This parameter can be any combination of the following values:
01491   *     @arg FLASH_IT_EOP: FLASH end of programming Interrupt
01492   *     @arg FLASH_IT_ERR: FLASH Error Interrupt
01493   * @retval None
01494   */
01495 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
01496 {
01497   /* Check the parameters */
01498   assert_param(IS_FLASH_IT(FLASH_IT));
01499   assert_param(IS_FUNCTIONAL_STATE(NewState));
01500
01501   if(NewState != DISABLE)
01502   {
01503     /* Enable the interrupt sources */
01504     FLASH->PECR |= FLASH_IT;
01505   }
01506   else
01507   {
01508     /* Disable the interrupt sources */
01509     FLASH->PECR &= ~(uint32_t)FLASH_IT;
01510   }
01511 }
01512
01513 /**
01514   * @brief  Checks whether the specified FLASH flag is set or not.
01515   * @param  FLASH_FLAG: specifies the FLASH flag to check.
01516   *   This parameter can be one of the following values:
01517   *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
01518   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
01519   *     @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode
01520   *     @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag
01521   *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
01522   *     @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
01523   *     @arg FLASH_FLAG_SIZERR: FLASH size error flag
01524   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
01525   *     @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
01526   * @retval The new state of FLASH_FLAG (SET or RESET).
01527   */
01528 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
01529 {
01530   FlagStatus bitstatus = RESET;
01531
01532   /* Check the parameters */
01533   assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
01534
01535   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
01536   {
01537     bitstatus = SET;
01538   }
01539   else
01540   {
01541     bitstatus = RESET;
01542   }
01543   /* Return the new state of FLASH_FLAG (SET or RESET) */
01544   return bitstatus;
01545 }
01546
01547 /**
01548   * @brief  Clears the FLASH's pending flags.
01549   * @param  FLASH_FLAG: specifies the FLASH flags to clear.
01550   *   This parameter can be any combination of the following values:
01551   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
01552   *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
01553   *     @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
01554   *     @arg FLASH_FLAG_SIZERR: FLASH size error flag
01555   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
01556   *     @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
01557   * @retval None
01558   */
01559 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
01560 {
01561   /* Check the parameters */
01562   assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
01563
01564   /* Clear the flags */
01565   FLASH->SR = FLASH_FLAG;
01566 }
01567
01568 /**
01569   * @brief  Returns the FLASH Status.
01570   * @param  None
01571   * @retval FLASH Status: The returned value can be:
01572   *   FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
01573   */
01574 FLASH_Status FLASH_GetStatus(void)
01575 {
01576   FLASH_Status FLASHstatus = FLASH_COMPLETE;
01577
01578   if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
01579   {
01580     FLASHstatus = FLASH_BUSY;
01581   }
01582   else
01583   {
01584     if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
01585     {
01586       FLASHstatus = FLASH_ERROR_WRP;
01587     }
01588     else
01589     {
01590       if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)
01591       {
01592         FLASHstatus = FLASH_ERROR_PROGRAM;
01593       }
01594       else
01595       {
01596         FLASHstatus = FLASH_COMPLETE;
01597       }
01598     }
01599   }
01600   /* Return the FLASH Status */
01601   return FLASHstatus;
01602 }
01603
01604
01605 /**
01606   * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
01607   * @param  Timeout: FLASH programming Timeout.
01608   * @retval FLASH Status: The returned value can be: FLASH_BUSY,
01609   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01610   */
01611 FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
01612 {
01613   __IO FLASH_Status status = FLASH_COMPLETE;
01614
01615   /* Check for the FLASH Status */
01616   status = FLASH_GetStatus();
01617
01618   /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
01619   while((status == FLASH_BUSY) && (Timeout != 0x00))
01620   {
01621     status = FLASH_GetStatus();
01622     Timeout--;
01623   }
01624
01625   if(Timeout == 0x00 )
01626   {
01627     status = FLASH_TIMEOUT;
01628   }
01629   /* Return the operation status */
01630   return status;
01631 }
01632
01633 /**
01634   * @}
01635   */
01636
01637 /**
01638   * @}
01639   */
01640
01641   /**
01642   * @}
01643   */
01644
01645 /**
01646   * @}
01647   */
01648
01649 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash.h Source File

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stm32l1xx_flash.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the FLASH
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_FLASH_H
00028 #define __STM32L1xx_FLASH_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup FLASH
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  FLASH Status
00049   */
00050 typedef enum
00051 {
00052   FLASH_BUSY = 1,
00053   FLASH_ERROR_WRP,
00054   FLASH_ERROR_PROGRAM,
00055   FLASH_COMPLETE,
00056   FLASH_TIMEOUT
00057 }FLASH_Status;
00058
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /** @defgroup FLASH_Exported_Constants
00062   * @{
00063   */
00064
00065 /** @defgroup FLASH_Latency
00066   * @{
00067   */
00068 #define FLASH_Latency_0                ((uint8_t)0x00)  /*!< FLASH Zero Latency cycle */
00069 #define FLASH_Latency_1                ((uint8_t)0x01)  /*!< FLASH One Latency cycle */
00070
00071 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
00072                                    ((LATENCY) == FLASH_Latency_1))
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup FLASH_Interrupts
00078   * @{
00079   */
00080
00081 #define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
00082 #define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
00083 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup FLASH_Address
00089   * @{
00090   */
00091
00092 #define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
00093 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup Option_Bytes_Write_Protection
00100   * @{
00101   */
00102
00103 #define OB_WRP_Pages0to15              ((uint32_t)0x00000001) /* Write protection of Sector0 */
00104 #define OB_WRP_Pages16to31             ((uint32_t)0x00000002) /* Write protection of Sector1 */
00105 #define OB_WRP_Pages32to47             ((uint32_t)0x00000004) /* Write protection of Sector2 */
00106 #define OB_WRP_Pages48to63             ((uint32_t)0x00000008) /* Write protection of Sector3 */
00107 #define OB_WRP_Pages64to79             ((uint32_t)0x00000010) /* Write protection of Sector4 */
00108 #define OB_WRP_Pages80to95             ((uint32_t)0x00000020) /* Write protection of Sector5 */
00109 #define OB_WRP_Pages96to111            ((uint32_t)0x00000040) /* Write protection of Sector6 */
00110 #define OB_WRP_Pages112to127           ((uint32_t)0x00000080) /* Write protection of Sector7 */
00111 #define OB_WRP_Pages128to143           ((uint32_t)0x00000100) /* Write protection of Sector8 */
00112 #define OB_WRP_Pages144to159           ((uint32_t)0x00000200) /* Write protection of Sector9 */
00113 #define OB_WRP_Pages160to175           ((uint32_t)0x00000400) /* Write protection of Sector10 */
00114 #define OB_WRP_Pages176to191           ((uint32_t)0x00000800) /* Write protection of Sector11 */
00115 #define OB_WRP_Pages192to207           ((uint32_t)0x00001000) /* Write protection of Sector12 */
00116 #define OB_WRP_Pages208to223           ((uint32_t)0x00002000) /* Write protection of Sector13 */
00117 #define OB_WRP_Pages224to239           ((uint32_t)0x00004000) /* Write protection of Sector14 */
00118 #define OB_WRP_Pages240to255           ((uint32_t)0x00008000) /* Write protection of Sector15 */
00119 #define OB_WRP_Pages256to271           ((uint32_t)0x00010000) /* Write protection of Sector16 */
00120 #define OB_WRP_Pages272to287           ((uint32_t)0x00020000) /* Write protection of Sector17 */
00121 #define OB_WRP_Pages288to303           ((uint32_t)0x00040000) /* Write protection of Sector18 */
00122 #define OB_WRP_Pages304to319           ((uint32_t)0x00080000) /* Write protection of Sector19 */
00123 #define OB_WRP_Pages320to335           ((uint32_t)0x00100000) /* Write protection of Sector20 */
00124 #define OB_WRP_Pages336to351           ((uint32_t)0x00200000) /* Write protection of Sector21 */
00125 #define OB_WRP_Pages352to367           ((uint32_t)0x00400000) /* Write protection of Sector22 */
00126 #define OB_WRP_Pages368to383           ((uint32_t)0x00800000) /* Write protection of Sector23 */
00127 #define OB_WRP_Pages384to399           ((uint32_t)0x01000000) /* Write protection of Sector24 */
00128 #define OB_WRP_Pages400to415           ((uint32_t)0x02000000) /* Write protection of Sector25 */
00129 #define OB_WRP_Pages416to431           ((uint32_t)0x04000000) /* Write protection of Sector26 */
00130 #define OB_WRP_Pages432to447           ((uint32_t)0x08000000) /* Write protection of Sector27 */
00131 #define OB_WRP_Pages448to463           ((uint32_t)0x10000000) /* Write protection of Sector28 */
00132 #define OB_WRP_Pages464to479           ((uint32_t)0x20000000) /* Write protection of Sector29 */
00133 #define OB_WRP_Pages480to495           ((uint32_t)0x40000000) /* Write protection of Sector30 */
00134 #define OB_WRP_Pages496to511           ((uint32_t)0x80000000) /* Write protection of Sector31 */
00135
00136 #define OB_WRP_AllPages                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
00137
00138 #define OB_WRP1_Pages512to527          ((uint32_t)0x00000001) /* Write protection of Sector32 */
00139 #define OB_WRP1_Pages528to543          ((uint32_t)0x00000002) /* Write protection of Sector33 */
00140 #define OB_WRP1_Pages544to559          ((uint32_t)0x00000004) /* Write protection of Sector34 */
00141 #define OB_WRP1_Pages560to575          ((uint32_t)0x00000008) /* Write protection of Sector35 */
00142 #define OB_WRP1_Pages576to591          ((uint32_t)0x00000010) /* Write protection of Sector36 */
00143 #define OB_WRP1_Pages592to607          ((uint32_t)0x00000020) /* Write protection of Sector37 */
00144 #define OB_WRP1_Pages608to623          ((uint32_t)0x00000040) /* Write protection of Sector38 */
00145 #define OB_WRP1_Pages624to639          ((uint32_t)0x00000080) /* Write protection of Sector39 */
00146 #define OB_WRP1_Pages640to655          ((uint32_t)0x00000100) /* Write protection of Sector40 */
00147 #define OB_WRP1_Pages656to671          ((uint32_t)0x00000200) /* Write protection of Sector41 */
00148 #define OB_WRP1_Pages672to687          ((uint32_t)0x00000400) /* Write protection of Sector42 */
00149 #define OB_WRP1_Pages688to703          ((uint32_t)0x00000800) /* Write protection of Sector43 */
00150 #define OB_WRP1_Pages704to719          ((uint32_t)0x00001000) /* Write protection of Sector44 */
00151 #define OB_WRP1_Pages720to735          ((uint32_t)0x00002000) /* Write protection of Sector45 */
00152 #define OB_WRP1_Pages736to751          ((uint32_t)0x00004000) /* Write protection of Sector46 */
00153 #define OB_WRP1_Pages752to767          ((uint32_t)0x00008000) /* Write protection of Sector47 */
00154 #define OB_WRP1_Pages768to783          ((uint32_t)0x00010000) /* Write protection of Sector48 */
00155 #define OB_WRP1_Pages784to799          ((uint32_t)0x00020000) /* Write protection of Sector49 */
00156 #define OB_WRP1_Pages800to815          ((uint32_t)0x00040000) /* Write protection of Sector50 */
00157 #define OB_WRP1_Pages816to831          ((uint32_t)0x00080000) /* Write protection of Sector51 */
00158 #define OB_WRP1_Pages832to847          ((uint32_t)0x00100000) /* Write protection of Sector52 */
00159 #define OB_WRP1_Pages848to863          ((uint32_t)0x00200000) /* Write protection of Sector53 */
00160 #define OB_WRP1_Pages864to879          ((uint32_t)0x00400000) /* Write protection of Sector54 */
00161 #define OB_WRP1_Pages880to895          ((uint32_t)0x00800000) /* Write protection of Sector55 */
00162 #define OB_WRP1_Pages896to911          ((uint32_t)0x01000000) /* Write protection of Sector56 */
00163 #define OB_WRP1_Pages912to927          ((uint32_t)0x02000000) /* Write protection of Sector57 */
00164 #define OB_WRP1_Pages928to943          ((uint32_t)0x04000000) /* Write protection of Sector58 */
00165 #define OB_WRP1_Pages944to959          ((uint32_t)0x08000000) /* Write protection of Sector59 */
00166 #define OB_WRP1_Pages960to975          ((uint32_t)0x10000000) /* Write protection of Sector60 */
00167 #define OB_WRP1_Pages976to991          ((uint32_t)0x20000000) /* Write protection of Sector61 */
00168 #define OB_WRP1_Pages992to1007         ((uint32_t)0x40000000) /* Write protection of Sector62 */
00169 #define OB_WRP1_Pages1008to1023        ((uint32_t)0x80000000) /* Write protection of Sector63 */
00170
00171 #define OB_WRP1_AllPages               ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
00172
00173 #define OB_WRP2_Pages1024to1039        ((uint32_t)0x00000001) /* Write protection of Sector64 */
00174 #define OB_WRP2_Pages1040to1055        ((uint32_t)0x00000002) /* Write protection of Sector65 */
00175 #define OB_WRP2_Pages1056to1071        ((uint32_t)0x00000004) /* Write protection of Sector66 */
00176 #define OB_WRP2_Pages1072to1087        ((uint32_t)0x00000008) /* Write protection of Sector67 */
00177 #define OB_WRP2_Pages1088to1103        ((uint32_t)0x00000010) /* Write protection of Sector68 */
00178 #define OB_WRP2_Pages1104to1119        ((uint32_t)0x00000020) /* Write protection of Sector69 */
00179 #define OB_WRP2_Pages1120to1135        ((uint32_t)0x00000040) /* Write protection of Sector70 */
00180 #define OB_WRP2_Pages1136to1151        ((uint32_t)0x00000080) /* Write protection of Sector71 */
00181 #define OB_WRP2_Pages1152to1167        ((uint32_t)0x00000100) /* Write protection of Sector72 */
00182 #define OB_WRP2_Pages1168to1183        ((uint32_t)0x00000200) /* Write protection of Sector73 */
00183 #define OB_WRP2_Pages1184to1199        ((uint32_t)0x00000400) /* Write protection of Sector74 */
00184 #define OB_WRP2_Pages1200to1215        ((uint32_t)0x00000800) /* Write protection of Sector75 */
00185 #define OB_WRP2_Pages1216to1231        ((uint32_t)0x00001000) /* Write protection of Sector76 */
00186 #define OB_WRP2_Pages1232to1247        ((uint32_t)0x00002000) /* Write protection of Sector77 */
00187 #define OB_WRP2_Pages1248to1263        ((uint32_t)0x00004000) /* Write protection of Sector78 */
00188 #define OB_WRP2_Pages1264to1279        ((uint32_t)0x00008000) /* Write protection of Sector79 */
00189 #define OB_WRP2_Pages1280to1295        ((uint32_t)0x00010000) /* Write protection of Sector80 */
00190 #define OB_WRP2_Pages1296to1311        ((uint32_t)0x00020000) /* Write protection of Sector81 */
00191 #define OB_WRP2_Pages1312to1327        ((uint32_t)0x00040000) /* Write protection of Sector82 */
00192 #define OB_WRP2_Pages1328to1343        ((uint32_t)0x00080000) /* Write protection of Sector83 */
00193 #define OB_WRP2_Pages1344to1359        ((uint32_t)0x00100000) /* Write protection of Sector84 */
00194 #define OB_WRP2_Pages1360to1375        ((uint32_t)0x00200000) /* Write protection of Sector85 */
00195 #define OB_WRP2_Pages1376to1391        ((uint32_t)0x00400000) /* Write protection of Sector86 */
00196 #define OB_WRP2_Pages1392to1407        ((uint32_t)0x00800000) /* Write protection of Sector87 */
00197 #define OB_WRP2_Pages1408to1423        ((uint32_t)0x01000000) /* Write protection of Sector88 */
00198 #define OB_WRP2_Pages1424to1439        ((uint32_t)0x02000000) /* Write protection of Sector89 */
00199 #define OB_WRP2_Pages1440to1455        ((uint32_t)0x04000000) /* Write protection of Sector90 */
00200 #define OB_WRP2_Pages1456to1471        ((uint32_t)0x08000000) /* Write protection of Sector91 */
00201 #define OB_WRP2_Pages1472to1487        ((uint32_t)0x10000000) /* Write protection of Sector92 */
00202 #define OB_WRP2_Pages1488to1503        ((uint32_t)0x20000000) /* Write protection of Sector93 */
00203 #define OB_WRP2_Pages1504to1519        ((uint32_t)0x40000000) /* Write protection of Sector94 */
00204 #define OB_WRP2_Pages1520to1535        ((uint32_t)0x80000000) /* Write protection of Sector95 */
00205
00206 #define OB_WRP2_AllPages               ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
00207
00208 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
00209
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup Option_Bytes_Read_Protection
00215   * @{
00216   */
00217
00218 /**
00219   * @brief  Read Protection Level
00220   */
00221 #define OB_RDP_Level_0   ((uint8_t)0xAA)
00222 #define OB_RDP_Level_1   ((uint8_t)0xBB)
00223 /*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
00224                                                 it's no more possible to go back to level 1 or 0 */
00225
00226 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
00227                           ((LEVEL) == OB_RDP_Level_1))/*||\
00228                           ((LEVEL) == OB_RDP_Level_2))*/
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup Option_Bytes_IWatchdog
00234   * @{
00235   */
00236
00237 #define OB_IWDG_SW                     ((uint8_t)0x10)  /*!< Software WDG selected */
00238 #define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware WDG selected */
00239 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00240
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup Option_Bytes_nRST_STOP
00246   * @{
00247   */
00248
00249 #define OB_STOP_NoRST                  ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
00250 #define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
00251 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup Option_Bytes_nRST_STDBY
00258   * @{
00259   */
00260
00261 #define OB_STDBY_NoRST                 ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
00262 #define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
00263 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup Option_Bytes_BOOT
00270   * @{
00271   */
00272
00273 #define OB_BOOT_BANK2                  ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
00274                                                             and this parameter is selected the device will boot from Bank 2
00275                                                             or Bank 1, depending on the activation of the bank */
00276 #define OB_BOOT_BANK1                  ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
00277                                                             and this parameter is selected the device will boot from Bank1(Default) */
00278 #define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup Option_Bytes_BOR_Level
00285   * @{
00286   */
00287
00288 #define OB_BOR_OFF       ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
00289                                               power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
00290 #define OB_BOR_LEVEL1    ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply    */
00291 #define OB_BOR_LEVEL2    ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply    */
00292 #define OB_BOR_LEVEL3    ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply    */
00293 #define OB_BOR_LEVEL4    ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply  */
00294 #define OB_BOR_LEVEL5    ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply    */
00295
00296 #define IS_OB_BOR_LEVEL(LEVEL)  (((LEVEL) == OB_BOR_OFF) || \
00297                                  ((LEVEL) == OB_BOR_LEVEL1) || \
00298                                  ((LEVEL) == OB_BOR_LEVEL2) || \
00299                                  ((LEVEL) == OB_BOR_LEVEL3) || \
00300                                  ((LEVEL) == OB_BOR_LEVEL4) || \
00301                                  ((LEVEL) == OB_BOR_LEVEL5))
00302
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup FLASH_Flags
00308   * @{
00309   */
00310
00311 #define FLASH_FLAG_BSY                 FLASH_SR_BSY  /*!< FLASH Busy flag */
00312 #define FLASH_FLAG_EOP                 FLASH_SR_EOP  /*!< FLASH End of Programming flag */
00313 #define FLASH_FLAG_ENDHV               FLASH_SR_ENHV  /*!< FLASH End of High Voltage flag */
00314 #define FLASH_FLAG_READY               FLASH_SR_READY  /*!< FLASH Ready flag after low power mode */
00315 #define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
00316 #define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR  /*!< FLASH Programming Alignment error flag */
00317 #define FLASH_FLAG_SIZERR              FLASH_SR_SIZERR  /*!< FLASH Size error flag  */
00318 #define FLASH_FLAG_OPTVERR             FLASH_SR_OPTVERR  /*!< FLASH Option Validity error flag  */
00319 #define FLASH_FLAG_OPTVERRUSR          FLASH_SR_OPTVERRUSR  /*!< FLASH Option User Validity error flag  */
00320
00321 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
00322
00323 #define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
00324                                   ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
00325                                   ((FLAG) ==  FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
00326                                   ((FLAG) ==  FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
00327                                   ((FLAG) ==  FLASH_FLAG_OPTVERRUSR))
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup FLASH_Keys
00333   * @{
00334   */
00335
00336 #define FLASH_PDKEY1               ((uint32_t)0x04152637) /*!< Flash power down key1 */
00337 #define FLASH_PDKEY2               ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
00338                                                               to unlock the RUN_PD bit in FLASH_ACR */
00339
00340 #define FLASH_PEKEY1               ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
00341 #define FLASH_PEKEY2               ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
00342                                                                to unlock the write access to the FLASH_PECR register and
00343                                                                data EEPROM */
00344
00345 #define FLASH_PRGKEY1              ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
00346 #define FLASH_PRGKEY2              ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
00347                                                                to unlock the program memory */
00348
00349 #define FLASH_OPTKEY1              ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
00350 #define FLASH_OPTKEY2              ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
00351                                                               unlock the write access to the option byte block */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup Timeout_definition
00357   * @{
00358   */
00359 #define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x8000)
00360
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup CMSIS_Legacy
00366   * @{
00367   */
00368 #if defined ( __ICCARM__ )
00369 #define InterruptType_ACTLR_DISMCYCINT_Msk         IntType_ACTLR_DISMCYCINT_Msk
00370 #endif
00371 /**
00372   * @}
00373   */
00374 /**
00375   * @}
00376   */
00377
00378 /* Exported macro ------------------------------------------------------------*/
00379 /* Exported functions ------------------------------------------------------- */
00380
00381 /**
00382   * @brief  FLASH memory functions that can be executed from FLASH.
00383   */
00384 /* FLASH Interface configuration functions ************************************/
00385 void FLASH_SetLatency(uint32_t FLASH_Latency);
00386 void FLASH_PrefetchBufferCmd(FunctionalState NewState);
00387 void FLASH_ReadAccess64Cmd(FunctionalState NewState);
00388 void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
00389
00390 /* FLASH Memory Programming functions *****************************************/
00391 void FLASH_Unlock(void);
00392 void FLASH_Lock(void);
00393 FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
00394 FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
00395
00396 /* DATA EEPROM Programming functions ******************************************/
00397 void DATA_EEPROM_Unlock(void);
00398 void DATA_EEPROM_Lock(void);
00399 void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
00400 FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
00401 FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
00402 FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
00403 FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
00404 FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
00405 FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
00406 FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
00407 FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
00408 FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
00409
00410 /* Option Bytes Programming functions *****************************************/
00411 void FLASH_OB_Unlock(void);
00412 void FLASH_OB_Lock(void);
00413 void FLASH_OB_Launch(void);
00414 FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
00415 FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
00416 FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
00417 FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
00418 FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
00419 FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
00420 FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
00421 uint8_t FLASH_OB_GetUser(void);
00422 uint32_t FLASH_OB_GetWRP(void);
00423 uint32_t FLASH_OB_GetWRP1(void);
00424 uint32_t FLASH_OB_GetWRP2(void);
00425 FlagStatus FLASH_OB_GetRDP(void);
00426 uint8_t FLASH_OB_GetBOR(void);
00427
00428 /* Interrupts and flags management functions **********************************/
00429 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
00430 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
00431 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
00432 FLASH_Status FLASH_GetStatus(void);
00433 FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
00434
00435 /**
00436   * @brief  FLASH memory functions that should be executed from internal SRAM.
00437   *         These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
00438   *         file.
00439   */
00440 __RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
00441 __RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
00442 __RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
00443 __RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
00444 __RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
00445 __RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
00446
00447 #ifdef __cplusplus
00448 }
00449 #endif
00450
00451 #endif /* __STM32L1xx_FLASH_H */
00452
00453 /**
00454   * @}
00455   */
00456
00457 /**
00458   * @}
00459   */
00460
00461 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_flash_ramfunc.c Source File

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stm32l1xx_flash_ramfunc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_flash_ramfunc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides all the Flash firmware functions which should be
00008   *          executed from the internal SRAM. This file should be placed in
00009   *          internal SRAM.
00010   *          Other FLASH memory functions that can be used from the FLASH are
00011   *          defined in the "stm32l1xx_flash.c" file.
00012 @verbatim
00013
00014     *** ARM Compiler ***
00015     --------------------
00016     [..] RAM functions are defined using the toolchain options.
00017          Functions that are be executed in RAM should reside in a separate
00018          source module. Using the 'Options for File' dialog you can simply change
00019          the 'Code / Const' area of a module to a memory space in physical RAM.
00020          Available memory areas are declared in the 'Target' tab of the
00021          Options for Target' dialog.
00022
00023     *** ICCARM Compiler ***
00024     -----------------------
00025     [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
00026
00027     *** GNU Compiler ***
00028     --------------------
00029     [..] RAM functions are defined using a specific toolchain attribute
00030          "__attribute__((section(".data")))".
00031
00032     *** TASKING Compiler ***
00033     ------------------------
00034     [..] RAM functions are defined using a specific toolchain pragma. This
00035          pragma is defined inside this file.
00036
00037 @endverbatim
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00050   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00051   *
00052   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32l1xx_flash.h"
00058
00059 /** @addtogroup STM32L1xx_StdPeriph_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup FLASH
00064   * @brief FLASH driver modules
00065   * @{
00066   */
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 static __RAM_FUNC GetStatus(void);
00074 static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);
00075
00076 /* Private functions ---------------------------------------------------------*/
00077
00078 /** @defgroup FLASH_Private_Functions
00079   * @{
00080   */
00081
00082 /** @addtogroup FLASH_Group1
00083  *
00084 @verbatim
00085 @endverbatim
00086   * @{
00087   */
00088 #if defined (  __TASKING__  )
00089 #pragma section_code_init on
00090 #endif
00091
00092 /**
00093   * @brief  Enable or disable the power down mode during RUN mode.
00094   * @note  This function can be used only when the user code is running from Internal SRAM.
00095   * @param  NewState: new state of the power down mode during RUN mode.
00096   *   This parameter can be: ENABLE or DISABLE.
00097   * @retval None
00098   */
00099 __RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)
00100 {
00101   FLASH_Status status = FLASH_COMPLETE;
00102
00103   if (NewState != DISABLE)
00104   {
00105      /* Unlock the RUN_PD bit */
00106      FLASH->PDKEYR = FLASH_PDKEY1;
00107      FLASH->PDKEYR = FLASH_PDKEY2;
00108
00109      /* Set the RUN_PD bit in  FLASH_ACR register to put Flash in power down mode */
00110      FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;
00111
00112      if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)
00113      {
00114        status = FLASH_ERROR_PROGRAM;
00115      }
00116   }
00117   else
00118   {
00119     /* Clear the RUN_PD bit in  FLASH_ACR register to put Flash in idle  mode */
00120     FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);
00121   }
00122
00123   /* Return the Write Status */
00124   return status;
00125 }
00126
00127 /**
00128   * @}
00129   */
00130
00131 /** @addtogroup FLASH_Group2
00132  *
00133 @verbatim
00134 @endverbatim
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Erases a specified 2 page in program memory in parallel.
00140   * @note   This function can be used only for STM32L1XX_HD density devices.
00141   *         To correctly run this function, the FLASH_Unlock() function
00142   *         must be called before.
00143   *         Call the FLASH_Lock() to disable the flash memory access
00144   *        (recommended to protect the FLASH memory against possible unwanted operation).
00145   * @param  Page_Address1: The page address in program memory to be erased in
00146   *         the first Bank (BANK1). This parameter should be between 0x08000000
00147   *         and 0x0802FF00.
00148   * @param  Page_Address2: The page address in program memory to be erased in
00149   *         the second Bank (BANK2). This parameter should be between 0x08030000
00150   *         and 0x0805FF00.
00151   * @note   A Page is erased in the Program memory only if the address to load
00152   *         is the start address of a page (multiple of 256 bytes).
00153   * @retval FLASH Status: The returned value can be:
00154   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00155   */
00156 FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
00157 {
00158   FLASH_Status status = FLASH_COMPLETE;
00159
00160   /* Wait for last operation to be completed */
00161   status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00162
00163   if(status == FLASH_COMPLETE)
00164   {
00165     /* If the previous operation is completed, proceed to erase the page */
00166
00167     /* Set the PARALLBANK bit */
00168     FLASH->PECR |= FLASH_PECR_PARALLBANK;
00169
00170     /* Set the ERASE bit */
00171     FLASH->PECR |= FLASH_PECR_ERASE;
00172
00173     /* Set PROG bit */
00174     FLASH->PECR |= FLASH_PECR_PROG;
00175
00176     /* Write 00000000h to the first word of the first program page to erase */
00177     *(__IO uint32_t *)Page_Address1 = 0x00000000;
00178     /* Write 00000000h to the first word of the second program page to erase */
00179     *(__IO uint32_t *)Page_Address2 = 0x00000000;
00180
00181     /* Wait for last operation to be completed */
00182     status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00183
00184     /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
00185     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
00186     FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
00187     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
00188   }
00189   /* Return the Erase Status */
00190   return status;
00191 }
00192
00193 /**
00194   * @brief  Programs a half page in program memory.
00195   * @param  Address: specifies the address to be written.
00196   * @param  pBuffer: pointer to the buffer  containing the data to be  written to
00197   *         the half page.
00198   * @note   To correctly run this function, the FLASH_Unlock() function
00199   *         must be called before.
00200   *         Call the FLASH_Lock() to disable the flash memory access
00201   *         (recommended to protect the FLASH memory against possible unwanted operation)
00202   * @note   Half page write is possible only from SRAM.
00203   * @note   If there are more than 32 words to write, after 32 words another
00204   *         Half Page programming operation starts and has to be finished.
00205   * @note   A half page is written to the program memory only if the first
00206   *         address to load is the start address of a half page (multiple of 128
00207   *         bytes) and the 31 remaining words to load are in the same half page.
00208   * @note   During the Program memory half page write all read operations are
00209   *         forbidden (this includes DMA read operations and debugger read
00210   *         operations such as breakpoints, periodic updates, etc.).
00211   * @note   If a PGAERR is set during a Program memory half page write, the
00212   *         complete write operation is aborted. Software should then reset the
00213   *         FPRG and PROG/DATA bits and restart the write operation from the
00214   *         beginning.
00215   * @retval FLASH Status: The returned value can be:
00216   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00217   */
00218 __RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)
00219 {
00220   uint32_t count = 0;
00221
00222   FLASH_Status status = FLASH_COMPLETE;
00223
00224   /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
00225      This bit prevents the interruption of multicycle instructions and therefore
00226      will increase the interrupt latency. of Cortex-M3. */
00227   SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
00228
00229   /* Wait for last operation to be completed */
00230   status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00231
00232   if(status == FLASH_COMPLETE)
00233   {
00234     /* if the previous operation is completed, proceed to program the new
00235     half page */
00236     FLASH->PECR |= FLASH_PECR_FPRG;
00237     FLASH->PECR |= FLASH_PECR_PROG;
00238
00239     /* Write one half page directly with 32 different words */
00240     while(count < 32)
00241     {
00242       *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);
00243       count ++;
00244     }
00245     /* Wait for last operation to be completed */
00246     status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00247
00248     /* if the write operation is completed, disable the PROG and FPRG bits */
00249     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
00250     FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
00251   }
00252
00253   SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
00254
00255   /* Return the Write Status */
00256   return status;
00257 }
00258
00259 /**
00260   * @brief  Programs 2 half page in program memory in parallel.
00261   * @param  Address1: specifies the first address to be written in the first bank
00262   *        (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.
00263   * @param  pBuffer1: pointer to the buffer  containing the data to be  written
00264   *         to the first half page in the first bank.
00265   * @param  Address2: specifies the second address to be written in the second bank
00266   *        (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.
00267   * @param  pBuffer2: pointer to the buffer containing the data to be  written
00268   *         to the second half page in the second bank.
00269   * @note   This function can be used only for STM32L1XX_HD density devices.
00270   * @note   To correctly run this function, the FLASH_Unlock() function
00271   *         must be called before.
00272   *         Call the FLASH_Lock() to disable the flash memory access
00273   *         (recommended to protect the FLASH memory against possible unwanted operation).
00274   * @note   Half page write is possible only from SRAM.
00275   * @note   If there are more than 32 words to write, after 32 words another
00276   *         Half Page programming operation starts and has to be finished.
00277   * @note   A half page is written to the program memory only if the first
00278   *         address to load is the start address of a half page (multiple of 128
00279   *         bytes) and the 31 remaining words to load are in the same half page.
00280   * @note   During the Program memory half page write all read operations are
00281   *         forbidden (this includes DMA read operations and debugger read
00282   *         operations such as breakpoints, periodic updates, etc.).
00283   * @note   If a PGAERR is set during a Program memory half page write, the
00284   *         complete write operation is aborted. Software should then reset the
00285   *         FPRG and PROG/DATA bits and restart the write operation from the
00286   *         beginning.
00287   * @retval FLASH Status: The returned value can be:
00288   *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00289   */
00290 __RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
00291 {
00292   uint32_t count = 0;
00293
00294   FLASH_Status status = FLASH_COMPLETE;
00295
00296   /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
00297      This bit prevents the interruption of multicycle instructions and therefore
00298      will increase the interrupt latency. of Cortex-M3. */
00299   SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
00300
00301   /* Wait for last operation to be completed */
00302   status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00303
00304   if(status == FLASH_COMPLETE)
00305   {
00306     /* If the previous operation is completed, proceed to program the new
00307        half page */
00308     FLASH->PECR |= FLASH_PECR_PARALLBANK;
00309     FLASH->PECR |= FLASH_PECR_FPRG;
00310     FLASH->PECR |= FLASH_PECR_PROG;
00311
00312     /* Write the first half page directly with 32 different words */
00313     while(count < 32)
00314     {
00315       *(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++);
00316       count ++;
00317     }
00318     count = 0;
00319     /* Write the second half page directly with 32 different words */
00320     while(count < 32)
00321     {
00322       *(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++);
00323       count ++;
00324     }
00325     /* Wait for last operation to be completed */
00326     status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00327
00328     /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
00329     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
00330     FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
00331     FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
00332   }
00333
00334   SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
00335
00336   /* Return the Write Status */
00337   return status;
00338 }
00339
00340 /**
00341   * @}
00342   */
00343
00344 /** @addtogroup FLASH_Group3
00345  *
00346 @verbatim
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Erase a double word in data memory.
00353   * @param  Address: specifies the address to be erased.
00354   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00355   *         must be called before.
00356   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00357   *         and Flash program erase control register access(recommended to protect
00358   *         the DATA_EEPROM against possible unwanted operation).
00359   * @note   Data memory double word erase is possible only from SRAM.
00360   * @note   A double word is erased to the data memory only if the first address
00361   *         to load is the start address of a double word (multiple of 8 bytes).
00362   * @note   During the Data memory double word erase, all read operations are
00363   *         forbidden (this includes DMA read operations and debugger read
00364   *         operations such as breakpoints, periodic updates, etc.).
00365   * @retval FLASH Status: The returned value can be:
00366   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00367   */
00368
00369 __RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)
00370 {
00371   FLASH_Status status = FLASH_COMPLETE;
00372
00373   /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
00374      This bit prevents the interruption of multicycle instructions and therefore
00375      will increase the interrupt latency. of Cortex-M3. */
00376   SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
00377
00378   /* Wait for last operation to be completed */
00379   status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00380
00381   if(status == FLASH_COMPLETE)
00382   {
00383     /* If the previous operation is completed, proceed to erase the next double word */
00384     /* Set the ERASE bit */
00385     FLASH->PECR |= FLASH_PECR_ERASE;
00386
00387     /* Set DATA bit */
00388     FLASH->PECR |= FLASH_PECR_DATA;
00389
00390     /* Write 00000000h to the 2 words to erase */
00391     *(__IO uint32_t *)Address = 0x00000000;
00392     Address += 4;
00393     *(__IO uint32_t *)Address = 0x00000000;
00394
00395     /* Wait for last operation to be completed */
00396     status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00397
00398     /* If the erase operation is completed, disable the ERASE and DATA bits */
00399     FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
00400     FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
00401   }
00402
00403   SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
00404
00405   /* Return the erase status */
00406   return status;
00407 }
00408
00409 /**
00410   * @brief  Write a double word in data memory without erase.
00411   * @param  Address: specifies the address to be written.
00412   * @param  Data: specifies the data to be written.
00413   * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
00414   *         must be called before.
00415   *         Call the DATA_EEPROM_Lock() to he data EEPROM access
00416   *         and Flash program erase control register access(recommended to protect
00417   *         the DATA_EEPROM against possible unwanted operation).
00418   * @note   Data memory double word write is possible only from SRAM.
00419   * @note   A data memory double word is written to the data memory only if the
00420   *         first address to load is the start address of a double word (multiple
00421   *         of double word).
00422   * @note   During the Data memory double word write, all read operations are
00423   *         forbidden (this includes DMA read operations and debugger read
00424   *         operations such as breakpoints, periodic updates, etc.).
00425   * @retval FLASH Status: The returned value can be:
00426   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00427   */
00428 __RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
00429 {
00430   FLASH_Status status = FLASH_COMPLETE;
00431
00432   /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
00433      This bit prevents the interruption of multicycle instructions and therefore
00434      will increase the interrupt latency. of Cortex-M3. */
00435   SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
00436
00437   /* Wait for last operation to be completed */
00438   status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00439
00440   if(status == FLASH_COMPLETE)
00441   {
00442     /* If the previous operation is completed, proceed to program the new data*/
00443     FLASH->PECR |= FLASH_PECR_FPRG;
00444     FLASH->PECR |= FLASH_PECR_DATA;
00445
00446     /* Write the 2 words */
00447      *(__IO uint32_t *)Address = (uint32_t) Data;
00448      Address += 4;
00449      *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
00450
00451     /* Wait for last operation to be completed */
00452     status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
00453
00454     /* If the write operation is completed, disable the FPRG and DATA bits */
00455     FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
00456     FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
00457   }
00458
00459   SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
00460
00461   /* Return the Write Status */
00462   return status;
00463 }
00464
00465 /**
00466   * @}
00467   */
00468
00469 /**
00470   * @brief  Returns the FLASH Status.
00471   * @param  None
00472   * @retval FLASH Status: The returned value can be: FLASH_BUSY,
00473   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE
00474   */
00475 static __RAM_FUNC GetStatus(void)
00476 {
00477   FLASH_Status FLASHstatus = FLASH_COMPLETE;
00478
00479   if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
00480   {
00481     FLASHstatus = FLASH_BUSY;
00482   }
00483   else
00484   {
00485     if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
00486     {
00487       FLASHstatus = FLASH_ERROR_WRP;
00488     }
00489     else
00490     {
00491       if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)
00492       {
00493         FLASHstatus = FLASH_ERROR_PROGRAM;
00494       }
00495       else
00496       {
00497         FLASHstatus = FLASH_COMPLETE;
00498       }
00499     }
00500   }
00501   /* Return the FLASH Status */
00502   return FLASHstatus;
00503 }
00504
00505 /**
00506   * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
00507   * @param  Timeout: FLASH programming Timeout
00508   * @retval FLASH Status: The returned value can be: FLASH_BUSY,
00509   *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or
00510   *   FLASH_TIMEOUT.
00511   */
00512 static __RAM_FUNC  WaitForLastOperation(uint32_t Timeout)
00513 {
00514   __IO FLASH_Status status = FLASH_COMPLETE;
00515
00516   /* Check for the FLASH Status */
00517   status = GetStatus();
00518
00519   /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
00520   while((status == FLASH_BUSY) && (Timeout != 0x00))
00521   {
00522     status = GetStatus();
00523     Timeout--;
00524   }
00525
00526   if(Timeout == 0x00 )
00527   {
00528     status = FLASH_TIMEOUT;
00529   }
00530   /* Return the operation status */
00531   return status;
00532 }
00533
00534 #if defined (  __TASKING__  )
00535 #pragma section_code_init restore
00536 #endif
00537
00538 /**
00539   * @}
00540   */
00541
00542   /**
00543   * @}
00544   */
00545
00546 /**
00547   * @}
00548   */
00549
00550 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_fsmc.c Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src

stm32l1xx_fsmc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_fsmc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the FSMC peripheral:
00009   *           + Initialization
00010   *           + Interrupts and flags management
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00023   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00024   *
00025   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00026   ******************************************************************************
00027   */
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32l1xx_fsmc.h"
00031 #include "stm32l1xx_rcc.h"
00032
00033 /** @addtogroup STM32L1xx_StdPeriph_Driver
00034   * @{
00035   */
00036
00037 /** @defgroup FSMC
00038   * @brief FSMC driver modules
00039   * @{
00040   */
00041
00042 /* Private typedef -----------------------------------------------------------*/
00043 /* Private define ------------------------------------------------------------*/
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private function prototypes -----------------------------------------------*/
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /** @defgroup FSMC_Private_Functions
00050   * @{
00051   */
00052
00053 /** @defgroup FSMC_Group1 NOR/SRAM Controller functions
00054  *  @brief   NOR/SRAM Controller functions
00055  *
00056   @verbatim
00057   ==============================================================================
00058                   ##### NOR-SRAM Controller functions #####
00059   ==============================================================================
00060     [..] The following sequence should be followed to configure the FSMC to
00061          interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
00062          NOR/SRAM Bank:
00063     (#) Enable the clock for the FSMC and associated GPIOs using the following
00064         functions:
00065         (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00066         (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
00067     (#) FSMC pins configuration
00068         (++) Connect the involved FSMC pins to AF12 using the following function
00069              GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
00070         (++) Configure these FSMC pins in alternate function mode by calling the
00071              function GPIO_Init();
00072     (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
00073         FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure; and fill the
00074         FSMC_NORSRAMInitStructure variable with the allowed values of the
00075         structure member.
00076     (#) Initialize the NOR/SRAM Controller by calling the function
00077         FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00078     (#) Then enable the NOR/SRAM Bank, for example:
00079         FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
00080     (#) At this stage you can read/write from/to the memory connected to the
00081         NOR/SRAM Bank.
00082
00083 @endverbatim
00084
00085   * @{
00086   */
00087
00088 /**
00089   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default
00090   *   reset values.
00091   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00092   *   This parameter can be one of the following values:
00093   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
00094   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
00095   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
00096   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
00097   * @retval None
00098   */
00099 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
00100 {
00101   /* Check the parameter */
00102   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00103
00104   /* FSMC_Bank1_NORSRAM1 */
00105   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
00106   {
00107     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
00108   }
00109   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
00110   else
00111   {
00112     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
00113   }
00114   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
00115   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
00116 }
00117
00118 /**
00119   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
00120   *   parameters in the FSMC_NORSRAMInitStruct.
00121   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
00122   *   structure that contains the configuration information for
00123   *   the FSMC NOR/SRAM specified Banks.
00124   * @retval None
00125   */
00126 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00127 {
00128   /* Check the parameters */
00129   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
00130   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
00131   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
00132   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
00133   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
00134   assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
00135   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
00136   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
00137   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
00138   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
00139   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
00140   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
00141   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
00142   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
00143   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
00144   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
00145   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
00146   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
00147   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
00148   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
00149
00150   /* Bank1 NOR/SRAM control register configuration */
00151   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
00152             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
00153             FSMC_NORSRAMInitStruct->FSMC_MemoryType |
00154             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
00155             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
00156             FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
00157             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
00158             FSMC_NORSRAMInitStruct->FSMC_WrapMode |
00159             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
00160             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
00161             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
00162             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
00163             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
00164
00165   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
00166   {
00167     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
00168   }
00169
00170   /* Bank1 NOR/SRAM timing register configuration */
00171   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
00172             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
00173             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
00174             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
00175             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
00176             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
00177             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
00178              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
00179
00180
00181   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
00182   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00183   {
00184     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
00185     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
00186     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
00187     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
00188     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
00189     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
00190     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
00191               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
00192               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
00193               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
00194               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
00195               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
00196                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
00197   }
00198   else
00199   {
00200     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
00201   }
00202 }
00203
00204 /**
00205   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
00206   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
00207   *   structure which will be initialized.
00208   * @retval None
00209   */
00210 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00211 {
00212   /* Reset NOR/SRAM Init structure parameters values */
00213   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
00214   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
00215   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
00216   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00217   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00218   FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00219   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00220   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
00221   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00222   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00223   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00224   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00225   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00226   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00227   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00228   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00229   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00230   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
00231   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
00232   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00233   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00234   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00235   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00236   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00237   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
00238   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
00239   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00240 }
00241
00242 /**
00243   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
00244   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00245   *   This parameter can be one of the following values:
00246   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
00247   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
00248   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
00249   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
00250   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
00251   * @retval None
00252   */
00253 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00254 {
00255   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00256   assert_param(IS_FUNCTIONAL_STATE(NewState));
00257
00258   if (NewState != DISABLE)
00259   {
00260     /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
00261     FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
00262   }
00263   else
00264   {
00265     /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
00266     FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
00267   }
00268 }
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_fsmc.h Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_fsmc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_fsmc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the FSMC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_FSMC_H
00028 #define __STM32L1xx_FSMC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup FSMC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  Timing parameters For NOR/SRAM Banks
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
00054                                              the duration of the address setup time.
00055                                              This parameter can be a value between 0 and 0xF.
00056                                              @note It is not used with synchronous NOR Flash memories. */
00057
00058   uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
00059                                              the duration of the address hold time.
00060                                              This parameter can be a value between 0 and 0xF.
00061                                              @note It is not used with synchronous NOR Flash memories.*/
00062
00063   uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
00064                                              the duration of the data setup time.
00065                                              This parameter can be a value between 0 and 0xFF.
00066                                              @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
00067
00068   uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
00069                                              the duration of the bus turnaround.
00070                                              This parameter can be a value between 0 and 0xF.
00071                                              @note It is only used for multiplexed NOR Flash memories. */
00072
00073   uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
00074                                              This parameter can be a value between 1 and 0xF.
00075                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
00076
00077   uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
00078                                              to the memory before getting the first data.
00079                                              The parameter value depends on the memory type as shown below:
00080                                               - It must be set to 0 in case of a CRAM
00081                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
00082                                               - It may assume a value between 0 and 0xF in NOR Flash memories
00083                                                 with synchronous burst mode enable */
00084
00085   uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode.
00086                                              This parameter can be a value of @ref FSMC_Access_Mode */
00087 }FSMC_NORSRAMTimingInitTypeDef;
00088
00089 /**
00090   * @brief  FSMC NOR/SRAM Init structure definition
00091   */
00092
00093 typedef struct
00094 {
00095   uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
00096                                           This parameter can be a value of @ref FSMC_NORSRAM_Bank */
00097
00098   uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
00099                                           multiplexed on the databus or not.
00100                                           This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
00101
00102   uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
00103                                           the corresponding memory bank.
00104                                           This parameter can be a value of @ref FSMC_Memory_Type */
00105
00106   uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
00107                                           This parameter can be a value of @ref FSMC_Data_Width */
00108
00109   uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
00110                                           valid only with synchronous burst Flash memories.
00111                                           This parameter can be a value of @ref FSMC_Burst_Access_Mode */
00112
00113   uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
00114                                           valid only with asynchronous Flash memories.
00115                                           This parameter can be a value of @ref FSMC_AsynchronousWait */
00116
00117   uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
00118                                           the Flash memory in burst mode.
00119                                           This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
00120
00121   uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
00122                                           memory, valid only when accessing Flash memories in burst mode.
00123                                           This parameter can be a value of @ref FSMC_Wrap_Mode */
00124
00125   uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
00126                                           clock cycle before the wait state or during the wait state,
00127                                           valid only when accessing memories in burst mode.
00128                                           This parameter can be a value of @ref FSMC_Wait_Timing */
00129
00130   uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC.
00131                                           This parameter can be a value of @ref FSMC_Write_Operation */
00132
00133   uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
00134                                           signal, valid for Flash memory access in burst mode.
00135                                           This parameter can be a value of @ref FSMC_Wait_Signal */
00136
00137   uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
00138                                           This parameter can be a value of @ref FSMC_Extended_Mode */
00139
00140   uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
00141                                           This parameter can be a value of @ref FSMC_Write_Burst */
00142
00143   FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/
00144
00145   FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/
00146 }FSMC_NORSRAMInitTypeDef;
00147
00148 /* Exported constants --------------------------------------------------------*/
00149
00150 /** @defgroup FSMC_Exported_Constants
00151   * @{
00152   */
00153
00154 /** @defgroup FSMC_NORSRAM_Bank
00155   * @{
00156   */
00157 #define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
00158 #define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
00159 #define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
00160 #define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
00161
00162 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
00163                                     ((BANK) == FSMC_Bank1_NORSRAM2) || \
00164                                     ((BANK) == FSMC_Bank1_NORSRAM3) || \
00165                                     ((BANK) == FSMC_Bank1_NORSRAM4))
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup NOR_SRAM_Controller
00171   * @{
00172   */
00173
00174 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
00175   * @{
00176   */
00177
00178 #define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
00179 #define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
00180 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
00181                           ((MUX) == FSMC_DataAddressMux_Enable))
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup FSMC_Memory_Type
00188   * @{
00189   */
00190
00191 #define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
00192 #define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
00193 #define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
00194 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
00195                                 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
00196                                 ((MEMORY) == FSMC_MemoryType_NOR))
00197
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup FSMC_Data_Width
00203   * @{
00204   */
00205
00206 #define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
00207 #define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
00208 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
00209                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))
00210
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup FSMC_Burst_Access_Mode
00216   * @{
00217   */
00218
00219 #define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000)
00220 #define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
00221 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
00222                                   ((STATE) == FSMC_BurstAccessMode_Enable))
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup FSMC_AsynchronousWait
00228   * @{
00229   */
00230 #define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
00231 #define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
00232 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
00233                                  ((STATE) == FSMC_AsynchronousWait_Enable))
00234
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup FSMC_Wait_Signal_Polarity
00240   * @{
00241   */
00242
00243 #define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
00244 #define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
00245 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
00246                                          ((POLARITY) == FSMC_WaitSignalPolarity_High))
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup FSMC_Wrap_Mode
00253   * @{
00254   */
00255
00256 #define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
00257 #define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400)
00258 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
00259                                  ((MODE) == FSMC_WrapMode_Enable))
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup FSMC_Wait_Timing
00266   * @{
00267   */
00268
00269 #define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
00270 #define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800)
00271 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
00272                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
00273
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup FSMC_Write_Operation
00279   * @{
00280   */
00281
00282 #define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
00283 #define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
00284 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
00285                                             ((OPERATION) == FSMC_WriteOperation_Enable))
00286
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup FSMC_Wait_Signal
00292   * @{
00293   */
00294
00295 #define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
00296 #define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000)
00297 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
00298                                       ((SIGNAL) == FSMC_WaitSignal_Enable))
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup FSMC_Extended_Mode
00304   * @{
00305   */
00306
00307 #define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
00308 #define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
00309
00310 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
00311                                      ((MODE) == FSMC_ExtendedMode_Enable))
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup FSMC_Write_Burst
00318   * @{
00319   */
00320
00321 #define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
00322 #define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000)
00323 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
00324                                     ((BURST) == FSMC_WriteBurst_Enable))
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup FSMC_Address_Setup_Time
00330   * @{
00331   */
00332
00333 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
00334
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup FSMC_Address_Hold_Time
00340   * @{
00341   */
00342
00343 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup FSMC_Data_Setup_Time
00350   * @{
00351   */
00352
00353 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
00354
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup FSMC_Bus_Turn_around_Duration
00360   * @{
00361   */
00362
00363 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
00364
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup FSMC_CLK_Division
00370   * @{
00371   */
00372
00373 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup FSMC_Data_Latency
00380   * @{
00381   */
00382
00383 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
00384
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup FSMC_Access_Mode
00390   * @{
00391   */
00392
00393 #define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
00394 #define FSMC_AccessMode_B                               ((uint32_t)0x10000000)
00395 #define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
00396 #define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
00397 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
00398                                    ((MODE) == FSMC_AccessMode_B) || \
00399                                    ((MODE) == FSMC_AccessMode_C) || \
00400                                    ((MODE) == FSMC_AccessMode_D))
00401
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /* Exported macro ------------------------------------------------------------*/
00415 /* Exported functions ------------------------------------------------------- */
00416 /* NOR/SRAM Controller functions **********************************************/
00417 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
00418 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00419 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00420 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00421
00422 #ifdef __cplusplus
00423 }
00424 #endif
00425
00426 #endif /*__STM32L1xx_FSMC_H */
00427 /**
00428   * @}
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_gpio.c Source File

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stm32l1xx_gpio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the GPIO peripheral:
00009   *           + Initialization and Configuration
00010   *           + GPIO Read and Write
00011   *           + GPIO Alternate functions configuration
00012   *
00013   *  @verbatim
00014     ===========================================================================
00015                          ##### How to use this driver #####
00016     ===========================================================================
00017       [..]
00018       (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
00019       (#) Configure the GPIO pin(s) using GPIO_Init()
00020           Four possible configuration are available for each pin:
00021          (++) Input: Floating, Pull-up, Pull-down.
00022          (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
00023               Open Drain (Pull-up, Pull-down or no Pull).
00024               In output mode, the speed is configurable: Very Low, Low,
00025               Medium or High.
00026          (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
00027               Open Drain (Pull-up, Pull-down or no Pull).
00028          (++) Analog: required mode when a pin is to be used as ADC channel,
00029               DAC output or comparator input.
00030       (#) Peripherals alternate function:
00031           (++) For ADC, DAC and comparators, configure the desired pin in
00032                analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
00033           (++) For other peripherals (TIM, USART...):
00034               (+++) Connect the pin to the desired peripherals' Alternate
00035                     Function (AF) using GPIO_PinAFConfig() function.
00036               (+++) Configure the desired pin in alternate function mode using
00037                     GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
00038               (+++) Select the type, pull-up/pull-down and output speed via
00039                     GPIO_PuPd, GPIO_OType and GPIO_Speed members.
00040               (+++) Call GPIO_Init() function.
00041       (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
00042       (#) To set/reset the level of a pin configured in output mode use
00043           GPIO_SetBits()/GPIO_ResetBits()
00044       (#) During and just after reset, the alternate functions are not
00045           active and the GPIO pins are configured in input floating mode
00046           (except JTAG pins).
00047       (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
00048           general-purpose (PC14 and PC15, respectively) when the LSE
00049           oscillator is off. The LSE has priority over the GPIO function.
00050       (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00051           general-purpose PH0 and PH1, respectively, when the HSE
00052           oscillator is off. The HSE has priority over the GPIO function.
00053     @endverbatim
00054   *
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00059   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00060   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00061   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00062   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00063   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00064   *
00065   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00066   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00067   *
00068   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00069   ******************************************************************************
00070   */
00071
00072 /* Includes ------------------------------------------------------------------*/
00073 #include "stm32l1xx_gpio.h"
00074 #include "stm32l1xx_rcc.h"
00075
00076 /** @addtogroup STM32L1xx_StdPeriph_Driver
00077   * @{
00078   */
00079
00080 /** @defgroup GPIO
00081   * @brief GPIO driver modules
00082   * @{
00083   */
00084
00085 /* Private typedef -----------------------------------------------------------*/
00086 /* Private define ------------------------------------------------------------*/
00087 /* Private macro -------------------------------------------------------------*/
00088 /* Private variables ---------------------------------------------------------*/
00089 /* Private function prototypes -----------------------------------------------*/
00090 /* Private functions ---------------------------------------------------------*/
00091
00092 /** @defgroup GPIO_Private_Functions
00093   * @{
00094   */
00095
00096 /** @defgroup GPIO_Group1 Initialization and Configuration
00097  *  @brief   Initialization and Configuration
00098  *
00099 @verbatim
00100  ===============================================================================
00101                     ##### Initialization and Configuration #####
00102  ===============================================================================
00103
00104 @endverbatim
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  Deinitializes the GPIOx peripheral registers to their default reset
00110   *         values.
00111   *         By default, The GPIO pins are configured in input floating mode
00112   *         (except JTAG pins).
00113   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00114   * @retval None
00115   */
00116 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
00117 {
00118   /* Check the parameters */
00119   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00120
00121   if(GPIOx == GPIOA)
00122   {
00123     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
00124     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
00125   }
00126   else if(GPIOx == GPIOB)
00127   {
00128     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
00129     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
00130   }
00131   else if(GPIOx == GPIOC)
00132   {
00133     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
00134     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
00135   }
00136   else if(GPIOx == GPIOD)
00137   {
00138     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
00139     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
00140   }
00141   else if(GPIOx == GPIOE)
00142   {
00143     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
00144     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
00145   }
00146   else if(GPIOx == GPIOF)
00147   {
00148     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
00149     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
00150   }
00151   else if(GPIOx == GPIOG)
00152   {
00153     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, ENABLE);
00154     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, DISABLE);
00155   }
00156   else
00157   {
00158     if(GPIOx == GPIOH)
00159     {
00160       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
00161       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
00162     }
00163   }
00164 }
00165
00166 /**
00167   * @brief  Initializes the GPIOx peripheral according to the specified
00168   *         parameters in the GPIO_InitStruct.
00169   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00170   * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
00171   *         contains the configuration information for the specified GPIO
00172   *         peripheral.
00173
00174   * @retval None
00175   */
00176 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
00177 {
00178   uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
00179
00180   /* Check the parameters */
00181   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00182   assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
00183   assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
00184   assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
00185
00186   /* -------------------------Configure the port pins---------------- */
00187   /*-- GPIO Mode Configuration --*/
00188   for (pinpos = 0x00; pinpos < 0x10; pinpos++)
00189   {
00190     pos = ((uint32_t)0x01) << pinpos;
00191
00192     /* Get the port pins position */
00193     currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
00194
00195     if (currentpin == pos)
00196     {
00197       GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
00198
00199       GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
00200
00201       if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
00202       {
00203         /* Check Speed mode parameters */
00204         assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
00205
00206         /* Speed mode configuration */
00207         GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
00208         GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
00209
00210         /*Check Output mode parameters */
00211         assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
00212
00213         /* Output mode configuration */
00214         GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
00215         GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
00216       }
00217
00218       /* Pull-up Pull down resistor configuration */
00219       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
00220       GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
00221     }
00222   }
00223 }
00224
00225 /**
00226   * @brief  Fills each GPIO_InitStruct member with its default value.
00227   * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
00228   *         be initialized.
00229   * @retval None
00230   */
00231 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
00232 {
00233   /* Reset GPIO init structure parameters values */
00234   GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
00235   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
00236   GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;
00237   GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
00238   GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
00239 }
00240
00241 /**
00242   * @brief  Locks GPIO Pins configuration registers.
00243   *         The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00244   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00245   *         The configuration of the locked GPIO pins can no longer be modified
00246   *         until the next reset.
00247   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00248   * @param  GPIO_Pin: specifies the port bit to be written.
00249   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00250   * @retval None
00251   */
00252 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00253 {
00254   __IO uint32_t tmp = 0x00010000;
00255
00256   /* Check the parameters */
00257   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00258   assert_param(IS_GPIO_PIN(GPIO_Pin));
00259
00260   tmp |= GPIO_Pin;
00261   /* Set LCKK bit */
00262   GPIOx->LCKR = tmp;
00263   /* Reset LCKK bit */
00264   GPIOx->LCKR =  GPIO_Pin;
00265   /* Set LCKK bit */
00266   GPIOx->LCKR = tmp;
00267   /* Read LCKK bit*/
00268   tmp = GPIOx->LCKR;
00269   /* Read LCKK bit*/
00270   tmp = GPIOx->LCKR;
00271 }
00272
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup GPIO_Group2 GPIO Read and Write
00278  *  @brief   GPIO Read and Write
00279  *
00280 @verbatim
00281  ===============================================================================
00282                       ##### GPIO Read and Write #####
00283  ===============================================================================
00284
00285 @endverbatim
00286   * @{
00287   */
00288
00289 /**
00290   * @brief  Reads the specified input port pin.
00291   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00292   * @param  GPIO_Pin: specifies the port bit to read.
00293   *   This parameter can be GPIO_Pin_x where x can be (0..15).
00294   * @retval The input port pin value.
00295   */
00296 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00297 {
00298   uint8_t bitstatus = 0x00;
00299
00300   /* Check the parameters */
00301   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00302   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00303
00304   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
00305   {
00306     bitstatus = (uint8_t)Bit_SET;
00307   }
00308   else
00309   {
00310     bitstatus = (uint8_t)Bit_RESET;
00311   }
00312   return bitstatus;
00313 }
00314
00315 /**
00316   * @brief  Reads the specified GPIO input data port.
00317   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00318   * @retval GPIO input data port value.
00319   */
00320 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
00321 {
00322   /* Check the parameters */
00323   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00324
00325   return ((uint16_t)GPIOx->IDR);
00326 }
00327
00328 /**
00329   * @brief  Reads the specified output data port bit.
00330   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00331   * @param  GPIO_Pin: Specifies the port bit to read.
00332   *   This parameter can be GPIO_Pin_x where x can be (0..15).
00333   * @retval The output port pin value.
00334   */
00335 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00336 {
00337   uint8_t bitstatus = 0x00;
00338
00339   /* Check the parameters */
00340   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00341   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00342
00343   if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
00344   {
00345     bitstatus = (uint8_t)Bit_SET;
00346   }
00347   else
00348   {
00349     bitstatus = (uint8_t)Bit_RESET;
00350   }
00351   return bitstatus;
00352 }
00353
00354 /**
00355   * @brief  Reads the specified GPIO output data port.
00356   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00357   * @retval GPIO output data port value.
00358   */
00359 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
00360 {
00361   /* Check the parameters */
00362   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00363
00364   return ((uint16_t)GPIOx->ODR);
00365 }
00366
00367 /**
00368   * @brief  Sets the selected data port bits.
00369   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00370   * @param  GPIO_Pin: specifies the port bits to be written.
00371   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00372   * @note  This functions uses GPIOx_BSRR register to allow atomic read/modify
00373   *        accesses. In this way, there is no risk of an IRQ occurring between
00374   *        the read and the modify access.
00375   * @retval None
00376   */
00377 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00378 {
00379   /* Check the parameters */
00380   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00381   assert_param(IS_GPIO_PIN(GPIO_Pin));
00382
00383   GPIOx->BSRRL = GPIO_Pin;
00384 }
00385
00386 /**
00387   * @brief  Clears the selected data port bits.
00388   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00389   * @param  GPIO_Pin: specifies the port bits to be written.
00390   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00391   * @note  This functions uses GPIOx_BSRR register to allow atomic read/modify
00392   *        accesses. In this way, there is no risk of an IRQ occurring between
00393   *        the read and the modify access.
00394   * @retval None
00395   */
00396 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00397 {
00398   /* Check the parameters */
00399   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00400   assert_param(IS_GPIO_PIN(GPIO_Pin));
00401
00402   GPIOx->BSRRH = GPIO_Pin;
00403 }
00404
00405 /**
00406   * @brief  Sets or clears the selected data port bit.
00407   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00408   * @param  GPIO_Pin: specifies the port bit to be written.
00409   *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
00410   * @param  BitVal: specifies the value to be written to the selected bit.
00411   *   This parameter can be one of the BitAction enum values:
00412   *     @arg Bit_RESET: to clear the port pin
00413   *     @arg Bit_SET: to set the port pin
00414   * @retval None
00415   */
00416 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
00417 {
00418   /* Check the parameters */
00419   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00420   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00421   assert_param(IS_GPIO_BIT_ACTION(BitVal));
00422
00423   if (BitVal != Bit_RESET)
00424   {
00425     GPIOx->BSRRL = GPIO_Pin;
00426   }
00427   else
00428   {
00429     GPIOx->BSRRH = GPIO_Pin ;
00430   }
00431 }
00432
00433 /**
00434   * @brief  Writes data to the specified GPIO data port.
00435   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00436   * @param  PortVal: specifies the value to be written to the port output data
00437   *                  register.
00438   * @retval None
00439   */
00440 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
00441 {
00442   /* Check the parameters */
00443   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00444
00445   GPIOx->ODR = PortVal;
00446 }
00447
00448 /**
00449   * @brief  Toggles the specified GPIO pins..
00450   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00451   * @param  GPIO_Pin: Specifies the pins to be toggled.
00452   * @retval None
00453   */
00454 void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00455 {
00456   /* Check the parameters */
00457   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00458
00459   GPIOx->ODR ^= GPIO_Pin;
00460 }
00461
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
00467  *  @brief   GPIO Alternate functions configuration functions
00468  *
00469 @verbatim
00470  ===============================================================================
00471           ##### GPIO Alternate functions configuration functions #####
00472  ===============================================================================
00473
00474 @endverbatim
00475   * @{
00476   */
00477
00478 /**
00479   * @brief  Changes the mapping of the specified pin.
00480   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
00481   * @param  GPIO_PinSource: specifies the pin for the Alternate function.
00482   *   This parameter can be GPIO_PinSourcex where x can be (0..15).
00483   * @param  GPIO_AFSelection: selects the pin to used as Alternat function.
00484   *   This parameter can be one of the following values:
00485   *     @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization
00486   *     @arg GPIO_AF_MCO: Microcontroller clock output
00487   *     @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,
00488   *                           512 Hz clock output (with an LSE oscillator of 32.768 kHz)
00489   *     @arg GPIO_AF_WKUP: wakeup
00490   *     @arg GPIO_AF_SWJ: SWJ (SW and JTAG)
00491   *     @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
00492   *     @arg GPIO_AF_TIM2c: Connect TIM2 pins to AF1
00493   *     @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
00494   *     @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
00495   *     @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
00496   *     @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
00497   *     @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
00498   *     @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
00499   *     @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
00500   *     @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
00501   *     @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
00502   *     @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
00503   *     @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
00504   *     @arg GPIO_AF_USART1: Connect USART1 pins to AF7
00505   *     @arg GPIO_AF_USART2: Connect USART2 pins to AF7
00506   *     @arg GPIO_AF_USART3: Connect USART3 pins to AF7
00507   *     @arg GPIO_AF_UART4: Connect UART4 pins to AF8
00508   *     @arg GPIO_AF_UART5: Connect UART5 pins to AF8
00509   *     @arg GPIO_AF_USB: Connect USB pins to AF10
00510   *     @arg GPIO_AF_LCD: Connect LCD pins to AF11
00511   *     @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
00512   *     @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
00513   *     @arg GPIO_AF_RI: Connect RI pins to AF14
00514   *     @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal
00515   * @note The pin should already been configured in Alternate Function mode(AF)
00516   *        using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
00517   * @note Please refer to the Alternate function mapping table in the device
00518   *        datasheet for the detailed mapping of the system and peripherals'
00519   *        alternate function I/O pins.
00520   * @note EVENTOUT is not mapped on PH0, PH1 and PH2.
00521   * @retval None
00522   */
00523 void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
00524 {
00525   uint32_t temp = 0x00;
00526   uint32_t temp_2 = 0x00;
00527
00528   /* Check the parameters */
00529   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00530   assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
00531   assert_param(IS_GPIO_AF(GPIO_AF));
00532
00533   temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
00534   GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
00535   temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
00536   GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
00537 }
00538
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
00551 /**
00552   * @}
00553   */
00554 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_gpio.h Source File

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stm32l1xx_gpio.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the GPIO
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_GPIO_H
00028 #define __STM32L1xx_GPIO_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup GPIO
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
00048                                     ((PERIPH) == GPIOB) || \
00049                                     ((PERIPH) == GPIOC) || \
00050                                     ((PERIPH) == GPIOD) || \
00051                                     ((PERIPH) == GPIOE) || \
00052                                     ((PERIPH) == GPIOH) || \
00053                                     ((PERIPH) == GPIOF) || \
00054                                     ((PERIPH) == GPIOG))
00055
00056 /** @defgroup Configuration_Mode_enumeration
00057   * @{
00058   */
00059 typedef enum
00060 {
00061   GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
00062   GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
00063   GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
00064   GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
00065 }GPIOMode_TypeDef;
00066 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
00067                             ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup Output_type_enumeration
00073   * @{
00074   */
00075 typedef enum
00076 { GPIO_OType_PP = 0x00,
00077   GPIO_OType_OD = 0x01
00078 }GPIOOType_TypeDef;
00079 #define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
00080
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup Output_Maximum_frequency_enumeration
00086   * @{
00087   */
00088 typedef enum
00089 {
00090   GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */
00091   GPIO_Speed_2MHz   = 0x01, /*!< Low Speed */
00092   GPIO_Speed_10MHz  = 0x02, /*!< Medium Speed */
00093   GPIO_Speed_40MHz  = 0x03  /*!< High Speed */
00094 }GPIOSpeed_TypeDef;
00095 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
00096                               ((SPEED) == GPIO_Speed_10MHz)||  ((SPEED) == GPIO_Speed_40MHz))
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
00102   * @{
00103   */
00104 typedef enum
00105 { GPIO_PuPd_NOPULL = 0x00,
00106   GPIO_PuPd_UP     = 0x01,
00107   GPIO_PuPd_DOWN   = 0x02
00108 }GPIOPuPd_TypeDef;
00109 #define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
00110                             ((PUPD) == GPIO_PuPd_DOWN))
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup Bit_SET_and_Bit_RESET_enumeration
00116   * @{
00117   */
00118 typedef enum
00119 { Bit_RESET = 0,
00120   Bit_SET
00121 }BitAction;
00122 #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
00123
00124 /**
00125   * @}
00126   */
00127
00128 /**
00129   * @brief  GPIO Init structure definition
00130   */
00131 typedef struct
00132 {
00133   uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
00134                                        This parameter can be any value of @ref GPIO_pins_define */
00135
00136   GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
00137                                        This parameter can be a value of @ref GPIOMode_TypeDef */
00138
00139   GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
00140                                        This parameter can be a value of @ref GPIOSpeed_TypeDef */
00141
00142   GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
00143                                        This parameter can be a value of @ref GPIOOType_TypeDef */
00144
00145   GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00146                                        This parameter can be a value of @ref GPIOPuPd_TypeDef */
00147 }GPIO_InitTypeDef;
00148
00149 /* Exported constants --------------------------------------------------------*/
00150
00151 /** @defgroup GPIO_Exported_Constants
00152   * @{
00153   */
00154
00155 /** @defgroup GPIO_pins_define
00156   * @{
00157   */
00158 #define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
00159 #define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
00160 #define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
00161 #define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
00162 #define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
00163 #define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
00164 #define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
00165 #define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
00166 #define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
00167 #define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
00168 #define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
00169 #define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
00170 #define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
00171 #define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
00172 #define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
00173 #define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
00174 #define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
00175
00176 #define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
00177 #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
00178                               ((PIN) == GPIO_Pin_1) || \
00179                               ((PIN) == GPIO_Pin_2) || \
00180                               ((PIN) == GPIO_Pin_3) || \
00181                               ((PIN) == GPIO_Pin_4) || \
00182                               ((PIN) == GPIO_Pin_5) || \
00183                               ((PIN) == GPIO_Pin_6) || \
00184                               ((PIN) == GPIO_Pin_7) || \
00185                               ((PIN) == GPIO_Pin_8) || \
00186                               ((PIN) == GPIO_Pin_9) || \
00187                               ((PIN) == GPIO_Pin_10) || \
00188                               ((PIN) == GPIO_Pin_11) || \
00189                               ((PIN) == GPIO_Pin_12) || \
00190                               ((PIN) == GPIO_Pin_13) || \
00191                               ((PIN) == GPIO_Pin_14) || \
00192                               ((PIN) == GPIO_Pin_15))
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup GPIO_Pin_sources
00198   * @{
00199   */
00200 #define GPIO_PinSource0            ((uint8_t)0x00)
00201 #define GPIO_PinSource1            ((uint8_t)0x01)
00202 #define GPIO_PinSource2            ((uint8_t)0x02)
00203 #define GPIO_PinSource3            ((uint8_t)0x03)
00204 #define GPIO_PinSource4            ((uint8_t)0x04)
00205 #define GPIO_PinSource5            ((uint8_t)0x05)
00206 #define GPIO_PinSource6            ((uint8_t)0x06)
00207 #define GPIO_PinSource7            ((uint8_t)0x07)
00208 #define GPIO_PinSource8            ((uint8_t)0x08)
00209 #define GPIO_PinSource9            ((uint8_t)0x09)
00210 #define GPIO_PinSource10           ((uint8_t)0x0A)
00211 #define GPIO_PinSource11           ((uint8_t)0x0B)
00212 #define GPIO_PinSource12           ((uint8_t)0x0C)
00213 #define GPIO_PinSource13           ((uint8_t)0x0D)
00214 #define GPIO_PinSource14           ((uint8_t)0x0E)
00215 #define GPIO_PinSource15           ((uint8_t)0x0F)
00216
00217 #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
00218                                        ((PINSOURCE) == GPIO_PinSource1) || \
00219                                        ((PINSOURCE) == GPIO_PinSource2) || \
00220                                        ((PINSOURCE) == GPIO_PinSource3) || \
00221                                        ((PINSOURCE) == GPIO_PinSource4) || \
00222                                        ((PINSOURCE) == GPIO_PinSource5) || \
00223                                        ((PINSOURCE) == GPIO_PinSource6) || \
00224                                        ((PINSOURCE) == GPIO_PinSource7) || \
00225                                        ((PINSOURCE) == GPIO_PinSource8) || \
00226                                        ((PINSOURCE) == GPIO_PinSource9) || \
00227                                        ((PINSOURCE) == GPIO_PinSource10) || \
00228                                        ((PINSOURCE) == GPIO_PinSource11) || \
00229                                        ((PINSOURCE) == GPIO_PinSource12) || \
00230                                        ((PINSOURCE) == GPIO_PinSource13) || \
00231                                        ((PINSOURCE) == GPIO_PinSource14) || \
00232                                        ((PINSOURCE) == GPIO_PinSource15))
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup GPIO_Alternat_function_selection_define
00238   * @{
00239   */
00240
00241 /**
00242   * @brief  AF 0 selection
00243   */
00244 #define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /*!< RTC 50/60 Hz Alternate Function mapping */
00245 #define GPIO_AF_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping */
00246 #define GPIO_AF_RTC_AF1       ((uint8_t)0x00)  /*!< RTC_AF1 Alternate Function mapping */
00247 #define GPIO_AF_WKUP          ((uint8_t)0x00)  /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */
00248 #define GPIO_AF_SWJ           ((uint8_t)0x00)  /*!< SWJ (SW and JTAG) Alternate Function mapping */
00249 #define GPIO_AF_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping */
00250
00251 /**
00252   * @brief  AF 1 selection
00253   */
00254 #define GPIO_AF_TIM2          ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */
00255 /**
00256   * @brief  AF 2 selection
00257   */
00258 #define GPIO_AF_TIM3          ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */
00259 #define GPIO_AF_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
00260 #define GPIO_AF_TIM5          ((uint8_t)0x02)  /*!< TIM5 Alternate Function mapping */
00261 /**
00262   * @brief  AF 3 selection
00263   */
00264 #define GPIO_AF_TIM9           ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */
00265 #define GPIO_AF_TIM10          ((uint8_t)0x03)  /*!< TIM10 Alternate Function mapping */
00266 #define GPIO_AF_TIM11          ((uint8_t)0x03)  /*!< TIM11 Alternate Function mapping */
00267 /**
00268   * @brief  AF 4 selection
00269   */
00270 #define GPIO_AF_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */
00271 #define GPIO_AF_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */
00272 /**
00273   * @brief  AF 5 selection
00274   */
00275 #define GPIO_AF_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00276 #define GPIO_AF_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00277 /**
00278   * @brief  AF 6 selection
00279   */
00280 #define GPIO_AF_SPI3          ((uint8_t)0x06)  /*!< SPI3 Alternate Function mapping */
00281 /**
00282   * @brief  AF 7 selection
00283   */
00284 #define GPIO_AF_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping */
00285 #define GPIO_AF_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping */
00286 #define GPIO_AF_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping */
00287 /**
00288   * @brief  AF 8 selection
00289   */
00290 #define GPIO_AF_UART4         ((uint8_t)0x08)  /*!< UART4 Alternate Function mapping */
00291 #define GPIO_AF_UART5         ((uint8_t)0x08)  /*!< UART5 Alternate Function mapping */
00292 /**
00293   * @brief  AF 10 selection
00294   */
00295 #define GPIO_AF_USB           ((uint8_t)0xA)  /*!< USB Full speed device  Alternate Function mapping */
00296 /**
00297   * @brief  AF 11 selection
00298   */
00299 #define GPIO_AF_LCD           ((uint8_t)0x0B)  /*!< LCD Alternate Function mapping */
00300 /**
00301   * @brief  AF 12 selection
00302   */
00303 #define GPIO_AF_FSMC           ((uint8_t)0x0C)  /*!< FSMC Alternate Function mapping */
00304 #define GPIO_AF_SDIO           ((uint8_t)0x0C)  /*!< SDIO Alternate Function mapping */
00305 /**
00306   * @brief  AF 14 selection
00307   */
00308 #define GPIO_AF_RI            ((uint8_t)0x0E)  /*!< RI Alternate Function mapping */
00309
00310 /**
00311   * @brief  AF 15 selection
00312   */
00313 #define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /*!< EVENTOUT Alternate Function mapping */
00314
00315 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO)    || \
00316                           ((AF) == GPIO_AF_RTC_AF1)  || ((AF) == GPIO_AF_WKUP)   || \
00317                           ((AF) == GPIO_AF_SWJ)      || ((AF) == GPIO_AF_TRACE)  || \
00318                           ((AF) == GPIO_AF_TIM2)     || ((AF)== GPIO_AF_TIM3)    || \
00319                           ((AF) == GPIO_AF_TIM4)     || ((AF)== GPIO_AF_TIM9)    || \
00320                           ((AF) == GPIO_AF_TIM10)    || ((AF)== GPIO_AF_TIM11)   || \
00321                           ((AF) == GPIO_AF_I2C1)     || ((AF) == GPIO_AF_I2C2)   || \
00322                           ((AF) == GPIO_AF_SPI1)     || ((AF) == GPIO_AF_SPI2)   || \
00323                           ((AF) == GPIO_AF_USART1)   || ((AF) == GPIO_AF_USART2) || \
00324                           ((AF) == GPIO_AF_USART3)   || ((AF) == GPIO_AF_USB)    || \
00325                           ((AF) == GPIO_AF_LCD)      || ((AF) == GPIO_AF_RI)     || \
00326                           ((AF) == GPIO_AF_TIM5)     || ((AF) == GPIO_AF_SPI3)   || \
00327                           ((AF) == GPIO_AF_UART4)    || ((AF) == GPIO_AF_UART5)  || \
00328                           ((AF) == GPIO_AF_FSMC)     || ((AF) == GPIO_AF_SDIO)   || \
00329                           ((AF) == GPIO_AF_EVENTOUT))
00330
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup GPIO_Legacy
00336   * @{
00337   */
00338
00339 #define GPIO_Mode_AIN GPIO_Mode_AN
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /* Exported macro ------------------------------------------------------------*/
00350 /* Exported functions ------------------------------------------------------- */
00351
00352 /*  Function used to set the GPIO configuration to the default reset state ****/
00353 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
00354
00355 /* Initialization and Configuration functions *********************************/
00356 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
00357 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
00358 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00359
00360 /* GPIO Read and Write functions **********************************************/
00361 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00362 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
00363 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00364 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
00365 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00366 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00367 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
00368 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
00369 void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00370
00371 /* GPIO Alternate functions configuration functions ***************************/
00372 void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
00373
00374 #ifdef __cplusplus
00375 }
00376 #endif
00377
00378 #endif /*__STM32L1xx_GPIO_H */
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_i2c.c Source File

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stm32l1xx_i2c.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Inter-integrated circuit (I2C)
00009   *           + Initialization and Configuration
00010   *           + Data transfers
00011   *           + PEC management
00012   *           + DMA transfers management
00013   *           + Interrupts, events and flags management
00014   *
00015   *  @verbatim
00016   *
00017   * ============================================================================
00018   *                    ##### How to use this driver #####
00019   * ============================================================================
00020    [..]
00021    (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
00022        function for I2C1 or I2C2.
00023    (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using
00024        RCC_AHBPeriphClockCmd() function.
00025    (#) Peripherals alternate function:
00026        (++) Connect the pin to the desired peripherals' Alternate
00027             Function (AF) using GPIO_PinAFConfig() function.
00028        (++) Configure the desired pin in alternate function by:
00029             GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
00030        (++) Select the type, pull-up/pull-down and output speed via
00031             GPIO_PuPd, GPIO_OType and GPIO_Speed members
00032        (++) Call GPIO_Init() function.
00033    (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
00034        Address using the I2C_Init() function.
00035    (#) Optionally you can enable/configure the following parameters without
00036        re-initialization (i.e there is no need to call again I2C_Init() function):
00037        (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
00038        (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
00039        (++) Enable the general call using the I2C_GeneralCallCmd() function.
00040        (++) Enable the clock stretching using I2C_StretchClockCmd() function.
00041        (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
00042             function.
00043        (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
00044        (++) For SMBus Mode:
00045             (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function.
00046             (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function.
00047    (#) Enable the NVIC and the corresponding interrupt using the function
00048        I2C_ITConfig() if you need to use interrupt mode.
00049    (#) When using the DMA mode
00050       (++) Configure the DMA using DMA_Init() function.
00051       (++) Active the needed channel Request using I2C_DMACmd() or
00052            I2C_DMALastTransferCmd() function.
00053    (#) Enable the I2C using the I2C_Cmd() function.
00054    (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
00055        transfers.
00056     @endverbatim
00057   ******************************************************************************
00058   * @attention
00059   *
00060   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00061   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00062   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00063   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00064   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00065   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00066   *
00067   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00068   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00069   *
00070   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00071   ******************************************************************************
00072   */
00073
00074 /* Includes ------------------------------------------------------------------*/
00075 #include "stm32l1xx_i2c.h"
00076 #include "stm32l1xx_rcc.h"
00077
00078
00079 /** @addtogroup STM32L1xx_StdPeriph_Driver
00080   * @{
00081   */
00082
00083 /** @defgroup I2C
00084   * @brief I2C driver modules
00085   * @{
00086   */
00087
00088 /* Private typedef -----------------------------------------------------------*/
00089 /* Private define ------------------------------------------------------------*/
00090
00091 #define CR1_CLEAR_MASK          ((uint16_t)0xFBF5)      /*<! I2C registers Masks */
00092 #define FLAG_MASK               ((uint32_t)0x00FFFFFF)  /*<! I2C FLAG mask */
00093 #define ITEN_MASK               ((uint32_t)0x07000000)  /*<! I2C Interrupt Enable mask */
00094
00095 /* Private macro -------------------------------------------------------------*/
00096 /* Private variables ---------------------------------------------------------*/
00097 /* Private function prototypes -----------------------------------------------*/
00098 /* Private functions ---------------------------------------------------------*/
00099
00100 /** @defgroup I2C_Private_Functions
00101   * @{
00102   */
00103
00104 /** @defgroup I2C_Group1 Initialization and Configuration functions
00105  *  @brief   Initialization and Configuration functions
00106  *
00107 @verbatim
00108  ===============================================================================
00109             ##### Initialization and Configuration functions #####
00110  ===============================================================================
00111
00112 @endverbatim
00113   * @{
00114   */
00115
00116 /**
00117   * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
00118   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00119   * @retval None
00120   */
00121 void I2C_DeInit(I2C_TypeDef* I2Cx)
00122 {
00123   /* Check the parameters */
00124   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00125
00126   if (I2Cx == I2C1)
00127   {
00128     /* Enable I2C1 reset state */
00129     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
00130     /* Release I2C1 from reset state */
00131     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
00132   }
00133   else
00134   {
00135     /* Enable I2C2 reset state */
00136     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
00137     /* Release I2C2 from reset state */
00138     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
00139   }
00140 }
00141
00142 /**
00143   * @brief  Initializes the I2Cx peripheral according to the specified
00144   *         parameters in the I2C_InitStruct.
00145   * @note   To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency
00146   *         (I2C peripheral input clock) must be a multiple of 10 MHz.
00147   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00148   * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
00149   *   contains the configuration information for the specified I2C peripheral.
00150   * @retval None
00151   */
00152 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
00153 {
00154   uint16_t tmpreg = 0, freqrange = 0;
00155   uint16_t result = 0x04;
00156   uint32_t pclk1 = 8000000;
00157   RCC_ClocksTypeDef  rcc_clocks;
00158   /* Check the parameters */
00159   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00160   assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
00161   assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
00162   assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
00163   assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
00164   assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
00165   assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
00166
00167 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
00168   /* Get the I2Cx CR2 value */
00169   tmpreg = I2Cx->CR2;
00170   /* Clear frequency FREQ[5:0] bits */
00171   tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
00172   /* Get pclk1 frequency value */
00173   RCC_GetClocksFreq(&rcc_clocks);
00174   pclk1 = rcc_clocks.PCLK1_Frequency;
00175   /* Set frequency bits depending on pclk1 value */
00176   freqrange = (uint16_t)(pclk1 / 1000000);
00177   tmpreg |= freqrange;
00178   /* Write to I2Cx CR2 */
00179   I2Cx->CR2 = tmpreg;
00180
00181 /*---------------------------- I2Cx CCR Configuration ------------------------*/
00182   /* Disable the selected I2C peripheral to configure TRISE */
00183   I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
00184   /* Reset tmpreg value */
00185   /* Clear F/S, DUTY and CCR[11:0] bits */
00186   tmpreg = 0;
00187
00188   /* Configure speed in standard mode */
00189   if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
00190   {
00191     /* Standard mode speed calculate */
00192     result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
00193     /* Test if CCR value is under 0x4*/
00194     if (result < 0x04)
00195     {
00196       /* Set minimum allowed value */
00197       result = 0x04;
00198     }
00199     /* Set speed value for standard mode */
00200     tmpreg |= result;
00201     /* Set Maximum Rise Time for standard mode */
00202     I2Cx->TRISE = freqrange + 1;
00203   }
00204   /* Configure speed in fast mode */
00205   /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
00206      input clock) must be a multiple of 10 MHz */
00207   else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
00208   {
00209     if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
00210     {
00211       /* Fast mode speed calculate: Tlow/Thigh = 2 */
00212       result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
00213     }
00214     else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
00215     {
00216       /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
00217       result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
00218       /* Set DUTY bit */
00219       result |= I2C_DutyCycle_16_9;
00220     }
00221
00222     /* Test if CCR value is under 0x1*/
00223     if ((result & I2C_CCR_CCR) == 0)
00224     {
00225       /* Set minimum allowed value */
00226       result |= (uint16_t)0x0001;
00227     }
00228     /* Set speed value and set F/S bit for fast mode */
00229     tmpreg |= (uint16_t)(result | I2C_CCR_FS);
00230     /* Set Maximum Rise Time for fast mode */
00231     I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
00232   }
00233
00234   /* Write to I2Cx CCR */
00235   I2Cx->CCR = tmpreg;
00236   /* Enable the selected I2C peripheral */
00237   I2Cx->CR1 |= I2C_CR1_PE;
00238
00239 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
00240   /* Get the I2Cx CR1 value */
00241   tmpreg = I2Cx->CR1;
00242   /* Clear ACK, SMBTYPE and  SMBUS bits */
00243   tmpreg &= CR1_CLEAR_MASK;
00244   /* Configure I2Cx: mode and acknowledgement */
00245   /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
00246   /* Set ACK bit according to I2C_Ack value */
00247   tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
00248   /* Write to I2Cx CR1 */
00249   I2Cx->CR1 = tmpreg;
00250
00251 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
00252   /* Set I2Cx Own Address1 and acknowledged address */
00253   I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
00254 }
00255
00256 /**
00257   * @brief  Fills each I2C_InitStruct member with its default value.
00258   * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
00259   * @retval None
00260   */
00261 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
00262 {
00263 /*---------------- Reset I2C init structure parameters values ----------------*/
00264   /* initialize the I2C_ClockSpeed member */
00265   I2C_InitStruct->I2C_ClockSpeed = 5000;
00266   /* Initialize the I2C_Mode member */
00267   I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
00268   /* Initialize the I2C_DutyCycle member */
00269   I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
00270   /* Initialize the I2C_OwnAddress1 member */
00271   I2C_InitStruct->I2C_OwnAddress1 = 0;
00272   /* Initialize the I2C_Ack member */
00273   I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
00274   /* Initialize the I2C_AcknowledgedAddress member */
00275   I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00276 }
00277
00278 /**
00279   * @brief  Enables or disables the specified I2C peripheral.
00280   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00281   * @param  NewState: new state of the I2Cx peripheral.
00282   *   This parameter can be: ENABLE or DISABLE.
00283   * @retval None
00284   */
00285 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00286 {
00287   /* Check the parameters */
00288   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00289   assert_param(IS_FUNCTIONAL_STATE(NewState));
00290   if (NewState != DISABLE)
00291   {
00292     /* Enable the selected I2C peripheral */
00293     I2Cx->CR1 |= I2C_CR1_PE;
00294   }
00295   else
00296   {
00297     /* Disable the selected I2C peripheral */
00298     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
00299   }
00300 }
00301
00302 /**
00303   * @brief  Generates I2Cx communication START condition.
00304   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00305   * @param  NewState: new state of the I2C START condition generation.
00306   *   This parameter can be: ENABLE or DISABLE.
00307   * @retval None.
00308   */
00309 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
00310 {
00311   /* Check the parameters */
00312   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00313   assert_param(IS_FUNCTIONAL_STATE(NewState));
00314   if (NewState != DISABLE)
00315   {
00316     /* Generate a START condition */
00317     I2Cx->CR1 |= I2C_CR1_START;
00318   }
00319   else
00320   {
00321     /* Disable the START condition generation */
00322     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
00323   }
00324 }
00325
00326 /**
00327   * @brief  Generates I2Cx communication STOP condition.
00328   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00329   * @param  NewState: new state of the I2C STOP condition generation.
00330   *   This parameter can be: ENABLE or DISABLE.
00331   * @retval None.
00332   */
00333 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
00334 {
00335   /* Check the parameters */
00336   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00337   assert_param(IS_FUNCTIONAL_STATE(NewState));
00338   if (NewState != DISABLE)
00339   {
00340     /* Generate a STOP condition */
00341     I2Cx->CR1 |= I2C_CR1_STOP;
00342   }
00343   else
00344   {
00345     /* Disable the STOP condition generation */
00346     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
00347   }
00348 }
00349
00350 /**
00351   * @brief  Enables or disables the specified I2C acknowledge feature.
00352   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00353   * @param  NewState: new state of the I2C Acknowledgement.
00354   *   This parameter can be: ENABLE or DISABLE.
00355   * @retval None.
00356   */
00357 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
00358 {
00359   /* Check the parameters */
00360   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00361   assert_param(IS_FUNCTIONAL_STATE(NewState));
00362   if (NewState != DISABLE)
00363   {
00364     /* Enable the acknowledgement */
00365     I2Cx->CR1 |= I2C_CR1_ACK;
00366   }
00367   else
00368   {
00369     /* Disable the acknowledgement */
00370     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
00371   }
00372 }
00373
00374 /**
00375   * @brief  Configures the specified I2C own address2.
00376   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00377   * @param  Address: specifies the 7bit I2C own address2.
00378   * @retval None.
00379   */
00380 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
00381 {
00382   uint16_t tmpreg = 0;
00383
00384   /* Check the parameters */
00385   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00386
00387   /* Get the old register value */
00388   tmpreg = I2Cx->OAR2;
00389
00390   /* Reset I2Cx Own address2 bit [7:1] */
00391   tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
00392
00393   /* Set I2Cx Own address2 */
00394   tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
00395
00396   /* Store the new register value */
00397   I2Cx->OAR2 = tmpreg;
00398 }
00399
00400 /**
00401   * @brief  Enables or disables the specified I2C dual addressing mode.
00402   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00403   * @param  NewState: new state of the I2C dual addressing mode.
00404   *   This parameter can be: ENABLE or DISABLE.
00405   * @retval None
00406   */
00407 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00408 {
00409   /* Check the parameters */
00410   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00411   assert_param(IS_FUNCTIONAL_STATE(NewState));
00412   if (NewState != DISABLE)
00413   {
00414     /* Enable dual addressing mode */
00415     I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
00416   }
00417   else
00418   {
00419     /* Disable dual addressing mode */
00420     I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
00421   }
00422 }
00423
00424 /**
00425   * @brief  Enables or disables the specified I2C general call feature.
00426   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00427   * @param  NewState: new state of the I2C General call.
00428   *   This parameter can be: ENABLE or DISABLE.
00429   * @retval None
00430   */
00431 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00432 {
00433   /* Check the parameters */
00434   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00435   assert_param(IS_FUNCTIONAL_STATE(NewState));
00436   if (NewState != DISABLE)
00437   {
00438     /* Enable generall call */
00439     I2Cx->CR1 |= I2C_CR1_ENGC;
00440   }
00441   else
00442   {
00443     /* Disable generall call */
00444     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
00445   }
00446 }
00447
00448 /**
00449   * @brief  Enables or disables the specified I2C software reset.
00450   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00451   * @param  NewState: new state of the I2C software reset.
00452   *   This parameter can be: ENABLE or DISABLE.
00453   * @retval None
00454   */
00455 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00456 {
00457   /* Check the parameters */
00458   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00459   assert_param(IS_FUNCTIONAL_STATE(NewState));
00460   if (NewState != DISABLE)
00461   {
00462     /* Peripheral under reset */
00463     I2Cx->CR1 |= I2C_CR1_SWRST;
00464   }
00465   else
00466   {
00467     /* Peripheral not under reset */
00468     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
00469   }
00470 }
00471
00472 /**
00473   * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
00474   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00475   * @param  I2C_SMBusAlert: specifies SMBAlert pin level.
00476   *   This parameter can be one of the following values:
00477   *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
00478   *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
00479   * @retval None
00480   */
00481 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00485   assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
00486   if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
00487   {
00488     /* Drive the SMBusAlert pin Low */
00489     I2Cx->CR1 |= I2C_SMBusAlert_Low;
00490   }
00491   else
00492   {
00493     /* Drive the SMBusAlert pin High  */
00494     I2Cx->CR1 &= I2C_SMBusAlert_High;
00495   }
00496 }
00497
00498 /**
00499   * @brief  Enables or disables the specified I2C ARP.
00500   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00501   * @param  NewState: new state of the I2Cx ARP.
00502   *   This parameter can be: ENABLE or DISABLE.
00503   * @retval None
00504   */
00505 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00506 {
00507   /* Check the parameters */
00508   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00509   assert_param(IS_FUNCTIONAL_STATE(NewState));
00510   if (NewState != DISABLE)
00511   {
00512     /* Enable the selected I2C ARP */
00513     I2Cx->CR1 |= I2C_CR1_ENARP;
00514   }
00515   else
00516   {
00517     /* Disable the selected I2C ARP */
00518     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
00519   }
00520 }
00521
00522 /**
00523   * @brief  Enables or disables the specified I2C Clock stretching.
00524   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00525   * @param  NewState: new state of the I2Cx Clock stretching.
00526   *   This parameter can be: ENABLE or DISABLE.
00527   * @retval None
00528   */
00529 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00530 {
00531   /* Check the parameters */
00532   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00533   assert_param(IS_FUNCTIONAL_STATE(NewState));
00534   if (NewState == DISABLE)
00535   {
00536     /* Enable the selected I2C Clock stretching */
00537     I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
00538   }
00539   else
00540   {
00541     /* Disable the selected I2C Clock stretching */
00542     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
00543   }
00544 }
00545
00546 /**
00547   * @brief  Selects the specified I2C fast mode duty cycle.
00548   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00549   * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
00550   *   This parameter can be one of the following values:
00551   *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
00552   *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
00553   * @retval None
00554   */
00555 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
00556 {
00557   /* Check the parameters */
00558   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00559   assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
00560   if (I2C_DutyCycle != I2C_DutyCycle_16_9)
00561   {
00562     /* I2C fast mode Tlow/Thigh=2 */
00563     I2Cx->CCR &= I2C_DutyCycle_2;
00564   }
00565   else
00566   {
00567     /* I2C fast mode Tlow/Thigh=16/9 */
00568     I2Cx->CCR |= I2C_DutyCycle_16_9;
00569   }
00570 }
00571
00572 /**
00573   * @brief  Transmits the address byte to select the slave device.
00574   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00575   * @param  Address: specifies the slave address which will be transmitted.
00576   * @param  I2C_Direction: specifies whether the I2C device will be a
00577   *   Transmitter or a Receiver. This parameter can be one of the following values:
00578   *     @arg I2C_Direction_Transmitter: Transmitter mode
00579   *     @arg I2C_Direction_Receiver: Receiver mode
00580   * @retval None.
00581   */
00582 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
00583 {
00584   /* Check the parameters */
00585   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00586   assert_param(IS_I2C_DIRECTION(I2C_Direction));
00587   /* Test on the direction to set/reset the read/write bit */
00588   if (I2C_Direction != I2C_Direction_Transmitter)
00589   {
00590     /* Set the address bit0 for read */
00591     Address |= I2C_OAR1_ADD0;
00592   }
00593   else
00594   {
00595     /* Reset the address bit0 for write */
00596     Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
00597   }
00598   /* Send the address */
00599   I2Cx->DR = Address;
00600 }
00601
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup I2C_Group2 Data transfers functions
00607  *  @brief   Data transfers functions
00608  *
00609 @verbatim
00610  ===============================================================================
00611                     ##### Data transfers functions #####
00612  ===============================================================================
00613
00614 @endverbatim
00615   * @{
00616   */
00617
00618 /**
00619   * @brief  Sends a data byte through the I2Cx peripheral.
00620   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00621   * @param  Data: Byte to be transmitted.
00622   * @retval None
00623   */
00624 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
00625 {
00626   /* Check the parameters */
00627   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00628   /* Write in the DR register the data to be sent */
00629   I2Cx->DR = Data;
00630 }
00631
00632 /**
00633   * @brief  Returns the most recent received data by the I2Cx peripheral.
00634   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00635   * @retval The value of the received data.
00636   */
00637 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
00638 {
00639   /* Check the parameters */
00640   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00641   /* Return the data in the DR register */
00642   return (uint8_t)I2Cx->DR;
00643 }
00644
00645 /**
00646   * @brief  Selects the specified I2C NACK position in master receiver mode.
00647   *         This function is useful in I2C Master Receiver mode when the number
00648   *         of data to be received is equal to 2. In this case, this function
00649   *         should be called (with parameter I2C_NACKPosition_Next) before data
00650   *         reception starts,as described in the 2-byte reception procedure
00651   *         recommended in Reference Manual in Section: Master receiver.
00652   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00653   * @param  I2C_NACKPosition: specifies the NACK position.
00654   *   This parameter can be one of the following values:
00655   *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
00656   *          received byte.
00657   *     @arg I2C_NACKPosition_Current: indicates that current byte is the last
00658   *          received byte.
00659   * @note    This function configures the same bit (POS) as I2C_PECPositionConfig()
00660   *          but is intended to be used in I2C mode while I2C_PECPositionConfig()
00661   *          is intended to used in SMBUS mode.
00662   *
00663   * @retval None
00664   */
00665 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
00666 {
00667   /* Check the parameters */
00668   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00669   assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
00670
00671   /* Check the input parameter */
00672   if (I2C_NACKPosition == I2C_NACKPosition_Next)
00673   {
00674     /* Next byte in shift register is the last received byte */
00675     I2Cx->CR1 |= I2C_NACKPosition_Next;
00676   }
00677   else
00678   {
00679     /* Current byte in shift register is the last received byte */
00680     I2Cx->CR1 &= I2C_NACKPosition_Current;
00681   }
00682 }
00683
00684 /**
00685   * @}
00686   */
00687
00688 /** @defgroup I2C_Group3 PEC management functions
00689  *  @brief   PEC management functions
00690  *
00691 @verbatim
00692  ===============================================================================
00693                     ##### PEC management functions #####
00694  ===============================================================================
00695
00696 @endverbatim
00697   * @{
00698   */
00699
00700 /**
00701   * @brief  Enables or disables the specified I2C PEC transfer.
00702   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00703   * @param  NewState: new state of the I2C PEC transmission.
00704   *   This parameter can be: ENABLE or DISABLE.
00705   * @retval None
00706   */
00707 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
00708 {
00709   /* Check the parameters */
00710   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00711   assert_param(IS_FUNCTIONAL_STATE(NewState));
00712   if (NewState != DISABLE)
00713   {
00714     /* Enable the selected I2C PEC transmission */
00715     I2Cx->CR1 |= I2C_CR1_PEC;
00716   }
00717   else
00718   {
00719     /* Disable the selected I2C PEC transmission */
00720     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
00721   }
00722 }
00723
00724 /**
00725   * @brief  Selects the specified I2C PEC position.
00726   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00727   * @param  I2C_PECPosition: specifies the PEC position.
00728   *   This parameter can be one of the following values:
00729   *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
00730   *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
00731   * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
00732   *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
00733   *          is intended to used in I2C mode.
00734   * @retval None
00735   */
00736 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
00737 {
00738   /* Check the parameters */
00739   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00740   assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
00741   if (I2C_PECPosition == I2C_PECPosition_Next)
00742   {
00743     /* Next byte in shift register is PEC */
00744     I2Cx->CR1 |= I2C_PECPosition_Next;
00745   }
00746   else
00747   {
00748     /* Current byte in shift register is PEC */
00749     I2Cx->CR1 &= I2C_PECPosition_Current;
00750   }
00751 }
00752
00753 /**
00754   * @brief  Enables or disables the PEC value calculation of the transferred bytes.
00755   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00756   * @param  NewState: new state of the I2Cx PEC value calculation.
00757   *   This parameter can be: ENABLE or DISABLE.
00758   * @retval None
00759   */
00760 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
00761 {
00762   /* Check the parameters */
00763   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00764   assert_param(IS_FUNCTIONAL_STATE(NewState));
00765   if (NewState != DISABLE)
00766   {
00767     /* Enable the selected I2C PEC calculation */
00768     I2Cx->CR1 |= I2C_CR1_ENPEC;
00769   }
00770   else
00771   {
00772     /* Disable the selected I2C PEC calculation */
00773     I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
00774   }
00775 }
00776
00777 /**
00778   * @brief  Returns the PEC value for the specified I2C.
00779   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00780   * @retval The PEC value.
00781   */
00782 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
00783 {
00784   /* Check the parameters */
00785   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00786   /* Return the selected I2C PEC value */
00787   return ((I2Cx->SR2) >> 8);
00788 }
00789
00790 /**
00791   * @}
00792   */
00793
00794 /** @defgroup I2C_Group4 DMA transfers management functions
00795  *  @brief   DMA transfers management functions
00796  *
00797 @verbatim
00798  ===============================================================================
00799                ##### DMA transfers management functions #####
00800  ===============================================================================
00801   [..] This section provides functions allowing to configure the I2C DMA channels
00802        requests.
00803 @endverbatim
00804   * @{
00805   */
00806
00807 /**
00808   * @brief  Enables or disables the specified I2C DMA requests.
00809   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00810   * @param  NewState: new state of the I2C DMA transfer.
00811   *   This parameter can be: ENABLE or DISABLE.
00812   * @retval None
00813   */
00814 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00815 {
00816   /* Check the parameters */
00817   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00818   assert_param(IS_FUNCTIONAL_STATE(NewState));
00819   if (NewState != DISABLE)
00820   {
00821     /* Enable the selected I2C DMA requests */
00822     I2Cx->CR2 |= I2C_CR2_DMAEN;
00823   }
00824   else
00825   {
00826     /* Disable the selected I2C DMA requests */
00827     I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
00828   }
00829 }
00830
00831 /**
00832   * @brief  Specifies that the next DMA transfer is the last one.
00833   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00834   * @param  NewState: new state of the I2C DMA last transfer.
00835   *   This parameter can be: ENABLE or DISABLE.
00836   * @retval None
00837   */
00838 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00839 {
00840   /* Check the parameters */
00841   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00842   assert_param(IS_FUNCTIONAL_STATE(NewState));
00843   if (NewState != DISABLE)
00844   {
00845     /* Next DMA transfer is the last transfer */
00846     I2Cx->CR2 |= I2C_CR2_LAST;
00847   }
00848   else
00849   {
00850     /* Next DMA transfer is not the last transfer */
00851     I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
00852   }
00853 }
00854
00855 /**
00856   * @}
00857   */
00858
00859 /** @defgroup I2C_Group5 Interrupts events and flags management functions
00860  *  @brief   Interrupts, events and flags management functions
00861  *
00862 @verbatim
00863  ===============================================================================
00864         ##### Interrupts, events and flags management functions #####
00865  ===============================================================================
00866     [..] This section provides functions allowing to configure the I2C Interrupts
00867          sources and check or clear the flags or pending bits status.
00868          The user should identify which mode will be used in his application to manage
00869          the communication: Polling mode, Interrupt mode or DMA mode.
00870
00871
00872                 ##### I2C State Monitoring Functions #####
00873  ===============================================================================
00874     [..]This I2C driver provides three different ways for I2C state monitoring
00875         depending on the application requirements and constraints:
00876
00877
00878      ***. Basic state monitoring (Using I2C_CheckEvent() function) ***
00879      -----------------------------------------------------------------
00880     [..]It compares the status registers (SR1 and SR2) content to a given event
00881         (can be the combination of one or more flags).
00882         It returns SUCCESS if the current status includes the given flags
00883         and returns ERROR if one or more flags are missing in the current status.
00884
00885     (+) When to use
00886         (++) This function is suitable for most applications as well as for
00887              startup activity since the events are fully described in the product
00888              reference manual (RM0038).
00889         (++) It is also suitable for users who need to define their own events.
00890     (+) Limitations
00891         (++) If an error occurs (ie. error flags are set besides to the monitored
00892              flags), the I2C_CheckEvent() function may return SUCCESS despite
00893              the communication hold or corrupted real state.
00894              In this case, it is advised to use error interrupts to monitor
00895              the error events and handle them in the interrupt IRQ handler.
00896         -@@- For error management, it is advised to use the following functions:
00897              (+@@) I2C_ITConfig() to configure and enable the error interrupts
00898                    (I2C_IT_ERR).
00899              (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
00900                    Where x is the peripheral instance (I2C1, I2C2 ...).
00901              (+@@) I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the
00902                    I2Cx_ER_IRQHandler() function in order to determine which error occurred.
00903              (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00904                    and/or I2C_GenerateStop() in order to clear the error flag and source
00905                    and return to correct  communication status.
00906
00907      *** Advanced state monitoring (Using the function I2C_GetLastEvent()) ***
00908      -------------------------------------------------------------------------
00909     [..] Using the function I2C_GetLastEvent() which returns the image of both status
00910         registers in a single word (uint32_t) (Status Register 2 value is shifted left
00911         by 16 bits and concatenated to Status Register 1).
00912
00913     (+) When to use
00914        (++) This function is suitable for the same applications above but it
00915             allows to overcome the mentioned limitation of I2C_GetFlagStatus()
00916             function.
00917        (++) The returned value could be compared to events already defined in
00918             the library (stm32l1xx_i2c.h) or to custom values defined by user.
00919             This function is suitable when multiple flags are monitored at the
00920             same time.
00921        (++) At the opposite of I2C_CheckEvent() function, this function allows
00922             user to choose when an event is accepted (when all events flags are
00923             set and no other flags are set or just when the needed flags are set
00924             like I2C_CheckEvent() function.
00925
00926      (+) Limitations
00927          (++) User may need to define his own events.
00928          (++) Same remark concerning the error management is applicable for this
00929               function if user decides to check only regular communication flags
00930               (and ignores error flags).
00931
00932
00933     *** Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ***
00934     ----------------------------------------------------------------------------
00935     [..] Using the function I2C_GetFlagStatus() which simply returns the status of
00936          one single flag (ie. I2C_FLAG_RXNE ...).
00937          (+) When to use
00938              (++) This function could be used for specific applications or in debug
00939                   phase.
00940              (++) It is suitable when only one flag checking is needed (most I2C
00941                   events are monitored through multiple flags).
00942          (+) Limitations:
00943              (++) When calling this function, the Status register is accessed.
00944                   Some flags are cleared when the status register is accessed.
00945                   So checking the status of one Flag, may clear other ones.
00946              (++) Function may need to be called twice or more in order to monitor
00947                   one single event.
00948
00949     [..] For detailed description of Events, please refer to section I2C_Events in
00950          stm32l1xx_i2c.h file.
00951
00952 @endverbatim
00953   * @{
00954   */
00955
00956 /**
00957   * @brief  Reads the specified I2C register and returns its value.
00958   * @param  I2C_Register: specifies the register to read.
00959   *   This parameter can be one of the following values:
00960   *     @arg I2C_Register_CR1:  CR1 register.
00961   *     @arg I2C_Register_CR2:   CR2 register.
00962   *     @arg I2C_Register_OAR1:  OAR1 register.
00963   *     @arg I2C_Register_OAR2:  OAR2 register.
00964   *     @arg I2C_Register_DR:    DR register.
00965   *     @arg I2C_Register_SR1:   SR1 register.
00966   *     @arg I2C_Register_SR2:   SR2 register.
00967   *     @arg I2C_Register_CCR:   CCR register.
00968   *     @arg I2C_Register_TRISE: TRISE register.
00969   * @retval The value of the read register.
00970   */
00971 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
00972 {
00973   __IO uint32_t tmp = 0;
00974
00975   /* Check the parameters */
00976   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00977   assert_param(IS_I2C_REGISTER(I2C_Register));
00978
00979   tmp = (uint32_t) I2Cx;
00980   tmp += I2C_Register;
00981
00982   /* Return the selected register value */
00983   return (*(__IO uint16_t *) tmp);
00984 }
00985
00986 /**
00987   * @brief  Enables or disables the specified I2C interrupts.
00988   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00989   * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
00990   *   This parameter can be any combination of the following values:
00991   *     @arg I2C_IT_BUF: Buffer interrupt mask
00992   *     @arg I2C_IT_EVT: Event interrupt mask
00993   *     @arg I2C_IT_ERR: Error interrupt mask
00994   * @param  NewState: new state of the specified I2C interrupts.
00995   *   This parameter can be: ENABLE or DISABLE.
00996   * @retval None
00997   */
00998 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
00999 {
01000   /* Check the parameters */
01001   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01002   assert_param(IS_FUNCTIONAL_STATE(NewState));
01003   assert_param(IS_I2C_CONFIG_IT(I2C_IT));
01004
01005   if (NewState != DISABLE)
01006   {
01007     /* Enable the selected I2C interrupts */
01008     I2Cx->CR2 |= I2C_IT;
01009   }
01010   else
01011   {
01012     /* Disable the selected I2C interrupts */
01013     I2Cx->CR2 &= (uint16_t)~I2C_IT;
01014   }
01015 }
01016
01017 /*
01018  ===============================================================================
01019                           1. Basic state monitoring
01020  ===============================================================================
01021  */
01022
01023 /**
01024   * @brief  Checks whether the last I2Cx Event is equal to the one passed
01025   *   as parameter.
01026   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01027   * @param  I2C_EVENT: specifies the event to be checked.
01028   *   This parameter can be one of the following values:
01029   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED:                   EV1
01030   *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED:                      EV1
01031   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED:             EV1
01032   *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED:                EV1
01033   *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED:                    EV1
01034   *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED:                                 EV2
01035   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF):              EV2
01036   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL):            EV2
01037   *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED:                              EV3
01038   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF):           EV3
01039   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL):         EV3
01040   *     @arg I2C_EVENT_SLAVE_ACK_FAILURE:                                 EV3_2
01041   *     @arg I2C_EVENT_SLAVE_STOP_DETECTED:                                 EV4
01042   *     @arg I2C_EVENT_MASTER_MODE_SELECT:                                  EV5
01043   *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED:                    EV6
01044   *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED:                       EV6
01045   *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED:                                EV7
01046   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING:                            EV8
01047   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED:                           EV8_2
01048   *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10:                               EV9
01049   * @note For detailed description of Events, please refer to section
01050   *        I2C_Events in stm32l1xx_i2c.h file.
01051   * @retval An ErrorStatus enumeration value:
01052   * - SUCCESS: Last event is equal to the I2C_EVENT
01053   * - ERROR: Last event is different from the I2C_EVENT
01054   */
01055 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
01056 {
01057   uint32_t lastevent = 0;
01058   uint32_t flag1 = 0, flag2 = 0;
01059   ErrorStatus status = ERROR;
01060
01061   /* Check the parameters */
01062   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01063   assert_param(IS_I2C_EVENT(I2C_EVENT));
01064
01065   /* Read the I2Cx status register */
01066   flag1 = I2Cx->SR1;
01067   flag2 = I2Cx->SR2;
01068   flag2 = flag2 << 16;
01069
01070   /* Get the last event value from I2C status register */
01071   lastevent = (flag1 | flag2) & FLAG_MASK;
01072
01073   /* Check whether the last event contains the I2C_EVENT */
01074   if ((lastevent & I2C_EVENT) == I2C_EVENT)
01075   {
01076     /* SUCCESS: last event is equal to I2C_EVENT */
01077     status = SUCCESS;
01078   }
01079   else
01080   {
01081     /* ERROR: last event is different from I2C_EVENT */
01082     status = ERROR;
01083   }
01084   /* Return status */
01085   return status;
01086 }
01087
01088 /*
01089  ===============================================================================
01090                           2. Advanced state monitoring
01091  ===============================================================================
01092  */
01093
01094 /**
01095   * @brief  Returns the last I2Cx Event.
01096   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01097   *
01098   * @note For detailed description of Events, please refer to section
01099   *    I2C_Events in stm32l1xx_i2c.h file.
01100   *
01101   * @retval The last event
01102   */
01103 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
01104 {
01105   uint32_t lastevent = 0;
01106   uint32_t flag1 = 0, flag2 = 0;
01107
01108   /* Check the parameters */
01109   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01110
01111   /* Read the I2Cx status register */
01112   flag1 = I2Cx->SR1;
01113   flag2 = I2Cx->SR2;
01114   flag2 = flag2 << 16;
01115
01116   /* Get the last event value from I2C status register */
01117   lastevent = (flag1 | flag2) & FLAG_MASK;
01118
01119   /* Return status */
01120   return lastevent;
01121 }
01122
01123 /*
01124  ===============================================================================
01125                           3. Flag-based state monitoring
01126  ===============================================================================
01127  */
01128
01129 /**
01130   * @brief  Checks whether the specified I2C flag is set or not.
01131   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01132   * @param  I2C_FLAG: specifies the flag to check.
01133   *   This parameter can be one of the following values:
01134   *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
01135   *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
01136   *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
01137   *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
01138   *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
01139   *     @arg I2C_FLAG_BUSY: Bus busy flag
01140   *     @arg I2C_FLAG_MSL: Master/Slave flag
01141   *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
01142   *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
01143   *     @arg I2C_FLAG_PECERR: PEC error in reception flag
01144   *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
01145   *     @arg I2C_FLAG_AF: Acknowledge failure flag
01146   *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
01147   *     @arg I2C_FLAG_BERR: Bus error flag
01148   *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
01149   *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
01150   *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
01151   *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
01152   *     @arg I2C_FLAG_BTF: Byte transfer finished flag
01153   *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
01154   *   Address matched flag (Slave mode)"ENDAD"
01155   *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
01156   * @retval The new state of I2C_FLAG (SET or RESET).
01157   */
01158 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
01159 {
01160   FlagStatus bitstatus = RESET;
01161   __IO uint32_t i2creg = 0, i2cxbase = 0;
01162
01163   /* Check the parameters */
01164   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01165   assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
01166
01167   /* Get the I2Cx peripheral base address */
01168   i2cxbase = (uint32_t)I2Cx;
01169
01170   /* Read flag register index */
01171   i2creg = I2C_FLAG >> 28;
01172
01173   /* Get bit[23:0] of the flag */
01174   I2C_FLAG &= FLAG_MASK;
01175
01176   if(i2creg != 0)
01177   {
01178     /* Get the I2Cx SR1 register address */
01179     i2cxbase += 0x14;
01180   }
01181   else
01182   {
01183     /* Flag in I2Cx SR2 Register */
01184     I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
01185     /* Get the I2Cx SR2 register address */
01186     i2cxbase += 0x18;
01187   }
01188
01189   if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
01190   {
01191     /* I2C_FLAG is set */
01192     bitstatus = SET;
01193   }
01194   else
01195   {
01196     /* I2C_FLAG is reset */
01197     bitstatus = RESET;
01198   }
01199
01200   /* Return the I2C_FLAG status */
01201   return  bitstatus;
01202 }
01203
01204 /**
01205   * @brief  Clears the I2Cx's pending flags.
01206   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01207   * @param  I2C_FLAG: specifies the flag to clear.
01208   *   This parameter can be any combination of the following values:
01209   *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
01210   *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
01211   *     @arg I2C_FLAG_PECERR: PEC error in reception flag
01212   *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
01213   *     @arg I2C_FLAG_AF: Acknowledge failure flag
01214   *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
01215   *     @arg I2C_FLAG_BERR: Bus error flag
01216   *
01217
01218   *@note STOPF (STOP detection) is cleared by software sequence: a read operation
01219   *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
01220   *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
01221   *@note ADD10 (10-bit header sent) is cleared by software sequence: a read
01222   *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
01223   *     second byte of the address in DR register.
01224   *@note BTF (Byte Transfer Finished) is cleared by software sequence: a read
01225   *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
01226   *     read/write to I2C_DR register (I2C_SendData()).
01227   *@note ADDR (Address sent) is cleared by software sequence: a read operation to
01228   *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
01229   *     I2C_SR2 register ((void)(I2Cx->SR2)).
01230   *@note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
01231   *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
01232   *     register  (I2C_SendData()).
01233   * @retval None
01234   */
01235 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
01236 {
01237   uint32_t flagpos = 0;
01238   /* Check the parameters */
01239   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01240   assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
01241   /* Get the I2C flag position */
01242   flagpos = I2C_FLAG & FLAG_MASK;
01243   /* Clear the selected I2C flag */
01244   I2Cx->SR1 = (uint16_t)~flagpos;
01245 }
01246
01247 /**
01248   * @brief  Checks whether the specified I2C interrupt has occurred or not.
01249   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01250   * @param  I2C_IT: specifies the interrupt source to check.
01251   *   This parameter can be one of the following values:
01252   *     @arg I2C_IT_SMBALERT: SMBus Alert flag
01253   *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
01254   *     @arg I2C_IT_PECERR: PEC error in reception flag
01255   *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
01256   *     @arg I2C_IT_AF: Acknowledge failure flag
01257   *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
01258   *     @arg I2C_IT_BERR: Bus error flag
01259   *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
01260   *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
01261   *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
01262   *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
01263   *     @arg I2C_IT_BTF: Byte transfer finished flag
01264   *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
01265   *                       Address matched flag (Slave mode)"ENDAD"
01266   *     @arg I2C_IT_SB: Start bit flag (Master mode)
01267   * @retval The new state of I2C_IT (SET or RESET).
01268   */
01269 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
01270 {
01271   ITStatus bitstatus = RESET;
01272   uint32_t enablestatus = 0;
01273
01274   /* Check the parameters */
01275   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01276   assert_param(IS_I2C_GET_IT(I2C_IT));
01277
01278   /* Check if the interrupt source is enabled or not */
01279   enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
01280
01281   /* Get bit[23:0] of the flag */
01282   I2C_IT &= FLAG_MASK;
01283
01284   /* Check the status of the specified I2C flag */
01285   if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
01286   {
01287     /* I2C_IT is set */
01288     bitstatus = SET;
01289   }
01290   else
01291   {
01292     /* I2C_IT is reset */
01293     bitstatus = RESET;
01294   }
01295   /* Return the I2C_IT status */
01296   return  bitstatus;
01297 }
01298
01299 /**
01300   * @brief  Clears the I2Cx's interrupt pending bits.
01301   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01302   * @param  I2C_IT: specifies the interrupt pending bit to clear.
01303   *   This parameter can be any combination of the following values:
01304   *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
01305   *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
01306   *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
01307   *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
01308   *     @arg I2C_IT_AF: Acknowledge failure interrupt
01309   *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
01310   *     @arg I2C_IT_BERR: Bus error interrupt
01311   *
01312
01313   * @note STOPF (STOP detection) is cleared by software sequence: a read operation
01314   *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
01315   *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
01316   * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
01317   *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
01318   *     byte of the address in I2C_DR register.
01319   * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
01320   *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
01321   *     read/write to I2C_DR register (I2C_SendData()).
01322   * @note ADDR (Address sent) is cleared by software sequence: a read operation to
01323   *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
01324   *     I2C_SR2 register ((void)(I2Cx->SR2)).
01325   * @note SB (Start Bit) is cleared by software sequence: a read operation to
01326   *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
01327   *     I2C_DR register (I2C_SendData()).
01328   * @retval None
01329   */
01330 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
01331 {
01332   uint32_t flagpos = 0;
01333   /* Check the parameters */
01334   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01335   assert_param(IS_I2C_CLEAR_IT(I2C_IT));
01336   /* Get the I2C flag position */
01337   flagpos = I2C_IT & FLAG_MASK;
01338   /* Clear the selected I2C flag */
01339   I2Cx->SR1 = (uint16_t)~flagpos;
01340 }
01341
01342 /**
01343   * @}
01344   */
01345
01346 /**
01347   * @}
01348   */
01349
01350 /**
01351   * @}
01352   */
01353
01354 /**
01355   * @}
01356   */
01357
01358 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
01359
01360
01361


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_i2c.h Source File

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stm32l1xx_i2c.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the I2C firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_I2C_H
00028 #define __STM32L1xx_I2C_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup I2C
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  I2C Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
00054                                          This parameter must be set to a value lower than 400kHz */
00055
00056   uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
00057                                          This parameter can be a value of @ref I2C_mode */
00058
00059   uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
00060                                          This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
00061
00062   uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
00063                                          This parameter can be a 7-bit or 10-bit address. */
00064
00065   uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
00066                                          This parameter can be a value of @ref I2C_acknowledgement */
00067
00068   uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
00069                                          This parameter can be a value of @ref I2C_acknowledged_address */
00070 }I2C_InitTypeDef;
00071
00072 /* Exported constants --------------------------------------------------------*/
00073
00074
00075 /** @defgroup I2C_Exported_Constants
00076   * @{
00077   */
00078
00079 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
00080                                    ((PERIPH) == I2C2))
00081 /** @defgroup I2C_mode
00082   * @{
00083   */
00084
00085 #define I2C_Mode_I2C                    ((uint16_t)0x0000)
00086 #define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
00087 #define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
00088 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
00089                            ((MODE) == I2C_Mode_SMBusDevice) || \
00090                            ((MODE) == I2C_Mode_SMBusHost))
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup I2C_duty_cycle_in_fast_mode
00096   * @{
00097   */
00098
00099 #define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
00100 #define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
00101 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
00102                                   ((CYCLE) == I2C_DutyCycle_2))
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup I2C_acknowledgement
00108   * @{
00109   */
00110
00111 #define I2C_Ack_Enable                  ((uint16_t)0x0400)
00112 #define I2C_Ack_Disable                 ((uint16_t)0x0000)
00113 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
00114                                  ((STATE) == I2C_Ack_Disable))
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup I2C_transfer_direction
00120   * @{
00121   */
00122
00123 #define  I2C_Direction_Transmitter      ((uint8_t)0x00)
00124 #define  I2C_Direction_Receiver         ((uint8_t)0x01)
00125 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
00126                                      ((DIRECTION) == I2C_Direction_Receiver))
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup I2C_acknowledged_address
00132   * @{
00133   */
00134
00135 #define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
00136 #define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
00137 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
00138                                              ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup I2C_registers
00144   * @{
00145   */
00146
00147 #define I2C_Register_CR1                ((uint8_t)0x00)
00148 #define I2C_Register_CR2                ((uint8_t)0x04)
00149 #define I2C_Register_OAR1               ((uint8_t)0x08)
00150 #define I2C_Register_OAR2               ((uint8_t)0x0C)
00151 #define I2C_Register_DR                 ((uint8_t)0x10)
00152 #define I2C_Register_SR1                ((uint8_t)0x14)
00153 #define I2C_Register_SR2                ((uint8_t)0x18)
00154 #define I2C_Register_CCR                ((uint8_t)0x1C)
00155 #define I2C_Register_TRISE              ((uint8_t)0x20)
00156 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
00157                                    ((REGISTER) == I2C_Register_CR2) || \
00158                                    ((REGISTER) == I2C_Register_OAR1) || \
00159                                    ((REGISTER) == I2C_Register_OAR2) || \
00160                                    ((REGISTER) == I2C_Register_DR) || \
00161                                    ((REGISTER) == I2C_Register_SR1) || \
00162                                    ((REGISTER) == I2C_Register_SR2) || \
00163                                    ((REGISTER) == I2C_Register_CCR) || \
00164                                    ((REGISTER) == I2C_Register_TRISE))
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup I2C_SMBus_alert_pin_level
00170   * @{
00171   */
00172
00173 #define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
00174 #define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
00175 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
00176                                    ((ALERT) == I2C_SMBusAlert_High))
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup I2C_PEC_position
00182   * @{
00183   */
00184
00185 #define I2C_PECPosition_Next            ((uint16_t)0x0800)
00186 #define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
00187 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
00188                                        ((POSITION) == I2C_PECPosition_Current))
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup I2C_NACK_position
00194   * @{
00195   */
00196
00197 #define I2C_NACKPosition_Next           ((uint16_t)0x0800)
00198 #define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
00199 #define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
00200                                          ((POSITION) == I2C_NACKPosition_Current))
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup I2C_interrupts_definition
00206   * @{
00207   */
00208
00209 #define I2C_IT_BUF                      ((uint16_t)0x0400)
00210 #define I2C_IT_EVT                      ((uint16_t)0x0200)
00211 #define I2C_IT_ERR                      ((uint16_t)0x0100)
00212 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup I2C_interrupts_definition
00218   * @{
00219   */
00220
00221 #define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
00222 #define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
00223 #define I2C_IT_PECERR                   ((uint32_t)0x01001000)
00224 #define I2C_IT_OVR                      ((uint32_t)0x01000800)
00225 #define I2C_IT_AF                       ((uint32_t)0x01000400)
00226 #define I2C_IT_ARLO                     ((uint32_t)0x01000200)
00227 #define I2C_IT_BERR                     ((uint32_t)0x01000100)
00228 #define I2C_IT_TXE                      ((uint32_t)0x06000080)
00229 #define I2C_IT_RXNE                     ((uint32_t)0x06000040)
00230 #define I2C_IT_STOPF                    ((uint32_t)0x02000010)
00231 #define I2C_IT_ADD10                    ((uint32_t)0x02000008)
00232 #define I2C_IT_BTF                      ((uint32_t)0x02000004)
00233 #define I2C_IT_ADDR                     ((uint32_t)0x02000002)
00234 #define I2C_IT_SB                       ((uint32_t)0x02000001)
00235
00236 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
00237
00238 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
00239                            ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
00240                            ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
00241                            ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
00242                            ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
00243                            ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
00244                            ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup I2C_flags_definition
00250   * @{
00251   */
00252
00253 /**
00254   * @brief  SR2 register flags
00255   */
00256
00257 #define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
00258 #define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
00259 #define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
00260 #define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
00261 #define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
00262 #define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
00263 #define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
00264
00265 /**
00266   * @brief  SR1 register flags
00267   */
00268
00269 #define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
00270 #define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
00271 #define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
00272 #define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
00273 #define I2C_FLAG_AF                     ((uint32_t)0x10000400)
00274 #define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
00275 #define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
00276 #define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
00277 #define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
00278 #define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
00279 #define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
00280 #define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
00281 #define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
00282 #define I2C_FLAG_SB                     ((uint32_t)0x10000001)
00283
00284 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
00285
00286 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
00287                                ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
00288                                ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
00289                                ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
00290                                ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
00291                                ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
00292                                ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
00293                                ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
00294                                ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
00295                                ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
00296                                ((FLAG) == I2C_FLAG_SB))
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup I2C_Events
00302   * @{
00303   */
00304
00305 /**
00306  ===============================================================================
00307                I2C Master Events (Events grouped in order of communication)
00308  ===============================================================================
00309  */
00310
00311 /**
00312   * @brief  Communication start
00313   *
00314   * After sending the START condition (I2C_GenerateSTART() function) the master
00315   * has to wait for this event. It means that the Start condition has been correctly
00316   * released on the I2C bus (the bus is free, no other devices is communicating).
00317   *
00318   */
00319 /* --EV5 */
00320 #define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
00321
00322 /**
00323   * @brief  Address Acknowledge
00324   *
00325   * After checking on EV5 (start condition correctly released on the bus), the
00326   * master sends the address of the slave(s) with which it will communicate
00327   * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
00328   * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
00329   * his address. If an acknowledge is sent on the bus, one of the following events will
00330   * be set:
00331   *
00332   *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
00333   *     event is set.
00334   *
00335   *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
00336   *     is set
00337   *
00338   *  3) In case of 10-Bit addressing mode, the master (just after generating the START
00339   *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
00340   *  function). Then master should wait on EV9. It means that the 10-bit addressing
00341   *  header has been correctly sent on the bus. Then master should send the second part of
00342   *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
00343   *  should wait for event EV6.
00344   *
00345   */
00346
00347 /* --EV6 */
00348 #define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
00349 #define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
00350 /* --EV9 */
00351 #define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
00352
00353 /**
00354   * @brief Communication events
00355   *
00356   * If a communication is established (START condition generated and slave address
00357   * acknowledged) then the master has to check on one of the following events for
00358   * communication procedures:
00359   *
00360   * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
00361   *    the data received from the slave (I2C_ReceiveData() function).
00362   *
00363   * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
00364   *    function) then to wait on event EV8 or EV8_2.
00365   *    These two events are similar:
00366   *     - EV8 means that the data has been written in the data register and is
00367   *       being shifted out.
00368   *     - EV8_2 means that the data has been physically shifted out and output
00369   *       on the bus.
00370   *     In most cases, using EV8 is sufficient for the application.
00371   *     Using EV8_2 leads to a slower communication but ensure more reliable test.
00372   *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
00373   *     (before Stop condition generation).
00374   *
00375   *  @note In case the  user software does not guarantee that this event EV7 is
00376   *  managed before the current byte end of transfer, then user may check on EV7
00377   *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
00378   *  In this case the communication may be slower.
00379   *
00380   */
00381
00382 /* Master RECEIVER mode -----------------------------*/
00383 /* --EV7 */
00384 #define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
00385
00386 /* Master TRANSMITTER mode --------------------------*/
00387 /* --EV8 */
00388 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
00389 /* --EV8_2 */
00390 #define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
00391
00392
00393 /**
00394  ===============================================================================
00395                I2C Slave Events (Events grouped in order of communication)
00396  ===============================================================================
00397  */
00398
00399
00400 /**
00401   * @brief  Communication start events
00402   *
00403   * Wait on one of these events at the start of the communication. It means that
00404   * the I2C peripheral detected a Start condition on the bus (generated by master
00405   * device) followed by the peripheral address. The peripheral generates an ACK
00406   * condition on the bus (if the acknowledge feature is enabled through function
00407   * I2C_AcknowledgeConfig()) and the events listed above are set :
00408   *
00409   * 1) In normal case (only one address managed by the slave), when the address
00410   *   sent by the master matches the own address of the peripheral (configured by
00411   *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
00412   *   (where XXX could be TRANSMITTER or RECEIVER).
00413   *
00414   * 2) In case the address sent by the master matches the second address of the
00415   *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled
00416   *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
00417   *   (where XXX could be TRANSMITTER or RECEIVER) are set.
00418   *
00419   * 3) In case the address sent by the master is General Call (address 0x00) and
00420   *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
00421   *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
00422   *
00423   */
00424
00425 /* --EV1  (all the events below are variants of EV1) */
00426 /* 1) Case of One Single Address managed by the slave */
00427 #define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
00428 #define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
00429
00430 /* 2) Case of Dual address managed by the slave */
00431 #define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
00432 #define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
00433
00434 /* 3) Case of General Call enabled for the slave */
00435 #define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
00436
00437 /**
00438   * @brief  Communication events
00439   *
00440   * Wait on one of these events when EV1 has already been checked and:
00441   *
00442   * - Slave RECEIVER mode:
00443   *     - EV2: When the application is expecting a data byte to be received.
00444   *     - EV4: When the application is expecting the end of the communication: master
00445   *       sends a stop condition and data transmission is stopped.
00446   *
00447   * - Slave Transmitter mode:
00448   *    - EV3: When a byte has been transmitted by the slave and the application is expecting
00449   *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
00450   *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
00451   *      used when the user software doesn't guarantee the EV3 is managed before the
00452   *      current byte end of transfer.
00453   *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
00454   *      shall end (before sending the STOP condition). In this case slave has to stop sending
00455   *      data bytes and expect a Stop condition on the bus.
00456   *
00457   *  @note In case the  user software does not guarantee that the event EV2 is
00458   *  managed before the current byte end of transfer, then user may check on EV2
00459   *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
00460   *  In this case the communication may be slower.
00461   *
00462   */
00463
00464 /* Slave RECEIVER mode --------------------------*/
00465 /* --EV2 */
00466 #define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
00467 /* --EV4  */
00468 #define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
00469
00470 /* Slave TRANSMITTER mode -----------------------*/
00471 /* --EV3 */
00472 #define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
00473 #define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
00474 /* --EV3_2 */
00475 #define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
00476
00477 /*
00478  ===============================================================================
00479                           End of Events Description
00480  ===============================================================================
00481  */
00482
00483 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
00484                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
00485                              ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
00486                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
00487                              ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
00488                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
00489                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
00490                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
00491                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
00492                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
00493                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
00494                              ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
00495                              ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
00496                              ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
00497                              ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
00498                              ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
00499                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
00500                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
00501                              ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
00502                              ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup I2C_own_address1
00508   * @{
00509   */
00510
00511 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup I2C_clock_speed
00517   * @{
00518   */
00519
00520 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
00521 /**
00522   * @}
00523   */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /* Exported macro ------------------------------------------------------------*/
00530 /* Exported functions ------------------------------------------------------- */
00531
00532 /*  Function used to set the I2C configuration to the default reset state *****/
00533 void I2C_DeInit(I2C_TypeDef* I2Cx);
00534
00535 /* Initialization and Configuration functions *********************************/
00536 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
00537 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
00538 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00539 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
00540 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
00541 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
00542 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
00543 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00544 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00545 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00546 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
00547 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00548 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00549 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
00550 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
00551
00552 /* Data transfers functions ***************************************************/
00553 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
00554 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
00555 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
00556
00557 /* PEC management functions ***************************************************/
00558 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
00559 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
00560 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
00561 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
00562
00563 /* DMA transfers management functions *****************************************/
00564 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00565 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00566
00567
00568 /* Interrupts, events and flags management functions **************************/
00569 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
00570 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
00571
00572 /*
00573
00574  ===============================================================================
00575                           I2C State Monitoring Functions
00576  ===============================================================================
00577   This I2C driver provides three different ways for I2C state monitoring
00578   depending on the application requirements and constraints:
00579
00580
00581      1. Basic state monitoring (Using I2C_CheckEvent() function)
00582      -----------------------------------------------------------
00583         It compares the status registers (SR1 and SR2) content to a given event
00584         (can be the combination of one or more flags).
00585         It returns SUCCESS if the current status includes the given flags
00586         and returns ERROR if one or more flags are missing in the current status.
00587
00588           - When to use
00589              - This function is suitable for most applications as well as for startup
00590                activity since the events are fully described in the product reference
00591                manual (RM0038).
00592              - It is also suitable for users who need to define their own events.
00593
00594           - Limitations
00595              - If an error occurs (ie. error flags are set besides to the monitored
00596                flags), the I2C_CheckEvent() function may return SUCCESS despite
00597                the communication hold or corrupted real state.
00598                In this case, it is advised to use error interrupts to monitor
00599                the error events and handle them in the interrupt IRQ handler.
00600
00601      Note
00602          For error management, it is advised to use the following functions:
00603            - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00604            - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
00605              Where x is the peripheral instance (I2C1, I2C2 ...)
00606            - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the
00607              I2Cx_ER_IRQHandler() function in order to determine which error occurred.
00608            - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00609              and/or I2C_GenerateStop() in order to clear the error flag and source
00610              and return to correct  communciation status.
00611
00612
00613      2. Advanced state monitoring (Using the function I2C_GetLastEvent())
00614      --------------------------------------------------------------------
00615         Using the function I2C_GetLastEvent() which returns the image of both status
00616         registers in a single word (uint32_t) (Status Register 2 value is shifted left
00617         by 16 bits and concatenated to Status Register 1).
00618
00619           - When to use
00620              - This function is suitable for the same applications above but it
00621                allows to overcome the mentioned limitation of I2C_GetFlagStatus()
00622                function.
00623              - The returned value could be compared to events already defined in
00624                the library (stm32l1xx_i2c.h) or to custom values defined by user.
00625                This function is suitable when multiple flags are monitored at the
00626                same time.
00627              - At the opposite of I2C_CheckEvent() function, this function allows
00628                user to choose when an event is accepted (when all events flags are
00629                set and no other flags are set or just when the needed flags are set
00630                like I2C_CheckEvent() function.
00631
00632           - Limitations
00633              - User may need to define his own events.
00634              - Same remark concerning the error management is applicable for this
00635                function if user decides to check only regular communication flags
00636                (and ignores error flags).
00637
00638
00639      3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
00640      -----------------------------------------------------------------------
00641
00642       Using the function I2C_GetFlagStatus() which simply returns the status of
00643       one single flag (ie. I2C_FLAG_RXNE ...).
00644
00645           - When to use
00646              - This function could be used for specific applications or in debug
00647                phase.
00648              - It is suitable when only one flag checking is needed (most I2C
00649                events are monitored through multiple flags).
00650           - Limitations:
00651              - When calling this function, the Status register is accessed.
00652                Some flags are cleared when the status register is accessed.
00653                So checking the status of one Flag, may clear other ones.
00654              - Function may need to be called twice or more in order to monitor
00655                one single event.
00656
00657    For detailed description of Events, please refer to section I2C_Events in
00658    stm32l1xx_i2c.h file.
00659
00660 */
00661
00662 /*
00663  ===============================================================================
00664                           1. Basic state monitoring
00665  ===============================================================================
00666  */
00667 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
00668 /*
00669  ===============================================================================
00670                           2. Advanced state monitoring
00671  ===============================================================================
00672  */
00673 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
00674 /*
00675  ===============================================================================
00676                           3. Flag-based state monitoring
00677  ===============================================================================
00678  */
00679 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
00680
00681
00682 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
00683 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
00684 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
00685
00686 #ifdef __cplusplus
00687 }
00688 #endif
00689
00690 #endif /*__STM32L1xx_I2C_H */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_iwdg.c Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • src

stm32l1xx_iwdg.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Independent watchdog (IWDG) peripheral:
00009   *           + Prescaler and Counter configuration
00010   *           + IWDG activation
00011   *           + Flag management
00012   *
00013   *  @verbatim
00014   *
00015   ==============================================================================
00016                           ##### IWDG features #####
00017   ==============================================================================
00018     [..] The IWDG can be started by either software or hardware (configurable
00019          through option byte).
00020
00021     [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
00022          thus stays active even if the main clock fails.
00023          Once the IWDG is started, the LSI is forced ON and cannot be disabled
00024          (LSI cannot be disabled too), and the counter starts counting down from
00025          the reset value of 0xFFF. When it reaches the end of count value (0x000)
00026          a system reset is generated.
00027          The IWDG counter should be reloaded at regular intervals to prevent
00028          an MCU reset.
00029
00030     [..] The IWDG is implemented in the VDD voltage domain that is still functional
00031          in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00032
00033     [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
00034          reset occurs.
00035
00036     [..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
00037          The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
00038          devices provide the capability to measure the LSI frequency (LSI clock
00039          connected internally to TIM10 CH1 input capture). The measured value
00040          can be used to have an IWDG timeout with an acceptable accuracy.
00041          For more information, please refer to the STM32L1xx Reference manual.
00042
00043                           ##### How to use this driver #####
00044   ==============================================================================
00045     [..]
00046     (#) Enable write access to IWDG_PR and IWDG_RLR registers using
00047         IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
00048     (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
00049
00050     (#) Configure the IWDG counter value using IWDG_SetReload() function.
00051         This value will be loaded in the IWDG counter each time the counter
00052         is reloaded, then the IWDG will start counting down from this value.
00053
00054     (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
00055         in software mode (no need to enable the LSI, it will be enabled
00056         by hardware).
00057
00058     (#) Then the application program must reload the IWDG counter at regular
00059         intervals during normal operation to prevent an MCU reset, using
00060         IWDG_ReloadCounter() function.
00061
00062     @endverbatim
00063   *
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00068   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00069   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00070   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00071   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00072   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00073   *
00074   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00075   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00076   *
00077   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00078   ******************************************************************************
00079   */
00080
00081 /* Includes ------------------------------------------------------------------*/
00082 #include "stm32l1xx_iwdg.h"
00083
00084 /** @addtogroup STM32L1xx_StdPeriph_Driver
00085   * @{
00086   */
00087
00088 /** @defgroup IWDG
00089   * @brief IWDG driver modules
00090   * @{
00091   */
00092
00093 /* Private typedef -----------------------------------------------------------*/
00094 /* Private define ------------------------------------------------------------*/
00095 /* ---------------------- IWDG registers bit mask ----------------------------*/
00096 /* KR register bit mask */
00097 #define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
00098 #define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
00099
00100 /* Private macro -------------------------------------------------------------*/
00101 /* Private variables ---------------------------------------------------------*/
00102 /* Private function prototypes -----------------------------------------------*/
00103 /* Private functions ---------------------------------------------------------*/
00104
00105 /** @defgroup IWDG_Private_Functions
00106   * @{
00107   */
00108
00109 /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
00110  *  @brief   Prescaler and Counter configuration functions
00111  *
00112 @verbatim
00113   ==============================================================================
00114             ##### Prescaler and Counter configuration functions #####
00115   ==============================================================================
00116
00117 @endverbatim
00118   * @{
00119   */
00120
00121 /**
00122   * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
00123   * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
00124   *   This parameter can be one of the following values:
00125   *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
00126   *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
00127   * @retval None
00128   */
00129 void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
00130 {
00131   /* Check the parameters */
00132   assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
00133   IWDG->KR = IWDG_WriteAccess;
00134 }
00135
00136 /**
00137   * @brief  Sets IWDG Prescaler value.
00138   * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
00139   *   This parameter can be one of the following values:
00140   *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
00141   *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
00142   *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
00143   *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
00144   *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
00145   *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
00146   *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
00147   * @retval None
00148   */
00149 void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
00150 {
00151   /* Check the parameters */
00152   assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
00153   IWDG->PR = IWDG_Prescaler;
00154 }
00155
00156 /**
00157   * @brief  Sets IWDG Reload value.
00158   * @param  Reload: specifies the IWDG Reload value.
00159   *   This parameter must be a number between 0 and 0x0FFF.
00160   * @retval None
00161   */
00162 void IWDG_SetReload(uint16_t Reload)
00163 {
00164   /* Check the parameters */
00165   assert_param(IS_IWDG_RELOAD(Reload));
00166   IWDG->RLR = Reload;
00167 }
00168
00169 /**
00170   * @brief  Reloads IWDG counter with value defined in the reload register
00171   *   (write access to IWDG_PR and IWDG_RLR registers disabled).
00172   * @param  None
00173   * @retval None
00174   */
00175 void IWDG_ReloadCounter(void)
00176 {
00177   IWDG->KR = KR_KEY_RELOAD;
00178 }
00179
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup IWDG_Group2 IWDG activation function
00185  *  @brief   IWDG activation function
00186  *
00187 @verbatim
00188   ==============================================================================
00189                           ##### IWDG activation function #####
00190   ==============================================================================
00191
00192 @endverbatim
00193   * @{
00194   */
00195
00196 /**
00197   * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
00198   * @param  None.
00199   * @retval None.
00200   */
00201 void IWDG_Enable(void)
00202 {
00203   IWDG->KR = KR_KEY_ENABLE;
00204 }
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup IWDG_Group3 Flag management function
00211  *  @brief  Flag management function
00212  *
00213 @verbatim
00214  ===============================================================================
00215                       ##### Flag management function #####
00216  ===============================================================================
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Checks whether the specified IWDG flag is set or not.
00224   * @param  IWDG_FLAG: specifies the flag to check.
00225   *   This parameter can be one of the following values:
00226   *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
00227   *     @arg IWDG_FLAG_RVU: Reload Value Update on going
00228   * @retval The new state of IWDG_FLAG (SET or RESET).
00229   */
00230 FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
00231 {
00232   FlagStatus bitstatus = RESET;
00233   /* Check the parameters */
00234   assert_param(IS_IWDG_FLAG(IWDG_FLAG));
00235   if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
00236   {
00237     bitstatus = SET;
00238   }
00239   else
00240   {
00241     bitstatus = RESET;
00242   }
00243   /* Return the flag status */
00244   return bitstatus;
00245 }
00246
00247 /**
00248   * @}
00249   */
00250
00251 /**
00252   * @}
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 /**
00260   * @}
00261   */
00262
00263 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_iwdg.h Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_iwdg.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the IWDG
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_IWDG_H
00028 #define __STM32L1xx_IWDG_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup IWDG
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup IWDG_Exported_Constants
00049   * @{
00050   */
00051
00052 /** @defgroup IWDG_WriteAccess
00053   * @{
00054   */
00055
00056 #define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
00057 #define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
00058 #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
00059                                       ((ACCESS) == IWDG_WriteAccess_Disable))
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup IWDG_prescaler
00065   * @{
00066   */
00067
00068 #define IWDG_Prescaler_4            ((uint8_t)0x00)
00069 #define IWDG_Prescaler_8            ((uint8_t)0x01)
00070 #define IWDG_Prescaler_16           ((uint8_t)0x02)
00071 #define IWDG_Prescaler_32           ((uint8_t)0x03)
00072 #define IWDG_Prescaler_64           ((uint8_t)0x04)
00073 #define IWDG_Prescaler_128          ((uint8_t)0x05)
00074 #define IWDG_Prescaler_256          ((uint8_t)0x06)
00075 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
00076                                       ((PRESCALER) == IWDG_Prescaler_8)  || \
00077                                       ((PRESCALER) == IWDG_Prescaler_16) || \
00078                                       ((PRESCALER) == IWDG_Prescaler_32) || \
00079                                       ((PRESCALER) == IWDG_Prescaler_64) || \
00080                                       ((PRESCALER) == IWDG_Prescaler_128)|| \
00081                                       ((PRESCALER) == IWDG_Prescaler_256))
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup IWDG_Flag
00087   * @{
00088   */
00089
00090 #define IWDG_FLAG_PVU               ((uint16_t)0x0001)
00091 #define IWDG_FLAG_RVU               ((uint16_t)0x0002)
00092 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
00093 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
00094 /**
00095   * @}
00096   */
00097
00098 /**
00099   * @}
00100   */
00101
00102 /* Exported macro ------------------------------------------------------------*/
00103 /* Exported functions ------------------------------------------------------- */
00104
00105 /* Prescaler and Counter configuration functions ******************************/
00106 void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
00107 void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
00108 void IWDG_SetReload(uint16_t Reload);
00109 void IWDG_ReloadCounter(void);
00110
00111 /* IWDG activation function ***************************************************/
00112 void IWDG_Enable(void);
00113
00114 /* Flag management function ***************************************************/
00115 FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
00116
00117 #ifdef __cplusplus
00118 }
00119 #endif
00120
00121 #endif /* __STM32L1xx_IWDG_H */
00122
00123 /**
00124   * @}
00125   */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_lcd.c Source File

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stm32l1xx_lcd.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_lcd.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the LCD controller (LCD) peripheral:
00009   *           + Initialization and configuration
00010   *           + LCD RAM memory write
00011   *           + Interrupts and flags management
00012   *
00013   *  @verbatim
00014
00015  ===============================================================================
00016                             ##### LCD Clock #####
00017  ===============================================================================
00018     [..] LCDCLK is the same as RTCCLK.
00019     [..] To configure the RTCCLK/LCDCLK, proceed as follows:
00020          (+) Enable the Power Controller (PWR) APB1 interface clock using the
00021              RCC_APB1PeriphClockCmd() function.
00022          (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
00023          (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
00024
00025     [..] The frequency generator allows you to achieve various LCD frame rates
00026          starting from an LCD input clock frequency (LCDCLK) which can vary
00027          from 32 kHz up to 1 MHz.
00028
00029                       ##### LCD and low power modes #####
00030  ===============================================================================
00031     [..] The LCD still active during STOP mode.
00032
00033                       ##### How to use this driver #####
00034  ===============================================================================
00035     [..]
00036         (#) Enable LCD clock using
00037             RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function.
00038         (#) Configure the LCD prescaler, divider, duty, bias and voltage source
00039             using LCD_Init() function.
00040         (#) Optionally you can enable/configure:
00041             (++) LCD High Drive using the LCD_HighDriveCmd() function.
00042             (++) LCD COM/SEG Mux using the LCD_MuxSegmentCmd() function.
00043             (++) LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function.
00044             (++) LCD Dead Time using the LCD_DeadTimeConfig() function
00045             (++) The LCD Blink mode and frequency using the LCD_BlinkConfig() function.
00046             (++) The LCD Contrast using the LCD_ContrastConfig() function.
00047         (#) Call the LCD_WaitForSynchro() function to wait for LCD_FCR register
00048             synchronization.
00049         (#) Call the LCD_Cmd() to enable the LCD controller.
00050         (#) Wait until the LCD Controller status is enabled and the step-up
00051             converter is ready using the LCD_GetFlagStatus() and
00052             LCD_FLAG_ENS and LCD_FLAG_RDY flags.
00053         (#) Write to the LCD RAM memory using the LCD_Write() function.
00054         (#) Request an update display using the LCD_UpdateDisplayRequest()
00055             function.
00056         (#) Wait until the update display is finished by checking the UDD
00057             flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD).
00058
00059     @endverbatim
00060
00061   ******************************************************************************
00062   * @attention
00063   *
00064   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00065   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00066   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00067   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00068   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00069   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00070   *
00071   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00072   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00073   *
00074   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00075   ******************************************************************************
00076   */
00077
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32l1xx_lcd.h"
00080 #include "stm32l1xx_rcc.h"
00081
00082 /** @addtogroup STM32L1xx_StdPeriph_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup LCD
00087   * @brief LCD driver modules
00088   * @{
00089   */
00090
00091 /* Private typedef -----------------------------------------------------------*/
00092 /* Private define ------------------------------------------------------------*/
00093 /* ------------ LCD registers bit address in the alias region --------------- */
00094 #define LCD_OFFSET                   (LCD_BASE - PERIPH_BASE)
00095
00096 /* --- CR Register ---*/
00097
00098 /* Alias word address of LCDEN bit */
00099 #define CR_OFFSET                    (LCD_OFFSET + 0x00)
00100 #define LCDEN_BitNumber              0x00
00101 #define CR_LCDEN_BB                  (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))
00102
00103 /* Alias word address of MUX_SEG bit */
00104 #define MUX_SEG_BitNumber            0x07
00105 #define CR_MUX_SEG_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))
00106
00107
00108 /* --- FCR Register ---*/
00109
00110 /* Alias word address of HD bit */
00111 #define FCR_OFFSET                   (LCD_OFFSET + 0x04)
00112 #define HD_BitNumber                 0x00
00113 #define FCR_HD_BB                    (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))
00114
00115 /* --- SR Register ---*/
00116
00117 /* Alias word address of UDR bit */
00118 #define SR_OFFSET                    (LCD_OFFSET + 0x08)
00119 #define UDR_BitNumber                0x02
00120 #define SR_UDR_BB                    (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))
00121
00122 #define FCR_MASK                     ((uint32_t)0xFC03FFFF)  /* LCD FCR Mask */
00123 #define CR_MASK                      ((uint32_t)0xFFFFFF81)  /* LCD CR Mask */
00124 #define PON_MASK                     ((uint32_t)0xFFFFFF8F)  /* LCD PON Mask */
00125 #define DEAD_MASK                    ((uint32_t)0xFFFFFC7F)  /* LCD DEAD Mask */
00126 #define BLINK_MASK                   ((uint32_t)0xFFFC1FFF)  /* LCD BLINK Mask */
00127 #define CONTRAST_MASK                ((uint32_t)0xFFFFE3FF)  /* LCD CONTRAST Mask */
00128
00129 /* Private macro -------------------------------------------------------------*/
00130 /* Private variables ---------------------------------------------------------*/
00131 /* Private function prototypes -----------------------------------------------*/
00132 /* Private functions ---------------------------------------------------------*/
00133
00134 /** @defgroup LCD_Private_Functions
00135   * @{
00136   */
00137
00138 /** @defgroup LCD_Group1 Initialization and Configuration functions
00139  *  @brief   Initialization and Configuration functions
00140  *
00141 @verbatim
00142  ===============================================================================
00143             ##### Initialization and Configuration functions #####
00144  ===============================================================================
00145
00146 @endverbatim
00147   * @{
00148   */
00149
00150 /**
00151   * @brief  Deinitializes the LCD peripheral registers to their default reset
00152   *         values.
00153   * @param  None
00154   * @retval None
00155   */
00156 void LCD_DeInit(void)
00157 {
00158   /* Enable LCD reset state */
00159   RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);
00160   /* Release LCD from reset state */
00161   RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);
00162 }
00163
00164 /**
00165   * @brief  Initializes the LCD peripheral according to the specified parameters
00166   *         in the LCD_InitStruct.
00167   * @note   This function can be used only when the LCD is disabled.
00168   * @param  LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains
00169   *         the configuration information for the specified LCD peripheral.
00170   * @retval None
00171   */
00172 void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)
00173 {
00174   /* Check function parameters */
00175   assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));
00176   assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));
00177   assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));
00178   assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias));
00179   assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));
00180
00181   LCD->FCR &= (uint32_t)FCR_MASK;
00182   LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);
00183
00184   LCD_WaitForSynchro();
00185
00186   LCD->CR &= (uint32_t)CR_MASK;
00187   LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \
00188                         LCD_InitStruct->LCD_VoltageSource);
00189
00190 }
00191
00192 /**
00193   * @brief  Fills each LCD_InitStruct member with its default value.
00194   * @param  LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will
00195   *         be initialized.
00196   * @retval None
00197   */
00198 void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)
00199 {
00200 /*--------------- Reset LCD init structure parameters values -----------------*/
00201   LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */
00202
00203   LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */
00204
00205   LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */
00206
00207   LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */
00208
00209   LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */
00210 }
00211
00212 /**
00213   * @brief  Enables or disables the LCD Controller.
00214   * @param  NewState: new state of the LCD peripheral.
00215   *   This parameter can be: ENABLE or DISABLE.
00216   * @retval None
00217   */
00218 void LCD_Cmd(FunctionalState NewState)
00219 {
00220   assert_param(IS_FUNCTIONAL_STATE(NewState));
00221
00222   /* Check the parameters */
00223   assert_param(IS_FUNCTIONAL_STATE(NewState));
00224
00225   *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;
00226 }
00227
00228 /**
00229   * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
00230   *   This function must be called after any write operation to LCD_FCR register.
00231   * @param  None
00232   * @retval None
00233   */
00234 void LCD_WaitForSynchro(void)
00235 {
00236   /* Loop until FCRSF flag is set */
00237   while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)
00238   {
00239   }
00240 }
00241
00242 /**
00243   * @brief  Enables or disables the low resistance divider. Displays with high
00244   *         internal resistance may need a longer drive time to achieve
00245   *         satisfactory contrast. This function is useful in this case if some
00246   *         additional power consumption can be tolerated.
00247   * @note   When this mode is enabled, the PulseOn Duration (PON) have to be
00248   *         programmed to 1/CK_PS (LCD_PulseOnDuration_1).
00249   * @param  NewState: new state of the low resistance divider.
00250   *   This parameter can be: ENABLE or DISABLE.
00251   * @retval None
00252   */
00253 void LCD_HighDriveCmd(FunctionalState NewState)
00254 {
00255   /* Check the parameters */
00256   assert_param(IS_FUNCTIONAL_STATE(NewState));
00257
00258   *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;
00259 }
00260
00261 /**
00262   * @brief  Enables or disables the Mux Segment.
00263   * @note   This function can be used only when the LCD is disabled.
00264   * @param  NewState: new state of the Mux Segment.
00265   *   This parameter can be: ENABLE or DISABLE.
00266   * @retval None
00267   */
00268 void LCD_MuxSegmentCmd(FunctionalState NewState)
00269 {
00270   /* Check the parameters */
00271   assert_param(IS_FUNCTIONAL_STATE(NewState));
00272
00273   *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;
00274 }
00275
00276 /**
00277   * @brief  Configures the LCD pulses on duration.
00278   * @param  LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of
00279   *         CK_PS (prescaled LCD clock period) pulses.
00280   *   This parameter can be one of the following values:
00281   *     @arg LCD_PulseOnDuration_0: 0 pulse
00282   *     @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS
00283   *     @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS
00284   *     @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS
00285   *     @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS
00286   *     @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS
00287   *     @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS
00288   *     @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS
00289   * @retval None
00290   */
00291 void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)
00292 {
00293   /* Check the parameters */
00294   assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));
00295
00296   LCD->FCR &= (uint32_t)PON_MASK;
00297   LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);
00298 }
00299
00300 /**
00301   * @brief  Configures the LCD dead time.
00302   * @param  LCD_DeadTime: specifies the LCD dead time.
00303   *   This parameter can be one of the following values:
00304   *     @arg LCD_DeadTime_0: No dead Time
00305   *     @arg LCD_DeadTime_1: One Phase between different couple of Frame
00306   *     @arg LCD_DeadTime_2: Two Phase between different couple of Frame
00307   *     @arg LCD_DeadTime_3: Three Phase between different couple of Frame
00308   *     @arg LCD_DeadTime_4: Four Phase between different couple of Frame
00309   *     @arg LCD_DeadTime_5: Five Phase between different couple of Frame
00310   *     @arg LCD_DeadTime_6: Six Phase between different couple of Frame
00311   *     @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
00312   * @retval None
00313   */
00314 void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)
00315 {
00316   /* Check the parameters */
00317   assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
00318
00319   LCD->FCR &= (uint32_t)DEAD_MASK;
00320   LCD->FCR |= (uint32_t)(LCD_DeadTime);
00321 }
00322
00323 /**
00324   * @brief  Configures the LCD Blink mode and Blink frequency.
00325   * @param  LCD_BlinkMode: specifies the LCD blink mode.
00326   *   This parameter can be one of the following values:
00327   *     @arg LCD_BlinkMode_Off:           Blink disabled
00328   *     @arg LCD_BlinkMode_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
00329   *     @arg LCD_BlinkMode_SEG0_AllCOM:   Blink enabled on SEG[0], all COM (up to 8
00330   *                                       pixels according to the programmed duty)
00331   *     @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM
00332   *                                       (all pixels)
00333   * @param  LCD_BlinkFrequency: specifies the LCD blink frequency.
00334   *   This parameter can be one of the following values:
00335   *     @arg LCD_BlinkFrequency_Div8:    The Blink frequency = fLcd/8
00336   *     @arg LCD_BlinkFrequency_Div16:   The Blink frequency = fLcd/16
00337   *     @arg LCD_BlinkFrequency_Div32:   The Blink frequency = fLcd/32
00338   *     @arg LCD_BlinkFrequency_Div64:   The Blink frequency = fLcd/64
00339   *     @arg LCD_BlinkFrequency_Div128:  The Blink frequency = fLcd/128
00340   *     @arg LCD_BlinkFrequency_Div256:  The Blink frequency = fLcd/256
00341   *     @arg LCD_BlinkFrequency_Div512:  The Blink frequency = fLcd/512
00342   *     @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
00343   * @retval None
00344   */
00345 void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
00346 {
00347   /* Check the parameters */
00348   assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
00349   assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
00350
00351   LCD->FCR &= (uint32_t)BLINK_MASK;
00352   LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);
00353 }
00354
00355 /**
00356   * @brief  Configures the LCD Contrast.
00357   * @param  LCD_Contrast: specifies the LCD Contrast.
00358   *   This parameter can be one of the following values:
00359   *     @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V
00360   *     @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V
00361   *     @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V
00362   *     @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V
00363   *     @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V
00364   *     @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V
00365   *     @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V
00366   *     @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V
00367   * @retval None
00368   */
00369 void LCD_ContrastConfig(uint32_t LCD_Contrast)
00370 {
00371   /* Check the parameters */
00372   assert_param(IS_LCD_CONTRAST(LCD_Contrast));
00373
00374   LCD->FCR &= (uint32_t)CONTRAST_MASK;
00375   LCD->FCR |= (uint32_t)(LCD_Contrast);
00376 }
00377
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup LCD_Group2  LCD RAM memory write functions
00383  *  @brief    LCD RAM memory write functions
00384  *
00385 @verbatim
00386  ===============================================================================
00387                   ##### LCD RAM memory write functions #####
00388  ===============================================================================
00389     [..] Using its double buffer memory the LCD controller ensures the coherency
00390          of the displayed information without having to use interrupts to control
00391          LCD_RAM modification.
00392
00393     [..] The application software can access the first buffer level (LCD_RAM) through
00394          the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag
00395          in the LCD_SR register using the LCD_UpdateDisplayRequest() function.
00396
00397     [..] This UDR flag (update display request) requests the updated information
00398          to be moved into the second buffer level (LCD_DISPLAY).
00399
00400     [..] This operation is done synchronously with the frame (at the beginning of
00401          the next frame), until the update is completed, the LCD_RAM is write
00402          protected and the UDR flag stays high.
00403
00404     [..] Once the update is completed another flag (UDD - Update Display Done) is
00405          set and generates an interrupt if the UDDIE bit in the LCD_FCR register
00406         is set.
00407
00408     [..] The time it takes to update LCD_DISPLAY is, in the worst case, one odd
00409          and one even frame.
00410
00411     [..] The update will not occur (UDR = 1 and UDD = 0) until the display is
00412          enabled (LCDEN = 1).
00413
00414 @endverbatim
00415   * @{
00416   */
00417
00418 /**
00419   * @brief  Writes a word in the specific LCD RAM.
00420   * @param  LCD_RAMRegister: specifies the LCD Contrast.
00421   *   This parameter can be one of the following values:
00422   *     @arg LCD_RAMRegister_0: LCD RAM Register 0
00423   *     @arg LCD_RAMRegister_1: LCD RAM Register 1
00424   *     @arg LCD_RAMRegister_2: LCD RAM Register 2
00425   *     @arg LCD_RAMRegister_3: LCD RAM Register 3
00426   *     @arg LCD_RAMRegister_4: LCD RAM Register 4
00427   *     @arg LCD_RAMRegister_5: LCD RAM Register 5
00428   *     @arg LCD_RAMRegister_6: LCD RAM Register 6
00429   *     @arg LCD_RAMRegister_7: LCD RAM Register 7
00430   *     @arg LCD_RAMRegister_8: LCD RAM Register 8
00431   *     @arg LCD_RAMRegister_9: LCD RAM Register 9
00432   *     @arg LCD_RAMRegister_10: LCD RAM Register 10
00433   *     @arg LCD_RAMRegister_11: LCD RAM Register 11
00434   *     @arg LCD_RAMRegister_12: LCD RAM Register 12
00435   *     @arg LCD_RAMRegister_13: LCD RAM Register 13
00436   *     @arg LCD_RAMRegister_14: LCD RAM Register 14
00437   *     @arg LCD_RAMRegister_15: LCD RAM Register 15
00438   * @param  LCD_Data: specifies LCD Data Value to be written.
00439   * @retval None
00440   */
00441 void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)
00442 {
00443   /* Check the parameters */
00444   assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
00445
00446   /* Copy data bytes to RAM register */
00447   LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;
00448 }
00449
00450 /**
00451   * @brief  Enables the Update Display Request.
00452   * @note   Each time software modifies the LCD_RAM it must set the UDR bit to
00453   *         transfer the updated data to the second level buffer.
00454   *         The UDR bit stays set until the end of the update and during this
00455   *         time the LCD_RAM is write protected.
00456   * @note   When the display is disabled, the update is performed for all
00457   *         LCD_DISPLAY locations.
00458   *         When the display is enabled, the update is performed only for locations
00459   *         for which commons are active (depending on DUTY). For example if
00460   *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
00461   * @param  None
00462   * @retval None
00463   */
00464 void LCD_UpdateDisplayRequest(void)
00465 {
00466   *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;
00467 }
00468
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup LCD_Group3 Interrupts and flags management functions
00474  *  @brief   Interrupts and flags management functions
00475  *
00476 @verbatim
00477  ===============================================================================
00478             ##### Interrupts and flags management functions #####
00479  ===============================================================================
00480
00481 @endverbatim
00482   * @{
00483   */
00484
00485 /**
00486   * @brief  Enables or disables the specified LCD interrupts.
00487   * @param  LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.
00488   *   This parameter can be any combination of the following values:
00489   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00490   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00491   * @param NewState: new state of the specified LCD interrupts.
00492   *   This parameter can be: ENABLE or DISABLE.
00493   * @retval None
00494   */
00495 void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)
00496 {
00497   /* Check the parameters */
00498   assert_param(IS_LCD_IT(LCD_IT));
00499   assert_param(IS_FUNCTIONAL_STATE(NewState));
00500
00501   if (NewState != DISABLE)
00502   {
00503     LCD->FCR |= LCD_IT;
00504   }
00505   else
00506   {
00507     LCD->FCR &= (uint32_t)~LCD_IT;
00508   }
00509 }
00510
00511 /**
00512   * @brief  Checks whether the specified LCD flag is set or not.
00513   * @param  LCD_FLAG: specifies the flag to check.
00514   *   This parameter can be one of the following values:
00515   *     @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
00516   *      @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
00517   *             goes from 0 to 1. On deactivation it reflects the real status of
00518   *             LCD so it becomes 0 at the end of the last displayed frame.
00519   *     @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
00520   *       the beginning of a new frame, at the same time as the display data is
00521   *       updated.
00522   *     @arg LCD_FLAG_UDR: Update Display Request flag.
00523   *     @arg LCD_FLAG_UDD: Update Display Done flag.
00524   *     @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
00525   *                        of the step-up converter.
00526   *     @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
00527   *       This flag is set by hardware each time the LCD_FCR register is updated
00528   *       in the LCDCLK domain.
00529   * @retval The new state of LCD_FLAG (SET or RESET).
00530   */
00531 FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)
00532 {
00533   FlagStatus bitstatus = RESET;
00534
00535   /* Check the parameters */
00536   assert_param(IS_LCD_GET_FLAG(LCD_FLAG));
00537
00538   if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)
00539   {
00540     bitstatus = SET;
00541   }
00542   else
00543   {
00544     bitstatus = RESET;
00545   }
00546   return bitstatus;
00547 }
00548
00549 /**
00550   * @brief  Clears the LCD's pending flags.
00551   * @param  LCD_FLAG: specifies the flag to clear.
00552   *   This parameter can be any combination of the following values:
00553   *     @arg LCD_FLAG_SOF: Start of Frame Interrupt
00554   *     @arg LCD_FLAG_UDD: Update Display Done Interrupt
00555   * @retval None
00556   */
00557 void LCD_ClearFlag(uint32_t LCD_FLAG)
00558 {
00559   /* Check the parameters */
00560   assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));
00561
00562   /* Clear the corresponding LCD flag */
00563   LCD->CLR = (uint32_t)LCD_FLAG;
00564 }
00565
00566 /**
00567   * @brief  Checks whether the specified RTC interrupt has occurred or not.
00568   * @param  LCD_IT: specifies the LCD interrupts sources to check.
00569   *   This parameter can be one of the following values:
00570   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00571   *     @arg LCD_IT_UDD: Update Display Done Interrupt.
00572   *     @note If the device is in STOP mode (PCLK not provided) UDD will not
00573   *          generate an interrupt even if UDDIE = 1.
00574   *          If the display is not enabled the UDD interrupt will never occur.
00575   * @retval The new state of the LCD_IT (SET or RESET).
00576   */
00577 ITStatus LCD_GetITStatus(uint32_t LCD_IT)
00578 {
00579   ITStatus bitstatus = RESET;
00580
00581   /* Check the parameters */
00582   assert_param(IS_LCD_GET_IT(LCD_IT));
00583
00584   if ((LCD->SR & LCD_IT) != (uint16_t)RESET)
00585   {
00586     bitstatus = SET;
00587   }
00588   else
00589   {
00590     bitstatus = RESET;
00591   }
00592
00593   if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))
00594   {
00595     bitstatus = SET;
00596   }
00597   else
00598   {
00599     bitstatus = RESET;
00600   }
00601   return bitstatus;
00602 }
00603
00604 /**
00605   * @brief  Clears the LCD's interrupt pending bits.
00606   * @param  LCD_IT: specifies the interrupt pending bit to clear.
00607   *   This parameter can be any combination of the following values:
00608   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00609   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00610   * @retval None
00611   */
00612 void LCD_ClearITPendingBit(uint32_t LCD_IT)
00613 {
00614   /* Check the parameters */
00615   assert_param(IS_LCD_IT(LCD_IT));
00616
00617   /* Clear the corresponding LCD pending bit */
00618   LCD->CLR = (uint32_t)LCD_IT;
00619 }
00620
00621 /**
00622   * @}
00623   */
00624
00625 /**
00626   * @}
00627   */
00628
00629 /**
00630   * @}
00631   */
00632
00633 /**
00634   * @}
00635   */
00636
00637 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_lcd.h Source File

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stm32l1xx_lcd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_lcd.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the LCD firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_LCD_H
00028 #define __STM32L1xx_LCD_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup LCD
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  LCD Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t LCD_Prescaler;     /*!< Configures the LCD Prescaler.
00054                                    This parameter can be one value of @ref LCD_Prescaler */
00055   uint32_t LCD_Divider;       /*!< Configures the LCD Divider.
00056                                   This parameter can be one value of @ref LCD_Divider */
00057   uint32_t LCD_Duty;          /*!< Configures the LCD Duty.
00058                                   This parameter can be one value of @ref LCD_Duty */
00059   uint32_t LCD_Bias;          /*!< Configures the LCD Bias.
00060                                   This parameter can be one value of @ref LCD_Bias */
00061   uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.
00062                                   This parameter can be one value of @ref LCD_Voltage_Source */
00063 }LCD_InitTypeDef;
00064
00065
00066 /* Exported constants --------------------------------------------------------*/
00067
00068 /** @defgroup LCD_Exported_Constants
00069   * @{
00070   */
00071
00072 /** @defgroup LCD_Prescaler
00073   * @{
00074   */
00075
00076 #define LCD_Prescaler_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
00077 #define LCD_Prescaler_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
00078 #define LCD_Prescaler_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
00079 #define LCD_Prescaler_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
00080 #define LCD_Prescaler_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
00081 #define LCD_Prescaler_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
00082 #define LCD_Prescaler_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
00083 #define LCD_Prescaler_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
00084 #define LCD_Prescaler_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
00085 #define LCD_Prescaler_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
00086 #define LCD_Prescaler_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
00087 #define LCD_Prescaler_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
00088 #define LCD_Prescaler_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
00089 #define LCD_Prescaler_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
00090 #define LCD_Prescaler_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
00091 #define LCD_Prescaler_32768    ((uint32_t)0x03C00000)  /*!< CLKPS = LCDCLK/32768  */
00092
00093 #define IS_LCD_PRESCALER(PRESCALER)    (((PRESCALER) == LCD_Prescaler_1) || \
00094                                         ((PRESCALER) == LCD_Prescaler_2) || \
00095                                         ((PRESCALER) == LCD_Prescaler_4) || \
00096                                         ((PRESCALER) == LCD_Prescaler_8) || \
00097                                         ((PRESCALER) == LCD_Prescaler_16) || \
00098                                         ((PRESCALER) == LCD_Prescaler_32) || \
00099                                         ((PRESCALER) == LCD_Prescaler_64) || \
00100                                         ((PRESCALER) == LCD_Prescaler_128) || \
00101                                         ((PRESCALER) == LCD_Prescaler_256) || \
00102                                         ((PRESCALER) == LCD_Prescaler_512) || \
00103                                         ((PRESCALER) == LCD_Prescaler_1024) || \
00104                                         ((PRESCALER) == LCD_Prescaler_2048) || \
00105                                         ((PRESCALER) == LCD_Prescaler_4096) || \
00106                                         ((PRESCALER) == LCD_Prescaler_8192) || \
00107                                         ((PRESCALER) == LCD_Prescaler_16384) || \
00108                                         ((PRESCALER) == LCD_Prescaler_32768))
00109
00110 /**
00111   * @}
00112   */
00113
00114 /** @defgroup LCD_Divider
00115   * @{
00116   */
00117
00118 #define LCD_Divider_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
00119 #define LCD_Divider_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
00120 #define LCD_Divider_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
00121 #define LCD_Divider_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
00122 #define LCD_Divider_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
00123 #define LCD_Divider_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
00124 #define LCD_Divider_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
00125 #define LCD_Divider_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
00126 #define LCD_Divider_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
00127 #define LCD_Divider_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
00128 #define LCD_Divider_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
00129 #define LCD_Divider_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
00130 #define LCD_Divider_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
00131 #define LCD_Divider_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
00132 #define LCD_Divider_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
00133 #define LCD_Divider_31    ((uint32_t)0x003C0000)  /*!< LCD frequency = CLKPS/31 */
00134
00135 #define IS_LCD_DIVIDER(DIVIDER)    (((DIVIDER) == LCD_Divider_16) || \
00136                                     ((DIVIDER) == LCD_Divider_17) || \
00137                                     ((DIVIDER) == LCD_Divider_18) || \
00138                                     ((DIVIDER) == LCD_Divider_19) || \
00139                                     ((DIVIDER) == LCD_Divider_20) || \
00140                                     ((DIVIDER) == LCD_Divider_21) || \
00141                                     ((DIVIDER) == LCD_Divider_22) || \
00142                                     ((DIVIDER) == LCD_Divider_23) || \
00143                                     ((DIVIDER) == LCD_Divider_24) || \
00144                                     ((DIVIDER) == LCD_Divider_25) || \
00145                                     ((DIVIDER) == LCD_Divider_26) || \
00146                                     ((DIVIDER) == LCD_Divider_27) || \
00147                                     ((DIVIDER) == LCD_Divider_28) || \
00148                                     ((DIVIDER) == LCD_Divider_29) || \
00149                                     ((DIVIDER) == LCD_Divider_30) || \
00150                                     ((DIVIDER) == LCD_Divider_31))
00151
00152 /**
00153   * @}
00154   */
00155
00156
00157 /** @defgroup LCD_Duty
00158   * @{
00159   */
00160
00161 #define LCD_Duty_Static                 ((uint32_t)0x00000000) /*!< Static duty */
00162 #define LCD_Duty_1_2                    ((uint32_t)0x00000004) /*!< 1/2 duty    */
00163 #define LCD_Duty_1_3                    ((uint32_t)0x00000008) /*!< 1/3 duty    */
00164 #define LCD_Duty_1_4                    ((uint32_t)0x0000000C) /*!< 1/4 duty    */
00165 #define LCD_Duty_1_8                    ((uint32_t)0x00000010) /*!< 1/4 duty    */
00166
00167 #define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \
00168                            ((DUTY) == LCD_Duty_1_2) || \
00169                            ((DUTY) == LCD_Duty_1_3) || \
00170                            ((DUTY) == LCD_Duty_1_4) || \
00171                            ((DUTY) == LCD_Duty_1_8))
00172
00173 /**
00174   * @}
00175   */
00176
00177
00178 /** @defgroup LCD_Bias
00179   * @{
00180   */
00181
00182 #define LCD_Bias_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
00183 #define LCD_Bias_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
00184 #define LCD_Bias_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
00185
00186 #define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
00187                            ((BIAS) == LCD_Bias_1_2) || \
00188                            ((BIAS) == LCD_Bias_1_3))
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup LCD_Voltage_Source
00194   * @{
00195   */
00196
00197 #define LCD_VoltageSource_Internal      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
00198 #define LCD_VoltageSource_External      LCD_CR_VSEL             /*!< External voltage source for the LCD */
00199
00200 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
00201                                        ((SOURCE) == LCD_VoltageSource_External))
00202
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup LCD_Interrupts
00208   * @{
00209   */
00210 #define LCD_IT_SOF                      LCD_FCR_SOFIE
00211 #define LCD_IT_UDD                      LCD_FCR_UDDIE
00212
00213 #define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))
00214
00215 #define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup LCD_PulseOnDuration
00222   * @{
00223   */
00224
00225 #define LCD_PulseOnDuration_0           ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse   */
00226 #define LCD_PulseOnDuration_1           ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS  */
00227 #define LCD_PulseOnDuration_2           ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS  */
00228 #define LCD_PulseOnDuration_3           ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS  */
00229 #define LCD_PulseOnDuration_4           ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS  */
00230 #define LCD_PulseOnDuration_5           ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS  */
00231 #define LCD_PulseOnDuration_6           ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS  */
00232 #define LCD_PulseOnDuration_7           ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS  */
00233
00234 #define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
00235                                             ((DURATION) == LCD_PulseOnDuration_1) || \
00236                                             ((DURATION) == LCD_PulseOnDuration_2) || \
00237                                             ((DURATION) == LCD_PulseOnDuration_3) || \
00238                                             ((DURATION) == LCD_PulseOnDuration_4) || \
00239                                             ((DURATION) == LCD_PulseOnDuration_5) || \
00240                                             ((DURATION) == LCD_PulseOnDuration_6) || \
00241                                             ((DURATION) == LCD_PulseOnDuration_7))
00242 /**
00243   * @}
00244   */
00245
00246
00247 /** @defgroup LCD_DeadTime
00248   * @{
00249   */
00250
00251 #define LCD_DeadTime_0                  ((uint32_t)0x00000000) /*!< No dead Time  */
00252 #define LCD_DeadTime_1                  ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame   */
00253 #define LCD_DeadTime_2                  ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame   */
00254 #define LCD_DeadTime_3                  ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */
00255 #define LCD_DeadTime_4                  ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame  */
00256 #define LCD_DeadTime_5                  ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame  */
00257 #define LCD_DeadTime_6                  ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame   */
00258 #define LCD_DeadTime_7                  ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */
00259
00260 #define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
00261                                 ((TIME) == LCD_DeadTime_1) || \
00262                                 ((TIME) == LCD_DeadTime_2) || \
00263                                 ((TIME) == LCD_DeadTime_3) || \
00264                                 ((TIME) == LCD_DeadTime_4) || \
00265                                 ((TIME) == LCD_DeadTime_5) || \
00266                                 ((TIME) == LCD_DeadTime_6) || \
00267                                 ((TIME) == LCD_DeadTime_7))
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LCD_BlinkMode
00273   * @{
00274   */
00275
00276 #define LCD_BlinkMode_Off               ((uint32_t)0x00000000) /*!< Blink disabled            */
00277 #define LCD_BlinkMode_SEG0_COM0         ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
00278 #define LCD_BlinkMode_SEG0_AllCOM       ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to
00279                                                                     8 pixels according to the programmed duty)  */
00280 #define LCD_BlinkMode_AllSEG_AllCOM     ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels)  */
00281
00282 #define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \
00283                                  ((MODE) == LCD_BlinkMode_SEG0_COM0) || \
00284                                  ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \
00285                                  ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup LCD_BlinkFrequency
00291   * @{
00292   */
00293
00294 #define LCD_BlinkFrequency_Div8         ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8    */
00295 #define LCD_BlinkFrequency_Div16        ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16   */
00296 #define LCD_BlinkFrequency_Div32        ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32   */
00297 #define LCD_BlinkFrequency_Div64        ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64   */
00298 #define LCD_BlinkFrequency_Div128       ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128  */
00299 #define LCD_BlinkFrequency_Div256       ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256  */
00300 #define LCD_BlinkFrequency_Div512       ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512  */
00301 #define LCD_BlinkFrequency_Div1024      ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */
00302
00303 #define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \
00304                                            ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \
00305                                            ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \
00306                                            ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \
00307                                            ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \
00308                                            ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \
00309                                            ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \
00310                                            ((FREQUENCY) == LCD_BlinkFrequency_Div1024))
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup LCD_Contrast
00316   * @{
00317   */
00318
00319 #define LCD_Contrast_Level_0               ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V    */
00320 #define LCD_Contrast_Level_1               ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V    */
00321 #define LCD_Contrast_Level_2               ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V    */
00322 #define LCD_Contrast_Level_3               ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V    */
00323 #define LCD_Contrast_Level_4               ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V    */
00324 #define LCD_Contrast_Level_5               ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V    */
00325 #define LCD_Contrast_Level_6               ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V    */
00326 #define LCD_Contrast_Level_7               ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V    */
00327
00328 #define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
00329                                    ((CONTRAST) == LCD_Contrast_Level_1) || \
00330                                    ((CONTRAST) == LCD_Contrast_Level_2) || \
00331                                    ((CONTRAST) == LCD_Contrast_Level_3) || \
00332                                    ((CONTRAST) == LCD_Contrast_Level_4) || \
00333                                    ((CONTRAST) == LCD_Contrast_Level_5) || \
00334                                    ((CONTRAST) == LCD_Contrast_Level_6) || \
00335                                    ((CONTRAST) == LCD_Contrast_Level_7))
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup LCD_Flag
00341   * @{
00342   */
00343
00344 #define LCD_FLAG_ENS                    LCD_SR_ENS
00345 #define LCD_FLAG_SOF                    LCD_SR_SOF
00346 #define LCD_FLAG_UDR                    LCD_SR_UDR
00347 #define LCD_FLAG_UDD                    LCD_SR_UDD
00348 #define LCD_FLAG_RDY                    LCD_SR_RDY
00349 #define LCD_FLAG_FCRSF                  LCD_SR_FCRSR
00350
00351 #define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \
00352                                ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \
00353                                ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))
00354
00355 #define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup LCD_RAMRegister
00361   * @{
00362   */
00363
00364 #define LCD_RAMRegister_0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
00365 #define LCD_RAMRegister_1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
00366 #define LCD_RAMRegister_2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
00367 #define LCD_RAMRegister_3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
00368 #define LCD_RAMRegister_4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
00369 #define LCD_RAMRegister_5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
00370 #define LCD_RAMRegister_6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
00371 #define LCD_RAMRegister_7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
00372 #define LCD_RAMRegister_8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
00373 #define LCD_RAMRegister_9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
00374 #define LCD_RAMRegister_10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
00375 #define LCD_RAMRegister_11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
00376 #define LCD_RAMRegister_12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
00377 #define LCD_RAMRegister_13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
00378 #define LCD_RAMRegister_14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
00379 #define LCD_RAMRegister_15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
00380
00381 #define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
00382                                        ((REGISTER) == LCD_RAMRegister_1) || \
00383                                        ((REGISTER) == LCD_RAMRegister_2) || \
00384                                        ((REGISTER) == LCD_RAMRegister_3) || \
00385                                        ((REGISTER) == LCD_RAMRegister_4) || \
00386                                        ((REGISTER) == LCD_RAMRegister_5) || \
00387                                        ((REGISTER) == LCD_RAMRegister_6) || \
00388                                        ((REGISTER) == LCD_RAMRegister_7) || \
00389                                        ((REGISTER) == LCD_RAMRegister_8) || \
00390                                        ((REGISTER) == LCD_RAMRegister_9) || \
00391                                        ((REGISTER) == LCD_RAMRegister_10) || \
00392                                        ((REGISTER) == LCD_RAMRegister_11) || \
00393                                        ((REGISTER) == LCD_RAMRegister_12) || \
00394                                        ((REGISTER) == LCD_RAMRegister_13) || \
00395                                        ((REGISTER) == LCD_RAMRegister_14) || \
00396                                        ((REGISTER) == LCD_RAMRegister_15))
00397
00398 /**
00399   * @}
00400   */
00401
00402 /**
00403   * @}
00404   */
00405
00406 /* Exported macro ------------------------------------------------------------*/
00407 /* Exported functions ------------------------------------------------------- */
00408
00409 /*  Function used to set the LCD configuration to the default reset state *****/
00410 void LCD_DeInit(void);
00411
00412 /* Initialization and Configuration functions *********************************/
00413 void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);
00414 void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);
00415 void LCD_Cmd(FunctionalState NewState);
00416 void LCD_WaitForSynchro(void);
00417 void LCD_HighDriveCmd(FunctionalState NewState);
00418 void LCD_MuxSegmentCmd(FunctionalState NewState);
00419 void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);
00420 void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);
00421 void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);
00422 void LCD_ContrastConfig(uint32_t LCD_Contrast);
00423
00424 /* LCD RAM memory write functions *********************************************/
00425 void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);
00426 void LCD_UpdateDisplayRequest(void);
00427
00428 /* Interrupts and flags management functions **********************************/
00429 void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);
00430 FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);
00431 void LCD_ClearFlag(uint32_t LCD_FLAG);
00432 ITStatus LCD_GetITStatus(uint32_t LCD_IT);
00433 void LCD_ClearITPendingBit(uint32_t LCD_IT);
00434
00435 #ifdef __cplusplus
00436 }
00437 #endif
00438
00439 #endif /* __STM32L1xx_LCD_H */
00440
00441 /**
00442   * @}
00443   */
00444
00445 /**
00446   * @}
00447   */
00448
00449 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_opamp.c Source File

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stm32l1xx_opamp.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_opamp.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the operational amplifiers (opamp) peripheral:
00009   *           + Initialization and configuration
00010   *           + Calibration management
00011   *
00012   *  @verbatim
00013   ==============================================================================
00014                             ##### How to use this driver #####
00015   ==============================================================================
00016     [..] The device integrates three independent rail-to-rail operational amplifiers
00017          OPAMP1, OPAMP2 and OPAMP3:
00018                (+) Internal connections to the ADC.
00019                (+) Internal connections to the DAC.
00020                (+) Internal connection to COMP1 (only OPAMP3).
00021                (+) Internal connection for unity gain (voltage follower) configuration.
00022                (+) Calibration capability.
00023                (+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).
00024     [..]
00025          (#) COMP AHB clock must be enabled to get write access
00026              to OPAMP registers using
00027          (#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)
00028
00029          (#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)
00030              and OPAMPx_OUT in analog mode.
00031
00032          (#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()
00033
00034          (#) Enable the OPAMP peripheral using OPAMP_Cmd()
00035
00036          -@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled
00037              and the ADC must use the OPAMP output channel number:
00038              (+@) OPAMP1 output is connected to ADC channel 3.
00039              (+@) OPAMP2 output is connected to ADC channel 8.
00040              (+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).
00041
00042   *  @endverbatim
00043   *
00044   ******************************************************************************
00045   * @attention
00046   *
00047   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00048   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00049   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00050   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00051   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00052   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00053   *
00054   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00055   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00056   *
00057   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00058   ******************************************************************************
00059   */
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32l1xx_opamp.h"
00063
00064
00065 /** @addtogroup STM32L1xx_StdPeriph_Driver
00066   * @{
00067   */
00068
00069 /** @defgroup OPAMP
00070   * @brief OPAMP driver modules
00071   * @{
00072   */
00073
00074 /* Private typedef -----------------------------------------------------------*/
00075 /* Private define ------------------------------------------------------------*/
00076 /* Private macro -------------------------------------------------------------*/
00077 /* Private variables ---------------------------------------------------------*/
00078 /* Private function prototypes -----------------------------------------------*/
00079 /* Private functions ---------------------------------------------------------*/
00080
00081 /** @defgroup OPAMP_Private_Functions
00082   * @{
00083   */
00084
00085 /** @defgroup OPAMP_Group1 Initialization and configuration
00086  *  @brief   Initialization and configuration
00087  *
00088 @verbatim
00089  ===============================================================================
00090                             ##### Initialization and configuration #####
00091  ===============================================================================
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Deinitialize the OPAMPs register to its default reset value.
00099   * @note   At startup, OTR and LPOTR registers are set to factory programmed values.
00100   * @param  None.
00101   * @retval None.
00102   */
00103 void OPAMP_DeInit(void)
00104 {
00105   /*!< Set OPAMP_CSR register to reset value */
00106   OPAMP->CSR = 0x00010101;
00107   /*!< Set OPAMP_OTR register to reset value */
00108   OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);
00109   /*!< Set OPAMP_LPOTR register to reset value */
00110   OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);
00111 }
00112
00113 /**
00114   * @brief  Close or Open the OPAMP switches.
00115   * @param  OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.
00116   *   This parameter can be any combinations of the following values:
00117   *     @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to
00118   *                               OPAMP1 negative input (internal follower)
00119   *     @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
00120   *     @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
00121   *     @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
00122   *     @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
00123   *     @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to
00124   *                               OPAMP2 negative input (internal follower)
00125   *     @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
00126   *     @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
00127   *     @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
00128   *     @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
00129   *     @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
00130   *     @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to
00131   *                               OPAMP3 negative input (internal follower)
00132   *     @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
00133   *     @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
00134   *     @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
00135   *     @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
00136   *
00137   * @param  NewState: New state of the OPAMP switch.
00138   *   This parameter can be:
00139   *     ENABLE to close the OPAMP switch
00140   *     or DISABLE to open the OPAMP switch
00141   * @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
00142   * @retval None
00143   */
00144 void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
00145 {
00146   /* Check the parameter */
00147   assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));
00148   assert_param(IS_FUNCTIONAL_STATE(NewState));
00149
00150   if (NewState != DISABLE)
00151   {
00152     /* Close the selected switches */
00153     OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;
00154   }
00155   else
00156   {
00157     /* Open the selected switches */
00158     OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);
00159   }
00160 }
00161
00162 /**
00163   * @brief  Enable or disable the OPAMP peripheral.
00164   * @param  OPAMP_Selection: the selected OPAMP.
00165   *   This parameter can be one of the following values:
00166   *     @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected
00167   *     @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected
00168   *     @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected
00169   * @param  NewState: new state of the selected OPAMP peripheral.
00170   *         This parameter can be: ENABLE or DISABLE.
00171   * @retval None
00172   */
00173 void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
00174 {
00175   /* Check the parameter */
00176   assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
00177   assert_param(IS_FUNCTIONAL_STATE(NewState));
00178
00179   if (NewState != DISABLE)
00180   {
00181     /* Enable the selected OPAMP */
00182     OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);
00183   }
00184   else
00185   {
00186     /* Disable the selected OPAMP */
00187     OPAMP->CSR |= (uint32_t) OPAMP_Selection;
00188   }
00189 }
00190
00191 /**
00192   * @brief  Enable or disable the low power mode for OPAMP peripheral.
00193   * @param  OPAMP_Selection: the selected OPAMP.
00194   *   This parameter can be one of the following values:
00195   *     @arg OPAMP_Selection_OPAMP1: OPAMP1 selected
00196   *     @arg OPAMP_Selection_OPAMP2: OPAMP2 selected
00197   *     @arg OPAMP_Selection_OPAMP3: OPAMP3 selected
00198   * @param  NewState: new low power state of the selected OPAMP peripheral.
00199   *         This parameter can be: ENABLE or DISABLE.
00200   * @retval None
00201   */
00202 void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
00203 {
00204   /* Check the parameter */
00205   assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
00206   assert_param(IS_FUNCTIONAL_STATE(NewState));
00207
00208   if (NewState != DISABLE)
00209   {
00210     /* Set the selected OPAMP in low power mode */
00211     OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);
00212   }
00213   else
00214   {
00215     /* Disable the low power mode for the selected OPAMP */
00216     OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));
00217   }
00218 }
00219
00220 /**
00221   * @brief  Select the OPAMP power range.
00222   * @note   The OPAMP power range selection must be performed while OPAMPs are powered down.
00223   * @param  OPAMP_Range: the selected OPAMP power range.
00224   *   This parameter can be one of the following values:
00225   *     @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
00226   *     @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
00227   * @retval None
00228   */
00229 void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)
00230 {
00231   /* Check the parameter */
00232   assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));
00233
00234   /* Reset the OPAMP range bit */
00235   OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));
00236
00237   /* Select the OPAMP power range */
00238   OPAMP->CSR |= OPAMP_PowerRange;
00239 }
00240
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup OPAMP_Group2 Calibration functions
00246  *  @brief   Calibration functions
00247  *
00248 @verbatim
00249  ===============================================================================
00250                             ##### Calibration functions #####
00251  ===============================================================================
00252
00253 @endverbatim
00254   * @{
00255   */
00256
00257 /**
00258   * @brief  Select the trimming mode.
00259   * @param  OffsetTrimming: the selected offset trimming mode.
00260   *   This parameter  can be one of the following values:
00261   *     @arg OffsetTrimming_Factory: factory trimming values are used for offset
00262   *                                  calibration.
00263   *     @arg OffsetTrimming_User: user trimming values are used for offset
00264   *                               calibration.
00265   * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
00266   *       function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
00267   *       trimming value.
00268   * @retval None
00269   */
00270 void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)
00271 {
00272   /* Check the parameter */
00273   assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
00274
00275   /* Reset the OPAMP_OTR range bit */
00276   OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));
00277
00278   /* Select the OPAMP offset trimming  */
00279   OPAMP->CSR |= OPAMP_Trimming;
00280
00281 }
00282
00283 /**
00284   * @brief  Configure the trimming value of OPAMPs in normal mode.
00285   * @param  OPAMP_Selection: the selected OPAMP.
00286   *   This parameter can be one of the following values:
00287   *         @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
00288   *         @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
00289   *         @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
00290   * @param  OPAMP_Input: the selected OPAMP input.
00291   *   This parameter can be one of the following values:
00292   *         @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
00293   *         @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
00294   * @param  OPAMP_TrimValue: the trimming value. This parameter can be any value lower
00295   *         or equal to 0x0000001F.
00296   * @retval None
00297   */
00298 void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
00299 {
00300   uint32_t tmpreg = 0;
00301
00302   /* Check the parameter */
00303   assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
00304   assert_param(IS_OPAMP_INPUT(OPAMP_Input));
00305   assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
00306
00307   /* Get the OPAMP_OTR value */
00308   tmpreg = OPAMP->OTR;
00309
00310   if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
00311   {
00312     /* Reset the OPAMP inputs selection */
00313     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
00314     /* Select the OPAMP input */
00315     tmpreg |= OPAMP_Input;
00316
00317     if(OPAMP_Input == OPAMP_Input_PMOS)
00318     {
00319       /* Reset the trimming value corresponding to OPAMP1 PMOS input */
00320       tmpreg &= (0xFFFFFFE0);
00321       /* Set the new trimming value corresponding to OPAMP1 PMOS input */
00322       tmpreg |= (OPAMP_TrimValue);
00323     }
00324     else
00325     {
00326       /* Reset the trimming value corresponding to OPAMP1 NMOS input */
00327       tmpreg &= (0xFFFFFC1F);
00328       /* Set the new trimming value corresponding to OPAMP1 NMOS input */
00329       tmpreg |= (OPAMP_TrimValue<<5);
00330     }
00331   }
00332   else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
00333   {
00334     /* Reset the OPAMP inputs selection */
00335     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
00336     /* Select the OPAMP input */
00337     tmpreg |= (uint32_t)(OPAMP_Input<<8);
00338
00339     if(OPAMP_Input == OPAMP_Input_PMOS)
00340     {
00341       /* Reset the trimming value corresponding to OPAMP2 PMOS input */
00342       tmpreg &= (0xFFFF83FF);
00343       /* Set the new trimming value corresponding to OPAMP2 PMOS input */
00344       tmpreg |= (OPAMP_TrimValue<<10);
00345     }
00346     else
00347     {
00348       /* Reset the trimming value corresponding to OPAMP2 NMOS input */
00349       tmpreg &= (0xFFF07FFF);
00350       /* Set the new trimming value corresponding to OPAMP2 NMOS input */
00351       tmpreg |= (OPAMP_TrimValue<<15);
00352     }
00353   }
00354   else
00355   {
00356     /* Reset the OPAMP inputs selection */
00357     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
00358     /* Select the OPAMP input */
00359     tmpreg |= (uint32_t)(OPAMP_Input<<16);
00360
00361     if(OPAMP_Input == OPAMP_Input_PMOS)
00362     {
00363       /* Reset the trimming value corresponding to OPAMP3 PMOS input */
00364       tmpreg &= (0xFE0FFFFF);
00365       /* Set the new trimming value corresponding to OPAMP3 PMOS input */
00366       tmpreg |= (OPAMP_TrimValue<<20);
00367     }
00368     else
00369     {
00370       /* Reset the trimming value corresponding to OPAMP3 NMOS input */
00371       tmpreg &= (0xC1FFFFFF);
00372       /* Set the new trimming value corresponding to OPAMP3 NMOS input */
00373       tmpreg |= (OPAMP_TrimValue<<25);
00374     }
00375   }
00376
00377   /* Set the OPAMP_OTR register */
00378   OPAMP->OTR = tmpreg;
00379 }
00380
00381 /**
00382   * @brief  Configure the trimming value of OPAMPs in low power mode.
00383   * @param  OPAMP_Selection: the selected OPAMP.
00384   *   This parameter can be one of the following values:
00385   *         @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
00386   *         @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
00387   *         @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
00388   * @param  OPAMP_Input: the selected OPAMP input.
00389   *   This parameter can be one of the following values:
00390   *         @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
00391   *         @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
00392   * @param  OPAMP_TrimValue: the trimming value.
00393   *    This parameter can be any value lower or equal to 0x0000001F.
00394   * @retval None
00395   */
00396 void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
00397 {
00398   uint32_t tmpreg = 0;
00399
00400   /* Check the parameter */
00401   assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
00402   assert_param(IS_OPAMP_INPUT(OPAMP_Input));
00403   assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
00404
00405   /* Get the OPAMP_LPOTR value */
00406   tmpreg = OPAMP->LPOTR;
00407
00408   if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
00409   {
00410     /* Reset the OPAMP inputs selection */
00411     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
00412     /* Select the OPAMP input */
00413     tmpreg |= OPAMP_Input;
00414
00415     if(OPAMP_Input == OPAMP_Input_PMOS)
00416     {
00417       /* Reset the trimming value corresponding to OPAMP1 PMOS input */
00418       tmpreg &= (0xFFFFFFE0);
00419       /* Set the new trimming value corresponding to OPAMP1 PMOS input */
00420       tmpreg |= (OPAMP_TrimValue);
00421     }
00422     else
00423     {
00424       /* Reset the trimming value corresponding to OPAMP1 NMOS input */
00425       tmpreg &= (0xFFFFFC1F);
00426       /* Set the new trimming value corresponding to OPAMP1 NMOS input */
00427       tmpreg |= (OPAMP_TrimValue<<5);
00428     }
00429   }
00430   else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
00431   {
00432     /* Reset the OPAMP inputs selection */
00433     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
00434     /* Select the OPAMP input */
00435     tmpreg |= (uint32_t)(OPAMP_Input<<8);
00436
00437     if(OPAMP_Input == OPAMP_Input_PMOS)
00438     {
00439       /* Reset the trimming value corresponding to OPAMP2 PMOS input */
00440       tmpreg &= (0xFFFF83FF);
00441       /* Set the new trimming value corresponding to OPAMP2 PMOS input */
00442       tmpreg |= (OPAMP_TrimValue<<10);
00443     }
00444     else
00445     {
00446       /* Reset the trimming value corresponding to OPAMP2 NMOS input */
00447       tmpreg &= (0xFFF07FFF);
00448       /* Set the new trimming value corresponding to OPAMP2 NMOS input */
00449       tmpreg |= (OPAMP_TrimValue<<15);
00450     }
00451   }
00452   else
00453   {
00454     /* Reset the OPAMP inputs selection */
00455     tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
00456     /* Select the OPAMP input */
00457     tmpreg |= (uint32_t)(OPAMP_Input<<16);
00458
00459     if(OPAMP_Input == OPAMP_Input_PMOS)
00460     {
00461       /* Reset the trimming value corresponding to OPAMP3 PMOS input */
00462       tmpreg &= (0xFE0FFFFF);
00463       /* Set the new trimming value corresponding to OPAMP3 PMOS input */
00464       tmpreg |= (OPAMP_TrimValue<<20);
00465     }
00466     else
00467     {
00468       /* Reset the trimming value corresponding to OPAMP3 NMOS input */
00469       tmpreg &= (0xC1FFFFFF);
00470       /* Set the new trimming value corresponding to OPAMP3 NMOS input */
00471       tmpreg |= (OPAMP_TrimValue<<25);
00472     }
00473   }
00474
00475   /* Set the OPAMP_LPOTR register */
00476   OPAMP->LPOTR = tmpreg;
00477 }
00478
00479 /**
00480   * @brief  Checks whether the specified OPAMP calibration flag is set or not.
00481   * @note   User should wait until calibration flag change the value when changing
00482   *         the trimming value.
00483   * @param  OPAMP_Selection: the selected OPAMP.
00484   *   This parameter can be one of the following values:
00485   *     @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.
00486   *     @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.
00487   *     @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.
00488   * @retval The new state of the OPAMP calibration flag (SET or RESET).
00489   */
00490 FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)
00491 {
00492   FlagStatus bitstatus = RESET;
00493   uint32_t tmpreg = 0;
00494
00495   /* Check the parameter */
00496   assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
00497
00498   /* Get the CSR register value */
00499   tmpreg = OPAMP->CSR;
00500
00501   /* Check if OPAMP1 is selected */
00502   if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
00503   {
00504     /* Check OPAMP1 CAL bit status */
00505     if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)
00506     {
00507       bitstatus = SET;
00508     }
00509     else
00510     {
00511       bitstatus = RESET;
00512     }
00513   }
00514   /* Check if OPAMP2 is selected */
00515   else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)
00516   {
00517     /* Check OPAMP2 CAL bit status */
00518     if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)
00519     {
00520       bitstatus = SET;
00521     }
00522     else
00523     {
00524       bitstatus = RESET;
00525     }
00526   }
00527   else
00528   {
00529     /* Check OPAMP3 CAL bit status */
00530     if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)
00531     {
00532       bitstatus = SET;
00533     }
00534     else
00535     {
00536       bitstatus = RESET;
00537     }
00538   }
00539   return bitstatus;
00540 }
00541
00542 /**
00543   * @}
00544   */
00545
00546 /**
00547   * @}
00548   */
00549
00550 /**
00551   * @}
00552   */
00553
00554 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_opamp.h Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
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  • inc

stm32l1xx_opamp.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_opamp.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the operational
00008   *          amplifiers (opamp) firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_OPAMP_H
00028 #define __STM32L1xx_OPAMP_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup OPAMP
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup OPAMP_Exported_Constants
00049   * @{
00050   */
00051
00052 /** @defgroup OPAMP_Selection
00053   * @{
00054   */
00055
00056 #define OPAMP_Selection_OPAMP1                    OPAMP_CSR_OPA1PD
00057 #define OPAMP_Selection_OPAMP2                    OPAMP_CSR_OPA2PD
00058 #define OPAMP_Selection_OPAMP3                    OPAMP_CSR_OPA3PD
00059
00060 #define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
00061                                      ((PERIPH) == OPAMP_Selection_OPAMP2) || \
00062                                      ((PERIPH) == OPAMP_Selection_OPAMP3))
00063
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup OPAMP_Switches
00069   * @{
00070   */
00071
00072 /* OPAMP1 Switches */
00073 #define OPAMP_OPAMP1Switch3           OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */
00074 #define OPAMP_OPAMP1Switch4           OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */
00075 #define OPAMP_OPAMP1Switch5           OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */
00076 #define OPAMP_OPAMP1Switch6           OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */
00077 #define OPAMP_OPAMP1SwitchANA         OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */
00078
00079 /* OPAMP2 Switches */
00080 #define OPAMP_OPAMP2Switch3           OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */
00081 #define OPAMP_OPAMP2Switch4           OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */
00082 #define OPAMP_OPAMP2Switch5           OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */
00083 #define OPAMP_OPAMP2Switch6           OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */
00084 #define OPAMP_OPAMP2Switch7           OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */
00085 #define OPAMP_OPAMP2SwitchANA         OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */
00086
00087 /* OPAMP3 Switches */
00088 #define OPAMP_OPAMP3Switch3           OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */
00089 #define OPAMP_OPAMP3Switch4           OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */
00090 #define OPAMP_OPAMP3Switch5           OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */
00091 #define OPAMP_OPAMP3Switch6           OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */
00092 #define OPAMP_OPAMP3SwitchANA         OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */
00093
00094 #define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
00095
00096 /**
00097   * @}
00098   */
00099
00100 /** @defgroup OPAMP_Trimming
00101   * @{
00102   */
00103
00104 #define OPAMP_Trimming_Factory        ((uint32_t)0x00000000) /*!< Factory trimming */
00105 #define OPAMP_Trimming_User           OPAMP_OTR_OT_USER /*!< User trimming */
00106
00107 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
00108                                      ((TRIMMING) == OPAMP_Trimming_User))
00109
00110 /**
00111   * @}
00112   */
00113
00114 /** @defgroup OPAMP_Input
00115   * @{
00116   */
00117
00118 #define OPAMP_Input_NMOS              OPAMP_CSR_OPA1CAL_H /*!< NMOS input */
00119 #define OPAMP_Input_PMOS              OPAMP_CSR_OPA1CAL_L /*!< PMOS input */
00120
00121 #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \
00122                                ((INPUT) == OPAMP_Input_PMOS))
00123
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup OPAMP_TrimValue
00129   * @{
00130   */
00131
00132 #define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup OPAMP_PowerRange
00139   * @{
00140   */
00141
00142 #define OPAMP_PowerRange_Low          ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */
00143 #define OPAMP_PowerRange_High         OPAMP_CSR_AOP_RANGE    /*!< High power range is selected (VDDA is higher than 2.4V) */
00144
00145 #define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \
00146                                ((RANGE) == OPAMP_PowerRange_High))
00147
00148 /**
00149   * @}
00150   */
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported macro ------------------------------------------------------------*/
00156 /* Exported functions ------------------------------------------------------- */
00157 /* Initialization and Configuration functions *********************************/
00158 void OPAMP_DeInit(void);
00159 void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);
00160 void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
00161 void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
00162 void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);
00163
00164 /* Calibration functions ******************************************************/
00165 void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);
00166 void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
00167 void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
00168 FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);
00169
00170 #ifdef __cplusplus
00171 }
00172 #endif
00173
00174 #endif /*__STM32L1xx_OPAMP_H */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_pwr.c Source File

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  • src

stm32l1xx_pwr.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Power Controller (PWR) peripheral:
00009   *           + RTC Domain Access
00010   *           + PVD configuration
00011   *           + WakeUp pins configuration
00012   *           + Ultra Low Power mode configuration
00013   *           + Voltage Scaling configuration
00014   *           + Low Power modes configuration
00015   *           + Flags management
00016   *
00017   ******************************************************************************
00018   * @attention
00019   *
00020   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00021   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00022   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00023   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00024   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00025   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00026   *
00027   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00028   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00029   *
00030   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00031   ******************************************************************************
00032   */
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx_pwr.h"
00036 #include "stm32l1xx_rcc.h"
00037
00038 /** @addtogroup STM32L1xx_StdPeriph_Driver
00039   * @{
00040   */
00041
00042 /** @defgroup PWR
00043   * @brief PWR driver modules
00044   * @{
00045   */
00046
00047 /* Private typedef -----------------------------------------------------------*/
00048 /* Private define ------------------------------------------------------------*/
00049 /* --------- PWR registers bit address in the alias region ---------- */
00050 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
00051
00052 /* --- CR Register ---*/
00053
00054 /* Alias word address of DBP bit */
00055 #define CR_OFFSET                (PWR_OFFSET + 0x00)
00056 #define DBP_BitNumber            0x08
00057 #define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
00058
00059 /* Alias word address of PVDE bit */
00060 #define PVDE_BitNumber           0x04
00061 #define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
00062
00063 /* Alias word address of ULP bit */
00064 #define ULP_BitNumber           0x09
00065 #define CR_ULP_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
00066
00067 /* Alias word address of FWU bit */
00068 #define FWU_BitNumber           0x0A
00069 #define CR_FWU_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
00070
00071 /* --- CSR Register ---*/
00072
00073 /* Alias word address of EWUP bit */
00074 #define CSR_OFFSET               (PWR_OFFSET + 0x04)
00075 #define EWUP_BitNumber           0x08
00076 #define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
00077
00078 /* ------------------ PWR registers bit mask ------------------------ */
00079
00080 /* CR register bit mask */
00081 #define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
00082 #define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
00083 #define CR_VOS_MASK              ((uint32_t)0xFFFFE7FF)
00084
00085 /* Private macro -------------------------------------------------------------*/
00086 /* Private variables ---------------------------------------------------------*/
00087 /* Private function prototypes -----------------------------------------------*/
00088 /* Private functions ---------------------------------------------------------*/
00089
00090 /** @defgroup PWR_Private_Functions
00091   * @{
00092   */
00093
00094 /** @defgroup PWR_Group1 RTC Domain Access function
00095  *  @brief   RTC Domain Access function
00096  *
00097 @verbatim
00098   ==============================================================================
00099                      ##### RTC Domain Access function #####
00100   ==============================================================================
00101
00102     [..] After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup
00103          registers) are protected against possible stray write accesses.
00104     [..] To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.
00105
00106 @endverbatim
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
00112   * @note   Before calling this function, the VOS[1:0] bits should be configured
00113   *         to "10" and the system frequency has to be configured accordingly.
00114   *         To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
00115   *         function.
00116   * @note   ULP and FWU bits are not reset by this function.
00117   * @param  None
00118   * @retval None
00119   */
00120 void PWR_DeInit(void)
00121 {
00122   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
00123   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00124 }
00125
00126 /**
00127   * @brief  Enables or disables access to the RTC and backup registers.
00128   * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
00129   *         RTC Domain Access should be kept enabled.
00130   * @param  NewState: new state of the access to the RTC and backup registers.
00131   *   This parameter can be: ENABLE or DISABLE.
00132   * @retval None
00133   */
00134 void PWR_RTCAccessCmd(FunctionalState NewState)
00135 {
00136   /* Check the parameters */
00137   assert_param(IS_FUNCTIONAL_STATE(NewState));
00138
00139   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
00140 }
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup PWR_Group2 PVD configuration functions
00147  *  @brief   PVD configuration functions
00148  *
00149 @verbatim
00150   ==============================================================================
00151                     ##### PVD configuration functions #####
00152   ==============================================================================
00153   [..]
00154   (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
00155       selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
00156   (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
00157       internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
00158       when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
00159   (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
00160       PVD threshold. This event is internally connected to the EXTI line16
00161       and can generate an interrupt if enabled through the EXTI registers.
00162   (+) The PVD is stopped in Standby mode.
00163
00164 @endverbatim
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00170   * @param  PWR_PVDLevel: specifies the PVD detection level.
00171   *   This parameter can be one of the following values:
00172   *     @arg PWR_PVDLevel_0: PVD detection level set to 1.9V.
00173   *     @arg PWR_PVDLevel_1: PVD detection level set to 2.1V.
00174   *     @arg PWR_PVDLevel_2: PVD detection level set to 2.3V.
00175   *     @arg PWR_PVDLevel_3: PVD detection level set to 2.5V.
00176   *     @arg PWR_PVDLevel_4: PVD detection level set to 2.7V.
00177   *     @arg PWR_PVDLevel_5: PVD detection level set to 2.9V.
00178   *     @arg PWR_PVDLevel_6: PVD detection level set to 3.1V.
00179   *     @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).
00180   * @retval None
00181   */
00182 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
00183 {
00184   uint32_t tmpreg = 0;
00185
00186   /* Check the parameters */
00187   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
00188
00189   tmpreg = PWR->CR;
00190
00191   /* Clear PLS[7:5] bits */
00192   tmpreg &= CR_PLS_MASK;
00193
00194   /* Set PLS[7:5] bits according to PWR_PVDLevel value */
00195   tmpreg |= PWR_PVDLevel;
00196
00197   /* Store the new value */
00198   PWR->CR = tmpreg;
00199 }
00200
00201 /**
00202   * @brief  Enables or disables the Power Voltage Detector(PVD).
00203   * @param  NewState: new state of the PVD.
00204   *   This parameter can be: ENABLE or DISABLE.
00205   * @retval None
00206   */
00207 void PWR_PVDCmd(FunctionalState NewState)
00208 {
00209   /* Check the parameters */
00210   assert_param(IS_FUNCTIONAL_STATE(NewState));
00211
00212   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
00213 }
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup PWR_Group3 WakeUp pins configuration functions
00220  *  @brief   WakeUp pins configuration functions
00221  *
00222 @verbatim
00223   ==============================================================================
00224                ##### WakeUp pin configuration functions #####
00225   ==============================================================================
00226
00227   (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
00228       forced in input pull down configuration and are active on rising edges.
00229   (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
00230       WakeUp Pin 3 on PE.06.
00231
00232 @endverbatim
00233   * @{
00234   */
00235
00236 /**
00237   * @brief  Enables or disables the WakeUp Pin functionality.
00238   * @param  PWR_WakeUpPin: specifies the WakeUpPin.
00239   *   This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
00240   * @param  NewState: new state of the WakeUp Pin functionality.
00241   *   This parameter can be: ENABLE or DISABLE.
00242   * @retval None
00243   */
00244 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
00245 {
00246   __IO uint32_t tmp = 0;
00247
00248   /* Check the parameters */
00249   assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
00250
00251   assert_param(IS_FUNCTIONAL_STATE(NewState));
00252
00253   tmp = CSR_EWUP_BB + PWR_WakeUpPin;
00254
00255   *(__IO uint32_t *) (tmp) = (uint32_t)NewState;
00256 }
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup PWR_Group4 Ultra Low Power mode configuration functions
00263  *  @brief   Ultra Low Power mode configuration functions
00264  *
00265 @verbatim
00266   ==============================================================================
00267              ##### Ultra Low Power mode configuration functions #####
00268   ==============================================================================
00269   [..]
00270   (+) The internal voltage reference consumption is not negligible, in particular
00271       in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()
00272       function (ULP bit (Ultra low power) in the PWR_CR register) to disable the
00273       internal voltage reference. However, in this case, when exiting from the
00274       Stop/Standby mode, the functions managed through the internal voltage reference
00275       are not reliable during the internal voltage reference startup time (up to 3 ms).
00276       To reduce the wakeup time, the device can exit from Stop/Standby mode without
00277       waiting for the internal voltage reference startup time. This is performed
00278       by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
00279       wakeup) in the PWR_CR register) before entering Stop/Standby mode.
00280
00281 @endverbatim
00282   * @{
00283   */
00284
00285 /**
00286   * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.
00287   * @param  NewState: new state of the Fast WakeUp  functionality.
00288   *   This parameter can be: ENABLE or DISABLE.
00289   * @retval None
00290   */
00291 void PWR_FastWakeUpCmd(FunctionalState NewState)
00292 {
00293   /* Check the parameters */
00294   assert_param(IS_FUNCTIONAL_STATE(NewState));
00295
00296   *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
00297 }
00298
00299 /**
00300   * @brief  Enables or disables the Ultra Low Power mode.
00301   * @param  NewState: new state of the Ultra Low Power mode.
00302   *   This parameter can be: ENABLE or DISABLE.
00303   * @retval None
00304   */
00305 void PWR_UltraLowPowerCmd(FunctionalState NewState)
00306 {
00307   /* Check the parameters */
00308   assert_param(IS_FUNCTIONAL_STATE(NewState));
00309
00310   *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
00311 }
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup PWR_Group5 Voltage Scaling configuration functions
00318  *  @brief   Voltage Scaling configuration functions
00319  *
00320 @verbatim
00321   ==============================================================================
00322               ##### Voltage Scaling configuration functions #####
00323   ==============================================================================
00324
00325     (+) The dynamic voltage scaling is a power management technique which consists in
00326         increasing or decreasing the voltage used for the digital peripherals (VCORE),
00327         according to the circumstances.
00328
00329    [..] Depending on the device voltage range, the maximum frequency and FLASH wait
00330         state should be adapted accordingly:
00331    [..]
00332         +------------------------------------------------------------------+
00333         |   Wait states   |                HCLK clock frequency (MHz)      |
00334         |                 |------------------------------------------------|
00335         |    (Latency)    |            voltage range       | voltage range |
00336         |                 |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
00337         |                 |----------------|---------------|---------------|
00338         |                 |     Range 3    |    Range 2    |    Range 1    |
00339         |                 |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
00340         |---------------- |----------------|---------------|---------------|
00341         | 0WS(1CPU cycle) |0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
00342         |-----------------|----------------|---------------|---------------|
00343         | 1WS(2CPU cycle) |2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
00344         |-----------------|----------------|---------------|---------------|
00345         | CPU Performance |      Low       |     Medium    |     High      |
00346         |-----__----------|----------------|---------------|---------------|
00347         |Power Performance|      High      |     Medium    |      Low      |
00348         +------------------------------------------------------------------+
00349
00350     (+) To modify the Product voltage range, user application has to:
00351         (++) Check VDD to identify which ranges are allowed (see table above).
00352         (++) Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus()
00353              function and wait until it is  reset.
00354         (++) Configure the Voltage range using the PWR_VoltageScalingConfig() function.
00355
00356     (+) When VCORE range 1 is selected and VDD drops below 2.0 V, the application must
00357         reconfigure the system:
00358         (++) Detect that VDD drops below 2.0 V using the PVD Level 1.
00359         (++) Adapt the clock frequency to the voltage range that will be selected at next step.
00360         (++) Select the required voltage range.
00361         (++) When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system
00362              reconfiguration is required.
00363
00364     (+) When VDD is above 2.0 V, any of the 3 voltage ranges can be selected.
00365         (++) When the voltage range is above the targeted voltage range (e.g. from range
00366              1 to 2).
00367         (++) Adapt the clock frequency to the lower voltage range that will be selected
00368              at next step.
00369         (++) Select the required voltage range.
00370         (++) When the voltage range is below the targeted voltage range (e.g. from range
00371              3 to 1).
00372         (++) Select the required voltage range.
00373         (++) Tune the clock frequency if needed.
00374
00375     (+) When VDD is below 2.0 V, only range 2 and 3 can be selected:
00376         (++) From range 2 to range 3.
00377              (+++) Adapt the clock frequency to voltage range 3.
00378              (+++) Select voltage range 3.
00379         (++) From range 3 to range 2.
00380              (+++) Select the voltage range 2.
00381              (+++) Tune the clock frequency if needed.
00382
00383 @endverbatim
00384   * @{
00385   */
00386
00387 /**
00388   * @brief  Configures the voltage scaling range.
00389   * @note   During voltage scaling configuration, the system clock is stopped
00390   *         until the regulator is stabilized (VOSF = 0). This must be taken
00391   *         into account during application developement, in case a critical
00392   *         reaction time to interrupt is needed, and depending on peripheral
00393   *         used (timer, communication,...).
00394   *
00395   * @param  PWR_VoltageScaling: specifies the voltage scaling range.
00396   *   This parameter can be:
00397   *     @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).
00398   *     @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).
00399   *     @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V)
00400   * @retval None
00401   */
00402 void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
00403 {
00404   uint32_t tmp = 0;
00405
00406   /* Check the parameters */
00407   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
00408
00409   tmp = PWR->CR;
00410
00411   tmp &= CR_VOS_MASK;
00412   tmp |= PWR_VoltageScaling;
00413
00414   PWR->CR = tmp & 0xFFFFFFF3;
00415
00416 }
00417
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup PWR_Group6 Low Power modes configuration functions
00423  *  @brief   Low Power modes configuration functions
00424  *
00425 @verbatim
00426   ==============================================================================
00427               ##### Low Power modes configuration functions #####
00428   ==============================================================================
00429
00430     [..] The devices feature five low-power modes:
00431     (+) Low power run mode: regulator in low power mode, limited clock frequency,
00432         limited number of peripherals running.
00433     (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
00434     (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
00435         limited number of peripherals running, regulator in low power mode.
00436     (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode.
00437     (+) Standby mode: VCORE domain powered off.
00438
00439   *** Low power run mode (LP run) ***
00440   ===================================
00441       [..]
00442     (+) Entry:
00443         (++) Decrease the system frequency.
00444         (++) The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()
00445              function.
00446     (+) Exit:
00447         (++) The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()
00448              function.
00449         (++) Increase the system frequency if needed.
00450
00451   *** Sleep mode ***
00452   ==================
00453   [..]
00454     (+) Entry:
00455         (++) The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,)
00456              function with regulator ON.
00457     (+) Exit:
00458         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00459              controller (NVIC) can wake up the device from Sleep mode.
00460
00461   *** Low power sleep mode (LP sleep) ***
00462   =======================================
00463   [..]
00464     (+) Entry:
00465         (++) The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()
00466              function.
00467         (++) Decrease the system frequency.
00468         (++) The regulator is forced in low power mode and the WFI or WFE instructions
00469              are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function
00470              with regulator in LowPower.
00471     (+) Exit:
00472         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00473              controller (NVIC) can wake up the device from Sleep LP mode.
00474
00475   *** Stop mode ***
00476   =================
00477   [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
00478        the HSI and the HSE RC oscillators are disabled. Internal SRAM and register
00479        contents are preserved.
00480        The voltage regulator can be configured either in normal or low-power mode.
00481        To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
00482        sensor can be switched off before entering the Stop mode. They can be switched
00483        on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()
00484        function.
00485
00486     (+) Entry:
00487         (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
00488              function with regulator in LowPower or with Regulator ON.
00489     (+) Exit:
00490         (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00491
00492   *** Standby mode ***
00493   ====================
00494   [..] The Standby mode allows to achieve the lowest power consumption. It is based
00495        on the Cortex-M3 deepsleep mode, with the voltage regulator disabled.
00496        The VCORE domain is consequently powered off. The PLL, the MSI, the HSI
00497        oscillator and the HSE oscillator are also switched off. SRAM and register
00498        contents are lost except for the RTC registers, RTC backup registers and
00499        Standby circuitry.
00500
00501   [..] The voltage regulator is OFF.
00502
00503   [..] To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
00504        sensor can be switched off before entering the Standby mode. They can be switched
00505        on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()
00506        function.
00507
00508     (+) Entry:
00509         (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
00510     (+) Exit:
00511         (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
00512             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
00513
00514   *** Auto-wakeup (AWU) from low-power mode ***
00515   =============================================
00516   [..]The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00517       Wakeup event, a tamper event, a time-stamp event, or a comparator event,
00518       without depending on an external interrupt (Auto-wakeup mode).
00519
00520     (+) RTC auto-wakeup (AWU) from the Stop mode
00521         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
00522              (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
00523                    or Event modes) using the EXTI_Init() function.
00524              (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
00525              (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
00526                    and RTC_AlarmCmd() functions.
00527         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00528              is necessary to:
00529              (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
00530                    or Event modes) using the EXTI_Init() function.
00531              (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
00532                    function.
00533              (+++) Configure the RTC to detect the tamper or time stamp event using the
00534                    RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
00535                    functions.
00536         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
00537              (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
00538                    or Event modes) using the EXTI_Init() function.
00539              (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
00540              (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
00541                    RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
00542
00543     (+) RTC auto-wakeup (AWU) from the Standby mode
00544         (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
00545              (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
00546              (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
00547                    and RTC_AlarmCmd() functions.
00548         (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
00549              is necessary to:
00550              (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
00551                    function.
00552              (+++) Configure the RTC to detect the tamper or time stamp event using the
00553                    RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
00554                    functions.
00555         (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
00556              (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
00557              (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
00558                    RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
00559
00560     (+) Comparator auto-wakeup (AWU) from the Stop mode
00561         (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
00562              event, it is necessary to:
00563              (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
00564                    to be sensitive to to the selected edges (falling, rising or falling
00565                    and rising) (Interrupt or Event modes) using the EXTI_Init() function.
00566              (+++) Configure the comparator to generate the event.
00567
00568 @endverbatim
00569   * @{
00570   */
00571
00572 /**
00573   * @brief  Enters/Exits the Low Power Run mode.
00574   * @note   Low power run mode can only be entered when VCORE is in range 2.
00575   *         In addition, the dynamic voltage scaling must not be used when Low
00576   *         power run mode is selected. Only Stop and Sleep modes with regulator
00577   *         configured in Low power mode is allowed when Low power run mode is
00578   *         selected.
00579   * @note   In Low power run mode, all I/O pins keep the same state as in Run mode.
00580   * @param  NewState: new state of the Low Power Run mode.
00581   *   This parameter can be: ENABLE or DISABLE.
00582   * @retval None
00583   */
00584 void PWR_EnterLowPowerRunMode(FunctionalState NewState)
00585 {
00586   /* Check the parameters */
00587   assert_param(IS_FUNCTIONAL_STATE(NewState));
00588
00589   if (NewState != DISABLE)
00590   {
00591     PWR->CR |= PWR_CR_LPSDSR;
00592     PWR->CR |= PWR_CR_LPRUN;
00593   }
00594   else
00595   {
00596     PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
00597     PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
00598   }
00599 }
00600
00601 /**
00602   * @brief  Enters Sleep mode.
00603   * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
00604   * @param  PWR_Regulator: specifies the regulator state in Sleep mode.
00605   *   This parameter can be one of the following values:
00606   *     @arg PWR_Regulator_ON: Sleep mode with regulator ON
00607   *     @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
00608   * @note   Low power sleep mode can only be entered when VCORE is in range 2.
00609   * @note   When the voltage regulator operates in low power mode, an additional
00610   *         startup delay is incurred when waking up from Low power sleep mode.
00611   * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
00612   *   This parameter can be one of the following values:
00613   *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
00614   *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
00615   * @retval None
00616   */
00617 void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
00618 {
00619   uint32_t tmpreg = 0;
00620
00621   /* Check the parameters */
00622   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
00623
00624   assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
00625
00626   /* Select the regulator state in Sleep mode ---------------------------------*/
00627   tmpreg = PWR->CR;
00628
00629   /* Clear PDDS and LPDSR bits */
00630   tmpreg &= CR_DS_MASK;
00631
00632   /* Set LPDSR bit according to PWR_Regulator value */
00633   tmpreg |= PWR_Regulator;
00634
00635   /* Store the new value */
00636   PWR->CR = tmpreg;
00637
00638   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00639   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
00640
00641   /* Select SLEEP mode entry -------------------------------------------------*/
00642   if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
00643   {
00644     /* Request Wait For Interrupt */
00645     __WFI();
00646   }
00647   else
00648   {
00649     /* Request Wait For Event */
00650     __WFE();
00651   }
00652 }
00653
00654 /**
00655   * @brief  Enters STOP mode.
00656   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
00657   * @note   When exiting Stop mode by issuing an interrupt or a wakeup event,
00658   *         the MSI RC oscillator is selected as system clock.
00659   * @note   When the voltage regulator operates in low power mode, an additional
00660   *         startup delay is incurred when waking up from Stop mode.
00661   *         By keeping the internal regulator ON during Stop mode, the consumption
00662   *         is higher although the startup time is reduced.
00663   * @param  PWR_Regulator: specifies the regulator state in STOP mode.
00664   *   This parameter can be one of the following values:
00665   *     @arg PWR_Regulator_ON: STOP mode with regulator ON.
00666   *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
00667   * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
00668   *   This parameter can be one of the following values:
00669   *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.
00670   *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.
00671   * @retval None
00672   */
00673 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
00674 {
00675   uint32_t tmpreg = 0;
00676
00677   /* Check the parameters */
00678   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
00679   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
00680
00681   /* Select the regulator state in STOP mode ---------------------------------*/
00682   tmpreg = PWR->CR;
00683   /* Clear PDDS and LPDSR bits */
00684   tmpreg &= CR_DS_MASK;
00685
00686   /* Set LPDSR bit according to PWR_Regulator value */
00687   tmpreg |= PWR_Regulator;
00688
00689   /* Store the new value */
00690   PWR->CR = tmpreg;
00691
00692   /* Set SLEEPDEEP bit of Cortex System Control Register */
00693   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00694
00695   /* Select STOP mode entry --------------------------------------------------*/
00696   if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00697   {
00698     /* Request Wait For Interrupt */
00699     __WFI();
00700   }
00701   else
00702   {
00703     /* Request Wait For Event */
00704     __WFE();
00705   }
00706   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00707   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
00708 }
00709
00710 /**
00711   * @brief  Enters STANDBY mode.
00712   * @note   In Standby mode, all I/O pins are high impedance except for:
00713   *         Reset pad (still available)
00714   *         RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
00715   *         time-stamp, RTC Alarm out, or RTC clock calibration out.
00716   *         WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
00717   * @param  None
00718   * @retval None
00719   */
00720 void PWR_EnterSTANDBYMode(void)
00721 {
00722   /* Clear Wakeup flag */
00723   PWR->CR |= PWR_CR_CWUF;
00724
00725   /* Select STANDBY mode */
00726   PWR->CR |= PWR_CR_PDDS;
00727
00728   /* Set SLEEPDEEP bit of Cortex System Control Register */
00729   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00730
00731 /* This option is used to ensure that store operations are completed */
00732 #if defined ( __CC_ARM   )
00733   __force_stores();
00734 #endif
00735   /* Request Wait For Interrupt */
00736   __WFI();
00737 }
00738
00739 /**
00740   * @}
00741   */
00742
00743 /** @defgroup PWR_Group7 Flags management functions
00744  *  @brief   Flags management functions
00745  *
00746 @verbatim
00747   ==============================================================================
00748                        ##### Flags management functions #####
00749   ==============================================================================
00750
00751 @endverbatim
00752   * @{
00753   */
00754
00755 /**
00756   * @brief  Checks whether the specified PWR flag is set or not.
00757   * @param  PWR_FLAG: specifies the flag to check.
00758   *   This parameter can be one of the following values:
00759   *     @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
00760   *       was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
00761   *       RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
00762   *     @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
00763   *                       resumed from StandBy mode.
00764   *     @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00765   *       by the PWR_PVDCmd() function.
00766   *     @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
00767   *       flag indicates the state of the internal voltage reference, VREFINT.
00768   *     @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
00769   *       the internal regulator to be ready after the voltage range is changed.
00770   *       The VOSF flag indicates that the regulator has reached the voltage level
00771   *       defined with bits VOS[1:0] of PWR_CR register.
00772   *     @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware
00773   *       when the MCU is in Low power run mode.
00774   *       When the MCU exits from Low power run mode, this flag stays SET until
00775   *       the regulator is ready in main mode. A polling on this flag is
00776   *       recommended to wait for the regulator main mode.
00777   *       This flag is RESET by hardware when the regulator is ready.
00778   * @retval The new state of PWR_FLAG (SET or RESET).
00779   */
00780 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
00781 {
00782   FlagStatus bitstatus = RESET;
00783   /* Check the parameters */
00784   assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
00785
00786   if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
00787   {
00788     bitstatus = SET;
00789   }
00790   else
00791   {
00792     bitstatus = RESET;
00793   }
00794   /* Return the flag status */
00795   return bitstatus;
00796 }
00797
00798 /**
00799   * @brief  Clears the PWR's pending flags.
00800   * @param  PWR_FLAG: specifies the flag to clear.
00801   *   This parameter can be one of the following values:
00802   *     @arg PWR_FLAG_WU: Wake Up flag
00803   *     @arg PWR_FLAG_SB: StandBy flag
00804   * @retval None
00805   */
00806 void PWR_ClearFlag(uint32_t PWR_FLAG)
00807 {
00808   /* Check the parameters */
00809   assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
00810
00811   PWR->CR |=  PWR_FLAG << 2;
00812 }
00813
00814 /**
00815   * @}
00816   */
00817
00818 /**
00819   * @}
00820   */
00821
00822 /**
00823   * @}
00824   */
00825
00826 /**
00827   * @}
00828   */
00829
00830 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_pwr.h Source File

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stm32l1xx_pwr.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the PWR firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_PWR_H
00028 #define __STM32L1xx_PWR_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup PWR
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup PWR_Exported_Constants
00049   * @{
00050   */
00051
00052 /** @defgroup PWR_PVD_detection_level
00053   * @{
00054   */
00055
00056 #define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
00057 #define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
00058 #define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
00059 #define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
00060 #define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
00061 #define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
00062 #define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
00063 #define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7 /* External input analog voltage
00064                                                           (Compare internally to VREFINT) */
00065 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
00066                                  ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
00067                                  ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
00068                                  ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup PWR_WakeUp_Pins
00074   * @{
00075   */
00076
00077 #define PWR_WakeUpPin_1                 ((uint32_t)0x00000000)
00078 #define PWR_WakeUpPin_2                 ((uint32_t)0x00000004)
00079 #define PWR_WakeUpPin_3                 ((uint32_t)0x00000008)
00080 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
00081                                 ((PIN) == PWR_WakeUpPin_2) || \
00082                                 ((PIN) == PWR_WakeUpPin_3))
00083 /**
00084   * @}
00085   */
00086
00087
00088 /** @defgroup PWR_Voltage_Scaling_Ranges
00089   * @{
00090   */
00091
00092 #define PWR_VoltageScaling_Range1       PWR_CR_VOS_0
00093 #define PWR_VoltageScaling_Range2       PWR_CR_VOS_1
00094 #define PWR_VoltageScaling_Range3       PWR_CR_VOS
00095
00096 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
00097                                              ((RANGE) == PWR_VoltageScaling_Range2) || \
00098                                              ((RANGE) == PWR_VoltageScaling_Range3))
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
00104   * @{
00105   */
00106
00107 #define PWR_Regulator_ON                ((uint32_t)0x00000000)
00108 #define PWR_Regulator_LowPower          PWR_CR_LPSDSR
00109 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
00110                                      ((REGULATOR) == PWR_Regulator_LowPower))
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup PWR_SLEEP_mode_entry
00116   * @{
00117   */
00118
00119 #define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
00120 #define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
00121 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
00122
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup PWR_STOP_mode_entry
00128   * @{
00129   */
00130
00131 #define PWR_STOPEntry_WFI               ((uint8_t)0x01)
00132 #define PWR_STOPEntry_WFE               ((uint8_t)0x02)
00133 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup PWR_Flag
00140   * @{
00141   */
00142
00143 #define PWR_FLAG_WU                     PWR_CSR_WUF
00144 #define PWR_FLAG_SB                     PWR_CSR_SBF
00145 #define PWR_FLAG_PVDO                   PWR_CSR_PVDO
00146 #define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF
00147 #define PWR_FLAG_VOS                    PWR_CSR_VOSF
00148 #define PWR_FLAG_REGLP                  PWR_CSR_REGLPF
00149
00150 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
00151                                ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
00152                                ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
00153
00154 #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported macro ------------------------------------------------------------*/
00164 /* Exported functions ------------------------------------------------------- */
00165
00166 /* Function used to set the PWR configuration to the default reset state ******/
00167 void PWR_DeInit(void);
00168
00169 /* RTC Domain Access function *************************************************/
00170 void PWR_RTCAccessCmd(FunctionalState NewState);
00171
00172 /* PVD configuration functions ************************************************/
00173 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
00174 void PWR_PVDCmd(FunctionalState NewState);
00175
00176 /* WakeUp pins configuration functions ****************************************/
00177 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
00178
00179 /* Ultra Low Power mode configuration functions *******************************/
00180 void PWR_FastWakeUpCmd(FunctionalState NewState);
00181 void PWR_UltraLowPowerCmd(FunctionalState NewState);
00182
00183 /* Voltage Scaling configuration functions ************************************/
00184 void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
00185
00186 /* Low Power modes configuration functions ************************************/
00187 void PWR_EnterLowPowerRunMode(FunctionalState NewState);
00188 void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
00189 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
00190 void PWR_EnterSTANDBYMode(void);
00191
00192 /* Flags management functions *************************************************/
00193 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
00194 void PWR_ClearFlag(uint32_t PWR_FLAG);
00195
00196 #ifdef __cplusplus
00197 }
00198 #endif
00199
00200 #endif /* __STM32L1xx_PWR_H */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rcc.c Source File

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stm32l1xx_rcc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Reset and clock control (RCC) peripheral:
00009   *           + Internal/external clocks, PLL, CSS and MCO configuration
00010   *           + System, AHB and APB busses clocks configuration
00011   *           + Peripheral clocks configuration
00012   *           + Interrupts and flags management
00013   *
00014  @verbatim
00015
00016  ===============================================================================
00017                         ##### RCC specific features #####
00018  ===============================================================================
00019     [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
00020          all peripherals are off except internal SRAM, Flash and JTAG.
00021          (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
00022              all peripherals mapped on these busses are running at MSI speed.
00023          (#) The clock for all peripherals is switched off, except the SRAM and
00024              FLASH.
00025          (#) All GPIOs are in input floating state, except the JTAG pins which
00026              are assigned to be used for debug purpose.
00027     [..] Once the device started from reset, the user application has to:
00028          (#) Configure the clock source to be used to drive the System clock
00029              (if the application needs higher frequency/performance)
00030          (#) Configure the System clock frequency and Flash settings
00031          (#) Configure the AHB and APB busses prescalers
00032          (#) Enable the clock for the peripheral(s) to be used
00033          (#) Configure the clock source(s) for peripherals whose clocks are not
00034              derived from the System clock (ADC, RTC/LCD and IWDG)
00035
00036  @endverbatim
00037
00038   ******************************************************************************
00039   * @attention
00040   *
00041   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00042   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00043   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00044   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00045   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00046   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00047   *
00048   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00049   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00050   *
00051   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00052   ******************************************************************************
00053   */
00054
00055 /* Includes ------------------------------------------------------------------*/
00056 #include "stm32l1xx_rcc.h"
00057
00058 /** @addtogroup STM32L1xx_StdPeriph_Driver
00059   * @{
00060   */
00061
00062 /** @defgroup RCC
00063   * @brief RCC driver modules
00064   * @{
00065   */
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069
00070 /* ------------ RCC registers bit address in the alias region ----------- */
00071 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00072
00073 /* --- CR Register ---*/
00074
00075 /* Alias word address of HSION bit */
00076 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
00077 #define HSION_BitNumber           0x00
00078 #define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
00079
00080 /* Alias word address of MSION bit */
00081 #define MSION_BitNumber           0x08
00082 #define CR_MSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
00083
00084 /* Alias word address of PLLON bit */
00085 #define PLLON_BitNumber           0x18
00086 #define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
00087
00088 /* Alias word address of CSSON bit */
00089 #define CSSON_BitNumber           0x1C
00090 #define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
00091
00092 /* --- CSR Register ---*/
00093
00094 /* Alias word address of LSION bit */
00095 #define CSR_OFFSET                (RCC_OFFSET + 0x34)
00096 #define LSION_BitNumber           0x00
00097 #define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
00098
00099 /* Alias word address of LSECSSON bit */
00100 #define LSECSSON_BitNumber        0x0B
00101 #define CSR_LSECSSON_BB          (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSECSSON_BitNumber * 4))
00102
00103 /* Alias word address of RTCEN bit */
00104 #define RTCEN_BitNumber           0x16
00105 #define CSR_RTCEN_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
00106
00107 /* Alias word address of RTCRST bit */
00108 #define RTCRST_BitNumber          0x17
00109 #define CSR_RTCRST_BB             (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
00110
00111
00112 /* ---------------------- RCC registers mask -------------------------------- */
00113 /* RCC Flag Mask */
00114 #define FLAG_MASK                 ((uint8_t)0x1F)
00115
00116 /* CR register byte 3 (Bits[23:16]) base address */
00117 #define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)
00118
00119 /* ICSCR register byte 4 (Bits[31:24]) base address */
00120 #define ICSCR_BYTE4_ADDRESS       ((uint32_t)0x40023807)
00121
00122 /* CFGR register byte 3 (Bits[23:16]) base address */
00123 #define CFGR_BYTE3_ADDRESS        ((uint32_t)0x4002380A)
00124
00125 /* CFGR register byte 4 (Bits[31:24]) base address */
00126 #define CFGR_BYTE4_ADDRESS        ((uint32_t)0x4002380B)
00127
00128 /* CIR register byte 2 (Bits[15:8]) base address */
00129 #define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002380D)
00130
00131 /* CIR register byte 3 (Bits[23:16]) base address */
00132 #define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002380E)
00133
00134 /* CSR register byte 2 (Bits[15:8]) base address */
00135 #define CSR_BYTE2_ADDRESS         ((uint32_t)0x40023835)
00136
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139
00140 static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
00141 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00142
00143 /* Private function prototypes -----------------------------------------------*/
00144 /* Private functions ---------------------------------------------------------*/
00145
00146 /** @defgroup RCC_Private_Functions
00147   * @{
00148   */
00149
00150 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
00151  *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions
00152  *
00153 @verbatim
00154  ===============================================================================
00155  ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
00156  ===============================================================================
00157     [..] This section provide functions allowing to configure the internal/external
00158          clocks, PLL, CSS and MCO.
00159          (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
00160              or through the PLL as System clock source.
00161          (#) MSI (multi-speed internal), multispeed low power RC
00162              (65.536 KHz to 4.194 MHz) MHz used as System clock source.
00163          (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
00164              and/or RTC clock source.
00165          (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
00166              directly or through the PLL as System clock source. Can be used
00167              also as RTC clock source.
00168          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00169          (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
00170          (#) CSS (Clock security system), once enable and if a HSE clock failure
00171              occurs (HSE used directly or through PLL as System clock source),
00172              the System clock is automatically switched to MSI and an interrupt
00173              is generated if enabled.
00174              The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
00175              exception vector.
00176          (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
00177              HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
00178              PA8 pin.
00179
00180 @endverbatim
00181   * @{
00182   */
00183
00184 /**
00185   * @brief  Resets the RCC clock configuration to the default reset state.
00186   * @note   The default reset state of the clock configuration is given below:
00187   * @note      MSI ON and used as system clock source (MSI range is not modified
00188   *            by this function, it keep the value configured by user application)
00189   * @note      HSI, HSE and PLL OFF
00190   * @note      AHB, APB1 and APB2 prescaler set to 1.
00191   * @note      CSS and MCO OFF
00192   * @note      All interrupts disabled
00193   * @note    However, this function doesn't modify the configuration of the
00194   * @note      Peripheral clocks
00195   * @note      LSI, LSE and RTC clocks
00196   * @param  None
00197   * @retval None
00198   */
00199 void RCC_DeInit(void)
00200 {
00201
00202   /* Set MSION bit */
00203   RCC->CR |= (uint32_t)0x00000100;
00204
00205   /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
00206   RCC->CFGR &= (uint32_t)0x88FFC00C;
00207
00208   /* Reset HSION, HSEON, CSSON and PLLON bits */
00209   RCC->CR &= (uint32_t)0xEEFEFFFE;
00210
00211   /* Reset HSEBYP bit */
00212   RCC->CR &= (uint32_t)0xFFFBFFFF;
00213
00214   /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
00215   RCC->CFGR &= (uint32_t)0xFF02FFFF;
00216
00217   /* Disable all interrupts */
00218   RCC->CIR = 0x00000000;
00219 }
00220
00221 /**
00222   * @brief  Configures the External High Speed oscillator (HSE).
00223   * @note    After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
00224   *           software should wait on HSERDY flag to be set indicating that HSE clock
00225   *           is stable and can be used to clock the PLL and/or system clock.
00226   *  @note    HSE state can not be changed if it is used directly or through the
00227   *           PLL as system clock. In this case, you have to select another source
00228   *           of the system clock then change the HSE state (ex. disable it).
00229   *  @note    The HSE is stopped by hardware when entering STOP and STANDBY modes.
00230   * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
00231   *         was previously enabled you have to enable it again after calling this
00232   *         function.
00233   * @param RCC_HSE: specifies the new state of the HSE.
00234   *   This parameter can be one of the following values:
00235   *     @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
00236   *                       6 HSE oscillator clock cycles.
00237   *     @arg RCC_HSE_ON: turn ON the HSE oscillator
00238   *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
00239   * @retval None
00240   */
00241 void RCC_HSEConfig(uint8_t RCC_HSE)
00242 {
00243   /* Check the parameters */
00244   assert_param(IS_RCC_HSE(RCC_HSE));
00245
00246   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
00247   *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
00248
00249   /* Set the new HSE configuration -------------------------------------------*/
00250   *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
00251
00252 }
00253
00254 /**
00255   * @brief  Waits for HSE start-up.
00256   * @note   This functions waits on HSERDY flag to be set and return SUCCESS if
00257   *         this flag is set, otherwise returns ERROR if the timeout is reached
00258   *         and this flag is not set. The timeout value is defined by the constant
00259   *         HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending
00260   *         on the HSE crystal used in your application.
00261   * @param  None
00262   * @retval An ErrorStatus enumeration value:
00263   *          - SUCCESS: HSE oscillator is stable and ready to use
00264   *          - ERROR: HSE oscillator not yet ready
00265   */
00266 ErrorStatus RCC_WaitForHSEStartUp(void)
00267 {
00268   __IO uint32_t StartUpCounter = 0;
00269   ErrorStatus status = ERROR;
00270   FlagStatus HSEStatus = RESET;
00271
00272   /* Wait till HSE is ready and if timeout is reached exit */
00273   do
00274   {
00275     HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00276     StartUpCounter++;
00277   } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
00278
00279   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00280   {
00281     status = SUCCESS;
00282   }
00283   else
00284   {
00285     status = ERROR;
00286   }
00287   return (status);
00288 }
00289
00290 /**
00291   * @brief  Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
00292   * @note   The calibration is used to compensate for the variations in voltage
00293   *         and temperature that influence the frequency of the internal MSI RC.
00294   *         Refer to the Application Note AN3300 for more details on how to
00295   *         calibrate the MSI.
00296   * @param  MSICalibrationValue: specifies the MSI calibration trimming value.
00297   *   This parameter must be a number between 0 and 0xFF.
00298   * @retval None
00299   */
00300 void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
00301 {
00302
00303   /* Check the parameters */
00304   assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
00305
00306   *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
00307 }
00308
00309 /**
00310   * @brief  Configures the Internal Multi Speed oscillator (MSI) clock range.
00311   * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
00312   *           around 2.097 MHz. The MSI clock does not change after wake-up from
00313   *           STOP mode.
00314   *  @note    The MSI clock range can be modified on the fly.
00315   * @param  RCC_MSIRange: specifies the MSI Clock range.
00316   *   This parameter must be one of the following values:
00317   *     @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz
00318   *     @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz
00319   *     @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz
00320   *     @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz
00321   *     @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz
00322   *     @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
00323   *     @arg RCC_MSIRange_6: MSI clock is around 4.194 MHz
00324   *
00325   * @retval None
00326   */
00327 void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
00328 {
00329   uint32_t tmpreg = 0;
00330
00331   /* Check the parameters */
00332   assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
00333
00334   tmpreg = RCC->ICSCR;
00335
00336   /* Clear MSIRANGE[2:0] bits */
00337   tmpreg &= ~RCC_ICSCR_MSIRANGE;
00338
00339   /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
00340   tmpreg |= (uint32_t)RCC_MSIRange;
00341
00342   /* Store the new value */
00343   RCC->ICSCR = tmpreg;
00344 }
00345
00346 /**
00347   * @brief  Enables or disables the Internal Multi Speed oscillator (MSI).
00348   * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
00349   *           It is used (enabled by hardware) as system clock source after
00350   *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
00351   *           of failure of the HSE used directly or indirectly as system clock
00352   *           (if the Clock Security System CSS is enabled).
00353   * @note     MSI can not be stopped if it is used as system clock source.
00354   *           In this case, you have to select another source of the system
00355   *           clock then stop the MSI.
00356   * @note     After enabling the MSI, the application software should wait on
00357   *           MSIRDY flag to be set indicating that MSI clock is stable and can
00358   *           be used as system clock source.
00359   * @param  NewState: new state of the MSI.
00360   *   This parameter can be: ENABLE or DISABLE.
00361   * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
00362   *         clock cycles.
00363   * @retval None
00364   */
00365 void RCC_MSICmd(FunctionalState NewState)
00366 {
00367   /* Check the parameters */
00368   assert_param(IS_FUNCTIONAL_STATE(NewState));
00369
00370   *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
00371 }
00372
00373 /**
00374   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00375   * @note   The calibration is used to compensate for the variations in voltage
00376   *         and temperature that influence the frequency of the internal HSI RC.
00377   *         Refer to the Application Note AN3300 for more details on how to
00378   *         calibrate the HSI.
00379   * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
00380   *   This parameter must be a number between 0 and 0x1F.
00381   * @retval None
00382   */
00383 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
00384 {
00385   uint32_t tmpreg = 0;
00386
00387   /* Check the parameters */
00388   assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
00389
00390   tmpreg = RCC->ICSCR;
00391
00392   /* Clear HSITRIM[4:0] bits */
00393   tmpreg &= ~RCC_ICSCR_HSITRIM;
00394
00395   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
00396   tmpreg |= (uint32_t)HSICalibrationValue << 8;
00397
00398   /* Store the new value */
00399   RCC->ICSCR = tmpreg;
00400 }
00401
00402 /**
00403   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00404   * @note     After enabling the HSI, the application software should wait on
00405   *           HSIRDY flag to be set indicating that HSI clock is stable and can
00406   *           be used to clock the PLL and/or system clock.
00407   * @note     HSI can not be stopped if it is used directly or through the PLL
00408   *           as system clock. In this case, you have to select another source
00409   *           of the system clock then stop the HSI.
00410   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
00411   * @param  NewState: new state of the HSI.
00412   *   This parameter can be: ENABLE or DISABLE.
00413   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
00414   *         clock cycles.
00415   * @retval None
00416   */
00417 void RCC_HSICmd(FunctionalState NewState)
00418 {
00419   /* Check the parameters */
00420   assert_param(IS_FUNCTIONAL_STATE(NewState));
00421
00422   *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
00423 }
00424
00425 /**
00426   * @brief  Configures the External Low Speed oscillator (LSE).
00427   * @note     As the LSE is in the RTC domain and write access is denied to this
00428   *           domain after reset, you have to enable write access using
00429   *           PWR_RTCAccessCmd(ENABLE) function before to configure the LSE
00430   *           (to be done once after reset).
00431   * @note     After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
00432   *           software should wait on LSERDY flag to be set indicating that LSE clock
00433   *           is stable and can be used to clock the RTC.
00434   * @param  RCC_LSE: specifies the new state of the LSE.
00435   *   This parameter can be one of the following values:
00436   *     @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
00437   *                       6 LSE oscillator clock cycles.
00438   *     @arg RCC_LSE_ON: turn ON the LSE oscillator
00439   *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
00440   * @retval None
00441   */
00442 void RCC_LSEConfig(uint8_t RCC_LSE)
00443 {
00444   /* Check the parameters */
00445   assert_param(IS_RCC_LSE(RCC_LSE));
00446
00447   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
00448   *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
00449
00450   /* Set the new LSE configuration -------------------------------------------*/
00451   *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;
00452 }
00453
00454 /**
00455   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00456   * @note     After enabling the LSI, the application software should wait on
00457   *           LSIRDY flag to be set indicating that LSI clock is stable and can
00458   *           be used to clock the IWDG and/or the RTC.
00459   * @note     LSI can not be disabled if the IWDG is running.
00460   * @param  NewState: new state of the LSI.
00461   *   This parameter can be: ENABLE or DISABLE.
00462   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
00463   *         clock cycles.
00464   * @retval None
00465   */
00466 void RCC_LSICmd(FunctionalState NewState)
00467 {
00468   /* Check the parameters */
00469   assert_param(IS_FUNCTIONAL_STATE(NewState));
00470
00471   *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
00472 }
00473
00474 /**
00475   * @brief  Configures the PLL clock source and multiplication factor.
00476   * @note   This function must be used only when the PLL is disabled.
00477   *
00478   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00479   *   This parameter can be one of the following values:
00480   *     @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
00481   *     @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
00482   * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
00483   *         PLL source).
00484   *
00485   * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
00486   *   This parameter can be:
00487   *     @arg RCC_PLLMul_3: PLL clock source multiplied by 3
00488   *     @arg RCC_PLLMul_4: PLL clock source multiplied by 4
00489   *     @arg RCC_PLLMul_6: PLL clock source multiplied by 6
00490   *     @arg RCC_PLLMul_8: PLL clock source multiplied by 8
00491   *     @arg RCC_PLLMul_12: PLL clock source multiplied by 12
00492   *     @arg RCC_PLLMul_16: PLL clock source multiplied by 16
00493   *     @arg RCC_PLLMul_24: PLL clock source multiplied by 24
00494   *     @arg RCC_PLLMul_32: PLL clock source multiplied by 32
00495   *     @arg RCC_PLLMul_48: PLL clock source multiplied by 48
00496   * @note   The application software must set correctly the PLL multiplication
00497   *         factor to avoid exceeding:
00498   *             - 96 MHz as PLLVCO when the product is in range 1
00499   *             - 48 MHz as PLLVCO when the product is in range 2
00500   *             - 24 MHz when the product is in range 3
00501   * @note   When using the USB the PLLVCO should be 96MHz
00502   *
00503   * @param  RCC_PLLDiv: specifies the PLL division factor.
00504   *   This parameter can be:
00505   *     @arg RCC_PLLDiv_2: PLL Clock output divided by 2
00506   *     @arg RCC_PLLDiv_3: PLL Clock output divided by 3
00507   *     @arg RCC_PLLDiv_4: PLL Clock output divided by 4
00508   * @note   The application software must set correctly the output division to avoid
00509   *         exceeding 32 MHz as SYSCLK.
00510   *
00511   * @retval None
00512   */
00513 void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
00514 {
00515   /* Check the parameters */
00516   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00517   assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
00518   assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
00519
00520   *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
00521 }
00522
00523 /**
00524   * @brief  Enables or disables the PLL.
00525   * @note     After enabling the PLL, the application software should wait on
00526   *           PLLRDY flag to be set indicating that PLL clock is stable and can
00527   *           be used as system clock source.
00528   * @note     The PLL can not be disabled if it is used as system clock source
00529   * @note     The PLL is disabled by hardware when entering STOP and STANDBY modes.
00530   * @param  NewState: new state of the PLL.
00531   *   This parameter can be: ENABLE or DISABLE.
00532   * @retval None
00533   */
00534 void RCC_PLLCmd(FunctionalState NewState)
00535 {
00536   /* Check the parameters */
00537   assert_param(IS_FUNCTIONAL_STATE(NewState));
00538
00539   *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00540 }
00541
00542 /**
00543   * @brief  Enables or disables the Clock Security System.
00544   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00545   *         is automatically disabled and an interrupt is generated to inform the
00546   *         software about the failure (Clock Security System Interrupt, CSSI),
00547   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00548   *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
00549   * @param  NewState: new state of the Clock Security System.
00550   *         This parameter can be: ENABLE or DISABLE.
00551   * @retval None
00552   */
00553 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
00554 {
00555   /* Check the parameters */
00556   assert_param(IS_FUNCTIONAL_STATE(NewState));
00557
00558   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
00559 }
00560
00561 /**
00562   * @brief  Enables or disables the LSE Clock Security System.
00563   * @param  NewState: new state of the Clock Security System.
00564   *         This parameter can be: ENABLE or DISABLE.
00565   * @retval None
00566   */
00567 void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState)
00568 {
00569   /* Check the parameters */
00570   assert_param(IS_FUNCTIONAL_STATE(NewState));
00571
00572   *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)NewState;
00573 }
00574
00575 /**
00576   * @brief  Selects the clock source to output on MCO pin (PA8).
00577   * @note   PA8 should be configured in alternate function mode.
00578   * @param  RCC_MCOSource: specifies the clock source to output.
00579   *   This parameter can be one of the following values:
00580   *     @arg RCC_MCOSource_NoClock: No clock selected
00581   *     @arg RCC_MCOSource_SYSCLK: System clock selected
00582   *     @arg RCC_MCOSource_HSI: HSI oscillator clock selected
00583   *     @arg RCC_MCOSource_MSI: MSI oscillator clock selected
00584   *     @arg RCC_MCOSource_HSE: HSE oscillator clock selected
00585   *     @arg RCC_MCOSource_PLLCLK: PLL clock selected
00586   *     @arg RCC_MCOSource_LSI: LSI clock selected
00587   *     @arg RCC_MCOSource_LSE: LSE clock selected
00588   * @param  RCC_MCODiv: specifies the MCO prescaler.
00589   *   This parameter can be one of the following values:
00590   *     @arg RCC_MCODiv_1: no division applied to MCO clock
00591   *     @arg RCC_MCODiv_2: division by 2 applied to MCO clock
00592   *     @arg RCC_MCODiv_4: division by 4 applied to MCO clock
00593   *     @arg RCC_MCODiv_8: division by 8 applied to MCO clock
00594   *     @arg RCC_MCODiv_16: division by 16 applied to MCO clock
00595   * @retval None
00596   */
00597 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
00598 {
00599   /* Check the parameters */
00600   assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
00601   assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
00602
00603   /* Select MCO clock source and prescaler */
00604   *(__IO uint8_t *) CFGR_BYTE4_ADDRESS =  RCC_MCOSource | RCC_MCODiv;
00605 }
00606
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
00612  *  @brief   System, AHB and APB busses clocks configuration functions
00613  *
00614 @verbatim
00615  ===============================================================================
00616      ##### System, AHB and APB busses clocks configuration functions #####
00617  ===============================================================================
00618     [..] This section provide functions allowing to configure the System, AHB,
00619          APB1 and APB2 busses clocks.
00620          (#) Several clock sources can be used to drive the System clock (SYSCLK):
00621              MSI, HSI, HSE and PLL.
00622              The AHB clock (HCLK) is derived from System clock through configurable
00623              prescaler and used to clock the CPU, memory and peripherals mapped
00624              on AHB bus (DMA and GPIO).APB1 (PCLK1) and APB2 (PCLK2) clocks are
00625              derived from AHB clock through configurable prescalers and used to
00626              clock the peripherals mapped on these busses. You can use
00627              "RCC_GetClocksFreq()" function to retrieve the frequencies of these
00628              clocks.
00629
00630          -@- All the peripheral clocks are derived from the System clock (SYSCLK)
00631              except:
00632              (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
00633              (+@) The ADC clock which is always the HSI clock. A divider by 1, 2
00634                   or 4 allows to adapt the clock frequency to the device operating
00635                   conditions.
00636              (+@) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz
00637                   HSE_RTC (HSE divided by a programmable prescaler).
00638                   The System clock (SYSCLK) frequency must be higher or equal to
00639                   the RTC/LCD clock frequency.
00640              (+@) IWDG clock which is always the LSI clock.
00641
00642          (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
00643              Depending on the device voltage range, the maximum frequency should
00644              be adapted accordingly:
00645
00646         +----------------------------------------------------------------+
00647         |  Wait states  |                HCLK clock frequency (MHz)      |
00648         |               |------------------------------------------------|
00649         |   (Latency)   |            voltage range       | voltage range |
00650         |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
00651         |               |----------------|---------------|---------------|
00652         |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
00653         |-------------- |----------------|---------------|---------------|
00654         |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
00655         |---------------|----------------|---------------|---------------|
00656         |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
00657         +----------------------------------------------------------------+
00658
00659          (#) After reset, the System clock source is the MSI (2 MHz) with 0 WS,
00660              Flash 32-bit access is enabled and prefetch is disabled.
00661     [..] It is recommended to use the following software sequences to tune the
00662          number of wait states needed to access the Flash memory with the CPU
00663          frequency (HCLK).
00664          (+) Increasing the CPU frequency (in the same voltage range)
00665          (+) Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)"
00666              function
00667          (+) Check that 64-bit access is taken into account by reading FLASH_ACR
00668          (+) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)"
00669              function
00670          (+) Check that the new number of WS is taken into account by reading
00671              FLASH_ACR
00672          (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
00673          (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
00674              function
00675          (+) Check that the new CPU clock source is taken into account by reading
00676            the clock source status, using "RCC_GetSYSCLKSource()" function
00677          (+) Decreasing the CPU frequency (in the same voltage range)
00678          (+) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
00679          (+) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()"
00680              function
00681          (+) Check that the new CPU clock source is taken into account by reading
00682            the clock source status, using "RCC_GetSYSCLKSource()" function
00683          (+) Program the new number of WS, using "FLASH_SetLatency()" function
00684          (+) Check that the new number of WS is taken into account by reading
00685              FLASH_ACR
00686          (+) Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)"
00687              function
00688          (+) Check that 32-bit access is taken into account by reading FLASH_ACR
00689
00690 @endverbatim
00691   * @{
00692   */
00693
00694 /**
00695   * @brief  Configures the system clock (SYSCLK).
00696   * @note     The MSI is used (enabled by hardware) as system clock source after
00697   *           startup from Reset, wake-up from STOP and STANDBY mode, or in case
00698   *           of failure of the HSE used directly or indirectly as system clock
00699   *           (if the Clock Security System CSS is enabled).
00700   * @note     A switch from one clock source to another occurs only if the target
00701   *           clock source is ready (clock stable after startup delay or PLL locked).
00702   *           If a clock source which is not yet ready is selected, the switch will
00703   *           occur when the clock source will be ready.
00704   *           You can use RCC_GetSYSCLKSource() function to know which clock is
00705   *           currently used as system clock source.
00706   * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source
00707   *   This parameter can be one of the following values:
00708   *     @arg RCC_SYSCLKSource_MSI:    MSI selected as system clock source
00709   *     @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
00710   *     @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
00711   *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
00712   * @retval None
00713   */
00714 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
00715 {
00716   uint32_t tmpreg = 0;
00717
00718   /* Check the parameters */
00719   assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
00720
00721   tmpreg = RCC->CFGR;
00722
00723   /* Clear SW[1:0] bits */
00724   tmpreg &= ~RCC_CFGR_SW;
00725
00726   /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
00727   tmpreg |= RCC_SYSCLKSource;
00728
00729   /* Store the new value */
00730   RCC->CFGR = tmpreg;
00731 }
00732
00733 /**
00734   * @brief  Returns the clock source used as system clock.
00735   * @param  None
00736   * @retval The clock source used as system clock. The returned value can be one
00737   *         of the following values:
00738   *              - 0x00: MSI used as system clock
00739   *              - 0x04: HSI used as system clock
00740   *              - 0x08: HSE used as system clock
00741   *              - 0x0C: PLL used as system clock
00742   */
00743 uint8_t RCC_GetSYSCLKSource(void)
00744 {
00745   return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
00746 }
00747
00748 /**
00749   * @brief  Configures the AHB clock (HCLK).
00750   * @note   Depending on the device voltage range, the software has to set correctly
00751   *         these bits to ensure that the system frequency does not exceed the
00752   *         maximum allowed frequency (for more details refer to section above
00753   *         "CPU, AHB and APB busses clocks configuration functions")
00754   * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
00755   *                     the system clock (SYSCLK).
00756   *   This parameter can be one of the following values:
00757   *     @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
00758   *     @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
00759   *     @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
00760   *     @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
00761   *     @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
00762   *     @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
00763   *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
00764   *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
00765   *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
00766   * @retval None
00767   */
00768 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
00769 {
00770   uint32_t tmpreg = 0;
00771
00772   /* Check the parameters */
00773   assert_param(IS_RCC_HCLK(RCC_SYSCLK));
00774
00775   tmpreg = RCC->CFGR;
00776
00777   /* Clear HPRE[3:0] bits */
00778   tmpreg &= ~RCC_CFGR_HPRE;
00779
00780   /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
00781   tmpreg |= RCC_SYSCLK;
00782
00783   /* Store the new value */
00784   RCC->CFGR = tmpreg;
00785 }
00786
00787 /**
00788   * @brief  Configures the Low Speed APB clock (PCLK1).
00789   * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from
00790   *                   the AHB clock (HCLK).
00791   *   This parameter can be one of the following values:
00792   *     @arg RCC_HCLK_Div1:  APB1 clock = HCLK
00793   *     @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2
00794   *     @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4
00795   *     @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8
00796   *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
00797   * @retval None
00798   */
00799 void RCC_PCLK1Config(uint32_t RCC_HCLK)
00800 {
00801   uint32_t tmpreg = 0;
00802
00803   /* Check the parameters */
00804   assert_param(IS_RCC_PCLK(RCC_HCLK));
00805
00806   tmpreg = RCC->CFGR;
00807
00808   /* Clear PPRE1[2:0] bits */
00809   tmpreg &= ~RCC_CFGR_PPRE1;
00810
00811   /* Set PPRE1[2:0] bits according to RCC_HCLK value */
00812   tmpreg |= RCC_HCLK;
00813
00814   /* Store the new value */
00815   RCC->CFGR = tmpreg;
00816 }
00817
00818 /**
00819   * @brief  Configures the High Speed APB clock (PCLK2).
00820   * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from
00821   *                   the AHB clock (HCLK).
00822   *   This parameter can be one of the following values:
00823   *     @arg RCC_HCLK_Div1:  APB2 clock = HCLK
00824   *     @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2
00825   *     @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4
00826   *     @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8
00827   *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
00828   * @retval None
00829   */
00830 void RCC_PCLK2Config(uint32_t RCC_HCLK)
00831 {
00832   uint32_t tmpreg = 0;
00833
00834   /* Check the parameters */
00835   assert_param(IS_RCC_PCLK(RCC_HCLK));
00836
00837   tmpreg = RCC->CFGR;
00838
00839   /* Clear PPRE2[2:0] bits */
00840   tmpreg &= ~RCC_CFGR_PPRE2;
00841
00842   /* Set PPRE2[2:0] bits according to RCC_HCLK value */
00843   tmpreg |= RCC_HCLK << 3;
00844
00845   /* Store the new value */
00846   RCC->CFGR = tmpreg;
00847 }
00848
00849 /**
00850   * @brief  Returns the frequencies of the System, AHB and APB busses clocks.
00851   * @note     The frequency returned by this function is not the real frequency
00852   *           in the chip. It is calculated based on the predefined constant and
00853   *           the source selected by RCC_SYSCLKConfig():
00854   *
00855   * @note     If SYSCLK source is MSI, function returns values based on  MSI
00856   *             Value as defined by the MSI range, refer to RCC_MSIRangeConfig()
00857   *
00858   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00859   *
00860   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
00861   *
00862   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
00863   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
00864   *
00865   *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
00866   *             16 MHz) but the real value may vary depending on the variations
00867   *             in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
00868   *
00869   *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
00870   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
00871   *              frequency of the crystal used. Otherwise, this function may
00872   *              return wrong result.
00873   *
00874   *         - The result of this function could be not correct when using fractional
00875   *           value for HSE crystal.
00876   *
00877   * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
00878   *         the clocks frequencies.
00879   *
00880   * @note     This function can be used by the user application to compute the
00881   *           baudrate for the communication peripherals or configure other parameters.
00882   * @note     Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00883   *           must be called to update the structure's field. Otherwise, any
00884   *           configuration based on this function will be incorrect.
00885   *
00886   * @retval None
00887   */
00888 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
00889 {
00890   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
00891
00892   /* Get SYSCLK source -------------------------------------------------------*/
00893   tmp = RCC->CFGR & RCC_CFGR_SWS;
00894
00895   switch (tmp)
00896   {
00897     case 0x00:  /* MSI used as system clock */
00898       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
00899       RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
00900       break;
00901     case 0x04:  /* HSI used as system clock */
00902       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00903       break;
00904     case 0x08:  /* HSE used as system clock */
00905       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
00906       break;
00907     case 0x0C:  /* PLL used as system clock */
00908       /* Get PLL clock source and multiplication factor ----------------------*/
00909       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
00910       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
00911       pllmul = PLLMulTable[(pllmul >> 18)];
00912       plldiv = (plldiv >> 22) + 1;
00913
00914       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00915
00916       if (pllsource == 0x00)
00917       {
00918         /* HSI oscillator clock selected as PLL clock source */
00919         RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
00920       }
00921       else
00922       {
00923         /* HSE selected as PLL clock source */
00924         RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
00925       }
00926       break;
00927     default: /* MSI used as system clock */
00928       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
00929       RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));
00930       break;
00931   }
00932   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
00933   /* Get HCLK prescaler */
00934   tmp = RCC->CFGR & RCC_CFGR_HPRE;
00935   tmp = tmp >> 4;
00936   presc = APBAHBPrescTable[tmp];
00937   /* HCLK clock frequency */
00938   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00939
00940   /* Get PCLK1 prescaler */
00941   tmp = RCC->CFGR & RCC_CFGR_PPRE1;
00942   tmp = tmp >> 8;
00943   presc = APBAHBPrescTable[tmp];
00944   /* PCLK1 clock frequency */
00945   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00946
00947   /* Get PCLK2 prescaler */
00948   tmp = RCC->CFGR & RCC_CFGR_PPRE2;
00949   tmp = tmp >> 11;
00950   presc = APBAHBPrescTable[tmp];
00951   /* PCLK2 clock frequency */
00952   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00953 }
00954
00955 /**
00956   * @}
00957   */
00958
00959 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
00960  *  @brief   Peripheral clocks configuration functions
00961  *
00962 @verbatim
00963  ===============================================================================
00964              ##### Peripheral clocks configuration functions #####
00965  ===============================================================================
00966     [..] This section provide functions allowing to configure the Peripheral clocks.
00967          (#) The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
00968          (HSE divided by a programmable prescaler).
00969          (#) After restart from Reset or wakeup from STANDBY, all peripherals are
00970              off except internal SRAM, Flash and JTAG. Before to start using a
00971              peripheral you have to enable its interface clock. You can do this
00972              using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and
00973              RCC_APB1PeriphClockCmd() functions.
00974
00975          (#) To reset the peripherals configuration (to the default state after
00976              device reset) you can use RCC_AHBPeriphResetCmd(),
00977              RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions.
00978          (#) To further reduce power consumption in SLEEP mode the peripheral
00979              clocks can be disabled prior to executing the WFI or WFE instructions.
00980              You can do this using RCC_AHBPeriphClockLPModeCmd(),
00981              RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd()
00982              functions.
00983
00984 @endverbatim
00985   * @{
00986   */
00987
00988 /**
00989   * @brief  Configures the RTC and LCD clock (RTCCLK / LCDCLK).
00990   * @note     As the RTC clock configuration bits are in the RTC domain and write
00991   *           access is denied to this domain after reset, you have to enable write
00992   *           access using PWR_RTCAccessCmd(ENABLE) function before to configure
00993   *           the RTC clock source (to be done once after reset).
00994   * @note     Once the RTC clock is configured it can't be changed unless the RTC
00995   *           is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
00996   * @note     The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
00997   *
00998   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
00999   *   This parameter can be one of the following values:
01000   *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
01001   *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
01002   *     @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
01003   *     @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
01004   *     @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
01005   *     @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
01006   *
01007   * @note     If the LSE or LSI is used as RTC clock source, the RTC continues to
01008   *           work in STOP and STANDBY modes, and can be used as wakeup source.
01009   *           However, when the HSE clock is used as RTC clock source, the RTC
01010   *           cannot be used in STOP and STANDBY modes.
01011   *
01012   * @note     The maximum input clock frequency for RTC is 1MHz (when using HSE as
01013   *           RTC clock source).
01014   *
01015   * @retval None
01016   */
01017 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
01018 {
01019   uint32_t      tmpreg = 0;
01020
01021   /* Check the parameters */
01022   assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
01023
01024   if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
01025   {
01026     /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
01027     tmpreg = RCC->CR;
01028
01029     /* Clear RTCPRE[1:0] bits */
01030     tmpreg &= ~RCC_CR_RTCPRE;
01031
01032     /* Configure HSE division factor for RTC clock */
01033     tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
01034
01035     /* Store the new value */
01036     RCC->CR = tmpreg;
01037   }
01038
01039   RCC->CSR &= ~RCC_CSR_RTCSEL;
01040
01041   /* Select the RTC clock source */
01042   RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
01043 }
01044
01045 /**
01046   * @brief  Enables or disables the RTC clock.
01047   * @note   This function must be used only after the RTC clock source was selected
01048   *         using the RCC_RTCCLKConfig function.
01049   * @param  NewState: new state of the RTC clock.
01050   *   This parameter can be: ENABLE or DISABLE.
01051   * @retval None
01052   */
01053 void RCC_RTCCLKCmd(FunctionalState NewState)
01054 {
01055   /* Check the parameters */
01056   assert_param(IS_FUNCTIONAL_STATE(NewState));
01057
01058   *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
01059 }
01060
01061 /**
01062   * @brief  Forces or releases the RTC peripheral and associated resources reset.
01063   * @note   This function resets the RTC peripheral, RTC clock source selection
01064   *         (in RCC_CSR) and the backup registers.
01065   * @param  NewState: new state of the RTC reset.
01066   *   This parameter can be: ENABLE or DISABLE.
01067   * @retval None
01068   */
01069 void RCC_RTCResetCmd(FunctionalState NewState)
01070 {
01071   /* Check the parameters */
01072   assert_param(IS_FUNCTIONAL_STATE(NewState));
01073
01074   *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
01075 }
01076
01077 /**
01078   * @brief  Enables or disables the AHB peripheral clock.
01079   * @note   After reset, the peripheral clock (used for registers read/write access)
01080   *         is disabled and the application software has to enable this clock before
01081   *         using it.
01082   * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
01083   *   This parameter can be any combination of the following values:
01084   *     @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
01085   *     @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
01086   *     @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
01087   *     @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
01088   *     @arg RCC_AHBPeriph_GPIOE:         GPIOE clock
01089   *     @arg RCC_AHBPeriph_GPIOH:         GPIOH clock
01090   *     @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
01091   *     @arg RCC_AHBPeriph_GPIOG:         GPIOG clock
01092   *     @arg RCC_AHBPeriph_CRC:           CRC clock
01093   *     @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
01094   *     @arg RCC_AHBPeriph_DMA1:          DMA1 clock
01095   *     @arg RCC_AHBPeriph_DMA2:          DMA2 clock
01096   *     @arg RCC_AHBPeriph_AES:           AES clock
01097   *     @arg RCC_AHBPeriph_FSMC:          FSMC clock
01098   * @param  NewState: new state of the specified peripheral clock.
01099   *         This parameter can be: ENABLE or DISABLE.
01100   * @retval None
01101   */
01102 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01103 {
01104   /* Check the parameters */
01105   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
01106   assert_param(IS_FUNCTIONAL_STATE(NewState));
01107
01108   if (NewState != DISABLE)
01109   {
01110     RCC->AHBENR |= RCC_AHBPeriph;
01111   }
01112   else
01113   {
01114     RCC->AHBENR &= ~RCC_AHBPeriph;
01115   }
01116 }
01117
01118 /**
01119   * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
01120   * @note   After reset, the peripheral clock (used for registers read/write access)
01121   *         is disabled and the application software has to enable this clock before
01122   *         using it.
01123   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
01124   *   This parameter can be any combination of the following values:
01125   *     @arg RCC_APB2Periph_SYSCFG: SYSCFG APB2 Clock.
01126   *     @arg RCC_APB2Periph_TIM9: TIM9 APB2 Clock.
01127   *     @arg RCC_APB2Periph_TIM10: TIM10 APB2 Clock.
01128   *     @arg RCC_APB2Periph_TIM11: TIM11 APB2 Clock.
01129   *     @arg RCC_APB2Periph_ADC1: ADC1 APB2 Clock.
01130   *     @arg RCC_APB2Periph_SDIO: SDIO APB2 Clock.
01131   *     @arg RCC_APB2Periph_SPI1: SPI1 APB2 Clock.
01132   *     @arg RCC_APB2Periph_USART1: USART1 APB2 Clock.
01133   * @param  NewState: new state of the specified peripheral clock.
01134   *         This parameter can be: ENABLE or DISABLE.
01135   * @retval None
01136   */
01137 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01138 {
01139   /* Check the parameters */
01140   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01141   assert_param(IS_FUNCTIONAL_STATE(NewState));
01142
01143   if (NewState != DISABLE)
01144   {
01145     RCC->APB2ENR |= RCC_APB2Periph;
01146   }
01147   else
01148   {
01149     RCC->APB2ENR &= ~RCC_APB2Periph;
01150   }
01151 }
01152
01153 /**
01154   * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
01155   * @note   After reset, the peripheral clock (used for registers read/write access)
01156   *         is disabled and the application software has to enable this clock before
01157   *         using it.
01158   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
01159   *   This parameter can be any combination of the following values:
01160   *     @arg RCC_APB1Periph_TIM2:      TIM2 clock
01161   *     @arg RCC_APB1Periph_TIM3:      TIM3 clock
01162   *     @arg RCC_APB1Periph_TIM4:      TIM4 clock
01163   *     @arg RCC_APB1Periph_TIM5:      TIM5 clock
01164   *     @arg RCC_APB1Periph_TIM6:      TIM6 clock
01165   *     @arg RCC_APB1Periph_TIM7:      TIM7 clock
01166   *     @arg RCC_APB1Periph_LCD:       LCD clock
01167   *     @arg RCC_APB1Periph_WWDG:      WWDG clock
01168   *     @arg RCC_APB1Periph_SPI2:      SPI2 clock
01169   *     @arg RCC_APB1Periph_SPI3:      SPI3 clock
01170   *     @arg RCC_APB1Periph_USART2:    USART2 clock
01171   *     @arg RCC_APB1Periph_USART3:    USART3 clock
01172   *     @arg RCC_APB1Periph_UART4:     UART4 clock
01173   *     @arg RCC_APB1Periph_UART5:     UART5 clock
01174   *     @arg RCC_APB1Periph_I2C1:      I2C1 clock
01175   *     @arg RCC_APB1Periph_I2C2:      I2C2 clock
01176   *     @arg RCC_APB1Periph_USB:       USB clock
01177   *     @arg RCC_APB1Periph_PWR:       PWR clock
01178   *     @arg RCC_APB1Periph_DAC:       DAC clock
01179   *     @arg RCC_APB1Periph_COMP       COMP  clock
01180   * @param  NewState: new state of the specified peripheral clock.
01181   *         This parameter can be: ENABLE or DISABLE.
01182   * @retval None
01183   */
01184 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01185 {
01186   /* Check the parameters */
01187   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01188   assert_param(IS_FUNCTIONAL_STATE(NewState));
01189
01190   if (NewState != DISABLE)
01191   {
01192     RCC->APB1ENR |= RCC_APB1Periph;
01193   }
01194   else
01195   {
01196     RCC->APB1ENR &= ~RCC_APB1Periph;
01197   }
01198 }
01199
01200 /**
01201   * @brief  Forces or releases AHB peripheral reset.
01202   * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
01203   *   This parameter can be any combination of the following values:
01204   *     @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
01205   *     @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
01206   *     @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
01207   *     @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
01208   *     @arg RCC_AHBPeriph_GPIOE:         GPIOE clock
01209   *     @arg RCC_AHBPeriph_GPIOH:         GPIOH clock
01210   *     @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
01211   *     @arg RCC_AHBPeriph_GPIOG:         GPIOG clock
01212   *     @arg RCC_AHBPeriph_CRC:           CRC clock
01213   *     @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
01214   *     @arg RCC_AHBPeriph_DMA1:          DMA1 clock
01215   *     @arg RCC_AHBPeriph_DMA2:          DMA2 clock
01216   *     @arg RCC_AHBPeriph_AES:           AES clock
01217   *     @arg RCC_AHBPeriph_FSMC:          FSMC clock
01218   * @param  NewState: new state of the specified peripheral reset.
01219   *         This parameter can be: ENABLE or DISABLE.
01220   * @retval None
01221   */
01222 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01223 {
01224   /* Check the parameters */
01225   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
01226   assert_param(IS_FUNCTIONAL_STATE(NewState));
01227
01228   if (NewState != DISABLE)
01229   {
01230     RCC->AHBRSTR |= RCC_AHBPeriph;
01231   }
01232   else
01233   {
01234     RCC->AHBRSTR &= ~RCC_AHBPeriph;
01235   }
01236 }
01237
01238 /**
01239   * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
01240   * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
01241   *   This parameter can be any combination of the following values:
01242   *     @arg RCC_APB2Periph_SYSCFG:       SYSCFG clock
01243   *     @arg RCC_APB2Periph_TIM9:         TIM9 clock
01244   *     @arg RCC_APB2Periph_TIM10:        TIM10 clock
01245   *     @arg RCC_APB2Periph_TIM11:        TIM11 clock
01246   *     @arg RCC_APB2Periph_ADC1:         ADC1 clock
01247   *     @arg RCC_APB2Periph_SDIO:         SDIO clock
01248   *     @arg RCC_APB2Periph_SPI1:         SPI1 clock
01249   *     @arg RCC_APB2Periph_USART1:       USART1 clock
01250   * @param  NewState: new state of the specified peripheral reset.
01251   *         This parameter can be: ENABLE or DISABLE.
01252   * @retval None
01253   */
01254 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01255 {
01256   /* Check the parameters */
01257   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01258   assert_param(IS_FUNCTIONAL_STATE(NewState));
01259
01260   if (NewState != DISABLE)
01261   {
01262     RCC->APB2RSTR |= RCC_APB2Periph;
01263   }
01264   else
01265   {
01266     RCC->APB2RSTR &= ~RCC_APB2Periph;
01267   }
01268 }
01269
01270 /**
01271   * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
01272   * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
01273   *   This parameter can be any combination of the following values:
01274   *     @arg RCC_APB1Periph_TIM2:           TIM2 clock
01275   *     @arg RCC_APB1Periph_TIM3:           TIM3 clock
01276   *     @arg RCC_APB1Periph_TIM4:           TIM4 clock
01277   *     @arg RCC_APB1Periph_TIM5:           TIM5 clock
01278   *     @arg RCC_APB1Periph_TIM6:           TIM6 clock
01279   *     @arg RCC_APB1Periph_TIM7:           TIM7 clock
01280   *     @arg RCC_APB1Periph_LCD:            LCD clock
01281   *     @arg RCC_APB1Periph_WWDG:           WWDG clock
01282   *     @arg RCC_APB1Periph_SPI2:           SPI2 clock
01283   *     @arg RCC_APB1Periph_SPI3:           SPI3 clock
01284   *     @arg RCC_APB1Periph_USART2:         USART2 clock
01285   *     @arg RCC_APB1Periph_USART3:         USART3 clock
01286   *     @arg RCC_APB1Periph_UART4:          UART4 clock
01287   *     @arg RCC_APB1Periph_UART5:          UART5 clock
01288   *     @arg RCC_APB1Periph_I2C1:           I2C1 clock
01289   *     @arg RCC_APB1Periph_I2C2:           I2C2 clock
01290   *     @arg RCC_APB1Periph_USB:            USB clock
01291   *     @arg RCC_APB1Periph_PWR:            PWR clock
01292   *     @arg RCC_APB1Periph_DAC:            DAC clock
01293   *     @arg RCC_APB1Periph_COMP
01294   * @param  NewState: new state of the specified peripheral clock.
01295   *         This parameter can be: ENABLE or DISABLE.
01296   * @retval None
01297   */
01298 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01299 {
01300   /* Check the parameters */
01301   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01302   assert_param(IS_FUNCTIONAL_STATE(NewState));
01303
01304   if (NewState != DISABLE)
01305   {
01306     RCC->APB1RSTR |= RCC_APB1Periph;
01307   }
01308   else
01309   {
01310     RCC->APB1RSTR &= ~RCC_APB1Periph;
01311   }
01312 }
01313
01314 /**
01315   * @brief  Enables or disables the AHB peripheral clock during SLEEP mode.
01316   * @note     Peripheral clock gating in SLEEP mode can be used to further reduce
01317   *           power consumption.
01318   *         - After wakeup from SLEEP mode, the peripheral clock is enabled again.
01319   *         - By default, all peripheral clocks are enabled during SLEEP mode.
01320   * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
01321   *   This parameter can be any combination of the following values:
01322   *     @arg RCC_AHBPeriph_GPIOA:           GPIOA clock
01323   *     @arg RCC_AHBPeriph_GPIOB:           GPIOB clock
01324   *     @arg RCC_AHBPeriph_GPIOC:           GPIOC clock
01325   *     @arg RCC_AHBPeriph_GPIOD:           GPIOD clock
01326   *     @arg RCC_AHBPeriph_GPIOE:           GPIOE clock
01327   *     @arg RCC_AHBPeriph_GPIOH:           GPIOH clock
01328   *     @arg RCC_AHBPeriph_GPIOF:           GPIOF clock
01329   *     @arg RCC_AHBPeriph_GPIOG:           GPIOG clock
01330   *     @arg RCC_AHBPeriph_CRC:             CRC clock
01331   *     @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
01332   *     @arg RCC_AHBPeriph_SRAM:            SRAM clock
01333   *     @arg RCC_AHBPeriph_DMA1:            DMA1 clock
01334   *     @arg RCC_AHBPeriph_DMA2:            DMA2 clock
01335   *     @arg RCC_AHBPeriph_AES:             AES clock
01336   *     @arg RCC_AHBPeriph_FSMC:            FSMC clock
01337   * @param  NewState: new state of the specified peripheral clock.
01338   *         This parameter can be: ENABLE or DISABLE.
01339   * @retval None
01340   */
01341 void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01342 {
01343   /* Check the parameters */
01344   assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
01345   assert_param(IS_FUNCTIONAL_STATE(NewState));
01346
01347   if (NewState != DISABLE)
01348   {
01349     RCC->AHBLPENR |= RCC_AHBPeriph;
01350   }
01351   else
01352   {
01353     RCC->AHBLPENR &= ~RCC_AHBPeriph;
01354   }
01355 }
01356
01357 /**
01358   * @brief  Enables or disables the APB2 peripheral clock during SLEEP mode.
01359   * @note     Peripheral clock gating in SLEEP mode can be used to further reduce
01360   *           power consumption.
01361   * @note     After wakeup from SLEEP mode, the peripheral clock is enabled again.
01362   * @note     By default, all peripheral clocks are enabled during SLEEP mode.
01363   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
01364   *   This parameter can be any combination of the following values:
01365   *     @arg RCC_APB2Periph_SYSCFG:          SYSCFG clock
01366   *     @arg RCC_APB2Periph_TIM9:            TIM9 clock
01367   *     @arg RCC_APB2Periph_TIM10:           TIM10 clock
01368   *     @arg RCC_APB2Periph_TIM11:           TIM11 clock
01369   *     @arg RCC_APB2Periph_ADC1:            ADC1 clock
01370   *     @arg RCC_APB2Periph_SDIO:            SDIO clock
01371   *     @arg RCC_APB2Periph_SPI1:            SPI1 clock
01372   *     @arg RCC_APB2Periph_USART1:          USART1 clock
01373   * @param  NewState: new state of the specified peripheral clock.
01374   *         This parameter can be: ENABLE or DISABLE.
01375   * @retval None
01376   */
01377 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01378 {
01379   /* Check the parameters */
01380   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01381   assert_param(IS_FUNCTIONAL_STATE(NewState));
01382
01383   if (NewState != DISABLE)
01384   {
01385     RCC->APB2LPENR |= RCC_APB2Periph;
01386   }
01387   else
01388   {
01389     RCC->APB2LPENR &= ~RCC_APB2Periph;
01390   }
01391 }
01392
01393 /**
01394   * @brief  Enables or disables the APB1 peripheral clock during SLEEP mode.
01395   * @note     Peripheral clock gating in SLEEP mode can be used to further reduce
01396   *           power consumption.
01397   * @note     After wakeup from SLEEP mode, the peripheral clock is enabled again.
01398   * @note     By default, all peripheral clocks are enabled during SLEEP mode.
01399   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
01400   *   This parameter can be any combination of the following values:
01401   *     @arg RCC_APB1Periph_TIM2:                 TIM2 clock
01402   *     @arg RCC_APB1Periph_TIM3:                 TIM3 clock
01403   *     @arg RCC_APB1Periph_TIM4:                 TIM4 clock
01404   *     @arg RCC_APB1Periph_TIM5:                 TIM5 clock
01405   *     @arg RCC_APB1Periph_TIM6:                 TIM6 clock
01406   *     @arg RCC_APB1Periph_TIM7:                 TIM7 clock
01407   *     @arg RCC_APB1Periph_LCD:                  LCD clock
01408   *     @arg RCC_APB1Periph_WWDG:                 WWDG clock
01409   *     @arg RCC_APB1Periph_SPI2:                 SPI2 clock
01410   *     @arg RCC_APB1Periph_SPI3:                 SPI3 clock
01411   *     @arg RCC_APB1Periph_USART2:               USART2 clock
01412   *     @arg RCC_APB1Periph_USART3:               USART3 clock
01413   *     @arg RCC_APB1Periph_UART4:                UART4 clock
01414   *     @arg RCC_APB1Periph_UART5:                UART5 clock
01415   *     @arg RCC_APB1Periph_I2C1:                 I2C1 clock
01416   *     @arg RCC_APB1Periph_I2C2:                 I2C2 clock
01417   *     @arg RCC_APB1Periph_USB:                  USB clock
01418   *     @arg RCC_APB1Periph_PWR:                  PWR clock
01419   *     @arg RCC_APB1Periph_DAC:                  DAC clock
01420   *     @arg RCC_APB1Periph_COMP:                 COMP clock
01421   * @param  NewState: new state
01422   * @param  NewState: new state of the specified peripheral clock.
01423   *         This parameter can be: ENABLE or DISABLE.
01424   * @retval None
01425   */
01426 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01427 {
01428   /* Check the parameters */
01429   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01430   assert_param(IS_FUNCTIONAL_STATE(NewState));
01431
01432   if (NewState != DISABLE)
01433   {
01434     RCC->APB1LPENR |= RCC_APB1Periph;
01435   }
01436   else
01437   {
01438     RCC->APB1LPENR &= ~RCC_APB1Periph;
01439   }
01440 }
01441
01442 /**
01443   * @}
01444   */
01445
01446 /** @defgroup RCC_Group4 Interrupts and flags management functions
01447  *  @brief   Interrupts and flags management functions
01448  *
01449 @verbatim
01450  ===============================================================================
01451              ##### Interrupts and flags management functions #####
01452  ===============================================================================
01453
01454 @endverbatim
01455   * @{
01456   */
01457
01458 /**
01459   * @brief  Enables or disables the specified RCC interrupts.
01460   * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
01461   *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
01462   *         automatically generated. The NMI will be executed indefinitely, and
01463   *         since NMI has higher priority than any other IRQ (and main program)
01464   *         the application will be stacked in the NMI ISR unless the CSS interrupt
01465   *         pending bit is cleared.
01466   * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
01467   *   This parameter can be any combination of the following values:
01468   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01469   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01470   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01471   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01472   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01473   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
01474   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
01475   * @param  NewState: new state of the specified RCC interrupts.
01476   *   This parameter can be: ENABLE or DISABLE.
01477   * @retval None
01478   */
01479 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
01480 {
01481   /* Check the parameters */
01482   assert_param(IS_RCC_IT(RCC_IT));
01483   assert_param(IS_FUNCTIONAL_STATE(NewState));
01484
01485   if (NewState != DISABLE)
01486   {
01487     /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
01488     *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
01489   }
01490   else
01491   {
01492     /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
01493     *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
01494   }
01495 }
01496
01497 /**
01498   * @brief  Checks whether the specified RCC flag is set or not.
01499   * @param  RCC_FLAG: specifies the flag to check.
01500   *   This parameter can be one of the following values:
01501   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01502   *     @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
01503   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01504   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01505   *     @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
01506   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01507   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01508   *     @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
01509   *     @arg RCC_FLAG_PINRST: Pin reset
01510   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01511   *     @arg RCC_FLAG_SFTRST: Software reset
01512   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01513   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01514   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01515   * @retval The new state of RCC_FLAG (SET or RESET).
01516   */
01517 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
01518 {
01519   uint32_t tmp = 0;
01520   uint32_t statusreg = 0;
01521   FlagStatus bitstatus = RESET;
01522
01523   /* Check the parameters */
01524   assert_param(IS_RCC_FLAG(RCC_FLAG));
01525
01526   /* Get the RCC register index */
01527   tmp = RCC_FLAG >> 5;
01528
01529   if (tmp == 1)               /* The flag to check is in CR register */
01530   {
01531     statusreg = RCC->CR;
01532   }
01533   else          /* The flag to check is in CSR register (tmp == 2) */
01534   {
01535     statusreg = RCC->CSR;
01536   }
01537
01538   /* Get the flag position */
01539   tmp = RCC_FLAG & FLAG_MASK;
01540
01541   if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
01542   {
01543     bitstatus = SET;
01544   }
01545   else
01546   {
01547     bitstatus = RESET;
01548   }
01549   /* Return the flag status */
01550   return bitstatus;
01551 }
01552
01553 /**
01554   * @brief  Clears the RCC reset flags.
01555   *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
01556   *         RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
01557   * @param  None
01558   * @retval None
01559   */
01560 void RCC_ClearFlag(void)
01561 {
01562   /* Set RMVF bit to clear the reset flags */
01563   RCC->CSR |= RCC_CSR_RMVF;
01564 }
01565
01566 /**
01567   * @brief  Checks whether the specified RCC interrupt has occurred or not.
01568   * @param  RCC_IT: specifies the RCC interrupt source to check.
01569   *   This parameter can be one of the following values:
01570   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01571   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01572   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01573   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01574   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01575   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
01576   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
01577   *     @arg RCC_IT_CSS: Clock Security System interrupt
01578   * @retval The new state of RCC_IT (SET or RESET).
01579   */
01580 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
01581 {
01582   ITStatus bitstatus = RESET;
01583   /* Check the parameters */
01584   assert_param(IS_RCC_GET_IT(RCC_IT));
01585
01586   /* Check the status of the specified RCC interrupt */
01587   if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
01588   {
01589     bitstatus = SET;
01590   }
01591   else
01592   {
01593     bitstatus = RESET;
01594   }
01595   /* Return the RCC_IT status */
01596   return  bitstatus;
01597 }
01598
01599 /**
01600   * @brief  Clears the RCC's interrupt pending bits.
01601   * @param  RCC_IT: specifies the interrupt pending bit to clear.
01602   *   This parameter can be any combination of the following values:
01603   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01604   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01605   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01606   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01607   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01608   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
01609   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
01610   *     @arg RCC_IT_CSS: Clock Security System interrupt
01611   * @retval None
01612   */
01613 void RCC_ClearITPendingBit(uint8_t RCC_IT)
01614 {
01615   /* Check the parameters */
01616   assert_param(IS_RCC_CLEAR_IT(RCC_IT));
01617
01618   /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
01619      pending bits */
01620   *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
01621 }
01622
01623 /**
01624   * @}
01625   */
01626
01627 /**
01628   * @}
01629   */
01630
01631 /**
01632   * @}
01633   */
01634
01635 /**
01636   * @}
01637   */
01638
01639 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rcc.h Source File

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stm32l1xx_rcc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the RCC
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_RCC_H
00028 #define __STM32L1xx_RCC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup RCC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 typedef struct
00048 {
00049   uint32_t SYSCLK_Frequency;
00050   uint32_t HCLK_Frequency;
00051   uint32_t PCLK1_Frequency;
00052   uint32_t PCLK2_Frequency;
00053 }RCC_ClocksTypeDef;
00054
00055 /* Exported constants --------------------------------------------------------*/
00056
00057 /** @defgroup RCC_Exported_Constants
00058   * @{
00059   */
00060
00061 /** @defgroup RCC_HSE_configuration
00062   * @{
00063   */
00064
00065 #define RCC_HSE_OFF                      ((uint8_t)0x00)
00066 #define RCC_HSE_ON                       ((uint8_t)0x01)
00067 #define RCC_HSE_Bypass                   ((uint8_t)0x05)
00068 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
00069                          ((HSE) == RCC_HSE_Bypass))
00070
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup RCC_MSI_Clock_Range
00076   * @{
00077   */
00078
00079 #define RCC_MSIRange_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
00080 #define RCC_MSIRange_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
00081 #define RCC_MSIRange_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
00082 #define RCC_MSIRange_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
00083 #define RCC_MSIRange_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
00084 #define RCC_MSIRange_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
00085 #define RCC_MSIRange_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
00086
00087 #define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \
00088                                        ((RANGE) == RCC_MSIRange_1) || \
00089                                        ((RANGE) == RCC_MSIRange_2) || \
00090                                        ((RANGE) == RCC_MSIRange_3) || \
00091                                        ((RANGE) == RCC_MSIRange_4) || \
00092                                        ((RANGE) == RCC_MSIRange_5) || \
00093                                        ((RANGE) == RCC_MSIRange_6))
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup RCC_PLL_Clock_Source
00100   * @{
00101   */
00102
00103 #define RCC_PLLSource_HSI                ((uint8_t)0x00)
00104 #define RCC_PLLSource_HSE                ((uint8_t)0x01)
00105
00106 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
00107                                    ((SOURCE) == RCC_PLLSource_HSE))
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup RCC_PLL_Multiplication_Factor
00113   * @{
00114   */
00115
00116 #define RCC_PLLMul_3                     ((uint8_t)0x00)
00117 #define RCC_PLLMul_4                     ((uint8_t)0x04)
00118 #define RCC_PLLMul_6                     ((uint8_t)0x08)
00119 #define RCC_PLLMul_8                     ((uint8_t)0x0C)
00120 #define RCC_PLLMul_12                    ((uint8_t)0x10)
00121 #define RCC_PLLMul_16                    ((uint8_t)0x14)
00122 #define RCC_PLLMul_24                    ((uint8_t)0x18)
00123 #define RCC_PLLMul_32                    ((uint8_t)0x1C)
00124 #define RCC_PLLMul_48                    ((uint8_t)0x20)
00125
00126
00127 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
00128                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
00129                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
00130                              ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
00131                              ((MUL) == RCC_PLLMul_48))
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup RCC_PLL_Divider_Factor
00137   * @{
00138   */
00139
00140 #define RCC_PLLDiv_2                     ((uint8_t)0x40)
00141 #define RCC_PLLDiv_3                     ((uint8_t)0x80)
00142 #define RCC_PLLDiv_4                     ((uint8_t)0xC0)
00143
00144
00145 #define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
00146                              ((DIV) == RCC_PLLDiv_4))
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup RCC_System_Clock_Source
00152   * @{
00153   */
00154
00155 #define RCC_SYSCLKSource_MSI             RCC_CFGR_SW_MSI
00156 #define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
00157 #define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
00158 #define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
00159 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
00160                                       ((SOURCE) == RCC_SYSCLKSource_HSI) || \
00161                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \
00162                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup RCC_AHB_Clock_Source
00168   * @{
00169   */
00170
00171 #define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
00172 #define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
00173 #define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
00174 #define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
00175 #define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
00176 #define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
00177 #define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
00178 #define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
00179 #define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
00180 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
00181                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
00182                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
00183                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
00184                            ((HCLK) == RCC_SYSCLK_Div512))
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup RCC_APB1_APB2_Clock_Source
00190   * @{
00191   */
00192
00193 #define RCC_HCLK_Div1                    RCC_CFGR_PPRE1_DIV1
00194 #define RCC_HCLK_Div2                    RCC_CFGR_PPRE1_DIV2
00195 #define RCC_HCLK_Div4                    RCC_CFGR_PPRE1_DIV4
00196 #define RCC_HCLK_Div8                    RCC_CFGR_PPRE1_DIV8
00197 #define RCC_HCLK_Div16                   RCC_CFGR_PPRE1_DIV16
00198 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
00199                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
00200                            ((PCLK) == RCC_HCLK_Div16))
00201 /**
00202   * @}
00203   */
00204
00205
00206 /** @defgroup RCC_Interrupt_Source
00207   * @{
00208   */
00209
00210 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
00211 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
00212 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
00213 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
00214 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
00215 #define RCC_IT_MSIRDY                    ((uint8_t)0x20)
00216 #define RCC_IT_LSECSS                    ((uint8_t)0x40)
00217 #define RCC_IT_CSS                       ((uint8_t)0x80)
00218
00219 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
00220
00221 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00222                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00223                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
00224                            ((IT) == RCC_IT_CSS)  || ((IT) == RCC_IT_LSECSS))
00225
00226 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
00227
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup RCC_LSE_Configuration
00233   * @{
00234   */
00235
00236 #define RCC_LSE_OFF                      ((uint8_t)0x00)
00237 #define RCC_LSE_ON                       ((uint8_t)0x01)
00238 #define RCC_LSE_Bypass                   ((uint8_t)0x05)
00239 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
00240                          ((LSE) == RCC_LSE_Bypass))
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup RCC_RTC_Clock_Source
00246   * @{
00247   */
00248
00249 #define RCC_RTCCLKSource_LSE             RCC_CSR_RTCSEL_LSE
00250 #define RCC_RTCCLKSource_LSI             RCC_CSR_RTCSEL_LSI
00251 #define RCC_RTCCLKSource_HSE_Div2        RCC_CSR_RTCSEL_HSE
00252 #define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
00253 #define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
00254 #define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
00255 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
00256                                       ((SOURCE) == RCC_RTCCLKSource_LSI) || \
00257                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
00258                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
00259                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
00260                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup RCC_AHB_Peripherals
00266   * @{
00267   */
00268
00269 #define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
00270 #define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
00271 #define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
00272 #define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
00273 #define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
00274 #define RCC_AHBPeriph_GPIOH               RCC_AHBENR_GPIOHEN
00275 #define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
00276 #define RCC_AHBPeriph_GPIOG               RCC_AHBENR_GPIOGEN
00277 #define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
00278 #define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
00279 #define RCC_AHBPeriph_SRAM                RCC_AHBLPENR_SRAMLPEN
00280 #define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
00281 #define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
00282 #define RCC_AHBPeriph_AES                 RCC_AHBENR_AESEN
00283 #define RCC_AHBPeriph_FSMC                RCC_AHBENR_FSMCEN
00284
00285 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
00286 #define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup RCC_APB2_Peripherals
00293   * @{
00294   */
00295
00296 #define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
00297 #define RCC_APB2Periph_TIM9              RCC_APB2ENR_TIM9EN
00298 #define RCC_APB2Periph_TIM10             RCC_APB2ENR_TIM10EN
00299 #define RCC_APB2Periph_TIM11             RCC_APB2ENR_TIM11EN
00300 #define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
00301 #define RCC_APB2Periph_SDIO              RCC_APB2ENR_SDIOEN
00302 #define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
00303 #define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
00304
00305 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup RCC_APB1_Peripherals
00311   * @{
00312   */
00313
00314 #define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
00315 #define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
00316 #define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN
00317 #define RCC_APB1Periph_TIM5              RCC_APB1ENR_TIM5EN
00318 #define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
00319 #define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
00320 #define RCC_APB1Periph_LCD               RCC_APB1ENR_LCDEN
00321 #define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
00322 #define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
00323 #define RCC_APB1Periph_SPI3              RCC_APB1ENR_SPI3EN
00324 #define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
00325 #define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
00326 #define RCC_APB1Periph_UART4             RCC_APB1ENR_UART4EN
00327 #define RCC_APB1Periph_UART5             RCC_APB1ENR_UART5EN
00328 #define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
00329 #define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
00330 #define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
00331 #define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
00332 #define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN
00333 #define RCC_APB1Periph_COMP              RCC_APB1ENR_COMPEN
00334
00335
00336 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup RCC_MCO_Clock_Source
00342   * @{
00343   */
00344
00345 #define RCC_MCOSource_NoClock            ((uint8_t)0x00)
00346 #define RCC_MCOSource_SYSCLK             ((uint8_t)0x01)
00347 #define RCC_MCOSource_HSI                ((uint8_t)0x02)
00348 #define RCC_MCOSource_MSI                ((uint8_t)0x03)
00349 #define RCC_MCOSource_HSE                ((uint8_t)0x04)
00350 #define RCC_MCOSource_PLLCLK             ((uint8_t)0x05)
00351 #define RCC_MCOSource_LSI                ((uint8_t)0x06)
00352 #define RCC_MCOSource_LSE                ((uint8_t)0x07)
00353
00354 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
00355                                    ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_MSI) || \
00356                                    ((SOURCE) == RCC_MCOSource_HSE)  || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
00357                                    ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup RCC_MCO_Output_Divider
00363   * @{
00364   */
00365
00366 #define RCC_MCODiv_1                     ((uint8_t)0x00)
00367 #define RCC_MCODiv_2                     ((uint8_t)0x10)
00368 #define RCC_MCODiv_4                     ((uint8_t)0x20)
00369 #define RCC_MCODiv_8                     ((uint8_t)0x30)
00370 #define RCC_MCODiv_16                    ((uint8_t)0x40)
00371
00372 #define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
00373                              ((DIV) == RCC_MCODiv_4)  || ((DIV) == RCC_MCODiv_8) || \
00374                              ((DIV) == RCC_MCODiv_16))
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup RCC_Flag
00380   * @{
00381   */
00382
00383 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
00384 #define RCC_FLAG_MSIRDY                  ((uint8_t)0x29)
00385 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
00386 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
00387 #define RCC_FLAG_LSERDY                  ((uint8_t)0x49)
00388 #define RCC_FLAG_LSECSS                  ((uint8_t)0x4A)
00389 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
00390 #define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
00391 #define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
00392 #define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
00393 #define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
00394 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
00395 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
00396 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
00397
00398 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00399                            ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
00400                            ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
00401                            ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
00402                            ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
00403                            ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
00404                            ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LSECSS))
00405
00406 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
00407 #define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
00408
00409 /**
00410   * @}
00411   */
00412
00413 /**
00414   * @}
00415   */
00416
00417 /* Exported macro ------------------------------------------------------------*/
00418 /* Exported functions ------------------------------------------------------- */
00419
00420 /* Function used to set the RCC clock configuration to the default reset state */
00421 void RCC_DeInit(void);
00422
00423 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
00424 void RCC_HSEConfig(uint8_t RCC_HSE);
00425 ErrorStatus RCC_WaitForHSEStartUp(void);
00426 void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
00427 void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
00428 void RCC_MSICmd(FunctionalState NewState);
00429 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
00430 void RCC_HSICmd(FunctionalState NewState);
00431 void RCC_LSEConfig(uint8_t RCC_LSE);
00432 void RCC_LSICmd(FunctionalState NewState);
00433 void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
00434 void RCC_PLLCmd(FunctionalState NewState);
00435 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
00436 void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState);
00437 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
00438
00439 /* System, AHB and APB busses clocks configuration functions ******************/
00440 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
00441 uint8_t RCC_GetSYSCLKSource(void);
00442 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
00443 void RCC_PCLK1Config(uint32_t RCC_HCLK);
00444 void RCC_PCLK2Config(uint32_t RCC_HCLK);
00445 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
00446
00447 /* Peripheral clocks configuration functions **********************************/
00448 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
00449 void RCC_RTCCLKCmd(FunctionalState NewState);
00450 void RCC_RTCResetCmd(FunctionalState NewState);
00451
00452 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00453 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00454 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00455
00456 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00457 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00458 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00459
00460 void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00461 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00462 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00463
00464 /* Interrupts and flags management functions **********************************/
00465 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
00466 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
00467 void RCC_ClearFlag(void);
00468 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
00469 void RCC_ClearITPendingBit(uint8_t RCC_IT);
00470
00471 #ifdef __cplusplus
00472 }
00473 #endif
00474
00475 #endif /* __STM32L1xx_RCC_H */
00476
00477 /**
00478   * @}
00479   */
00480
00481 /**
00482   * @}
00483   */
00484
00485 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rtc.c Source File

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stm32l1xx_rtc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Real-Time Clock (RTC) peripheral:
00009   *           + Initialization
00010   *           + Calendar (Time and Date) configuration
00011   *           + Alarms (Alarm A and Alarm B) configuration
00012   *           + WakeUp Timer configuration
00013   *           + Daylight Saving configuration
00014   *           + Output pin Configuration
00015   *           + Coarse digital Calibration configuration
00016   *           + Smooth digital Calibration configuration
00017   *           + TimeStamp configuration
00018   *           + Tampers configuration
00019   *           + Backup Data Registers configuration
00020   *           + Output Type Config configuration
00021   *           + Shift control synchronisation
00022   *           + Interrupts and flags management
00023   *
00024  @verbatim
00025
00026  ===============================================================================
00027                         ##### RTC Domain Reset #####
00028  ===============================================================================
00029     [..] After power-on reset, the RTC domain (RTC clock source configuration,
00030          RTC registers and RTC Backup data registers) is reset. You can also
00031          reset this domain by software using the RCC_RTCResetCmd() function.
00032
00033                     ##### RTC Operating Condition #####
00034  ===============================================================================
00035     [..] As long as the supply voltage remains in the operating range,
00036          the RTC never stops, regardless of the device status (Run mode,
00037          low power modes or under reset).
00038
00039                        ##### RTC Domain Access #####
00040  ===============================================================================
00041     [..] After reset, the RTC domain (RTC clock source configuration,
00042          RTC registers and RTC Backup data registers) are protected against
00043          possible stray write accesses.
00044     [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00045          (+) Enable the Power Controller (PWR) APB1 interface clock using the
00046              RCC_APB1PeriphClockCmd() function.
00047          (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
00048          (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
00049          (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
00050
00051                      ##### How to use this driver #####
00052  ===============================================================================
00053     [..]
00054         (+) Enable the RTC domain access (see description in the section above)
00055         (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
00056             RTC hour format using the RTC_Init() function.
00057  ***Time and Date configuration ***
00058  ==================================
00059     [..]
00060         (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
00061             and RTC_SetDate() functions.
00062         (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
00063             functions.
00064         (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
00065         (+) Use the RTC_DayLightSavingConfig() function to add or sub one
00066             hour to the RTC Calendar.
00067
00068  ***Alarm configuration ***
00069  ==========================
00070     [..]
00071         (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
00072         (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
00073         (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
00074         (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
00075
00076  ***RTC Wakeup configuration ***
00077  ===============================
00078     [..]
00079         (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
00080             function.
00081         (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
00082             function.
00083         (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
00084         (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
00085             function.
00086
00087  ***Outputs configuration ***
00088  ============================
00089     [..] The RTC has 2 different outputs:
00090         (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00091             and WaKeUp signals.
00092             To output the selected RTC signal on RTC_AF1 pin, use the
00093             RTC_OutputConfig() function.
00094         (+) AFO_CALIB: this output is 512Hz signal or 1Hz.
00095             To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
00096             function.
00097
00098  ***Smooth digital Calibration configuration ***
00099  ===============================================
00100     [..]
00101         (+) Configure the RTC Original Digital Calibration Value and the corresponding
00102             calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
00103             function.
00104
00105  ***Coarse digital Calibration configuration ***
00106  ===============================================
00107     [..]
00108         (+) Configure the RTC Coarse Calibration Value and the corresponding
00109             sign using the RTC_CoarseCalibConfig() function.
00110         (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd()
00111             function.
00112
00113  ***TimeStamp configuration ***
00114  ==============================
00115     [..]
00116         (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp
00117             using the RTC_TimeStampCmd() function.
00118         (+) To read the RTC TimeStamp Time and Date register, use the
00119             RTC_GetTimeStamp() function.
00120         (+) To read the RTC TimeStamp SubSecond register, use the
00121             RTC_GetTimeStampSubSecond() function.
00122
00123  ***Tamper configuration ***
00124  ===========================
00125     [..]
00126         (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
00127             function.
00128         (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
00129             filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
00130             function.
00131         (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
00132             function.
00133         (+) Configure the Tamper precharge or discharge duration using
00134             RTC_TamperPinsPrechargeDuration() function.
00135         (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
00136         (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
00137         (+) Enable the Time stamp on Tamper detection event using
00138             RTC_TSOnTamperDetecCmd() function.
00139
00140  ***Backup Data Registers configuration ***
00141  ==========================================
00142     [..]
00143         (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
00144             function.
00145         (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
00146             function.
00147
00148                        ##### RTC and low power modes #####
00149  ===============================================================================
00150     [..] The MCU can be woken up from a low power mode by an RTC alternate
00151          function.
00152     [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00153          RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00154          These RTC alternate functions can wake up the system from the Stop
00155          and Standby lowpower modes.
00156          The system can also wake up from low power modes without depending
00157          on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00158          or the RTC wakeup events.
00159     [..] The RTC provides a programmable time base for waking up from the
00160          Stop or Standby mode at regular intervals.
00161          Wakeup from STOP and Standby modes is possible only when the RTC
00162          clock source is LSE or LSI.
00163
00164                ##### Selection of RTC_AF1 alternate functions #####
00165  ===============================================================================
00166     [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
00167          (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
00168          (+) AFO_ALARM output.
00169          (+) AFO_CALIB output.
00170          (+) AFI_TAMPER.
00171          (+) AFI_TIMESTAMP.
00172
00173    +------------------------------------------------------------------------------------------+
00174    |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2  |ALARMOUTTYPE  |
00175    |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |ENABLED |  AFO_ALARM   |
00176    |  and function   |          |          |           |              |        |Configuration |
00177    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00178    |   Alarm out     |          |          |           |              | Don't  |              |
00179    |   output OD     |     1    |    0     |Don't care | Don't care   | care   |      0       |
00180    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00181    |   Alarm out     |          |          |           |              | Don't  |              |
00182    |   output PP     |     1    |    0     |Don't care | Don't care   | care   |      1       |
00183    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00184    | Calibration out |          |          |           |              | Don't  |              |
00185    |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
00186    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00187    |  TAMPER input   |          |          |           |              | Don't  |              |
00188    |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
00189    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00190    |  TIMESTAMP and  |          |          |           |              | Don't  |              |
00191    |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
00192    |   floating      |          |          |           |              |        |              |
00193    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00194    | TIMESTAMP input |          |          |           |              | Don't  |              |
00195    |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
00196    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00197    |  Wakeup Pin 2   |     0    |    0     |     0     |      0       |   1    |  Don't care  |
00198    |-----------------|----------|----------|-----------|--------------|--------|--------------|
00199    |  Standard GPIO  |     0    |    0     |     0     |      0       |   0    |  Don't care  |
00200    +------------------------------------------------------------------------------------------+
00201
00202  @endverbatim
00203
00204   ******************************************************************************
00205   * @attention
00206   *
00207   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00208   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00209   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00210   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00211   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00212   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00213   *
00214   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00215   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00216   *
00217   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00218   ******************************************************************************
00219   */
00220
00221 /* Includes ------------------------------------------------------------------*/
00222 #include "stm32l1xx_rtc.h"
00223 #include "stm32l1xx_rcc.h"
00224
00225 /** @addtogroup STM32L1xx_StdPeriph_Driver
00226   * @{
00227   */
00228
00229 /** @defgroup RTC
00230   * @brief RTC driver modules
00231   * @{
00232   */
00233
00234 /* Private typedef -----------------------------------------------------------*/
00235 /* Private define ------------------------------------------------------------*/
00236
00237 /* Masks Definition */
00238 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
00239 #define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
00240 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)
00241 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
00242 #define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
00243                                             RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
00244                                             RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
00245                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
00246                                             RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
00247                                             RTC_FLAG_SHPF))
00248
00249 #define INITMODE_TIMEOUT         ((uint32_t) 0x00002000)
00250 #define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
00251 #define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
00252 #define SHPF_TIMEOUT             ((uint32_t) 0x00002000)
00253
00254 /* Private macro -------------------------------------------------------------*/
00255 /* Private variables ---------------------------------------------------------*/
00256 /* Private function prototypes -----------------------------------------------*/
00257 static uint8_t RTC_ByteToBcd2(uint8_t Value);
00258 static uint8_t RTC_Bcd2ToByte(uint8_t Value);
00259
00260 /* Private functions ---------------------------------------------------------*/
00261
00262 /** @defgroup RTC_Private_Functions
00263   * @{
00264   */
00265
00266 /** @defgroup RTC_Group1 Initialization and Configuration functions
00267  *  @brief   Initialization and Configuration functions
00268  *
00269 @verbatim
00270  ===============================================================================
00271             ##### Initialization and Configuration functions #####
00272  ===============================================================================
00273     [..] This section provide functions allowing to initialize and configure the
00274          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00275          RTC registers Write protection, enter and exit the RTC initialization mode,
00276          RTC registers synchronization check and reference clock detection enable.
00277          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00278              It is split into 2 programmable prescalers to minimize power consumption.
00279              (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
00280              (++) When both prescalers are used, it is recommended to configure the
00281                  asynchronous prescaler to a high value to minimize consumption.
00282          (#) All RTC registers are Write protected. Writing to the RTC registers
00283              is enabled by writing a key into the Write Protection register, RTC_WPR.
00284          (#) To Configure the RTC Calendar, user application should enter
00285              initialization mode. In this mode, the calendar counter is stopped
00286              and its value can be updated. When the initialization sequence is
00287              complete, the calendar restarts counting after 4 RTCCLK cycles.
00288          (#) To read the calendar through the shadow registers after Calendar
00289              initialization, calendar update or after wakeup from low power modes
00290              the software must first clear the RSF flag. The software must then
00291              wait until it is set again before reading the calendar, which means
00292              that the calendar registers have been correctly copied into the
00293              RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
00294              implements the above software sequence (RSF clear and RSF check).
00295
00296 @endverbatim
00297   * @{
00298   */
00299
00300 /**
00301   * @brief  Deinitializes the RTC registers to their default reset values.
00302   * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
00303   *         registers.
00304   * @param  None
00305   * @retval An ErrorStatus enumeration value:
00306   *          - SUCCESS: RTC registers are deinitialized
00307   *          - ERROR: RTC registers are not deinitialized
00308   */
00309 ErrorStatus RTC_DeInit(void)
00310 {
00311   __IO uint32_t wutcounter = 0x00;
00312   uint32_t wutwfstatus = 0x00;
00313   ErrorStatus status = ERROR;
00314
00315   /* Disable the write protection for RTC registers */
00316   RTC->WPR = 0xCA;
00317   RTC->WPR = 0x53;
00318
00319   /* Set Initialization mode */
00320   if (RTC_EnterInitMode() == ERROR)
00321   {
00322     status = ERROR;
00323   }
00324   else
00325   {
00326     /* Reset TR, DR and CR registers */
00327     RTC->TR = (uint32_t)0x00000000;
00328     RTC->DR = (uint32_t)0x00002101;
00329
00330     /* Reset All CR bits except CR[2:0] */
00331     RTC->CR &= (uint32_t)0x00000007;
00332
00333     /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00334     do
00335     {
00336       wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
00337       wutcounter++;
00338     } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
00339
00340     if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
00341     {
00342       status = ERROR;
00343     }
00344     else
00345     {
00346       /* Reset all RTC CR register bits */
00347       RTC->CR        &= (uint32_t)0x00000000;
00348       RTC->WUTR      = (uint32_t)0x0000FFFF;
00349       RTC->PRER      = (uint32_t)0x007F00FF;
00350       RTC->CALIBR    = (uint32_t)0x00000000;
00351       RTC->ALRMAR    = (uint32_t)0x00000000;
00352       RTC->ALRMBR    = (uint32_t)0x00000000;
00353       RTC->SHIFTR    = (uint32_t)0x00000000;
00354       RTC->CALR       = (uint32_t)0x00000000;
00355       RTC->ALRMASSR  = (uint32_t)0x00000000;
00356       RTC->ALRMBSSR  = (uint32_t)0x00000000;
00357
00358       /* Reset ISR register and exit initialization mode */
00359       RTC->ISR = (uint32_t)0x00000000;
00360
00361       /* Reset Tamper and alternate functions configuration register */
00362       RTC->TAFCR = 0x00000000;
00363
00364       /* Wait till the RTC RSF flag is set */
00365       if (RTC_WaitForSynchro() == ERROR)
00366       {
00367         status = ERROR;
00368       }
00369       else
00370       {
00371         status = SUCCESS;
00372       }
00373     }
00374   }
00375
00376   /* Enable the write protection for RTC registers */
00377   RTC->WPR = 0xFF;
00378
00379   return status;
00380 }
00381
00382 /**
00383   * @brief  Initializes the RTC registers according to the specified parameters
00384   *         in RTC_InitStruct.
00385   * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
00386   *         the configuration information for the RTC peripheral.
00387   * @note   The RTC Prescaler register is write protected and can be written in
00388   *         initialization mode only.
00389   * @retval An ErrorStatus enumeration value:
00390   *          - SUCCESS: RTC registers are initialized
00391   *          - ERROR: RTC registers are not initialized
00392   */
00393 ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
00394 {
00395   ErrorStatus status = ERROR;
00396
00397   /* Check the parameters */
00398   assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
00399   assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
00400   assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
00401
00402   /* Disable the write protection for RTC registers */
00403   RTC->WPR = 0xCA;
00404   RTC->WPR = 0x53;
00405
00406   /* Set Initialization mode */
00407   if (RTC_EnterInitMode() == ERROR)
00408   {
00409     status = ERROR;
00410   }
00411   else
00412   {
00413     /* Clear RTC CR FMT Bit */
00414     RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
00415     /* Set RTC_CR register */
00416     RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
00417
00418     /* Configure the RTC PRER */
00419     RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
00420     RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
00421
00422     /* Exit Initialization mode */
00423     RTC_ExitInitMode();
00424
00425     status = SUCCESS;
00426   }
00427   /* Enable the write protection for RTC registers */
00428   RTC->WPR = 0xFF;
00429
00430   return status;
00431 }
00432
00433 /**
00434   * @brief  Fills each RTC_InitStruct member with its default value.
00435   * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
00436   *         initialized.
00437   * @retval None
00438   */
00439 void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
00440 {
00441   /* Initialize the RTC_HourFormat member */
00442   RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
00443
00444   /* Initialize the RTC_AsynchPrediv member */
00445   RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
00446
00447   /* Initialize the RTC_SynchPrediv member */
00448   RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
00449 }
00450
00451 /**
00452   * @brief  Enables or disables the RTC registers write protection.
00453   * @note   All the RTC registers are write protected except for RTC_ISR[13:8],
00454   *         RTC_TAFCR and RTC_BKPxR.
00455   * @note   Writing a wrong key reactivates the write protection.
00456   * @note   The protection mechanism is not affected by system reset.
00457   * @param  NewState: new state of the write protection.
00458   *   This parameter can be: ENABLE or DISABLE.
00459   * @retval None
00460   */
00461 void RTC_WriteProtectionCmd(FunctionalState NewState)
00462 {
00463   /* Check the parameters */
00464   assert_param(IS_FUNCTIONAL_STATE(NewState));
00465
00466   if (NewState != DISABLE)
00467   {
00468     /* Enable the write protection for RTC registers */
00469     RTC->WPR = 0xFF;
00470   }
00471   else
00472   {
00473     /* Disable the write protection for RTC registers */
00474     RTC->WPR = 0xCA;
00475     RTC->WPR = 0x53;
00476   }
00477 }
00478
00479 /**
00480   * @brief  Enters the RTC Initialization mode.
00481   * @note   The RTC Initialization mode is write protected, use the
00482   *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
00483   * @param  None
00484   * @retval An ErrorStatus enumeration value:
00485   *          - SUCCESS: RTC is in Init mode
00486   *          - ERROR: RTC is not in Init mode
00487   */
00488 ErrorStatus RTC_EnterInitMode(void)
00489 {
00490   __IO uint32_t initcounter = 0x00;
00491   ErrorStatus status = ERROR;
00492   uint32_t initstatus = 0x00;
00493
00494   /* Check if the Initialization mode is set */
00495   if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
00496   {
00497     /* Set the Initialization mode */
00498     RTC->ISR = (uint32_t)RTC_INIT_MASK;
00499
00500     /* Wait till RTC is in INIT state and if Time out is reached exit */
00501     do
00502     {
00503       initstatus = RTC->ISR & RTC_ISR_INITF;
00504       initcounter++;
00505     } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
00506
00507     if ((RTC->ISR & RTC_ISR_INITF) != RESET)
00508     {
00509       status = SUCCESS;
00510     }
00511     else
00512     {
00513       status = ERROR;
00514     }
00515   }
00516   else
00517   {
00518     status = SUCCESS;
00519   }
00520
00521   return (status);
00522 }
00523
00524 /**
00525   * @brief  Exits the RTC Initialization mode.
00526   * @note   When the initialization sequence is complete, the calendar restarts
00527   *         counting after 4 RTCCLK cycles.
00528   * @note   The RTC Initialization mode is write protected, use the
00529   *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
00530   * @param  None
00531   * @retval None
00532   */
00533 void RTC_ExitInitMode(void)
00534 {
00535   /* Exit Initialization mode */
00536   RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
00537 }
00538
00539 /**
00540   * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
00541   *         synchronized with RTC APB clock.
00542   * @note   The RTC Resynchronization mode is write protected, use the
00543   *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
00544   * @note   To read the calendar through the shadow registers after Calendar
00545   *         initialization, calendar update or after wakeup from low power modes
00546   *         the software must first clear the RSF flag.
00547   *         The software must then wait until it is set again before reading
00548   *         the calendar, which means that the calendar registers have been
00549   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00550   * @param  None
00551   * @retval An ErrorStatus enumeration value:
00552   *          - SUCCESS: RTC registers are synchronised
00553   *          - ERROR: RTC registers are not synchronised
00554   */
00555 ErrorStatus RTC_WaitForSynchro(void)
00556 {
00557   __IO uint32_t synchrocounter = 0;
00558   ErrorStatus status = ERROR;
00559   uint32_t synchrostatus = 0x00;
00560
00561   /* Disable the write protection for RTC registers */
00562   RTC->WPR = 0xCA;
00563   RTC->WPR = 0x53;
00564
00565   /* Clear RSF flag */
00566   RTC->ISR &= (uint32_t)RTC_RSF_MASK;
00567
00568   /* Wait the registers to be synchronised */
00569   do
00570   {
00571     synchrostatus = RTC->ISR & RTC_ISR_RSF;
00572     synchrocounter++;
00573   } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
00574
00575   if ((RTC->ISR & RTC_ISR_RSF) != RESET)
00576   {
00577     status = SUCCESS;
00578   }
00579   else
00580   {
00581     status = ERROR;
00582   }
00583
00584   /* Enable the write protection for RTC registers */
00585   RTC->WPR = 0xFF;
00586
00587   return (status);
00588 }
00589
00590 /**
00591   * @brief  Enables or disables the RTC reference clock detection.
00592   * @param  NewState: new state of the RTC reference clock.
00593   *   This parameter can be: ENABLE or DISABLE.
00594   * @retval An ErrorStatus enumeration value:
00595   *          - SUCCESS: RTC reference clock detection is enabled
00596   *          - ERROR: RTC reference clock detection is disabled
00597   */
00598 ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
00599 {
00600   ErrorStatus status = ERROR;
00601
00602   /* Check the parameters */
00603   assert_param(IS_FUNCTIONAL_STATE(NewState));
00604
00605   /* Disable the write protection for RTC registers */
00606   RTC->WPR = 0xCA;
00607   RTC->WPR = 0x53;
00608
00609   /* Set Initialization mode */
00610   if (RTC_EnterInitMode() == ERROR)
00611   {
00612     status = ERROR;
00613   }
00614   else
00615   {
00616     if (NewState != DISABLE)
00617     {
00618       /* Enable the RTC reference clock detection */
00619       RTC->CR |= RTC_CR_REFCKON;
00620     }
00621     else
00622     {
00623       /* Disable the RTC reference clock detection */
00624       RTC->CR &= ~RTC_CR_REFCKON;
00625     }
00626     /* Exit Initialization mode */
00627     RTC_ExitInitMode();
00628
00629     status = SUCCESS;
00630   }
00631
00632   /* Enable the write protection for RTC registers */
00633   RTC->WPR = 0xFF;
00634
00635   return status;
00636 }
00637
00638 /**
00639   * @brief  Enables or Disables the Bypass Shadow feature.
00640   * @note   When the Bypass Shadow is enabled the calendar value are taken
00641   *         directly from the Calendar counter.
00642   * @param  NewState: new state of the Bypass Shadow feature.
00643   *         This parameter can be: ENABLE or DISABLE.
00644   * @retval None
00645 */
00646 void RTC_BypassShadowCmd(FunctionalState NewState)
00647 {
00648   /* Check the parameters */
00649   assert_param(IS_FUNCTIONAL_STATE(NewState));
00650
00651   /* Disable the write protection for RTC registers */
00652   RTC->WPR = 0xCA;
00653   RTC->WPR = 0x53;
00654
00655   if (NewState != DISABLE)
00656   {
00657     /* Set the BYPSHAD bit */
00658     RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
00659   }
00660   else
00661   {
00662     /* Reset the BYPSHAD bit */
00663     RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
00664   }
00665
00666   /* Enable the write protection for RTC registers */
00667   RTC->WPR = 0xFF;
00668 }
00669
00670 /**
00671   * @}
00672   */
00673
00674 /** @defgroup RTC_Group2 Time and Date configuration functions
00675  *  @brief   Time and Date configuration functions
00676  *
00677 @verbatim
00678  ===============================================================================
00679                ##### Time and Date configuration functions #####
00680  ===============================================================================
00681     [..] This section provide functions allowing to program and read the RTC
00682          Calendar (Time and Date).
00683
00684 @endverbatim
00685   * @{
00686   */
00687
00688 /**
00689   * @brief  Set the RTC current time.
00690   * @param  RTC_Format: specifies the format of the entered parameters.
00691   *   This parameter can be  one of the following values:
00692   *     @arg RTC_Format_BIN:  Binary data format.
00693   *     @arg RTC_Format_BCD:  BCD data format.
00694   * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
00695   *                        the time configuration information for the RTC.
00696   * @retval An ErrorStatus enumeration value:
00697   *          - SUCCESS: RTC Time register is configured
00698   *          - ERROR: RTC Time register is not configured
00699   */
00700 ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
00701 {
00702   uint32_t tmpreg = 0;
00703   ErrorStatus status = ERROR;
00704
00705   /* Check the parameters */
00706   assert_param(IS_RTC_FORMAT(RTC_Format));
00707
00708   if (RTC_Format == RTC_Format_BIN)
00709   {
00710     if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
00711     {
00712       assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
00713       assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
00714     }
00715     else
00716     {
00717       RTC_TimeStruct->RTC_H12 = 0x00;
00718       assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
00719     }
00720     assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
00721     assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
00722   }
00723   else
00724   {
00725     if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
00726     {
00727       tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
00728       assert_param(IS_RTC_HOUR12(tmpreg));
00729       assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
00730     }
00731     else
00732     {
00733       RTC_TimeStruct->RTC_H12 = 0x00;
00734       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
00735     }
00736     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
00737     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
00738   }
00739
00740   /* Check the input parameters format */
00741   if (RTC_Format != RTC_Format_BIN)
00742   {
00743     tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
00744              ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
00745              ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
00746              ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
00747   }
00748   else
00749   {
00750     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
00751                    ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
00752                    ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
00753                    (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
00754   }
00755
00756   /* Disable the write protection for RTC registers */
00757   RTC->WPR = 0xCA;
00758   RTC->WPR = 0x53;
00759
00760   /* Set Initialization mode */
00761   if (RTC_EnterInitMode() == ERROR)
00762   {
00763     status = ERROR;
00764   }
00765   else
00766   {
00767     /* Set the RTC_TR register */
00768     RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00769
00770     /* Exit Initialization mode */
00771     RTC_ExitInitMode();
00772
00773     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00774     if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
00775     {
00776       if (RTC_WaitForSynchro() == ERROR)
00777       {
00778         status = ERROR;
00779       }
00780       else
00781       {
00782         status = SUCCESS;
00783       }
00784     }
00785     else
00786     {
00787       status = SUCCESS;
00788     }
00789
00790   }
00791   /* Enable the write protection for RTC registers */
00792   RTC->WPR = 0xFF;
00793
00794   return status;
00795 }
00796
00797 /**
00798   * @brief  Fills each RTC_TimeStruct member with its default value
00799   *         (Time = 00h:00min:00sec).
00800   * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
00801   *         initialized.
00802   * @retval None
00803   */
00804 void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
00805 {
00806   /* Time = 00h:00min:00sec */
00807   RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
00808   RTC_TimeStruct->RTC_Hours = 0;
00809   RTC_TimeStruct->RTC_Minutes = 0;
00810   RTC_TimeStruct->RTC_Seconds = 0;
00811 }
00812
00813 /**
00814   * @brief  Get the RTC current Time.
00815   * @param  RTC_Format: specifies the format of the returned parameters.
00816   *   This parameter can be  one of the following values:
00817   *     @arg RTC_Format_BIN:  Binary data format.
00818   *     @arg RTC_Format_BCD:  BCD data format.
00819   * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
00820   *                        contain the returned current time configuration.
00821   * @retval None
00822   */
00823 void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
00824 {
00825   uint32_t tmpreg = 0;
00826
00827   /* Check the parameters */
00828   assert_param(IS_RTC_FORMAT(RTC_Format));
00829
00830   /* Get the RTC_TR register */
00831   tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
00832
00833   /* Fill the structure fields with the read parameters */
00834   RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00835   RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
00836   RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00837   RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
00838
00839   /* Check the input parameters format */
00840   if (RTC_Format == RTC_Format_BIN)
00841   {
00842     /* Convert the structure parameters to Binary format */
00843     RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
00844     RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
00845     RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
00846   }
00847 }
00848
00849 /**
00850   * @brief  Gets the RTC current Calendar Subseconds value.
00851   * @note   This function freeze the Time and Date registers after reading the
00852   *         SSR register.
00853   * @param  None
00854   * @retval RTC current Calendar Subseconds value.
00855   */
00856 uint32_t RTC_GetSubSecond(void)
00857 {
00858   uint32_t tmpreg = 0;
00859
00860   /* Get subseconds values from the correspondent registers*/
00861   tmpreg = (uint32_t)(RTC->SSR);
00862
00863   /* Read DR register to unfroze calendar registers */
00864   (void) (RTC->DR);
00865
00866   return (tmpreg);
00867 }
00868
00869 /**
00870   * @brief  Set the RTC current date.
00871   * @param  RTC_Format: specifies the format of the entered parameters.
00872   *   This parameter can be  one of the following values:
00873   *     @arg RTC_Format_BIN:  Binary data format.
00874   *     @arg RTC_Format_BCD:  BCD data format.
00875   * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
00876   *                         the date configuration information for the RTC.
00877   * @retval An ErrorStatus enumeration value:
00878   *          - SUCCESS: RTC Date register is configured
00879   *          - ERROR: RTC Date register is not configured
00880   */
00881 ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
00882 {
00883   uint32_t tmpreg = 0;
00884   ErrorStatus status = ERROR;
00885
00886   /* Check the parameters */
00887   assert_param(IS_RTC_FORMAT(RTC_Format));
00888
00889   if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
00890   {
00891     RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
00892   }
00893   if (RTC_Format == RTC_Format_BIN)
00894   {
00895     assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
00896     assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
00897     assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
00898   }
00899   else
00900   {
00901     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
00902     tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
00903     assert_param(IS_RTC_MONTH(tmpreg));
00904     tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
00905     assert_param(IS_RTC_DATE(tmpreg));
00906   }
00907   assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
00908
00909   /* Check the input parameters format */
00910   if (RTC_Format != RTC_Format_BIN)
00911   {
00912     tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
00913               (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
00914               ((uint32_t)RTC_DateStruct->RTC_Date) | \
00915               (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
00916   }
00917   else
00918   {
00919     tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
00920               ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
00921               ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
00922               ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
00923   }
00924
00925   /* Disable the write protection for RTC registers */
00926   RTC->WPR = 0xCA;
00927   RTC->WPR = 0x53;
00928
00929   /* Set Initialization mode */
00930   if (RTC_EnterInitMode() == ERROR)
00931   {
00932     status = ERROR;
00933   }
00934   else
00935   {
00936     /* Set the RTC_DR register */
00937     RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
00938
00939     /* Exit Initialization mode */
00940     RTC_ExitInitMode();
00941
00942     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00943     if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
00944     {
00945       if (RTC_WaitForSynchro() == ERROR)
00946       {
00947         status = ERROR;
00948       }
00949       else
00950       {
00951         status = SUCCESS;
00952       }
00953     }
00954     else
00955     {
00956       status = SUCCESS;
00957     }
00958   }
00959   /* Enable the write protection for RTC registers */
00960   RTC->WPR = 0xFF;
00961
00962   return status;
00963 }
00964
00965 /**
00966   * @brief  Fills each RTC_DateStruct member with its default value
00967   *         (Monday, January 01 xx00).
00968   * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
00969   *         initialized.
00970   * @retval None
00971   */
00972 void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
00973 {
00974   /* Monday, January 01 xx00 */
00975   RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
00976   RTC_DateStruct->RTC_Date = 1;
00977   RTC_DateStruct->RTC_Month = RTC_Month_January;
00978   RTC_DateStruct->RTC_Year = 0;
00979 }
00980
00981 /**
00982   * @brief  Get the RTC current date.
00983   * @param  RTC_Format: specifies the format of the returned parameters.
00984   *   This parameter can be one of the following values:
00985   *     @arg RTC_Format_BIN: Binary data format.
00986   *     @arg RTC_Format_BCD: BCD data format.
00987   * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
00988   *                        contain the returned current date configuration.
00989   * @retval None
00990   */
00991 void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
00992 {
00993   uint32_t tmpreg = 0;
00994
00995   /* Check the parameters */
00996   assert_param(IS_RTC_FORMAT(RTC_Format));
00997
00998   /* Get the RTC_TR register */
00999   tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
01000
01001   /* Fill the structure fields with the read parameters */
01002   RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
01003   RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
01004   RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
01005   RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
01006
01007   /* Check the input parameters format */
01008   if (RTC_Format == RTC_Format_BIN)
01009   {
01010     /* Convert the structure parameters to Binary format */
01011     RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
01012     RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
01013     RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
01014   }
01015 }
01016
01017 /**
01018   * @}
01019   */
01020
01021 /** @defgroup RTC_Group3 Alarms configuration functions
01022  *  @brief   Alarms (Alarm A and Alarm B) configuration functions
01023  *
01024 @verbatim
01025  ===============================================================================
01026          ##### Alarms (Alarm A and Alarm B) configuration functions #####
01027  ===============================================================================
01028     [..] This section provide functions allowing to program and read the RTC
01029          Alarms.
01030
01031 @endverbatim
01032   * @{
01033   */
01034
01035 /**
01036   * @brief  Set the specified RTC Alarm.
01037   * @note   The Alarm register can only be written when the corresponding Alarm
01038   *         is disabled (Use the RTC_AlarmCmd(DISABLE)).
01039   * @param  RTC_Format: specifies the format of the returned parameters.
01040   *   This parameter can be one of the following values:
01041   *     @arg RTC_Format_BIN: Binary data format.
01042   *     @arg RTC_Format_BCD: BCD data format.
01043   * @param  RTC_Alarm: specifies the alarm to be configured.
01044   *   This parameter can be one of the following values:
01045   *     @arg RTC_Alarm_A: to select Alarm A.
01046   *     @arg RTC_Alarm_B: to select Alarm B.
01047   * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
01048   *                          contains the alarm configuration parameters.
01049   * @retval None
01050   */
01051 void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
01052 {
01053   uint32_t tmpreg = 0;
01054
01055   /* Check the parameters */
01056   assert_param(IS_RTC_FORMAT(RTC_Format));
01057   assert_param(IS_RTC_ALARM(RTC_Alarm));
01058   assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
01059   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
01060
01061   if (RTC_Format == RTC_Format_BIN)
01062   {
01063     if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
01064     {
01065       assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
01066       assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
01067     }
01068     else
01069     {
01070       RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
01071       assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
01072     }
01073     assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
01074     assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
01075
01076     if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
01077     {
01078       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
01079     }
01080     else
01081     {
01082       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
01083     }
01084   }
01085   else
01086   {
01087     if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
01088     {
01089       tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
01090       assert_param(IS_RTC_HOUR12(tmpreg));
01091       assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
01092     }
01093     else
01094     {
01095       RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
01096       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
01097     }
01098
01099     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
01100     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
01101
01102     if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
01103     {
01104       tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
01105       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01106     }
01107     else
01108     {
01109       tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
01110       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01111     }
01112   }
01113
01114   /* Check the input parameters format */
01115   if (RTC_Format != RTC_Format_BIN)
01116   {
01117     tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
01118               ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
01119               ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
01120               ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
01121               ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
01122               ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
01123               ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
01124   }
01125   else
01126   {
01127     tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
01128               ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
01129               ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
01130               ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
01131               ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
01132               ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
01133               ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
01134   }
01135
01136   /* Disable the write protection for RTC registers */
01137   RTC->WPR = 0xCA;
01138   RTC->WPR = 0x53;
01139
01140   /* Configure the Alarm register */
01141   if (RTC_Alarm == RTC_Alarm_A)
01142   {
01143     RTC->ALRMAR = (uint32_t)tmpreg;
01144   }
01145   else
01146   {
01147     RTC->ALRMBR = (uint32_t)tmpreg;
01148   }
01149
01150   /* Enable the write protection for RTC registers */
01151   RTC->WPR = 0xFF;
01152 }
01153
01154 /**
01155   * @brief  Fills each RTC_AlarmStruct member with its default value
01156   *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
01157   *         all fields are masked).
01158   * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
01159   *         will be initialized.
01160   * @retval None
01161   */
01162 void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
01163 {
01164   /* Alarm Time Settings : Time = 00h:00mn:00sec */
01165   RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
01166   RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
01167   RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
01168   RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
01169
01170   /* Alarm Date Settings : Date = 1st day of the month */
01171   RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
01172   RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
01173
01174   /* Alarm Masks Settings : Mask =  all fields are not masked */
01175   RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
01176 }
01177
01178 /**
01179   * @brief  Get the RTC Alarm value and masks.
01180   * @param  RTC_Format: specifies the format of the output parameters.
01181   *   This parameter can be one of the following values:
01182   *     @arg RTC_Format_BIN: Binary data format.
01183   *     @arg RTC_Format_BCD: BCD data format.
01184   * @param  RTC_Alarm: specifies the alarm to be read.
01185   *   This parameter can be one of the following values:
01186   *     @arg RTC_Alarm_A: to select Alarm A.
01187   *     @arg RTC_Alarm_B: to select Alarm B.
01188   * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
01189   *                          contains the output alarm configuration values.
01190   * @retval None
01191   */
01192 void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
01193 {
01194   uint32_t tmpreg = 0;
01195
01196   /* Check the parameters */
01197   assert_param(IS_RTC_FORMAT(RTC_Format));
01198   assert_param(IS_RTC_ALARM(RTC_Alarm));
01199
01200   /* Get the RTC_ALRMxR register */
01201   if (RTC_Alarm == RTC_Alarm_A)
01202   {
01203     tmpreg = (uint32_t)(RTC->ALRMAR);
01204   }
01205   else
01206   {
01207     tmpreg = (uint32_t)(RTC->ALRMBR);
01208   }
01209
01210   /* Fill the structure with the read parameters */
01211   RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
01212                                                      RTC_ALRMAR_HU)) >> 16);
01213   RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
01214                                                      RTC_ALRMAR_MNU)) >> 8);
01215   RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
01216                                                      RTC_ALRMAR_SU));
01217   RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
01218   RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
01219   RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01220   RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
01221
01222   if (RTC_Format == RTC_Format_BIN)
01223   {
01224     RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
01225                                                         RTC_AlarmTime.RTC_Hours);
01226     RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
01227                                                         RTC_AlarmTime.RTC_Minutes);
01228     RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
01229                                                         RTC_AlarmTime.RTC_Seconds);
01230     RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
01231   }
01232 }
01233
01234 /**
01235   * @brief  Enables or disables the specified RTC Alarm.
01236   * @param  RTC_Alarm: specifies the alarm to be configured.
01237   *   This parameter can be any combination of the following values:
01238   *     @arg RTC_Alarm_A: to select Alarm A.
01239   *     @arg RTC_Alarm_B: to select Alarm B.
01240   * @param  NewState: new state of the specified alarm.
01241   *   This parameter can be: ENABLE or DISABLE.
01242   * @retval An ErrorStatus enumeration value:
01243   *          - SUCCESS: RTC Alarm is enabled/disabled
01244   *          - ERROR: RTC Alarm is not enabled/disabled
01245   */
01246 ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
01247 {
01248   __IO uint32_t alarmcounter = 0x00;
01249   uint32_t alarmstatus = 0x00;
01250   ErrorStatus status = ERROR;
01251
01252   /* Check the parameters */
01253   assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
01254   assert_param(IS_FUNCTIONAL_STATE(NewState));
01255
01256   /* Disable the write protection for RTC registers */
01257   RTC->WPR = 0xCA;
01258   RTC->WPR = 0x53;
01259
01260   /* Configure the Alarm state */
01261   if (NewState != DISABLE)
01262   {
01263     RTC->CR |= (uint32_t)RTC_Alarm;
01264
01265     status = SUCCESS;
01266   }
01267   else
01268   {
01269     /* Disable the Alarm in RTC_CR register */
01270     RTC->CR &= (uint32_t)~RTC_Alarm;
01271
01272     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01273     do
01274     {
01275       alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
01276       alarmcounter++;
01277     } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
01278
01279     if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
01280     {
01281       status = ERROR;
01282     }
01283     else
01284     {
01285       status = SUCCESS;
01286     }
01287   }
01288
01289   /* Enable the write protection for RTC registers */
01290   RTC->WPR = 0xFF;
01291
01292   return status;
01293 }
01294
01295 /**
01296   * @brief  Configure the RTC AlarmA/B Subseconds value and mask.*
01297   * @note   This function is performed only when the Alarm is disabled.
01298   * @param  RTC_Alarm: specifies the alarm to be configured.
01299   *   This parameter can be one of the following values:
01300   *     @arg RTC_Alarm_A: to select Alarm A.
01301   *     @arg RTC_Alarm_B: to select Alarm B.
01302   * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
01303   *   This parameter can be a value from 0 to 0x00007FFF.
01304   * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
01305   *   This parameter can be any combination of the following values:
01306   *     @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
01307   *                                      There is no comparison on sub seconds for Alarm.
01308   *     @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
01309   *                                         Only SS[0] is compared
01310   *     @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
01311   *                                          Only SS[1:0] are compared
01312   *     @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
01313   *                                          Only SS[2:0] are compared
01314   *     @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
01315   *                                          Only SS[3:0] are compared
01316   *     @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
01317   *                                          Only SS[4:0] are compared.
01318   *     @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
01319   *                                          Only SS[5:0] are compared.
01320   *     @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
01321   *                                          Only SS[6:0] are compared.
01322   *     @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
01323   *                                          Only SS[7:0] are compared.
01324   *     @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
01325   *                                          Only SS[8:0] are compared.
01326   *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
01327   *                                          Only SS[9:0] are compared.
01328   *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
01329   *                                          Only SS[10:0] are compared.
01330   *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
01331   *                                          Only SS[11:0] are compared.
01332   *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
01333   *                                          Only SS[12:0] are compared.
01334   *     @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
01335   *                                          Only SS[13:0] are compared.
01336   *     @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match
01337   *                                          to activate alarm.
01338   * @retval None
01339   */
01340 void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
01341 {
01342   uint32_t tmpreg = 0;
01343
01344   /* Check the parameters */
01345   assert_param(IS_RTC_ALARM(RTC_Alarm));
01346   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
01347   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
01348
01349   /* Disable the write protection for RTC registers */
01350   RTC->WPR = 0xCA;
01351   RTC->WPR = 0x53;
01352
01353   /* Configure the Alarm A or Alarm B SubSecond registers */
01354   tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
01355
01356   if (RTC_Alarm == RTC_Alarm_A)
01357   {
01358     /* Configure the AlarmA SubSecond register */
01359     RTC->ALRMASSR = tmpreg;
01360   }
01361   else
01362   {
01363     /* Configure the Alarm B SubSecond register */
01364     RTC->ALRMBSSR = tmpreg;
01365   }
01366
01367   /* Enable the write protection for RTC registers */
01368   RTC->WPR = 0xFF;
01369
01370 }
01371
01372 /**
01373   * @brief  Gets the RTC Alarm Subseconds value.
01374   * @param  RTC_Alarm: specifies the alarm to be read.
01375   *   This parameter can be one of the following values:
01376   *     @arg RTC_Alarm_A: to select Alarm A.
01377   *     @arg RTC_Alarm_B: to select Alarm B.
01378   * @param  None
01379   * @retval RTC Alarm Subseconds value.
01380   */
01381 uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
01382 {
01383   uint32_t tmpreg = 0;
01384
01385   /* Get the RTC_ALRMxR register */
01386   if (RTC_Alarm == RTC_Alarm_A)
01387   {
01388     tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
01389   }
01390   else
01391   {
01392     tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
01393   }
01394
01395   return (tmpreg);
01396 }
01397
01398 /**
01399   * @}
01400   */
01401
01402 /** @defgroup RTC_Group4 WakeUp Timer configuration functions
01403  *  @brief   WakeUp Timer configuration functions
01404  *
01405 @verbatim
01406  ===============================================================================
01407                ##### WakeUp Timer configuration functions #####
01408  ===============================================================================
01409     [..] This section provide functions allowing to program and read the RTC WakeUp.
01410
01411 @endverbatim
01412   * @{
01413   */
01414
01415 /**
01416   * @brief  Configures the RTC Wakeup clock source.
01417   * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
01418   *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
01419   * @param  RTC_WakeUpClock: Wakeup Clock source.
01420   *   This parameter can be one of the following values:
01421   *            @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16.
01422   *            @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8.
01423   *            @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4.
01424   *            @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2.
01425   *            @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE.
01426   *            @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE.
01427   * @retval None
01428   */
01429 void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
01430 {
01431   /* Check the parameters */
01432   assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
01433
01434   /* Disable the write protection for RTC registers */
01435   RTC->WPR = 0xCA;
01436   RTC->WPR = 0x53;
01437
01438   /* Clear the Wakeup Timer clock source bits in CR register */
01439   RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01440
01441   /* Configure the clock source */
01442   RTC->CR |= (uint32_t)RTC_WakeUpClock;
01443
01444   /* Enable the write protection for RTC registers */
01445   RTC->WPR = 0xFF;
01446 }
01447
01448 /**
01449   * @brief  Configures the RTC Wakeup counter.
01450   * @note   The RTC WakeUp counter can only be written when the RTC WakeUp.
01451   *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
01452   * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
01453   *   This parameter can be a value from 0x0000 to 0xFFFF.
01454   * @retval None
01455   */
01456 void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
01457 {
01458   /* Check the parameters */
01459   assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
01460
01461   /* Disable the write protection for RTC registers */
01462   RTC->WPR = 0xCA;
01463   RTC->WPR = 0x53;
01464
01465   /* Configure the Wakeup Timer counter */
01466   RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
01467
01468   /* Enable the write protection for RTC registers */
01469   RTC->WPR = 0xFF;
01470 }
01471
01472 /**
01473   * @brief  Returns the RTC WakeUp timer counter value.
01474   * @param  None
01475   * @retval The RTC WakeUp Counter value.
01476   */
01477 uint32_t RTC_GetWakeUpCounter(void)
01478 {
01479   /* Get the counter value */
01480   return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
01481 }
01482
01483 /**
01484   * @brief  Enables or Disables the RTC WakeUp timer.
01485   * @param  NewState: new state of the WakeUp timer.
01486   *   This parameter can be: ENABLE or DISABLE.
01487   * @retval None
01488   */
01489 ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
01490 {
01491   __IO uint32_t wutcounter = 0x00;
01492   uint32_t wutwfstatus = 0x00;
01493   ErrorStatus status = ERROR;
01494
01495   /* Check the parameters */
01496   assert_param(IS_FUNCTIONAL_STATE(NewState));
01497
01498   /* Disable the write protection for RTC registers */
01499   RTC->WPR = 0xCA;
01500   RTC->WPR = 0x53;
01501
01502   if (NewState != DISABLE)
01503   {
01504     /* Enable the Wakeup Timer */
01505     RTC->CR |= (uint32_t)RTC_CR_WUTE;
01506     status = SUCCESS;
01507   }
01508   else
01509   {
01510     /* Disable the Wakeup Timer */
01511     RTC->CR &= (uint32_t)~RTC_CR_WUTE;
01512     /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01513     do
01514     {
01515       wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
01516       wutcounter++;
01517     } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
01518
01519     if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
01520     {
01521       status = ERROR;
01522     }
01523     else
01524     {
01525       status = SUCCESS;
01526     }
01527   }
01528
01529   /* Enable the write protection for RTC registers */
01530   RTC->WPR = 0xFF;
01531
01532   return status;
01533 }
01534
01535 /**
01536   * @}
01537   */
01538
01539 /** @defgroup RTC_Group5 Daylight Saving configuration functions
01540  *  @brief   Daylight Saving configuration functions
01541  *
01542 @verbatim
01543  ===============================================================================
01544               ##### Daylight Saving configuration functions #####
01545  ===============================================================================
01546     [..] This section provide functions allowing to configure the RTC DayLight Saving.
01547
01548 @endverbatim
01549   * @{
01550   */
01551
01552 /**
01553   * @brief  Adds or substract one hour from the current time.
01554   * @param  RTC_DayLightSaveOperation: the value of hour adjustment.
01555   *   This parameter can be one of the following values:
01556   *     @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time).
01557   *     @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time).
01558   * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit
01559   *                            in CR register to store the operation.
01560   *   This parameter can be one of the following values:
01561   *            @arg RTC_StoreOperation_Reset: BCK Bit Reset.
01562   *            @arg RTC_StoreOperation_Set: BCK Bit Set.
01563   * @retval None
01564   */
01565 void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
01566 {
01567   /* Check the parameters */
01568   assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
01569   assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
01570
01571   /* Disable the write protection for RTC registers */
01572   RTC->WPR = 0xCA;
01573   RTC->WPR = 0x53;
01574
01575   /* Clear the bits to be configured */
01576   RTC->CR &= (uint32_t)~(RTC_CR_BCK);
01577
01578   /* Configure the RTC_CR register */
01579   RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
01580
01581   /* Enable the write protection for RTC registers */
01582   RTC->WPR = 0xFF;
01583 }
01584
01585 /**
01586   * @brief  Returns the RTC Day Light Saving stored operation.
01587   * @param  None
01588   * @retval RTC Day Light Saving stored operation.
01589   *          - RTC_StoreOperation_Reset
01590   *          - RTC_StoreOperation_Set
01591   */
01592 uint32_t RTC_GetStoreOperation(void)
01593 {
01594   return (RTC->CR & RTC_CR_BCK);
01595 }
01596
01597 /**
01598   * @}
01599   */
01600
01601 /** @defgroup RTC_Group6 Output pin Configuration function
01602  *  @brief   Output pin Configuration function
01603  *
01604 @verbatim
01605  ===============================================================================
01606                   ##### Output pin Configuration function #####
01607  ===============================================================================
01608     [..] This section provide functions allowing to configure the RTC Output source.
01609
01610 @endverbatim
01611   * @{
01612   */
01613
01614 /**
01615   * @brief  Configures the RTC output source (AFO_ALARM).
01616   * @param  RTC_Output: Specifies which signal will be routed to the RTC output.
01617   *   This parameter can be one of the following values:
01618   *     @arg RTC_Output_Disable: No output selected
01619   *     @arg RTC_Output_AlarmA: signal of AlarmA mapped to output.
01620   *     @arg RTC_Output_AlarmB: signal of AlarmB mapped to output.
01621   *     @arg RTC_Output_WakeUp: signal of WakeUp mapped to output.
01622   * @param  RTC_OutputPolarity: Specifies the polarity of the output signal.
01623   *   This parameter can be one of the following:
01624   *     @arg RTC_OutputPolarity_High: The output pin is high when the
01625   *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
01626   *     @arg RTC_OutputPolarity_Low: The output pin is low when the
01627   *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
01628   * @retval None
01629   */
01630 void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
01631 {
01632   /* Check the parameters */
01633   assert_param(IS_RTC_OUTPUT(RTC_Output));
01634   assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
01635
01636   /* Disable the write protection for RTC registers */
01637   RTC->WPR = 0xCA;
01638   RTC->WPR = 0x53;
01639
01640   /* Clear the bits to be configured */
01641   RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
01642
01643   /* Configure the output selection and polarity */
01644   RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
01645
01646   /* Enable the write protection for RTC registers */
01647   RTC->WPR = 0xFF;
01648 }
01649
01650 /**
01651   * @}
01652   */
01653
01654 /** @defgroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
01655  *  @brief   Coarse and Smooth Calibrations configuration functions
01656  *
01657 @verbatim
01658  ===============================================================================
01659         ##### Coarse and Smooth Calibrations configuration functions #####
01660  ===============================================================================
01661
01662 @endverbatim
01663   * @{
01664   */
01665
01666 /**
01667   * @brief  Configures the Coarse Calibration parameters.
01668   * @param  RTC_CalibSign: specifies the sign of the calibration value.
01669   *   This parameter can be  one of the following values:
01670   *     @arg RTC_CalibSign_Positive: The value sign is positive.
01671   *     @arg RTC_CalibSign_Negative: The value sign is negative.
01672   * @param  Value: value of calibration expressed in ppm (coded on 5 bits)
01673   *                This value should be between 0 and 63 when using negative sign
01674   *                with a 2-ppm step.
01675   *                This value should be between 0 and 126 when using positive sign
01676   *                with a 4-ppm step.
01677   * @retval An ErrorStatus enumeration value:
01678   *          - SUCCESS: RTC Coarse calibration are initialized
01679   *          - ERROR: RTC Coarse calibration are not initialized
01680   */
01681 ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
01682 {
01683   ErrorStatus status = ERROR;
01684
01685   /* Check the parameters */
01686   assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
01687   assert_param(IS_RTC_CALIB_VALUE(Value));
01688
01689   /* Disable the write protection for RTC registers */
01690   RTC->WPR = 0xCA;
01691   RTC->WPR = 0x53;
01692
01693   /* Set Initialization mode */
01694   if (RTC_EnterInitMode() == ERROR)
01695   {
01696     status = ERROR;
01697   }
01698   else
01699   {
01700     /* Set the coarse calibration value */
01701     RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
01702     /* Exit Initialization mode */
01703     RTC_ExitInitMode();
01704
01705     status = SUCCESS;
01706   }
01707
01708   /* Enable the write protection for RTC registers */
01709   RTC->WPR = 0xFF;
01710
01711   return status;
01712 }
01713
01714 /**
01715 * @brief  Enables or disables the Coarse calibration process.
01716   * @param  NewState: new state of the Coarse calibration.
01717   *          This parameter can be: ENABLE or DISABLE.
01718   * @retval An ErrorStatus enumeration value:
01719   *          - SUCCESS: RTC Coarse calibration are enabled/disabled
01720   *          - ERROR: RTC Coarse calibration are not enabled/disabled
01721   */
01722 ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
01723 {
01724   ErrorStatus status = ERROR;
01725
01726   /* Check the parameters */
01727   assert_param(IS_FUNCTIONAL_STATE(NewState));
01728
01729   /* Disable the write protection for RTC registers */
01730   RTC->WPR = 0xCA;
01731   RTC->WPR = 0x53;
01732
01733   /* Set Initialization mode */
01734   if (RTC_EnterInitMode() == ERROR)
01735   {
01736     status =  ERROR;
01737   }
01738   else
01739   {
01740     if (NewState != DISABLE)
01741     {
01742       /* Enable the Coarse Calibration */
01743       RTC->CR |= (uint32_t)RTC_CR_DCE;
01744     }
01745     else
01746     {
01747       /* Disable the Coarse Calibration */
01748       RTC->CR &= (uint32_t)~RTC_CR_DCE;
01749     }
01750     /* Exit Initialization mode */
01751     RTC_ExitInitMode();
01752
01753     status = SUCCESS;
01754   }
01755
01756   /* Enable the write protection for RTC registers */
01757   RTC->WPR = 0xFF;
01758
01759   return status;
01760 }
01761
01762 /**
01763   * @brief  Enables or disables the RTC clock to be output through the relative
01764   *         pin.
01765   * @param  NewState: new state of the coarse calibration Output.
01766   *   This parameter can be: ENABLE or DISABLE.
01767   * @retval None
01768   */
01769 void RTC_CalibOutputCmd(FunctionalState NewState)
01770 {
01771   /* Check the parameters */
01772   assert_param(IS_FUNCTIONAL_STATE(NewState));
01773
01774   /* Disable the write protection for RTC registers */
01775   RTC->WPR = 0xCA;
01776   RTC->WPR = 0x53;
01777
01778   if (NewState != DISABLE)
01779   {
01780     /* Enable the RTC clock output */
01781     RTC->CR |= (uint32_t)RTC_CR_COE;
01782   }
01783   else
01784   {
01785     /* Disable the RTC clock output */
01786     RTC->CR &= (uint32_t)~RTC_CR_COE;
01787   }
01788
01789   /* Enable the write protection for RTC registers */
01790   RTC->WPR = 0xFF;
01791 }
01792
01793 /**
01794   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01795   * @param  RTC_CalibOutput : Select the Calibration output Selection .
01796   *   This parameter can be one of the following values:
01797   *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
01798   *     @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
01799   * @retval None
01800 */
01801 void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
01802 {
01803   /* Check the parameters */
01804   assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
01805
01806   /* Disable the write protection for RTC registers */
01807   RTC->WPR = 0xCA;
01808   RTC->WPR = 0x53;
01809
01810   /*clear flags before config*/
01811   RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
01812
01813   /* Configure the RTC_CR register */
01814   RTC->CR |= (uint32_t)RTC_CalibOutput;
01815
01816   /* Enable the write protection for RTC registers */
01817   RTC->WPR = 0xFF;
01818 }
01819
01820 /**
01821   * @brief  Configures the Smooth Calibration Settings.
01822   * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
01823   *   This parameter can be can be one of the following values:
01824   *     @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
01825   *     @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
01826   *     @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
01827   * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
01828   *   This parameter can be one of the following values:
01829   *     @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
01830   *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
01831   * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
01832   *   This parameter can be one any value from 0 to 0x000001FF.
01833   * @retval An ErrorStatus enumeration value:
01834   *          - SUCCESS: RTC Calib registers are configured
01835   *          - ERROR: RTC Calib registers are not configured
01836 */
01837 ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
01838                                   uint32_t RTC_SmoothCalibPlusPulses,
01839                                   uint32_t RTC_SmouthCalibMinusPulsesValue)
01840 {
01841   ErrorStatus status = ERROR;
01842   uint32_t recalpfcount = 0;
01843
01844   /* Check the parameters */
01845   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
01846   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
01847   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
01848
01849   /* Disable the write protection for RTC registers */
01850   RTC->WPR = 0xCA;
01851   RTC->WPR = 0x53;
01852
01853   /* check if a calibration is pending*/
01854   if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
01855   {
01856     /* wait until the Calibration is completed*/
01857     while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
01858     {
01859       recalpfcount++;
01860     }
01861   }
01862
01863   /* check if the calibration pending is completed or if there is no calibration operation at all*/
01864   if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
01865   {
01866     /* Configure the Smooth calibration settings */
01867     RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
01868
01869     status = SUCCESS;
01870   }
01871   else
01872   {
01873     status = ERROR;
01874   }
01875
01876   /* Enable the write protection for RTC registers */
01877   RTC->WPR = 0xFF;
01878
01879   return (ErrorStatus)(status);
01880 }
01881
01882 /**
01883   * @}
01884   */
01885
01886
01887 /** @defgroup RTC_Group8 TimeStamp configuration functions
01888  *  @brief   TimeStamp configuration functions
01889  *
01890 @verbatim
01891  ===============================================================================
01892                  ##### TimeStamp configuration functions #####
01893  ===============================================================================
01894
01895 @endverbatim
01896   * @{
01897   */
01898
01899 /**
01900   * @brief  Enables or Disables the RTC TimeStamp functionality with the
01901   *         specified time stamp pin stimulating edge.
01902   * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
01903   *         activated.
01904   *   This parameter can be one of the following:
01905   *     @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
01906   *                                    edge of the related pin.
01907   *     @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
01908   *                                     falling edge of the related pin.
01909   * @param  NewState: new state of the TimeStamp.
01910   *   This parameter can be: ENABLE or DISABLE.
01911   * @retval None
01912   */
01913 void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
01914 {
01915   uint32_t tmpreg = 0;
01916
01917   /* Check the parameters */
01918   assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
01919   assert_param(IS_FUNCTIONAL_STATE(NewState));
01920
01921   /* Get the RTC_CR register and clear the bits to be configured */
01922   tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
01923
01924   /* Get the new configuration */
01925   if (NewState != DISABLE)
01926   {
01927     tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
01928   }
01929   else
01930   {
01931     tmpreg |= (uint32_t)(RTC_TimeStampEdge);
01932   }
01933
01934   /* Disable the write protection for RTC registers */
01935   RTC->WPR = 0xCA;
01936   RTC->WPR = 0x53;
01937
01938   /* Configure the Time Stamp TSEDGE and Enable bits */
01939   RTC->CR = (uint32_t)tmpreg;
01940
01941   /* Enable the write protection for RTC registers */
01942   RTC->WPR = 0xFF;
01943 }
01944
01945 /**
01946   * @brief  Get the RTC TimeStamp value and masks.
01947   * @param  RTC_Format: specifies the format of the output parameters.
01948   *   This parameter can be one of the following values:
01949   *     @arg RTC_Format_BIN: Binary data format
01950   *     @arg RTC_Format_BCD: BCD data format
01951   * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
01952   *                             contains the TimeStamp time values.
01953   * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
01954   *                             contains the TimeStamp date values.
01955   * @retval None
01956   */
01957 void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
01958                                       RTC_DateTypeDef* RTC_StampDateStruct)
01959 {
01960   uint32_t tmptime = 0, tmpdate = 0;
01961
01962   /* Check the parameters */
01963   assert_param(IS_RTC_FORMAT(RTC_Format));
01964
01965   /* Get the TimeStamp time and date registers values */
01966   tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
01967   tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
01968
01969   /* Fill the Time structure fields with the read parameters */
01970   RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
01971   RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
01972   RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
01973   RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
01974
01975   /* Fill the Date structure fields with the read parameters */
01976   RTC_StampDateStruct->RTC_Year = 0;
01977   RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
01978   RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
01979   RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
01980
01981   /* Check the input parameters format */
01982   if (RTC_Format == RTC_Format_BIN)
01983   {
01984     /* Convert the Time structure parameters to Binary format */
01985     RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
01986     RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
01987     RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
01988
01989     /* Convert the Date structure parameters to Binary format */
01990     RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
01991     RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
01992     RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
01993   }
01994 }
01995
01996 /**
01997   * @brief  Get the RTC timestamp Subseconds value.
01998   * @param  None
01999   * @retval RTC current timestamp Subseconds value.
02000   */
02001 uint32_t RTC_GetTimeStampSubSecond(void)
02002 {
02003   /* Get timestamp subseconds values from the correspondent registers */
02004   return (uint32_t)(RTC->TSSSR);
02005 }
02006
02007 /**
02008   * @}
02009   */
02010
02011 /** @defgroup RTC_Group9 Tampers configuration functions
02012  *  @brief   Tampers configuration functions
02013  *
02014 @verbatim
02015  ===============================================================================
02016                  ##### Tampers configuration functions #####
02017  ===============================================================================
02018
02019 @endverbatim
02020   * @{
02021   */
02022
02023 /**
02024   * @brief  Configures the select Tamper pin edge.
02025   * @param  RTC_Tamper: Selected tamper pin.
02026   *   This parameter can be any combination of the following values:
02027   *     @arg RTC_Tamper_1: Select Tamper 1.
02028   *     @arg RTC_Tamper_2: Select Tamper 2.
02029   *     @arg RTC_Tamper_3: Select Tamper 3.
02030   * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that
02031   *                            stimulates tamper event.
02032   *   This parameter can be one of the following values:
02033   *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
02034   *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
02035   *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
02036   *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
02037   * @retval None
02038   */
02039 void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
02040 {
02041   /* Check the parameters */
02042   assert_param(IS_RTC_TAMPER(RTC_Tamper));
02043   assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
02044
02045   /* Check if the  active level for Tamper is rising edge (Low level)*/
02046   if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
02047   {
02048     /* Configure the RTC_TAFCR register */
02049     RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
02050   }
02051   else
02052   {
02053     /* Configure the RTC_TAFCR register */
02054     RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
02055   }
02056 }
02057
02058 /**
02059   * @brief  Enables or Disables the Tamper detection.
02060   * @param  RTC_Tamper: Selected tamper pin.
02061   *   This parameter can be any combination of the following values:
02062   *     @arg RTC_Tamper_1: Select Tamper 1.
02063   *     @arg RTC_Tamper_2: Select Tamper 2.
02064   *     @arg RTC_Tamper_3: Select Tamper 3.
02065   * @param  NewState: new state of the tamper pin.
02066   *         This parameter can be: ENABLE or DISABLE.
02067   * @retval None
02068   */
02069 void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
02070 {
02071   /* Check the parameters */
02072   assert_param(IS_RTC_TAMPER(RTC_Tamper));
02073   assert_param(IS_FUNCTIONAL_STATE(NewState));
02074
02075   if (NewState != DISABLE)
02076   {
02077     /* Enable the selected Tamper pin */
02078     RTC->TAFCR |= (uint32_t)RTC_Tamper;
02079   }
02080   else
02081   {
02082     /* Disable the selected Tamper pin */
02083     RTC->TAFCR &= (uint32_t)~RTC_Tamper;
02084   }
02085 }
02086
02087 /**
02088   * @brief  Configures the Tampers Filter.
02089   * @param  RTC_TamperFilter: Specifies the tampers filter.
02090   *   This parameter can be one of the following values:
02091   *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
02092   *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
02093   *                                    samples at the active level.
02094   *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
02095   *                                    samples at the active level.
02096   *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
02097   *                                    samples at the active level.
02098   * @retval None
02099   */
02100 void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
02101 {
02102   /* Check the parameters */
02103   assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
02104
02105   /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
02106   RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
02107
02108   /* Configure the RTC_TAFCR register */
02109   RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
02110 }
02111
02112 /**
02113   * @brief  Configures the Tampers Sampling Frequency.
02114   * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
02115   *   This parameter can be one of the following values:
02116   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
02117   *                                           with a frequency =  RTCCLK / 32768
02118   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
02119   *                                           with a frequency =  RTCCLK / 16384
02120   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
02121   *                                           with a frequency =  RTCCLK / 8192
02122   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
02123   *                                           with a frequency =  RTCCLK / 4096
02124   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
02125   *                                           with a frequency =  RTCCLK / 2048
02126   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
02127   *                                           with a frequency =  RTCCLK / 1024
02128   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
02129   *                                           with a frequency =  RTCCLK / 512
02130   *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
02131   *                                           with a frequency =  RTCCLK / 256
02132   * @retval None
02133   */
02134 void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
02135 {
02136   /* Check the parameters */
02137   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
02138
02139   /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
02140   RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
02141
02142   /* Configure the RTC_TAFCR register */
02143   RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
02144 }
02145
02146 /**
02147   * @brief  Configures the Tampers Pins input Precharge Duration.
02148   * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
02149   *         Precharge Duration.
02150   *   This parameter can be one of the following values:
02151   *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
02152   *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
02153   *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
02154   *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
02155   * @retval None
02156   */
02157 void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
02158 {
02159   /* Check the parameters */
02160   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
02161
02162   /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
02163   RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
02164
02165   /* Configure the RTC_TAFCR register */
02166   RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
02167 }
02168
02169 /**
02170   * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
02171   * @note   The timestamp is valid even the TSE bit in tamper control register
02172   *         is reset.
02173   * @param  NewState: new state of the timestamp on tamper event.
02174   *         This parameter can be: ENABLE or DISABLE.
02175   * @retval None
02176   */
02177 void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
02178 {
02179   /* Check the parameters */
02180   assert_param(IS_FUNCTIONAL_STATE(NewState));
02181
02182   if (NewState != DISABLE)
02183   {
02184     /* Save timestamp on tamper detection event */
02185     RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
02186   }
02187   else
02188   {
02189     /* Tamper detection does not cause a timestamp to be saved */
02190     RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
02191   }
02192 }
02193
02194 /**
02195   * @brief  Enables or Disables the Precharge of Tamper pin.
02196   * @param  NewState: new state of tamper pull up.
02197   *   This parameter can be: ENABLE or DISABLE.
02198   * @retval None
02199   */
02200 void RTC_TamperPullUpCmd(FunctionalState NewState)
02201 {
02202   /* Check the parameters */
02203   assert_param(IS_FUNCTIONAL_STATE(NewState));
02204
02205  if (NewState != DISABLE)
02206   {
02207     /* Enable precharge of the selected Tamper pin */
02208     RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
02209   }
02210   else
02211   {
02212     /* Disable precharge of the selected Tamper pin */
02213     RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
02214   }
02215 }
02216
02217 /**
02218   * @}
02219   */
02220
02221 /** @defgroup RTC_Group10 Backup Data Registers configuration functions
02222  *  @brief   Backup Data Registers configuration functions
02223  *
02224 @verbatim
02225  ===============================================================================
02226           ##### Backup Data Registers configuration functions #####
02227  ===============================================================================
02228
02229 @endverbatim
02230   * @{
02231   */
02232
02233 /**
02234   * @brief  Writes a data in a specified RTC Backup data register.
02235   * @param  RTC_BKP_DR: RTC Backup data Register number.
02236   *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
02237   *                          specify the register.
02238   * @param  Data: Data to be written in the specified RTC Backup data register.
02239   * @retval None
02240   */
02241 void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
02242 {
02243   __IO uint32_t tmp = 0;
02244
02245   /* Check the parameters */
02246   assert_param(IS_RTC_BKP(RTC_BKP_DR));
02247
02248   tmp = RTC_BASE + 0x50;
02249   tmp += (RTC_BKP_DR * 4);
02250
02251   /* Write the specified register */
02252   *(__IO uint32_t *)tmp = (uint32_t)Data;
02253 }
02254
02255 /**
02256   * @brief  Reads data from the specified RTC Backup data Register.
02257   * @param  RTC_BKP_DR: RTC Backup data Register number.
02258   *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
02259   *                          specify the register.
02260   * @retval None
02261   */
02262 uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
02263 {
02264   __IO uint32_t tmp = 0;
02265
02266   /* Check the parameters */
02267   assert_param(IS_RTC_BKP(RTC_BKP_DR));
02268
02269   tmp = RTC_BASE + 0x50;
02270   tmp += (RTC_BKP_DR * 4);
02271
02272   /* Read the specified register */
02273   return (*(__IO uint32_t *)tmp);
02274 }
02275
02276 /**
02277   * @}
02278   */
02279
02280 /** @defgroup RTC_Group11 Output Type Config configuration functions
02281  *  @brief   Output Type Config configuration functions
02282  *
02283 @verbatim
02284  ===============================================================================
02285              ##### Output Type Config configuration functions #####
02286  ===============================================================================
02287
02288 @endverbatim
02289   * @{
02290   */
02291
02292 /**
02293   * @brief  Configures the RTC Output Pin mode.
02294   * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
02295   *   This parameter can be one of the following values:
02296   *     @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
02297   *                                    Open Drain mode.
02298   *     @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in
02299   *                                    Push Pull mode.
02300   * @retval None
02301   */
02302 void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
02303 {
02304   /* Check the parameters */
02305   assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
02306
02307   RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
02308   RTC->TAFCR |= (uint32_t)(RTC_OutputType);
02309 }
02310
02311 /**
02312   * @}
02313   */
02314
02315 /** @defgroup RTC_Group12 Shift control synchronisation functions
02316  *  @brief   Shift control synchronisation functions
02317  *
02318 @verbatim
02319  ===============================================================================
02320             ##### Shift control synchronisation functions #####
02321  ===============================================================================
02322
02323 @endverbatim
02324   * @{
02325   */
02326
02327 /**
02328   * @brief  Configures the Synchronization Shift Control Settings.
02329   * @note   When REFCKON is set, firmware must not write to Shift control register
02330   * @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
02331   *   This parameter can be one of the following values :
02332   *     @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
02333   *     @arg RTC_ShiftAdd1S_Reset: No effect.
02334   * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
02335   *         This parameter can be one any value from 0 to 0x7FFF.
02336   * @retval An ErrorStatus enumeration value:
02337   *          - SUCCESS: RTC Shift registers are configured
02338   *          - ERROR: RTC Shift registers are not configured
02339 */
02340 ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
02341 {
02342   ErrorStatus status = ERROR;
02343   uint32_t shpfcount = 0;
02344
02345   /* Check the parameters */
02346   assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
02347   assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
02348
02349   /* Disable the write protection for RTC registers */
02350   RTC->WPR = 0xCA;
02351   RTC->WPR = 0x53;
02352
02353   /* Check if a Shift is pending*/
02354   if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
02355   {
02356     /* Wait until the shift is completed*/
02357     while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
02358     {
02359       shpfcount++;
02360     }
02361   }
02362
02363   /* Check if the Shift pending is completed or if there is no Shift operation at all*/
02364   if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
02365   {
02366     /* check if the reference clock detection is disabled */
02367     if((RTC->CR & RTC_CR_REFCKON) == RESET)
02368     {
02369       /* Configure the Shift settings */
02370       RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
02371
02372       if(RTC_WaitForSynchro() == ERROR)
02373       {
02374         status = ERROR;
02375       }
02376       else
02377       {
02378         status = SUCCESS;
02379       }
02380     }
02381     else
02382     {
02383       status = ERROR;
02384     }
02385   }
02386   else
02387   {
02388     status = ERROR;
02389   }
02390
02391   /* Enable the write protection for RTC registers */
02392   RTC->WPR = 0xFF;
02393
02394   return (ErrorStatus)(status);
02395 }
02396
02397 /**
02398   * @}
02399   */
02400
02401 /** @defgroup RTC_Group13 Interrupts and flags management functions
02402  *  @brief   Interrupts and flags management functions
02403  *
02404 @verbatim
02405  ===============================================================================
02406             ##### Interrupts and flags management functions #####
02407  ===============================================================================
02408     [..] All RTC interrupts are connected to the EXTI controller.
02409          (+) To enable the RTC Alarm interrupt, the following sequence is required:
02410          (+) Configure and enable the EXTI Line 17 in interrupt mode and select
02411              the rising edge sensitivity using the EXTI_Init() function.
02412          (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
02413              the NVIC_Init() function.
02414          (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
02415              using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
02416
02417          (+) To enable the RTC Wakeup interrupt, the following sequence is required:
02418          (+) Configure and enable the EXTI Line 20 in interrupt mode and select
02419              the rising edge sensitivity using the EXTI_Init() function.
02420          (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
02421              NVIC_Init() function.
02422          (+) Configure the RTC to generate the RTC wakeup timer event using the
02423              RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
02424              functions.
02425
02426          (+) To enable the RTC Tamper interrupt, the following sequence is required:
02427          (+) Configure and enable the EXTI Line 19 in interrupt mode and select
02428              the rising edge sensitivity using the EXTI_Init() function.
02429          (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
02430              the NVIC_Init() function.
02431          (+) Configure the RTC to detect the RTC tamper event using the
02432              RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
02433
02434          (+) To enable the RTC TimeStamp interrupt, the following sequence is
02435              required:
02436          (+) Configure and enable the EXTI Line 19 in interrupt mode and select
02437              the rising edge sensitivity using the EXTI_Init() function.
02438          (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
02439              the NVIC_Init() function.
02440          (+) Configure the RTC to detect the RTC time-stamp event using the
02441              RTC_TimeStampCmd() functions.
02442
02443 @endverbatim
02444   * @{
02445   */
02446
02447 /**
02448   * @brief  Enables or disables the specified RTC interrupts.
02449   * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
02450   *   This parameter can be any combination of the following values:
02451   *     @arg RTC_IT_TS:  Time Stamp interrupt mask.
02452   *     @arg RTC_IT_WUT:  WakeUp Timer interrupt mask.
02453   *     @arg RTC_IT_ALRB:  Alarm B interrupt mask.
02454   *     @arg RTC_IT_ALRA:  Alarm A interrupt mask.
02455   *     @arg RTC_IT_TAMP: Tamper event interrupt mask.
02456   * @param  NewState: new state of the specified RTC interrupts.
02457   *   This parameter can be: ENABLE or DISABLE.
02458   * @retval None
02459   */
02460 void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
02461 {
02462   /* Check the parameters */
02463   assert_param(IS_RTC_CONFIG_IT(RTC_IT));
02464   assert_param(IS_FUNCTIONAL_STATE(NewState));
02465
02466   /* Disable the write protection for RTC registers */
02467   RTC->WPR = 0xCA;
02468   RTC->WPR = 0x53;
02469
02470   if (NewState != DISABLE)
02471   {
02472     /* Configure the Interrupts in the RTC_CR register */
02473     RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
02474     /* Configure the Tamper Interrupt in the RTC_TAFCR */
02475     RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
02476   }
02477   else
02478   {
02479     /* Configure the Interrupts in the RTC_CR register */
02480     RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
02481     /* Configure the Tamper Interrupt in the RTC_TAFCR */
02482     RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
02483   }
02484   /* Enable the write protection for RTC registers */
02485   RTC->WPR = 0xFF;
02486 }
02487
02488 /**
02489   * @brief  Checks whether the specified RTC flag is set or not.
02490   * @param  RTC_FLAG: specifies the flag to check.
02491   *   This parameter can be one of the following values:
02492   *     @arg RTC_FLAG_RECALPF: RECALPF event flag.
02493   *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
02494   *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
02495   *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
02496   *     @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag.
02497   *     @arg RTC_FLAG_TSF: Time Stamp event flag.
02498   *     @arg RTC_FLAG_WUTF: WakeUp Timer flag.
02499   *     @arg RTC_FLAG_ALRBF: Alarm B flag.
02500   *     @arg RTC_FLAG_ALRAF: Alarm A flag.
02501   *     @arg RTC_FLAG_INITF: Initialization mode flag.
02502   *     @arg RTC_FLAG_RSF: Registers Synchronized flag.
02503   *     @arg RTC_FLAG_INITS: Registers Configured flag.
02504   *     @argRTC_FLAG_SHPF: Shift operation pending flag.
02505   *     @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag.
02506   *     @arg RTC_FLAG_ALRBWF: Alarm B Write flag.
02507   *     @arg RTC_FLAG_ALRAWF: Alarm A write flag.
02508   * @retval The new state of RTC_FLAG (SET or RESET).
02509   */
02510 FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
02511 {
02512   FlagStatus bitstatus = RESET;
02513   uint32_t tmpreg = 0;
02514
02515   /* Check the parameters */
02516   assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
02517
02518   /* Get all the flags */
02519   tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
02520
02521   /* Return the status of the flag */
02522   if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
02523   {
02524     bitstatus = SET;
02525   }
02526   else
02527   {
02528     bitstatus = RESET;
02529   }
02530   return bitstatus;
02531 }
02532
02533 /**
02534   * @brief  Clears the RTC's pending flags.
02535   * @param  RTC_FLAG: specifies the RTC flag to clear.
02536   *   This parameter can be any combination of the following values:
02537   *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
02538   *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
02539   *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
02540   *     @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag.
02541   *     @arg RTC_FLAG_TSF: Time Stamp event flag.
02542   *     @arg RTC_FLAG_WUTF: WakeUp Timer flag.
02543   *     @arg RTC_FLAG_ALRBF: Alarm B flag.
02544   *     @arg RTC_FLAG_ALRAF: Alarm A flag.
02545   *     @arg RTC_FLAG_RSF: Registers Synchronized flag.
02546   * @retval None
02547   */
02548 void RTC_ClearFlag(uint32_t RTC_FLAG)
02549 {
02550   /* Check the parameters */
02551   assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
02552
02553   /* Clear the Flags in the RTC_ISR register */
02554   RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
02555 }
02556
02557 /**
02558   * @brief  Checks whether the specified RTC interrupt has occurred or not.
02559   * @param  RTC_IT: specifies the RTC interrupt source to check.
02560   *   This parameter can be one of the following values:
02561   *     @arg RTC_IT_TS: Time Stamp interrupt.
02562   *     @arg RTC_IT_WUT: WakeUp Timer interrupt.
02563   *     @arg RTC_IT_ALRB: Alarm B interrupt.
02564   *     @arg RTC_IT_ALRA: Alarm A interrupt.
02565   *     @arg RTC_IT_TAMP1: Tamper1 event interrupt.
02566   *     @arg RTC_IT_TAMP2: Tamper2 event interrupt.
02567   *     @arg RTC_IT_TAMP3: Tamper3 event interrupt.
02568   * @retval The new state of RTC_IT (SET or RESET).
02569   */
02570 ITStatus RTC_GetITStatus(uint32_t RTC_IT)
02571 {
02572   ITStatus bitstatus = RESET;
02573   uint32_t tmpreg = 0, enablestatus = 0;
02574
02575   /* Check the parameters */
02576   assert_param(IS_RTC_GET_IT(RTC_IT));
02577
02578   /* Get the TAMPER Interrupt enable bit and pending bit */
02579   tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
02580
02581   /* Get the Interrupt enable Status */
02582   enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
02583
02584   /* Get the Interrupt pending bit */
02585   tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
02586
02587   /* Get the status of the Interrupt */
02588   if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
02589   {
02590     bitstatus = SET;
02591   }
02592   else
02593   {
02594     bitstatus = RESET;
02595   }
02596   return bitstatus;
02597 }
02598
02599 /**
02600   * @brief  Clears the RTC's interrupt pending bits.
02601   * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
02602   *   This parameter can be any combination of the following values:
02603   *     @arg RTC_IT_TS: Time Stamp interrupt
02604   *     @arg RTC_IT_WUT: WakeUp Timer interrupt
02605   *     @arg RTC_IT_ALRB: Alarm B interrupt
02606   *     @arg RTC_IT_ALRA: Alarm A interrupt
02607   *     @arg RTC_IT_TAMP1: Tamper1 event interrupt
02608   *     @arg RTC_IT_TAMP2: Tamper2 event interrupt
02609   *     @arg RTC_IT_TAMP3: Tamper3 event interrupt
02610   * @retval None
02611   */
02612 void RTC_ClearITPendingBit(uint32_t RTC_IT)
02613 {
02614   uint32_t tmpreg = 0;
02615
02616   /* Check the parameters */
02617   assert_param(IS_RTC_CLEAR_IT(RTC_IT));
02618
02619   /* Get the RTC_ISR Interrupt pending bits mask */
02620   tmpreg = (uint32_t)(RTC_IT >> 4);
02621
02622   /* Clear the interrupt pending bits in the RTC_ISR register */
02623   RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
02624 }
02625
02626 /**
02627   * @}
02628   */
02629
02630 /**
02631   * @brief  Converts a 2 digit decimal to BCD format.
02632   * @param  Value: Byte to be converted.
02633   * @retval Converted byte
02634   */
02635 static uint8_t RTC_ByteToBcd2(uint8_t Value)
02636 {
02637   uint8_t bcdhigh = 0;
02638
02639   while (Value >= 10)
02640   {
02641     bcdhigh++;
02642     Value -= 10;
02643   }
02644
02645   return  ((uint8_t)(bcdhigh << 4) | Value);
02646 }
02647
02648 /**
02649   * @brief  Convert from 2 digit BCD to Binary.
02650   * @param  Value: BCD value to be converted.
02651   * @retval Converted word
02652   */
02653 static uint8_t RTC_Bcd2ToByte(uint8_t Value)
02654 {
02655   uint8_t tmp = 0;
02656   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
02657   return (tmp + (Value & (uint8_t)0x0F));
02658 }
02659
02660 /**
02661   * @}
02662   */
02663
02664 /**
02665   * @}
02666   */
02667
02668 /**
02669   * @}
02670   */
02671
02672 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_rtc.h Source File

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stm32l1xx_rtc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the RTC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_RTC_H
00028 #define __STM32L1xx_RTC_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup RTC
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  RTC Init structures definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
00053                              This parameter can be a value of @ref RTC_Hour_Formats */
00054
00055   uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
00056                              This parameter must be set to a value lower than 0x7F */
00057
00058   uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
00059                              This parameter must be set to a value lower than 0x7FFF */
00060 }RTC_InitTypeDef;
00061
00062 /**
00063   * @brief  RTC Time structure definition
00064   */
00065 typedef struct
00066 {
00067   uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
00068                         This parameter must be set to a value in the 0-12 range
00069                         if the RTC_HourFormat_12 is selected or 0-23 range if
00070                         the RTC_HourFormat_24 is selected. */
00071
00072   uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
00073                         This parameter must be set to a value in the 0-59 range. */
00074
00075   uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
00076                         This parameter must be set to a value in the 0-59 range. */
00077
00078   uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
00079                         This parameter can be a value of @ref RTC_AM_PM_Definitions */
00080 }RTC_TimeTypeDef;
00081
00082 /**
00083   * @brief  RTC Date structure definition
00084   */
00085 typedef struct
00086 {
00087   uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
00088                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
00089
00090   uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
00091                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
00092
00093   uint8_t RTC_Date;     /*!< Specifies the RTC Date.
00094                         This parameter must be set to a value in the 1-31 range. */
00095
00096   uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
00097                         This parameter must be set to a value in the 0-99 range. */
00098 }RTC_DateTypeDef;
00099
00100 /**
00101   * @brief  RTC Alarm structure definition
00102   */
00103 typedef struct
00104 {
00105   RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
00106
00107   uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00108                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00109
00110   uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00111                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00112
00113   uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00114                                      If the Alarm Date is selected, this parameter
00115                                      must be set to a value in the 1-31 range.
00116                                      If the Alarm WeekDay is selected, this
00117                                      parameter can be a value of @ref RTC_WeekDay_Definitions */
00118 }RTC_AlarmTypeDef;
00119
00120 /* Exported constants --------------------------------------------------------*/
00121
00122 /** @defgroup RTC_Exported_Constants
00123   * @{
00124   */
00125
00126
00127 /** @defgroup RTC_Hour_Formats
00128   * @{
00129   */
00130 #define RTC_HourFormat_24              ((uint32_t)0x00000000)
00131 #define RTC_HourFormat_12              ((uint32_t)0x00000040)
00132 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
00133                                         ((FORMAT) == RTC_HourFormat_24))
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup RTC_Asynchronous_Predivider
00139   * @{
00140   */
00141 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
00142
00143 /**
00144   * @}
00145   */
00146
00147
00148 /** @defgroup RTC_Synchronous_Predivider
00149   * @{
00150   */
00151 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup RTC_Time_Definitions
00158   * @{
00159   */
00160 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
00161 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
00162 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
00163 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
00164
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup RTC_AM_PM_Definitions
00170   * @{
00171   */
00172 #define RTC_H12_AM                     ((uint8_t)0x00)
00173 #define RTC_H12_PM                     ((uint8_t)0x40)
00174 #define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup RTC_Year_Date_Definitions
00181   * @{
00182   */
00183 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
00184
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup RTC_Month_Date_Definitions
00190   * @{
00191   */
00192
00193 /* Coded in BCD format */
00194 #define RTC_Month_January              ((uint8_t)0x01)
00195 #define RTC_Month_February             ((uint8_t)0x02)
00196 #define RTC_Month_March                ((uint8_t)0x03)
00197 #define RTC_Month_April                ((uint8_t)0x04)
00198 #define RTC_Month_May                  ((uint8_t)0x05)
00199 #define RTC_Month_June                 ((uint8_t)0x06)
00200 #define RTC_Month_July                 ((uint8_t)0x07)
00201 #define RTC_Month_August               ((uint8_t)0x08)
00202 #define RTC_Month_September            ((uint8_t)0x09)
00203 #define RTC_Month_October              ((uint8_t)0x10)
00204 #define RTC_Month_November             ((uint8_t)0x11)
00205 #define RTC_Month_December             ((uint8_t)0x12)
00206 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
00207 #define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
00208
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RTC_WeekDay_Definitions
00214   * @{
00215   */
00216
00217 #define RTC_Weekday_Monday             ((uint8_t)0x01)
00218 #define RTC_Weekday_Tuesday            ((uint8_t)0x02)
00219 #define RTC_Weekday_Wednesday          ((uint8_t)0x03)
00220 #define RTC_Weekday_Thursday           ((uint8_t)0x04)
00221 #define RTC_Weekday_Friday             ((uint8_t)0x05)
00222 #define RTC_Weekday_Saturday           ((uint8_t)0x06)
00223 #define RTC_Weekday_Sunday             ((uint8_t)0x07)
00224 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
00225                                  ((WEEKDAY) == RTC_Weekday_Tuesday) || \
00226                                  ((WEEKDAY) == RTC_Weekday_Wednesday) || \
00227                                  ((WEEKDAY) == RTC_Weekday_Thursday) || \
00228                                  ((WEEKDAY) == RTC_Weekday_Friday) || \
00229                                  ((WEEKDAY) == RTC_Weekday_Saturday) || \
00230                                  ((WEEKDAY) == RTC_Weekday_Sunday))
00231 /**
00232   * @}
00233   */
00234
00235
00236 /** @defgroup RTC_Alarm_Definitions
00237   * @{
00238   */
00239 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
00240 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
00241                                                     ((WEEKDAY) == RTC_Weekday_Tuesday) || \
00242                                                     ((WEEKDAY) == RTC_Weekday_Wednesday) || \
00243                                                     ((WEEKDAY) == RTC_Weekday_Thursday) || \
00244                                                     ((WEEKDAY) == RTC_Weekday_Friday) || \
00245                                                     ((WEEKDAY) == RTC_Weekday_Saturday) || \
00246                                                     ((WEEKDAY) == RTC_Weekday_Sunday))
00247
00248 /**
00249   * @}
00250   */
00251
00252
00253 /** @defgroup RTC_AlarmDateWeekDay_Definitions
00254   * @{
00255   */
00256 #define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
00257 #define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
00258
00259 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
00260                                             ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
00261
00262 /**
00263   * @}
00264   */
00265
00266
00267 /** @defgroup RTC_AlarmMask_Definitions
00268   * @{
00269   */
00270 #define RTC_AlarmMask_None                ((uint32_t)0x00000000)
00271 #define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
00272 #define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
00273 #define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
00274 #define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
00275 #define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
00276 #define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
00277
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup RTC_Alarms_Definitions
00283   * @{
00284   */
00285 #define RTC_Alarm_A                       ((uint32_t)0x00000100)
00286 #define RTC_Alarm_B                       ((uint32_t)0x00000200)
00287 #define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
00288 #define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
00295   * @{
00296   */
00297 #define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
00298                                                                        There is no comparison on sub seconds
00299                                                                        for Alarm */
00300 #define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
00301                                                                        comparison. Only SS[0] is compared. */
00302 #define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
00303                                                                        comparison. Only SS[1:0] are compared */
00304 #define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
00305                                                                        comparison. Only SS[2:0] are compared */
00306 #define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
00307                                                                        comparison. Only SS[3:0] are compared */
00308 #define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
00309                                                                        comparison. Only SS[4:0] are compared */
00310 #define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
00311                                                                        comparison. Only SS[5:0] are compared */
00312 #define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
00313                                                                        comparison. Only SS[6:0] are compared */
00314 #define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
00315                                                                        comparison. Only SS[7:0] are compared */
00316 #define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
00317                                                                        comparison. Only SS[8:0] are compared */
00318 #define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
00319                                                                        comparison. Only SS[9:0] are compared */
00320 #define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
00321                                                                        comparison. Only SS[10:0] are compared */
00322 #define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
00323                                                                        comparison.Only SS[11:0] are compared */
00324 #define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
00325                                                                        comparison. Only SS[12:0] are compared */
00326 #define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
00327                                                                        comparison.Only SS[13:0] are compared */
00328 #define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
00329                                                                        to activate alarm. */
00330 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
00331                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
00332                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
00333                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
00334                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
00335                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
00336                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
00337                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
00338                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
00339                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
00340                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
00341                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
00342                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
00343                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
00344                                               ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
00345                                               ((MASK) == RTC_AlarmSubSecondMask_None))
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup RTC_Alarm_Sub_Seconds_Value
00351   * @{
00352   */
00353
00354 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
00355
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup RTC_Wakeup_Timer_Definitions
00361   * @{
00362   */
00363 #define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
00364 #define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
00365 #define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
00366 #define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
00367 #define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
00368 #define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
00369 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
00370                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
00371                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
00372                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
00373                                     ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
00374                                     ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
00375 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup RTC_Time_Stamp_Edges_definitions
00381   * @{
00382   */
00383 #define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
00384 #define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
00385 #define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
00386                                      ((EDGE) == RTC_TimeStampEdge_Falling))
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup RTC_Output_selection_Definitions
00392   * @{
00393   */
00394 #define RTC_Output_Disable             ((uint32_t)0x00000000)
00395 #define RTC_Output_AlarmA              ((uint32_t)0x00200000)
00396 #define RTC_Output_AlarmB              ((uint32_t)0x00400000)
00397 #define RTC_Output_WakeUp              ((uint32_t)0x00600000)
00398
00399 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
00400                                ((OUTPUT) == RTC_Output_AlarmA) || \
00401                                ((OUTPUT) == RTC_Output_AlarmB) || \
00402                                ((OUTPUT) == RTC_Output_WakeUp))
00403
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup RTC_Output_Polarity_Definitions
00409   * @{
00410   */
00411 #define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
00412 #define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
00413 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
00414                                 ((POL) == RTC_OutputPolarity_Low))
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup RTC_Coarse_Calibration_Definitions
00420   * @{
00421   */
00422 #define RTC_CalibSign_Positive            ((uint32_t)0x00000000)
00423 #define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
00424 #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
00425                                  ((SIGN) == RTC_CalibSign_Negative))
00426 #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
00427
00428 /**
00429   * @}
00430   */
00431
00432  /** @defgroup RTC_Calib_Output_selection_Definitions
00433   * @{
00434   */
00435 #define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000)
00436 #define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
00437 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
00438                                       ((OUTPUT) == RTC_CalibOutput_1Hz))
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup RTC_Smooth_calib_period_Definitions
00444   * @{
00445   */
00446 #define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
00447                                                              period is 32s,  else 2exp20 RTCCLK seconds */
00448 #define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
00449                                                              period is 16s, else 2exp19 RTCCLK seconds */
00450 #define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
00451                                                              period is 8s, else 2exp18 RTCCLK seconds */
00452 #define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
00453                                              ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
00454                                              ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
00455
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
00461   * @{
00462   */
00463 #define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added
00464                                                                 during a X -second window = Y - CALM[8:0].
00465                                                                  with Y = 512, 256, 128 when X = 32, 16, 8 */
00466 #define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
00467                                                                  during a 32-second window =   CALM[8:0]. */
00468 #define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
00469                                          ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
00470
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
00476   * @{
00477   */
00478 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
00479
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup RTC_DayLightSaving_Definitions
00485   * @{
00486   */
00487 #define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
00488 #define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
00489 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
00490                                       ((SAVE) == RTC_DayLightSaving_ADD1H))
00491
00492 #define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
00493 #define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
00494 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
00495                                            ((OPERATION) == RTC_StoreOperation_Set))
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup RTC_Tamper_Trigger_Definitions
00501   * @{
00502   */
00503 #define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
00504 #define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
00505 #define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
00506 #define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
00507 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
00508                                         ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
00509                                         ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
00510                                         ((TRIGGER) == RTC_TamperTrigger_HighLevel))
00511
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup RTC_Tamper_Filter_Definitions
00517   * @{
00518   */
00519 #define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
00520
00521 #define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2
00522                                                           consecutive samples at the active level */
00523 #define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4
00524                                                           consecutive samples at the active level */
00525 #define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8
00526                                                           consecutive samples at the active leve. */
00527 #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
00528                                       ((FILTER) == RTC_TamperFilter_2Sample) || \
00529                                       ((FILTER) == RTC_TamperFilter_4Sample) || \
00530                                       ((FILTER) == RTC_TamperFilter_8Sample))
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
00536   * @{
00537   */
00538 #define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
00539                                                                            with a frequency =  RTCCLK / 32768 */
00540 #define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
00541                                                                             with a frequency =  RTCCLK / 16384 */
00542 #define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
00543                                                                            with a frequency =  RTCCLK / 8192  */
00544 #define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
00545                                                                            with a frequency =  RTCCLK / 4096  */
00546 #define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
00547                                                                            with a frequency =  RTCCLK / 2048  */
00548 #define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
00549                                                                            with a frequency =  RTCCLK / 1024  */
00550 #define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
00551                                                                            with a frequency =  RTCCLK / 512   */
00552 #define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
00553                                                                            with a frequency =  RTCCLK / 256   */
00554 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
00555                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
00556                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
00557                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
00558                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
00559                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
00560                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
00561                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
00562
00563 /**
00564   * @}
00565   */
00566
00567   /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
00568   * @{
00569   */
00570 #define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
00571                                                                          sampling during 1 RTCCLK cycle */
00572 #define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
00573                                                                          sampling during 2 RTCCLK cycles */
00574 #define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
00575                                                                          sampling during 4 RTCCLK cycles */
00576 #define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
00577                                                                          sampling during 8 RTCCLK cycles */
00578
00579 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
00580                                                     ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
00581                                                     ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
00582                                                     ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup RTC_Tamper_Pins_Definitions
00588   * @{
00589   */
00590 #define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
00591                                                       input tamper 1 */
00592 #define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
00593                                                       input tamper 2 */
00594 #define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
00595                                                       input tamper 3 */
00596
00597 #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
00598
00599
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup RTC_Output_Type_ALARM_OUT
00605   * @{
00606   */
00607 #define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
00608 #define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
00609 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
00610                                   ((TYPE) == RTC_OutputType_PushPull))
00611
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup RTC_Add_1_Second_Parameter_Definitions
00617   * @{
00618   */
00619 #define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
00620 #define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
00621 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
00622                                  ((SEL) == RTC_ShiftAdd1S_Set))
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup RTC_Substract_Fraction_Of_Second_Value
00628   * @{
00629   */
00630 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
00631
00632 /**
00633   * @}
00634   */
00635
00636 /** @defgroup RTC_Backup_Registers_Definitions
00637   * @{
00638   */
00639
00640 #define RTC_BKP_DR0                       ((uint32_t)0x00000000)
00641 #define RTC_BKP_DR1                       ((uint32_t)0x00000001)
00642 #define RTC_BKP_DR2                       ((uint32_t)0x00000002)
00643 #define RTC_BKP_DR3                       ((uint32_t)0x00000003)
00644 #define RTC_BKP_DR4                       ((uint32_t)0x00000004)
00645 #define RTC_BKP_DR5                       ((uint32_t)0x00000005)
00646 #define RTC_BKP_DR6                       ((uint32_t)0x00000006)
00647 #define RTC_BKP_DR7                       ((uint32_t)0x00000007)
00648 #define RTC_BKP_DR8                       ((uint32_t)0x00000008)
00649 #define RTC_BKP_DR9                       ((uint32_t)0x00000009)
00650 #define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
00651 #define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
00652 #define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
00653 #define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
00654 #define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
00655 #define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
00656 #define RTC_BKP_DR16                      ((uint32_t)0x00000010)
00657 #define RTC_BKP_DR17                      ((uint32_t)0x00000011)
00658 #define RTC_BKP_DR18                      ((uint32_t)0x00000012)
00659 #define RTC_BKP_DR19                      ((uint32_t)0x00000013)
00660 #define RTC_BKP_DR20                      ((uint32_t)0x00000014)
00661 #define RTC_BKP_DR21                      ((uint32_t)0x00000015)
00662 #define RTC_BKP_DR22                      ((uint32_t)0x00000016)
00663 #define RTC_BKP_DR23                      ((uint32_t)0x00000017)
00664 #define RTC_BKP_DR24                      ((uint32_t)0x00000018)
00665 #define RTC_BKP_DR25                      ((uint32_t)0x00000019)
00666 #define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
00667 #define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
00668 #define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
00669 #define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
00670 #define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
00671 #define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
00672 #define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
00673                                            ((BKP) == RTC_BKP_DR1) || \
00674                                            ((BKP) == RTC_BKP_DR2) || \
00675                                            ((BKP) == RTC_BKP_DR3) || \
00676                                            ((BKP) == RTC_BKP_DR4) || \
00677                                            ((BKP) == RTC_BKP_DR5) || \
00678                                            ((BKP) == RTC_BKP_DR6) || \
00679                                            ((BKP) == RTC_BKP_DR7) || \
00680                                            ((BKP) == RTC_BKP_DR8) || \
00681                                            ((BKP) == RTC_BKP_DR9) || \
00682                                            ((BKP) == RTC_BKP_DR10) || \
00683                                            ((BKP) == RTC_BKP_DR11) || \
00684                                            ((BKP) == RTC_BKP_DR12) || \
00685                                            ((BKP) == RTC_BKP_DR13) || \
00686                                            ((BKP) == RTC_BKP_DR14) || \
00687                                            ((BKP) == RTC_BKP_DR15) || \
00688                                            ((BKP) == RTC_BKP_DR16) || \
00689                                            ((BKP) == RTC_BKP_DR17) || \
00690                                            ((BKP) == RTC_BKP_DR18) || \
00691                                            ((BKP) == RTC_BKP_DR19) || \
00692                                            ((BKP) == RTC_BKP_DR20) || \
00693                                            ((BKP) == RTC_BKP_DR21) || \
00694                                            ((BKP) == RTC_BKP_DR22) || \
00695                                            ((BKP) == RTC_BKP_DR23) || \
00696                                            ((BKP) == RTC_BKP_DR24) || \
00697                                            ((BKP) == RTC_BKP_DR25) || \
00698                                            ((BKP) == RTC_BKP_DR26) || \
00699                                            ((BKP) == RTC_BKP_DR27) || \
00700                                            ((BKP) == RTC_BKP_DR28) || \
00701                                            ((BKP) == RTC_BKP_DR29) || \
00702                                            ((BKP) == RTC_BKP_DR30) || \
00703                                            ((BKP) == RTC_BKP_DR31))
00704 /**
00705   * @}
00706   */
00707
00708 /** @defgroup RTC_Input_parameter_format_definitions
00709   * @{
00710   */
00711 #define RTC_Format_BIN                    ((uint32_t)0x000000000)
00712 #define RTC_Format_BCD                    ((uint32_t)0x000000001)
00713 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
00714
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup RTC_Flags_Definitions
00720   * @{
00721   */
00722 #define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
00723 #define RTC_FLAG_TAMP3F                   ((uint32_t)0x00008000)
00724 #define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
00725 #define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
00726 #define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
00727 #define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
00728 #define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
00729 #define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
00730 #define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
00731 #define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
00732 #define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
00733 #define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
00734 #define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
00735 #define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
00736 #define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
00737 #define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
00738 #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
00739                                ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
00740                                ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
00741                                ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
00742                                ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
00743                                ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
00744                                 ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
00745                                 ((FLAG) == RTC_FLAG_SHPF))
00746 #define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
00747
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup RTC_Interrupts_Definitions
00753   * @{
00754   */
00755 #define RTC_IT_TS                         ((uint32_t)0x00008000)
00756 #define RTC_IT_WUT                        ((uint32_t)0x00004000)
00757 #define RTC_IT_ALRB                       ((uint32_t)0x00002000)
00758 #define RTC_IT_ALRA                       ((uint32_t)0x00001000)
00759 #define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
00760 #define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
00761 #define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
00762 #define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
00763
00764
00765 #define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
00766 #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_WUT) || \
00767                            ((IT) == RTC_IT_ALRB)  || ((IT) == RTC_IT_ALRA) || \
00768                            ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
00769                            ((IT) == RTC_IT_TAMP3))
00770 #define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
00771
00772 /**
00773   * @}
00774   */
00775
00776 /** @defgroup RTC_Legacy
00777   * @{
00778   */
00779 #define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
00780 #define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
00781
00782 /**
00783   * @}
00784   */
00785
00786 /**
00787   * @}
00788   */
00789
00790
00791 /* Exported macro ------------------------------------------------------------*/
00792 /* Exported functions ------------------------------------------------------- */
00793
00794 /*  Function used to set the RTC configuration to the default reset state *****/
00795 ErrorStatus RTC_DeInit(void);
00796
00797
00798 /* Initialization and Configuration functions *********************************/
00799 ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
00800 void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
00801 void RTC_WriteProtectionCmd(FunctionalState NewState);
00802 ErrorStatus RTC_EnterInitMode(void);
00803 void RTC_ExitInitMode(void);
00804 ErrorStatus RTC_WaitForSynchro(void);
00805 ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
00806 void RTC_BypassShadowCmd(FunctionalState NewState);
00807
00808 /* Time and Date configuration functions **************************************/
00809 ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
00810 void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
00811 void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
00812 uint32_t RTC_GetSubSecond(void);
00813 ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
00814 void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
00815 void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
00816
00817 /* Alarms (Alarm A and Alarm B) configuration functions  **********************/
00818 void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
00819 void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
00820 void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
00821 ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
00822 void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
00823 uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
00824
00825 /* WakeUp Timer configuration functions ***************************************/
00826 void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
00827 void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
00828 uint32_t RTC_GetWakeUpCounter(void);
00829 ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
00830
00831 /* Daylight Saving configuration functions ************************************/
00832 void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
00833 uint32_t RTC_GetStoreOperation(void);
00834
00835 /* Output pin Configuration function ******************************************/
00836 void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
00837
00838 /* Coarse and Smooth Calibration configuration functions **********************/
00839 ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
00840 ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
00841 void RTC_CalibOutputCmd(FunctionalState NewState);
00842 void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
00843 ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
00844                                   uint32_t RTC_SmoothCalibPlusPulses,
00845                                   uint32_t RTC_SmouthCalibMinusPulsesValue);
00846
00847 /* TimeStamp configuration functions ******************************************/
00848 void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
00849 void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
00850                                       RTC_DateTypeDef* RTC_StampDateStruct);
00851 uint32_t RTC_GetTimeStampSubSecond(void);
00852
00853 /* Tampers configuration functions ********************************************/
00854 void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
00855 void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
00856 void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
00857 void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
00858 void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
00859 void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
00860 void RTC_TamperPullUpCmd(FunctionalState NewState);
00861
00862 /* Backup Data Registers configuration functions ******************************/
00863 void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
00864 uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
00865
00866 /* Output Type Config configuration functions *********************************/
00867 void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
00868
00869 /* RTC_Shift_control_synchonisation_functions *********************************/
00870 ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
00871
00872 /* Interrupts and flags management functions **********************************/
00873 void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
00874 FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
00875 void RTC_ClearFlag(uint32_t RTC_FLAG);
00876 ITStatus RTC_GetITStatus(uint32_t RTC_IT);
00877 void RTC_ClearITPendingBit(uint32_t RTC_IT);
00878
00879 #ifdef __cplusplus
00880 }
00881 #endif
00882
00883 #endif /*__STM32L1xx_RTC_H */
00884
00885 /**
00886   * @}
00887   */
00888
00889 /**
00890   * @}
00891   */
00892
00893 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_sdio.c Source File

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stm32l1xx_sdio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_sdio.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the SDIO peripheral:
00009   *           + Initialization
00010   *           + Interrupts and flags management
00011   *
00012   *  @verbatim
00013   ==============================================================================
00014                          ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
00018        (PLLVCO) througth a fixed divider by 2.
00019        Before to start working with SDIO peripheral make sure that the PLLVCO is
00020        well configured to 96MHz.
00021        The SDIO peripheral uses two clock signals:
00022        (++) SDIO adapter clock (SDIOCLK = 48 MHz).
00023        (++) APB2 bus clock (PCLK2).
00024             PCLK2 and SDIO_CK clock frequencies must respect the following
00025             condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).
00026     (#) Enable peripheral clock using
00027         RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
00028     (#) According to the SDIO mode, enable the GPIO clocks using
00029         RCC_AHBPeriphClockCmd() function.
00030         The I/O can be one of the following configurations:
00031         (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
00032         (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
00033         (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
00034
00035     (#) Peripheral's alternate function:
00036         (++) Connect the pin to the desired peripherals' Alternate
00037              Function (AF) using GPIO_PinAFConfig() function.
00038         (++) Configure the desired pin in alternate function by:
00039              GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
00040         (++) Select the type, pull-up/pull-down and output speed via
00041              GPIO_PuPd, GPIO_OType and GPIO_Speed members.
00042         (++) Call GPIO_Init() function.
00043
00044     (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
00045         hardware, flow control and the Clock Divider using the SDIO_Init()
00046         function.
00047     (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
00048         function.
00049     (#) Enable the clock using the SDIO_ClockCmd() function.
00050     (#) Enable the NVIC and the corresponding interrupt using the function
00051         SDIO_ITConfig() if you need to use interrupt mode.
00052     (#) When using the DMA mode
00053         (++) Configure the DMA using DMA_Init() function.
00054         (++) Active the needed channel Request using SDIO_DMACmd() function.
00055     (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
00056     (#) To control the CPSM (Command Path State Machine) and send commands to the
00057         card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and
00058         SDIO_GetResponse() functions. First, user has to fill the command
00059         structure (pointer to SDIO_CmdInitTypeDef) according to the selected
00060         command to be sent. The parameters that should be filled are:
00061         (++) Command Argument.
00062         (++) Command Index.
00063         (++) Command Response type.
00064         (++) Command Wait.
00065         (++) CPSM Status (Enable or Disable).
00066         To check if the command is well received, read the SDIO_CMDRESP register
00067         using the SDIO_GetCommandResponse(). The SDIO responses registers
00068         (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function.
00069     (#) To control the DPSM (Data Path State Machine) and send/receive
00070         data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
00071         SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
00072
00073     *** Read Operations ***
00074     -----------------------
00075       [..]
00076       (#) First, user has to fill the data structure (pointer to
00077           SDIO_DataInitTypeDef) according to the selected data type to be received.
00078           The parameters that should be filled are:
00079           (++) Data TimeOut.
00080           (++) Data Length.
00081           (++) Data Block size.
00082           (++) Data Transfer direction: should be from card (To SDIO).
00083           (++) Data Transfer mode.
00084           (++) DPSM Status (Enable or Disable).
00085       (#) Configure the SDIO resources to receive the data from the card
00086           according to selected transfer mode (Refer to Step 8, 9 and 10).
00087       (#) Send the selected Read command (refer to step 11).
00088       (#) Use the SDIO flags/interrupts to check the transfer status.
00089
00090   *** Write Operations ***
00091   ------------------------
00092     [..]
00093     (#) First, user has to fill the data structure (pointer to
00094         SDIO_DataInitTypeDef) according to the selected data type to be received.
00095         The parameters that should be filled are:
00096         (++) Data TimeOut.
00097         (++) Data Length.
00098         (++) Data Block size.
00099         (++) Data Transfer direction:  should be to card (To CARD).
00100         (++) Data Transfer mode.
00101         (++) DPSM Status (Enable or Disable).
00102     (#) Configure the SDIO resources to send the data to the card
00103         according to selected transfer mode (Refer to Step 8, 9 and 10).
00104     (#) Send the selected Write command (refer to step 11).
00105     (#) Use the SDIO flags/interrupts to check the transfer status.
00106
00107   @endverbatim
00108   *
00109   ******************************************************************************
00110   * @attention
00111   *
00112   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00113   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00114   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00115   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00116   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00117   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00118   *
00119   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00120   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00121   *
00122   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00123   ******************************************************************************
00124   */
00125
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32l1xx_sdio.h"
00128 #include "stm32l1xx_rcc.h"
00129
00130 /** @addtogroup STM32L1xx_StdPeriph_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup SDIO
00135   * @brief SDIO driver modules
00136   * @{
00137   */
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141
00142 /* ------------ SDIO registers bit address in the alias region ----------- */
00143 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
00144
00145 /* --- CLKCR Register ---*/
00146
00147 /* Alias word address of CLKEN bit */
00148 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
00149 #define CLKEN_BitNumber           0x08
00150 #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
00151
00152 /* --- CMD Register ---*/
00153
00154 /* Alias word address of SDIOSUSPEND bit */
00155 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
00156 #define SDIOSUSPEND_BitNumber     0x0B
00157 #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
00158
00159 /* Alias word address of ENCMDCOMPL bit */
00160 #define ENCMDCOMPL_BitNumber      0x0C
00161 #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
00162
00163 /* Alias word address of NIEN bit */
00164 #define NIEN_BitNumber            0x0D
00165 #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
00166
00167 /* Alias word address of ATACMD bit */
00168 #define ATACMD_BitNumber          0x0E
00169 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
00170
00171 /* --- DCTRL Register ---*/
00172
00173 /* Alias word address of DMAEN bit */
00174 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
00175 #define DMAEN_BitNumber           0x03
00176 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
00177
00178 /* Alias word address of RWSTART bit */
00179 #define RWSTART_BitNumber         0x08
00180 #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
00181
00182 /* Alias word address of RWSTOP bit */
00183 #define RWSTOP_BitNumber          0x09
00184 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
00185
00186 /* Alias word address of RWMOD bit */
00187 #define RWMOD_BitNumber           0x0A
00188 #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
00189
00190 /* Alias word address of SDIOEN bit */
00191 #define SDIOEN_BitNumber          0x0B
00192 #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
00193
00194 /* ---------------------- SDIO registers bit mask ------------------------ */
00195
00196 /* --- CLKCR Register ---*/
00197
00198 /* CLKCR register clear mask */
00199 #define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100)
00200
00201 /* --- PWRCTRL Register ---*/
00202
00203 /* SDIO PWRCTRL Mask */
00204 #define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
00205
00206 /* --- DCTRL Register ---*/
00207
00208 /* SDIO DCTRL Clear Mask */
00209 #define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
00210
00211 /* --- CMD Register ---*/
00212
00213 /* CMD Register clear mask */
00214 #define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
00215
00216 /* SDIO RESP Registers Address */
00217 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
00218
00219 /* Private macro -------------------------------------------------------------*/
00220 /* Private variables ---------------------------------------------------------*/
00221 /* Private function prototypes -----------------------------------------------*/
00222 /* Private functions ---------------------------------------------------------*/
00223
00224 /** @defgroup SDIO_Private_Functions
00225   * @{
00226   */
00227
00228 /** @defgroup SDIO_Group1 Initialization and Configuration functions
00229  *  @brief   Initialization and Configuration functions
00230  *
00231  @verbatim
00232   ==============================================================================
00233               ##### Initialization and Configuration functions #####
00234   ==============================================================================
00235
00236 @endverbatim
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
00242   * @param  None
00243   * @retval None
00244   */
00245 void SDIO_DeInit(void)
00246 {
00247   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
00248   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
00249 }
00250
00251 /**
00252   * @brief  Initializes the SDIO peripheral according to the specified
00253   *   parameters in the SDIO_InitStruct.
00254   * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
00255   *   that contains the configuration information for the SDIO peripheral.
00256   * @retval None
00257   */
00258 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
00259 {
00260   uint32_t tmpreg = 0;
00261
00262   /* Check the parameters */
00263   assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
00264   assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
00265   assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
00266   assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
00267   assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
00268
00269 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
00270   /* Get the SDIO CLKCR value */
00271   tmpreg = SDIO->CLKCR;
00272
00273   /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
00274   tmpreg &= CLKCR_CLEAR_MASK;
00275
00276   /* Set CLKDIV bits according to SDIO_ClockDiv value */
00277   /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
00278   /* Set BYPASS bit according to SDIO_ClockBypass value */
00279   /* Set WIDBUS bits according to SDIO_BusWide value */
00280   /* Set NEGEDGE bits according to SDIO_ClockEdge value */
00281   /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
00282   tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
00283              SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
00284              SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
00285
00286   /* Write to SDIO CLKCR */
00287   SDIO->CLKCR = tmpreg;
00288 }
00289
00290 /**
00291   * @brief  Fills each SDIO_InitStruct member with its default value.
00292   * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
00293   *   will be initialized.
00294   * @retval None
00295   */
00296 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
00297 {
00298   /* SDIO_InitStruct members default value */
00299   SDIO_InitStruct->SDIO_ClockDiv = 0x00;
00300   SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
00301   SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
00302   SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
00303   SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
00304   SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00305 }
00306
00307 /**
00308   * @brief  Enables or disables the SDIO Clock.
00309   * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
00310   * @retval None
00311   */
00312 void SDIO_ClockCmd(FunctionalState NewState)
00313 {
00314   /* Check the parameters */
00315   assert_param(IS_FUNCTIONAL_STATE(NewState));
00316
00317   *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
00318 }
00319
00320 /**
00321   * @brief  Sets the power status of the controller.
00322   * @param  SDIO_PowerState: new state of the Power state.
00323   *   This parameter can be one of the following values:
00324   *     @arg SDIO_PowerState_OFF: SDIO Power OFF.
00325   *     @arg SDIO_PowerState_ON: SDIO Power ON.
00326   * @retval None
00327   */
00328 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
00332
00333   SDIO->POWER = SDIO_PowerState;
00334 }
00335
00336 /**
00337   * @brief  Gets the power status of the controller.
00338   * @param  None
00339   * @retval Power status of the controller. The returned value can
00340   *   be one of the following:
00341   * - 0x00: Power OFF
00342   * - 0x02: Power UP
00343   * - 0x03: Power ON
00344   */
00345 uint32_t SDIO_GetPowerState(void)
00346 {
00347   return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
00348 }
00349
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup SDIO_Group2 DMA transfers management functions
00355  *  @brief   DMA transfers management functions
00356  *
00357  @verbatim
00358   ==============================================================================
00359                   ##### DMA transfers management functions #####
00360   ==============================================================================
00361     [..] This section provide functions allowing to program SDIO DMA transfer.
00362
00363 @endverbatim
00364   * @{
00365   */
00366
00367 /**
00368   * @brief  Enables or disables the SDIO DMA request.
00369   * @param  NewState: new state of the selected SDIO DMA request.
00370   *   This parameter can be: ENABLE or DISABLE.
00371   * @retval None
00372   */
00373 void SDIO_DMACmd(FunctionalState NewState)
00374 {
00375   /* Check the parameters */
00376   assert_param(IS_FUNCTIONAL_STATE(NewState));
00377
00378   *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
00379 }
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup SDIO_Group3 Command path state machine (CPSM) management functions
00386  *  @brief   Command path state machine (CPSM) management functions
00387  *
00388  @verbatim
00389   ==============================================================================
00390        ##### Command path state machine (CPSM) management functions #####
00391   ==============================================================================
00392   [..] This section provide functions allowing to program and read the Command
00393        path state machine (CPSM).
00394
00395 @endverbatim
00396   * @{
00397   */
00398
00399 /**
00400   * @brief  Initializes the SDIO Command according to the specified
00401   *   parameters in the SDIO_CmdInitStruct and send the command.
00402   * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
00403   *   structure that contains the configuration information for the SDIO command.
00404   * @retval None
00405   */
00406 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
00407 {
00408   uint32_t tmpreg = 0;
00409
00410   /* Check the parameters */
00411   assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
00412   assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
00413   assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
00414   assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
00415
00416 /*---------------------------- SDIO ARG Configuration ------------------------*/
00417   /* Set the SDIO Argument value */
00418   SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
00419
00420 /*---------------------------- SDIO CMD Configuration ------------------------*/
00421   /* Get the SDIO CMD value */
00422   tmpreg = SDIO->CMD;
00423   /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
00424   tmpreg &= CMD_CLEAR_MASK;
00425   /* Set CMDINDEX bits according to SDIO_CmdIndex value */
00426   /* Set WAITRESP bits according to SDIO_Response value */
00427   /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
00428   /* Set CPSMEN bits according to SDIO_CPSM value */
00429   tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
00430            | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
00431
00432   /* Write to SDIO CMD */
00433   SDIO->CMD = tmpreg;
00434 }
00435
00436 /**
00437   * @brief  Fills each SDIO_CmdInitStruct member with its default value.
00438   * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
00439   *   structure which will be initialized.
00440   * @retval None
00441   */
00442 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
00443 {
00444   /* SDIO_CmdInitStruct members default value */
00445   SDIO_CmdInitStruct->SDIO_Argument = 0x00;
00446   SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
00447   SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
00448   SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
00449   SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
00450 }
00451
00452 /**
00453   * @brief  Returns command index of last command for which response received.
00454   * @param  None
00455   * @retval Returns the command index of the last command response received.
00456   */
00457 uint8_t SDIO_GetCommandResponse(void)
00458 {
00459   return (uint8_t)(SDIO->RESPCMD);
00460 }
00461
00462 /**
00463   * @brief  Returns response received from the card for the last command.
00464   * @param  SDIO_RESP: Specifies the SDIO response register.
00465   *   This parameter can be one of the following values:
00466   *     @arg SDIO_RESP1: Response Register 1.
00467   *     @arg SDIO_RESP2: Response Register 2.
00468   *     @arg SDIO_RESP3: Response Register 3.
00469   *     @arg SDIO_RESP4: Response Register 4.
00470   * @retval The Corresponding response register value.
00471   */
00472 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
00473 {
00474   __IO uint32_t tmp = 0;
00475
00476   /* Check the parameters */
00477   assert_param(IS_SDIO_RESP(SDIO_RESP));
00478
00479   tmp = SDIO_RESP_ADDR + SDIO_RESP;
00480
00481   return (*(__IO uint32_t *) tmp);
00482 }
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup SDIO_Group4 Data path state machine (DPSM) management functions
00489  *  @brief   Data path state machine (DPSM) management functions
00490  *
00491  @verbatim
00492   ==============================================================================
00493         ##### Data path state machine (DPSM) management functions #####
00494   ==============================================================================
00495   [..] This section provide functions allowing to program and read the Data path
00496        state machine (DPSM).
00497
00498 @endverbatim
00499   * @{
00500   */
00501
00502 /**
00503   * @brief  Initializes the SDIO data path according to the specified
00504   *   parameters in the SDIO_DataInitStruct.
00505   * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
00506   *   contains the configuration information for the SDIO command.
00507   * @retval None
00508   */
00509 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00510 {
00511   uint32_t tmpreg = 0;
00512
00513   /* Check the parameters */
00514   assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
00515   assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
00516   assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
00517   assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
00518   assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
00519
00520 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
00521   /* Set the SDIO Data TimeOut value */
00522   SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
00523
00524 /*---------------------------- SDIO DLEN Configuration -----------------------*/
00525   /* Set the SDIO DataLength value */
00526   SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
00527
00528 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
00529   /* Get the SDIO DCTRL value */
00530   tmpreg = SDIO->DCTRL;
00531   /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
00532   tmpreg &= DCTRL_CLEAR_MASK;
00533   /* Set DEN bit according to SDIO_DPSM value */
00534   /* Set DTMODE bit according to SDIO_TransferMode value */
00535   /* Set DTDIR bit according to SDIO_TransferDir value */
00536   /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
00537   tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
00538            | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
00539
00540   /* Write to SDIO DCTRL */
00541   SDIO->DCTRL = tmpreg;
00542 }
00543
00544 /**
00545   * @brief  Fills each SDIO_DataInitStruct member with its default value.
00546   * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
00547   *   will be initialized.
00548   * @retval None
00549   */
00550 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00551 {
00552   /* SDIO_DataInitStruct members default value */
00553   SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
00554   SDIO_DataInitStruct->SDIO_DataLength = 0x00;
00555   SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
00556   SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
00557   SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
00558   SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
00559 }
00560
00561 /**
00562   * @brief  Returns number of remaining data bytes to be transferred.
00563   * @param  None
00564   * @retval Number of remaining data bytes to be transferred
00565   */
00566 uint32_t SDIO_GetDataCounter(void)
00567 {
00568   return SDIO->DCOUNT;
00569 }
00570
00571 /**
00572   * @brief  Read one data word from Rx FIFO.
00573   * @param  None
00574   * @retval Data received
00575   */
00576 uint32_t SDIO_ReadData(void)
00577 {
00578   return SDIO->FIFO;
00579 }
00580
00581 /**
00582   * @brief  Write one data word to Tx FIFO.
00583   * @param  Data: 32-bit data word to write.
00584   * @retval None
00585   */
00586 void SDIO_WriteData(uint32_t Data)
00587 {
00588   SDIO->FIFO = Data;
00589 }
00590
00591 /**
00592   * @brief  Returns the number of words left to be written to or read from FIFO.
00593   * @param  None
00594   * @retval Remaining number of words.
00595   */
00596 uint32_t SDIO_GetFIFOCount(void)
00597 {
00598   return SDIO->FIFOCNT;
00599 }
00600
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup SDIO_Group5 SDIO IO Cards mode management functions
00606  *  @brief   SDIO IO Cards mode management functions
00607  *
00608  @verbatim
00609   ==============================================================================
00610               ##### SDIO IO Cards mode management functions #####
00611   ==============================================================================
00612   [..] This section provide functions allowing to program and read the SDIO IO
00613        Cards.
00614
00615 @endverbatim
00616   * @{
00617   */
00618
00619 /**
00620   * @brief  Starts the SD I/O Read Wait operation.
00621   * @param  NewState: new state of the Start SDIO Read Wait operation.
00622   *   This parameter can be: ENABLE or DISABLE.
00623   * @retval None
00624   */
00625 void SDIO_StartSDIOReadWait(FunctionalState NewState)
00626 {
00627   /* Check the parameters */
00628   assert_param(IS_FUNCTIONAL_STATE(NewState));
00629
00630   *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
00631 }
00632
00633 /**
00634   * @brief  Stops the SD I/O Read Wait operation.
00635   * @param  NewState: new state of the Stop SDIO Read Wait operation.
00636   *   This parameter can be: ENABLE or DISABLE.
00637   * @retval None
00638   */
00639 void SDIO_StopSDIOReadWait(FunctionalState NewState)
00640 {
00641   /* Check the parameters */
00642   assert_param(IS_FUNCTIONAL_STATE(NewState));
00643
00644   *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
00645 }
00646
00647 /**
00648   * @brief  Sets one of the two options of inserting read wait interval.
00649   * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
00650   *   This parametre can be:
00651   *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.
00652   *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.
00653   * @retval None
00654   */
00655 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
00656 {
00657   /* Check the parameters */
00658   assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
00659
00660   *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
00661 }
00662
00663 /**
00664   * @brief  Enables or disables the SD I/O Mode Operation.
00665   * @param  NewState: new state of SDIO specific operation.
00666   *   This parameter can be: ENABLE or DISABLE.
00667   * @retval None
00668   */
00669 void SDIO_SetSDIOOperation(FunctionalState NewState)
00670 {
00671   /* Check the parameters */
00672   assert_param(IS_FUNCTIONAL_STATE(NewState));
00673
00674   *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
00675 }
00676
00677 /**
00678   * @brief  Enables or disables the SD I/O Mode suspend command sending.
00679   * @param  NewState: new state of the SD I/O Mode suspend command.
00680   *   This parameter can be: ENABLE or DISABLE.
00681   * @retval None
00682   */
00683 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
00684 {
00685   /* Check the parameters */
00686   assert_param(IS_FUNCTIONAL_STATE(NewState));
00687
00688   *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
00689 }
00690
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup SDIO_Group6 CE-ATA mode management functions
00696  *  @brief   CE-ATA mode management functions
00697  *
00698  @verbatim
00699   ==============================================================================
00700                     ##### CE-ATA mode management functions #####
00701   ==============================================================================
00702   [..] This section provide functions allowing to program and read the CE-ATA
00703        card.
00704
00705 @endverbatim
00706   * @{
00707   */
00708
00709 /**
00710   * @brief  Enables or disables the command completion signal.
00711   * @param  NewState: new state of command completion signal.
00712   *   This parameter can be: ENABLE or DISABLE.
00713   * @retval None
00714   */
00715 void SDIO_CommandCompletionCmd(FunctionalState NewState)
00716 {
00717   /* Check the parameters */
00718   assert_param(IS_FUNCTIONAL_STATE(NewState));
00719
00720   *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
00721 }
00722
00723 /**
00724   * @brief  Enables or disables the CE-ATA interrupt.
00725   * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
00726   * @retval None
00727   */
00728 void SDIO_CEATAITCmd(FunctionalState NewState)
00729 {
00730   /* Check the parameters */
00731   assert_param(IS_FUNCTIONAL_STATE(NewState));
00732
00733   *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
00734 }
00735
00736 /**
00737   * @brief  Sends CE-ATA command (CMD61).
00738   * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
00739   * @retval None
00740   */
00741 void SDIO_SendCEATACmd(FunctionalState NewState)
00742 {
00743   /* Check the parameters */
00744   assert_param(IS_FUNCTIONAL_STATE(NewState));
00745
00746   *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
00747 }
00748
00749 /**
00750   * @}
00751   */
00752
00753 /** @defgroup SDIO_Group7 Interrupts and flags management functions
00754  *  @brief   Interrupts and flags management functions
00755
00756
00757  @verbatim
00758   ==============================================================================
00759               ##### Interrupts and flags management functions #####
00760   ==============================================================================
00761
00762  @endverbatim
00763   * @{
00764   */
00765
00766 /**
00767   * @brief  Enables or disables the SDIO interrupts.
00768   * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
00769   *   This parameter can be one or a combination of the following values:
00770   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
00771   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
00772   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
00773   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
00774   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
00775   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt.
00776   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt.
00777   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt.
00778   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt.
00779   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00780   *                            bus mode interrupt.
00781   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt.
00782   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt.
00783   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt.
00784   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt.
00785   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
00786   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
00787   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt.
00788   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt.
00789   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt.
00790   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt.
00791   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt.
00792   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt.
00793   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt.
00794   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
00795   * @param  NewState: new state of the specified SDIO interrupts.
00796   *   This parameter can be: ENABLE or DISABLE.
00797   * @retval None
00798   */
00799 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
00800 {
00801   /* Check the parameters */
00802   assert_param(IS_SDIO_IT(SDIO_IT));
00803   assert_param(IS_FUNCTIONAL_STATE(NewState));
00804
00805   if (NewState != DISABLE)
00806   {
00807     /* Enable the SDIO interrupts */
00808     SDIO->MASK |= SDIO_IT;
00809   }
00810   else
00811   {
00812     /* Disable the SDIO interrupts */
00813     SDIO->MASK &= ~SDIO_IT;
00814   }
00815 }
00816
00817 /**
00818   * @brief  Checks whether the specified SDIO flag is set or not.
00819   * @param  SDIO_FLAG: specifies the flag to check.
00820   *   This parameter can be one of the following values:
00821   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
00822   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
00823   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
00824   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout.
00825   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
00826   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error.
00827   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed).
00828   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required).
00829   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero).
00830   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
00831   *                              bus mode.
00832   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed).
00833   *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress.
00834   *     @arg SDIO_FLAG_TXACT:    Data transmit in progress.
00835   *     @arg SDIO_FLAG_RXACT:    Data receive in progress.
00836   *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.
00837   *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.
00838   *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full.
00839   *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full.
00840   *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty.
00841   *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty.
00842   *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO.
00843   *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO.
00844   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received.
00845   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
00846   * @retval The new state of SDIO_FLAG (SET or RESET).
00847   */
00848 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
00849 {
00850   FlagStatus bitstatus = RESET;
00851
00852   /* Check the parameters */
00853   assert_param(IS_SDIO_FLAG(SDIO_FLAG));
00854
00855   if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
00856   {
00857     bitstatus = SET;
00858   }
00859   else
00860   {
00861     bitstatus = RESET;
00862   }
00863   return bitstatus;
00864 }
00865
00866 /**
00867   * @brief  Clears the SDIO's pending flags.
00868   * @param  SDIO_FLAG: specifies the flag to clear.
00869   *   This parameter can be one or a combination of the following values:
00870   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
00871   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
00872   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
00873   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout.
00874   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
00875   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error.
00876   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed).
00877   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required).
00878   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero).
00879   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
00880   *                              bus mode.
00881   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed).
00882   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received.
00883   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
00884   * @retval None
00885   */
00886 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
00887 {
00888   /* Check the parameters */
00889   assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
00890
00891   SDIO->ICR = SDIO_FLAG;
00892 }
00893
00894 /**
00895   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
00896   * @param  SDIO_IT: specifies the SDIO interrupt source to check.
00897   *   This parameter can be one of the following values:
00898   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
00899   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
00900   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
00901   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
00902   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
00903   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt.
00904   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt.
00905   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt.
00906   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt.
00907   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00908   *                            bus mode interrupt.
00909   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt.
00910   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt.
00911   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt.
00912   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt.
00913   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
00914   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
00915   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt.
00916   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt.
00917   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt.
00918   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt.
00919   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt.
00920   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt.
00921   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt.
00922   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
00923   * @retval The new state of SDIO_IT (SET or RESET).
00924   */
00925 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
00926 {
00927   ITStatus bitstatus = RESET;
00928
00929   /* Check the parameters */
00930   assert_param(IS_SDIO_GET_IT(SDIO_IT));
00931   if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
00932   {
00933     bitstatus = SET;
00934   }
00935   else
00936   {
00937     bitstatus = RESET;
00938   }
00939   return bitstatus;
00940 }
00941
00942 /**
00943   * @brief  Clears the SDIO's interrupt pending bits.
00944   * @param  SDIO_IT: specifies the interrupt pending bit to clear.
00945   *   This parameter can be one or a combination of the following values:
00946   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
00947   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
00948   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
00949   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
00950   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
00951   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt.
00952   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt.
00953   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt.
00954   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt.
00955   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00956   *                            bus mode interrupt.
00957   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt.
00958   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.
00959   * @retval None
00960   */
00961 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
00962 {
00963   /* Check the parameters */
00964   assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
00965
00966   SDIO->ICR = SDIO_IT;
00967 }
00968
00969 /**
00970   * @}
00971   */
00972
00973 /**
00974   * @}
00975   */
00976
00977 /**
00978   * @}
00979   */
00980
00981 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_sdio.h Source File

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stm32l1xx_sdio.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_sdio.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the SDIO firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_SDIO_H
00028 #define __STM32L1xx_SDIO_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup SDIO
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 typedef struct
00048 {
00049   uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
00050                                            This parameter can be a value of @ref SDIO_Clock_Edge */
00051
00052   uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
00053                                            enabled or disabled.
00054                                            This parameter can be a value of @ref SDIO_Clock_Bypass */
00055
00056   uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
00057                                            disabled when the bus is idle.
00058                                            This parameter can be a value of @ref SDIO_Clock_Power_Save */
00059
00060   uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
00061                                            This parameter can be a value of @ref SDIO_Bus_Wide */
00062
00063   uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
00064                                            This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
00065
00066   uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
00067                                            This parameter can be a value between 0x00 and 0xFF. */
00068
00069 } SDIO_InitTypeDef;
00070
00071 typedef struct
00072 {
00073   uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
00074                                 to a card as part of a command message. If a command
00075                                 contains an argument, it must be loaded into this register
00076                                 before writing the command to the command register */
00077
00078   uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
00079
00080   uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
00081                                 This parameter can be a value of @ref SDIO_Response_Type */
00082
00083   uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
00084                                 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
00085
00086   uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
00087                                 is enabled or disabled.
00088                                 This parameter can be a value of @ref SDIO_CPSM_State */
00089 } SDIO_CmdInitTypeDef;
00090
00091 typedef struct
00092 {
00093   uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
00094
00095   uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
00096
00097   uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
00098                                      This parameter can be a value of @ref SDIO_Data_Block_Size */
00099
00100   uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
00101                                      is a read or write.
00102                                      This parameter can be a value of @ref SDIO_Transfer_Direction */
00103
00104   uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
00105                                      This parameter can be a value of @ref SDIO_Transfer_Type */
00106
00107   uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
00108                                      is enabled or disabled.
00109                                      This parameter can be a value of @ref SDIO_DPSM_State */
00110 } SDIO_DataInitTypeDef;
00111
00112 /* Exported constants --------------------------------------------------------*/
00113
00114 /** @defgroup SDIO_Exported_Constants
00115   * @{
00116   */
00117
00118 /** @defgroup SDIO_Clock_Edge
00119   * @{
00120   */
00121
00122 #define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
00123 #define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
00124 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
00125                                   ((EDGE) == SDIO_ClockEdge_Falling))
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup SDIO_Clock_Bypass
00131   * @{
00132   */
00133
00134 #define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
00135 #define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)
00136 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
00137                                      ((BYPASS) == SDIO_ClockBypass_Enable))
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup SDIO_Clock_Power_Save
00143   * @{
00144   */
00145
00146 #define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
00147 #define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200)
00148 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
00149                                         ((SAVE) == SDIO_ClockPowerSave_Enable))
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup SDIO_Bus_Wide
00155   * @{
00156   */
00157
00158 #define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
00159 #define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
00160 #define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
00161 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
00162                                 ((WIDE) == SDIO_BusWide_8b))
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup SDIO_Hardware_Flow_Control
00169   * @{
00170   */
00171
00172 #define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
00173 #define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
00174 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
00175                                                 ((CONTROL) == SDIO_HardwareFlowControl_Enable))
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SDIO_Power_State
00181   * @{
00182   */
00183
00184 #define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
00185 #define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
00186 #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
00187 /**
00188   * @}
00189   */
00190
00191
00192 /** @defgroup SDIO_Interrupt_soucres
00193   * @{
00194   */
00195
00196 #define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
00197 #define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
00198 #define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
00199 #define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
00200 #define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
00201 #define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
00202 #define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
00203 #define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
00204 #define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
00205 #define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
00206 #define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
00207 #define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
00208 #define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
00209 #define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
00210 #define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
00211 #define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
00212 #define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
00213 #define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
00214 #define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
00215 #define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
00216 #define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
00217 #define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
00218 #define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
00219 #define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
00220 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SDIO_Command_Index
00226   * @{
00227   */
00228
00229 #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup SDIO_Response_Type
00235   * @{
00236   */
00237
00238 #define SDIO_Response_No                    ((uint32_t)0x00000000)
00239 #define SDIO_Response_Short                 ((uint32_t)0x00000040)
00240 #define SDIO_Response_Long                  ((uint32_t)0x000000C0)
00241 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
00242                                     ((RESPONSE) == SDIO_Response_Short) || \
00243                                     ((RESPONSE) == SDIO_Response_Long))
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SDIO_Wait_Interrupt_State
00249   * @{
00250   */
00251
00252 #define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
00253 #define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
00254 #define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
00255 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
00256                             ((WAIT) == SDIO_Wait_Pend))
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup SDIO_CPSM_State
00262   * @{
00263   */
00264
00265 #define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
00266 #define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
00267 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup SDIO_Response_Registers
00273   * @{
00274   */
00275
00276 #define SDIO_RESP1                          ((uint32_t)0x00000000)
00277 #define SDIO_RESP2                          ((uint32_t)0x00000004)
00278 #define SDIO_RESP3                          ((uint32_t)0x00000008)
00279 #define SDIO_RESP4                          ((uint32_t)0x0000000C)
00280 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
00281                             ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SDIO_Data_Length
00287   * @{
00288   */
00289
00290 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SDIO_Data_Block_Size
00296   * @{
00297   */
00298
00299 #define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
00300 #define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
00301 #define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
00302 #define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
00303 #define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
00304 #define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
00305 #define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
00306 #define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
00307 #define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
00308 #define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
00309 #define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
00310 #define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
00311 #define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
00312 #define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
00313 #define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
00314 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
00315                                   ((SIZE) == SDIO_DataBlockSize_2b) || \
00316                                   ((SIZE) == SDIO_DataBlockSize_4b) || \
00317                                   ((SIZE) == SDIO_DataBlockSize_8b) || \
00318                                   ((SIZE) == SDIO_DataBlockSize_16b) || \
00319                                   ((SIZE) == SDIO_DataBlockSize_32b) || \
00320                                   ((SIZE) == SDIO_DataBlockSize_64b) || \
00321                                   ((SIZE) == SDIO_DataBlockSize_128b) || \
00322                                   ((SIZE) == SDIO_DataBlockSize_256b) || \
00323                                   ((SIZE) == SDIO_DataBlockSize_512b) || \
00324                                   ((SIZE) == SDIO_DataBlockSize_1024b) || \
00325                                   ((SIZE) == SDIO_DataBlockSize_2048b) || \
00326                                   ((SIZE) == SDIO_DataBlockSize_4096b) || \
00327                                   ((SIZE) == SDIO_DataBlockSize_8192b) || \
00328                                   ((SIZE) == SDIO_DataBlockSize_16384b))
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup SDIO_Transfer_Direction
00334   * @{
00335   */
00336
00337 #define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
00338 #define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
00339 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
00340                                    ((DIR) == SDIO_TransferDir_ToSDIO))
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup SDIO_Transfer_Type
00346   * @{
00347   */
00348
00349 #define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
00350 #define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
00351 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
00352                                      ((MODE) == SDIO_TransferMode_Block))
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup SDIO_DPSM_State
00358   * @{
00359   */
00360
00361 #define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
00362 #define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
00363 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup SDIO_Flags
00369   * @{
00370   */
00371
00372 #define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
00373 #define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
00374 #define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
00375 #define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
00376 #define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
00377 #define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
00378 #define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
00379 #define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
00380 #define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
00381 #define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
00382 #define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
00383 #define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
00384 #define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
00385 #define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
00386 #define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
00387 #define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
00388 #define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
00389 #define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
00390 #define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
00391 #define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
00392 #define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
00393 #define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
00394 #define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
00395 #define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
00396 #define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
00397                             ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
00398                             ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
00399                             ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
00400                             ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
00401                             ((FLAG)  == SDIO_FLAG_RXOVERR) || \
00402                             ((FLAG)  == SDIO_FLAG_CMDREND) || \
00403                             ((FLAG)  == SDIO_FLAG_CMDSENT) || \
00404                             ((FLAG)  == SDIO_FLAG_DATAEND) || \
00405                             ((FLAG)  == SDIO_FLAG_STBITERR) || \
00406                             ((FLAG)  == SDIO_FLAG_DBCKEND) || \
00407                             ((FLAG)  == SDIO_FLAG_CMDACT) || \
00408                             ((FLAG)  == SDIO_FLAG_TXACT) || \
00409                             ((FLAG)  == SDIO_FLAG_RXACT) || \
00410                             ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
00411                             ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
00412                             ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
00413                             ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
00414                             ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
00415                             ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
00416                             ((FLAG)  == SDIO_FLAG_TXDAVL) || \
00417                             ((FLAG)  == SDIO_FLAG_RXDAVL) || \
00418                             ((FLAG)  == SDIO_FLAG_SDIOIT) || \
00419                             ((FLAG)  == SDIO_FLAG_CEATAEND))
00420
00421 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
00422
00423 #define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
00424                             ((IT)  == SDIO_IT_DCRCFAIL) || \
00425                             ((IT)  == SDIO_IT_CTIMEOUT) || \
00426                             ((IT)  == SDIO_IT_DTIMEOUT) || \
00427                             ((IT)  == SDIO_IT_TXUNDERR) || \
00428                             ((IT)  == SDIO_IT_RXOVERR) || \
00429                             ((IT)  == SDIO_IT_CMDREND) || \
00430                             ((IT)  == SDIO_IT_CMDSENT) || \
00431                             ((IT)  == SDIO_IT_DATAEND) || \
00432                             ((IT)  == SDIO_IT_STBITERR) || \
00433                             ((IT)  == SDIO_IT_DBCKEND) || \
00434                             ((IT)  == SDIO_IT_CMDACT) || \
00435                             ((IT)  == SDIO_IT_TXACT) || \
00436                             ((IT)  == SDIO_IT_RXACT) || \
00437                             ((IT)  == SDIO_IT_TXFIFOHE) || \
00438                             ((IT)  == SDIO_IT_RXFIFOHF) || \
00439                             ((IT)  == SDIO_IT_TXFIFOF) || \
00440                             ((IT)  == SDIO_IT_RXFIFOF) || \
00441                             ((IT)  == SDIO_IT_TXFIFOE) || \
00442                             ((IT)  == SDIO_IT_RXFIFOE) || \
00443                             ((IT)  == SDIO_IT_TXDAVL) || \
00444                             ((IT)  == SDIO_IT_RXDAVL) || \
00445                             ((IT)  == SDIO_IT_SDIOIT) || \
00446                             ((IT)  == SDIO_IT_CEATAEND))
00447
00448 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
00449
00450 /**
00451   * @}
00452   */
00453
00454 /** @defgroup SDIO_Read_Wait_Mode
00455   * @{
00456   */
00457
00458 #define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
00459 #define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
00460 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
00461                                      ((MODE) == SDIO_ReadWaitMode_DATA2))
00462 /**
00463   * @}
00464   */
00465
00466 /**
00467   * @}
00468   */
00469
00470 /* Exported macro ------------------------------------------------------------*/
00471 /* Exported functions ------------------------------------------------------- */
00472 /*  Function used to set the SDIO configuration to the default reset state ****/
00473 void SDIO_DeInit(void);
00474
00475 /* Initialization and Configuration functions *********************************/
00476 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
00477 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
00478 void SDIO_ClockCmd(FunctionalState NewState);
00479 void SDIO_SetPowerState(uint32_t SDIO_PowerState);
00480 uint32_t SDIO_GetPowerState(void);
00481
00482 /* DMA transfers management functions *****************************************/
00483 void SDIO_DMACmd(FunctionalState NewState);
00484
00485 /* Command path state machine (CPSM) management functions *********************/
00486 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
00487 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
00488 uint8_t SDIO_GetCommandResponse(void);
00489 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
00490
00491 /* Data path state machine (DPSM) management functions ************************/
00492 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
00493 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
00494 uint32_t SDIO_GetDataCounter(void);
00495 uint32_t SDIO_ReadData(void);
00496 void SDIO_WriteData(uint32_t Data);
00497 uint32_t SDIO_GetFIFOCount(void);
00498
00499 /* SDIO IO Cards mode management functions ************************************/
00500 void SDIO_StartSDIOReadWait(FunctionalState NewState);
00501 void SDIO_StopSDIOReadWait(FunctionalState NewState);
00502 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
00503 void SDIO_SetSDIOOperation(FunctionalState NewState);
00504 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
00505
00506 /* CE-ATA mode management functions *******************************************/
00507 void SDIO_CommandCompletionCmd(FunctionalState NewState);
00508 void SDIO_CEATAITCmd(FunctionalState NewState);
00509 void SDIO_SendCEATACmd(FunctionalState NewState);
00510
00511 /* Interrupts and flags management functions **********************************/
00512 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
00513 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
00514 void SDIO_ClearFlag(uint32_t SDIO_FLAG);
00515 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
00516 void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
00517
00518 #ifdef __cplusplus
00519 }
00520 #endif
00521
00522 #endif /* __STM32L1xx_SDIO_H */
00523
00524 /**
00525   * @}
00526   */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_spi.c Source File

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stm32l1xx_spi.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Serial peripheral interface (SPI):
00009   *           + Initialization and Configuration
00010   *           + Data transfers functions
00011   *           + Hardware CRC Calculation
00012   *           + DMA transfers management
00013   *           + Interrupts and flags management
00014   *
00015   *  @verbatim
00016     [..] The I2S feature is not implemented in STM32L1xx Ultra Low Power
00017          Medium-density devices and it's supported only STM32L1xx Ultra Low Power
00018          Medium-density Plus and High-density devices.
00019
00020  ===============================================================================
00021                        ##### How to use this driver #####
00022  ===============================================================================
00023     [..]
00024         (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
00025             function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
00026             function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)
00027             for SPI3.
00028
00029         (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using
00030             RCC_AHBPeriphClockCmd() function.
00031
00032         (#) Peripherals alternate function:
00033             (++) Connect the pin to the desired peripherals' Alternate
00034                  Function (AF) using GPIO_PinAFConfig() function.
00035             (++) Configure the desired pin in alternate function by:
00036                  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
00037             (++) Select the type, pull-up/pull-down and output speed via
00038                  GPIO_PuPd, GPIO_OType and GPIO_Speed members.
00039             (++) Call GPIO_Init() function.
00040
00041         (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
00042             Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
00043             function.In I2S mode, program the Mode, Standard, Data Format, MCLK
00044             Output, Audio frequency and Polarity using I2S_Init() function.
00045
00046         (#) Enable the NVIC and the corresponding interrupt using the function
00047             SPI_ITConfig() if you need to use interrupt mode.
00048
00049         (#) When using the DMA mode
00050             (++) Configure the DMA using DMA_Init() function.
00051             (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
00052
00053         (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
00054             I2S_Cmd().
00055
00056         (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
00057
00058         (#) Optionally, you can enable/configure the following parameters without
00059             re-initialization (i.e there is no need to call again SPI_Init() function):
00060             (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
00061                  is programmed as Data direction parameter using the SPI_Init()
00062                  function it can be possible to switch between SPI_Direction_Tx
00063                  or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
00064             (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
00065                  using the SPI_Init() function it can be possible to manage the
00066                  NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
00067             (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
00068             (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
00069
00070         (#) To use the CRC Hardware calculation feature refer to the Peripheral
00071             CRC hardware Calculation subsection.
00072
00073     @endverbatim
00074
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00079   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00080   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00081   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00082   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00083   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00084   *
00085   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00086   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00087   *
00088   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00089   ******************************************************************************
00090   */
00091
00092 /* Includes ------------------------------------------------------------------*/
00093 #include "stm32l1xx_spi.h"
00094 #include "stm32l1xx_rcc.h"
00095
00096 /** @addtogroup STM32L1xx_StdPeriph_Driver
00097   * @{
00098   */
00099
00100 /** @defgroup SPI
00101   * @brief SPI driver modules
00102   * @{
00103   */
00104
00105 /* Private typedef -----------------------------------------------------------*/
00106 /* Private define ------------------------------------------------------------*/
00107 /* SPI registers Masks */
00108 #define CR1_CLEAR_MASK       ((uint16_t)0x3040)
00109 #define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
00110
00111 /* Private macro -------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Private functions ---------------------------------------------------------*/
00115
00116 /** @defgroup SPI_Private_Functions
00117   * @{
00118   */
00119
00120 /** @defgroup SPI_Group1 Initialization and Configuration functions
00121  *  @brief   Initialization and Configuration functions
00122  *
00123 @verbatim
00124  ===============================================================================
00125            ##### Initialization and Configuration functions #####
00126  ===============================================================================
00127     [..] This section provides a set of functions allowing to initialize the SPI
00128          Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
00129          Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
00130     [..] The SPI_Init() function follows the SPI configuration procedures for
00131          Master mode and Slave mode (details for these procedures are available
00132          in reference manual (RM0038)).
00133
00134 @endverbatim
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Deinitializes the SPIx peripheral registers to their default
00140   *         reset values.
00141   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00142   *               in SPI mode or 2 or 3 in I2S mode.
00143   * @retval None
00144   */
00145 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
00146 {
00147   /* Check the parameters */
00148   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00149
00150   if (SPIx == SPI1)
00151   {
00152     /* Enable SPI1 reset state */
00153     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
00154     /* Release SPI1 from reset state */
00155     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00156   }
00157   else if (SPIx == SPI2)
00158   {
00159     /* Enable SPI2 reset state */
00160     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
00161     /* Release SPI2 from reset state */
00162     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
00163     }
00164   else
00165   {
00166     if (SPIx == SPI3)
00167     {
00168       /* Enable SPI3 reset state */
00169       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
00170       /* Release SPI3 from reset state */
00171       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00172     }
00173   }
00174 }
00175
00176 /**
00177   * @brief  Initializes the SPIx peripheral according to the specified
00178   *         parameters in the SPI_InitStruct.
00179   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00180   * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
00181   *         contains the configuration information for the specified SPI peripheral.
00182   * @retval None
00183   */
00184 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
00185 {
00186   uint16_t tmpreg = 0;
00187
00188   /* check the parameters */
00189   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00190
00191   /* Check the SPI parameters */
00192   assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
00193   assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
00194   assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
00195   assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
00196   assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
00197   assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
00198   assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
00199   assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
00200   assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
00201
00202 /*---------------------------- SPIx CR1 Configuration ------------------------*/
00203   /* Get the SPIx CR1 value */
00204   tmpreg = SPIx->CR1;
00205   /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
00206   tmpreg &= CR1_CLEAR_MASK;
00207   /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
00208      master/salve mode, CPOL and CPHA */
00209   /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
00210   /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
00211   /* Set LSBFirst bit according to SPI_FirstBit value */
00212   /* Set BR bits according to SPI_BaudRatePrescaler value */
00213   /* Set CPOL bit according to SPI_CPOL value */
00214   /* Set CPHA bit according to SPI_CPHA value */
00215   tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
00216                   SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
00217                   SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
00218                   SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
00219   /* Write to SPIx CR1 */
00220   SPIx->CR1 = tmpreg;
00221
00222   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00223   SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
00224 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
00225   /* Write to SPIx CRCPOLY */
00226   SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
00227 }
00228
00229 /**
00230   * @brief  Initializes the SPIx peripheral according to the specified
00231   *         parameters in the I2S_InitStruct.
00232   * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
00233   *         (configured in I2S mode).
00234   * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
00235   *         contains the configuration information for the specified SPI peripheral
00236   *         configured in I2S mode.
00237   * @note
00238   *  The function calculates the optimal prescaler needed to obtain the most
00239   *  accurate audio frequency (depending on the I2S clock source, the PLL values
00240   *  and the product configuration). But in case the prescaler value is greater
00241   *  than 511, the default value (0x02) will be configured instead.
00242   * @retval None
00243   */
00244 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
00245 {
00246   uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
00247   uint32_t tmp = 0;
00248   RCC_ClocksTypeDef RCC_Clocks;
00249   uint32_t sourceclock = 0;
00250
00251   /* Check the I2S parameters */
00252   assert_param(IS_SPI_23_PERIPH(SPIx));
00253   assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
00254   assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
00255   assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
00256   assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
00257   assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
00258   assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
00259
00260 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
00261   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00262   SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
00263   SPIx->I2SPR = 0x0002;
00264
00265   /* Get the I2SCFGR register value */
00266   tmpreg = SPIx->I2SCFGR;
00267
00268   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
00269   if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
00270   {
00271     i2sodd = (uint16_t)0;
00272     i2sdiv = (uint16_t)2;
00273   }
00274   /* If the requested audio frequency is not the default, compute the prescaler */
00275   else
00276   {
00277     /* Check the frame length (For the Prescaler computing) */
00278     if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
00279     {
00280       /* Packet length is 16 bits */
00281       packetlength = 1;
00282     }
00283     else
00284     {
00285       /* Packet length is 32 bits */
00286       packetlength = 2;
00287     }
00288
00289     /* I2S Clock source is System clock: Get System Clock frequency */
00290     RCC_GetClocksFreq(&RCC_Clocks);
00291
00292     /* Get the source clock value: based on System Clock value */
00293     sourceclock = RCC_Clocks.SYSCLK_Frequency;
00294
00295     /* Compute the Real divider depending on the MCLK output state with a flaoting point */
00296     if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
00297     {
00298       /* MCLK output is enabled */
00299       tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00300     }
00301     else
00302     {
00303       /* MCLK output is disabled */
00304       tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00305     }
00306
00307     /* Remove the flaoting point */
00308     tmp = tmp / 10;
00309
00310     /* Check the parity of the divider */
00311     i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
00312
00313     /* Compute the i2sdiv prescaler */
00314     i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
00315
00316     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00317     i2sodd = (uint16_t) (i2sodd << 8);
00318   }
00319
00320   /* Test if the divider is 1 or 0 or greater than 0xFF */
00321   if ((i2sdiv < 2) || (i2sdiv > 0xFF))
00322   {
00323     /* Set the default values */
00324     i2sdiv = 2;
00325     i2sodd = 0;
00326   }
00327
00328   /* Write to SPIx I2SPR register the computed value */
00329   SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
00330
00331   /* Configure the I2S with the SPI_InitStruct values */
00332   tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
00333                   (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
00334                   (uint16_t)I2S_InitStruct->I2S_CPOL))));
00335
00336   /* Write to SPIx I2SCFGR */
00337   SPIx->I2SCFGR = tmpreg;
00338 }
00339
00340 /**
00341   * @brief  Fills each SPI_InitStruct member with its default value.
00342   * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
00343   * @retval None
00344   */
00345 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
00346 {
00347 /*--------------- Reset SPI init structure parameters values -----------------*/
00348   /* Initialize the SPI_Direction member */
00349   SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00350   /* initialize the SPI_Mode member */
00351   SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
00352   /* initialize the SPI_DataSize member */
00353   SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
00354   /* Initialize the SPI_CPOL member */
00355   SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
00356   /* Initialize the SPI_CPHA member */
00357   SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
00358   /* Initialize the SPI_NSS member */
00359   SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
00360   /* Initialize the SPI_BaudRatePrescaler member */
00361   SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00362   /* Initialize the SPI_FirstBit member */
00363   SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
00364   /* Initialize the SPI_CRCPolynomial member */
00365   SPI_InitStruct->SPI_CRCPolynomial = 7;
00366 }
00367
00368 /**
00369   * @brief  Fills each I2S_InitStruct member with its default value.
00370   * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
00371   * @retval None
00372   */
00373 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
00374 {
00375 /*--------------- Reset I2S init structure parameters values -----------------*/
00376   /* Initialize the I2S_Mode member */
00377   I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
00378
00379   /* Initialize the I2S_Standard member */
00380   I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
00381
00382   /* Initialize the I2S_DataFormat member */
00383   I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
00384
00385   /* Initialize the I2S_MCLKOutput member */
00386   I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00387
00388   /* Initialize the I2S_AudioFreq member */
00389   I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
00390
00391   /* Initialize the I2S_CPOL member */
00392   I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
00393 }
00394
00395 /**
00396   * @brief  Enables or disables the specified SPI peripheral.
00397   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00398   * @param  NewState: new state of the SPIx peripheral.
00399   *   This parameter can be: ENABLE or DISABLE.
00400   * @retval None
00401   */
00402 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00403 {
00404   /* Check the parameters */
00405   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00406   assert_param(IS_FUNCTIONAL_STATE(NewState));
00407   if (NewState != DISABLE)
00408   {
00409     /* Enable the selected SPI peripheral */
00410     SPIx->CR1 |= SPI_CR1_SPE;
00411   }
00412   else
00413   {
00414     /* Disable the selected SPI peripheral */
00415     SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
00416   }
00417 }
00418
00419 /**
00420   * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
00421   * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
00422   * @param  NewState: new state of the SPIx peripheral.
00423   *         This parameter can be: ENABLE or DISABLE.
00424   * @retval None
00425   */
00426 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_SPI_23_PERIPH(SPIx));
00430   assert_param(IS_FUNCTIONAL_STATE(NewState));
00431
00432   if (NewState != DISABLE)
00433   {
00434     /* Enable the selected SPI peripheral (in I2S mode) */
00435     SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
00436   }
00437   else
00438   {
00439     /* Disable the selected SPI peripheral in I2S mode */
00440     SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
00441   }
00442 }
00443
00444 /**
00445   * @brief  Configures the data size for the selected SPI.
00446   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00447   * @param  SPI_DataSize: specifies the SPI data size.
00448   *   This parameter can be one of the following values:
00449   *     @arg SPI_DataSize_16b: Set data frame format to 16bit.
00450   *     @arg SPI_DataSize_8b: Set data frame format to 8bit.
00451   * @retval None.
00452   */
00453 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
00454 {
00455   /* Check the parameters */
00456   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00457   assert_param(IS_SPI_DATASIZE(SPI_DataSize));
00458   /* Clear DFF bit */
00459   SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
00460   /* Set new DFF bit value */
00461   SPIx->CR1 |= SPI_DataSize;
00462 }
00463
00464 /**
00465   * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
00466   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00467   * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode.
00468   *   This parameter can be one of the following values:
00469   *     @arg SPI_Direction_Tx: Selects Tx transmission direction.
00470   *     @arg SPI_Direction_Rx: Selects Rx receive direction.
00471   * @retval None
00472   */
00473 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
00474 {
00475   /* Check the parameters */
00476   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00477   assert_param(IS_SPI_DIRECTION(SPI_Direction));
00478   if (SPI_Direction == SPI_Direction_Tx)
00479   {
00480     /* Set the Tx only mode */
00481     SPIx->CR1 |= SPI_Direction_Tx;
00482   }
00483   else
00484   {
00485     /* Set the Rx only mode */
00486     SPIx->CR1 &= SPI_Direction_Rx;
00487   }
00488 }
00489
00490 /**
00491   * @brief  Configures internally by software the NSS pin for the selected SPI.
00492   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00493   * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
00494   *   This parameter can be one of the following values:
00495   *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally.
00496   *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally.
00497   * @retval None
00498   */
00499 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
00500 {
00501   /* Check the parameters */
00502   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00503   assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
00504   if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
00505   {
00506     /* Set NSS pin internally by software */
00507     SPIx->CR1 |= SPI_NSSInternalSoft_Set;
00508   }
00509   else
00510   {
00511     /* Reset NSS pin internally by software */
00512     SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
00513   }
00514 }
00515
00516 /**
00517   * @brief  Enables or disables the SS output for the selected SPI.
00518   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00519   * @param  NewState: new state of the SPIx SS output.
00520   *   This parameter can be: ENABLE or DISABLE.
00521   * @retval None
00522   */
00523 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00524 {
00525   /* Check the parameters */
00526   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00527   assert_param(IS_FUNCTIONAL_STATE(NewState));
00528   if (NewState != DISABLE)
00529   {
00530     /* Enable the selected SPI SS output */
00531     SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
00532   }
00533   else
00534   {
00535     /* Disable the selected SPI SS output */
00536     SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
00537   }
00538 }
00539
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup SPI_Group2 Data transfers functions
00545  *  @brief   Data transfers functions
00546  *
00547 @verbatim
00548  ===============================================================================
00549                     ##### Data transfers functions #####
00550  ===============================================================================
00551 ....[..] This section provides a set of functions allowing to manage the SPI data
00552          transfers.
00553 ....[..] In reception, data are received and then stored into an internal Rx buffer
00554          while In transmission, data are first stored into an internal Tx buffer
00555          before being transmitted.
00556 ....[..] The read access of the SPI_DR register can be done using the
00557          SPI_I2S_ReceiveData() function and returns the Rx buffered value.
00558          Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData()
00559          function and stores the written data into Tx buffer.
00560
00561 @endverbatim
00562   * @{
00563   */
00564
00565 /**
00566   * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral.
00567   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00568   *         in SPI mode or 2 or 3 in I2S mode.
00569   * @retval The value of the received data.
00570   */
00571 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
00572 {
00573   /* Check the parameters */
00574   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00575
00576   /* Return the data in the DR register */
00577   return SPIx->DR;
00578 }
00579
00580 /**
00581   * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
00582   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00583   *         in SPI mode or 2 or 3 in I2S mode.
00584   * @param  Data: Data to be transmitted.
00585   * @retval None
00586   */
00587 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
00588 {
00589   /* Check the parameters */
00590   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00591
00592   /* Write in the DR register the data to be sent */
00593   SPIx->DR = Data;
00594 }
00595
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup SPI_Group3 Hardware CRC Calculation functions
00601  *  @brief   Hardware CRC Calculation functions
00602  *
00603 @verbatim
00604  ===============================================================================
00605                 ##### Hardware CRC Calculation functions #####
00606  ===============================================================================
00607     [..] This section provides a set of functions allowing to manage the SPI CRC
00608          hardware calculation SPI communication using CRC is possible through
00609          the following procedure:
00610          (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate
00611              Prescaler, Slave Management, Peripheral Mode and CRC Polynomial
00612              values using the SPI_Init() function.
00613          (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
00614          (#) Enable the SPI using the SPI_Cmd() function.
00615          (#) Before writing the last data to the TX buffer, set the CRCNext bit
00616              using the SPI_TransmitCRC() function to indicate that after
00617              transmission of the last data, the CRC should be transmitted.
00618          (#) After transmitting the last data, the SPI transmits the CRC.
00619              The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and
00620              compared against the SPI_RXCRCR value.
00621              If the value does not match, the SPI_FLAG_CRCERR flag is set and an
00622              interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
00623     -@-
00624        (+@) It is advised to don't read the calculate CRC values during the communication.
00625        (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
00626        when the clock is stable, that is, when the clock is in the steady state.
00627        If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
00628        to the SCK slave input clock as soon as CRCEN is set, and this, whatever
00629        the value of the SPE bit.
00630        (+@) With high bitrate frequencies, be careful when transmitting the CRC.
00631        As the number of used CPU cycles has to be as low as possible in the CRC
00632        transfer phase, it is forbidden to call software functions in the CRC
00633        transmission sequence to avoid errors in the last data and CRC reception.
00634        In fact, CRCNEXT bit has to be written before the end of the transmission/
00635        reception of the last data.
00636        (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
00637        degradation of the SPI speed performance due to CPU accesses impacting the
00638        SPI bandwidth.
00639        (+@) When the STM32L15xxx are configured as slaves and the NSS hardware mode is
00640        used, the NSS pin needs to be kept low between the data phase and the CRC
00641        phase.
00642        (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
00643        calculation takes place even if a high level is applied on the NSS pin.
00644        This may happen for example in case of a multislave environment where the
00645        communication master addresses slaves alternately.
00646        (+@) Between a slave deselection (high level on NSS) and a new slave selection
00647        (low level on NSS), the CRC value should be cleared on both master and slave
00648        sides in order to resynchronize the master and slave for their respective
00649        CRC calculation.
00650     -@- To clear the CRC, follow the procedure below:
00651        (#@) Disable SPI using the SPI_Cmd() function
00652        (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
00653        (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
00654        (#@) Enable SPI using the SPI_Cmd() function.
00655
00656 @endverbatim
00657   * @{
00658   */
00659
00660 /**
00661   * @brief  Enables or disables the CRC value calculation of the transferred bytes.
00662   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00663   * @param  NewState: new state of the SPIx CRC value calculation.
00664   *   This parameter can be: ENABLE or DISABLE.
00665   * @retval None
00666   */
00667 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
00668 {
00669   /* Check the parameters */
00670   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00671   assert_param(IS_FUNCTIONAL_STATE(NewState));
00672   if (NewState != DISABLE)
00673   {
00674     /* Enable the selected SPI CRC calculation */
00675     SPIx->CR1 |= SPI_CR1_CRCEN;
00676   }
00677   else
00678   {
00679     /* Disable the selected SPI CRC calculation */
00680     SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
00681   }
00682 }
00683
00684 /**
00685   * @brief  Transmit the SPIx CRC value.
00686   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00687   * @retval None
00688   */
00689 void SPI_TransmitCRC(SPI_TypeDef* SPIx)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00693
00694   /* Enable the selected SPI CRC transmission */
00695   SPIx->CR1 |= SPI_CR1_CRCNEXT;
00696 }
00697
00698 /**
00699   * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
00700   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00701   * @param  SPI_CRC: specifies the CRC register to be read.
00702   *   This parameter can be one of the following values:
00703   *     @arg SPI_CRC_Tx: Selects Tx CRC register.
00704   *     @arg SPI_CRC_Rx: Selects Rx CRC register.
00705   * @retval The selected CRC register value.
00706   */
00707 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
00708 {
00709   uint16_t crcreg = 0;
00710   /* Check the parameters */
00711   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00712   assert_param(IS_SPI_CRC(SPI_CRC));
00713   if (SPI_CRC != SPI_CRC_Rx)
00714   {
00715     /* Get the Tx CRC register */
00716     crcreg = SPIx->TXCRCR;
00717   }
00718   else
00719   {
00720     /* Get the Rx CRC register */
00721     crcreg = SPIx->RXCRCR;
00722   }
00723   /* Return the selected CRC register */
00724   return crcreg;
00725 }
00726
00727 /**
00728   * @brief  Returns the CRC Polynomial register value for the specified SPI.
00729   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00730   * @retval The CRC Polynomial register value.
00731   */
00732 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
00733 {
00734   /* Check the parameters */
00735   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00736
00737   /* Return the CRC polynomial register */
00738   return SPIx->CRCPR;
00739 }
00740
00741 /**
00742   * @}
00743   */
00744
00745 /** @defgroup SPI_Group4 DMA transfers management functions
00746  *  @brief   DMA transfers management functions
00747   *
00748 @verbatim
00749  ===============================================================================
00750                 ##### DMA transfers management functions #####
00751  ===============================================================================
00752
00753 @endverbatim
00754   * @{
00755   */
00756
00757 /**
00758   * @brief  Enables or disables the SPIx/I2Sx DMA interface.
00759   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00760   *               in SPI mode or 2 or 3 in I2S mode.
00761   * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
00762   *   This parameter can be any combination of the following values:
00763   *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.
00764   *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.
00765   * @param  NewState: new state of the selected SPI DMA transfer request.
00766   *   This parameter can be: ENABLE or DISABLE.
00767   * @retval None
00768   */
00769 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
00770 {
00771   /* Check the parameters */
00772   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00773   assert_param(IS_FUNCTIONAL_STATE(NewState));
00774   assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
00775
00776   if (NewState != DISABLE)
00777   {
00778     /* Enable the selected SPI DMA requests */
00779     SPIx->CR2 |= SPI_I2S_DMAReq;
00780   }
00781   else
00782   {
00783     /* Disable the selected SPI DMA requests */
00784     SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
00785   }
00786 }
00787
00788 /**
00789   * @}
00790   */
00791
00792 /** @defgroup SPI_Group5 Interrupts and flags management functions
00793  *  @brief   Interrupts and flags management functions
00794   *
00795 @verbatim
00796  ===============================================================================
00797              ##### Interrupts and flags management functions #####
00798  ===============================================================================
00799     [..] This section provides a set of functions allowing to configure the SPI
00800          Interrupts sources and check or clear the flags or pending bits status.
00801          The user should identify which mode will be used in his application to
00802          manage the communication: Polling mode, Interrupt mode or DMA mode.
00803   *** Polling Mode ***
00804   ====================
00805     [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
00806         (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer
00807              register.
00808         (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer
00809              register.
00810         (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer
00811              of the SPI.
00812         (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
00813         (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
00814         (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
00815         (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
00816         (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
00817         (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
00818     -@- Do not use the BSY flag to handle each data transmission or reception.
00819         It is better to use the TXE and RXNE flags instead.
00820     [..] In this Mode it is advised to use the following functions:
00821          (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).
00822          (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).
00823
00824   *** Interrupt Mode ***
00825   ======================
00826     [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt
00827          sources and 7 pending bits:
00828     [..] Pending Bits:
00829         (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
00830         (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
00831         (#) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur.
00832         (#) SPI_IT_MODF : to indicate if a Mode Fault error occur.
00833         (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
00834         (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
00835         (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
00836     [..] Interrupt Source:
00837         (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
00838             interrupt.
00839         (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
00840             empty interrupt.
00841         (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
00842     [..] In this Mode it is advised to use the following functions:
00843          (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT,
00844              FunctionalState NewState).
00845          (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).
00846          (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).
00847
00848   *** DMA Mode ***
00849   ================
00850     [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel
00851          requests:
00852         (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
00853         (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
00854
00855     [..] In this Mode it is advised to use the following function:
00856          (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq,
00857              FunctionalState NewState).
00858
00859 @endverbatim
00860   * @{
00861   */
00862
00863 /**
00864   * @brief  Enables or disables the specified SPI/I2S interrupts.
00865   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00866   *         in SPI mode or 2 or 3 in I2S mode.
00867
00868   * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
00869   *   This parameter can be one of the following values:
00870   *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.
00871   *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.
00872   *     @arg SPI_I2S_IT_ERR: Error interrupt mask.
00873   * @param  NewState: new state of the specified SPI interrupt.
00874   *   This parameter can be: ENABLE or DISABLE.
00875   * @retval None
00876   */
00877 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
00878 {
00879   uint16_t itpos = 0, itmask = 0 ;
00880
00881   /* Check the parameters */
00882   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00883   assert_param(IS_FUNCTIONAL_STATE(NewState));
00884   assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
00885
00886   /* Get the SPI IT index */
00887   itpos = SPI_I2S_IT >> 4;
00888
00889   /* Set the IT mask */
00890   itmask = (uint16_t)1 << (uint16_t)itpos;
00891
00892   if (NewState != DISABLE)
00893   {
00894     /* Enable the selected SPI interrupt */
00895     SPIx->CR2 |= itmask;
00896   }
00897   else
00898   {
00899     /* Disable the selected SPI interrupt */
00900     SPIx->CR2 &= (uint16_t)~itmask;
00901   }
00902 }
00903
00904 /**
00905   * @brief  Checks whether the specified SPIx/I2Sx flag is set or not.
00906   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00907   *         in SPI mode or 2 or 3 in I2S mode.
00908
00909   * @param  SPI_I2S_FLAG: specifies the SPI flag to check.
00910   *   This parameter can be one of the following values:
00911   *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
00912   *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
00913   *     @arg SPI_I2S_FLAG_BSY: Busy flag.
00914   *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
00915   *     @arg SPI_FLAG_MODF: Mode Fault flag.
00916   *     @arg SPI_FLAG_CRCERR: CRC Error flag.
00917   *     @arg SPI_I2S_FLAG_FRE: Format Error.
00918   *     @arg I2S_FLAG_UDR: Underrun Error flag.
00919   *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
00920   * @retval The new state of SPI_I2S_FLAG (SET or RESET).
00921   */
00922 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00923 {
00924   FlagStatus bitstatus = RESET;
00925   /* Check the parameters */
00926   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00927   assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
00928
00929   /* Check the status of the specified SPI flag */
00930   if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
00931   {
00932     /* SPI_I2S_FLAG is set */
00933     bitstatus = SET;
00934   }
00935   else
00936   {
00937     /* SPI_I2S_FLAG is reset */
00938     bitstatus = RESET;
00939   }
00940   /* Return the SPI_I2S_FLAG status */
00941   return  bitstatus;
00942 }
00943
00944 /**
00945   * @brief  Clears the SPIx CRC Error (CRCERR) flag.
00946   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00947   *         in SPI mode or 2 or 3 in I2S mode.
00948
00949   * @param  SPI_I2S_FLAG: specifies the SPI flag to clear.
00950   *   This function clears only CRCERR flag.
00951
00952   * @note OVR (OverRun error) flag is cleared by software sequence: a read
00953   *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
00954   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
00955   * @note UDR (UnderRun error) flag is cleared by a read operation to
00956   *     SPI_SR register (SPI_I2S_GetFlagStatus()).
00957   * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
00958   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
00959   *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00960   * @retval None
00961   */
00962 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00963 {
00964   /* Check the parameters */
00965   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00966   assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
00967
00968   /* Clear the selected SPI CRC Error (CRCERR) flag */
00969   SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
00970 }
00971
00972 /**
00973   * @brief  Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
00974   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
00975   *         in SPI mode or 2 or 3 in I2S mode.
00976
00977   * @param  SPI_I2S_IT: specifies the SPI interrupt source to check.
00978   *   This parameter can be one of the following values:
00979   *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
00980   *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
00981   *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
00982   *     @arg SPI_IT_MODF: Mode Fault interrupt.
00983   *     @arg SPI_IT_CRCERR: CRC Error interrupt.
00984   *     @arg I2S_IT_UDR: Underrun interrupt.
00985   *     @arg SPI_I2S_IT_FRE: Format Error interrupt.
00986   * @retval The new state of SPI_I2S_IT (SET or RESET).
00987   */
00988 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
00989 {
00990   ITStatus bitstatus = RESET;
00991   uint16_t itpos = 0, itmask = 0, enablestatus = 0;
00992
00993   /* Check the parameters */
00994   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00995   assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
00996
00997   /* Get the SPI_I2S_IT index */
00998   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
00999
01000   /* Get the SPI_I2S_IT IT mask */
01001   itmask = SPI_I2S_IT >> 4;
01002
01003   /* Set the IT mask */
01004   itmask = 0x01 << itmask;
01005
01006   /* Get the SPI_I2S_IT enable bit status */
01007   enablestatus = (SPIx->CR2 & itmask) ;
01008
01009   /* Check the status of the specified SPI interrupt */
01010   if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
01011   {
01012     /* SPI_I2S_IT is set */
01013     bitstatus = SET;
01014   }
01015   else
01016   {
01017     /* SPI_I2S_IT is reset */
01018     bitstatus = RESET;
01019   }
01020   /* Return the SPI_I2S_IT status */
01021   return bitstatus;
01022 }
01023
01024 /**
01025   * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
01026   * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
01027   *         in SPI mode or 2 or 3 in I2S mode.
01028
01029   * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
01030   *   This function clears only CRCERR interrupt pending bit.
01031
01032   *     OVR (OverRun Error) interrupt pending bit is cleared by software
01033   *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
01034   *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
01035   * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
01036   *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
01037   * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
01038   *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
01039   *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
01040   *     the SPI).
01041   * @retval None
01042   */
01043 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
01044 {
01045   uint16_t itpos = 0;
01046   /* Check the parameters */
01047   assert_param(IS_SPI_ALL_PERIPH(SPIx));
01048   assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
01049
01050   /* Get the SPI_I2S IT index */
01051   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
01052
01053   /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
01054   SPIx->SR = (uint16_t)~itpos;
01055 }
01056
01057 /**
01058   * @}
01059   */
01060
01061 /**
01062   * @}
01063   */
01064
01065 /**
01066   * @}
01067   */
01068
01069 /**
01070   * @}
01071   */
01072
01073 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_spi.h Source File

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stm32l1xx_spi.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the SPI
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_SPI_H
00028 #define __STM32L1xx_SPI_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup SPI
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  SPI Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
00054                                          This parameter can be a value of @ref SPI_data_direction */
00055
00056   uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
00057                                          This parameter can be a value of @ref SPI_mode */
00058
00059   uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
00060                                          This parameter can be a value of @ref SPI_data_size */
00061
00062   uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
00063                                          This parameter can be a value of @ref SPI_Clock_Polarity */
00064
00065   uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
00066                                          This parameter can be a value of @ref SPI_Clock_Phase */
00067
00068   uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
00069                                          hardware (NSS pin) or by software using the SSI bit.
00070                                          This parameter can be a value of @ref SPI_Slave_Select_management */
00071
00072   uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00073                                          used to configure the transmit and receive SCK clock.
00074                                          This parameter can be a value of @ref SPI_BaudRate_Prescaler
00075                                          @note The communication clock is derived from the master
00076                                                clock. The slave clock does not need to be set. */
00077
00078   uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00079                                          This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00080
00081   uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
00082 }SPI_InitTypeDef;
00083
00084 /**
00085   * @brief  I2S Init structure definition
00086   */
00087
00088 typedef struct
00089 {
00090
00091   uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
00092                                   This parameter can be a value of @ref SPI_I2S_Mode */
00093
00094   uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
00095                                   This parameter can be a value of @ref SPI_I2S_Standard */
00096
00097   uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
00098                                   This parameter can be a value of @ref SPI_I2S_Data_Format */
00099
00100   uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
00101                                   This parameter can be a value of @ref SPI_I2S_MCLK_Output */
00102
00103   uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
00104                                   This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
00105
00106   uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
00107                                   This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
00108 }I2S_InitTypeDef;
00109
00110 /* Exported constants --------------------------------------------------------*/
00111
00112 /** @defgroup SPI_Exported_Constants
00113   * @{
00114   */
00115
00116 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
00117                                    ((PERIPH) == SPI2) || \
00118                                    ((PERIPH) == SPI3))
00119 #define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
00120                                    ((PERIPH) == SPI3))
00121
00122 /** @defgroup SPI_data_direction
00123   * @{
00124   */
00125
00126 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
00127 #define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
00128 #define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
00129 #define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
00130 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
00131                                      ((MODE) == SPI_Direction_2Lines_RxOnly) || \
00132                                      ((MODE) == SPI_Direction_1Line_Rx) || \
00133                                      ((MODE) == SPI_Direction_1Line_Tx))
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup SPI_mode
00139   * @{
00140   */
00141
00142 #define SPI_Mode_Master                 ((uint16_t)0x0104)
00143 #define SPI_Mode_Slave                  ((uint16_t)0x0000)
00144 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
00145                            ((MODE) == SPI_Mode_Slave))
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup SPI_data_size
00151   * @{
00152   */
00153
00154 #define SPI_DataSize_16b                ((uint16_t)0x0800)
00155 #define SPI_DataSize_8b                 ((uint16_t)0x0000)
00156 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
00157                                    ((DATASIZE) == SPI_DataSize_8b))
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup SPI_Clock_Polarity
00163   * @{
00164   */
00165
00166 #define SPI_CPOL_Low                    ((uint16_t)0x0000)
00167 #define SPI_CPOL_High                   ((uint16_t)0x0002)
00168 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
00169                            ((CPOL) == SPI_CPOL_High))
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup SPI_Clock_Phase
00175   * @{
00176   */
00177
00178 #define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
00179 #define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
00180 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
00181                            ((CPHA) == SPI_CPHA_2Edge))
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup SPI_Slave_Select_management
00187   * @{
00188   */
00189
00190 #define SPI_NSS_Soft                    ((uint16_t)0x0200)
00191 #define SPI_NSS_Hard                    ((uint16_t)0x0000)
00192 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
00193                          ((NSS) == SPI_NSS_Hard))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup SPI_BaudRate_Prescaler
00199   * @{
00200   */
00201
00202 #define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
00203 #define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
00204 #define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
00205 #define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
00206 #define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
00207 #define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
00208 #define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
00209 #define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
00210 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
00211                                               ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
00212                                               ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
00213                                               ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
00214                                               ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
00215                                               ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
00216                                               ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
00217                                               ((PRESCALER) == SPI_BaudRatePrescaler_256))
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup SPI_MSB_LSB_transmission
00223   * @{
00224   */
00225
00226 #define SPI_FirstBit_MSB                ((uint16_t)0x0000)
00227 #define SPI_FirstBit_LSB                ((uint16_t)0x0080)
00228 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
00229                                ((BIT) == SPI_FirstBit_LSB))
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup SPI_I2S_Mode
00235   * @{
00236   */
00237
00238 #define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
00239 #define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
00240 #define I2S_Mode_MasterTx               ((uint16_t)0x0200)
00241 #define I2S_Mode_MasterRx               ((uint16_t)0x0300)
00242 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
00243                            ((MODE) == I2S_Mode_SlaveRx) || \
00244                            ((MODE) == I2S_Mode_MasterTx)|| \
00245                            ((MODE) == I2S_Mode_MasterRx))
00246 /**
00247   * @}
00248   */
00249
00250
00251 /** @defgroup SPI_I2S_Standard
00252   * @{
00253   */
00254
00255 #define I2S_Standard_Phillips           ((uint16_t)0x0000)
00256 #define I2S_Standard_MSB                ((uint16_t)0x0010)
00257 #define I2S_Standard_LSB                ((uint16_t)0x0020)
00258 #define I2S_Standard_PCMShort           ((uint16_t)0x0030)
00259 #define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
00260 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
00261                                    ((STANDARD) == I2S_Standard_MSB) || \
00262                                    ((STANDARD) == I2S_Standard_LSB) || \
00263                                    ((STANDARD) == I2S_Standard_PCMShort) || \
00264                                    ((STANDARD) == I2S_Standard_PCMLong))
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup SPI_I2S_Data_Format
00270   * @{
00271   */
00272
00273 #define I2S_DataFormat_16b              ((uint16_t)0x0000)
00274 #define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
00275 #define I2S_DataFormat_24b              ((uint16_t)0x0003)
00276 #define I2S_DataFormat_32b              ((uint16_t)0x0005)
00277 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
00278                                     ((FORMAT) == I2S_DataFormat_16bextended) || \
00279                                     ((FORMAT) == I2S_DataFormat_24b) || \
00280                                     ((FORMAT) == I2S_DataFormat_32b))
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SPI_I2S_MCLK_Output
00286   * @{
00287   */
00288
00289 #define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
00290 #define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
00291 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
00292                                     ((OUTPUT) == I2S_MCLKOutput_Disable))
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup SPI_I2S_Audio_Frequency
00298   * @{
00299   */
00300
00301 #define I2S_AudioFreq_192k               ((uint32_t)192000)
00302 #define I2S_AudioFreq_96k                ((uint32_t)96000)
00303 #define I2S_AudioFreq_48k                ((uint32_t)48000)
00304 #define I2S_AudioFreq_44k                ((uint32_t)44100)
00305 #define I2S_AudioFreq_32k                ((uint32_t)32000)
00306 #define I2S_AudioFreq_22k                ((uint32_t)22050)
00307 #define I2S_AudioFreq_16k                ((uint32_t)16000)
00308 #define I2S_AudioFreq_11k                ((uint32_t)11025)
00309 #define I2S_AudioFreq_8k                 ((uint32_t)8000)
00310 #define I2S_AudioFreq_Default            ((uint32_t)2)
00311
00312 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
00313                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
00314                                  ((FREQ) == I2S_AudioFreq_Default))
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup SPI_I2S_Clock_Polarity
00320   * @{
00321   */
00322
00323 #define I2S_CPOL_Low                    ((uint16_t)0x0000)
00324 #define I2S_CPOL_High                   ((uint16_t)0x0008)
00325 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
00326                            ((CPOL) == I2S_CPOL_High))
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup SPI_I2S_DMA_transfer_requests
00332   * @{
00333   */
00334
00335 #define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
00336 #define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
00337 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup SPI_NSS_internal_software_management
00343   * @{
00344   */
00345
00346 #define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
00347 #define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
00348 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
00349                                        ((INTERNAL) == SPI_NSSInternalSoft_Reset))
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup SPI_CRC_Transmit_Receive
00355   * @{
00356   */
00357
00358 #define SPI_CRC_Tx                      ((uint8_t)0x00)
00359 #define SPI_CRC_Rx                      ((uint8_t)0x01)
00360 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup SPI_direction_transmit_receive
00366   * @{
00367   */
00368
00369 #define SPI_Direction_Rx                ((uint16_t)0xBFFF)
00370 #define SPI_Direction_Tx                ((uint16_t)0x4000)
00371 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
00372                                      ((DIRECTION) == SPI_Direction_Tx))
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup SPI_I2S_interrupts_definition
00378   * @{
00379   */
00380
00381 #define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
00382 #define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
00383 #define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
00384 #define I2S_IT_UDR                      ((uint8_t)0x53)
00385 #define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
00386
00387 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
00388                                   ((IT) == SPI_I2S_IT_RXNE) || \
00389                                   ((IT) == SPI_I2S_IT_ERR))
00390
00391 #define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
00392 #define SPI_IT_MODF                     ((uint8_t)0x55)
00393 #define SPI_IT_CRCERR                   ((uint8_t)0x54)
00394
00395 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
00396
00397 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
00398                                ((IT) == SPI_IT_CRCERR)   || ((IT) == SPI_IT_MODF) || \
00399                                ((IT) == SPI_I2S_IT_OVR)  || ((IT) == I2S_IT_UDR) ||\
00400                                ((IT) == SPI_I2S_IT_FRE))
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup SPI_I2S_flags_definition
00406   * @{
00407   */
00408
00409 #define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
00410 #define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
00411 #define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
00412 #define I2S_FLAG_UDR                    ((uint16_t)0x0008)
00413 #define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
00414 #define SPI_FLAG_MODF                   ((uint16_t)0x0020)
00415 #define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
00416 #define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
00417 #define SPI_I2S_FLAG_FRE                ((uint16_t)0x0100)
00418
00419 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
00420 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
00421                                    ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
00422                                    ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
00423                                    ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
00424                                    ((FLAG) == SPI_I2S_FLAG_FRE))
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup SPI_CRC_polynomial
00430   * @{
00431   */
00432
00433 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup SPI_I2S_Legacy
00439   * @{
00440   */
00441
00442 #define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
00443 #define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
00444 #define SPI_IT_TXE                   SPI_I2S_IT_TXE
00445 #define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
00446 #define SPI_IT_ERR                   SPI_I2S_IT_ERR
00447 #define SPI_IT_OVR                   SPI_I2S_IT_OVR
00448 #define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
00449 #define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
00450 #define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
00451 #define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
00452 #define SPI_DeInit                   SPI_I2S_DeInit
00453 #define SPI_ITConfig                 SPI_I2S_ITConfig
00454 #define SPI_DMACmd                   SPI_I2S_DMACmd
00455 #define SPI_SendData                 SPI_I2S_SendData
00456 #define SPI_ReceiveData              SPI_I2S_ReceiveData
00457 #define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
00458 #define SPI_ClearFlag                SPI_I2S_ClearFlag
00459 #define SPI_GetITStatus              SPI_I2S_GetITStatus
00460 #define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
00461 /**
00462   * @}
00463   */
00464
00465 /**
00466   * @}
00467   */
00468
00469 /* Exported macro ------------------------------------------------------------*/
00470 /* Exported functions ------------------------------------------------------- */
00471
00472 /*  Function used to set the SPI configuration to the default reset state *****/
00473 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
00474
00475 /* Initialization and Configuration functions *********************************/
00476 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
00477 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
00478 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
00479 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
00480 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00481 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00482 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
00483 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
00484 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
00485 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00486
00487 /* Data transfers functions ***************************************************/
00488 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
00489 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
00490
00491 /* Hardware CRC Calculation functions *****************************************/
00492 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
00493 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
00494 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
00495 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
00496
00497 /* DMA transfers management functions *****************************************/
00498 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
00499
00500 /* Interrupts and flags management functions **********************************/
00501 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
00502 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
00503 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
00504 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
00505 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
00506
00507 #ifdef __cplusplus
00508 }
00509 #endif
00510
00511 #endif /*__STM32L1xx_SPI_H */
00512
00513 /**
00514   * @}
00515   */
00516
00517 /**
00518   * @}
00519   */
00520
00521 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_syscfg.c Source File

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stm32l1xx_syscfg.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_syscfg.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the SYSCFG and RI peripherals:
00009   *           + SYSCFG Initialization and Configuration
00010   *           + RI Initialization and Configuration
00011   *
00012 @verbatim
00013  ===============================================================================
00014                      ##### How to use this driver #####
00015  ===============================================================================
00016     [..] This driver provides functions for:
00017          (#) Remapping the memory accessible in the code area using
00018           SYSCFG_MemoryRemapConfig().
00019          (#) Manage the EXTI lines connection to the GPIOs using
00020              SYSCFG_EXTILineConfig().
00021          (#) Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).
00022          (#) Input routing of COMP1 and COMP2.
00023          (#) Routing of internal reference voltage VREFINT to PB0 and PB1.
00024          (#) The RI registers can be accessed only when the comparator
00025              APB interface clock is enabled.
00026              To enable comparator clock use:
00027              RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
00028              Following functions uses RI registers:
00029              (++) SYSCFG_RIDeInit()
00030              (++) SYSCFG_RITIMSelect()
00031              (++) SYSCFG_RITIMInputCaptureConfig()
00032              (++) SYSCFG_RIResistorConfig()
00033              (++) SYSCFG_RIChannelSpeedConfig()
00034              (++) SYSCFG_RIIOSwitchConfig()
00035              (++) SYSCFG_RISwitchControlModeCmd()
00036              (++) SYSCFG_RIHysteresisConfig()
00037          (#) The SYSCFG registers can be accessed only when the SYSCFG
00038              interface APB clock is enabled.
00039              To enable SYSCFG APB clock use:
00040              RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00041              Following functions uses SYSCFG registers:
00042              (++) SYSCFG_DeInit()
00043              (++) SYSCFG_MemoryRemapConfig()
00044              (++) SYSCFG_GetBootMode()
00045              (++) SYSCFG_USBPuCmd()
00046              (++) SYSCFG_EXTILineConfig()
00047 @endverbatim
00048   *
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00053   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00054   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00055   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00056   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00057   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00058   *
00059   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00060   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00061   *
00062   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00063   ******************************************************************************
00064   */
00065
00066 /* Includes ------------------------------------------------------------------*/
00067 #include "stm32l1xx_syscfg.h"
00068 #include "stm32l1xx_rcc.h"
00069
00070 /** @addtogroup STM32L1xx_StdPeriph_Driver
00071   * @{
00072   */
00073
00074 /** @defgroup SYSCFG
00075   * @brief SYSCFG driver modules
00076   * @{
00077   */
00078
00079 /* Private typedef -----------------------------------------------------------*/
00080 /* Private define ------------------------------------------------------------*/
00081 #define TIM_SELECT_MASK             ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */
00082 #define IC_ROUTING_MASK             ((uint32_t)0x0000000F) /*!< Input Capture routing mask */
00083
00084 /* Private macro -------------------------------------------------------------*/
00085 /* Private variables ---------------------------------------------------------*/
00086 /* Private function prototypes -----------------------------------------------*/
00087 /* Private functions ---------------------------------------------------------*/
00088
00089 /** @defgroup SYSCFG_Private_Functions
00090   * @{
00091   */
00092
00093 /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
00094  *  @brief   SYSCFG Initialization and Configuration functions
00095  *
00096 @verbatim
00097  ===============================================================================
00098         ##### SYSCFG Initialization and Configuration functions #####
00099  ===============================================================================
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Deinitializes the SYSCFG registers to their default reset values.
00107   * @param  None.
00108   * @retval None.
00109   * @Note: MEMRMP bits are not reset by APB2 reset.
00110   */
00111 void SYSCFG_DeInit(void)
00112 {
00113    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00114    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
00115 }
00116
00117 /**
00118   * @brief Deinitializes the RI registers to their default reset values.
00119   * @param  None.
00120   * @retval None.
00121   */
00122 void SYSCFG_RIDeInit(void)
00123 {
00124   RI->ICR     = ((uint32_t)0x00000000);    /*!< Set RI->ICR to reset value */
00125   RI->ASCR1   = ((uint32_t)0x00000000);    /*!< Set RI->ASCR1 to reset value */
00126   RI->ASCR2   = ((uint32_t)0x00000000);    /*!< Set RI->ASCR2 to reset value */
00127   RI->HYSCR1  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR1 to reset value */
00128   RI->HYSCR2  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR2 to reset value */
00129   RI->HYSCR3  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR3 to reset value */
00130   RI->HYSCR4  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR4 to reset value */
00131 }
00132
00133 /**
00134   * @brief  Changes the mapping of the specified memory.
00135   * @param  SYSCFG_Memory: selects the memory remapping.
00136   *   This parameter can be one of the following values:
00137   *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
00138   *     @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
00139   *     @arg SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000
00140   *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
00141   * @retval None
00142   */
00143 void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
00144 {
00145   /* Check the parameters */
00146   assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
00147   SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
00148 }
00149
00150 /**
00151   * @brief  Returns the boot mode as configured by user.
00152   * @param  None.
00153   * @retval The boot mode as configured by user. The returned value can be one
00154   *         of the following values:
00155   *              - 0x00000000: Boot is configured in Main Flash memory
00156   *              - 0x00000100: Boot is configured in System Flash memory
00157   *              - 0x00000200: Boot is configured in FSMC memory
00158   *              - 0x00000300: Boot is configured in Embedded SRAM memory
00159   */
00160 uint32_t SYSCFG_GetBootMode(void)
00161 {
00162   return (SYSCFG->MEMRMP & SYSCFG_MEMRMP_BOOT_MODE);
00163 }
00164
00165 /**
00166   * @brief  Control the internal pull-up on USB DP line.
00167   * @param  NewState: New state of the internal pull-up on USB DP line.
00168   *   This parameter can be ENABLE: Connect internal pull-up on USB DP line.
00169   *                      or DISABLE: Disconnect internal pull-up on USB DP line.
00170   * @retval None
00171   */
00172 void SYSCFG_USBPuCmd(FunctionalState NewState)
00173 {
00174   /* Check the parameters */
00175   assert_param(IS_FUNCTIONAL_STATE(NewState));
00176
00177   if (NewState != DISABLE)
00178   {
00179     /* Connect internal pull-up on USB DP line */
00180     SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;
00181   }
00182   else
00183   {
00184     /* Disconnect internal pull-up on USB DP line */
00185     SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);
00186   }
00187 }
00188
00189 /**
00190   * @brief  Selects the GPIO pin used as EXTI Line.
00191   * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
00192   *                                for EXTI lines where x can be (A, B, C, D, E, F, G or H).
00193   * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
00194   *         This parameter can be EXTI_PinSourcex where x can be (0..15).
00195   * @retval None
00196   */
00197 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
00198 {
00199   uint32_t tmp = 0x00;
00200
00201   /* Check the parameters */
00202   assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
00203   assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
00204
00205   tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
00206   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
00207   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
00208 }
00209
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions
00215  *  @brief   RI Initialization and Configuration functions
00216  *
00217 @verbatim
00218  ===============================================================================
00219         ##### RI Initialization and Configuration functions #####
00220  ===============================================================================
00221
00222 @endverbatim
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Configures the routing interface to select which Timer to be routed.
00228   * @note   Routing capability can be applied only on one of the three timers
00229   *         (TIM2, TIM3 or TIM4) at a time.
00230   * @param  TIM_Select: Timer select.
00231   *   This parameter can be one of the following values:
00232   *     @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.
00233   *     @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.
00234   *     @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.
00235   *     @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.
00236   * @retval None.
00237   */
00238 void SYSCFG_RITIMSelect(uint32_t TIM_Select)
00239 {
00240   uint32_t tmpreg = 0;
00241
00242   /* Check the parameters */
00243   assert_param(IS_RI_TIM(TIM_Select));
00244
00245   /* Get the old register value */
00246   tmpreg = RI->ICR;
00247
00248   /* Clear the TIMx select bits */
00249   tmpreg &= TIM_SELECT_MASK;
00250
00251   /* Select the Timer */
00252   tmpreg |= (TIM_Select);
00253
00254   /* Write to RI->ICR register */
00255   RI->ICR = tmpreg;
00256 }
00257
00258 /**
00259   * @brief  Configures the routing interface to map Input Capture 1, 2, 3 or 4
00260   *         to a selected I/O pin.
00261   * @param  RI_InputCapture selects which input capture to be routed.
00262   *   This parameter can be one (or combination) of the following parameters:
00263   *     @arg  RI_InputCapture_IC1: Input capture 1 is selected.
00264   *     @arg  RI_InputCapture_IC2: Input capture 2 is selected.
00265   *     @arg  RI_InputCapture_IC3: Input capture 3 is selected.
00266   *     @arg  RI_InputCapture_IC4: Input capture 4 is selected.
00267   * @param  RI_InputCaptureRouting: selects which pin to be routed to Input Capture.
00268   *   This parameter can be one of the following values:
00269   * @param  RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15
00270   *     e.g.
00271   *       SYSCFG_RITIMSelect(TIM_Select_TIM2)
00272   *       SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)
00273   *       allows routing of Input capture IC1 of TIM2 to PA4.
00274   *       For details about correspondence between RI_InputCaptureRouting_x
00275   *       and I/O pins refer to the parameters' description in the header file
00276   *       or refer to the product reference manual.
00277   * @note Input capture selection bits are not reset by this function.
00278   *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.
00279   * @note The I/O should be configured in alternate function mode (AF14) using
00280   *       GPIO_PinAFConfig() function.
00281   * @retval None.
00282   */
00283 void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
00284 {
00285   uint32_t tmpreg = 0;
00286
00287   /* Check the parameters */
00288   assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
00289   assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));
00290
00291   /* Get the old register value */
00292   tmpreg = RI->ICR;
00293
00294   /* Select input captures to be routed */
00295   tmpreg |= (RI_InputCapture);
00296
00297   if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)
00298   {
00299     /* Clear the input capture select bits */
00300     tmpreg &= (uint32_t)(~IC_ROUTING_MASK);
00301
00302     /* Set RI_InputCaptureRouting bits  */
00303     tmpreg |= (uint32_t)( RI_InputCaptureRouting);
00304   }
00305
00306   if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)
00307   {
00308     /* Clear the input capture select bits */
00309     tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));
00310
00311     /* Set RI_InputCaptureRouting bits  */
00312     tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4));
00313   }
00314
00315   if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)
00316   {
00317     /* Clear the input capture select bits */
00318     tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));
00319
00320     /* Set RI_InputCaptureRouting bits  */
00321     tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));
00322   }
00323
00324   if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)
00325   {
00326     /* Clear the input capture select bits */
00327     tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));
00328
00329     /* Set RI_InputCaptureRouting bits  */
00330     tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));
00331   }
00332
00333   /* Write to RI->ICR register */
00334   RI->ICR = tmpreg;
00335 }
00336
00337 /**
00338   * @brief  Configures the Pull-up and Pull-down Resistors
00339   * @param  RI_Resistor selects the resistor to connect.
00340   *   This parameter can be  one of the following values:
00341   *     @arg RI_Resistor_10KPU: 10K pull-up resistor.
00342   *     @arg RI_Resistor_400KPU: 400K pull-up resistor.
00343   *     @arg RI_Resistor_10KPD: 10K pull-down resistor.
00344   *     @arg RI_Resistor_400KPD: 400K pull-down resistor.
00345   * @param  NewState: New state of the analog switch associated to the selected
00346   *         resistor.
00347   *   This parameter can be:
00348   *      ENABLE so the selected resistor is connected
00349   *      or DISABLE so the selected resistor is disconnected.
00350   * @note To avoid extra power consumption, only one resistor should be enabled
00351   *       at a time.
00352   * @retval None
00353   */
00354 void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)
00355 {
00356   /* Check the parameters */
00357   assert_param(IS_RI_RESISTOR(RI_Resistor));
00358   assert_param(IS_FUNCTIONAL_STATE(NewState));
00359
00360   if (NewState != DISABLE)
00361   {
00362     /* Enable the resistor */
00363     COMP->CSR |= (uint32_t) RI_Resistor;
00364   }
00365   else
00366   {
00367     /* Disable the Resistor */
00368     COMP->CSR &= (uint32_t) (~RI_Resistor);
00369   }
00370 }
00371
00372 /**
00373   * @brief  Configures the ADC channels speed.
00374   * @param  RI_Channel selects the channel.
00375   *   This parameter can be  one of the following values:
00376   *     @arg RI_Channel_3: Channel 3 is selected.
00377   *     @arg RI_Channel_8: Channel 8 is selected.
00378   *     @arg RI_Channel_13: Channel 13 is selected.
00379   * @param  RI_ChannelSpeed: The speed of the selected ADC channel
00380   *   This parameter can be:
00381   *      RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel
00382   *      or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.
00383   * @retval None
00384   */
00385 void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
00386 {
00387   /* Check the parameters */
00388   assert_param(IS_RI_CHANNEL(RI_Channel));
00389   assert_param(IS_RI_CHANNELSPEED(RI_ChannelSpeed));
00390
00391   if(RI_ChannelSpeed != RI_ChannelSpeed_Fast)
00392   {
00393     /* Set the selected channel as a slow ADC channel */
00394     COMP->CSR &= (uint32_t) (~RI_Channel);
00395   }
00396   else
00397   {
00398     /* Set the selected channel as a fast ADC channel */
00399     COMP->CSR |= (uint32_t) (RI_Channel);
00400   }
00401 }
00402
00403 /**
00404   * @brief  Close or Open the routing interface Input Output switches.
00405   * @param  RI_IOSwitch: selects the I/O analog switch number.
00406   *   This parameter can be one of the following values:
00407   * @param RI_IOSwitch_CH0 --> RI_IOSwitch_CH15.
00408   * @param RI_IOSwitch_CH18 --> RI_IOSwitch_CH25.
00409   * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4.
00410   * @param RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2.
00411   * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3.
00412   * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3.
00413   * @param RI_IOSwitch_VCOMP
00414   * RI_IOSwitch_CH27
00415   * @param RI_IOSwitch_CH28 --> RI_IOSwitch_CH30
00416   * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4
00417   * @param RI_IOSwitch_GR6_1
00418   * @param RI_IOSwitch_GR6_2
00419   * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3
00420   * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_4
00421   * @param RI_IOSwitch_CH0b --> RI_IOSwitch_CH3b
00422   * @param RI_IOSwitch_CH6b --> RI_IOSwitch_CH12b
00423   * @param RI_IOSwitch_GR6_3
00424   * @param RI_IOSwitch_GR6_4
00425   * @param RI_IOSwitch_GR5_4
00426
00427   * @param  NewState: New state of the analog switch.
00428   *   This parameter can be
00429   *     ENABLE so the Input Output switch is closed
00430   *     or DISABLE so the Input Output switch is open.
00431   * @retval None
00432   */
00433 void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)
00434 {
00435   uint32_t ioswitchmask = 0;
00436
00437   /* Check the parameters */
00438   assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
00439
00440   /* Read Analog switch register index */
00441   ioswitchmask = RI_IOSwitch >> 31;
00442
00443   /* Get Bits[30:0] of the IO switch */
00444   RI_IOSwitch  &= 0x7FFFFFFF;
00445
00446
00447   if (NewState != DISABLE)
00448   {
00449     if (ioswitchmask != 0)
00450     {
00451       /* Close the analog switches */
00452       RI->ASCR1 |= RI_IOSwitch;
00453     }
00454     else
00455     {
00456       /* Open the analog switches */
00457       RI->ASCR2 |= RI_IOSwitch;
00458     }
00459   }
00460   else
00461   {
00462     if (ioswitchmask != 0)
00463     {
00464       /* Close the analog switches */
00465       RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);
00466     }
00467     else
00468     {
00469       /* Open the analog switches */
00470       RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);
00471     }
00472   }
00473 }
00474
00475 /**
00476   * @brief  Enable or disable the switch control mode.
00477   * @param  NewState: New state of the switch control mode. This parameter can
00478   *         be ENABLE: ADC analog switches closed if the corresponding
00479   *                    I/O switch is also closed.
00480   *                    When using COMP1, switch control mode must be enabled.
00481   *         or DISABLE: ADC analog switches open or controlled by the ADC interface.
00482   *                    When using the ADC for acquisition, switch control mode
00483   *                    must be disabled.
00484   * @note COMP1 comparator and ADC cannot be used at the same time since
00485   *       they share the ADC switch matrix.
00486   * @retval None
00487   */
00488 void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)
00489 {
00490   /* Check the parameters */
00491   assert_param(IS_FUNCTIONAL_STATE(NewState));
00492
00493   if (NewState != DISABLE)
00494   {
00495     /* Enable the Switch control mode */
00496     RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;
00497   }
00498   else
00499   {
00500     /* Disable the Switch control mode */
00501     RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);
00502   }
00503 }
00504
00505 /**
00506   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A..E
00507   *         When the I/Os are programmed in input mode by standard I/O port
00508   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
00509   *         When hysteresis is disabled, it is possible to read the
00510   *         corresponding port with a trigger level of VDDIO/2.
00511   * @param  RI_Port: selects the GPIO Port.
00512   *   This parameter can be one of the following values:
00513   *     @arg RI_PortA: Port A is selected
00514   *     @arg RI_PortB: Port B is selected
00515   *     @arg RI_PortC: Port C is selected
00516   *     @arg RI_PortD: Port D is selected
00517   *     @arg RI_PortE: Port E is selected
00518   *     @arg RI_PortF: Port F is selected
00519   *     @arg RI_PortG: Port G is selected
00520   *  @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.
00521   *    This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
00522   *  @param  NewState new state of the Hysteresis.
00523   *   This parameter can be:
00524   *      ENABLE so the Hysteresis is on
00525   *      or DISABLE so the Hysteresis is off
00526   * @retval None
00527   */
00528 void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,
00529                              FunctionalState NewState)
00530 {
00531   /* Check the parameters */
00532   assert_param(IS_RI_PORT(RI_Port));
00533   assert_param(IS_RI_PIN(RI_Pin));
00534   assert_param(IS_FUNCTIONAL_STATE(NewState));
00535
00536   if(RI_Port == RI_PortA)
00537   {
00538     if (NewState != DISABLE)
00539     {
00540       /* Hysteresis on */
00541       RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);
00542     }
00543     else
00544     {
00545       /* Hysteresis off */
00546       RI->HYSCR1 |= (uint32_t) RI_Pin;
00547     }
00548   }
00549
00550   else if(RI_Port == RI_PortB)
00551   {
00552
00553     if (NewState != DISABLE)
00554     {
00555       /* Hysteresis on */
00556       RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
00557     }
00558     else
00559     {
00560       /* Hysteresis off */
00561       RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
00562     }
00563   }
00564
00565   else if(RI_Port == RI_PortC)
00566   {
00567
00568     if (NewState != DISABLE)
00569     {
00570       /* Hysteresis on */
00571       RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));
00572     }
00573     else
00574     {
00575       /* Hysteresis off */
00576       RI->HYSCR2 |= (uint32_t) (RI_Pin );
00577     }
00578   }
00579   else if(RI_Port == RI_PortD)
00580   {
00581     if (NewState != DISABLE)
00582     {
00583       /* Hysteresis on */
00584       RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
00585     }
00586     else
00587     {
00588       /* Hysteresis off */
00589       RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
00590
00591     }
00592   }
00593   else if(RI_Port == RI_PortE)
00594   {
00595     if (NewState != DISABLE)
00596     {
00597       /* Hysteresis on */
00598       RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));
00599     }
00600     else
00601     {
00602       /* Hysteresis off */
00603       RI->HYSCR3 |= (uint32_t) (RI_Pin );
00604     }
00605   }
00606   else if(RI_Port == RI_PortF)
00607   {
00608     if (NewState != DISABLE)
00609     {
00610       /* Hysteresis on */
00611       RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
00612     }
00613     else
00614     {
00615       /* Hysteresis off */
00616       RI->HYSCR3 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
00617     }
00618   }
00619   else /* RI_Port == RI_PortG */
00620   {
00621     if (NewState != DISABLE)
00622     {
00623       /* Hysteresis on */
00624       RI->HYSCR4 &= (uint32_t) (~((uint32_t)RI_Pin));
00625     }
00626     else
00627     {
00628       /* Hysteresis off */
00629       RI->HYSCR4 |= (uint32_t) (RI_Pin);
00630     }
00631   }
00632 }
00633
00634 /**
00635   * @}
00636   */
00637
00638 /**
00639   * @}
00640   */
00641
00642 /**
00643   * @}
00644   */
00645
00646 /**
00647   * @}
00648   */
00649 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_syscfg.h Source File

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stm32l1xx_syscfg.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_syscfg.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the SYSCFG
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /*!< Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_SYSCFG_H
00028 #define __STM32L1xx_SYSCFG_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /*!< Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup SYSCFG
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup SYSCFG_Exported_Constants
00049   * @{
00050   */
00051
00052 /** @defgroup EXTI_Port_Sources
00053   * @{
00054   */
00055 #define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
00056 #define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
00057 #define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
00058 #define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
00059 #define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
00060 #define EXTI_PortSourceGPIOH       ((uint8_t)0x05)
00061 #define EXTI_PortSourceGPIOF       ((uint8_t)0x06)
00062 #define EXTI_PortSourceGPIOG       ((uint8_t)0x07)
00063
00064 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
00065                                          ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
00066                                          ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
00067                                          ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
00068                                          ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
00069                                          ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
00070                                          ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
00071                                          ((PORTSOURCE) == EXTI_PortSourceGPIOH))
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup EXTI_Pin_sources
00077   * @{
00078   */
00079 #define EXTI_PinSource0            ((uint8_t)0x00)
00080 #define EXTI_PinSource1            ((uint8_t)0x01)
00081 #define EXTI_PinSource2            ((uint8_t)0x02)
00082 #define EXTI_PinSource3            ((uint8_t)0x03)
00083 #define EXTI_PinSource4            ((uint8_t)0x04)
00084 #define EXTI_PinSource5            ((uint8_t)0x05)
00085 #define EXTI_PinSource6            ((uint8_t)0x06)
00086 #define EXTI_PinSource7            ((uint8_t)0x07)
00087 #define EXTI_PinSource8            ((uint8_t)0x08)
00088 #define EXTI_PinSource9            ((uint8_t)0x09)
00089 #define EXTI_PinSource10           ((uint8_t)0x0A)
00090 #define EXTI_PinSource11           ((uint8_t)0x0B)
00091 #define EXTI_PinSource12           ((uint8_t)0x0C)
00092 #define EXTI_PinSource13           ((uint8_t)0x0D)
00093 #define EXTI_PinSource14           ((uint8_t)0x0E)
00094 #define EXTI_PinSource15           ((uint8_t)0x0F)
00095 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
00096                                        ((PINSOURCE) == EXTI_PinSource1) || \
00097                                        ((PINSOURCE) == EXTI_PinSource2) || \
00098                                        ((PINSOURCE) == EXTI_PinSource3) || \
00099                                        ((PINSOURCE) == EXTI_PinSource4) || \
00100                                        ((PINSOURCE) == EXTI_PinSource5) || \
00101                                        ((PINSOURCE) == EXTI_PinSource6) || \
00102                                        ((PINSOURCE) == EXTI_PinSource7) || \
00103                                        ((PINSOURCE) == EXTI_PinSource8) || \
00104                                        ((PINSOURCE) == EXTI_PinSource9) || \
00105                                        ((PINSOURCE) == EXTI_PinSource10) || \
00106                                        ((PINSOURCE) == EXTI_PinSource11) || \
00107                                        ((PINSOURCE) == EXTI_PinSource12) || \
00108                                        ((PINSOURCE) == EXTI_PinSource13) || \
00109                                        ((PINSOURCE) == EXTI_PinSource14) || \
00110                                        ((PINSOURCE) == EXTI_PinSource15))
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup SYSCFG_Memory_Remap_Config
00116   * @{
00117   */
00118 #define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)
00119 #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
00120 #define SYSCFG_MemoryRemap_FSMC        ((uint8_t)0x02)
00121 #define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)
00122
00123 #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
00124                                                ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
00125                                                ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \
00126                                                ((REMAP) == SYSCFG_MemoryRemap_SRAM))
00127
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup RI_Resistor
00133   * @{
00134   */
00135
00136 #define RI_Resistor_10KPU              COMP_CSR_10KPU
00137 #define RI_Resistor_400KPU             COMP_CSR_400KPU
00138 #define RI_Resistor_10KPD              COMP_CSR_10KPD
00139 #define RI_Resistor_400KPD             COMP_CSR_400KPD
00140
00141 #define IS_RI_RESISTOR(RESISTOR)  (((RESISTOR) == COMP_CSR_10KPU) || \
00142                                    ((RESISTOR) == COMP_CSR_400KPU) || \
00143                                    ((RESISTOR) == COMP_CSR_10KPD) || \
00144                                    ((RESISTOR) == COMP_CSR_400KPD))
00145
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup RI_Channel
00151   * @{
00152   */
00153
00154 #define RI_Channel_3                   ((uint32_t)0x04000000)
00155 #define RI_Channel_8                   ((uint32_t)0x08000000)
00156 #define RI_Channel_13                  ((uint32_t)0x10000000)
00157
00158 #define IS_RI_CHANNEL(CHANNEL)  (((CHANNEL) == RI_Channel_3) || \
00159                                  ((CHANNEL) == RI_Channel_8) || \
00160                                  ((CHANNEL) == RI_Channel_13))
00161
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup RI_ChannelSpeed
00167   * @{
00168   */
00169
00170 #define RI_ChannelSpeed_Fast           ((uint32_t)0x00000000)
00171 #define RI_ChannelSpeed_Slow           ((uint32_t)0x00000001)
00172
00173 #define IS_RI_CHANNELSPEED(SPEED)  (((SPEED) == RI_ChannelSpeed_Fast) || \
00174                                     ((SPEED) == RI_ChannelSpeed_Slow))
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup RI_InputCapture
00181   * @{
00182   */
00183
00184 #define RI_InputCapture_IC1  RI_ICR_IC1    /*!< Input Capture 1 */
00185 #define RI_InputCapture_IC2  RI_ICR_IC2    /*!< Input Capture 2 */
00186 #define RI_InputCapture_IC3  RI_ICR_IC3    /*!< Input Capture 3 */
00187 #define RI_InputCapture_IC4  RI_ICR_IC4    /*!< Input Capture 4 */
00188
00189 #define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup TIM_Select
00195   * @{
00196   */
00197
00198 #define TIM_Select_None  ((uint32_t)0x00000000)    /*!< None selected */
00199 #define TIM_Select_TIM2  ((uint32_t)0x00010000)    /*!< Timer 2 selected */
00200 #define TIM_Select_TIM3  ((uint32_t)0x00020000)    /*!< Timer 3 selected */
00201 #define TIM_Select_TIM4  ((uint32_t)0x00030000)    /*!< Timer 4 selected */
00202
00203 #define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \
00204                         ((TIM) == TIM_Select_TIM2) || \
00205                         ((TIM) == TIM_Select_TIM3) || \
00206                         ((TIM) == TIM_Select_TIM4))
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup RI_InputCaptureRouting
00213   * @{
00214   */
00215                                                           /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */
00216 #define RI_InputCaptureRouting_0   ((uint32_t)0x00000000) /* PA0       PA1      PA2       PA3      */
00217 #define RI_InputCaptureRouting_1   ((uint32_t)0x00000001) /* PA4       PA5      PA6       PA7      */
00218 #define RI_InputCaptureRouting_2   ((uint32_t)0x00000002) /* PA8       PA9      PA10      PA11     */
00219 #define RI_InputCaptureRouting_3   ((uint32_t)0x00000003) /* PA12      PA13     PA14      PA15     */
00220 #define RI_InputCaptureRouting_4   ((uint32_t)0x00000004) /* PC0       PC1      PC2       PC3      */
00221 #define RI_InputCaptureRouting_5   ((uint32_t)0x00000005) /* PC4       PC5      PC6       PC7      */
00222 #define RI_InputCaptureRouting_6   ((uint32_t)0x00000006) /* PC8       PC9      PC10      PC11     */
00223 #define RI_InputCaptureRouting_7   ((uint32_t)0x00000007) /* PC12      PC13     PC14      PC15     */
00224 #define RI_InputCaptureRouting_8   ((uint32_t)0x00000008) /* PD0       PD1      PD2       PD3      */
00225 #define RI_InputCaptureRouting_9   ((uint32_t)0x00000009) /* PD4       PD5      PD6       PD7      */
00226 #define RI_InputCaptureRouting_10  ((uint32_t)0x0000000A) /* PD8       PD9      PD10      PD11     */
00227 #define RI_InputCaptureRouting_11  ((uint32_t)0x0000000B) /* PD12      PD13     PD14      PD15     */
00228 #define RI_InputCaptureRouting_12  ((uint32_t)0x0000000C) /* PE0       PE1      PE2       PE3      */
00229 #define RI_InputCaptureRouting_13  ((uint32_t)0x0000000D) /* PE4       PE5      PE6       PE7      */
00230 #define RI_InputCaptureRouting_14  ((uint32_t)0x0000000E) /* PE8       PE9      PE10      PE11     */
00231 #define RI_InputCaptureRouting_15  ((uint32_t)0x0000000F) /* PE12      PE13     PE14      PE15     */
00232
00233 #define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \
00234                                              ((ROUTING) == RI_InputCaptureRouting_1) || \
00235                                              ((ROUTING) == RI_InputCaptureRouting_2) || \
00236                                              ((ROUTING) == RI_InputCaptureRouting_3) || \
00237                                              ((ROUTING) == RI_InputCaptureRouting_4) || \
00238                                              ((ROUTING) == RI_InputCaptureRouting_5) || \
00239                                              ((ROUTING) == RI_InputCaptureRouting_6) || \
00240                                              ((ROUTING) == RI_InputCaptureRouting_7) || \
00241                                              ((ROUTING) == RI_InputCaptureRouting_8) || \
00242                                              ((ROUTING) == RI_InputCaptureRouting_9) || \
00243                                              ((ROUTING) == RI_InputCaptureRouting_10) || \
00244                                              ((ROUTING) == RI_InputCaptureRouting_11) || \
00245                                              ((ROUTING) == RI_InputCaptureRouting_12) || \
00246                                              ((ROUTING) == RI_InputCaptureRouting_13) || \
00247                                              ((ROUTING) == RI_InputCaptureRouting_14) || \
00248                                              ((ROUTING) == RI_InputCaptureRouting_15))
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup RI_IOSwitch
00255   * @{
00256   */
00257
00258 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
00259 #define RI_IOSwitch_CH0        ((uint32_t)0x80000001)
00260 #define RI_IOSwitch_CH1        ((uint32_t)0x80000002)
00261 #define RI_IOSwitch_CH2        ((uint32_t)0x80000004)
00262 #define RI_IOSwitch_CH3        ((uint32_t)0x80000008)
00263 #define RI_IOSwitch_CH4        ((uint32_t)0x80000010)
00264 #define RI_IOSwitch_CH5        ((uint32_t)0x80000020)
00265 #define RI_IOSwitch_CH6        ((uint32_t)0x80000040)
00266 #define RI_IOSwitch_CH7        ((uint32_t)0x80000080)
00267 #define RI_IOSwitch_CH8        ((uint32_t)0x80000100)
00268 #define RI_IOSwitch_CH9        ((uint32_t)0x80000200)
00269 #define RI_IOSwitch_CH10       ((uint32_t)0x80000400)
00270 #define RI_IOSwitch_CH11       ((uint32_t)0x80000800)
00271 #define RI_IOSwitch_CH12       ((uint32_t)0x80001000)
00272 #define RI_IOSwitch_CH13       ((uint32_t)0x80002000)
00273 #define RI_IOSwitch_CH14       ((uint32_t)0x80004000)
00274 #define RI_IOSwitch_CH15       ((uint32_t)0x80008000)
00275 #define RI_IOSwitch_CH31       ((uint32_t)0x80010000)
00276 #define RI_IOSwitch_CH18       ((uint32_t)0x80040000)
00277 #define RI_IOSwitch_CH19       ((uint32_t)0x80080000)
00278 #define RI_IOSwitch_CH20       ((uint32_t)0x80100000)
00279 #define RI_IOSwitch_CH21       ((uint32_t)0x80200000)
00280 #define RI_IOSwitch_CH22       ((uint32_t)0x80400000)
00281 #define RI_IOSwitch_CH23       ((uint32_t)0x80800000)
00282 #define RI_IOSwitch_CH24       ((uint32_t)0x81000000)
00283 #define RI_IOSwitch_CH25       ((uint32_t)0x82000000)
00284 #define RI_IOSwitch_VCOMP      ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect
00285                                                          selected channel to COMP1 non inverting input */
00286 #define RI_IOSwitch_CH27       ((uint32_t)0x88000000)
00287 #define RI_IOSwitch_CH28       ((uint32_t)0x90000000)
00288 #define RI_IOSwitch_CH29       ((uint32_t)0xA0000000)
00289 #define RI_IOSwitch_CH30       ((uint32_t)0xC0000000)
00290
00291 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
00292 #define RI_IOSwitch_GR10_1     ((uint32_t)0x00000001)
00293 #define RI_IOSwitch_GR10_2     ((uint32_t)0x00000002)
00294 #define RI_IOSwitch_GR10_3     ((uint32_t)0x00000004)
00295 #define RI_IOSwitch_GR10_4     ((uint32_t)0x00000008)
00296 #define RI_IOSwitch_GR6_1      ((uint32_t)0x00000010)
00297 #define RI_IOSwitch_GR6_2      ((uint32_t)0x00000020)
00298 #define RI_IOSwitch_GR5_1      ((uint32_t)0x00000040)
00299 #define RI_IOSwitch_GR5_2      ((uint32_t)0x00000080)
00300 #define RI_IOSwitch_GR5_3      ((uint32_t)0x00000100)
00301 #define RI_IOSwitch_GR4_1      ((uint32_t)0x00000200)
00302 #define RI_IOSwitch_GR4_2      ((uint32_t)0x00000400)
00303 #define RI_IOSwitch_GR4_3      ((uint32_t)0x00000800)
00304 #define RI_IOSwitch_GR4_4      ((uint32_t)0x00008000)
00305 #define RI_IOSwitch_CH0b       ((uint32_t)0x00010000)
00306 #define RI_IOSwitch_CH1b       ((uint32_t)0x00020000)
00307 #define RI_IOSwitch_CH2b       ((uint32_t)0x00040000)
00308 #define RI_IOSwitch_CH3b       ((uint32_t)0x00080000)
00309 #define RI_IOSwitch_CH6b       ((uint32_t)0x00100000)
00310 #define RI_IOSwitch_CH7b       ((uint32_t)0x00200000)
00311 #define RI_IOSwitch_CH8b       ((uint32_t)0x00400000)
00312 #define RI_IOSwitch_CH9b       ((uint32_t)0x00800000)
00313 #define RI_IOSwitch_CH10b      ((uint32_t)0x01000000)
00314 #define RI_IOSwitch_CH11b      ((uint32_t)0x02000000)
00315 #define RI_IOSwitch_CH12b      ((uint32_t)0x04000000)
00316 #define RI_IOSwitch_GR6_3      ((uint32_t)0x08000000)
00317 #define RI_IOSwitch_GR6_4      ((uint32_t)0x10000000)
00318 #define RI_IOSwitch_GR5_4      ((uint32_t)0x20000000)
00319
00320
00321 #define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \
00322                                   ((IOSWITCH) == RI_IOSwitch_CH1) || \
00323                                   ((IOSWITCH) == RI_IOSwitch_CH2) || \
00324                                   ((IOSWITCH) == RI_IOSwitch_CH3) || \
00325                                   ((IOSWITCH) == RI_IOSwitch_CH4) || \
00326                                   ((IOSWITCH) == RI_IOSwitch_CH5) || \
00327                                   ((IOSWITCH) == RI_IOSwitch_CH6) || \
00328                                   ((IOSWITCH) == RI_IOSwitch_CH7) || \
00329                                   ((IOSWITCH) == RI_IOSwitch_CH8) || \
00330                                   ((IOSWITCH) == RI_IOSwitch_CH9) || \
00331                                   ((IOSWITCH) == RI_IOSwitch_CH10) || \
00332                                   ((IOSWITCH) == RI_IOSwitch_CH11) || \
00333                                   ((IOSWITCH) == RI_IOSwitch_CH12) || \
00334                                   ((IOSWITCH) == RI_IOSwitch_CH13) || \
00335                                   ((IOSWITCH) == RI_IOSwitch_CH14) || \
00336                                   ((IOSWITCH) == RI_IOSwitch_CH15) || \
00337                                   ((IOSWITCH) == RI_IOSwitch_CH18) || \
00338                                   ((IOSWITCH) == RI_IOSwitch_CH19) || \
00339                                   ((IOSWITCH) == RI_IOSwitch_CH20) || \
00340                                   ((IOSWITCH) == RI_IOSwitch_CH21) || \
00341                                   ((IOSWITCH) == RI_IOSwitch_CH22) || \
00342                                   ((IOSWITCH) == RI_IOSwitch_CH23) || \
00343                                   ((IOSWITCH) == RI_IOSwitch_CH24) || \
00344                                   ((IOSWITCH) == RI_IOSwitch_CH25) || \
00345                                   ((IOSWITCH) == RI_IOSwitch_VCOMP) || \
00346                                   ((IOSWITCH) == RI_IOSwitch_CH27) || \
00347                                   ((IOSWITCH) == RI_IOSwitch_CH28) || \
00348                                   ((IOSWITCH) == RI_IOSwitch_CH29) || \
00349                                   ((IOSWITCH) == RI_IOSwitch_CH30) || \
00350                                   ((IOSWITCH) == RI_IOSwitch_CH31) || \
00351                                   ((IOSWITCH) == RI_IOSwitch_GR10_1) || \
00352                                   ((IOSWITCH) == RI_IOSwitch_GR10_2) || \
00353                                   ((IOSWITCH) == RI_IOSwitch_GR10_3) || \
00354                                   ((IOSWITCH) == RI_IOSwitch_GR10_4) || \
00355                                   ((IOSWITCH) == RI_IOSwitch_GR6_1) || \
00356                                   ((IOSWITCH) == RI_IOSwitch_GR6_2) || \
00357                                   ((IOSWITCH) == RI_IOSwitch_GR6_3) || \
00358                                   ((IOSWITCH) == RI_IOSwitch_GR6_4) || \
00359                                   ((IOSWITCH) == RI_IOSwitch_GR5_1) || \
00360                                   ((IOSWITCH) == RI_IOSwitch_GR5_2) || \
00361                                   ((IOSWITCH) == RI_IOSwitch_GR5_3) || \
00362                                   ((IOSWITCH) == RI_IOSwitch_GR5_4) || \
00363                                   ((IOSWITCH) == RI_IOSwitch_GR4_1) || \
00364                                   ((IOSWITCH) == RI_IOSwitch_GR4_2) || \
00365                                   ((IOSWITCH) == RI_IOSwitch_GR4_3) || \
00366                                   ((IOSWITCH) == RI_IOSwitch_GR4_4) || \
00367                                   ((IOSWITCH) == RI_IOSwitch_CH0b) || \
00368                                   ((IOSWITCH) == RI_IOSwitch_CH1b) || \
00369                                   ((IOSWITCH) == RI_IOSwitch_CH2b) || \
00370                                   ((IOSWITCH) == RI_IOSwitch_CH3b) || \
00371                                   ((IOSWITCH) == RI_IOSwitch_CH6b) || \
00372                                   ((IOSWITCH) == RI_IOSwitch_CH7b) || \
00373                                   ((IOSWITCH) == RI_IOSwitch_CH8b) || \
00374                                   ((IOSWITCH) == RI_IOSwitch_CH9b) || \
00375                                   ((IOSWITCH) == RI_IOSwitch_CH10b) || \
00376                                   ((IOSWITCH) == RI_IOSwitch_CH11b) || \
00377                                   ((IOSWITCH) == RI_IOSwitch_CH12b))
00378
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup RI_Port
00384   * @{
00385   */
00386
00387 #define RI_PortA                 ((uint8_t)0x01)   /*!< GPIOA selected */
00388 #define RI_PortB                 ((uint8_t)0x02)   /*!< GPIOB selected */
00389 #define RI_PortC                 ((uint8_t)0x03)   /*!< GPIOC selected */
00390 #define RI_PortD                 ((uint8_t)0x04)   /*!< GPIOD selected */
00391 #define RI_PortE                 ((uint8_t)0x05)   /*!< GPIOE selected */
00392 #define RI_PortF                 ((uint8_t)0x06)   /*!< GPIOF selected */
00393 #define RI_PortG                 ((uint8_t)0x07)   /*!< GPIOG selected */
00394
00395 #define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \
00396                           ((PORT) == RI_PortB) || \
00397                           ((PORT) == RI_PortC) || \
00398                           ((PORT) == RI_PortD) || \
00399                           ((PORT) == RI_PortE) || \
00400                           ((PORT) == RI_PortF) || \
00401                           ((PORT) == RI_PortG))
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup RI_Pin define
00407   * @{
00408   */
00409 #define RI_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
00410 #define RI_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
00411 #define RI_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
00412 #define RI_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
00413 #define RI_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
00414 #define RI_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
00415 #define RI_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
00416 #define RI_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
00417 #define RI_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
00418 #define RI_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
00419 #define RI_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
00420 #define RI_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
00421 #define RI_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
00422 #define RI_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
00423 #define RI_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
00424 #define RI_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
00425 #define RI_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
00426
00427 #define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
00428
00429 /**
00430   * @}
00431   */
00432
00433 /**
00434   * @}
00435   */
00436
00437 /* Exported macro ------------------------------------------------------------*/
00438 /* Exported functions ------------------------------------------------------- */
00439
00440 /*  Function used to set the SYSCFG and RI configuration to the default reset state **/
00441 void SYSCFG_DeInit(void);
00442 void SYSCFG_RIDeInit(void);
00443
00444 /* SYSCFG Initialization and Configuration functions **************************/
00445 void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
00446 uint32_t SYSCFG_GetBootMode(void);
00447 void SYSCFG_USBPuCmd(FunctionalState NewState);
00448 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
00449
00450 /* RI Initialization and Configuration functions ******************************/
00451 void SYSCFG_RITIMSelect(uint32_t TIM_Select);
00452 void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);
00453 void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);
00454 void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed);
00455 void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);
00456 void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);
00457 void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState);
00458
00459 #ifdef __cplusplus
00460 }
00461 #endif
00462
00463 #endif /*__STM32L1xx_SYSCFG_H */
00464
00465 /**
00466   * @}
00467   */
00468
00469 /**
00470   * @}
00471   */
00472
00473 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_tim.c Source File

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stm32l1xx_tim.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the TIM peripheral:
00009   *            + TimeBase management
00010   *            + Output Compare management
00011   *            + Input Capture management
00012   *            + Interrupts, DMA and flags management
00013   *            + Clocks management
00014   *            + Synchronization management
00015   *            + Specific interface management
00016   *            + Specific remapping management
00017   *
00018 *  @verbatim
00019
00020  ===============================================================================
00021                     ##### How to use this driver #####
00022  ===============================================================================
00023     [..] This driver provides functions to configure and program the TIM
00024          of all STM32L1xx devices These functions are split in 8 groups:
00025          (#) TIM TimeBase management: this group includes all needed functions
00026              to configure the TM Timebase unit:
00027              (++) Set/Get Prescaler.
00028              (++) Set/Get Autoreload.
00029              (++) Counter modes configuration.
00030              (++) Set Clock division.
00031              (++) Select the One Pulse mode.
00032              (++) Update Request Configuration.
00033              (++) Update Disable Configuration.
00034              (++) Auto-Preload Configuration.
00035              (++) Enable/Disable the counter.
00036
00037          (#) TIM Output Compare management: this group includes all needed
00038              functions to configure the Capture/Compare unit used in Output
00039              compare mode:
00040              (++) Configure each channel, independently, in Output Compare mode.
00041              (++) Select the output compare modes.
00042              (++) Select the Polarities of each channel.
00043              (++) Set/Get the Capture/Compare register values.
00044              (++) Select the Output Compare Fast mode.
00045              (++) Select the Output Compare Forced mode.
00046              (++) Output Compare-Preload Configuration.
00047              (++) Clear Output Compare Reference.
00048              (++) Select the OCREF Clear signal.
00049              (++) Enable/Disable the Capture/Compare Channels.
00050
00051          (#) TIM Input Capture management: this group includes all needed
00052              functions to configure the Capture/Compare unit used in
00053              Input Capture mode:
00054              (++) Configure each channel in input capture mode.
00055              (++) Configure Channel1/2 in PWM Input mode.
00056              (++) Set the Input Capture Prescaler.
00057              (++) Get the Capture/Compare values.
00058
00059          (#) TIM interrupts, DMA and flags management.
00060              (++) Enable/Disable interrupt sources.
00061              (++) Get flags status.
00062              (++) Clear flags/ Pending bits.
00063              (++) Enable/Disable DMA requests.
00064              (++) Configure DMA burst mode.
00065              (++) Select CaptureCompare DMA request.
00066
00067          (#) TIM clocks management: this group includes all needed functions
00068              to configure the clock controller unit:
00069              (++) Select internal/External clock.
00070              (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
00071
00072          (#) TIM synchronization management: this group includes all needed.
00073              functions to configure the Synchronization unit:
00074              (++) Select Input Trigger.
00075              (++) Select Output Trigger.
00076              (++) Select Master Slave Mode.
00077              (++) ETR Configuration when used as external trigger.
00078
00079          (#) TIM specific interface management, this group includes all
00080              needed functions to use the specific TIM interface:
00081              (++) Encoder Interface Configuration.
00082              (++) Select Hall Sensor.
00083
00084          (#) TIM specific remapping management includes the Remapping
00085              configuration of specific timers
00086
00087 @endverbatim
00088
00089   ******************************************************************************
00090   * @attention
00091   *
00092   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00093   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00094   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00095   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00096   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00097   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00098   *
00099   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00100   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00101   *
00102   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00103   ******************************************************************************
00104   */
00105
00106 /* Includes ------------------------------------------------------------------*/
00107 #include "stm32l1xx_tim.h"
00108 #include "stm32l1xx_rcc.h"
00109
00110 /** @addtogroup STM32L1xx_StdPeriph_Driver
00111   * @{
00112   */
00113
00114 /** @defgroup TIM
00115   * @brief TIM driver modules
00116   * @{
00117   */
00118
00119 /* Private typedef -----------------------------------------------------------*/
00120 /* Private define ------------------------------------------------------------*/
00121
00122 /* ---------------------- TIM registers bit mask ------------------------ */
00123 #define SMCR_ETR_MASK               ((uint16_t)0x00FF)
00124 #define CCMR_OFFSET                 ((uint16_t)0x0018)
00125 #define CCER_CCE_SET                ((uint16_t)0x0001)
00126
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130
00131 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00132                        uint16_t TIM_ICFilter);
00133 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00134                        uint16_t TIM_ICFilter);
00135 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00136                        uint16_t TIM_ICFilter);
00137 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00138                        uint16_t TIM_ICFilter);
00139 /* Private functions ---------------------------------------------------------*/
00140
00141 /** @defgroup TIM_Private_Functions
00142   * @{
00143   */
00144
00145 /** @defgroup TIM_Group1 TimeBase management functions
00146  *  @brief   TimeBase management functions
00147  *
00148 @verbatim
00149  ===============================================================================
00150                  ##### TimeBase management functions #####
00151  ===============================================================================
00152
00153         *** TIM Driver: how to use it in Timing(Time base) Mode ***
00154  ===============================================================================
00155     [..] To use the Timer in Timing(Time base) mode, the following steps are
00156          mandatory:
00157          (#) Enable TIM clock using
00158              RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
00159          (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
00160          (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
00161              the Time Base unit with the corresponding configuration.
00162          (#) Enable the NVIC if you need to generate the update interrupt.
00163          (#) Enable the corresponding interrupt using the function
00164              TIM_ITConfig(TIMx, TIM_IT_Update).
00165          (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
00166     [..]
00167         (@) All other functions can be used seperatly to modify, if needed,
00168             a specific feature of the Timer.
00169
00170 @endverbatim
00171   * @{
00172   */
00173
00174 /**
00175   * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
00176   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00177   * @retval None
00178   *
00179   */
00180 void TIM_DeInit(TIM_TypeDef* TIMx)
00181 {
00182   /* Check the parameters */
00183   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00184
00185   if (TIMx == TIM2)
00186   {
00187     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
00188     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00189   }
00190   else if (TIMx == TIM3)
00191   {
00192     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00193     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
00194   }
00195   else if (TIMx == TIM4)
00196   {
00197     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
00198     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00199   }
00200   else if (TIMx == TIM5)
00201   {
00202     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00203     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00204   }
00205   else if (TIMx == TIM6)
00206   {
00207     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
00208     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00209   }
00210   else if (TIMx == TIM7)
00211   {
00212     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00213     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
00214   }
00215
00216   else if (TIMx == TIM9)
00217   {
00218     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
00219     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
00220   }
00221   else if (TIMx == TIM10)
00222   {
00223     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
00224     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
00225   }
00226   else
00227   {
00228     if (TIMx == TIM11)
00229     {
00230       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
00231       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
00232     }
00233   }
00234
00235 }
00236
00237 /**
00238   * @brief  Initializes the TIMx Time Base Unit peripheral according to
00239   *         the specified parameters in the TIM_TimeBaseInitStruct.
00240   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00241   * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
00242   *         structure that contains the configuration information for
00243   *         the specified TIM peripheral.
00244   * @retval None
00245   */
00246 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00247 {
00248   uint16_t tmpcr1 = 0;
00249
00250   /* Check the parameters */
00251   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00252   assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
00253   assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
00254
00255   tmpcr1 = TIMx->CR1;
00256
00257   if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4) || ((TIMx) == TIM5))
00258   {
00259     /* Select the Counter Mode */
00260     tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
00261     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00262   }
00263
00264   if(((TIMx) != TIM6) && ((TIMx) != TIM7))
00265   {
00266     /* Set the clock division */
00267     tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
00268     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
00269   }
00270
00271   TIMx->CR1 = tmpcr1;
00272
00273   /* Set the Autoreload value */
00274   TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
00275
00276   /* Set the Prescaler value */
00277   TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00278
00279   /* Generate an update event to reload the Prescaler value immediatly */
00280   TIMx->EGR = TIM_PSCReloadMode_Immediate;
00281 }
00282
00283 /**
00284   * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
00285   * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
00286   *         structure which will be initialized.
00287   * @retval None
00288   */
00289 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00290 {
00291   /* Set the default configuration */
00292   TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
00293   TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
00294   TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00295   TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00296 }
00297
00298 /**
00299   * @brief  Configures the TIMx Prescaler.
00300   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00301   * @param  Prescaler: specifies the Prescaler Register value.
00302   * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
00303   *   This parameter can be one of the following values:
00304   *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
00305   *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
00306   * @retval None
00307   */
00308 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
00309 {
00310   /* Check the parameters */
00311   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00312   assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
00313
00314   /* Set the Prescaler value */
00315   TIMx->PSC = Prescaler;
00316   /* Set or reset the UG Bit */
00317   TIMx->EGR = TIM_PSCReloadMode;
00318 }
00319
00320 /**
00321   * @brief  Specifies the TIMx Counter Mode to be used.
00322   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
00323   * @param  TIM_CounterMode: specifies the Counter Mode to be used
00324   *   This parameter can be one of the following values:
00325   *     @arg TIM_CounterMode_Up: TIM Up Counting Mode.
00326   *     @arg TIM_CounterMode_Down: TIM Down Counting Mode.
00327   *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1.
00328   *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2.
00329   *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3.
00330   * @retval None
00331   */
00332 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
00333 {
00334   uint16_t tmpcr1 = 0;
00335
00336   /* Check the parameters */
00337   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00338   assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
00339
00340   tmpcr1 = TIMx->CR1;
00341   /* Reset the CMS and DIR Bits */
00342   tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
00343   /* Set the Counter Mode */
00344   tmpcr1 |= TIM_CounterMode;
00345   /* Write to TIMx CR1 register */
00346   TIMx->CR1 = tmpcr1;
00347 }
00348
00349 /**
00350   * @brief  Sets the TIMx Counter Register value
00351   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00352   * @param  Counter: specifies the Counter register new value.
00353   * @retval None
00354   */
00355 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
00356 {
00357   /* Check the parameters */
00358    assert_param(IS_TIM_ALL_PERIPH(TIMx));
00359
00360   /* Set the Counter Register value */
00361   TIMx->CNT = Counter;
00362 }
00363
00364 /**
00365   * @brief  Sets the TIMx Autoreload Register value
00366   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00367   * @param  Autoreload: specifies the Autoreload register new value.
00368   * @retval None
00369   */
00370 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
00371 {
00372   /* Check the parameters */
00373   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00374
00375   /* Set the Autoreload Register value */
00376   TIMx->ARR = Autoreload;
00377 }
00378
00379 /**
00380   * @brief  Gets the TIMx Counter value.
00381   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00382   * @retval Counter Register value.
00383   */
00384 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
00385 {
00386   /* Check the parameters */
00387   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00388
00389   /* Get the Counter Register value */
00390   return TIMx->CNT;
00391 }
00392
00393 /**
00394   * @brief  Gets the TIMx Prescaler value.
00395   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00396   * @retval Prescaler Register value.
00397   */
00398 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
00399 {
00400   /* Check the parameters */
00401   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00402
00403   /* Get the Prescaler Register value */
00404   return TIMx->PSC;
00405 }
00406
00407 /**
00408   * @brief  Enables or Disables the TIMx Update event.
00409   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00410   * @param  NewState: new state of the TIMx UDIS bit
00411   *   This parameter can be: ENABLE or DISABLE.
00412   * @retval None
00413   */
00414 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
00415 {
00416   /* Check the parameters */
00417   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00418   assert_param(IS_FUNCTIONAL_STATE(NewState));
00419
00420   if (NewState != DISABLE)
00421   {
00422     /* Set the Update Disable Bit */
00423     TIMx->CR1 |= TIM_CR1_UDIS;
00424   }
00425   else
00426   {
00427     /* Reset the Update Disable Bit */
00428     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
00429   }
00430 }
00431
00432 /**
00433   * @brief  Configures the TIMx Update Request Interrupt source.
00434   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00435   * @param  TIM_UpdateSource: specifies the Update source.
00436   *   This parameter can be one of the following values:
00437   *     @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow
00438                                        or the setting of UG bit, or an update generation
00439                                        through the slave mode controller.
00440   *     @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
00441   * @retval None
00442   */
00443 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
00444 {
00445   /* Check the parameters */
00446   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00447   assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
00448
00449   if (TIM_UpdateSource != TIM_UpdateSource_Global)
00450   {
00451     /* Set the URS Bit */
00452     TIMx->CR1 |= TIM_CR1_URS;
00453   }
00454   else
00455   {
00456     /* Reset the URS Bit */
00457     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
00458   }
00459 }
00460
00461 /**
00462   * @brief  Enables or disables TIMx peripheral Preload register on ARR.
00463   * @param  TIMx: where x can be  2 to 11 to select the TIM peripheral.
00464   * @param  NewState: new state of the TIMx peripheral Preload register
00465   *   This parameter can be: ENABLE or DISABLE.
00466   * @retval None
00467   */
00468 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
00469 {
00470   /* Check the parameters */
00471   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00472   assert_param(IS_FUNCTIONAL_STATE(NewState));
00473
00474   if (NewState != DISABLE)
00475   {
00476     /* Set the ARR Preload Bit */
00477     TIMx->CR1 |= TIM_CR1_ARPE;
00478   }
00479   else
00480   {
00481     /* Reset the ARR Preload Bit */
00482     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
00483   }
00484 }
00485
00486 /**
00487   * @brief  Selects the TIMx's One Pulse Mode.
00488   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
00489   * @param  TIM_OPMode: specifies the OPM Mode to be used.
00490   *   This parameter can be one of the following values:
00491   *     @arg TIM_OPMode_Single:: TIM One Pulse Single Mode (Counter stops counting
00492   *                              at the next update event (clearing the bit CEN)).
00493   *     @arg TIM_OPMode_Repetitive: TIM One Pulse Repetitive Mode
00494   *                                 (Counter is not stopped at update event).
00495   * @retval None
00496   */
00497 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
00498 {
00499   /* Check the parameters */
00500   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00501   assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
00502
00503   /* Reset the OPM Bit */
00504   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
00505   /* Configure the OPM Mode */
00506   TIMx->CR1 |= TIM_OPMode;
00507 }
00508
00509 /**
00510   * @brief  Sets the TIMx Clock Division value.
00511   * @param  TIMx: where x can be  2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
00512   * @param  TIM_CKD: specifies the clock division value.
00513   *   This parameter can be one of the following value:
00514   *     @arg TIM_CKD_DIV1: TDTS = Tck_tim.
00515   *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim.
00516   *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim.
00517   * @retval None
00518   */
00519 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
00520 {
00521   /* Check the parameters */
00522   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00523   assert_param(IS_TIM_CKD_DIV(TIM_CKD));
00524
00525   /* Reset the CKD Bits */
00526   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
00527   /* Set the CKD value */
00528   TIMx->CR1 |= TIM_CKD;
00529 }
00530
00531 /**
00532   * @brief  Enables or disables the specified TIM peripheral.
00533   * @param  TIMx: where x can be 2 to 11 to select the TIMx peripheral.
00534   * @param  NewState: new state of the TIMx peripheral.
00535   *         This parameter can be: ENABLE or DISABLE.
00536   * @retval None
00537   */
00538 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
00539 {
00540   /* Check the parameters */
00541   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00542   assert_param(IS_FUNCTIONAL_STATE(NewState));
00543
00544   if (NewState != DISABLE)
00545   {
00546     /* Enable the TIM Counter */
00547     TIMx->CR1 |= TIM_CR1_CEN;
00548   }
00549   else
00550   {
00551     /* Disable the TIM Counter */
00552     TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
00553   }
00554 }
00555
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup TIM_Group2 Output Compare management functions
00561  *  @brief    Output Compare management functions
00562  *
00563 @verbatim
00564  ===============================================================================
00565                 ##### Output Compare management functions #####
00566  ===============================================================================
00567         *** TIM Driver: how to use it in Output Compare Mode ***
00568  ===============================================================================
00569     [..] To use the Timer in Output Compare mode, the following steps are mandatory:
00570          (#) Enable TIM clock using
00571              RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
00572          (#) Configure the TIM pins by configuring the corresponding GPIO pins
00573          (#) Configure the Time base unit as described in the first part of this
00574              driver, if needed, else the Timer will run with the default
00575              configuration:
00576              (++) Autoreload value = 0xFFFF.
00577              (++) Prescaler value = 0x0000.
00578              (++) Counter mode = Up counting.
00579              (++) Clock Division = TIM_CKD_DIV1.
00580          (#) Fill the TIM_OCInitStruct with the desired parameters including:
00581              (++) The TIM Output Compare mode: TIM_OCMode.
00582              (++) TIM Output State: TIM_OutputState.
00583              (++) TIM Pulse value: TIM_Pulse.
00584              (++) TIM Output Compare Polarity : TIM_OCPolarity.
00585          (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
00586              channel with the corresponding configuration.
00587          (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
00588     [..]
00589         (@) All other functions can be used separately to modify, if needed,
00590           a specific feature of the Timer.
00591         (@) In case of PWM mode, this function is mandatory:
00592             TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
00593         (@) If the corresponding interrupt or DMA request are needed, the user should:
00594             (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
00595             (#@) Enable the corresponding interrupt (or DMA request) using the function
00596                  TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
00597
00598 @endverbatim
00599   * @{
00600   */
00601
00602 /**
00603   * @brief  Initializes the TIMx Channel1 according to the specified
00604   *         parameters in the TIM_OCInitStruct.
00605   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
00606   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00607   *         that contains the configuration information for the specified TIM
00608   *         peripheral.
00609   * @retval None
00610   */
00611 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00612 {
00613   uint16_t tmpccmrx = 0, tmpccer = 0;
00614
00615   /* Check the parameters */
00616   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00617   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00618   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00619   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00620   /* Disable the Channel 1: Reset the CC1E Bit */
00621   TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
00622
00623   /* Get the TIMx CCER register value */
00624   tmpccer = TIMx->CCER;
00625
00626   /* Get the TIMx CCMR1 register value */
00627   tmpccmrx = TIMx->CCMR1;
00628
00629   /* Reset the Output Compare Mode Bits */
00630   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
00631   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
00632
00633   /* Select the Output Compare Mode */
00634   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00635
00636   /* Reset the Output Polarity level */
00637   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
00638   /* Set the Output Compare Polarity */
00639   tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00640
00641   /* Set the Output State */
00642   tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00643
00644   /* Set the Capture Compare Register value */
00645   TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
00646
00647   /* Write to TIMx CCMR1 */
00648   TIMx->CCMR1 = tmpccmrx;
00649
00650   /* Write to TIMx CCER */
00651   TIMx->CCER = tmpccer;
00652 }
00653
00654 /**
00655   * @brief  Initializes the TIMx Channel2 according to the specified
00656   *         parameters in the TIM_OCInitStruct.
00657   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
00658   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00659   *         that contains the configuration information for the specified TIM
00660   *         peripheral.
00661   * @retval None
00662   */
00663 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00664 {
00665   uint16_t tmpccmrx = 0, tmpccer = 0;
00666
00667   /* Check the parameters */
00668   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00669   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00670   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00671   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00672   /* Disable the Channel 2: Reset the CC2E Bit */
00673   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
00674
00675   /* Get the TIMx CCER register value */
00676   tmpccer = TIMx->CCER;
00677
00678   /* Get the TIMx CCMR1 register value */
00679   tmpccmrx = TIMx->CCMR1;
00680
00681   /* Reset the Output Compare Mode Bits */
00682   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
00683
00684   /* Select the Output Compare Mode */
00685   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00686
00687   /* Reset the Output Polarity level */
00688   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
00689   /* Set the Output Compare Polarity */
00690   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
00691
00692   /* Set the Output State */
00693   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
00694
00695   /* Set the Capture Compare Register value */
00696   TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
00697
00698   /* Write to TIMx CCMR1 */
00699   TIMx->CCMR1 = tmpccmrx;
00700
00701   /* Write to TIMx CCER */
00702   TIMx->CCER = tmpccer;
00703 }
00704
00705 /**
00706   * @brief  Initializes the TIMx Channel3 according to the specified
00707   *         parameters in the TIM_OCInitStruct.
00708   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
00709   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00710   *         that contains the configuration information for the specified TIM
00711   *         peripheral.
00712   * @retval None
00713   */
00714 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00715 {
00716   uint16_t tmpccmrx = 0, tmpccer = 0;
00717
00718   /* Check the parameters */
00719   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00720   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00721   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00722   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00723
00724   /* Disable the Channel 2: Reset the CC2E Bit */
00725   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
00726
00727   /* Get the TIMx CCER register value */
00728   tmpccer = TIMx->CCER;
00729
00730   /* Get the TIMx CCMR2 register value */
00731   tmpccmrx = TIMx->CCMR2;
00732
00733   /* Reset the Output Compare Mode Bits */
00734   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
00735
00736   /* Select the Output Compare Mode */
00737   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00738
00739   /* Reset the Output Polarity level */
00740   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
00741   /* Set the Output Compare Polarity */
00742   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
00743
00744   /* Set the Output State */
00745   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
00746
00747   /* Set the Capture Compare Register value */
00748   TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
00749
00750   /* Write to TIMx CCMR2 */
00751   TIMx->CCMR2 = tmpccmrx;
00752
00753   /* Write to TIMx CCER */
00754   TIMx->CCER = tmpccer;
00755 }
00756
00757 /**
00758   * @brief  Initializes the TIMx Channel4 according to the specified
00759   *         parameters in the TIM_OCInitStruct.
00760   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
00761   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00762   *         that contains the configuration information for the specified TIM
00763   *         peripheral.
00764   * @retval None
00765   */
00766 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00767 {
00768   uint16_t tmpccmrx = 0, tmpccer = 0;
00769
00770   /* Check the parameters */
00771   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00772   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00773   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00774   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00775
00776   /* Disable the Channel 2: Reset the CC4E Bit */
00777   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
00778
00779   /* Get the TIMx CCER register value */
00780   tmpccer = TIMx->CCER;
00781
00782   /* Get the TIMx CCMR2 register value */
00783   tmpccmrx = TIMx->CCMR2;
00784
00785   /* Reset the Output Compare Mode Bits */
00786   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
00787
00788   /* Select the Output Compare Mode */
00789   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00790
00791   /* Reset the Output Polarity level */
00792   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
00793   /* Set the Output Compare Polarity */
00794   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
00795
00796   /* Set the Output State */
00797   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
00798
00799   /* Set the Capture Compare Register value */
00800   TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
00801
00802   /* Write to TIMx CCMR2 */
00803   TIMx->CCMR2 = tmpccmrx;
00804
00805   /* Write to TIMx CCER */
00806   TIMx->CCER = tmpccer;
00807 }
00808
00809 /**
00810   * @brief  Fills each TIM_OCInitStruct member with its default value.
00811   * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
00812   *         be initialized.
00813   * @retval None
00814   */
00815 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
00816 {
00817   /* Set the default configuration */
00818   TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
00819   TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
00820   TIM_OCInitStruct->TIM_Pulse = 0x0000;
00821   TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00822 }
00823
00824 /**
00825   * @brief  Selects the TIM Output Compare Mode.
00826   * @note   This function disables the selected channel before changing the Output
00827   *         Compare Mode.
00828   *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
00829   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
00830   * @param  TIM_Channel: specifies the TIM Channel.
00831   *   This parameter can be one of the following values:
00832   *     @arg TIM_Channel_1: TIM Channel 1.
00833   *     @arg TIM_Channel_2: TIM Channel 2.
00834   *     @arg TIM_Channel_3: TIM Channel 3.
00835   *     @arg TIM_Channel_4: TIM Channel 4.
00836   * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
00837   *   This parameter can be one of the following values:
00838   *     @arg TIM_OCMode_Timing: TIM Output Compare Timing mode.
00839   *     @arg TIM_OCMode_Active: TIM Output Compare Active mode.
00840   *     @arg TIM_OCMode_Inactive: TIM Output Compare Inactive mode.
00841   *     @arg TIM_OCMode_Toggle: TIM Output Compare Toggle mode.
00842   *     @arg TIM_OCMode_PWM1: TIM Output Compare PWM1 mode.
00843   *     @arg TIM_OCMode_PWM2: TIM Output Compare PWM2 mode.
00844   *     @arg TIM_ForcedAction_Active: TIM Forced Action Active mode.
00845   *     @arg TIM_ForcedAction_InActive: TIM Forced Action Inactive mode.
00846   * @retval None
00847   */
00848 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
00849 {
00850   uint32_t tmp = 0;
00851   uint16_t tmp1 = 0;
00852
00853   /* Check the parameters */
00854   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00855   assert_param(IS_TIM_OCM(TIM_OCMode));
00856
00857   tmp = (uint32_t) TIMx;
00858   tmp += CCMR_OFFSET;
00859
00860   tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
00861
00862   /* Disable the Channel: Reset the CCxE Bit */
00863   TIMx->CCER &= (uint16_t) ~tmp1;
00864
00865   if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
00866   {
00867     tmp += (TIM_Channel>>1);
00868
00869     /* Reset the OCxM bits in the CCMRx register */
00870     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
00871
00872     /* Configure the OCxM bits in the CCMRx register */
00873     *(__IO uint32_t *) tmp |= TIM_OCMode;
00874   }
00875   else
00876   {
00877     tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
00878
00879     /* Reset the OCxM bits in the CCMRx register */
00880     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
00881
00882     /* Configure the OCxM bits in the CCMRx register */
00883     *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
00884   }
00885 }
00886
00887 /**
00888   * @brief  Sets the TIMx Capture Compare1 Register value
00889   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
00890   * @param  Compare1: specifies the Capture Compare1 register new value.
00891   * @retval None
00892   */
00893 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
00894 {
00895   /* Check the parameters */
00896   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00897
00898   /* Set the Capture Compare1 Register value */
00899   TIMx->CCR1 = Compare1;
00900 }
00901
00902 /**
00903   * @brief  Sets the TIMx Capture Compare2 Register value.
00904   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
00905   * @param  Compare2: specifies the Capture Compare2 register new value.
00906   * @retval None
00907   */
00908 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
00909 {
00910   /* Check the parameters */
00911   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00912
00913   /* Set the Capture Compare2 Register value */
00914   TIMx->CCR2 = Compare2;
00915 }
00916
00917 /**
00918   * @brief  Sets the TIMx Capture Compare3 Register value.
00919   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
00920   * @param  Compare3: specifies the Capture Compare3 register new value.
00921   * @retval None
00922   */
00923 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
00924 {
00925   /* Check the parameters */
00926   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00927
00928   /* Set the Capture Compare3 Register value */
00929   TIMx->CCR3 = Compare3;
00930 }
00931
00932 /**
00933   * @brief  Sets the TIMx Capture Compare4 Register value.
00934   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
00935   * @param  Compare4: specifies the Capture Compare4 register new value.
00936   * @retval None
00937   */
00938 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
00939 {
00940   /* Check the parameters */
00941   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00942
00943   /* Set the Capture Compare4 Register value */
00944   TIMx->CCR4 = Compare4;
00945 }
00946
00947 /**
00948   * @brief  Forces the TIMx output 1 waveform to active or inactive level.
00949   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
00950   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
00951   *   This parameter can be one of the following values:
00952   *     @arg TIM_ForcedAction_Active: Force active level on OC1REF.
00953   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
00954   * @retval None
00955   */
00956 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
00957 {
00958   uint16_t tmpccmr1 = 0;
00959   /* Check the parameters */
00960   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00961   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
00962   tmpccmr1 = TIMx->CCMR1;
00963   /* Reset the OC1M Bits */
00964   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
00965   /* Configure The Forced output Mode */
00966   tmpccmr1 |= TIM_ForcedAction;
00967   /* Write to TIMx CCMR1 register */
00968   TIMx->CCMR1 = tmpccmr1;
00969 }
00970
00971 /**
00972   * @brief  Forces the TIMx output 2 waveform to active or inactive level.
00973   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM
00974   *   peripheral.
00975   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
00976   *   This parameter can be one of the following values:
00977   *     @arg TIM_ForcedAction_Active: Force active level on OC2REF.
00978   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
00979   * @retval None
00980   */
00981 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
00982 {
00983   uint16_t tmpccmr1 = 0;
00984
00985   /* Check the parameters */
00986   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00987   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
00988
00989   tmpccmr1 = TIMx->CCMR1;
00990   /* Reset the OC2M Bits */
00991   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
00992   /* Configure The Forced output Mode */
00993   tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
00994   /* Write to TIMx CCMR1 register */
00995   TIMx->CCMR1 = tmpccmr1;
00996 }
00997
00998 /**
00999   * @brief  Forces the TIMx output 3 waveform to active or inactive level.
01000   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01001   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01002   *   This parameter can be one of the following values:
01003   *     @arg TIM_ForcedAction_Active: Force active level on OC3REF.
01004   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
01005   * @retval None
01006   */
01007 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01008 {
01009   uint16_t tmpccmr2 = 0;
01010
01011   /* Check the parameters */
01012   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01013   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01014
01015   tmpccmr2 = TIMx->CCMR2;
01016   /* Reset the OC1M Bits */
01017   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
01018   /* Configure The Forced output Mode */
01019   tmpccmr2 |= TIM_ForcedAction;
01020   /* Write to TIMx CCMR2 register */
01021   TIMx->CCMR2 = tmpccmr2;
01022 }
01023
01024 /**
01025   * @brief  Forces the TIMx output 4 waveform to active or inactive level.
01026   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01027   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01028   *   This parameter can be one of the following values:
01029   *     @arg TIM_ForcedAction_Active: Force active level on OC4REF.
01030   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
01031   * @retval None
01032   */
01033 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01034 {
01035   uint16_t tmpccmr2 = 0;
01036   /* Check the parameters */
01037   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01038   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01039
01040   tmpccmr2 = TIMx->CCMR2;
01041   /* Reset the OC2M Bits */
01042   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
01043   /* Configure The Forced output Mode */
01044   tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
01045   /* Write to TIMx CCMR2 register */
01046   TIMx->CCMR2 = tmpccmr2;
01047 }
01048
01049 /**
01050   * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
01051   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01052   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register.
01053   *   This parameter can be one of the following values:
01054   *     @arg TIM_OCPreload_Enable: Enable TIM output compare Preload
01055   *     @arg TIM_OCPreload_Disable: Disable TIM output compare Preload
01056   * @retval None
01057   */
01058 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01059 {
01060   uint16_t tmpccmr1 = 0;
01061   /* Check the parameters */
01062   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01063   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01064
01065   tmpccmr1 = TIMx->CCMR1;
01066   /* Reset the OC1PE Bit */
01067   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
01068   /* Enable or Disable the Output Compare Preload feature */
01069   tmpccmr1 |= TIM_OCPreload;
01070   /* Write to TIMx CCMR1 register */
01071   TIMx->CCMR1 = tmpccmr1;
01072 }
01073
01074 /**
01075   * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
01076   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01077   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register.
01078   *   This parameter can be one of the following values:
01079   *     @arg TIM_OCPreload_Enable: Enable TIM output compare Preload
01080   *     @arg TIM_OCPreload_Disable: Disable TIM output compare Preload
01081   * @retval None
01082   */
01083 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01084 {
01085   uint16_t tmpccmr1 = 0;
01086   /* Check the parameters */
01087   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01088   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01089
01090   tmpccmr1 = TIMx->CCMR1;
01091   /* Reset the OC2PE Bit */
01092   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
01093   /* Enable or Disable the Output Compare Preload feature */
01094   tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
01095   /* Write to TIMx CCMR1 register */
01096   TIMx->CCMR1 = tmpccmr1;
01097 }
01098
01099 /**
01100   * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
01101   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01102   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register.
01103   *   This parameter can be one of the following values:
01104   *     @arg TIM_OCPreload_Enable: Enable TIM output compare Preload
01105   *     @arg TIM_OCPreload_Disable: Disable TIM output compare Preload
01106   * @retval None
01107   */
01108 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01109 {
01110   uint16_t tmpccmr2 = 0;
01111
01112   /* Check the parameters */
01113   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01114   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01115
01116   tmpccmr2 = TIMx->CCMR2;
01117   /* Reset the OC3PE Bit */
01118   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
01119   /* Enable or Disable the Output Compare Preload feature */
01120   tmpccmr2 |= TIM_OCPreload;
01121   /* Write to TIMx CCMR2 register */
01122   TIMx->CCMR2 = tmpccmr2;
01123 }
01124
01125 /**
01126   * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
01127   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01128   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register.
01129   *   This parameter can be one of the following values:
01130   *     @arg TIM_OCPreload_Enable: Enable TIM output compare Preload
01131   *     @arg TIM_OCPreload_Disable: Disable TIM output compare Preload
01132   * @retval None
01133   */
01134 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01135 {
01136   uint16_t tmpccmr2 = 0;
01137
01138   /* Check the parameters */
01139   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01140   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01141
01142   tmpccmr2 = TIMx->CCMR2;
01143   /* Reset the OC4PE Bit */
01144   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
01145   /* Enable or Disable the Output Compare Preload feature */
01146   tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
01147   /* Write to TIMx CCMR2 register */
01148   TIMx->CCMR2 = tmpccmr2;
01149 }
01150
01151 /**
01152   * @brief  Configures the TIMx Output Compare 1 Fast feature.
01153   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01154   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01155   *   This parameter can be one of the following values:
01156   *     @arg TIM_OCFast_Enable: TIM output compare fast enable.
01157   *     @arg TIM_OCFast_Disable: TIM output compare fast disable.
01158   * @retval None
01159   */
01160 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01161 {
01162   uint16_t tmpccmr1 = 0;
01163
01164   /* Check the parameters */
01165   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01166   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01167
01168   /* Get the TIMx CCMR1 register value */
01169   tmpccmr1 = TIMx->CCMR1;
01170   /* Reset the OC1FE Bit */
01171   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
01172   /* Enable or Disable the Output Compare Fast Bit */
01173   tmpccmr1 |= TIM_OCFast;
01174   /* Write to TIMx CCMR1 */
01175   TIMx->CCMR1 = tmpccmr1;
01176 }
01177
01178 /**
01179   * @brief  Configures the TIMx Output Compare 2 Fast feature.
01180   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01181   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01182   *   This parameter can be one of the following values:
01183   *     @arg TIM_OCFast_Enable: TIM output compare fast enable.
01184   *     @arg TIM_OCFast_Disable: TIM output compare fast disable.
01185   * @retval None
01186   */
01187 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01188 {
01189   uint16_t tmpccmr1 = 0;
01190
01191   /* Check the parameters */
01192   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01193   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01194
01195   /* Get the TIMx CCMR1 register value */
01196   tmpccmr1 = TIMx->CCMR1;
01197   /* Reset the OC2FE Bit */
01198   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
01199   /* Enable or Disable the Output Compare Fast Bit */
01200   tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
01201   /* Write to TIMx CCMR1 */
01202   TIMx->CCMR1 = tmpccmr1;
01203 }
01204
01205 /**
01206   * @brief  Configures the TIMx Output Compare 3 Fast feature.
01207   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01208   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01209   *   This parameter can be one of the following values:
01210   *     @arg TIM_OCFast_Enable: TIM output compare fast enable.
01211   *     @arg TIM_OCFast_Disable: TIM output compare fast disable.
01212   * @retval None
01213   */
01214 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01215 {
01216   uint16_t tmpccmr2 = 0;
01217
01218   /* Check the parameters */
01219   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01220   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01221
01222   /* Get the TIMx CCMR2 register value */
01223   tmpccmr2 = TIMx->CCMR2;
01224   /* Reset the OC3FE Bit */
01225   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
01226   /* Enable or Disable the Output Compare Fast Bit */
01227   tmpccmr2 |= TIM_OCFast;
01228   /* Write to TIMx CCMR2 */
01229   TIMx->CCMR2 = tmpccmr2;
01230 }
01231
01232 /**
01233   * @brief  Configures the TIMx Output Compare 4 Fast feature.
01234   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01235   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01236   *   This parameter can be one of the following values:
01237   *     @arg TIM_OCFast_Enable: TIM output compare fast enable.
01238   *     @arg TIM_OCFast_Disable: TIM output compare fast disable.
01239   * @retval None
01240   */
01241 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01242 {
01243   uint16_t tmpccmr2 = 0;
01244
01245   /* Check the parameters */
01246   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01247   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01248
01249   /* Get the TIMx CCMR2 register value */
01250   tmpccmr2 = TIMx->CCMR2;
01251   /* Reset the OC4FE Bit */
01252   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
01253   /* Enable or Disable the Output Compare Fast Bit */
01254   tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
01255   /* Write to TIMx CCMR2 */
01256   TIMx->CCMR2 = tmpccmr2;
01257 }
01258
01259 /**
01260   * @brief  Clears or safeguards the OCREF1 signal on an external event
01261   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01262   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01263   *   This parameter can be one of the following values:
01264   *     @arg TIM_OCClear_Enable: TIM Output clear enable.
01265   *     @arg TIM_OCClear_Disable: TIM Output clear disable.
01266   * @retval None
01267   */
01268 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01269 {
01270   uint16_t tmpccmr1 = 0;
01271
01272   /* Check the parameters */
01273   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01274   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01275
01276   tmpccmr1 = TIMx->CCMR1;
01277   /* Reset the OC1CE Bit */
01278   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
01279   /* Enable or Disable the Output Compare Clear Bit */
01280   tmpccmr1 |= TIM_OCClear;
01281   /* Write to TIMx CCMR1 register */
01282   TIMx->CCMR1 = tmpccmr1;
01283 }
01284
01285 /**
01286   * @brief  Clears or safeguards the OCREF2 signal on an external event
01287   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01288   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01289
01290   *   This parameter can be one of the following values:
01291   *     @arg TIM_OCClear_Enable: TIM Output clear enable.
01292   *     @arg TIM_OCClear_Disable: TIM Output clear disable .
01293   * @retval None
01294   */
01295 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01296 {
01297   uint16_t tmpccmr1 = 0;
01298
01299   /* Check the parameters */
01300   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01301   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01302
01303   tmpccmr1 = TIMx->CCMR1;
01304   /* Reset the OC2CE Bit */
01305   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
01306   /* Enable or Disable the Output Compare Clear Bit */
01307   tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
01308   /* Write to TIMx CCMR1 register */
01309   TIMx->CCMR1 = tmpccmr1;
01310 }
01311
01312 /**
01313   * @brief  Clears or safeguards the OCREF3 signal on an external event
01314   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01315   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01316   *   This parameter can be one of the following values:
01317   *     @arg TIM_OCClear_Enable: TIM Output clear enable.
01318   *     @arg TIM_OCClear_Disable: TIM Output clear disable.
01319   * @retval None
01320   */
01321 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01322 {
01323   uint16_t tmpccmr2 = 0;
01324
01325   /* Check the parameters */
01326   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01327   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01328
01329   tmpccmr2 = TIMx->CCMR2;
01330   /* Reset the OC3CE Bit */
01331   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
01332   /* Enable or Disable the Output Compare Clear Bit */
01333   tmpccmr2 |= TIM_OCClear;
01334   /* Write to TIMx CCMR2 register */
01335   TIMx->CCMR2 = tmpccmr2;
01336 }
01337
01338 /**
01339   * @brief  Clears or safeguards the OCREF4 signal on an external event
01340   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01341   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01342   *   This parameter can be one of the following values:
01343   *     @arg TIM_OCClear_Enable: TIM Output clear enable.
01344   *     @arg TIM_OCClear_Disable: TIM Output clear disable.
01345   * @retval None
01346   */
01347 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01348 {
01349   uint16_t tmpccmr2 = 0;
01350
01351   /* Check the parameters */
01352   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01353   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01354
01355   tmpccmr2 = TIMx->CCMR2;
01356   /* Reset the OC4CE Bit */
01357   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
01358   /* Enable or Disable the Output Compare Clear Bit */
01359   tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
01360   /* Write to TIMx CCMR2 register */
01361   TIMx->CCMR2 = tmpccmr2;
01362 }
01363
01364 /**
01365   * @brief  Configures the TIMx channel 1 polarity.
01366   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01367   * @param  TIM_OCPolarity: specifies the OC1 Polarity.
01368   *   This parameter can be one of the following values:
01369   *     @arg TIM_OCPolarity_High: Output Compare active high.
01370   *     @arg TIM_OCPolarity_Low: Output Compare active low.
01371   * @retval None
01372   */
01373 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01374 {
01375   uint16_t tmpccer = 0;
01376
01377   /* Check the parameters */
01378   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01379   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01380
01381   tmpccer = TIMx->CCER;
01382   /* Set or Reset the CC1P Bit */
01383   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
01384   tmpccer |= TIM_OCPolarity;
01385   /* Write to TIMx CCER register */
01386   TIMx->CCER = tmpccer;
01387 }
01388
01389 /**
01390   * @brief  Configures the TIMx channel 2 polarity.
01391   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01392   * @param  TIM_OCPolarity: specifies the OC2 Polarity.
01393   *   This parameter can be one of the following values:
01394   *     @arg TIM_OCPolarity_High: Output Compare active high.
01395   *     @arg TIM_OCPolarity_Low: Output Compare active low.
01396   * @retval None
01397   */
01398 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01399 {
01400   uint16_t tmpccer = 0;
01401
01402   /* Check the parameters */
01403   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01404   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01405
01406   tmpccer = TIMx->CCER;
01407   /* Set or Reset the CC2P Bit */
01408   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
01409   tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
01410   /* Write to TIMx CCER register */
01411   TIMx->CCER = tmpccer;
01412 }
01413
01414 /**
01415   * @brief  Configures the TIMx channel 3 polarity.
01416   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01417   * @param  TIM_OCPolarity: specifies the OC3 Polarity.
01418   *   This parameter can be one of the following values:
01419   *     @arg TIM_OCPolarity_High: Output Compare active high.
01420   *     @arg TIM_OCPolarity_Low: Output Compare active low.
01421   * @retval None
01422   */
01423 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01424 {
01425   uint16_t tmpccer = 0;
01426
01427   /* Check the parameters */
01428   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01429   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01430
01431   tmpccer = TIMx->CCER;
01432   /* Set or Reset the CC3P Bit */
01433   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
01434   tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
01435   /* Write to TIMx CCER register */
01436   TIMx->CCER = tmpccer;
01437 }
01438
01439 /**
01440   * @brief  Configures the TIMx channel 4 polarity.
01441   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01442   * @param  TIM_OCPolarity: specifies the OC4 Polarity.
01443   *   This parameter can be one of the following values:
01444   *     @arg TIM_OCPolarity_High: Output Compare active high.
01445   *     @arg TIM_OCPolarity_Low: Output Compare active low.
01446   * @retval None
01447   */
01448 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01449 {
01450   uint16_t tmpccer = 0;
01451
01452   /* Check the parameters */
01453   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01454   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01455
01456   tmpccer = TIMx->CCER;
01457   /* Set or Reset the CC4P Bit */
01458   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
01459   tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
01460   /* Write to TIMx CCER register */
01461   TIMx->CCER = tmpccer;
01462 }
01463
01464 /**
01465   * @brief  Selects the OCReference Clear source.
01466   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01467   * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.
01468   *   This parameter can be one of the following values:
01469   *     @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
01470   *     @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
01471   * @retval None
01472   */
01473 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
01474 {
01475   /* Check the parameters */
01476   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01477   assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
01478
01479   /* Set the TIM_OCReferenceClear source */
01480   TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
01481   TIMx->SMCR |=  TIM_OCReferenceClear;
01482 }
01483
01484 /**
01485   * @brief  Enables or disables the TIM Capture Compare Channel x.
01486   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01487   * @param  TIM_Channel: specifies the TIM Channel.
01488   *   This parameter can be one of the following values:
01489   *     @arg TIM_Channel_1: TIM Channel 1.
01490   *     @arg TIM_Channel_2: TIM Channel 2.
01491   *     @arg TIM_Channel_3: TIM Channel 3.
01492   *     @arg TIM_Channel_4: TIM Channel 4.
01493   * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
01494   *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
01495   * @retval None
01496   */
01497 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
01498 {
01499   uint16_t tmp = 0;
01500
01501   /* Check the parameters */
01502   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01503   assert_param(IS_TIM_CCX(TIM_CCx));
01504
01505   tmp = CCER_CCE_SET << TIM_Channel;
01506
01507   /* Reset the CCxE Bit */
01508   TIMx->CCER &= (uint16_t)~ tmp;
01509
01510   /* Set or reset the CCxE Bit */
01511   TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
01512 }
01513
01514 /**
01515   * @}
01516   */
01517
01518 /** @defgroup TIM_Group3 Input Capture management functions
01519  *  @brief    Input Capture management functions
01520  *
01521 @verbatim
01522  ===============================================================================
01523                ##### Input Capture management functions #####
01524  ===============================================================================
01525
01526           *** TIM Driver: how to use it in Input Capture Mode ***
01527  ===============================================================================
01528     [..] To use the Timer in Input Capture mode, the following steps are mandatory:
01529          (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
01530              function.
01531          (#) Configure the TIM pins by configuring the corresponding GPIO pins.
01532          (#) Configure the Time base unit as described in the first part of this
01533              driver, if needed, else the Timer will run with the default configuration:
01534              (++) Autoreload value = 0xFFFF.
01535              (++) Prescaler value = 0x0000.
01536              (++) Counter mode = Up counting.
01537              (++) Clock Division = TIM_CKD_DIV1.
01538          (#) Fill the TIM_ICInitStruct with the desired parameters including:
01539              (++) TIM Channel: TIM_Channel.
01540              (++) TIM Input Capture polarity: TIM_ICPolarity.
01541              (++) TIM Input Capture selection: TIM_ICSelection.
01542              (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
01543              (++) TIM Input CApture filter value: TIM_ICFilter.
01544          (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired
01545              channel with the corresponding configuration and to measure only
01546              frequency or duty cycle of the input signal,or, Call
01547              TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired
01548              channels with the corresponding configuration and to measure the
01549              frequency and the duty cycle of the input signal.
01550          (#) Enable the NVIC or the DMA to read the measured frequency.
01551          (#) Enable the corresponding interrupt (or DMA request) to read
01552              the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
01553              (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
01554          (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
01555          (#) Use TIM_GetCapturex(TIMx); to read the captured value.
01556     [..]
01557         (@) All other functions can be used separately to modify, if needed,
01558             a specific feature of the Timer.
01559
01560 @endverbatim
01561   * @{
01562   */
01563
01564 /**
01565   * @brief  Initializes the TIM peripheral according to the specified
01566   *         parameters in the TIM_ICInitStruct.
01567   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01568   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
01569   *         that contains the configuration information for the specified TIM
01570   *         peripheral.
01571   * @retval None
01572   */
01573 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
01574 {
01575   /* Check the parameters */
01576   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01577   assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
01578   assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
01579   assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
01580   assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
01581
01582   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
01583   {
01584     /* TI1 Configuration */
01585     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
01586                TIM_ICInitStruct->TIM_ICSelection,
01587                TIM_ICInitStruct->TIM_ICFilter);
01588     /* Set the Input Capture Prescaler value */
01589     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01590   }
01591   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
01592   {
01593     /* TI2 Configuration */
01594     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01595     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
01596                TIM_ICInitStruct->TIM_ICSelection,
01597                TIM_ICInitStruct->TIM_ICFilter);
01598     /* Set the Input Capture Prescaler value */
01599     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01600   }
01601   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
01602   {
01603     /* TI3 Configuration */
01604     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01605     TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
01606                TIM_ICInitStruct->TIM_ICSelection,
01607                TIM_ICInitStruct->TIM_ICFilter);
01608     /* Set the Input Capture Prescaler value */
01609     TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01610   }
01611   else
01612   {
01613     /* TI4 Configuration */
01614     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01615     TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
01616                TIM_ICInitStruct->TIM_ICSelection,
01617                TIM_ICInitStruct->TIM_ICFilter);
01618     /* Set the Input Capture Prescaler value */
01619     TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01620   }
01621 }
01622
01623 /**
01624   * @brief  Fills each TIM_ICInitStruct member with its default value.
01625   * @param  TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
01626   *         be initialized.
01627   * @retval None
01628   */
01629 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
01630 {
01631   /* Set the default configuration */
01632   TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
01633   TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
01634   TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
01635   TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
01636   TIM_ICInitStruct->TIM_ICFilter = 0x00;
01637 }
01638
01639 /**
01640   * @brief  Configures the TIM peripheral according to the specified
01641   *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
01642   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01643   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
01644   *         that contains the configuration information for the specified TIM
01645   *         peripheral.
01646   * @retval None
01647   */
01648 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
01649 {
01650   uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
01651   uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
01652   /* Check the parameters */
01653   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01654   /* Select the Opposite Input Polarity */
01655   if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
01656   {
01657     icoppositepolarity = TIM_ICPolarity_Falling;
01658   }
01659   else
01660   {
01661     icoppositepolarity = TIM_ICPolarity_Rising;
01662   }
01663   /* Select the Opposite Input */
01664   if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
01665   {
01666     icoppositeselection = TIM_ICSelection_IndirectTI;
01667   }
01668   else
01669   {
01670     icoppositeselection = TIM_ICSelection_DirectTI;
01671   }
01672   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
01673   {
01674     /* TI1 Configuration */
01675     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
01676                TIM_ICInitStruct->TIM_ICFilter);
01677     /* Set the Input Capture Prescaler value */
01678     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01679     /* TI2 Configuration */
01680     TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
01681     /* Set the Input Capture Prescaler value */
01682     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01683   }
01684   else
01685   {
01686     /* TI2 Configuration */
01687     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
01688                TIM_ICInitStruct->TIM_ICFilter);
01689     /* Set the Input Capture Prescaler value */
01690     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01691     /* TI1 Configuration */
01692     TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
01693     /* Set the Input Capture Prescaler value */
01694     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
01695   }
01696 }
01697
01698 /**
01699   * @brief  Gets the TIMx Input Capture 1 value.
01700   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01701   * @retval Capture Compare 1 Register value.
01702   */
01703 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
01704 {
01705   /* Check the parameters */
01706   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01707
01708   /* Get the Capture 1 Register value */
01709   return TIMx->CCR1;
01710 }
01711
01712 /**
01713   * @brief  Gets the TIMx Input Capture 2 value.
01714   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01715   * @retval Capture Compare 2 Register value.
01716   */
01717 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
01718 {
01719   /* Check the parameters */
01720   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01721
01722   /* Get the Capture 2 Register value */
01723   return TIMx->CCR2;
01724 }
01725
01726 /**
01727   * @brief  Gets the TIMx Input Capture 3 value.
01728   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01729   * @retval Capture Compare 3 Register value.
01730   */
01731 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
01732 {
01733   /* Check the parameters */
01734   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01735
01736   /* Get the Capture 3 Register value */
01737   return TIMx->CCR3;
01738 }
01739
01740 /**
01741   * @brief  Gets the TIMx Input Capture 4 value.
01742   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01743   * @retval Capture Compare 4 Register value.
01744   */
01745 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
01746 {
01747   /* Check the parameters */
01748   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01749
01750   /* Get the Capture 4 Register value */
01751   return TIMx->CCR4;
01752 }
01753
01754 /**
01755   * @brief  Sets the TIMx Input Capture 1 prescaler.
01756   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
01757   * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
01758   *   This parameter can be one of the following values:
01759   *     @arg TIM_ICPSC_DIV1: no prescaler.
01760   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events.
01761   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events.
01762   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events.
01763   * @retval None
01764   */
01765 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
01766 {
01767   /* Check the parameters */
01768   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01769   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
01770
01771   /* Reset the IC1PSC Bits */
01772   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
01773   /* Set the IC1PSC value */
01774   TIMx->CCMR1 |= TIM_ICPSC;
01775 }
01776
01777 /**
01778   * @brief  Sets the TIMx Input Capture 2 prescaler.
01779   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
01780   * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
01781   *   This parameter can be one of the following values:
01782   *     @arg TIM_ICPSC_DIV1: no prescaler.
01783   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events.
01784   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events.
01785   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events.
01786   * @retval None
01787   */
01788 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
01789 {
01790   /* Check the parameters */
01791   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01792   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
01793
01794   /* Reset the IC2PSC Bits */
01795   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
01796   /* Set the IC2PSC value */
01797   TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
01798 }
01799
01800 /**
01801   * @brief  Sets the TIMx Input Capture 3 prescaler.
01802   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01803   * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
01804   *   This parameter can be one of the following values:
01805   *     @arg TIM_ICPSC_DIV1: no prescaler.
01806   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events.
01807   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events.
01808   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events.
01809   * @retval None
01810   */
01811 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
01812 {
01813   /* Check the parameters */
01814   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01815   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
01816
01817   /* Reset the IC3PSC Bits */
01818   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
01819   /* Set the IC3PSC value */
01820   TIMx->CCMR2 |= TIM_ICPSC;
01821 }
01822
01823 /**
01824   * @brief  Sets the TIMx Input Capture 4 prescaler.
01825   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
01826   * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
01827   *   This parameter can be one of the following values:
01828   *     @arg TIM_ICPSC_DIV1: no prescaler.
01829   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events.
01830   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events.
01831   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events.
01832   * @retval None
01833   */
01834 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
01835 {
01836   /* Check the parameters */
01837   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01838   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
01839
01840   /* Reset the IC4PSC Bits */
01841   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
01842   /* Set the IC4PSC value */
01843   TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
01844 }
01845
01846 /**
01847   * @}
01848   */
01849
01850 /** @defgroup TIM_Group4 Interrupts DMA and flags management functions
01851  *  @brief    Interrupts, DMA and flags management functions
01852  *
01853 @verbatim
01854  ===============================================================================
01855           ##### Interrupts, DMA and flags management functions #####
01856  ===============================================================================
01857
01858 @endverbatim
01859   * @{
01860   */
01861
01862 /**
01863   * @brief  Enables or disables the specified TIM interrupts.
01864   * @param  TIMx: where x can be 2 to 11 to select the TIMx peripheral.
01865   * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
01866   *   This parameter can be any combination of the following values:
01867   *     @arg TIM_IT_Update: TIM update Interrupt source.
01868   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
01869   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
01870   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
01871   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
01872   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source.
01873   * @note TIM6 and TIM7 can only generate an update interrupt.
01874   * @note TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11.
01875   * @note TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
01876   * @param  NewState: new state of the TIM interrupts.
01877   *         This parameter can be: ENABLE or DISABLE.
01878   * @retval None
01879   */
01880 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
01881 {
01882   /* Check the parameters */
01883   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01884   assert_param(IS_TIM_IT(TIM_IT));
01885   assert_param(IS_FUNCTIONAL_STATE(NewState));
01886
01887   if (NewState != DISABLE)
01888   {
01889     /* Enable the Interrupt sources */
01890     TIMx->DIER |= TIM_IT;
01891   }
01892   else
01893   {
01894     /* Disable the Interrupt sources */
01895     TIMx->DIER &= (uint16_t)~TIM_IT;
01896   }
01897 }
01898
01899 /**
01900   * @brief  Configures the TIMx event to be generate by software.
01901   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
01902   * @param  TIM_EventSource: specifies the event source.
01903   *   This parameter can be one or more of the following values:
01904   *     @arg TIM_EventSource_Update: Timer update Event source.
01905   *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source.
01906   *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source.
01907   *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source.
01908   *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source.
01909   *     @arg TIM_EventSource_Trigger: Timer Trigger Event source.
01910   * @note TIM6 and TIM7 can only generate an update event.
01911   * @note TIM9 can only generate an update event, Capture Compare 1 event,
01912   *     Capture Compare 2 event and TIM_EventSource_Trigger.
01913   * @note TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
01914   * @retval None
01915   */
01916 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
01917 {
01918   /* Check the parameters */
01919   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01920   assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
01921   /* Set the event sources */
01922   TIMx->EGR = TIM_EventSource;
01923 }
01924
01925 /**
01926   * @brief  Checks whether the specified TIM flag is set or not.
01927   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
01928   * @param  TIM_FLAG: specifies the flag to check.
01929   *   This parameter can be one of the following values:
01930   *     @arg TIM_FLAG_Update: TIM update Flag.
01931   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
01932   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
01933   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
01934   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
01935   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag.
01936   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
01937   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
01938   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
01939   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
01940   *
01941   * @note TIM6 and TIM7 can have only one update flag.
01942   * @note TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,
01943   *     TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
01944   * @note TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
01945   * @retval The new state of TIM_FLAG (SET or RESET).
01946   */
01947 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
01948 {
01949   ITStatus bitstatus = RESET;
01950
01951   /* Check the parameters */
01952   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01953   assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
01954
01955   if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
01956   {
01957     bitstatus = SET;
01958   }
01959   else
01960   {
01961     bitstatus = RESET;
01962   }
01963   return bitstatus;
01964 }
01965
01966 /**
01967   * @brief  Clears the TIMx's pending flags.
01968   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
01969   * @param  TIM_FLAG: specifies the flag bit to clear.
01970   *   This parameter can be any combination of the following values:
01971   *     @arg TIM_FLAG_Update: TIM update Flag.
01972   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag.
01973   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag.
01974   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag.
01975   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag.
01976   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag.
01977   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag.
01978   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag.
01979   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag.
01980   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag.
01981   * @note TIM6 and TIM7 can have only one update flag.
01982   * @note TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags
01983   *     TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags.
01984   * @note TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1
01985   *     or TIM_FLAG_CC1OF flags
01986   * @retval None
01987   */
01988 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
01989 {
01990   /* Check the parameters */
01991   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01992   assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
01993
01994   /* Clear the flags */
01995   TIMx->SR = (uint16_t)~TIM_FLAG;
01996 }
01997
01998 /**
01999   * @brief  Checks whether the TIM interrupt has occurred or not.
02000   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
02001   * @param  TIM_IT: specifies the TIM interrupt source to check.
02002   *   This parameter can be one of the following values:
02003   *     @arg TIM_IT_Update: TIM update Interrupt source.
02004   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
02005   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
02006   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
02007   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
02008   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source.
02009   *
02010   * @note TIM6 and TIM7 can generate only an update interrupt.
02011   * @note TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,
02012   *     interrupt and TIM_IT_Trigger interrupt.
02013   * @note TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1
02014   *     interrupt
02015   * @retval The new state of the TIM_IT(SET or RESET).
02016   */
02017 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02018 {
02019   ITStatus bitstatus = RESET;
02020   uint16_t itstatus = 0x0, itenable = 0x0;
02021
02022   /* Check the parameters */
02023   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02024   assert_param(IS_TIM_GET_IT(TIM_IT));
02025
02026   itstatus = TIMx->SR & TIM_IT;
02027
02028   itenable = TIMx->DIER & TIM_IT;
02029   if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
02030   {
02031     bitstatus = SET;
02032   }
02033   else
02034   {
02035     bitstatus = RESET;
02036   }
02037   return bitstatus;
02038 }
02039
02040 /**
02041   * @brief  Clears the TIMx's interrupt pending bits.
02042   * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.
02043   * @param  TIM_IT: specifies the pending bit to clear.
02044   *   This parameter can be any combination of the following values:
02045   *     @arg TIM_IT_Update: TIM update Interrupt source.
02046   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source.
02047   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source.
02048   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source.
02049   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source.
02050   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source.
02051   * @note
02052   * @note TIM6 and TIM7 can generate only an update interrupt.
02053   * @note TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,
02054   *     and TIM_IT_Trigger interrupt.
02055   * @note TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1
02056   *     interrupt
02057   * @retval None
02058   */
02059 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02060 {
02061   /* Check the parameters */
02062   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02063   assert_param(IS_TIM_IT(TIM_IT));
02064
02065   /* Clear the IT pending Bit */
02066   TIMx->SR = (uint16_t)~TIM_IT;
02067 }
02068
02069 /**
02070   * @brief  Configures the TIMx's DMA interface.
02071   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
02072   * @param  TIM_DMABase: DMA Base address.
02073   *   This parameter can be one of the following values:
02074   *     @arg TIM_DMABase_CR1: TIM CR1 register as TIM DMA Base.
02075   *     @arg TIM_DMABase_CR2: TIM CR2 register as TIM DMA Base.
02076   *     @arg TIM_DMABase_SMCR: TIM SMCR register as TIM DMA Base.
02077   *     @arg TIM_DMABase_DIER: TIM DIER register as TIM DMA Base.
02078   *     @arg TIM_DMABase_SR: TIM SR register as TIM DMA Base.
02079   *     @arg TIM_DMABase_EGR: TIM EGR register as TIM DMA Base.
02080   *     @arg TIM_DMABase_CCMR1: TIM CCMR1 register as TIM DMA Base.
02081   *     @arg TIM_DMABase_CCMR2: TIM CCMR2 register as TIM DMA Base.
02082   *     @arg TIM_DMABase_CCER: TIM CCER register as TIM DMA Base.
02083   *     @arg TIM_DMABase_CNT: TIM CNT register as TIM DMA Base.
02084   *     @arg TIM_DMABase_PSC: TIM PSC register as TIM DMA Base.
02085   *     @arg TIM_DMABase_ARR: TIM ARR register as TIM DMA Base.
02086   *     @arg TIM_DMABase_CCR1: TIM CCR1 register as TIM DMA Base.
02087   *     @arg TIM_DMABase_CCR2: TIM CCR2 register as TIM DMA Base.
02088   *     @arg TIM_DMABase_CCR3: TIM CCR3 register as TIM DMA Base.
02089   *     @arg TIM_DMABase_CCR4: TIM CCR4 register as TIM DMA Base.
02090   *     @arg TIM_DMABase_DCR: TIM DCR register as TIM DMA Base.
02091   *     @arg TIM_DMABase_OR: TIM OR register as TIM DMA Base.
02092   * @param  TIM_DMABurstLength: DMA Burst length.
02093   *   This parameter can be one value between:
02094   *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
02095   * @retval None
02096   */
02097 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
02098 {
02099   /* Check the parameters */
02100   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02101   assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
02102   assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
02103   /* Set the DMA Base and the DMA Burst Length */
02104   TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
02105 }
02106
02107 /**
02108   * @brief  Enables or disables the TIMx's DMA Requests.
02109   * @param  TIMx: where x can be 2, 3, 4, 5, 6 or 7 to select the TIM peripheral.
02110   * @param  TIM_DMASource: specifies the DMA Request sources.
02111   *   This parameter can be any combination of the following values:
02112   *     @arg TIM_DMA_Update: TIM update Interrupt source.
02113   *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source.
02114   *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source.
02115   *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source.
02116   *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source.
02117   *     @arg TIM_DMA_Trigger: TIM Trigger DMA source.
02118   * @param  NewState: new state of the DMA Request sources.
02119   *   This parameter can be: ENABLE or DISABLE.
02120   * @retval None
02121   */
02122 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
02123 {
02124   /* Check the parameters */
02125   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02126   assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
02127   assert_param(IS_FUNCTIONAL_STATE(NewState));
02128
02129   if (NewState != DISABLE)
02130   {
02131     /* Enable the DMA sources */
02132     TIMx->DIER |= TIM_DMASource;
02133   }
02134   else
02135   {
02136     /* Disable the DMA sources */
02137     TIMx->DIER &= (uint16_t)~TIM_DMASource;
02138   }
02139 }
02140
02141 /**
02142   * @brief  Selects the TIMx peripheral Capture Compare DMA source.
02143   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
02144   * @param  NewState: new state of the Capture Compare DMA source
02145   *   This parameter can be: ENABLE or DISABLE.
02146   * @retval None
02147   */
02148 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
02149 {
02150   /* Check the parameters */
02151   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02152   assert_param(IS_FUNCTIONAL_STATE(NewState));
02153
02154   if (NewState != DISABLE)
02155   {
02156     /* Set the CCDS Bit */
02157     TIMx->CR2 |= TIM_CR2_CCDS;
02158   }
02159   else
02160   {
02161     /* Reset the CCDS Bit */
02162     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
02163   }
02164 }
02165
02166 /**
02167   * @}
02168   */
02169
02170 /** @defgroup TIM_Group5 Clocks management functions
02171  *  @brief    Clocks management functions
02172  *
02173 @verbatim
02174  ===============================================================================
02175                      ##### Clocks management functions #####
02176  ===============================================================================
02177
02178 @endverbatim
02179   * @{
02180   */
02181
02182 /**
02183   * @brief  Configures the TIMx internal Clock
02184   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02185   * @retval None
02186   */
02187 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
02188 {
02189   /* Check the parameters */
02190   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02191   /* Disable slave mode to clock the prescaler directly with the internal clock */
02192   TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
02193 }
02194
02195 /**
02196   * @brief  Configures the TIMx Internal Trigger as External Clock
02197   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02198   * @param  TIM_ITRSource: Trigger source.
02199   *   This parameter can be one of the following values:
02200   * @param  TIM_TS_ITR0: Internal Trigger 0.
02201   * @param  TIM_TS_ITR1: Internal Trigger 1.
02202   * @param  TIM_TS_ITR2: Internal Trigger 2.
02203   * @param  TIM_TS_ITR3: Internal Trigger 3.
02204   * @retval None
02205   */
02206 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
02207 {
02208   /* Check the parameters */
02209   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02210   assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
02211   /* Select the Internal Trigger */
02212   TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
02213   /* Select the External clock mode1 */
02214   TIMx->SMCR |= TIM_SlaveMode_External1;
02215 }
02216
02217 /**
02218   * @brief  Configures the TIMx Trigger as External Clock
02219   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02220   * @param  TIM_TIxExternalCLKSource: Trigger source.
02221   *   This parameter can be one of the following values:
02222   *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector.
02223   *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1.
02224   *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2.
02225   * @param  TIM_ICPolarity: specifies the TIx Polarity.
02226   *   This parameter can be one of the following values:
02227   *     @arg TIM_ICPolarity_Rising:
02228   *     @arg TIM_ICPolarity_Falling:
02229   * @param  ICFilter : specifies the filter value.
02230   *   This parameter must be a value between 0x0 and 0xF.
02231   * @retval None
02232   */
02233 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
02234                                 uint16_t TIM_ICPolarity, uint16_t ICFilter)
02235 {
02236   /* Check the parameters */
02237   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02238   assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
02239   assert_param(IS_TIM_IC_FILTER(ICFilter));
02240
02241   /* Configure the Timer Input Clock Source */
02242   if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
02243   {
02244     TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
02245   }
02246   else
02247   {
02248     TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
02249   }
02250   /* Select the Trigger source */
02251   TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
02252   /* Select the External clock mode1 */
02253   TIMx->SMCR |= TIM_SlaveMode_External1;
02254 }
02255
02256 /**
02257   * @brief  Configures the External clock Mode1
02258   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02259   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
02260   *   This parameter can be one of the following values:
02261   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
02262   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
02263   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
02264   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
02265   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
02266   *   This parameter can be one of the following values:
02267   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
02268   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
02269   * @param  ExtTRGFilter: External Trigger Filter.
02270   *   This parameter must be a value between 0x00 and 0x0F
02271   * @retval None
02272   */
02273 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
02274                              uint16_t ExtTRGFilter)
02275 {
02276   uint16_t tmpsmcr = 0;
02277
02278   /* Check the parameters */
02279   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02280   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
02281   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
02282   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
02283
02284   /* Configure the ETR Clock source */
02285   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
02286
02287   /* Get the TIMx SMCR register value */
02288   tmpsmcr = TIMx->SMCR;
02289   /* Reset the SMS Bits */
02290   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
02291   /* Select the External clock mode1 */
02292   tmpsmcr |= TIM_SlaveMode_External1;
02293   /* Select the Trigger selection : ETRF */
02294   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
02295   tmpsmcr |= TIM_TS_ETRF;
02296   /* Write to TIMx SMCR */
02297   TIMx->SMCR = tmpsmcr;
02298 }
02299
02300 /**
02301   * @brief  Configures the External clock Mode2
02302   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
02303   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
02304   *   This parameter can be one of the following values:
02305   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
02306   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
02307   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
02308   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
02309   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
02310   *   This parameter can be one of the following values:
02311   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
02312   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
02313   * @param  ExtTRGFilter: External Trigger Filter.
02314   *   This parameter must be a value between 0x00 and 0x0F
02315   * @retval None
02316   */
02317 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
02318                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
02319 {
02320   /* Check the parameters */
02321   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02322   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
02323   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
02324   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
02325
02326   /* Configure the ETR Clock source */
02327   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
02328   /* Enable the External clock mode2 */
02329   TIMx->SMCR |= TIM_SMCR_ECE;
02330 }
02331
02332 /**
02333   * @}
02334   */
02335
02336 /** @defgroup TIM_Group6 Synchronization management functions
02337  *  @brief    Synchronization management functions
02338  *
02339 @verbatim
02340  ===============================================================================
02341                ##### Synchronization management functions #####
02342  ===============================================================================
02343         *** TIM Driver: how to use it in synchronization Mode ***
02344  ===============================================================================
02345     [..] Case of two/several Timers
02346          (#) Configure the Master Timers using the following functions:
02347              (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
02348                   uint16_t TIM_TRGOSource).
02349              (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
02350                   uint16_t TIM_MasterSlaveMode);
02351          (#) Configure the Slave Timers using the following functions:
02352              (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
02353                   uint16_t TIM_InputTriggerSource);
02354              (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
02355     [..] Case of Timers and external trigger(ETR pin)
02356          (#) Configure the Etrenal trigger using this function:
02357              (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
02358                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
02359          (#) Configure the Slave Timers using the following functions:
02360              (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
02361                   uint16_t TIM_InputTriggerSource);
02362              (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
02363
02364 @endverbatim
02365   * @{
02366   */
02367
02368 /**
02369   * @brief  Selects the Input Trigger source
02370   * @param  TIMx: where x can be 2, 3, 4, 5, or 9 to select the TIM peripheral.
02371   * @param  TIM_InputTriggerSource: The Input Trigger source.
02372   *   This parameter can be one of the following values:
02373   *     @arg TIM_TS_ITR0: Internal Trigger 0.
02374   *     @arg TIM_TS_ITR1: Internal Trigger 1.
02375   *     @arg TIM_TS_ITR2: Internal Trigger 2.
02376   *     @arg TIM_TS_ITR3: Internal Trigger 3.
02377   *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector.
02378   *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1.
02379   *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2.
02380   *     @arg TIM_TS_ETRF: External Trigger input.
02381   * @retval None
02382   */
02383 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
02384 {
02385   uint16_t tmpsmcr = 0;
02386
02387   /* Check the parameters */
02388   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02389   assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
02390
02391   /* Get the TIMx SMCR register value */
02392   tmpsmcr = TIMx->SMCR;
02393   /* Reset the TS Bits */
02394   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
02395   /* Set the Input Trigger source */
02396   tmpsmcr |= TIM_InputTriggerSource;
02397   /* Write to TIMx SMCR */
02398   TIMx->SMCR = tmpsmcr;
02399 }
02400
02401 /**
02402   * @brief  Selects the TIMx Trigger Output Mode.
02403   * @param  TIMx: where x can be 2, 3, 4, 5, 6, 7 or 9 to select the TIM peripheral.
02404   * @param  TIM_TRGOSource: specifies the Trigger Output source.
02405   *   This paramter can be one of the following values:
02406   *
02407   *  @param For all TIMx
02408   *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
02409   *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
02410   *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
02411   *
02412   *  @param For all TIMx except TIM6 and TIM7
02413   *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
02414   *                              is to be set, as soon as a capture or compare match occurs (TRGO).
02415   *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
02416
02417   *  @param For all TIMx except TIM6, TIM7, TIM10 and TIM11
02418   *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
02419
02420   *  @param For TIM2, TIM3 and TIM4
02421   *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
02422   *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
02423   *
02424   * @retval None
02425   */
02426 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
02427 {
02428   /* Check the parameters */
02429   assert_param(IS_TIM_LIST5_PERIPH(TIMx));
02430   assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
02431
02432   /* Reset the MMS Bits */
02433   TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
02434   /* Select the TRGO source */
02435   TIMx->CR2 |=  TIM_TRGOSource;
02436 }
02437
02438 /**
02439   * @brief  Selects the TIMx Slave Mode.
02440   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02441   * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
02442   *   This paramter can be one of the following values:
02443   *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
02444   *                               the counter and triggers an update of the registers.
02445   *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
02446   *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
02447   *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
02448   * @retval None
02449   */
02450 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
02451 {
02452   /* Check the parameters */
02453   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02454   assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
02455
02456   /* Reset the SMS Bits */
02457   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
02458   /* Select the Slave Mode */
02459   TIMx->SMCR |= TIM_SlaveMode;
02460 }
02461
02462 /**
02463   * @brief  Sets or Resets the TIMx Master/Slave Mode.
02464   * @param  TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
02465   * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
02466   *   This paramter can be one of the following values:
02467   *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
02468   *                                      and its slaves (through TRGO).
02469   *     @arg TIM_MasterSlaveMode_Disable: No action
02470   * @retval None
02471   */
02472 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
02473 {
02474   /* Check the parameters */
02475   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02476   assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
02477
02478   /* Reset the MSM Bit */
02479   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
02480
02481   /* Set or Reset the MSM Bit */
02482   TIMx->SMCR |= TIM_MasterSlaveMode;
02483 }
02484
02485 /**
02486   * @brief  Configures the TIMx External Trigger (ETR).
02487   * @param  TIMx: where x can be 2, 3, 4, 5, 9, 10 or 11 to select the TIM peripheral.
02488   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
02489   *   This parameter can be one of the following values:
02490   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
02491   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
02492   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
02493   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
02494   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
02495   *   This parameter can be one of the following values:
02496   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
02497   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
02498   * @param  ExtTRGFilter: External Trigger Filter.
02499   *   This parameter must be a value between 0x00 and 0x0F
02500   * @retval None
02501   */
02502 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
02503                    uint16_t ExtTRGFilter)
02504 {
02505   uint16_t tmpsmcr = 0;
02506
02507   /* Check the parameters */
02508   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02509   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
02510   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
02511   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
02512
02513   tmpsmcr = TIMx->SMCR;
02514   /* Reset the ETR Bits */
02515   tmpsmcr &= SMCR_ETR_MASK;
02516   /* Set the Prescaler, the Filter value and the Polarity */
02517   tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
02518   /* Write to TIMx SMCR */
02519   TIMx->SMCR = tmpsmcr;
02520 }
02521
02522 /**
02523   * @}
02524   */
02525
02526 /** @defgroup TIM_Group7 Specific interface management functions
02527  *  @brief    Specific interface management functions
02528  *
02529 @verbatim
02530  ===============================================================================
02531              ##### Specific interface management functions #####
02532  ===============================================================================
02533
02534 @endverbatim
02535   * @{
02536   */
02537
02538 /**
02539   * @brief  Configures the TIMx Encoder Interface.
02540   * @param  TIMx: where x can be  2, 3, 4 or 5 to select the TIM peripheral.
02541   * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
02542   *   This parameter can be one of the following values:
02543   *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
02544   *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
02545   *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
02546   *                                on the level of the other input.
02547   * @param  TIM_IC1Polarity: specifies the IC1 Polarity.
02548   *   This parmeter can be one of the following values:
02549   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02550   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02551   * @param  TIM_IC2Polarity: specifies the IC2 Polarity
02552   *   This parmeter can be one of the following values:
02553   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02554   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02555   * @retval None
02556   */
02557 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
02558                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
02559 {
02560   uint16_t tmpsmcr = 0;
02561   uint16_t tmpccmr1 = 0;
02562   uint16_t tmpccer = 0;
02563
02564   /* Check the parameters */
02565   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02566   assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
02567   assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
02568   assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
02569
02570   /* Get the TIMx SMCR register value */
02571   tmpsmcr = TIMx->SMCR;
02572   /* Get the TIMx CCMR1 register value */
02573   tmpccmr1 = TIMx->CCMR1;
02574   /* Get the TIMx CCER register value */
02575   tmpccer = TIMx->CCER;
02576   /* Set the encoder Mode */
02577   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
02578   tmpsmcr |= TIM_EncoderMode;
02579   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02580   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
02581   tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
02582   /* Set the TI1 and the TI2 Polarities */
02583   tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
02584    tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
02585   /* Write to TIMx SMCR */
02586   TIMx->SMCR = tmpsmcr;
02587   /* Write to TIMx CCMR1 */
02588   TIMx->CCMR1 = tmpccmr1;
02589   /* Write to TIMx CCER */
02590   TIMx->CCER = tmpccer;
02591 }
02592
02593 /**
02594   * @brief  Enables or disables the TIMx's Hall sensor interface.
02595   * @param  TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
02596   * @param  NewState: new state of the TIMx Hall sensor interface.
02597   *   This parameter can be: ENABLE or DISABLE.
02598   * @retval None
02599   */
02600 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
02601 {
02602   /* Check the parameters */
02603   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02604   assert_param(IS_FUNCTIONAL_STATE(NewState));
02605
02606   if (NewState != DISABLE)
02607   {
02608     /* Set the TI1S Bit */
02609     TIMx->CR2 |= TIM_CR2_TI1S;
02610   }
02611   else
02612   {
02613     /* Reset the TI1S Bit */
02614     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
02615   }
02616 }
02617
02618 /**
02619   * @}
02620   */
02621
02622 /** @defgroup TIM_Group8 Specific remapping management function
02623  *  @brief   Specific remapping management function
02624  *
02625 @verbatim
02626  ===============================================================================
02627                ##### Specific remapping management function #####
02628  ===============================================================================
02629
02630 @endverbatim
02631   * @{
02632   */
02633
02634 /**
02635   * @brief  Configures the TIM2, TIM3, TIM9, TIM10 and TIM11 Remapping input
02636   *         Capabilities.
02637   * @param  TIMx: where x can be 2, 3, 9, 10 or 11 to select the TIM peripheral.
02638   * @param  TIM_Remap: specifies the TIM input remapping source.
02639   *   This parameter can be one of the following values:
02640   *     @arg TIM2_TIM10_OC: TIM2 ITR1 is connected to TIM10 output compare(default).
02641   *     @arg TIM2_TIM5_TRGO: TIM2 ITR1 is connected to TIM5 Trigger output.
02642   *     @arg TIM3_TIM11_OC: TIM3 ITR2 is connected to TIM11 output compare(default).
02643   *     @arg TIM3_TIM5_TRGO: TIM3 ITR2 is connected to TIM5 Trigger output.
02644   *     @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default).
02645   *     @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
02646   *     @arg TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO.
02647   *     @arg TIM9_TS_IO: TIM9 ITR1 is connected to Touch Sense IO.
02648   *     @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default).
02649   *     @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
02650   *     @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
02651   *     @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
02652   *     @arg TIM10_RI: TIM10 Channel 1 is connected to Routing Interface (RI).
02653   *     @arg TIM10_ETR_LSE: TIM10 ETR input is connected to LSE Clock.
02654   *     @arg TIM10_ETR_TIM9_TRGO: TIM10 ETR input is connected to TIM9 Trigger Output.
02655   *     @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default).
02656   *     @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
02657   *     @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
02658   *     @arg TIM11_RI: TIM11 Channel 1 is connected to Routing Interface (RI).
02659   *     @arg TIM11_ETR_LSE: TIM11 ETR input is connected to LSE Clock.
02660   *     @arg TIM11_ETR_TIM9_TRGO: TIM11 ETR input is connected to TIM9 Trigger Output.
02661   * @retval None
02662   */
02663 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap)
02664 {
02665   /* Check the parameters */
02666   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02667   assert_param(IS_TIM_REMAP(TIM_Remap));
02668
02669   /* Set the Timer remapping configuration */
02670   TIMx->OR &=  (uint16_t)(TIM_Remap >> 16);
02671   TIMx->OR |=  (uint16_t)TIM_Remap;
02672 }
02673
02674 /**
02675   * @}
02676   */
02677
02678 /**
02679   * @brief  Configure the TI1 as Input.
02680   * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
02681   * @param  TIM_ICPolarity : The Input Polarity.
02682   *   This parameter can be one of the following values:
02683   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02684   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02685   * @param  TIM_ICSelection: specifies the input to be used.
02686   *   This parameter can be one of the following values:
02687   *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
02688   *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
02689   *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
02690   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02691   *   This parameter must be a value between 0x00 and 0x0F.
02692   * @retval None
02693   */
02694 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02695                        uint16_t TIM_ICFilter)
02696 {
02697   uint16_t tmpccmr1 = 0, tmpccer = 0;
02698
02699   /* Disable the Channel 1: Reset the CC1E Bit */
02700   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
02701   tmpccmr1 = TIMx->CCMR1;
02702   tmpccer = TIMx->CCER;
02703   /* Select the Input and set the filter */
02704   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
02705   tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02706   /* Select the Polarity and set the CC1E Bit */
02707   tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
02708   tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
02709   /* Write to TIMx CCMR1 and CCER registers */
02710   TIMx->CCMR1 = tmpccmr1;
02711   TIMx->CCER = tmpccer;
02712 }
02713
02714 /**
02715   * @brief  Configure the TI2 as Input.
02716   * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
02717   * @param  TIM_ICPolarity : The Input Polarity.
02718   *   This parameter can be one of the following values:
02719   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02720   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02721   * @param  TIM_ICSelection: specifies the input to be used.
02722   *   This parameter can be one of the following values:
02723   *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
02724   *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
02725   *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
02726   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02727   *   This parameter must be a value between 0x00 and 0x0F.
02728   * @retval None
02729   */
02730 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02731                        uint16_t TIM_ICFilter)
02732 {
02733   uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
02734
02735   /* Disable the Channel 2: Reset the CC2E Bit */
02736   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
02737   tmpccmr1 = TIMx->CCMR1;
02738   tmpccer = TIMx->CCER;
02739   tmp = (uint16_t)(TIM_ICPolarity << 4);
02740   /* Select the Input and set the filter */
02741   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
02742   tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
02743   tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
02744   /* Select the Polarity and set the CC2E Bit */
02745   tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
02746   tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
02747   /* Write to TIMx CCMR1 and CCER registers */
02748   TIMx->CCMR1 = tmpccmr1 ;
02749   TIMx->CCER = tmpccer;
02750 }
02751
02752 /**
02753   * @brief  Configure the TI3 as Input.
02754   * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
02755   * @param  TIM_ICPolarity : The Input Polarity.
02756   *   This parameter can be one of the following values:
02757   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02758   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02759   * @param  TIM_ICSelection: specifies the input to be used.
02760   *   This parameter can be one of the following values:
02761   *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
02762   *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
02763   *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
02764   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02765   *   This parameter must be a value between 0x00 and 0x0F.
02766   * @retval None
02767   */
02768 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02769                        uint16_t TIM_ICFilter)
02770 {
02771   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02772
02773   /* Disable the Channel 3: Reset the CC3E Bit */
02774   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
02775   tmpccmr2 = TIMx->CCMR2;
02776   tmpccer = TIMx->CCER;
02777   tmp = (uint16_t)(TIM_ICPolarity << 8);
02778   /* Select the Input and set the filter */
02779   tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
02780   tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02781   /* Select the Polarity and set the CC3E Bit */
02782   tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
02783   tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
02784   /* Write to TIMx CCMR2 and CCER registers */
02785   TIMx->CCMR2 = tmpccmr2;
02786   TIMx->CCER = tmpccer;
02787 }
02788
02789 /**
02790   * @brief  Configure the TI4 as Input.
02791   * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
02792   * @param  TIM_ICPolarity : The Input Polarity.
02793   *   This parameter can be one of the following values:
02794   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
02795   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
02796   * @param  TIM_ICSelection: specifies the input to be used.
02797   *   This parameter can be one of the following values:
02798   *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
02799   *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
02800   *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
02801   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02802   *   This parameter must be a value between 0x00 and 0x0F.
02803   * @retval None
02804   */
02805 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02806                        uint16_t TIM_ICFilter)
02807 {
02808   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02809
02810   /* Disable the Channel 4: Reset the CC4E Bit */
02811   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
02812   tmpccmr2 = TIMx->CCMR2;
02813   tmpccer = TIMx->CCER;
02814   tmp = (uint16_t)(TIM_ICPolarity << 12);
02815   /* Select the Input and set the filter */
02816   tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
02817   tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
02818   tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
02819
02820   /* Select the Polarity and set the CC4E Bit */
02821   tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
02822   tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
02823   /* Write to TIMx CCMR2 and CCER registers */
02824   TIMx->CCMR2 = tmpccmr2;
02825   TIMx->CCER = tmpccer ;
02826 }
02827
02828 /**
02829   * @}
02830   */
02831
02832 /**
02833   * @}
02834   */
02835
02836 /**
02837   * @}
02838   */
02839
02840 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_tim.h Source File

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stm32l1xx_tim.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the TIM firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_TIM_H
00028 #define __STM32L1xx_TIM_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup TIM
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  TIM Time Base Init structure definition
00049   * @note   This structure is used with all TIMx except for TIM6 and TIM7.
00050   */
00051
00052 typedef struct
00053 {
00054   uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00055                                        This parameter can be a number between 0x0000 and 0xFFFF */
00056
00057   uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
00058                                        This parameter can be a value of @ref TIM_Counter_Mode */
00059
00060   uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
00061                                        Auto-Reload Register at the next update event.
00062                                        This parameter must be a number between 0x0000 and 0xFFFF.  */
00063
00064   uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
00065                                       This parameter can be a value of @ref TIM_Clock_Division_CKD */
00066
00067 } TIM_TimeBaseInitTypeDef;
00068
00069 /**
00070   * @brief  TIM Output Compare Init structure definition
00071   */
00072
00073 typedef struct
00074 {
00075   uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
00076                                    This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00077
00078   uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
00079                                    This parameter can be a value of @ref TIM_Output_Compare_state */
00080
00081   uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00082                                    This parameter can be a number between 0x0000 and 0xFFFF */
00083
00084   uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
00085                                    This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00086
00087 } TIM_OCInitTypeDef;
00088
00089 /**
00090   * @brief  TIM Input Capture Init structure definition
00091   */
00092
00093 typedef struct
00094 {
00095
00096   uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
00097                                   This parameter can be a value of @ref TIM_Channel */
00098
00099   uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
00100                                   This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00101
00102   uint16_t TIM_ICSelection;  /*!< Specifies the input.
00103                                   This parameter can be a value of @ref TIM_Input_Capture_Selection */
00104
00105   uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00106                                   This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00107
00108   uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
00109                                   This parameter can be a number between 0x0 and 0xF */
00110 } TIM_ICInitTypeDef;
00111
00112 /* Exported constants --------------------------------------------------------*/
00113
00114
00115 /** @defgroup TIM_Exported_constants
00116   * @{
00117   */
00118
00119 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00120                                    ((PERIPH) == TIM3) || \
00121                                    ((PERIPH) == TIM4) || \
00122                                    ((PERIPH) == TIM5) || \
00123                                    ((PERIPH) == TIM6) || \
00124                                    ((PERIPH) == TIM7) || \
00125                                    ((PERIPH) == TIM9) || \
00126                                    ((PERIPH) == TIM10) || \
00127                                    ((PERIPH) == TIM11))
00128
00129 /* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */
00130 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00131                                      ((PERIPH) == TIM3) || \
00132                                      ((PERIPH) == TIM4) || \
00133                                      ((PERIPH) == TIM5) || \
00134                                      ((PERIPH) == TIM9) || \
00135                                      ((PERIPH) == TIM10) || \
00136                                      ((PERIPH) == TIM11))
00137
00138 /* LIST3: TIM2, TIM3, TIM4 and TIM5 */
00139 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00140                                      ((PERIPH) == TIM3) || \
00141                                      ((PERIPH) == TIM4) || \
00142                                      ((PERIPH) == TIM5))
00143
00144 /* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */
00145 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00146                                      ((PERIPH) == TIM3) || \
00147                                      ((PERIPH) == TIM4) || \
00148                                      ((PERIPH) == TIM5) || \
00149                                      ((PERIPH) == TIM9))
00150
00151 /* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */
00152 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00153                                      ((PERIPH) == TIM3) || \
00154                                      ((PERIPH) == TIM4) || \
00155                                      ((PERIPH) == TIM5) ||\
00156                                      ((PERIPH) == TIM6) || \
00157                                      ((PERIPH) == TIM7) ||\
00158                                      ((PERIPH) == TIM9))
00159
00160 /* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */
00161 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00162                                      ((PERIPH) == TIM3) || \
00163                                      ((PERIPH) == TIM4) || \
00164                                      ((PERIPH) == TIM5) ||\
00165                                      ((PERIPH) == TIM6) || \
00166                                      ((PERIPH) == TIM7))
00167
00168 /* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */
00169 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
00170                                      ((PERIPH) == TIM3) || \
00171                                      ((PERIPH) == TIM9) || \
00172                                      ((PERIPH) == TIM10) || \
00173                                      ((PERIPH) == TIM11))
00174
00175
00176
00177 /** @defgroup TIM_Output_Compare_and_PWM_modes
00178   * @{
00179   */
00180
00181 #define TIM_OCMode_Timing                  ((uint16_t)0x0000)
00182 #define TIM_OCMode_Active                  ((uint16_t)0x0010)
00183 #define TIM_OCMode_Inactive                ((uint16_t)0x0020)
00184 #define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
00185 #define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
00186 #define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
00187 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
00188                               ((MODE) == TIM_OCMode_Active) || \
00189                               ((MODE) == TIM_OCMode_Inactive) || \
00190                               ((MODE) == TIM_OCMode_Toggle)|| \
00191                               ((MODE) == TIM_OCMode_PWM1) || \
00192                               ((MODE) == TIM_OCMode_PWM2))
00193 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
00194                           ((MODE) == TIM_OCMode_Active) || \
00195                           ((MODE) == TIM_OCMode_Inactive) || \
00196                           ((MODE) == TIM_OCMode_Toggle)|| \
00197                           ((MODE) == TIM_OCMode_PWM1) || \
00198                           ((MODE) == TIM_OCMode_PWM2) ||        \
00199                           ((MODE) == TIM_ForcedAction_Active) || \
00200                           ((MODE) == TIM_ForcedAction_InActive))
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup TIM_One_Pulse_Mode
00206   * @{
00207   */
00208
00209 #define TIM_OPMode_Single                  ((uint16_t)0x0008)
00210 #define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
00211 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
00212                                ((MODE) == TIM_OPMode_Repetitive))
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup TIM_Channel
00218   * @{
00219   */
00220
00221 #define TIM_Channel_1                      ((uint16_t)0x0000)
00222 #define TIM_Channel_2                      ((uint16_t)0x0004)
00223 #define TIM_Channel_3                      ((uint16_t)0x0008)
00224 #define TIM_Channel_4                      ((uint16_t)0x000C)
00225
00226 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00227                                  ((CHANNEL) == TIM_Channel_2) || \
00228                                  ((CHANNEL) == TIM_Channel_3) || \
00229                                  ((CHANNEL) == TIM_Channel_4))
00230
00231 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00232                                       ((CHANNEL) == TIM_Channel_2))
00233
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup TIM_Clock_Division_CKD
00239   * @{
00240   */
00241
00242 #define TIM_CKD_DIV1                       ((uint16_t)0x0000)
00243 #define TIM_CKD_DIV2                       ((uint16_t)0x0100)
00244 #define TIM_CKD_DIV4                       ((uint16_t)0x0200)
00245 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
00246                              ((DIV) == TIM_CKD_DIV2) || \
00247                              ((DIV) == TIM_CKD_DIV4))
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup TIM_Counter_Mode
00253   * @{
00254   */
00255
00256 #define TIM_CounterMode_Up                 ((uint16_t)0x0000)
00257 #define TIM_CounterMode_Down               ((uint16_t)0x0010)
00258 #define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
00259 #define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
00260 #define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
00261 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
00262                                    ((MODE) == TIM_CounterMode_Down) || \
00263                                    ((MODE) == TIM_CounterMode_CenterAligned1) || \
00264                                    ((MODE) == TIM_CounterMode_CenterAligned2) || \
00265                                    ((MODE) == TIM_CounterMode_CenterAligned3))
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup TIM_Output_Compare_Polarity
00271   * @{
00272   */
00273
00274 #define TIM_OCPolarity_High                ((uint16_t)0x0000)
00275 #define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
00276 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
00277                                       ((POLARITY) == TIM_OCPolarity_Low))
00278 /**
00279   * @}
00280   */
00281
00282
00283 /** @defgroup TIM_Output_Compare_state
00284   * @{
00285   */
00286
00287 #define TIM_OutputState_Disable            ((uint16_t)0x0000)
00288 #define TIM_OutputState_Enable             ((uint16_t)0x0001)
00289 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
00290                                     ((STATE) == TIM_OutputState_Enable))
00291 /**
00292   * @}
00293   */
00294
00295
00296 /** @defgroup TIM_Capture_Compare_state
00297   * @{
00298   */
00299
00300 #define TIM_CCx_Enable                      ((uint16_t)0x0001)
00301 #define TIM_CCx_Disable                     ((uint16_t)0x0000)
00302 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
00303                          ((CCX) == TIM_CCx_Disable))
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup TIM_Input_Capture_Polarity
00309   * @{
00310   */
00311
00312 #define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
00313 #define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
00314 #define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
00315 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00316                                       ((POLARITY) == TIM_ICPolarity_Falling)|| \
00317                                       ((POLARITY) == TIM_ICPolarity_BothEdge))
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup TIM_Input_Capture_Selection
00323   * @{
00324   */
00325
00326 #define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
00327                                                                    connected to IC1, IC2, IC3 or IC4, respectively */
00328 #define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
00329                                                                    connected to IC2, IC1, IC4 or IC3, respectively. */
00330 #define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
00331 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
00332                                         ((SELECTION) == TIM_ICSelection_IndirectTI) || \
00333                                         ((SELECTION) == TIM_ICSelection_TRC))
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup TIM_Input_Capture_Prescaler
00339   * @{
00340   */
00341
00342 #define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
00343 #define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
00344 #define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
00345 #define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
00346 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
00347                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
00348                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
00349                                         ((PRESCALER) == TIM_ICPSC_DIV8))
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup TIM_interrupt_sources
00355   * @{
00356   */
00357
00358 #define TIM_IT_Update                      ((uint16_t)0x0001)
00359 #define TIM_IT_CC1                         ((uint16_t)0x0002)
00360 #define TIM_IT_CC2                         ((uint16_t)0x0004)
00361 #define TIM_IT_CC3                         ((uint16_t)0x0008)
00362 #define TIM_IT_CC4                         ((uint16_t)0x0010)
00363 #define TIM_IT_Trigger                     ((uint16_t)0x0040)
00364 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
00365
00366 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
00367                            ((IT) == TIM_IT_CC1) || \
00368                            ((IT) == TIM_IT_CC2) || \
00369                            ((IT) == TIM_IT_CC3) || \
00370                            ((IT) == TIM_IT_CC4) || \
00371                            ((IT) == TIM_IT_Trigger))
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup TIM_DMA_Base_address
00377   * @{
00378   */
00379
00380 #define TIM_DMABase_CR1                    ((uint16_t)0x0000)
00381 #define TIM_DMABase_CR2                    ((uint16_t)0x0001)
00382 #define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
00383 #define TIM_DMABase_DIER                   ((uint16_t)0x0003)
00384 #define TIM_DMABase_SR                     ((uint16_t)0x0004)
00385 #define TIM_DMABase_EGR                    ((uint16_t)0x0005)
00386 #define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
00387 #define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
00388 #define TIM_DMABase_CCER                   ((uint16_t)0x0008)
00389 #define TIM_DMABase_CNT                    ((uint16_t)0x0009)
00390 #define TIM_DMABase_PSC                    ((uint16_t)0x000A)
00391 #define TIM_DMABase_ARR                    ((uint16_t)0x000B)
00392 #define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
00393 #define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
00394 #define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
00395 #define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
00396 #define TIM_DMABase_DCR                    ((uint16_t)0x0012)
00397 #define TIM_DMABase_OR                     ((uint16_t)0x0013)
00398 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
00399                                ((BASE) == TIM_DMABase_CR2) || \
00400                                ((BASE) == TIM_DMABase_SMCR) || \
00401                                ((BASE) == TIM_DMABase_DIER) || \
00402                                ((BASE) == TIM_DMABase_SR) || \
00403                                ((BASE) == TIM_DMABase_EGR) || \
00404                                ((BASE) == TIM_DMABase_CCMR1) || \
00405                                ((BASE) == TIM_DMABase_CCMR2) || \
00406                                ((BASE) == TIM_DMABase_CCER) || \
00407                                ((BASE) == TIM_DMABase_CNT) || \
00408                                ((BASE) == TIM_DMABase_PSC) || \
00409                                ((BASE) == TIM_DMABase_ARR) || \
00410                                ((BASE) == TIM_DMABase_CCR1) || \
00411                                ((BASE) == TIM_DMABase_CCR2) || \
00412                                ((BASE) == TIM_DMABase_CCR3) || \
00413                                ((BASE) == TIM_DMABase_CCR4) || \
00414                                ((BASE) == TIM_DMABase_DCR) || \
00415                                ((BASE) == TIM_DMABase_OR))
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup TIM_DMA_Burst_Length
00421   * @{
00422   */
00423
00424 #define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
00425 #define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
00426 #define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
00427 #define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
00428 #define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
00429 #define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
00430 #define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
00431 #define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
00432 #define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
00433 #define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
00434 #define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
00435 #define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
00436 #define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
00437 #define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
00438 #define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
00439 #define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
00440 #define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
00441 #define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
00442 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
00443                                    ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
00444                                    ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
00445                                    ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
00446                                    ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
00447                                    ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
00448                                    ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
00449                                    ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
00450                                    ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
00451                                    ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
00452                                    ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
00453                                    ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
00454                                    ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
00455                                    ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
00456                                    ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
00457                                    ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
00458                                    ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
00459                                    ((LENGTH) == TIM_DMABurstLength_18Transfers))
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup TIM_DMA_sources
00465   * @{
00466   */
00467
00468 #define TIM_DMA_Update                     ((uint16_t)0x0100)
00469 #define TIM_DMA_CC1                        ((uint16_t)0x0200)
00470 #define TIM_DMA_CC2                        ((uint16_t)0x0400)
00471 #define TIM_DMA_CC3                        ((uint16_t)0x0800)
00472 #define TIM_DMA_CC4                        ((uint16_t)0x1000)
00473 #define TIM_DMA_Trigger                    ((uint16_t)0x4000)
00474 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
00475
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup TIM_External_Trigger_Prescaler
00481   * @{
00482   */
00483
00484 #define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
00485 #define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
00486 #define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
00487 #define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
00488 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
00489                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
00490                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
00491                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup TIM_Internal_Trigger_Selection
00497   * @{
00498   */
00499
00500 #define TIM_TS_ITR0                        ((uint16_t)0x0000)
00501 #define TIM_TS_ITR1                        ((uint16_t)0x0010)
00502 #define TIM_TS_ITR2                        ((uint16_t)0x0020)
00503 #define TIM_TS_ITR3                        ((uint16_t)0x0030)
00504 #define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
00505 #define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
00506 #define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
00507 #define TIM_TS_ETRF                        ((uint16_t)0x0070)
00508 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00509                                              ((SELECTION) == TIM_TS_ITR1) || \
00510                                              ((SELECTION) == TIM_TS_ITR2) || \
00511                                              ((SELECTION) == TIM_TS_ITR3) || \
00512                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
00513                                              ((SELECTION) == TIM_TS_TI1FP1) || \
00514                                              ((SELECTION) == TIM_TS_TI2FP2) || \
00515                                              ((SELECTION) == TIM_TS_ETRF))
00516 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00517                                                       ((SELECTION) == TIM_TS_ITR1) || \
00518                                                       ((SELECTION) == TIM_TS_ITR2) || \
00519                                                       ((SELECTION) == TIM_TS_ITR3))
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup TIM_TIx_External_Clock_Source
00525   * @{
00526   */
00527
00528 #define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
00529 #define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
00530 #define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
00531
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup TIM_External_Trigger_Polarity
00537   * @{
00538   */
00539 #define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
00540 #define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
00541 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
00542                                        ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup TIM_Prescaler_Reload_Mode
00548   * @{
00549   */
00550
00551 #define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
00552 #define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
00553 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
00554                                          ((RELOAD) == TIM_PSCReloadMode_Immediate))
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup TIM_Forced_Action
00560   * @{
00561   */
00562
00563 #define TIM_ForcedAction_Active            ((uint16_t)0x0050)
00564 #define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
00565 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
00566                                       ((ACTION) == TIM_ForcedAction_InActive))
00567 /**
00568   * @}
00569   */
00570
00571 /** @defgroup TIM_Encoder_Mode
00572   * @{
00573   */
00574
00575 #define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
00576 #define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
00577 #define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
00578 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
00579                                    ((MODE) == TIM_EncoderMode_TI2) || \
00580                                    ((MODE) == TIM_EncoderMode_TI12))
00581 /**
00582   * @}
00583   */
00584
00585
00586 /** @defgroup TIM_Event_Source
00587   * @{
00588   */
00589
00590 #define TIM_EventSource_Update             ((uint16_t)0x0001)
00591 #define TIM_EventSource_CC1                ((uint16_t)0x0002)
00592 #define TIM_EventSource_CC2                ((uint16_t)0x0004)
00593 #define TIM_EventSource_CC3                ((uint16_t)0x0008)
00594 #define TIM_EventSource_CC4                ((uint16_t)0x0010)
00595 #define TIM_EventSource_Trigger            ((uint16_t)0x0040)
00596 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
00597
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup TIM_Update_Source
00603   * @{
00604   */
00605
00606 #define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
00607                                                                    or the setting of UG bit, or an update generation
00608                                                                    through the slave mode controller. */
00609 #define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
00610 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
00611                                       ((SOURCE) == TIM_UpdateSource_Regular))
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup TIM_Output_Compare_Preload_State
00617   * @{
00618   */
00619
00620 #define TIM_OCPreload_Enable               ((uint16_t)0x0008)
00621 #define TIM_OCPreload_Disable              ((uint16_t)0x0000)
00622 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
00623                                        ((STATE) == TIM_OCPreload_Disable))
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_Output_Compare_Fast_State
00629   * @{
00630   */
00631
00632 #define TIM_OCFast_Enable                  ((uint16_t)0x0004)
00633 #define TIM_OCFast_Disable                 ((uint16_t)0x0000)
00634 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
00635                                     ((STATE) == TIM_OCFast_Disable))
00636
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup TIM_Output_Compare_Clear_State
00642   * @{
00643   */
00644
00645 #define TIM_OCClear_Enable                 ((uint16_t)0x0080)
00646 #define TIM_OCClear_Disable                ((uint16_t)0x0000)
00647 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
00648                                      ((STATE) == TIM_OCClear_Disable))
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup TIM_Trigger_Output_Source
00654   * @{
00655   */
00656
00657 #define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
00658 #define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
00659 #define TIM_TRGOSource_Update              ((uint16_t)0x0020)
00660 #define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
00661 #define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
00662 #define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
00663 #define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
00664 #define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
00665 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
00666                                     ((SOURCE) == TIM_TRGOSource_Enable) || \
00667                                     ((SOURCE) == TIM_TRGOSource_Update) || \
00668                                     ((SOURCE) == TIM_TRGOSource_OC1) || \
00669                                     ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
00670                                     ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
00671                                     ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
00672                                     ((SOURCE) == TIM_TRGOSource_OC4Ref))
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup TIM_Slave_Mode
00678   * @{
00679   */
00680
00681 #define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
00682 #define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
00683 #define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
00684 #define TIM_SlaveMode_External1            ((uint16_t)0x0007)
00685 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
00686                                  ((MODE) == TIM_SlaveMode_Gated) || \
00687                                  ((MODE) == TIM_SlaveMode_Trigger) || \
00688                                  ((MODE) == TIM_SlaveMode_External1))
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup TIM_Master_Slave_Mode
00694   * @{
00695   */
00696
00697 #define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
00698 #define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
00699 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
00700                                  ((STATE) == TIM_MasterSlaveMode_Disable))
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup TIM_Flags
00706   * @{
00707   */
00708
00709 #define TIM_FLAG_Update                    ((uint16_t)0x0001)
00710 #define TIM_FLAG_CC1                       ((uint16_t)0x0002)
00711 #define TIM_FLAG_CC2                       ((uint16_t)0x0004)
00712 #define TIM_FLAG_CC3                       ((uint16_t)0x0008)
00713 #define TIM_FLAG_CC4                       ((uint16_t)0x0010)
00714 #define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
00715 #define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
00716 #define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
00717 #define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
00718 #define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
00719 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
00720                                ((FLAG) == TIM_FLAG_CC1) || \
00721                                ((FLAG) == TIM_FLAG_CC2) || \
00722                                ((FLAG) == TIM_FLAG_CC3) || \
00723                                ((FLAG) == TIM_FLAG_CC4) || \
00724                                ((FLAG) == TIM_FLAG_Trigger) || \
00725                                ((FLAG) == TIM_FLAG_CC1OF) || \
00726                                ((FLAG) == TIM_FLAG_CC2OF) || \
00727                                ((FLAG) == TIM_FLAG_CC3OF) || \
00728                                ((FLAG) == TIM_FLAG_CC4OF))
00729 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
00730
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup TIM_Input_Capture_Filer_Value
00736   * @{
00737   */
00738
00739 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
00740 /**
00741   * @}
00742   */
00743
00744 /** @defgroup TIM_External_Trigger_Filter
00745   * @{
00746   */
00747
00748 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
00749 /**
00750   * @}
00751   */
00752
00753 /** @defgroup TIM_OCReferenceClear
00754   * @{
00755   */
00756 #define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
00757 #define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
00758 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
00759                                               ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
00760
00761 /**
00762   * @}
00763   */
00764
00765 /** @defgroup TIM_Remap
00766   * @{
00767   */
00768
00769 #define TIM2_TIM10_OC                      ((uint32_t)0xFFFE0000)
00770 #define TIM2_TIM5_TRGO                     ((uint32_t)0xFFFE0001)
00771
00772 #define TIM3_TIM11_OC                      ((uint32_t)0xFFFE0000)
00773 #define TIM3_TIM5_TRGO                     ((uint32_t)0xFFFE0001)
00774
00775 #define TIM9_GPIO                          ((uint32_t)0xFFFC0000)
00776 #define TIM9_LSE                           ((uint32_t)0xFFFC0001)
00777
00778 #define TIM9_TIM3_TRGO                     ((uint32_t)0xFFFB0000)
00779 #define TIM9_TS_IO                         ((uint32_t)0xFFFB0004)
00780
00781 #define TIM10_GPIO                         ((uint32_t)0xFFF40000)
00782 #define TIM10_LSI                          ((uint32_t)0xFFF40001)
00783 #define TIM10_LSE                          ((uint32_t)0xFFF40002)
00784 #define TIM10_RTC                          ((uint32_t)0xFFF40003)
00785 #define TIM10_RI                           ((uint32_t)0xFFF40008)
00786
00787 #define TIM10_ETR_LSE                      ((uint32_t)0xFFFB0000)
00788 #define TIM10_ETR_TIM9_TRGO                ((uint32_t)0xFFFB0004)
00789
00790 #define TIM11_GPIO                         ((uint32_t)0xFFF40000)
00791 #define TIM11_MSI                          ((uint32_t)0xFFF40001)
00792 #define TIM11_HSE_RTC                      ((uint32_t)0xFFF40002)
00793 #define TIM11_RI                           ((uint32_t)0xFFF40008)
00794
00795 #define TIM11_ETR_LSE                      ((uint32_t)0xFFFB0000)
00796 #define TIM11_ETR_TIM9_TRGO                ((uint32_t)0xFFFB0004)
00797
00798 #define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM2_TIM10_OC)|| \
00799                                   ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \
00800                                   ((TIM_REMAP) == TIM3_TIM11_OC)|| \
00801                                   ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \
00802                                   ((TIM_REMAP) == TIM9_GPIO)|| \
00803                                   ((TIM_REMAP) == TIM9_LSE)|| \
00804                                   ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \
00805                                   ((TIM_REMAP) == TIM9_TS_IO)|| \
00806                                   ((TIM_REMAP) == TIM10_GPIO)|| \
00807                                   ((TIM_REMAP) == TIM10_LSI)|| \
00808                                   ((TIM_REMAP) == TIM10_LSE)|| \
00809                                   ((TIM_REMAP) == TIM10_RTC)|| \
00810                                   ((TIM_REMAP) == TIM10_RI)|| \
00811                                   ((TIM_REMAP) == TIM10_ETR_LSE)|| \
00812                                   ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \
00813                                   ((TIM_REMAP) == TIM11_GPIO)|| \
00814                                   ((TIM_REMAP) == TIM11_MSI)|| \
00815                                   ((TIM_REMAP) == TIM11_HSE_RTC)|| \
00816                                   ((TIM_REMAP) == TIM11_RI)|| \
00817                                   ((TIM_REMAP) == TIM11_ETR_LSE)|| \
00818                                   ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))
00819
00820 /**
00821   * @}
00822   */
00823
00824 /** @defgroup TIM_Legacy
00825   * @{
00826   */
00827
00828 #define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
00829 #define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
00830 #define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
00831 #define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
00832 #define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
00833 #define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
00834 #define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
00835 #define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
00836 #define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
00837 #define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
00838 #define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
00839 #define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
00840 #define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
00841 #define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
00842 #define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
00843 #define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
00844 #define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
00845 #define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
00846 /**
00847   * @}
00848   */
00849
00850 /**
00851   * @}
00852   */
00853
00854 /* Exported macro ------------------------------------------------------------*/
00855 /* Exported functions ------------------------------------------------------- */
00856
00857 /* TimeBase management ********************************************************/
00858 void TIM_DeInit(TIM_TypeDef* TIMx);
00859 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
00860 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
00861 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
00862 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
00863 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
00864 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
00865 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
00866 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
00867 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
00868 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
00869 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
00870 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
00871 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
00872 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
00873
00874 /* Output Compare management **************************************************/
00875 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
00876 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
00877 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
00878 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
00879 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
00880 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
00881 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
00882 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
00883 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
00884 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
00885 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
00886 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
00887 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
00888 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
00889 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
00890 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
00891 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
00892 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
00893 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
00894 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
00895 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
00896 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
00897 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
00898 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
00899 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
00900 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
00901 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
00902 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
00903 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
00904 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
00905 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
00906 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
00907
00908 /* Input Capture management ***************************************************/
00909 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
00910 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
00911 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
00912 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
00913 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
00914 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
00915 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
00916 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
00917 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
00918 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
00919 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
00920
00921 /* Interrupts, DMA and flags management ***************************************/
00922 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
00923 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
00924 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
00925 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
00926 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
00927 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
00928 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
00929 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
00930 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
00931
00932 /* Clocks management **********************************************************/
00933 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
00934 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
00935 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
00936                                 uint16_t TIM_ICPolarity, uint16_t ICFilter);
00937 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
00938                              uint16_t ExtTRGFilter);
00939 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
00940                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
00941
00942
00943 /* Synchronization management *************************************************/
00944 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
00945 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
00946 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
00947 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
00948 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
00949                    uint16_t ExtTRGFilter);
00950
00951 /* Specific interface management **********************************************/
00952 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
00953                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
00954 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
00955
00956 /* Specific remapping management **********************************************/
00957 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);
00958
00959
00960 #ifdef __cplusplus
00961 }
00962 #endif
00963
00964 #endif /*__STM32L1xx_TIM_H */
00965
00966 /**
00967   * @}
00968   */
00969
00970 /**
00971   * @}
00972   */
00973
00974 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_usart.c Source File

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stm32l1xx_usart.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Universal synchronous asynchronous receiver
00009   *          transmitter (USART):
00010   *           + Initialization and Configuration
00011   *           + Data transfers
00012   *           + Multi-Processor Communication
00013   *           + LIN mode
00014   *           + Half-duplex mode
00015   *           + Smartcard mode
00016   *           + IrDA mode
00017   *           + DMA transfers management
00018   *           + Interrupts and flags management
00019   *
00020   *  @verbatim
00021  ===============================================================================
00022                        ##### How to use this driver #####
00023  ===============================================================================
00024     [..]
00025         (#) Enable peripheral clock using
00026             RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) function for
00027             USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
00028             function for USART2 and USART3.
00029         (#) According to the USART mode, enable the GPIO clocks using
00030             RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
00031             or and SCLK).
00032         (#) Peripheral's alternate function:
00033             (++) Connect the pin to the desired peripherals' Alternate
00034                  Function (AF) using GPIO_PinAFConfig() function.
00035             (++) Configure the desired pin in alternate function by:
00036                  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
00037             (++) Select the type, pull-up/pull-down and output speed via
00038                  GPIO_PuPd, GPIO_OType and GPIO_Speed members.
00039             (++) Call GPIO_Init() function.
00040         (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
00041                flow control and Mode(Receiver/Transmitter) using the SPI_Init()
00042                function.
00043         (#) For synchronous mode, enable the clock and program the polarity,
00044             phase and last bit using the USART_ClockInit() function.
00045         (#) Enable the NVIC and the corresponding interrupt using the function
00046             USART_ITConfig() if you need to use interrupt mode.
00047         (#) When using the DMA mode.
00048             (++) Configure the DMA using DMA_Init() function.
00049             (++) Active the needed channel Request using USART_DMACmd() function.
00050         (#) Enable the USART using the USART_Cmd() function.
00051         (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
00052     [..]
00053         Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
00054         for more details.
00055
00056 @endverbatim
00057
00058   ******************************************************************************
00059    @attention
00060   *
00061   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00062   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00063   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00064   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00065   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00066   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00067   *
00068   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00069   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00070   *
00071   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00072   ******************************************************************************
00073   */
00074
00075 /* Includes ------------------------------------------------------------------*/
00076 #include "stm32l1xx_usart.h"
00077 #include "stm32l1xx_rcc.h"
00078
00079 /** @addtogroup STM32L1xx_StdPeriph_Driver
00080   * @{
00081   */
00082
00083 /** @defgroup USART
00084   * @brief USART driver modules
00085   * @{
00086   */
00087
00088 /* Private typedef -----------------------------------------------------------*/
00089 /* Private define ------------------------------------------------------------*/
00090
00091 /*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
00092 #define CR1_CLEAR_MASK            ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
00093                                               USART_CR1_PS | USART_CR1_TE | \
00094                                               USART_CR1_RE))
00095
00096 /*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
00097 #define CR2_CLOCK_CLEAR_MASK      ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
00098                                               USART_CR2_CPHA | USART_CR2_LBCL))
00099
00100 /*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
00101 #define CR3_CLEAR_MASK            ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
00102
00103 /*!< USART Interrupts mask */
00104 #define IT_MASK                   ((uint16_t)0x001F)
00105
00106 /* Private macro -------------------------------------------------------------*/
00107 /* Private variables ---------------------------------------------------------*/
00108 /* Private function prototypes -----------------------------------------------*/
00109 /* Private functions ---------------------------------------------------------*/
00110
00111 /** @defgroup USART_Private_Functions
00112   * @{
00113   */
00114
00115 /** @defgroup USART_Group1 Initialization and Configuration functions
00116  *  @brief   Initialization and Configuration functions
00117  *
00118 @verbatim
00119  ===============================================================================
00120           ##### Initialization and Configuration functions #####
00121  ===============================================================================
00122     [..]
00123         This subsection provides a set of functions allowing to initialize the USART
00124         in asynchronous and in synchronous modes.
00125         (+) For the asynchronous mode only these parameters can be configured:
00126         (+) Baud Rate.
00127         (+) Word Length.
00128         (+) Stop Bit.
00129         (+) Parity: If the parity is enabled, then the MSB bit of the data written
00130           in the data register is transmitted but is changed by the parity bit.
00131           Depending on the frame length defined by the M bit (8-bits or 9-bits),
00132           the possible USART frame formats are as listed in the following table:
00133     [..]
00134    +-------------------------------------------------------------+
00135    |   M bit |  PCE bit  |            USART frame                |
00136    |---------------------|---------------------------------------|
00137    |    0    |    0      |    | SB | 8 bit data | STB |          |
00138    |---------|-----------|---------------------------------------|
00139    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00140    |---------|-----------|---------------------------------------|
00141    |    1    |    0      |    | SB | 9 bit data | STB |          |
00142    |---------|-----------|---------------------------------------|
00143    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00144    +-------------------------------------------------------------+
00145     [..]
00146         (+) Hardware flow control.
00147         (+) Receiver/transmitter modes.
00148     [..] The USART_Init() function follows the USART  asynchronous configuration
00149          procedure(details for the procedure are available in reference manual
00150          (RM0038)).
00151         (+) For the synchronous mode in addition to the asynchronous mode parameters
00152             these parameters should be also configured:
00153             (++) USART Clock Enabled.
00154             (++) USART polarity.
00155             (++) USART phase.
00156             (++) USART LastBit.
00157     [..] These parameters can be configured using the USART_ClockInit() function.
00158
00159 @endverbatim
00160   * @{
00161   */
00162
00163 /**
00164   * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
00165   * @param  USARTx: Select the USART peripheral.
00166   *   This parameter can be one of the following values: USART1, USART2, USART3,
00167   *   UART4 or UART5.
00168   * @retval None.
00169   */
00170 void USART_DeInit(USART_TypeDef* USARTx)
00171 {
00172   /* Check the parameters */
00173   assert_param(IS_USART_ALL_PERIPH(USARTx));
00174
00175   if (USARTx == USART1)
00176   {
00177     RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
00178     RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
00179   }
00180   else if (USARTx == USART2)
00181   {
00182     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
00183     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
00184   }
00185   else if (USARTx == USART3)
00186   {
00187     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
00188     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
00189   }
00190   else if (USARTx == UART4)
00191   {
00192     RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
00193     RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
00194   }
00195   else
00196   {
00197     if (USARTx == UART5)
00198     {
00199       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
00200       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
00201     }
00202   }
00203 }
00204
00205 /**
00206   * @brief  Initializes the USARTx peripheral according to the specified
00207   *   parameters in the USART_InitStruct.
00208   * @param  USARTx: Select the USART peripheral.
00209   *   This parameter can be one of the following values: USART1, USART2, USART3,
00210   *   UART4 or UART5.
00211   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00212   *        contains the configuration information for the specified USART peripheral.
00213   * @retval None.
00214   */
00215 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
00216 {
00217   uint32_t tmpreg = 0x00, apbclock = 0x00;
00218   uint32_t integerdivider = 0x00;
00219   uint32_t fractionaldivider = 0x00;
00220   RCC_ClocksTypeDef RCC_ClocksStatus;
00221
00222   /* Check the parameters */
00223   assert_param(IS_USART_ALL_PERIPH(USARTx));
00224   assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
00225   assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
00226   assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
00227   assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
00228   assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
00229   assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
00230
00231   /* The hardware flow control is available only for USART1, USART2 and USART3 */
00232   if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
00233   {
00234     assert_param(IS_USART_123_PERIPH(USARTx));
00235   }
00236
00237 /*---------------------------- USART CR2 Configuration -----------------------*/
00238   tmpreg = USARTx->CR2;
00239   /* Clear STOP[13:12] bits */
00240   tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
00241
00242   /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
00243   /* Set STOP[13:12] bits according to USART_StopBits value */
00244   tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
00245
00246   /* Write to USART CR2 */
00247   USARTx->CR2 = (uint16_t)tmpreg;
00248
00249 /*---------------------------- USART CR1 Configuration -----------------------*/
00250   tmpreg = USARTx->CR1;
00251   /* Clear M, PCE, PS, TE and RE bits */
00252   tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
00253
00254   /* Configure the USART Word Length, Parity and mode ----------------------- */
00255   /* Set the M bits according to USART_WordLength value */
00256   /* Set PCE and PS bits according to USART_Parity value */
00257   /* Set TE and RE bits according to USART_Mode value */
00258   tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00259             USART_InitStruct->USART_Mode;
00260
00261   /* Write to USART CR1 */
00262   USARTx->CR1 = (uint16_t)tmpreg;
00263
00264 /*---------------------------- USART CR3 Configuration -----------------------*/
00265   tmpreg = USARTx->CR3;
00266   /* Clear CTSE and RTSE bits */
00267   tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
00268
00269   /* Configure the USART HFC -------------------------------------------------*/
00270   /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
00271   tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
00272
00273   /* Write to USART CR3 */
00274   USARTx->CR3 = (uint16_t)tmpreg;
00275
00276 /*---------------------------- USART BRR Configuration -----------------------*/
00277   /* Configure the USART Baud Rate -------------------------------------------*/
00278   RCC_GetClocksFreq(&RCC_ClocksStatus);
00279   if (USARTx == USART1)
00280   {
00281     apbclock = RCC_ClocksStatus.PCLK2_Frequency;
00282   }
00283   else
00284   {
00285     apbclock = RCC_ClocksStatus.PCLK1_Frequency;
00286   }
00287
00288   /* Determine the integer part */
00289   if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
00290   {
00291     /* Integer part computing in case Oversampling mode is 8 Samples */
00292     integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
00293   }
00294   else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
00295   {
00296     /* Integer part computing in case Oversampling mode is 16 Samples */
00297     integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
00298   }
00299   tmpreg = (integerdivider / 100) << 4;
00300
00301   /* Determine the fractional part */
00302   fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
00303
00304   /* Implement the fractional part in the register */
00305   if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
00306   {
00307     tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
00308   }
00309   else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
00310   {
00311     tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
00312   }
00313
00314   /* Write to USART BRR */
00315   USARTx->BRR = (uint16_t)tmpreg;
00316 }
00317
00318 /**
00319   * @brief  Fills each USART_InitStruct member with its default value.
00320   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
00321   *   which will be initialized.
00322   * @retval None
00323   */
00324 void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
00325 {
00326   /* USART_InitStruct members default value */
00327   USART_InitStruct->USART_BaudRate = 9600;
00328   USART_InitStruct->USART_WordLength = USART_WordLength_8b;
00329   USART_InitStruct->USART_StopBits = USART_StopBits_1;
00330   USART_InitStruct->USART_Parity = USART_Parity_No ;
00331   USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00332   USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00333 }
00334
00335 /**
00336   * @brief  Initializes the USARTx peripheral Clock according to the
00337   *         specified parameters in the USART_ClockInitStruct.
00338   * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
00339   * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
00340   *         structure that contains the configuration information for the specified
00341   *         USART peripheral.
00342   * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
00343   * @retval None.
00344   */
00345 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
00346 {
00347   uint32_t tmpreg = 0x00;
00348   /* Check the parameters */
00349   assert_param(IS_USART_123_PERIPH(USARTx));
00350   assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
00351   assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
00352   assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
00353   assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
00354
00355 /*---------------------------- USART CR2 Configuration -----------------------*/
00356   tmpreg = USARTx->CR2;
00357   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
00358   tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
00359   /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
00360   /* Set CLKEN bit according to USART_Clock value */
00361   /* Set CPOL bit according to USART_CPOL value */
00362   /* Set CPHA bit according to USART_CPHA value */
00363   /* Set LBCL bit according to USART_LastBit value */
00364   tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
00365                  USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
00366   /* Write to USART CR2 */
00367   USARTx->CR2 = (uint16_t)tmpreg;
00368 }
00369
00370 /**
00371   * @brief  Fills each USART_ClockInitStruct member with its default value.
00372   * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
00373   *   structure which will be initialized.
00374   * @retval None
00375   */
00376 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
00377 {
00378   /* USART_ClockInitStruct members default value */
00379   USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
00380   USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
00381   USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
00382   USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
00383 }
00384
00385 /**
00386   * @brief  Enables or disables the specified USART peripheral.
00387   * @param  USARTx: Select the USART peripheral.
00388   *   This parameter can be one of the following values:
00389   *   USART1, USART2, USART3, UART4 or UART5.
00390   * @param  NewState: new state of the USARTx peripheral.
00391   *         This parameter can be: ENABLE or DISABLE.
00392   * @retval None.
00393   */
00394 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
00395 {
00396   /* Check the parameters */
00397   assert_param(IS_USART_ALL_PERIPH(USARTx));
00398   assert_param(IS_FUNCTIONAL_STATE(NewState));
00399
00400   if (NewState != DISABLE)
00401   {
00402     /* Enable the selected USART by setting the UE bit in the CR1 register */
00403     USARTx->CR1 |= USART_CR1_UE;
00404   }
00405   else
00406   {
00407     /* Disable the selected USART by clearing the UE bit in the CR1 register */
00408     USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
00409   }
00410 }
00411
00412 /**
00413   * @brief  Sets the system clock prescaler.
00414   * @param  USARTx: Select the USART peripheral.
00415   *   This parameter can be one of the following values:
00416   *   USART1, USART2, USART3, UART4 or UART5.
00417   * @param  USART_Prescaler: specifies the prescaler clock.
00418   * @note   The function is used for IrDA mode with UART4 and UART5.
00419   * @retval None.
00420   */
00421 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
00422 {
00423   /* Check the parameters */
00424   assert_param(IS_USART_ALL_PERIPH(USARTx));
00425
00426   /* Clear the USART prescaler */
00427   USARTx->GTPR &= USART_GTPR_GT;
00428   /* Set the USART prescaler */
00429   USARTx->GTPR |= USART_Prescaler;
00430 }
00431
00432 /**
00433   * @brief  Enables or disables the USART's 8x oversampling mode.
00434   * @param USARTx: Select the USART peripheral.
00435   *   This parameter can be one of the following values:
00436   *     USART1, USART2, USART3, UART4 or UART5.
00437   * @param NewState: new state of the USART 8x oversampling mode.
00438   *   This parameter can be: ENABLE or DISABLE.
00439   *
00440   * @note
00441   *   This function has to be called before calling USART_Init()
00442   *   function in order to have correct baudrate Divider value.
00443   * @retval None
00444   */
00445 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
00446 {
00447   /* Check the parameters */
00448   assert_param(IS_USART_ALL_PERIPH(USARTx));
00449   assert_param(IS_FUNCTIONAL_STATE(NewState));
00450
00451   if (NewState != DISABLE)
00452   {
00453     /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
00454     USARTx->CR1 |= USART_CR1_OVER8;
00455   }
00456   else
00457   {
00458     /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
00459     USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
00460   }
00461 }
00462
00463 /**
00464   * @brief  Enables or disables the USART's one bit sampling method.
00465   * @param USARTx: Select the USART peripheral.
00466   *   This parameter can be one of the following values:
00467   *   USART1, USART2, USART3, UART4 or UART5.
00468   * @param NewState: new state of the USART one bit sampling method.
00469   *   This parameter can be: ENABLE or DISABLE.
00470   * @retval None.
00471   */
00472 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00473 {
00474   /* Check the parameters */
00475   assert_param(IS_USART_ALL_PERIPH(USARTx));
00476   assert_param(IS_FUNCTIONAL_STATE(NewState));
00477
00478   if (NewState != DISABLE)
00479   {
00480     /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
00481     USARTx->CR3 |= USART_CR3_ONEBIT;
00482   }
00483   else
00484   {
00485     /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
00486     USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
00487   }
00488 }
00489
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup USART_Group2 Data transfers functions
00495  *  @brief   Data transfers functions
00496  *
00497 @verbatim
00498  ===============================================================================
00499                     ##### Data transfers functions #####
00500  ===============================================================================
00501     [..] This subsection provides a set of functions allowing to manage
00502          the USART data transfers.
00503     [..] During an USART reception, data shifts in least significant bit first
00504          through the RX pin. In this mode, the USART_DR register consists of
00505          a buffer (RDR) between the internal bus and the received shift register.
00506          When a transmission is taking place, a write instruction to
00507          the USART_DR register stores the data in the TDR register and which is
00508          copied in the shift register at the end of the current transmission.
00509     [..] The read access of the USART_DR register can be done using
00510          the USART_ReceiveData() function and returns the RDR buffered value.
00511         Whereas a write access to the USART_DR can be done using USART_SendData()
00512         function and stores the written data into TDR buffer.
00513
00514 @endverbatim
00515   * @{
00516   */
00517
00518 /**
00519   * @brief  Transmits single data through the USARTx peripheral.
00520   * @param  USARTx: Select the USART peripheral.
00521   *   This parameter can be one of the following values:
00522   *   USART1, USART2, USART3, UART4 or UART5.
00523   * @param  Data: the data to transmit.
00524   * @retval None.
00525   */
00526 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
00527 {
00528   /* Check the parameters */
00529   assert_param(IS_USART_ALL_PERIPH(USARTx));
00530   assert_param(IS_USART_DATA(Data));
00531
00532   /* Transmit Data */
00533   USARTx->DR = (Data & (uint16_t)0x01FF);
00534 }
00535
00536 /**
00537   * @brief  Returns the most recent received data by the USARTx peripheral.
00538   * @param  USARTx: Select the USART peripheral.
00539   *   This parameter can be one of the following values:
00540   *   USART1, USART2, USART3, UART4 or UART5.
00541   * @retval The received data.
00542   */
00543 uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
00544 {
00545   /* Check the parameters */
00546   assert_param(IS_USART_ALL_PERIPH(USARTx));
00547
00548   /* Receive Data */
00549   return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
00550 }
00551
00552 /**
00553   * @}
00554   */
00555
00556 /** @defgroup USART_Group3 MultiProcessor Communication functions
00557  *  @brief   Multi-Processor Communication functions
00558  *
00559 @verbatim
00560  ===============================================================================
00561              ##### Multi-Processor Communication functions #####
00562  ===============================================================================
00563     [..] This subsection provides a set of functions allowing to manage the USART
00564          multiprocessor communication.
00565     [..] For instance one of the USARTs can be the master, its TX output is
00566          connected to the RX input of the other USART. The others are slaves,
00567          their respective TX outputs are logically ANDed together and connected
00568          to the RX input of the master. USART multiprocessor communication is
00569          possible through the following procedure:
00570          (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
00571              Mode transmitter or Mode receiver and hardware flow control values
00572              using the USART_Init() function.
00573          (#) Configures the USART address using the USART_SetAddress() function.
00574          (#) Configures the wake up methode (USART_WakeUp_IdleLine or
00575              USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
00576              for the slaves.
00577          (#) Enable the USART using the USART_Cmd() function.
00578          (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
00579              function.
00580
00581     [..] The USART Slave exit from mute mode when receive the wake up condition.
00582
00583 @endverbatim
00584   * @{
00585   */
00586
00587 /**
00588   * @brief  Sets the address of the USART node.
00589   * @param  USARTx: Select the USART peripheral.
00590   *   This parameter can be one of the following values:
00591   *   USART1, USART2, USART3, UART4 or UART5.
00592   * @param  USART_Address: Indicates the address of the USART node.
00593   * @retval None
00594   */
00595 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
00596 {
00597   /* Check the parameters */
00598   assert_param(IS_USART_ALL_PERIPH(USARTx));
00599   assert_param(IS_USART_ADDRESS(USART_Address));
00600
00601   /* Clear the USART address */
00602   USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
00603   /* Set the USART address node */
00604   USARTx->CR2 |= USART_Address;
00605 }
00606
00607 /**
00608   * @brief  Determines if the USART is in mute mode or not.
00609   * @param  USARTx: Select the USART peripheral.
00610   *   This parameter can be one of the following values:
00611   *   USART1, USART2, USART3, UART4 or UART5.
00612   * @param  NewState: new state of the USART mute mode.
00613   *   This parameter can be: ENABLE or DISABLE.
00614   * @retval None
00615   */
00616 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00617 {
00618   /* Check the parameters */
00619   assert_param(IS_USART_ALL_PERIPH(USARTx));
00620   assert_param(IS_FUNCTIONAL_STATE(NewState));
00621
00622   if (NewState != DISABLE)
00623   {
00624     /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
00625     USARTx->CR1 |= USART_CR1_RWU;
00626   }
00627   else
00628   {
00629     /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
00630     USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
00631   }
00632 }
00633 /**
00634   * @brief  Selects the USART WakeUp method.
00635   * @param  USARTx: Select the USART peripheral.
00636   *   This parameter can be one of the following values:
00637   *   USART1, USART2, USART3, UART4 or UART5.
00638   * @param  USART_WakeUp: specifies the USART wakeup method.
00639   *   This parameter can be one of the following values:
00640   *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection.
00641   *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark.
00642   * @retval None.
00643   */
00644 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
00645 {
00646   /* Check the parameters */
00647   assert_param(IS_USART_ALL_PERIPH(USARTx));
00648   assert_param(IS_USART_WAKEUP(USART_WakeUp));
00649
00650   USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
00651   USARTx->CR1 |= USART_WakeUp;
00652 }
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup USART_Group4 LIN mode functions
00659  *  @brief   LIN mode functions
00660  *
00661 @verbatim
00662  ===============================================================================
00663                        ##### LIN mode functions #####
00664  ===============================================================================
00665     [..] This subsection provides a set of functions allowing to manage the USART
00666          LIN Mode communication.
00667     [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
00668          with the LIN standard.
00669     [..] Only this LIN Feature is supported by the USART IP:
00670          (+) LIN Master Synchronous Break send capability and LIN slave break
00671              detection capability :  13-bit break generation and 10/11 bit break
00672              detection.
00673     [..] USART LIN Master transmitter communication is possible through the
00674          following procedure:
00675          (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
00676              Mode transmitter or Mode receiver and hardware flow control values
00677              using the USART_Init() function.
00678          (#) Enable the USART using the USART_Cmd() function.
00679          (#) Enable the LIN mode using the USART_LINCmd() function.
00680          (#) Send the break character using USART_SendBreak() function.
00681     [..] USART LIN Master receiver communication is possible through the
00682          following procedure:
00683          (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
00684              Mode transmitter or Mode receiver and hardware flow control values
00685             using the USART_Init() function.
00686          (#) Enable the USART using the USART_Cmd() function.
00687          (#) Configures the break detection length
00688              using the USART_LINBreakDetectLengthConfig() function.
00689          (#) Enable the LIN mode using the USART_LINCmd() function.
00690          -@- In LIN mode, the following bits must be kept cleared:
00691              (+@) CLKEN in the USART_CR2 register.
00692              (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
00693
00694 @endverbatim
00695   * @{
00696   */
00697
00698 /**
00699   * @brief  Sets the USART LIN Break detection length.
00700   * @param  USARTx: Select the USART peripheral.
00701   *   This parameter can be one of the following values:
00702   *   USART1, USART2, USART3, UART4 or UART5.
00703   * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
00704   *   This parameter can be one of the following values:
00705   *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection.
00706   *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection.
00707   * @retval None.
00708   */
00709 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
00710 {
00711   /* Check the parameters */
00712   assert_param(IS_USART_ALL_PERIPH(USARTx));
00713   assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
00714
00715   USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
00716   USARTx->CR2 |= USART_LINBreakDetectLength;
00717 }
00718
00719 /**
00720   * @brief  Enables or disables the USART's LIN mode.
00721   * @param  USARTx: Select the USART peripheral.
00722   *   This parameter can be one of the following values:
00723   *   USART1, USART2, USART3, UART4 or UART5.
00724   * @param  NewState: new state of the USART LIN mode.
00725   *   This parameter can be: ENABLE or DISABLE.
00726   * @retval None.
00727   */
00728 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00729 {
00730   /* Check the parameters */
00731   assert_param(IS_USART_ALL_PERIPH(USARTx));
00732   assert_param(IS_FUNCTIONAL_STATE(NewState));
00733
00734   if (NewState != DISABLE)
00735   {
00736     /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00737     USARTx->CR2 |= USART_CR2_LINEN;
00738   }
00739   else
00740   {
00741     /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
00742     USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
00743   }
00744 }
00745
00746 /**
00747   * @brief  Transmits break characters.
00748   * @param  USARTx: Select the USART peripheral.
00749   *   This parameter can be one of the following values:
00750   *   USART1, USART2, USART3, UART4 or UART5.
00751   * @retval None.
00752   */
00753 void USART_SendBreak(USART_TypeDef* USARTx)
00754 {
00755   /* Check the parameters */
00756   assert_param(IS_USART_ALL_PERIPH(USARTx));
00757
00758   /* Send break characters */
00759   USARTx->CR1 |= USART_CR1_SBK;
00760 }
00761
00762 /**
00763   * @}
00764   */
00765
00766 /** @defgroup USART_Group5 Halfduplex mode function
00767  *  @brief   Half-duplex mode function
00768  *
00769 @verbatim
00770  ===============================================================================
00771                    ##### Half-duplex mode function #####
00772  ===============================================================================
00773     [..] This subsection provides a set of functions allowing to manage the USART
00774          Half-duplex communication.
00775     [..] The USART can be configured to follow a single-wire half-duplex protocol
00776          where the TX and RX lines are internally connected.
00777     [..] USART Half duplex communication is possible through the following procedure:
00778          (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
00779              or Mode receiver and hardware flow control values using the USART_Init()
00780             function.
00781          (#) Configures the USART address using the USART_SetAddress() function.
00782          (#) Enable the USART using the USART_Cmd() function.
00783          (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
00784          -@- The RX pin is no longer used.
00785          -@- In Half-duplex mode the following bits must be kept cleared:
00786              (+@) LINEN and CLKEN bits in the USART_CR2 register.
00787              (+@) SCEN and IREN bits in the USART_CR3 register.
00788
00789 @endverbatim
00790   * @{
00791   */
00792
00793 /**
00794   * @brief  Enables or disables the USART's Half Duplex communication.
00795   * @param  USARTx: Select the USART peripheral.
00796   *   This parameter can be one of the following values:
00797   *   USART1, USART2, USART3, UART4 or UART5.
00798   * @param  NewState: new state of the USART Communication.
00799   *   This parameter can be: ENABLE or DISABLE.
00800   * @retval None
00801   */
00802 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00803 {
00804   /* Check the parameters */
00805   assert_param(IS_USART_ALL_PERIPH(USARTx));
00806   assert_param(IS_FUNCTIONAL_STATE(NewState));
00807
00808   if (NewState != DISABLE)
00809   {
00810     /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00811     USARTx->CR3 |= USART_CR3_HDSEL;
00812   }
00813   else
00814   {
00815     /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
00816     USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
00817   }
00818 }
00819
00820 /**
00821   * @}
00822   */
00823
00824
00825 /** @defgroup USART_Group6 Smartcard mode functions
00826  *  @brief   Smartcard mode functions
00827  *
00828 @verbatim
00829  ===============================================================================
00830                      ##### Smartcard mode functions #####
00831  ===============================================================================
00832     [..] This subsection provides a set of functions allowing to manage the USART
00833          Smartcard communication.
00834     [..] The Smartcard interface is designed to support asynchronous protocol
00835          Smartcards as defined in the ISO 7816-3 standard. The USART can provide
00836          a clock to the smartcard through the SCLK output. In smartcard mode,
00837          SCLK is not associated to the communication but is simply derived from
00838          the internal peripheral input clock through a 5-bit prescaler.
00839     [..] Smartcard communication is possible through the following procedure:
00840          (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
00841              function.
00842          (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
00843              function.
00844          (#) Program the USART clock using the USART_ClockInit() function as following:
00845              (++) USART Clock enabled.
00846              (++) USART CPOL Low.
00847              (++) USART CPHA on first edge.
00848              (++) USART Last Bit Clock Enabled.
00849          (#) Program the Smartcard interface using the USART_Init() function as
00850              following:
00851              (++) Word Length = 9 Bits.
00852              (++) 1.5 Stop Bit.
00853              (++) Even parity.
00854              (++) BaudRate = 12096 baud.
00855              (++) Hardware flow control disabled (RTS and CTS signals).
00856              (++) Tx and Rx enabled
00857          (#) Optionally you can enable the parity error interrupt using
00858              the USART_ITConfig() function.
00859          (#) Enable the USART using the USART_Cmd() function.
00860          (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
00861          (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
00862     [..]
00863   Please refer to the ISO 7816-3 specification for more details.
00864     [..]
00865          (@) It is also possible to choose 0.5 stop bit for receiving but it is
00866              recommended to use 1.5 stop bits for both transmitting and receiving
00867              to avoid switching between the two configurations.
00868          (@) In smartcard mode, the following bits must be kept cleared:
00869              (+@) LINEN bit in the USART_CR2 register.
00870              (+@) HDSEL and IREN bits in the USART_CR3 register.
00871
00872 @endverbatim
00873   * @{
00874   */
00875
00876 /**
00877   * @brief  Sets the specified USART guard time.
00878   * @param  USARTx: Select the USART peripheral.
00879   *   This parameter can be one of the following values:
00880   *   USART1, USART2 or USART3.
00881   * @param  USART_GuardTime: specifies the guard time.
00882   * @retval None.
00883   */
00884 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
00885 {
00886   /* Check the parameters */
00887   assert_param(IS_USART_123_PERIPH(USARTx));
00888
00889   /* Clear the USART Guard time */
00890   USARTx->GTPR &= USART_GTPR_PSC;
00891   /* Set the USART guard time */
00892   USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
00893 }
00894
00895 /**
00896   * @brief  Enables or disables the USART's Smart Card mode.
00897   * @param  USARTx: Select the USART peripheral.
00898   *   This parameter can be one of the following values:
00899   *   USART1, USART2 or USART3.
00900   * @param  NewState: new state of the Smart Card mode.
00901   *   This parameter can be: ENABLE or DISABLE.
00902   * @retval None
00903   */
00904 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00905 {
00906   /* Check the parameters */
00907   assert_param(IS_USART_123_PERIPH(USARTx));
00908   assert_param(IS_FUNCTIONAL_STATE(NewState));
00909   if (NewState != DISABLE)
00910   {
00911     /* Enable the SC mode by setting the SCEN bit in the CR3 register */
00912     USARTx->CR3 |= USART_CR3_SCEN;
00913   }
00914   else
00915   {
00916     /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
00917     USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
00918   }
00919 }
00920
00921 /**
00922   * @brief  Enables or disables NACK transmission.
00923   * @param  USARTx: Select the USART peripheral.
00924   *   This parameter can be one of the following values:
00925   *   USART1, USART2 or USART3.
00926   * @param  NewState: new state of the NACK transmission.
00927   *   This parameter can be: ENABLE or DISABLE.
00928   * @retval None.
00929   */
00930 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00931 {
00932   /* Check the parameters */
00933   assert_param(IS_USART_123_PERIPH(USARTx));
00934   assert_param(IS_FUNCTIONAL_STATE(NewState));
00935   if (NewState != DISABLE)
00936   {
00937     /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
00938     USARTx->CR3 |= USART_CR3_NACK;
00939   }
00940   else
00941   {
00942     /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
00943     USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
00944   }
00945 }
00946
00947 /**
00948   * @}
00949   */
00950
00951 /** @defgroup USART_Group7 IrDA mode functions
00952  *  @brief   IrDA mode functions
00953  *
00954 @verbatim
00955  ===============================================================================
00956                         ##### IrDA mode functions #####
00957  ===============================================================================
00958     [..] This subsection provides a set of functions allowing to manage the USART
00959          IrDA communication.
00960     [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
00961          any data on the IrDA receive line will be ignored by the IrDA decoder
00962          and if the Receiver is busy, data on the TX from the USART to IrDA will
00963          not be encoded by IrDA. While receiving data, transmission should be
00964          avoided as the data to be transmitted could be corrupted.
00965
00966     [..] IrDA communication is possible through the following procedure:
00967          (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
00968              Transmitter/Receiver modes and hardware flow control values using
00969              the USART_Init() function.
00970          (#) Enable the USART using the USART_Cmd() function.
00971          (#) Configures the IrDA pulse width by configuring the prescaler using
00972              the USART_SetPrescaler() function.
00973          (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal
00974              mode using the USART_IrDAConfig() function.
00975          (#) Enable the IrDA using the USART_IrDACmd() function.
00976
00977     [..]
00978     (@) A pulse of width less than two and greater than one PSC period(s) may or
00979         may not be rejected.
00980     (@) The receiver set up time should be managed by software. The IrDA physical
00981         layer specification specifies a minimum of 10 ms delay between
00982         transmission and reception (IrDA is a half duplex protocol).
00983     (@) In IrDA mode, the following bits must be kept cleared:
00984         (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
00985         (+@) SCEN and HDSEL bits in the USART_CR3 register.
00986
00987 @endverbatim
00988   * @{
00989   */
00990
00991 /**
00992   * @brief  Configures the USART's IrDA interface.
00993   * @param  USARTx: Select the USART peripheral.
00994   *   This parameter can be one of the following values:
00995   *   USART1, USART2, USART3, UART4 or UART5.
00996   * @param  USART_IrDAMode: specifies the IrDA mode.
00997   *   This parameter can be one of the following values:
00998   *     @arg USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.
00999   *     @arg USART_IrDAMode_Normal: USART IrDA Normal mode selected.
01000   * @retval None
01001   */
01002 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
01003 {
01004   /* Check the parameters */
01005   assert_param(IS_USART_ALL_PERIPH(USARTx));
01006   assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
01007
01008   USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
01009   USARTx->CR3 |= USART_IrDAMode;
01010 }
01011
01012 /**
01013   * @brief  Enables or disables the USART's IrDA interface.
01014   * @param  USARTx: Select the USART peripheral.
01015   *   This parameter can be one of the following values:
01016   *   USART1, USART2, USART3, UART4 or UART5.
01017   * @param  NewState: new state of the IrDA mode.
01018   *   This parameter can be: ENABLE or DISABLE.
01019   * @retval None
01020   */
01021 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
01022 {
01023   /* Check the parameters */
01024   assert_param(IS_USART_ALL_PERIPH(USARTx));
01025   assert_param(IS_FUNCTIONAL_STATE(NewState));
01026
01027   if (NewState != DISABLE)
01028   {
01029     /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
01030     USARTx->CR3 |= USART_CR3_IREN;
01031   }
01032   else
01033   {
01034     /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
01035     USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
01036   }
01037 }
01038
01039 /**
01040   * @}
01041   */
01042
01043 /** @defgroup USART_Group8 DMA transfers management functions
01044  *  @brief   DMA transfers management functions
01045  *
01046 @verbatim
01047  ===============================================================================
01048                ##### DMA transfers management functions #####
01049  ===============================================================================
01050
01051 @endverbatim
01052   * @{
01053   */
01054
01055 /**
01056   * @brief  Enables or disables the USART's DMA interface.
01057   * @param  USARTx: Select the USART peripheral.
01058   *   This parameter can be one of the following values:
01059   *   USART1, USART2, USART3, UART4 or UART5.
01060   * @param  USART_DMAReq: specifies the DMA request.
01061   *   This parameter can be any combination of the following values:
01062   *     @arg USART_DMAReq_Tx: USART DMA transmit request.
01063   *     @arg USART_DMAReq_Rx: USART DMA receive request.
01064   * @param  NewState: new state of the DMA Request sources.
01065   *   This parameter can be: ENABLE or DISABLE.
01066   * @retval None
01067   */
01068 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
01069 {
01070   /* Check the parameters */
01071   assert_param(IS_USART_ALL_PERIPH(USARTx));
01072   assert_param(IS_USART_DMAREQ(USART_DMAReq));
01073   assert_param(IS_FUNCTIONAL_STATE(NewState));
01074
01075   if (NewState != DISABLE)
01076   {
01077     /* Enable the DMA transfer for selected requests by setting the DMAT and/or
01078        DMAR bits in the USART CR3 register */
01079     USARTx->CR3 |= USART_DMAReq;
01080   }
01081   else
01082   {
01083     /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
01084        DMAR bits in the USART CR3 register */
01085     USARTx->CR3 &= (uint16_t)~USART_DMAReq;
01086   }
01087 }
01088
01089 /**
01090   * @}
01091   */
01092
01093 /** @defgroup USART_Group9 Interrupts and flags management functions
01094  *  @brief   Interrupts and flags management functions
01095  *
01096 @verbatim
01097  ===============================================================================
01098             ##### Interrupts and flags management functions #####
01099  ===============================================================================
01100     [..] This subsection provides a set of functions allowing to configure the
01101          USART Interrupts sources, DMA channels requests and check or clear the
01102          flags or pending bits status. The user should identify which mode will
01103          be used in his application to manage the communication: Polling mode,
01104          Interrupt mode or DMA mode.
01105  *** Polling Mode ***
01106  ====================
01107     [..] In Polling Mode, the SPI communication can be managed by 10 flags:
01108          (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
01109          (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
01110          (#) USART_FLAG_TC: to indicate the status of the transmit operation.
01111          (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
01112          (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
01113          (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
01114          (#) USART_FLAG_NE: to indicate if a noise error occur.
01115          (#) USART_FLAG_FE: to indicate if a frame error occur.
01116          (#) USART_FLAG_PE: to indicate if a parity error occur.
01117          (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
01118     [..] In this Mode it is advised to use the following functions:
01119          (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
01120          (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
01121
01122  *** Interrupt Mode ***
01123  ======================
01124     [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
01125          sources and 10 pending bits:
01126          (+) Pending Bits:
01127              (##) USART_IT_TXE: to indicate the status of the transmit buffer
01128                   register.
01129              (##) USART_IT_RXNE: to indicate the status of the receive buffer
01130                   register.
01131              (##) USART_IT_TC: to indicate the status of the transmit operation.
01132              (##) USART_IT_IDLE: to indicate the status of the Idle Line.
01133              (##) USART_IT_CTS: to indicate the status of the nCTS input.
01134              (##) USART_IT_LBD: to indicate the status of the LIN break detection.
01135              (##) USART_IT_NE: to indicate if a noise error occur.
01136              (##) USART_IT_FE: to indicate if a frame error occur.
01137              (##) USART_IT_PE: to indicate if a parity error occur.
01138              (##) USART_IT_ORE: to indicate if an Overrun error occur
01139                   (if the RXNEIE or EIE bits are set).
01140
01141          (+) Interrupt Source:
01142              (##) USART_IT_TXE: specifies the interrupt source for the Tx buffer
01143                   empty interrupt.
01144              (##) USART_IT_RXNE: specifies the interrupt source for the Rx buffer
01145                   not empty interrupt.
01146              (##) USART_IT_TC: specifies the interrupt source for the Transmit
01147                   complete interrupt.
01148              (##) USART_IT_IDLE: specifies the interrupt source for the Idle Line
01149                   interrupt.
01150              (##) USART_IT_CTS: specifies the interrupt source for the CTS interrupt.
01151              (##) USART_IT_LBD: specifies the interrupt source for the LIN break
01152                   detection interrupt.
01153              (##) USART_IT_PE: specifies the interrupt source for theparity error
01154                   interrupt.
01155              (##) USART_IT_ERR:  specifies the interrupt source for the errors
01156                   interrupt.
01157              -@@- Some parameters are coded in order to use them as interrupt
01158                  source or as pending bits.
01159     [..] In this Mode it is advised to use the following functions:
01160          (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT,
01161              FunctionalState NewState).
01162          (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
01163          (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
01164
01165  *** DMA Mode ***
01166  ================
01167     [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
01168          requests:
01169          (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
01170          (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
01171     [..] In this Mode it is advised to use the following function:
01172          (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
01173              FunctionalState NewState).
01174 @endverbatim
01175   * @{
01176   */
01177
01178 /**
01179   * @brief  Enables or disables the specified USART interrupts.
01180   * @param  USARTx: Select the USART peripheral.
01181   *   This parameter can be one of the following values:
01182   *   USART1, USART2, USART3, UART4 or UART5.
01183   * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
01184   *   This parameter can be one of the following values:
01185   *     @arg USART_IT_CTS:  CTS change interrupt.
01186   *     @arg USART_IT_LBD:  LIN Break detection interrupt.
01187   *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
01188   *     @arg USART_IT_TC:   Transmission complete interrupt.
01189   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
01190   *     @arg USART_IT_IDLE: Idle line detection interrupt.
01191   *     @arg USART_IT_PE:   Parity Error interrupt.
01192   *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error).
01193   * @param  NewState: new state of the specified USARTx interrupts.
01194   *   This parameter can be: ENABLE or DISABLE.
01195   * @retval None.
01196   */
01197 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
01198 {
01199   uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
01200   uint32_t usartxbase = 0x00;
01201   /* Check the parameters */
01202   assert_param(IS_USART_ALL_PERIPH(USARTx));
01203   assert_param(IS_USART_CONFIG_IT(USART_IT));
01204   assert_param(IS_FUNCTIONAL_STATE(NewState));
01205
01206   /* The CTS interrupt is not available for UART4 and UART5 */
01207   if (USART_IT == USART_IT_CTS)
01208   {
01209     assert_param(IS_USART_123_PERIPH(USARTx));
01210   }
01211
01212   usartxbase = (uint32_t)USARTx;
01213
01214   /* Get the USART register index */
01215   usartreg = (((uint8_t)USART_IT) >> 0x05);
01216
01217   /* Get the interrupt position */
01218   itpos = USART_IT & IT_MASK;
01219   itmask = (((uint32_t)0x01) << itpos);
01220
01221   if (usartreg == 0x01) /* The IT is in CR1 register */
01222   {
01223     usartxbase += 0x0C;
01224   }
01225   else if (usartreg == 0x02) /* The IT is in CR2 register */
01226   {
01227     usartxbase += 0x10;
01228   }
01229   else /* The IT is in CR3 register */
01230   {
01231     usartxbase += 0x14;
01232   }
01233   if (NewState != DISABLE)
01234   {
01235     *(__IO uint32_t*)usartxbase  |= itmask;
01236   }
01237   else
01238   {
01239     *(__IO uint32_t*)usartxbase &= ~itmask;
01240   }
01241 }
01242
01243 /**
01244   * @brief  Checks whether the specified USART flag is set or not.
01245   * @param  USARTx: Select the USART peripheral.
01246   *   This parameter can be one of the following values:
01247   *   USART1, USART2, USART3, UART4 or UART5.
01248   * @param  USART_FLAG: specifies the flag to check.
01249   *   This parameter can be one of the following values:
01250   *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
01251   *     @arg USART_FLAG_LBD:  LIN Break detection flag.
01252   *     @arg USART_FLAG_TXE:  Transmit data register empty flag.
01253   *     @arg USART_FLAG_TC:   Transmission Complete flag.
01254   *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
01255   *     @arg USART_FLAG_IDLE: Idle Line detection flag.
01256   *     @arg USART_FLAG_ORE:  OverRun Error flag.
01257   *     @arg USART_FLAG_NE:   Noise Error flag.
01258   *     @arg USART_FLAG_FE:   Framing Error flag.
01259   *     @arg USART_FLAG_PE:   Parity Error flag.
01260   * @retval The new state of USART_FLAG (SET or RESET).
01261   */
01262 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
01263 {
01264   FlagStatus bitstatus = RESET;
01265   /* Check the parameters */
01266   assert_param(IS_USART_ALL_PERIPH(USARTx));
01267   assert_param(IS_USART_FLAG(USART_FLAG));
01268
01269   /* The CTS flag is not available for UART4 and UART5 */
01270   if (USART_FLAG == USART_FLAG_CTS)
01271   {
01272     assert_param(IS_USART_123_PERIPH(USARTx));
01273   }
01274
01275   if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
01276   {
01277     bitstatus = SET;
01278   }
01279   else
01280   {
01281     bitstatus = RESET;
01282   }
01283   return bitstatus;
01284 }
01285
01286 /**
01287   * @brief  Clears the USARTx's pending flags.
01288   * @param  USARTx: Select the USART peripheral.
01289   *   This parameter can be one of the following values:
01290   *   USART1, USART2, USART3, UART4 or UART5.
01291   * @param  USART_FLAG: specifies the flag to clear.
01292   *   This parameter can be any combination of the following values:
01293   *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
01294   *     @arg USART_FLAG_LBD:  LIN Break detection flag.
01295   *     @arg USART_FLAG_TC:   Transmission Complete flag.
01296   *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
01297   *
01298   *
01299   * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
01300   *     error) and IDLE (Idle line detected) flags are cleared by software
01301   *     sequence: a read operation to USART_SR register (USART_GetFlagStatus())
01302   *     followed by a read operation to USART_DR register (USART_ReceiveData()).
01303   * @note RXNE flag can be also cleared by a read to the USART_DR register
01304   *     (USART_ReceiveData()).
01305   * @note TC flag can be also cleared by software sequence: a read operation to
01306   *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
01307   *     to USART_DR register (USART_SendData()).
01308   * @note TXE flag is cleared only by a write to the USART_DR register
01309   *     (USART_SendData()).
01310   * @retval None
01311   */
01312 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
01313 {
01314   /* Check the parameters */
01315   assert_param(IS_USART_ALL_PERIPH(USARTx));
01316   assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
01317
01318   /* The CTS flag is not available for UART4 and UART5 */
01319   if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
01320   {
01321     assert_param(IS_USART_123_PERIPH(USARTx));
01322   }
01323
01324   USARTx->SR = (uint16_t)~USART_FLAG;
01325 }
01326
01327 /**
01328   * @brief  Checks whether the specified USART interrupt has occurred or not.
01329   * @param  USARTx: Select the USART peripheral.
01330   *   This parameter can be one of the following values:
01331   *   USART1, USART2, USART3, UART4 or UART5.
01332   * @param  USART_IT: specifies the USART interrupt source to check.
01333   *   This parameter can be one of the following values:
01334   *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
01335   *     @arg USART_IT_LBD:  LIN Break detection interrupt
01336   *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
01337   *     @arg USART_IT_TC:   Transmission complete interrupt
01338   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
01339   *     @arg USART_IT_IDLE: Idle line detection interrupt
01340   *     @arg USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.
01341   *     @arg USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set.
01342   *     @arg USART_IT_NE:   Noise Error interrupt
01343   *     @arg USART_IT_FE:   Framing Error interrupt
01344   *     @arg USART_IT_PE:   Parity Error interrupt
01345   * @retval The new state of USART_IT (SET or RESET).
01346   */
01347 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
01348 {
01349   uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
01350   ITStatus bitstatus = RESET;
01351   /* Check the parameters */
01352   assert_param(IS_USART_ALL_PERIPH(USARTx));
01353   assert_param(IS_USART_GET_IT(USART_IT));
01354
01355   /* The CTS interrupt is not available for UART4 and UART5 */
01356   if (USART_IT == USART_IT_CTS)
01357   {
01358     assert_param(IS_USART_123_PERIPH(USARTx));
01359   }
01360
01361   /* Get the USART register index */
01362   usartreg = (((uint8_t)USART_IT) >> 0x05);
01363   /* Get the interrupt position */
01364   itmask = USART_IT & IT_MASK;
01365   itmask = (uint32_t)0x01 << itmask;
01366
01367   if (usartreg == 0x01) /* The IT  is in CR1 register */
01368   {
01369     itmask &= USARTx->CR1;
01370   }
01371   else if (usartreg == 0x02) /* The IT  is in CR2 register */
01372   {
01373     itmask &= USARTx->CR2;
01374   }
01375   else /* The IT  is in CR3 register */
01376   {
01377     itmask &= USARTx->CR3;
01378   }
01379
01380   bitpos = USART_IT >> 0x08;
01381   bitpos = (uint32_t)0x01 << bitpos;
01382   bitpos &= USARTx->SR;
01383   if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
01384   {
01385     bitstatus = SET;
01386   }
01387   else
01388   {
01389     bitstatus = RESET;
01390   }
01391
01392   return bitstatus;
01393 }
01394
01395 /**
01396   * @brief  Clears the USARTx's interrupt pending bits.
01397   * @param  USARTx: Select the USART peripheral.
01398   *   This parameter can be one of the following values:
01399   *   USART1, USART2, USART3, UART4 or UART5.
01400   * @param  USART_IT: specifies the interrupt pending bit to clear.
01401   *   This parameter can be one of the following values:
01402   *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
01403   *     @arg USART_IT_LBD:  LIN Break detection interrupt
01404   *     @arg USART_IT_TC:   Transmission complete interrupt.
01405   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
01406   *
01407
01408   * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
01409   *     error) and IDLE (Idle line detected) pending bits are cleared by
01410   *     software sequence: a read operation to USART_SR register
01411   *     (USART_GetITStatus()) followed by a read operation to USART_DR register
01412   *     (USART_ReceiveData()).
01413   * @note RXNE pending bit can be also cleared by a read to the USART_DR register
01414   *     (USART_ReceiveData()).
01415   * @note TC pending bit can be also cleared by software sequence: a read
01416   *     operation to USART_SR register (USART_GetITStatus()) followed by a write
01417   *     operation to USART_DR register (USART_SendData()).
01418   * @note TXE pending bit is cleared only by a write to the USART_DR register
01419   *     (USART_SendData()).
01420   * @retval None
01421   */
01422 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
01423 {
01424   uint16_t bitpos = 0x00, itmask = 0x00;
01425   /* Check the parameters */
01426   assert_param(IS_USART_ALL_PERIPH(USARTx));
01427   assert_param(IS_USART_CLEAR_IT(USART_IT));
01428
01429   /* The CTS interrupt is not available for UART4 and UART5 */
01430   if (USART_IT == USART_IT_CTS)
01431   {
01432     assert_param(IS_USART_123_PERIPH(USARTx));
01433   }
01434
01435   bitpos = USART_IT >> 0x08;
01436   itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
01437   USARTx->SR = (uint16_t)~itmask;
01438 }
01439
01440 /**
01441   * @}
01442   */
01443
01444 /**
01445   * @}
01446   */
01447
01448 /**
01449   * @}
01450   */
01451
01452 /**
01453   * @}
01454   */
01455
01456 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_usart.h Source File

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stm32l1xx_usart.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the USART
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_USART_H
00028 #define __STM32L1xx_USART_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup USART
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046
00047 /**
00048   * @brief  USART Init Structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
00054                                            The baud rate is computed using the following formula:
00055                                             - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
00056                                             - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
00057                                            Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
00058
00059   uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
00060                                            This parameter can be a value of @ref USART_Word_Length */
00061
00062   uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
00063                                            This parameter can be a value of @ref USART_Stop_Bits */
00064
00065   uint16_t USART_Parity;              /*!< Specifies the parity mode.
00066                                            This parameter can be a value of @ref USART_Parity
00067                                            @note When parity is enabled, the computed parity is inserted
00068                                                  at the MSB position of the transmitted data (9th bit when
00069                                                  the word length is set to 9 data bits; 8th bit when the
00070                                                  word length is set to 8 data bits). */
00071
00072   uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
00073                                            This parameter can be a value of @ref USART_Mode */
00074
00075   uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
00076                                            or disabled.
00077                                            This parameter can be a value of @ref USART_Hardware_Flow_Control */
00078 } USART_InitTypeDef;
00079
00080 /**
00081   * @brief  USART Clock Init Structure definition
00082   */
00083
00084 typedef struct
00085 {
00086
00087   uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
00088                                This parameter can be a value of @ref USART_Clock */
00089
00090   uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
00091                                This parameter can be a value of @ref USART_Clock_Polarity */
00092
00093   uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
00094                                This parameter can be a value of @ref USART_Clock_Phase */
00095
00096   uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
00097                                data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00098                                This parameter can be a value of @ref USART_Last_Bit */
00099 } USART_ClockInitTypeDef;
00100
00101 /* Exported constants --------------------------------------------------------*/
00102
00103 /** @defgroup USART_Exported_Constants
00104   * @{
00105   */
00106
00107 #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
00108                                      ((PERIPH) == USART2) || \
00109                                      ((PERIPH) == USART3) || \
00110                                      ((PERIPH) == UART4) || \
00111                                      ((PERIPH) == UART5))
00112
00113 #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
00114                                      ((PERIPH) == USART2) || \
00115                                      ((PERIPH) == USART3))
00116
00117 /** @defgroup USART_Word_Length
00118   * @{
00119   */
00120
00121 #define USART_WordLength_8b                  ((uint16_t)0x0000)
00122 #define USART_WordLength_9b                  ((uint16_t)0x1000)
00123
00124 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
00125                                       ((LENGTH) == USART_WordLength_9b))
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup USART_Stop_Bits
00131   * @{
00132   */
00133
00134 #define USART_StopBits_1                     ((uint16_t)0x0000)
00135 #define USART_StopBits_0_5                   ((uint16_t)0x1000)
00136 #define USART_StopBits_2                     ((uint16_t)0x2000)
00137 #define USART_StopBits_1_5                   ((uint16_t)0x3000)
00138 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
00139                                      ((STOPBITS) == USART_StopBits_0_5) || \
00140                                      ((STOPBITS) == USART_StopBits_2) || \
00141                                      ((STOPBITS) == USART_StopBits_1_5))
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup USART_Parity
00147   * @{
00148   */
00149
00150 #define USART_Parity_No                      ((uint16_t)0x0000)
00151 #define USART_Parity_Even                    ((uint16_t)0x0400)
00152 #define USART_Parity_Odd                     ((uint16_t)0x0600)
00153 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
00154                                  ((PARITY) == USART_Parity_Even) || \
00155                                  ((PARITY) == USART_Parity_Odd))
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup USART_Mode
00161   * @{
00162   */
00163
00164 #define USART_Mode_Rx                        ((uint16_t)0x0004)
00165 #define USART_Mode_Tx                        ((uint16_t)0x0008)
00166 #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup USART_Hardware_Flow_Control
00172   * @{
00173   */
00174 #define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
00175 #define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
00176 #define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
00177 #define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
00178 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
00179                               (((CONTROL) == USART_HardwareFlowControl_None) || \
00180                                ((CONTROL) == USART_HardwareFlowControl_RTS) || \
00181                                ((CONTROL) == USART_HardwareFlowControl_CTS) || \
00182                                ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup USART_Clock
00188   * @{
00189   */
00190 #define USART_Clock_Disable                  ((uint16_t)0x0000)
00191 #define USART_Clock_Enable                   ((uint16_t)0x0800)
00192 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
00193                                ((CLOCK) == USART_Clock_Enable))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup USART_Clock_Polarity
00199   * @{
00200   */
00201
00202 #define USART_CPOL_Low                       ((uint16_t)0x0000)
00203 #define USART_CPOL_High                      ((uint16_t)0x0400)
00204 #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup USART_Clock_Phase
00211   * @{
00212   */
00213
00214 #define USART_CPHA_1Edge                     ((uint16_t)0x0000)
00215 #define USART_CPHA_2Edge                     ((uint16_t)0x0200)
00216 #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
00217
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup USART_Last_Bit
00223   * @{
00224   */
00225
00226 #define USART_LastBit_Disable                ((uint16_t)0x0000)
00227 #define USART_LastBit_Enable                 ((uint16_t)0x0100)
00228 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
00229                                    ((LASTBIT) == USART_LastBit_Enable))
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup USART_Interrupt_definition
00235   * @{
00236   */
00237
00238 #define USART_IT_PE                          ((uint16_t)0x0028)
00239 #define USART_IT_TXE                         ((uint16_t)0x0727)
00240 #define USART_IT_TC                          ((uint16_t)0x0626)
00241 #define USART_IT_RXNE                        ((uint16_t)0x0525)
00242 #define USART_IT_IDLE                        ((uint16_t)0x0424)
00243 #define USART_IT_LBD                         ((uint16_t)0x0846)
00244 #define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
00245 #define USART_IT_CTS                         ((uint16_t)0x096A)
00246 #define USART_IT_ERR                         ((uint16_t)0x0060)
00247 #define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
00248 #define USART_IT_NE                          ((uint16_t)0x0260)
00249 #define USART_IT_FE                          ((uint16_t)0x0160)
00250
00251 /** @defgroup USART_Legacy
00252   * @{
00253   */
00254 #define USART_IT_ORE                          USART_IT_ORE_ER
00255 /**
00256   * @}
00257   */
00258
00259 #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
00260                                 ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00261                                 ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
00262                                 ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
00263 #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
00264                              ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00265                              ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
00266                              ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
00267                              ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
00268                              ((IT) == USART_IT_FE))
00269 #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00270                                ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup USART_DMA_Requests
00276   * @{
00277   */
00278
00279 #define USART_DMAReq_Tx                      ((uint16_t)0x0080)
00280 #define USART_DMAReq_Rx                      ((uint16_t)0x0040)
00281 #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
00282
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup USART_WakeUp_methods
00288   * @{
00289   */
00290
00291 #define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
00292 #define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
00293 #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
00294                                  ((WAKEUP) == USART_WakeUp_AddressMark))
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup USART_LIN_Break_Detection_Length
00300   * @{
00301   */
00302
00303 #define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
00304 #define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
00305 #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
00306                                (((LENGTH) == USART_LINBreakDetectLength_10b) || \
00307                                 ((LENGTH) == USART_LINBreakDetectLength_11b))
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup USART_IrDA_Low_Power
00313   * @{
00314   */
00315
00316 #define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
00317 #define USART_IrDAMode_Normal                ((uint16_t)0x0000)
00318 #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
00319                                   ((MODE) == USART_IrDAMode_Normal))
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup USART_Flags
00325   * @{
00326   */
00327
00328 #define USART_FLAG_CTS                       ((uint16_t)0x0200)
00329 #define USART_FLAG_LBD                       ((uint16_t)0x0100)
00330 #define USART_FLAG_TXE                       ((uint16_t)0x0080)
00331 #define USART_FLAG_TC                        ((uint16_t)0x0040)
00332 #define USART_FLAG_RXNE                      ((uint16_t)0x0020)
00333 #define USART_FLAG_IDLE                      ((uint16_t)0x0010)
00334 #define USART_FLAG_ORE                       ((uint16_t)0x0008)
00335 #define USART_FLAG_NE                        ((uint16_t)0x0004)
00336 #define USART_FLAG_FE                        ((uint16_t)0x0002)
00337 #define USART_FLAG_PE                        ((uint16_t)0x0001)
00338 #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
00339                              ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
00340                              ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
00341                              ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
00342                              ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
00343
00344 #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
00345
00346 #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
00347 #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
00348 #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
00349
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /* Exported macro ------------------------------------------------------------*/
00359 /* Exported functions ------------------------------------------------------- */
00360
00361 /*  Function used to set the USART configuration to the default reset state ***/
00362 void USART_DeInit(USART_TypeDef* USARTx);
00363
00364 /* Initialization and Configuration functions *********************************/
00365 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
00366 void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
00367 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
00368 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
00369 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
00370 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
00371 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
00372 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00373
00374 /* Data transfers functions ***************************************************/
00375 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
00376 uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
00377
00378 /* Multi-Processor Communication functions ************************************/
00379 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
00380 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
00381 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00382
00383 /* LIN mode functions *********************************************************/
00384 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
00385 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00386 void USART_SendBreak(USART_TypeDef* USARTx);
00387
00388 /* Half-duplex mode function **************************************************/
00389 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00390
00391 /* Smartcard mode functions ***************************************************/
00392 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00393 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00394 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
00395
00396 /* IrDA mode functions ********************************************************/
00397 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
00398 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
00399
00400 /* DMA transfers management functions *****************************************/
00401 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
00402
00403 /* Interrupts and flags management functions **********************************/
00404 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
00405 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
00406 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
00407 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
00408 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
00409
00410 #ifdef __cplusplus
00411 }
00412 #endif
00413
00414 #endif /* __STM32L1xx_USART_H */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_wwdg.c Source File

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stm32l1xx_wwdg.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Window watchdog (WWDG) peripheral:
00009   *           + Prescaler, Refresh window and Counter configuration
00010   *           + WWDG activation
00011   *           + Interrupts and flags management
00012   *
00013   *  @verbatim
00014   *
00015   ==============================================================================
00016                            ##### WWDG features #####
00017   ==============================================================================
00018     [..] Once enabled the WWDG generates a system reset on expiry of a programmed
00019         time period, unless the program refreshes the counter (downcounter)
00020         before to reach 0x3F value (i.e. a reset is generated when the counter
00021         value rolls over from 0x40 to 0x3F).
00022     [..] An MCU reset is also generated if the counter value is refreshed
00023          before the counter has reached the refresh window value. This
00024          implies that the counter must be refreshed in a limited window.
00025
00026     [..] Once enabled the WWDG cannot be disabled except by a system reset.
00027
00028     [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
00029          reset occurs.
00030
00031     [..] The WWDG counter input clock is derived from the APB clock divided
00032          by a programmable prescaler.
00033
00034     [..] WWDG counter clock = PCLK1 / Prescaler.
00035     [..] WWDG timeout = (WWDG counter clock) * (counter value).
00036
00037     [..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.
00038
00039                        ##### How to use this driver #####
00040   ==============================================================================
00041     [..]
00042         (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
00043             function.
00044
00045         (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
00046
00047         (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
00048
00049         (#) Set the WWDG counter value and start it using WWDG_Enable() function.
00050             When the WWDG is enabled the counter value should be configured to
00051             a value greater than 0x40 to prevent generating an immediate reset.
00052
00053         (#) Optionally you can enable the Early wakeup interrupt which is
00054             generated when the counter reach 0x40.
00055             Once enabled this interrupt cannot be disabled except by a system reset.
00056
00057         (#) Then the application program must refresh the WWDG counter at regular
00058             intervals during normal operation to prevent an MCU reset, using
00059             WWDG_SetCounter() function. This operation must occur only when
00060             the counter value is lower than the refresh window value,
00061             programmed using WWDG_SetWindowValue().
00062
00063   *  @endverbatim
00064   *
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00069   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00070   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00071   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00072   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00073   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00074   *
00075   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00076   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00077   *
00078   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32l1xx_wwdg.h"
00084 #include "stm32l1xx_rcc.h"
00085
00086 /** @addtogroup STM32L1xx_StdPeriph_Driver
00087   * @{
00088   */
00089
00090 /** @defgroup WWDG
00091   * @brief WWDG driver modules
00092   * @{
00093   */
00094
00095 /* Private typedef -----------------------------------------------------------*/
00096 /* Private define ------------------------------------------------------------*/
00097
00098 /* ----------- WWDG registers bit address in the alias region ----------- */
00099 #define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
00100
00101 /* Alias word address of EWI bit */
00102 #define CFR_OFFSET        (WWDG_OFFSET + 0x04)
00103 #define EWI_BitNumber     0x09
00104 #define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
00105
00106 /* --------------------- WWDG registers bit mask ------------------------ */
00107
00108 /* CFR register bit mask */
00109 #define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
00110 #define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
00111 #define BIT_MASK          ((uint8_t)0x7F)
00112
00113 /* Private macro -------------------------------------------------------------*/
00114 /* Private variables ---------------------------------------------------------*/
00115 /* Private function prototypes -----------------------------------------------*/
00116 /* Private functions ---------------------------------------------------------*/
00117
00118 /** @defgroup WWDG_Private_Functions
00119   * @{
00120   */
00121
00122 /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
00123  *  @brief   Prescaler, Refresh window and Counter configuration functions
00124  *
00125 @verbatim
00126   ==============================================================================
00127     ##### Prescaler, Refresh window and Counter configuration functions #####
00128   ==============================================================================
00129
00130 @endverbatim
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
00136   * @param  None
00137   * @retval None
00138   */
00139 void WWDG_DeInit(void)
00140 {
00141   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
00142   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
00143 }
00144
00145 /**
00146   * @brief  Sets the WWDG Prescaler.
00147   * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
00148   *   This parameter can be one of the following values:
00149   *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
00150   *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
00151   *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
00152   *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
00153   * @retval None
00154   */
00155 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
00156 {
00157   uint32_t tmpreg = 0;
00158   /* Check the parameters */
00159   assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
00160   /* Clear WDGTB[1:0] bits */
00161   tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
00162   /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
00163   tmpreg |= WWDG_Prescaler;
00164   /* Store the new value */
00165   WWDG->CFR = tmpreg;
00166 }
00167
00168 /**
00169   * @brief  Sets the WWDG window value.
00170   * @param  WindowValue: specifies the window value to be compared to the downcounter.
00171   *   This parameter value must be lower than 0x80.
00172   * @retval None
00173   */
00174 void WWDG_SetWindowValue(uint8_t WindowValue)
00175 {
00176   __IO uint32_t tmpreg = 0;
00177
00178   /* Check the parameters */
00179   assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
00180   /* Clear W[6:0] bits */
00181
00182   tmpreg = WWDG->CFR & CFR_W_MASK;
00183
00184   /* Set W[6:0] bits according to WindowValue value */
00185   tmpreg |= WindowValue & (uint32_t) BIT_MASK;
00186
00187   /* Store the new value */
00188   WWDG->CFR = tmpreg;
00189 }
00190
00191 /**
00192   * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
00193   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00194   * @param  None
00195   * @retval None
00196   */
00197 void WWDG_EnableIT(void)
00198 {
00199   *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
00200 }
00201
00202 /**
00203   * @brief  Sets the WWDG counter value.
00204   * @param  Counter: specifies the watchdog counter value.
00205   *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
00206   *   an immediate reset).
00207   * @retval None
00208   */
00209 void WWDG_SetCounter(uint8_t Counter)
00210 {
00211   /* Check the parameters */
00212   assert_param(IS_WWDG_COUNTER(Counter));
00213   /* Write to T[6:0] bits to configure the counter value, no need to do
00214      a read-modify-write; writing a 0 to WDGA bit does nothing */
00215   WWDG->CR = Counter & BIT_MASK;
00216 }
00217
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup WWDG_Group2 WWDG activation functions
00223  *  @brief   WWDG activation functions
00224  *
00225 @verbatim
00226   ==============================================================================
00227                      ##### WWDG activation function #####
00228   ==============================================================================
00229
00230 @endverbatim
00231   * @{
00232   */
00233
00234 /**
00235   * @brief  Enables WWDG and load the counter value.
00236   * @param  Counter: specifies the watchdog counter value.
00237   *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
00238   *   an immediate reset).
00239   * @retval None
00240   */
00241 void WWDG_Enable(uint8_t Counter)
00242 {
00243   /* Check the parameters */
00244   assert_param(IS_WWDG_COUNTER(Counter));
00245   WWDG->CR = WWDG_CR_WDGA | Counter;
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup WWDG_Group3 Interrupts and flags management functions
00253  *  @brief   Interrupts and flags management functions
00254  *
00255 @verbatim
00256   ==============================================================================
00257                 ##### Interrupts and flags management functions #####
00258   ==============================================================================
00259
00260 @endverbatim
00261   * @{
00262   */
00263
00264 /**
00265   * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
00266   * @param  None
00267   * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
00268   */
00269 FlagStatus WWDG_GetFlagStatus(void)
00270 {
00271   FlagStatus bitstatus = RESET;
00272
00273   if ((WWDG->SR) != (uint32_t)RESET)
00274   {
00275     bitstatus = SET;
00276   }
00277   else
00278   {
00279     bitstatus = RESET;
00280   }
00281   return bitstatus;
00282 }
00283
00284 /**
00285   * @brief  Clears Early Wakeup interrupt flag.
00286   * @param  None
00287   * @retval None
00288   */
00289 void WWDG_ClearFlag(void)
00290 {
00291   WWDG->SR = (uint32_t)RESET;
00292 }
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: stm32l1xx_wwdg.h Source File

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  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • STM32L1xx_StdPeriph_Driver
  • inc

stm32l1xx_wwdg.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l1xx_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   This file contains all the functions prototypes for the WWDG
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00020   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Define to prevent recursive inclusion -------------------------------------*/
00027 #ifndef __STM32L1xx_WWDG_H
00028 #define __STM32L1xx_WWDG_H
00029
00030 #ifdef __cplusplus
00031  extern "C" {
00032 #endif
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32l1xx.h"
00036
00037 /** @addtogroup STM32L1xx_StdPeriph_Driver
00038   * @{
00039   */
00040
00041 /** @addtogroup WWDG
00042   * @{
00043   */
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup WWDG_Exported_Constants
00049   * @{
00050   */
00051
00052 /** @defgroup WWDG_Prescaler
00053   * @{
00054   */
00055
00056 #define WWDG_Prescaler_1    ((uint32_t)0x00000000)
00057 #define WWDG_Prescaler_2    ((uint32_t)0x00000080)
00058 #define WWDG_Prescaler_4    ((uint32_t)0x00000100)
00059 #define WWDG_Prescaler_8    ((uint32_t)0x00000180)
00060 #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
00061                                       ((PRESCALER) == WWDG_Prescaler_2) || \
00062                                       ((PRESCALER) == WWDG_Prescaler_4) || \
00063                                       ((PRESCALER) == WWDG_Prescaler_8))
00064 #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
00065 #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
00066
00067 /**
00068   * @}
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Exported macro ------------------------------------------------------------*/
00076 /* Exported functions ------------------------------------------------------- */
00077 /*  Function used to set the WWDG configuration to the default reset state ****/
00078 void WWDG_DeInit(void);
00079
00080 /* Prescaler, Refresh window and Counter configuration functions **************/
00081 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
00082 void WWDG_SetWindowValue(uint8_t WindowValue);
00083 void WWDG_EnableIT(void);
00084 void WWDG_SetCounter(uint8_t Counter);
00085
00086 /* WWDG activation functions **************************************************/
00087 void WWDG_Enable(uint8_t Counter);
00088
00089 /* Interrupts and flags management functions **********************************/
00090 FlagStatus WWDG_GetFlagStatus(void);
00091 void WWDG_ClearFlag(void);
00092
00093 #ifdef __cplusplus
00094 }
00095 #endif
00096
00097 #endif /* __STM32L1xx_WWDG_H */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: system_stm32l1xx.c Source File

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system_stm32l1xx.c

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00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32l1xx.c
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *          This file contains the system clock configuration for STM32L1xx Ultra
00009   *          Low Power devices, and is generated by the clock configuration
00010   *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
00011   *
00012   * 1.  This file provides two functions and one global variable to be called from
00013   *     user application:
00014   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00015   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
00016   *                      depending on the configuration made in the clock xls tool.
00017   *                      This function is called at startup just after reset and
00018   *                      before branch to main program. This call is made inside
00019   *                      the "startup_stm32l1xx_xx.s" file.
00020   *
00021   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00022   *                                  by the user application to setup the SysTick
00023   *                                  timer or configure other parameters.
00024   *
00025   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00026   *                                 be called whenever the core clock is changed
00027   *                                 during program execution.
00028   *
00029   * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
00030   *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
00031   *    configure the system clock before to branch to main program.
00032   *
00033   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00034   *    function will do nothing and MSI still used as system clock source. User can
00035   *    add some code to deal with this issue inside the SetSysClock() function.
00036   *
00037   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
00038   *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
00039   *    through PLL, and you are using different crystal you have to adapt the HSE
00040   *    value to your own configuration.
00041   *
00042   * 5. This file configures the system clock as follows:
00043   *=============================================================================
00044   *                         System Clock Configuration
00045   *=============================================================================
00046   *        System Clock source          | PLL(HSE)
00047   *-----------------------------------------------------------------------------
00048   *        SYSCLK                       | 32000000 Hz
00049   *-----------------------------------------------------------------------------
00050   *        HCLK                         | 32000000 Hz
00051   *-----------------------------------------------------------------------------
00052   *        AHB Prescaler                | 1
00053   *-----------------------------------------------------------------------------
00054   *        APB1 Prescaler               | 1
00055   *-----------------------------------------------------------------------------
00056   *        APB2 Prescaler               | 1
00057   *-----------------------------------------------------------------------------
00058   *        HSE Frequency                | 8000000 Hz
00059   *-----------------------------------------------------------------------------
00060   *        PLL DIV                      | 3
00061   *-----------------------------------------------------------------------------
00062   *        PLL MUL                      | 12
00063   *-----------------------------------------------------------------------------
00064   *        VDD                          | 3.3 V
00065   *-----------------------------------------------------------------------------
00066   *        Vcore                        | 1.8 V (Range 1)
00067   *-----------------------------------------------------------------------------
00068   *        Flash Latency                | 1 WS
00069   *-----------------------------------------------------------------------------
00070   *        SDIO clock (SDIOCLK)         | 48000000 Hz
00071   *-----------------------------------------------------------------------------
00072   *        Require 48MHz for USB clock  | Disabled
00073   *-----------------------------------------------------------------------------
00074   *=============================================================================
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00079   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00080   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00081   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00082   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00083   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00084   *
00085   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00086   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00087   *
00088   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00089   ******************************************************************************
00090   */
00091
00092 /** @addtogroup CMSIS
00093   * @{
00094   */
00095
00096 /** @addtogroup stm32l1xx_system
00097   * @{
00098   */
00099
00100 /** @addtogroup STM32L1xx_System_Private_Includes
00101   * @{
00102   */
00103
00104 #include "stm32l1xx.h"
00105
00106 /**
00107   * @}
00108   */
00109
00110 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
00111   * @{
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /** @addtogroup STM32L1xx_System_Private_Defines
00119   * @{
00120   */
00121
00122 /*!< Uncomment the following line if you need to use external SRAM mounted
00123      on STM32L152D_EVAL board as data memory  */
00124 /* #define DATA_IN_ExtSRAM */
00125
00126 /*!< Uncomment the following line if you need to relocate your vector Table in
00127      Internal SRAM. */
00128 /* #define VECT_TAB_SRAM */
00129 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00130                                   This value must be a multiple of 0x200. */
00131 /**
00132   * @}
00133   */
00134
00135 /** @addtogroup STM32L1xx_System_Private_Macros
00136   * @{
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @addtogroup STM32L1xx_System_Private_Variables
00144   * @{
00145   */
00146 uint32_t SystemCoreClock    = 32000000;
00147 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
00148 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
00155   * @{
00156   */
00157
00158 static void SetSysClock(void);
00159 #ifdef DATA_IN_ExtSRAM
00160   static void SystemInit_ExtMemCtl(void);
00161 #endif /* DATA_IN_ExtSRAM */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /** @addtogroup STM32L1xx_System_Private_Functions
00168   * @{
00169   */
00170
00171 /**
00172   * @brief  Setup the microcontroller system.
00173   *         Initialize the Embedded Flash Interface, the PLL and update the
00174   *         SystemCoreClock variable.
00175   * @param  None
00176   * @retval None
00177   */
00178 void SystemInit (void)
00179 {
00180   /*!< Set MSION bit */
00181   RCC->CR |= (uint32_t)0x00000100;
00182
00183   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
00184   RCC->CFGR &= (uint32_t)0x88FFC00C;
00185
00186   /*!< Reset HSION, HSEON, CSSON and PLLON bits */
00187   RCC->CR &= (uint32_t)0xEEFEFFFE;
00188
00189   /*!< Reset HSEBYP bit */
00190   RCC->CR &= (uint32_t)0xFFFBFFFF;
00191
00192   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
00193   RCC->CFGR &= (uint32_t)0xFF02FFFF;
00194
00195   /*!< Disable all interrupts */
00196   RCC->CIR = 0x00000000;
00197
00198 #ifdef DATA_IN_ExtSRAM
00199   SystemInit_ExtMemCtl();
00200 #endif /* DATA_IN_ExtSRAM */
00201
00202   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
00203   SetSysClock();
00204
00205 #ifdef VECT_TAB_SRAM
00206   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00207 #else
00208   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00209 #endif
00210 }
00211
00212 /**
00213   * @brief  Update SystemCoreClock according to Clock Register Values
00214   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00215   *         be used by the user application to setup the SysTick timer or configure
00216   *         other parameters.
00217   *
00218   * @note   Each time the core clock (HCLK) changes, this function must be called
00219   *         to update SystemCoreClock variable value. Otherwise, any configuration
00220   *         based on this variable will be incorrect.
00221   *
00222   * @note   - The system frequency computed by this function is not the real
00223   *           frequency in the chip. It is calculated based on the predefined
00224   *           constant and the selected clock source:
00225   *
00226   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
00227   *             value as defined by the MSI range.
00228   *
00229   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00230   *
00231   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00232   *
00233   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00234   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
00235   *
00236   *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
00237   *             16 MHz) but the real value may vary depending on the variations
00238   *             in voltage and temperature.
00239   *
00240   *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
00241   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
00242   *              frequency of the crystal used. Otherwise, this function may
00243   *              have wrong result.
00244   *
00245   *         - The result of this function could be not correct when using fractional
00246   *           value for HSE crystal.
00247   * @param  None
00248   * @retval None
00249   */
00250 void SystemCoreClockUpdate (void)
00251 {
00252   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
00253
00254   /* Get SYSCLK source -------------------------------------------------------*/
00255   tmp = RCC->CFGR & RCC_CFGR_SWS;
00256
00257   switch (tmp)
00258   {
00259     case 0x00:  /* MSI used as system clock */
00260       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
00261       SystemCoreClock = (32768 * (1 << (msirange + 1)));
00262       break;
00263     case 0x04:  /* HSI used as system clock */
00264       SystemCoreClock = HSI_VALUE;
00265       break;
00266     case 0x08:  /* HSE used as system clock */
00267       SystemCoreClock = HSE_VALUE;
00268       break;
00269     case 0x0C:  /* PLL used as system clock */
00270       /* Get PLL clock source and multiplication factor ----------------------*/
00271       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
00272       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
00273       pllmul = PLLMulTable[(pllmul >> 18)];
00274       plldiv = (plldiv >> 22) + 1;
00275
00276       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00277
00278       if (pllsource == 0x00)
00279       {
00280         /* HSI oscillator clock selected as PLL clock entry */
00281         SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
00282       }
00283       else
00284       {
00285         /* HSE selected as PLL clock entry */
00286         SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
00287       }
00288       break;
00289     default: /* MSI used as system clock */
00290       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
00291       SystemCoreClock = (32768 * (1 << (msirange + 1)));
00292       break;
00293   }
00294   /* Compute HCLK clock frequency --------------------------------------------*/
00295   /* Get HCLK prescaler */
00296   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00297   /* HCLK clock frequency */
00298   SystemCoreClock >>= tmp;
00299 }
00300
00301 /**
00302   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
00303   *         settings.
00304   * @note   This function should be called only once the RCC clock configuration
00305   *         is reset to the default reset state (done in SystemInit() function).
00306   * @param  None
00307   * @retval None
00308   */
00309 static void SetSysClock(void)
00310 {
00311   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00312
00313   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00314   /* Enable HSE */
00315   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00316
00317   /* Wait till HSE is ready and if Time out is reached exit */
00318   do
00319   {
00320     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00321     StartUpCounter++;
00322   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00323
00324   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00325   {
00326     HSEStatus = (uint32_t)0x01;
00327   }
00328   else
00329   {
00330     HSEStatus = (uint32_t)0x00;
00331   }
00332
00333   if (HSEStatus == (uint32_t)0x01)
00334   {
00335     /* Enable 64-bit access */
00336     FLASH->ACR |= FLASH_ACR_ACC64;
00337
00338     /* Enable Prefetch Buffer */
00339     FLASH->ACR |= FLASH_ACR_PRFTEN;
00340
00341     /* Flash 1 wait state */
00342     FLASH->ACR |= FLASH_ACR_LATENCY;
00343
00344     /* Power enable */
00345     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
00346
00347     /* Select the Voltage Range 1 (1.8 V) */
00348     PWR->CR = PWR_CR_VOS_0;
00349
00350     /* Wait Until the Voltage Regulator is ready */
00351     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
00352     {
00353     }
00354
00355     /* HCLK = SYSCLK /1*/
00356     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00357
00358     /* PCLK2 = HCLK /1*/
00359     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00360
00361     /* PCLK1 = HCLK /1*/
00362     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00363
00364     /*  PLL configuration */
00365     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
00366                                         RCC_CFGR_PLLDIV));
00367     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
00368
00369     /* Enable PLL */
00370     RCC->CR |= RCC_CR_PLLON;
00371
00372     /* Wait till PLL is ready */
00373     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00374     {
00375     }
00376
00377     /* Select PLL as system clock source */
00378     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00379     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00380
00381     /* Wait till PLL is used as system clock source */
00382     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
00383     {
00384     }
00385   }
00386   else
00387   {
00388     /* If HSE fails to start-up, the application will have wrong clock
00389        configuration. User can add here some code to deal with this error */
00390   }
00391 }
00392
00393 #ifdef DATA_IN_ExtSRAM
00394 /**
00395   * @brief  Setup the external memory controller.
00396   *         Called in SystemInit() function before jump to main.
00397   *         This function configures the external SRAM mounted on STM32L152D_EVAL board
00398   *         This SRAM will be used as program data memory (including heap and stack).
00399   * @param  None
00400   * @retval None
00401   */
00402 void SystemInit_ExtMemCtl(void)
00403 {
00404 /*-- GPIOs Configuration -----------------------------------------------------*/
00405 /*
00406  +-------------------+--------------------+------------------+------------------+
00407  +                       SRAM pins assignment                                   +
00408  +-------------------+--------------------+------------------+------------------+
00409  | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
00410  | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
00411  | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
00412  | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
00413  | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
00414  | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
00415  | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
00416  | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
00417  | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 |
00418  | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 |
00419  | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
00420  | PD15 <-> FSMC_D1  |--------------------+
00421  +-------------------+
00422 */
00423
00424   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
00425   RCC->AHBENR   = 0x000080D8;
00426
00427   /* Connect PDx pins to FSMC Alternate function */
00428   GPIOD->AFR[0]  = 0x00CC00CC;
00429   GPIOD->AFR[1]  = 0xCCCCCCCC;
00430   /* Configure PDx pins in Alternate function mode */
00431   GPIOD->MODER   = 0xAAAA0A0A;
00432   /* Configure PDx pins speed to 40 MHz */
00433   GPIOD->OSPEEDR = 0xFFFF0F0F;
00434   /* Configure PDx pins Output type to push-pull */
00435   GPIOD->OTYPER  = 0x00000000;
00436   /* No pull-up, pull-down for PDx pins */
00437   GPIOD->PUPDR   = 0x00000000;
00438
00439   /* Connect PEx pins to FSMC Alternate function */
00440   GPIOE->AFR[0]  = 0xC00000CC;
00441   GPIOE->AFR[1]  = 0xCCCCCCCC;
00442   /* Configure PEx pins in Alternate function mode */
00443   GPIOE->MODER   = 0xAAAA800A;
00444   /* Configure PEx pins speed to 40 MHz */
00445   GPIOE->OSPEEDR = 0xFFFFC00F;
00446   /* Configure PEx pins Output type to push-pull */
00447   GPIOE->OTYPER  = 0x00000000;
00448   /* No pull-up, pull-down for PEx pins */
00449   GPIOE->PUPDR   = 0x00000000;
00450
00451   /* Connect PFx pins to FSMC Alternate function */
00452   GPIOF->AFR[0]  = 0x00CCCCCC;
00453   GPIOF->AFR[1]  = 0xCCCC0000;
00454   /* Configure PFx pins in Alternate function mode */
00455   GPIOF->MODER   = 0xAA000AAA;
00456   /* Configure PFx pins speed to 40 MHz */
00457   GPIOF->OSPEEDR = 0xFF000FFF;
00458   /* Configure PFx pins Output type to push-pull */
00459   GPIOF->OTYPER  = 0x00000000;
00460   /* No pull-up, pull-down for PFx pins */
00461   GPIOF->PUPDR   = 0x00000000;
00462
00463   /* Connect PGx pins to FSMC Alternate function */
00464   GPIOG->AFR[0]  = 0x00CCCCCC;
00465   GPIOG->AFR[1]  = 0x00000C00;
00466   /* Configure PGx pins in Alternate function mode */
00467   GPIOG->MODER   = 0x00200AAA;
00468   /* Configure PGx pins speed to 40 MHz */
00469   GPIOG->OSPEEDR = 0x00300FFF;
00470   /* Configure PGx pins Output type to push-pull */
00471   GPIOG->OTYPER  = 0x00000000;
00472   /* No pull-up, pull-down for PGx pins */
00473   GPIOG->PUPDR   = 0x00000000;
00474
00475 /*-- FSMC Configuration ------------------------------------------------------*/
00476   /* Enable the FSMC interface clock */
00477   RCC->AHBENR    = 0x400080D8;
00478
00479   /* Configure and enable Bank1_SRAM3 */
00480   FSMC_Bank1->BTCR[4]  = 0x00001011;
00481   FSMC_Bank1->BTCR[5]  = 0x00000300;
00482   FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
00483 /*
00484   Bank1_SRAM3 is configured as follow:
00485
00486   p.FSMC_AddressSetupTime = 0;
00487   p.FSMC_AddressHoldTime = 0;
00488   p.FSMC_DataSetupTime = 3;
00489   p.FSMC_BusTurnAroundDuration = 0;
00490   p.FSMC_CLKDivision = 0;
00491   p.FSMC_DataLatency = 0;
00492   p.FSMC_AccessMode = FSMC_AccessMode_A;
00493
00494   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
00495   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00496   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
00497   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00498   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00499   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00500   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00501   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00502   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00503   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00504   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00505   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00506   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00507   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00508   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00509
00510   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00511
00512   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
00513 */
00514
00515 }
00516 #endif /* DATA_IN_ExtSRAM */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


STM32L1xx Standard Peripherals Firmware Library: system_stm32l1xx.h Source File

  • File List
  • Globals
  • STM32L1xx_StdPeriph_Lib_V1.1.0
  • Libraries
  • CMSIS
  • Device
  • ST
  • STM32L1xx
  • Include

system_stm32l1xx.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32l1xx.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    24-January-2012
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
00019   * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
00020   *
00021   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
00022   ******************************************************************************
00023   */
00024
00025 /** @addtogroup CMSIS
00026   * @{
00027   */
00028
00029 /** @addtogroup stm32l1xx_system
00030   * @{
00031   */
00032
00033 /**
00034   * @brief Define to prevent recursive inclusion
00035   */
00036 #ifndef __SYSTEM_STM32L1XX_H
00037 #define __SYSTEM_STM32L1XX_H
00038
00039 #ifdef __cplusplus
00040  extern "C" {
00041 #endif
00042
00043 /** @addtogroup STM32L1xx_System_Includes
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @addtogroup STM32L1xx_System_Exported_types
00053   * @{
00054   */
00055
00056 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
00057
00058 /**
00059   * @}
00060   */
00061
00062 /** @addtogroup STM32L1xx_System_Exported_Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /** @addtogroup STM32L1xx_System_Exported_Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /** @addtogroup STM32L1xx_System_Exported_Functions
00079   * @{
00080   */
00081
00082 extern void SystemInit(void);
00083 extern void SystemCoreClockUpdate(void);
00084 /**
00085   * @}
00086   */
00087
00088 #ifdef __cplusplus
00089 }
00090 #endif
00091
00092 #endif /*__SYSTEM_STM32L1XX_H */
00093
00094 /**
00095   * @}
00096   */
00097
00098 /**
00099   * @}
00100   */
00101 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/


Release Notes for STM32L1xx CMSIS

Copyright © 2012 STMicroelectronics

Contents

  1. STM32L1xx CMSIS update history
  2. License

STM32L1xx CMSIS update history

V1.1.0 / 24-January-2012

Main Changes

  • Alpha version for STM32L1xx High-density and Medium-density Plus devices.
  • Add support for STM32L1xx High-density and Medium-density Plus devices:
    • Add new product define: "#define STM32L1XX_MDP"
    • Add new product define: "#define STM32L1XX_HD"
    • Change the library version to V1.1.0
    • Add new IRQ to support STM32L1XX_HD and STM32L1XX_MDP vector table
    • Add new and update someTypedef to support new peripherals (AES, SDIO, OPAMP, FSMC, I2S)
    • Add new peripherals address mapping
    • Update bits definition
  • Add new startup file "startup_stm32l1xx_mdp.s" for all toolchains
  • Add new startup file "startup_stm32l1xx_hd.s" for all toolchains
  • Change the RTC "CAL" register name to "CALR"
  • Update registers bits definitions.

V1.0.0 / 31-December-2010

Main Changes

  • Created

    License

    The use of this STM32 Firmware is governed by the terms and conditions of the License Agreement available in the root of this package.

    For complete documentation on STMicroelectronics Microcontrollers visit www.st.com


CMSIS Version History

This document describes the changes between the different CMSIS versions.

Version: 2.10 - July 2011

Information in this file, the accompany manuals, and software is
Copyright © ARM Ltd.
All rights reserved.

Contents

  1. Used Toolchains
  2. Changes to version V2.00
  3. Changes to version V1.30
  4. Changes to version V1.20
  5. Open Points
  6. Limitations

Used Toolchains

Following toolchains have been used for test / verification:.

  • ARM: MDK-ARM Version 4.21
  • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10

Changes to version V2.00

Added CMSIS DSP Software Library support for Cortex-M0 based MCUs

The CMSIS DSP Software Library provides now also libraries and examples for Cortex-M0.

For more information refer to CMSIS DSP Library documentation.

Added big endian support for DSP library

The CMSIS DSP Software Library provides now also pre-build libraries and projects for big endian devices.

For more information refer to CMSIS DSP Library documentation.

Simplified folder structure for CMSIS include files

All CMSIS core include files as well as the DSP-Library header files are located in a single folder ./CMSIS/Include.

Changed folder structure for Device Support packages

Device Support packages are expected to be in folder ./Device located at the same level as ./CMSIS.

The new Device folder contains the following subfolders:

  • Device
    • <Vendor>
      • <Device> | <Device Series>
        • Include
          <device>.h
          system_<device>.h
        • Source
          • Templates
            system_<device>.c
            • <Toolchain>
              startup_<device>.s
            • <Toolchain>
            • ...
      • <Device> | <Device Series>
      • ...
    • <Vendor>
    • ...

Template files are application specific files and are required to be copied to the project prior to use!

Removed CMSIS core source files

The CMSIS core source files core_cm0.c, core_cm3.c, core_cm4.c containing helper functions for older ARM compiler versions got removed.

For the ARM Compiler Toolchain version V4.0.677 or later is required!

Changes to version V1.30

Added CMSIS DSP Software Library

The CMSIS DSP Software Library is a suite of common signal processing functions targeted to Cortex-M processor based microcontrollers. Even though the code has been specifically optimized towards using the extended DSP instruction set of the Cortex-M4 processor, the library can be compiled for any Cortex-M processor.

For more information see CMSIS DSP Library documentation.

Added CMSIS System View Description

The CMSIS System View Description answers the challenges of accurate, detailed and timely device aware peripheral debugging support for Cortex Microcontroller based devices by the software development tools vendor community.

Silicon vendors shall create and maintain a formalized description of the debug view for all the peripherals contained in their Cortex Microcontroller based devices. Tool vendors use such descriptions to establish device specific debug support in their debugging tools.

A standardized System View Description shall provide a common approach to capturing peripheral debug related information in a machine readable files.

For more information see CMSIS System View Description.

Added Cortex-M4 Core Support

Additional folder CM4, containing the Cortex-M4 core support files, has been added.

  • CM0
  • CM3
  • CM4
    • CoreSupport
    • DeviceSupport

New naming for Core Support Files

The new Core Support Files are:

  • core_cm#.h (# = 0, 3, 4)
  • core_cmFunc.h (Cortex-M Core Register access functions)
  • core_cmInstr.h (Cortex-M Core instructions)
  • core_cm4_simd.h (Cortex-M4 SIMD instructions)

Changes to version V1.20

Removed CMSIS Middelware packages

CMSIS Middleware is removed and no longer focus of CMSIS.

SystemFrequency renamed to SystemCoreClock

The variable name SystemCoreClock is more precise than SystemFrequency because the variable holds the clock value at which the core is running.

Changed startup concept

The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit from main) has the weakness that it does not work for controllers which need a already configuerd clock system to configure the external memory controller.

Changed startup concept
  • SystemInit() is called from startup file before premain.
  • SystemInit() configures the clock system and also configures an existing external memory controller.
  • SystemInit() must not use global variables.
  • SystemCoreClock is initialized with a correct predefined value.
  • Additional function void SystemCoreClockUpdate (void) is provided.
    SystemCoreClockUpdate() updates the variable SystemCoreClock and must be called whenever the core clock is changed.
    SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.

Advanced Debug Functions

ITM communication channel is only capable for OUT direction. To allow also communication for IN direction a simple concept is provided.

  • Global variable volatile int ITM_RxBuffer used for IN data.
  • Function int ITM_CheckChar (void) checks if a new character is available.
  • Function int ITM_ReceiveChar (void) retrieves the new character.

For detailed explanation see file CMSIS debug support.htm.

Core Register Bit Definitions

Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the defines correspond with the Cortex-M Technical Reference Manual.

e.g. SysTick structure with bit definitions

/** \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct
{
  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

DoxyGen Tags

DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation using DoxyGen.

Folder Structure

The folder structure is changed to differentiate the single support packages.

  • CM0
  • CM3
    • CoreSupport
    • DeviceSupport
      • Vendor
        • Device
          • Startup
            • Toolchain
            • Toolchain
            • ...
        • Device
        • ...
      • Vendor
      • ...
    • Example (optional)
      • Toolchain
        • Device
        • Device
        • ...
      • Toolchain
      • ...
  • Documentation

Open Points

Following points need to be clarified and solved:

  • Equivalent C and Assembler startup files.

    Is there a need for having C startup files although assembler startup files are very efficient and do not need to be changed?

  • Placing of HEAP in external RAM.

    It must be possible to place HEAP in external RAM if the device supports an external memory controller.

  • Placing of STACK /HEAP.

    STACK should always be placed at the end of internal RAM.

    If HEAP is placed in internal RAM than it should be placed after RW ZI section.

Limitations

The following limitations are not covered with the current CMSIS version:

  • No C startup files are available.


Release Notes for STM32L1xx Standard Peripherals Library Drivers

Release Notes for STM32L1xx Standard Peripherals Library Drivers (StdPeriph_Driver)

Copyright © 2012 STMicroelectronics

Contents

  1. STM32L1xx Standard Peripherals Library Drivers update history
  2. License

STM32L1xx Standard Peripherals Library Drivers update history

V1.1.0 / 24-January-2012

Main Changes

  • Official version for STM32L1xx High-density and Medium-density Plus devices.
  • Add new drivers for new peripherals on STM32L1xx High-density and Medium-density Plus devices:
    • stm32l1xx_aes.h/.c
    • stm32l1xx_fsmc.h/.c
    • stm32l1xx_opamp.h/.c
    • stm32l1xx_sdio.h/.c
  • stm32l1xx_adc.h/.c
    • Add new channel for ADC Bank B
    • Add new function to select between Bank A and Bank B: void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_BankSelection);
    • Update ADC_InjectedChannelConfig() and ADC_RegularChannelConfig() to support new ADC channels.
  • stm32l1xx_comp.h/.c
    • Add new function: void COMP_SW1SwitchConfig(FunctionalState NewState);
  • stm32l1xx_dbgmcu.h/.c
    • Add new parmater for TIM5
  • stm32l1xx_dma.h/.c
    • Add DMA2 support
  • stm32l1xx_exti.h/.c
    • Add new EXTI Line 23 connected to TS channel acquisition event
  • stm32l1xx_flash.h/.c
    • Add new pages definitions for Write protection
    • Add new flag FLASH_FLAG_OPTVERRUSR
    • Add
new functions: FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(),
FLASH_OB_BootConfig(), FLASH_OB_GetWRP1(), FLASH_OB_GetWRP2(),
FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().
    • Update
functions to avoid STM32L1XX_MD workaround on Data EEPROM (FAST)
halfword/byte erase: DATA_EEPROM_FastProgramByte(),
DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte() and
DATA_EEPROM_ProgramHalfWord().
  • stm32l1xx_flash_ramfunc.c
    • Add new functions: FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().
    • Update FLASH_ProgramHalfPage(), FLASH_ProgramParallelHalfPage(), DATA_EEPROM_EraseDoubleWord() and DATA_EEPROM_ProgramDoubleWord() functions.
  • stm32l1xx_gpio.h/.c
    • Add new GPIO port definition.
    • Add new alternate functions for new peripherals.
  • stm32l1xx_i2c.h/.c
    • Add new function: void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
  • stm32l1xx_rcc.h/.c
    • Add new interrupt for RCC_IT_LSECSS
    • Add new definitions for new peripherals
    • Add new function: RCC_LSEClockSecuritySystemCmd()
  • stm32l1xx_rtc.h/.c
    • SYNCH_PREDIV max value changed to 0x7FFF
    • Add new definitions for RTC Alarm Sub Second "RTC_Alarm_Sub_Seconds_Masks" and Alarm Sub Second max value (0x7FFF)
    • Add new definitions for: RTC_Calib_Output_selection, RTC_Smooth_calib_period, RTC_Smooth_calib_Plus_pulses, RTC_Smooth_calib_Minus_pulses.
    • Add new definitions: RTC_TamperTrigger_LowLevel and RTC_TamperTrigger_HighLevel.
    • Add new definitions for RTC_Tamper_Filter, RTC_Tamper_Sampling_Frequencies, RTC_Tamper_Pin_Precharge_Duration, RTC_Tamper_2 and RTC_Tamper_3.
    • Add new RTC_Add_1_Second_Parameter and RTC_Substract_Fraction_Of_Second_Value defintions.
    • Add new Backup registers definitions from RTC_BKP_DR20 to RTC_BKP_DR31.
    • Add new flags: RTC_FLAG_RECALPF, RTC_FLAG_TAMP3F and RTC_FLAG_TAMP2F
    • Add new interrupts definitions RTC_IT_TAMP2 and RTC_IT_TAMP3
    • Add new functions: RTC_BypassShadowCmd(),
RTC_GetSubSecond(), RTC_AlarmSubSecondConfig(),
RTC_GetAlarmSubSecond(), RTC_CalibOutputConfig(),
RTC_SmoothCalibConfig(), RTC_GetTimeStampSubSecond(),
RTC_TamperFilterConfig(), RTC_TamperSamplingFreqConfig(),
RTC_TamperPinsPrechargeDuration(), RTC_TimeStampOnTamperDetectionCmd(),
RTC_TamperPullUpCmd(), RTC_SynchroShiftConfig().
  • stm32l1xx_spi.h/.c
    • Add support for I2S
    • Add new structure "I2S_InitTypeDef"
    • Add new parameter: I2S_Mode, I2S_Standard, I2S_Data_Format, I2S_MCLK_Output, I2S_Audio_Frequency and I2S_Clock_Polarity.
    • Add 2 interrupts: I2S_IT_UDR and SPI_I2S_IT_FRE
    • Add new flags: I2S_FLAG_CHSIDE, I2S_FLAG_UDR and SPI_I2S_FLAG_FRE
    • Add new functions: I2S_Init(), I2S_StructInit() and I2S_Cmd()
  • stm32l1xx_syscfg.h/.c
    • Add support for new port: EXTI_PortSourceGPIOF and EXTI_PortSourceGPIOG
    • Add new remap for FSMC: SYSCFG_MemoryRemap_FSMC
    • Add new RI Channels and new RI IOSwitch
    • Add new functions: SYSCFG_GetBootMode() and SYSCFG_RIChannelSpeedConfig()
  • stm32l1xx_tim.h/.c
    • Update to support TIM 32-bit
    • Change TIM_Period and TIM_Pulse to be declared as 32-bit
    • Remove the "TIM_DMABase_RCR": the RCR register is not present on STM32L1xx family.
    • Add new parameter: TIM_DMABase_OR
    • Change "TIM_DMABurstLength_1Byte" to "TIM_DMABurstLength_1Transfer"
    • Add new TIM_Remap: TIM2_TIM10_OC, TIM2_TIM5_TRGO, TIM3_TIM11_OC, TIM3_TIM5_TRGO, TIM10_ETR_LSE, TIM10_ETR_TIM9_TRGO, TIM11_ETR_LSE and TIM11_ETR_TIM9_TRGO.
    • Update TIM_RemapConfig() function coding.
    • Update all functions header comments to support TIM5.
  • stm32l1xx_usart.h/.c
    • Update to support UART4 and UART5
    • Update all functions header comment

V1.0.0 / 31-December-2010

Main Changes

  • Created

    License

    The use of this STM32 Firmware is governed by the terms and conditions of the License Agreement available in the root of this package.

    For complete documentation on STMicroelectronics Microcontrollers visit www.st.com