787 lines
20 KiB
C
787 lines
20 KiB
C
/**
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******************************************************************************
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* @file stm32l1xx_clock_config.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 24-January-2012
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* @brief This file provides firmware functions to configure the STM32L1xx
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* system clock frequency to MSI, HSI, HSE, 4 MHz, 8 MHz, 16 MHz and
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* 32 MHz.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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* LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_clock_config.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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ErrorStatus HSEStartUpStatus;
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/**
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* @brief Selects MSI (Default Value, 2MHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_2MHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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}
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/**
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* @brief Selects MSI (64KHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_64KHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 64KHz */
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RCC_MSIRangeConfig(RCC_MSIRange_0);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects MSI (128KHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_128KHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 128KHz */
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RCC_MSIRangeConfig(RCC_MSIRange_1);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects MSI (256KHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_256KHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 256KHz */
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RCC_MSIRangeConfig(RCC_MSIRange_2);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects MSI (512KHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_512KHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 512KHz */
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RCC_MSIRangeConfig(RCC_MSIRange_3);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects MSI (1MHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_1MHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 1MHz */
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RCC_MSIRangeConfig(RCC_MSIRange_4);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects MSI (4MHz) as System clock source and configure
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* HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToMSI_4MHz(void)
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{
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/* RCC system reset */
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RCC_DeInit();
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/* Enable 64-bit access */
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FLASH_ReadAccess64Cmd(ENABLE);
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/* Enable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(ENABLE);
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/* Flash 1 wait state */
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FLASH_SetLatency(FLASH_Latency_1);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 3 (1.2V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range3);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Set MSI clock range to 4MHz */
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RCC_MSIRangeConfig(RCC_MSIRange_6);
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/* Select MSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_MSI);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x00)
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{}
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}
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/**
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* @brief Selects HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToHSI(void)
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{
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__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
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/* RCC system reset(for debug purpose) */
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RCC_DeInit();
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/* Enable HSI */
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RCC_HSICmd(ENABLE);
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/* Wait till HSI is ready and if Time out is reached exit */
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do
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{
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HSIStatus = RCC_GetFlagStatus(RCC_FLAG_HSIRDY);
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StartUpCounter++;
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}
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while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
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if (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) != RESET)
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{
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HSIStatus = (uint32_t)0x01;
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}
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else
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{
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HSIStatus = (uint32_t)0x00;
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}
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if (HSIStatus == 0x01)
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{
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 1 (1.8V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Select HSI as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
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/* Wait till HSI is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x04)
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{}
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}
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else
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{ /* If HSI fails to start-up, the application will have wrong clock configuration.
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User can add here some code to deal with this error */
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/* Go to infinite loop */
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while (1)
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{}
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}
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}
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/**
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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void SetHCLKToHSE(void)
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{
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
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/* RCC system reset(for debug purpose) */
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RCC_DeInit();
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/* Enable HSE */
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RCC_HSEConfig(RCC_HSE_ON);
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/* Wait till HSE is ready */
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HSEStartUpStatus = RCC_WaitForHSEStartUp();
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if (HSEStartUpStatus == SUCCESS)
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{
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/* Flash 0 wait state */
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FLASH_SetLatency(FLASH_Latency_0);
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/* Disable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(DISABLE);
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/* Disable 64-bit access */
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FLASH_ReadAccess64Cmd(DISABLE);
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/* Enable the PWR APB1 Clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Select the Voltage Range 2 (1.5V) */
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PWR_VoltageScalingConfig(PWR_VoltageScaling_Range2);
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/* Wait Until the Voltage Regulator is ready */
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while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
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{}
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK */
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RCC_PCLK1Config(RCC_HCLK_Div1);
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/* Select HSE as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
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/* Wait till HSE is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x08)
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{}
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}
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else
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{ /* If HSE fails to start-up, the application will have wrong clock configuration.
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User can add here some code to deal with this error */
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/* Go to infinite loop */
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while (1)
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{}
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}
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}
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|
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/**
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
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* @param None
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* @retval None
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*/
|
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void SetHCLKTo4(void)
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{
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
|
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/* RCC system reset(for debug purpose) */
|
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RCC_DeInit();
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/* Enable HSE */
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RCC_HSEConfig(RCC_HSE_ON);
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/* Wait till HSE is ready */
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HSEStartUpStatus = RCC_WaitForHSEStartUp();
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if (HSEStartUpStatus == SUCCESS)
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{
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/* Flash 0 wait state */
|
|
FLASH_SetLatency(FLASH_Latency_0);
|
|
|
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/* Disable Prefetch Buffer */
|
|
FLASH_PrefetchBufferCmd(DISABLE);
|
|
|
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/* Disable 64-bit access */
|
|
FLASH_ReadAccess64Cmd(DISABLE);
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|
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/* Enable the PWR APB1 Clock */
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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|
|
/* Select the Voltage Range 2 (1.5V) */
|
|
PWR_VoltageScalingConfig(PWR_VoltageScaling_Range2);
|
|
|
|
/* Wait Until the Voltage Regulator is ready */
|
|
while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
|
|
{}
|
|
|
|
/* HCLK = SYSCLK/2 */
|
|
RCC_HCLKConfig(RCC_SYSCLK_Div2);
|
|
|
|
/* PCLK2 = HCLK */
|
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
|
|
|
/* PCLK1 = HCLK */
|
|
RCC_PCLK1Config(RCC_HCLK_Div1);
|
|
|
|
/* Select HSE as system clock source */
|
|
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
|
|
|
|
/* Wait till HSE is used as system clock source */
|
|
while (RCC_GetSYSCLKSource() != 0x08)
|
|
{}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock configuration.
|
|
User can add here some code to deal with this error */
|
|
|
|
/* Go to infinite loop */
|
|
while (1)
|
|
{}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SetHCLKTo8(void)
|
|
{
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
|
|
/* RCC system reset(for debug purpose) */
|
|
RCC_DeInit();
|
|
|
|
/* Enable HSE */
|
|
RCC_HSEConfig(RCC_HSE_ON);
|
|
|
|
/* Wait till HSE is ready */
|
|
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
|
|
|
if (HSEStartUpStatus == SUCCESS)
|
|
{
|
|
/* Flash 0 wait state */
|
|
FLASH_SetLatency(FLASH_Latency_0);
|
|
|
|
/* Disable Prefetch Buffer */
|
|
FLASH_PrefetchBufferCmd(DISABLE);
|
|
|
|
/* Disable 64-bit access */
|
|
FLASH_ReadAccess64Cmd(DISABLE);
|
|
|
|
/* Enable the PWR APB1 Clock */
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
|
|
|
|
/* Select the Voltage Range 2 (1.5V) */
|
|
PWR_VoltageScalingConfig(PWR_VoltageScaling_Range2);
|
|
|
|
/* Wait Until the Voltage Regulator is ready */
|
|
while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
|
|
{}
|
|
|
|
/* HCLK = SYSCLK */
|
|
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
|
|
|
/* PCLK2 = HCLK */
|
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
|
|
|
/* PCLK1 = HCLK */
|
|
RCC_PCLK1Config(RCC_HCLK_Div1);
|
|
|
|
/* Select HSE as system clock source */
|
|
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
|
|
|
|
/* Wait till HSE is used as system clock source */
|
|
while (RCC_GetSYSCLKSource() != 0x08)
|
|
{}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock configuration.
|
|
User can add here some code to deal with this error */
|
|
|
|
/* Go to infinite loop */
|
|
while (1)
|
|
{}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Selects PLL as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SetHCLKTo16(void)
|
|
{
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
|
|
/* RCC system reset(for debug purpose) */
|
|
RCC_DeInit();
|
|
|
|
/* Enable HSE */
|
|
RCC_HSEConfig(RCC_HSE_ON);
|
|
|
|
/* Wait till HSE is ready */
|
|
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
|
|
|
if (HSEStartUpStatus == SUCCESS)
|
|
{
|
|
/* Enable 64-bit access */
|
|
FLASH_ReadAccess64Cmd(ENABLE);
|
|
|
|
/* Enable Prefetch Buffer */
|
|
FLASH_PrefetchBufferCmd(ENABLE);
|
|
|
|
/* Flash 1 wait state */
|
|
FLASH_SetLatency(FLASH_Latency_1);
|
|
|
|
/* Enable the PWR APB1 Clock */
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
|
|
|
|
/* Select the Voltage Range 2 (1.5V) */
|
|
PWR_VoltageScalingConfig(PWR_VoltageScaling_Range2);
|
|
|
|
/* Wait Until the Voltage Regulator is ready */
|
|
while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
|
|
{}
|
|
|
|
/* HCLK = SYSCLK/2 */
|
|
RCC_HCLKConfig(RCC_SYSCLK_Div2);
|
|
|
|
/* PCLK2 = HCLK */
|
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
|
|
|
/* PCLK1 = HCLK */
|
|
RCC_PCLK1Config(RCC_HCLK_Div1);
|
|
|
|
/* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
|
|
RCC_PLLConfig(RCC_PLLSource_HSE, RCC_PLLMul_12, RCC_PLLDiv_3);
|
|
|
|
/* Enable PLL */
|
|
RCC_PLLCmd(ENABLE);
|
|
|
|
/* Wait till PLL is ready */
|
|
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
|
|
{}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while (RCC_GetSYSCLKSource() != 0x0C)
|
|
{}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock configuration.
|
|
User can add here some code to deal with this error */
|
|
|
|
/* Go to infinite loop */
|
|
while (1)
|
|
{}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Selects PLL as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SetHCLKTo32(void)
|
|
{
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
|
|
/* RCC system reset(for debug purpose) */
|
|
RCC_DeInit();
|
|
|
|
/* Enable HSE */
|
|
RCC_HSEConfig(RCC_HSE_ON);
|
|
|
|
/* Wait till HSE is ready */
|
|
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
|
|
|
if (HSEStartUpStatus == SUCCESS)
|
|
{
|
|
/* Enable 64-bit access */
|
|
FLASH_ReadAccess64Cmd(ENABLE);
|
|
|
|
/* Enable Prefetch Buffer */
|
|
FLASH_PrefetchBufferCmd(ENABLE);
|
|
|
|
/* Flash 1 wait state */
|
|
FLASH_SetLatency(FLASH_Latency_1);
|
|
|
|
/* Enable the PWR APB1 Clock */
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
|
|
|
|
/* Select the Voltage Range 1 (1.8V) */
|
|
PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1);
|
|
|
|
/* Wait Until the Voltage Regulator is ready */
|
|
while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET)
|
|
{}
|
|
|
|
/* HCLK = SYSCLK */
|
|
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
|
|
|
/* PCLK2 = HCLK */
|
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
|
|
|
/* PCLK1 = HCLK */
|
|
RCC_PCLK1Config(RCC_HCLK_Div1);
|
|
|
|
/* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
|
|
RCC_PLLConfig(RCC_PLLSource_HSE, RCC_PLLMul_12, RCC_PLLDiv_3);
|
|
|
|
/* Enable PLL */
|
|
RCC_PLLCmd(ENABLE);
|
|
|
|
/* Wait till PLL is ready */
|
|
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
|
|
{}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while (RCC_GetSYSCLKSource() != 0x0C)
|
|
{}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock configuration.
|
|
User can add here some code to deal with this error */
|
|
|
|
/* Go to infinite loop */
|
|
while (1)
|
|
{}
|
|
}
|
|
}
|
|
|
|
/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
|