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Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c Normal file
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Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c Normal file
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/**
******************************************************************************
* @file stm32h7xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
inside the stm32h7xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
* @{
*/
/**
* @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @param PreemptPriority The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Enables the MPU
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != 0UL)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @param PriorityGroup the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval status - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval status - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configures the SysTick clock source.
* @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
#if defined(DUAL_CORE)
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
*/
uint32_t HAL_GetCurrentCPUID(void)
{
if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
{
return CM7_CPUID;
}
else
{
return CM4_CPUID;
}
}
#else
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
*/
uint32_t HAL_GetCurrentCPUID(void)
{
return CM7_CPUID;
}
#endif /*DUAL_CORE*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32h7xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
-@- Multi (Double) buffer mode is possible with DMA and BDMA instances.
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer with interrupt
(+) Change on the fly the memory0 or memory1 address.
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
(+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
@endverbatim
* @{
*/
/**
* @brief Starts the multi_buffer DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable the Double buffer mode */
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
/* Clear all flags */
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
}
else /* BDMA instance(s) */
{
/* Enable the Double buffer mode */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
/* Clear all flags */
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Memory-to-memory transfer not supported in double buffering mode */
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable the Double buffer mode */
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
/* Clear all flags */
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
}
else /* BDMA instance(s) */
{
/* Enable the Double buffer mode */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
/* Clear all flags */
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable Common interrupts*/
MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
/*Enable Half Transfer IT if corresponding Callback is set*/
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
}
}
else /* BDMA instance(s) */
{
/* Enable Common interrupts*/
MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
/*Enable Half Transfer IT if corresponding Callback is set*/
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
}
}
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Change the memory0 or memory1 address on the fly.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param Address: The new address
* @param memory: the memory to be changed, This parameter can be one of
* the following values:
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
{
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
if(memory == MEMORY0)
{
/* change the memory0 address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
}
else
{
/* change the memory1 address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
}
}
else /* BDMA instance(s) */
{
if(memory == MEMORY0)
{
/* change the memory0 address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;
}
else
{
/* change the memory1 address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;
}
}
return HAL_OK;
}
/**
* @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
{
uint32_t syncSignalID = 0;
uint32_t syncPolarity = 0;
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
if(pSyncConfig->SyncEnable == ENABLE)
{
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
}
else
{
assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
}
syncSignalID = pSyncConfig->SyncSignalID;
syncPolarity = pSyncConfig->SyncPolarity;
}
/*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Disable the synchronization and event generation before applying a new config */
CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \
(syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \
((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process Locked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
return HAL_ERROR;
}
}
/**
* @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
* contains the request generator parameters.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
HAL_StatusTypeDef status;
HAL_DMA_StateTypeDef temp_state = hdma->State;
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
}
else
{
assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
}
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if(hdma->DMAmuxRequestGen == 0U)
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* error status */
status = HAL_ERROR;
}
else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
{
/* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity;
/* Process Locked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
{
/* Disable the request generator*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handles DMAMUX interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if(hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Configure DMA Stream data length */
((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
/* Configure DMA Stream source address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
}
}
else /* BDMA instance(s) */
{
/* Configure DMA Stream data length */
((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
/* Configure DMA Stream source address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
}
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

859
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c Normal file
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@ -0,0 +1,859 @@
/**
******************************************************************************
* @file stm32h7xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt (CORE1 or CORE2 in case of dual core line )
(++) Event (CORE1 or CORE2 in case of dual core line )
(++) a combination of the previous
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
(+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear source.
It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
Value can be one of the following:
(++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 0
(+++) On a configurable Line : the D3 domain wakeup signal is
automatically cleared after after the Delay + Rising Edge detect
(+++) On a direct Line : the D3 domain wakeup signal is
cleared after the direct event input signal is cleared
(++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b00 :
DMA ch6 event selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b01 :
DMA ch7 event selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b10 :
LPTIM4 out selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b11 :
LPTIM5 out selected as D3 domain pendclear source
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
choose gpio D3 PendClearSource using PendClearSource
member from EXTI_PendClear_Source structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
#if defined (DUAL_CORE)
/* Configure interrupt mode for Core2 : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
#endif /* DUAL_CORE */
/* Configure the D3 PendClear source in case of Wakeup target is Any */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
/*Calc the PMR register address for the given line */
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
{
/* Clear D3PMRx register for the given line */
regval &= ~maskline;
/* Store D3PMRx register value */
*regaddr = regval;
}
else
{
/* Set D3PMRx register to 1 for the given line */
regval |= maskline;
/* Store D3PMRx register value */
*regaddr = regval;
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
*regaddr = regval;
}
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
pExtiConfig->Mode = EXTI_MODE_NONE;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
#if defined (DUAL_CORE)
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
}
#endif /*DUAL_CORE*/
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00U;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
}
}
/* Get default Pend Clear Source */
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
/* 3] Get D3 Pend Clear source */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
if(((*regaddr) & linepos) != 0UL)
{
/* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Clear interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
#if defined (DUAL_CORE)
/* 1] Clear CM4 interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear CM4 event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
#endif /* DUAL_CORE */
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* 4] Clear D3 Config lines */
if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = (*regaddr & ~maskline);
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
/*Clear D3 PendClear source */
*regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4*/
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Get pending bit */
regval = (*regaddr & maskline);
if (regval != 0x00U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32h7xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#if defined(DUAL_CORE)
#define EXTI_CPU1 (0x01000000U)
#define EXTI_CPU2 (0x02000000U)
#endif /*DUAL_CORE*/
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the GPIOs
to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t temp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
temp |= (GPIO_Init->Speed << (position * 2U));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
temp = EXTI_CurrentCPU->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
{
temp |= iocurrent;
}
EXTI_CurrentCPU->EMR1 = temp;
/* Clear EXTI line configuration */
temp = EXTI_CurrentCPU->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
{
temp |= iocurrent;
}
EXTI_CurrentCPU->IMR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t tmp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position) ;
if (iocurrent != 0x00U)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->FTSR1 &= ~(iocurrent);
EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Sets or clears the selected data port bit.
*
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
}
/**
* @brief Toggles the specified GPIO pins.
* @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence*/
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
#if defined(DUAL_CORE) && defined(CORE_CM4)
if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#else
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#endif
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32h7xx_hal_hsem.c
* @author MCD Application Team
* @brief HSEM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the semaphore peripheral:
* + Semaphore Take function (2-Step Procedure) , non blocking
* + Semaphore FastTake function (1-Step Procedure) , non blocking
* + Semaphore Status check
* + Semaphore Clear Key Set and Get
* + Release and release all functions
* + Semaphore notification enabling and disabling and callnack functions
* + IRQ handler management
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255
(#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
(#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31
(++) It returns 1 if the given semaphore is taken otherwise (Free) zero
(#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255:
(++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
semaphore remains taken (locked)
(#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
This function takes as parameters :
(++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
(++) the Master ID:
(++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
Key or the MasterID doesn't match, semaphores remains taken (locked)
(#)Semaphores Release all key functions:
(++) HAL_HSEM_SetClearKey() to set semaphore release all Key
(++) HAL_HSEM_GetClearKey() to get release all Key
(#)Semaphores notification functions :
(++) HAL_HSEM_ActivateNotification to activate a notification callback on
a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
semaphores (bitfield).
(++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
(++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
Used by the notification functions
*** HSEM HAL driver macros list ***
=============================================
[..] Below the list of most used macros in HSEM HAL driver.
(+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
[..] Example of use :
[..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
[..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
(+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
(+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
(+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup HSEM HSEM
* @brief HSEM HAL module driver
* @{
*/
#ifdef HAL_HSEM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
/** @defgroup HSEM_Private_Constants HSEM Private Constants
* @{
*/
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
#ifndef HSEM_RLR_MASTERID
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
#endif
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
/**
* @}
*/
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
* @{
*/
/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
* @brief HSEM Take and Release functions
*
@verbatim
==============================================================================
##### HSEM Take and Release functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Take a semaphore with 2 Step method
(+) Fast Take a semaphore with 1 Step method
(+) Check semaphore state Taken or not
(+) Release a semaphore
(+) Release all semaphore at once
@endverbatim
* @{
*/
/**
* @brief Take a semaphore in 2 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#else
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails*/
return HAL_ERROR;
}
/**
* @brief Fast Take a semaphore with 1 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#else
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails */
return HAL_ERROR;
}
/**
* @brief Check semaphore state Taken or not.
* @param SemID: semaphore ID
* @retval HAL HSEM state
*/
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
{
return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
}
/**
* @brief Release a semaphore.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval None
*/
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
#if USE_MULTI_CORE_SHARED_CODE != 0U
HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
#else
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
#endif
}
/**
* @brief Release All semaphore used by a given Master .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @param CoreID: CoreID of the CPU that is using semaphores to be released
* @retval None
*/
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
{
assert_param(IS_HSEM_KEY(Key));
assert_param(IS_HSEM_COREID(CoreID));
HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
* @brief HSEM Set and Get Key functions.
*
@verbatim
==============================================================================
##### HSEM Set and Get Key functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set semaphore Key
(+) Get semaphore Key
@endverbatim
* @{
*/
/**
* @brief Set semaphore Key .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @retval None
*/
void HAL_HSEM_SetClearKey(uint32_t Key)
{
assert_param(IS_HSEM_KEY(Key));
MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
}
/**
* @brief Get semaphore Key .
* @retval Semaphore Key , value from 0 to 0xFFFF
*/
uint32_t HAL_HSEM_GetClearKey(void)
{
return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
* @brief HSEM Notification functions.
*
@verbatim
==============================================================================
##### HSEM IRQ handler management and Notification functions #####
==============================================================================
[..] This section provides HSEM IRQ handler and Notification function.
@endverbatim
* @{
*/
/**
* @brief Activate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER |= SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER |= SemMask;
}
#else
HSEM_COMMON->IER |= SemMask;
#endif
}
/**
* @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER &= ~SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER &= ~SemMask;
}
#else
HSEM_COMMON->IER &= ~SemMask;
#endif
}
/**
* @brief This function handles HSEM interrupt request
* @retval None
*/
void HAL_HSEM_IRQHandler(void)
{
uint32_t statusreg;
#if USE_MULTI_CORE_SHARED_CODE != 0U
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
/*Disable Interrupts*/
HSEM->C1IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C1ICR = ((uint32_t)statusreg);
}
else /* HSEM_CPU2_COREID */
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
/*Disable Interrupts*/
HSEM->C2IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C2ICR = ((uint32_t)statusreg);
}
#else
/* Get the list of masked freed semaphores*/
statusreg = HSEM_COMMON->MISR;
/*Disable Interrupts*/
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM_COMMON->ICR = ((uint32_t)statusreg);
#endif
/* Call FreeCallback */
HAL_HSEM_FreeCallback(statusreg);
}
/**
* @brief Semaphore Released Callback.
* @param SemMask: Mask of Released semaphores
* @retval None
*/
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(SemMask);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HSEM_FreeCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_HSEM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32h7xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32H7xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @note For all I2C5 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @note For all I2C5 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32h7xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization and de-initialization functions.
* + Peripheral Control functions.
* + Interrupt Handling functions.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### PWR peripheral overview #####
==============================================================================
[..]
(#) The Power control (PWR) provides an overview of the supply architecture
for the different power domains and of the supply configuration
controller.
In the H7 family, the number of power domains is different between
device lines. This difference is due to characteristics of each device.
(#) Domain architecture overview for the different H7 lines:
(+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
These devices have 3 power domains (D1, D2 and D3).
The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
peripherals. The D2 domain contains peripherals and a CPU
(Cortex-M4). The D3 domain contains the system control, I/O logic
and low-power peripherals.
(+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753
devices have 3 power domains (D1, D2 and D3).
The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
peripherals. The D2 domain contains peripherals. The D3 domains
contains the system control, I/O logic and low-power peripherals.
(+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD).
The core domain (CD) contains a CPU (Cortex-M7), a Flash
memory and peripherals. The SmartRun domain contains the system
control, I/O logic and low-power peripherals.
(#) Every entity have low power mode as described below :
(#) The CPU low power modes are :
(+) CPU CRUN.
(+) CPU CSLEEP.
(+) CPU CSTOP.
(#) The domain low power modes are :
(+) DRUN.
(+) DSTOP.
(+) DSTANDBY.
(#) The SYSTEM low power modes are :
(+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
Standby. In Run* mode, the performance is limited and the
system supply configuration shall be programmed. The system
enters Run mode only when the ACTVOSRDY bit in PWR control
status register 1 (PWR_CSR1) is set to 1.
(+) RUN.
(+) STOP.
(+) STANDBY.
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Power management peripheral is active by default at startup level in
STM32h7xx lines.
(#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
to enable/disable access to the backup domain (RTC registers, RTC backup
data registers and backup SRAM).
(#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
mode and voltage threshold) in order to set up the Power Voltage Detector,
then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start
and stop the PVD detection.
(+) PVD level could be one of the following values :
(++) 1V95
(++) 2V1
(++) 2V25
(++) 2V4
(++) 2V55
(++) 2V7
(++) 2V85
(++) External voltage level
(#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
with the right parameter to configure the wake up pin polarity (Low or
High) and to enable and disable it.
(#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
mode. Wake-up from SLEEP mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()).
Please ensure to clear all CPU pending events by calling
HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
in SLEEP mode with __WFE() entry.
(#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
mode for single core devices. For dual core devices, this API will enter
the domain (containing Cortex-Mx that executing this function) in DSTOP
mode. According to the used parameter, user could select the regulator to
be kept actif in low power mode and wake-up event type.
Please ensure to clear all CPU pending events by calling
HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
in CSTOP mode with __WFE() entry.
(#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
STANDBY mode for single core devices. For dual core devices, this API
will enter the domain (containing Cortex-Mx that executing this function)
in DSTANDBY mode.
(#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
enable and disable the Cortex-Mx re-entring in SLEEP mode after an
interruption handling is over.
(#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
to configure the Cortex-Mx to wake-up after any pending event / interrupt
even if it's disabled or has insufficient priority to cause exception
entry.
(#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
request.
*** PWR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in PWR HAL driver.
(+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
regulator output voltage.
(+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants PWR Private Constants
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#if !defined (DUAL_CORE)
#define PVD_MODE_IT (0x00010000U)
#define PVD_MODE_EVT (0x00020000U)
#endif /* !defined (DUAL_CORE) */
#define PVD_RISING_EDGE (0x00000001U)
#define PVD_FALLING_EDGE (0x00000002U)
#define PVD_RISING_FALLING_EDGE (0x00000003U)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and De-Initialization functions
*
@verbatim
===============================================================================
##### Initialization and De-Initialization Functions #####
===============================================================================
[..]
This section provides functions allowing to deinitialize power peripheral.
[..]
After system reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
domain.
The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
domain.
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset
* values.
* @note This functionality is not available in this product.
* The prototype is kept just to maintain compatibility with other
* products.
* @retval None.
*/
void HAL_PWR_DeInit (void)
{
}
/**
* @brief Enable access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None.
*/
void HAL_PWR_EnableBkUpAccess (void)
{
/* Enable access to RTC and backup registers */
SET_BIT (PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None.
*/
void HAL_PWR_DisableBkUpAccess (void)
{
/* Disable access to RTC and backup registers */
CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @brief Power Control functions
*
@verbatim
===============================================================================
##### Peripheral Control Functions #####
===============================================================================
[..]
This section provides functions allowing to control power peripheral.
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
register).
(+) A PVDO flag is available to indicate if VDD is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line 16 to generate an interrupt if enabled.
It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in STANDBY mode.
*** Wake-up pin configuration ***
=================================
[..]
(+) Wake-up pin is used to wake up the system from STANDBY mode.
The pin pull is configurable through the WKUPEPR register to be in
No-pull, Pull-up and Pull-down.
The pin polarity is configurable through the WKUPEPR register to be
active on rising or falling edges.
(+) There are up to six Wake-up pin in the STM32H7 devices family.
*** Low Power modes configuration ***
=====================================
[..]
The device present 3 principles low-power modes features:
(+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining
active (Powered and Clocked).
(+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the
regulator is running. The Main regulator or the LP
regulator could be selected.
(+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
supply regulator is powered off.
*** SLEEP mode ***
==================
[..]
(+) Entry:
The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
SLEEPEntry) function.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
-@@- The Regulator parameter is not used for the STM32H7 family
and is kept as parameter just to maintain compatibility with the
lower power families (STM32L).
(+) Exit:
Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from SLEEP mode.
*** STOP mode ***
=================
[..]
In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
register contents are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption in STOP mode, FLASH can be powered off before
entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the STOP mode using
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
STOPEntry) function with:
(++) Regulator:
(+++) PWR_MAINREGULATOR_ON: Main regulator ON.
(+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
(++) STOPEntry:
(+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
(+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
*** STANDBY mode ***
====================
[..]
(+)
The system STANDBY mode allows to achieve the lowest power consumption.
It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
disabled. The system is consequently powered off. The PLL, the HSI
oscillator and the HSE oscillator are also switched off. SRAM and register
contents are lost except for the RTC registers, RTC backup registers,
backup SRAM and standby circuitry.
[..]
The voltage regulator is OFF.
(++) Entry:
(+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
function.
(++) Exit:
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
RTC wakeup, tamper event, time stamp event, external reset in NRST
pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
RTC Wakeup event, a tamper event or a time-stamp event, without
depending on an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
(++) To wake up from the STOP mode with an RTC alarm event, it is
necessary to configure the RTC to generate the RTC alarm using the
HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
it is necessary to configure the RTC to detect the tamper or time
stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the STOP mode with an RTC WakeUp event, it is
necessary to configure the RTC to generate the RTC WakeUp event
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the event mode and the voltage threshold detected by the
* Programmable Voltage Detector(PVD).
* @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
* the configuration information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @note For dual core devices, please ensure to configure the EXTI lines for
* the different Cortex-Mx through PWR_Exported_Macro provided by this
* driver. All combination are allowed: wake up only Cortex-M7, wake up
* only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
* @retval None.
*/
void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
{
/* Check the PVD configuration parameter */
if (sConfigPVD == NULL)
{
return;
}
/* Check the parameters */
assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
/* Clear previous config */
#if !defined (DUAL_CORE)
__HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
__HAL_PWR_PVD_EXTI_DISABLE_IT ();
#endif /* !defined (DUAL_CORE) */
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
#if !defined (DUAL_CORE)
/* Interrupt mode configuration */
if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT ();
}
/* Event mode configuration */
if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
}
#endif /* !defined (DUAL_CORE) */
/* Rising edge configuration */
if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
}
/* Falling edge configuration */
if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
}
}
/**
* @brief Enable the Programmable Voltage Detector (PVD).
* @retval None.
*/
void HAL_PWR_EnablePVD (void)
{
/* Enable the power voltage detector */
SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
/**
* @brief Disable the Programmable Voltage Detector (PVD).
* @retval None.
*/
void HAL_PWR_DisablePVD (void)
{
/* Disable the power voltage detector */
CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values, which
* sets the default (rising edge):
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
* or one of the following values where the user can explicitly states
* the enabled pin and the chosen polarity:
* @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
* and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
* GPIOI port.
* @retval None.
*/
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
{
/* Check the parameters */
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
/*
Enable and Specify the Wake-Up pin polarity and the pull configuration
for the event detection (rising or falling edge).
*/
MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
* PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
* @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
* and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
* GPIOI port.
* @retval None.
*/
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
{
/* Check the parameters */
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
/* Disable the wake up pin selected */
CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
}
/**
* @brief Enter the current core in SLEEP mode (CSLEEP).
* @param Regulator : Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
* @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
* regulator ON.
* @note This parameter is not used for the STM32H7 family and is kept as
* parameter just to maintain compatibility with the lower power
* families.
* @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
* @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
* @note Ensure to clear pending events before calling this API through
* HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
* @retval None.
*/
void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param (IS_PWR_REGULATOR (Regulator));
assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Select SLEEP mode entry */
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI ();
}
else
{
/* Request Wait For Event */
__WFE ();
}
}
/**
* @brief Enter STOP mode.
* @note For single core devices, this API will enter the system in STOP mode
* with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is
* cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTOP mode. If all
* Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
* cleared, all the system will enter in STOP mode.
* @param Regulator : Specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
* @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
* regulator ON.
* @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
* @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
* @note In System STOP mode, all I/O pins keep the same state as in Run mode.
* @note When exiting System STOP mode by issuing an interrupt or a wakeup
* event, the HSI RC oscillator is selected as default system wakeup
* clock.
* @note In System STOP mode, when the voltage regulator operates in low
* power mode, an additional startup delay is incurred when the system
* is waking up. By keeping the internal regulator ON during STOP mode,
* the consumption is higher although the startup time is reduced.
* @retval None.
*/
void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param (IS_PWR_REGULATOR (Regulator));
assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
/* Select the regulator state in STOP mode */
MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
/* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
/* Check CPU ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
}
else
{
/* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
}
#else /* Single core devices */
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
#if defined (PWR_CPUCR_PDDS_D2)
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STOP mode */
__DSB ();
__ISB ();
/* Select STOP mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI ();
}
else
{
/* Request Wait For Event */
__WFE ();
}
/* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enter STANDBY mode.
* @note For single core devices, this API will enter the system in STANDBY
* mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
* register is cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTANDBY mode. If all
* Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
* is cleared, all the system will enter in STANDBY mode.
* @note The system enters Standby mode only when all domains are in DSTANDBY.
* @note When the System exit STANDBY mode by issuing an interrupt or a
* wakeup event, the HSI RC oscillator is selected as system clock.
* @note It is recommended to disable all regulators before entring STANDBY
* mode for power consumption saving purpose.
* @retval None.
*/
void HAL_PWR_EnterSTANDBYMode (void)
{
/* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
/* Check CPU ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
}
else
{
/* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
}
#else /* Single core devices */
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
#if defined (PWR_CPUCR_PDDS_D2)
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STOP mode */
__DSB ();
__ISB ();
/* This option is used to ensure that store operations are completed */
#if defined (__CC_ARM)
__force_stores();
#endif /* defined (__CC_ARM) */
/* Request Wait For Interrupt */
__WFI ();
}
/**
* @brief Indicate Sleep-On-Exit feature when returning from Handler mode to
* Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run
* only on interruptions handling.
* @retval None.
*/
void HAL_PWR_EnableSleepOnExit (void)
{
/* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to
* Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit (void)
{
/* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Enable CORTEX SEVONPEND feature.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, any
* pending event / interrupt even if it's disabled or has insufficient
* priority to cause exception entry wakes up the Cortex-Mx.
* @retval None.
*/
void HAL_PWR_EnableSEVOnPend (void)
{
/* Set SEVONPEND bit of Cortex-Mx System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Disable CORTEX SEVONPEND feature.
* @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
* enabled pending causes exception entry wakes up the Cortex-Mx.
* @retval None.
*/
void HAL_PWR_DisableSEVOnPend (void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
* @brief Interrupt Handling functions
*
@verbatim
===============================================================================
##### Interrupt Handling Functions #####
===============================================================================
[..]
This section provides functions allowing to handle the PVD pending
interrupts.
@endverbatim
* @{
*/
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_AVD_IRQHandler().
* @retval None.
*/
void HAL_PWR_PVD_IRQHandler (void)
{
#if defined (DUAL_CORE)
/* Check Cortex-Mx ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Check PWR EXTI D1 flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
{
/* Clear PWR EXTI D1 pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
}
else
{
/* Check PWR EXTI D2 flag */
if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
{
/* Clear PWR EXTI D2 pending bit */
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
}
#else /* Single core devices */
/* PVD EXTI line interrupt detected */
if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
{
/* Clear PWR EXTI pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
#endif /* defined (DUAL_CORE) */
}
/**
* @brief PWR PVD interrupt callback.
* @retval None.
*/
__weak void HAL_PWR_PVDCallback (void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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