diff --git a/SIF LIGHT/主板/1.25T-6P.PcbLib b/SIF LIGHT/主板/1.25T-6P.PcbLib new file mode 100644 index 0000000..e562a11 Binary files /dev/null and b/SIF LIGHT/主板/1.25T-6P.PcbLib differ diff --git a/SIF LIGHT/主板/1.25t-3p.PcbLib b/SIF LIGHT/主板/1.25t-3p.PcbLib new file mode 100644 index 0000000..ebe4ac3 Binary files /dev/null and b/SIF LIGHT/主板/1.25t-3p.PcbLib differ diff --git a/SIF LIGHT/主板/PCB_Project2.PrjPCB b/SIF LIGHT/主板/PCB_Project2.PrjPCB new file mode 100644 index 0000000..12e5f01 --- /dev/null +++ b/SIF LIGHT/主板/PCB_Project2.PrjPCB @@ -0,0 +1,1124 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=ds18b20.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=VFTAMGSC + +[Document2] +DocumentPath=1.25t-3p.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=WKJAWSLO + +[Document3] +DocumentPath=1.25T-6P.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=CTLILCNS + +[Document4] +DocumentPath=Դģ.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=ENQMCYPH + +[Document5] +DocumentPath=SIF Light_SCH 20220112_2022-07-06.schdoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=WUVEDJMT + +[Document6] +DocumentPath=PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=IAOXJSFD + +[GeneratedDocument1] +DocumentPath=Project Outputs for PCB_Project2\Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.html +DItemRevisionGUID= + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + diff --git a/SIF LIGHT/主板/PCB_Project2.PrjPCBStructure b/SIF LIGHT/主板/PCB_Project2.PrjPCBStructure new file mode 100644 index 0000000..9bb471a --- /dev/null +++ b/SIF LIGHT/主板/PCB_Project2.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=SIF Light_SCH 20220112_2022-07-06.schdoc diff --git a/SIF LIGHT/主板/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc b/SIF LIGHT/主板/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc new file mode 100644 index 0000000..7c2887a Binary files /dev/null and b/SIF LIGHT/主板/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc differ diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-32-55.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-32-55.LOG new file mode 100644 index 0000000..24d817e --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-32-55.LOG @@ -0,0 +1,201 @@ +Change Component DesignItemId : Designator=C2 Old DesignItemId= New DesignItemId=0.1uF +Change Component DesignItemId : Designator=C1 Old DesignItemId= New DesignItemId=1uF +Change Component DesignItemId : Designator=U1 Old DesignItemId= New DesignItemId=2·ֱģ +Change Component DesignItemId : Designator=R1 Old DesignItemId= New DesignItemId=4.7K +Change Component DesignItemId : Designator=R2 Old DesignItemId= New DesignItemId=4.7K +Change Component DesignItemId : Designator=R3 Old DesignItemId= New DesignItemId=4.7K +Change Component DesignItemId : Designator=R4 Old DesignItemId= New DesignItemId=4.7K +Change Component DesignItemId : Designator=C3 Old DesignItemId= New DesignItemId=10uF +Change Component DesignItemId : Designator=U5 Old DesignItemId= New DesignItemId=ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP +Change Component DesignItemId : Designator=BAT1 Old DesignItemId= New DesignItemId=CR1220-2ZX +Change Component DesignItemId : Designator=U4 Old DesignItemId= New DesignItemId=DS3231S +Change Component DesignItemId : Designator=J1 Old DesignItemId= New DesignItemId=PH2.0W-1X4P +Change Component DesignItemId : Designator=J2 Old DesignItemId= New DesignItemId=Դ +Change Component DesignItemId : Designator=J3 Old DesignItemId= New DesignItemId=Դ +Change Component DesignItemId : Designator=U2 Old DesignItemId= New DesignItemId=ѹģ +Change Component DesignItemId : Designator=U3 Old DesignItemId= New DesignItemId=ѹģ +Change component parameters: Designator = "U5"; Footprint = "ARDUINO-NANO-3.0#ISP"; UniqueID = "\ggea8e2f660ede1f0ef" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "sourceId"; Value = "MHTVTfAWi"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "M"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "timeStamp"; Value = "1463648055"; VariantName = "[No Variations]" +Change component parameters: Designator = "J1"; Footprint = "PH2.0W-1X4Pװ"; UniqueID = "\gge02c95373f3317acc" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "HeZo"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "43650-0615"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C239442"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "ݺ׿"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0W-1X4P"; VariantName = "[No Variations]" +Change component parameters: Designator = "J2"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge7a2095f9640df2a7" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]" +Change component parameters: Designator = "J3"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge24a1f388fafc13fc" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]" +Change component parameters: Designator = "R1"; Footprint = "R0603"; UniqueID = "\gge07bdca5a3aea9139" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Change component parameters: Designator = "R2"; Footprint = "R0603"; UniqueID = "\gge4ef602786d337833" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Change component parameters: Designator = "R3"; Footprint = "R0603"; UniqueID = "\gge195776cbb43ef2a0" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Change component parameters: Designator = "R4"; Footprint = "R0603"; UniqueID = "\gge8d4ca9ec2c2f1680" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Change component parameters: Designator = "BAT1"; Footprint = "BAT-SMD_CR1220-2ZX"; UniqueID = "\gge8f29627181d88637" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "Q&J"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "CR1220-2ZX"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C969906"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "B"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "CR1220-2ZX"; VariantName = "[No Variations]" +Change component parameters: Designator = "U4"; Footprint = "SOIC-16_L10.3-W7.5-P1.27-LS10.3-BL"; UniqueID = "\ggeae4eb166f739c636" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "MAXIM()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "DS3231S#T&R"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C2651514"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "DS3231S#T&R"; VariantName = "[No Variations]" +Change component parameters: Designator = "U1"; Footprint = "2·ֱģ(˫HŲ)"; UniqueID = "\gge950fff3d33dc0e42" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "nidewenyin"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "2·ֱģ(˫HŲ) COPY"; VariantName = "[No Variations]" +Change component parameters: Designator = "U2"; Footprint = "ѹģ"; UniqueID = "\ggee20cb5c0ba300364" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "ѹģ"; VariantName = "[No Variations]" +Change component parameters: Designator = "U3"; Footprint = "ѹģ"; UniqueID = "\ggee77114038a0ead5f" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "ѹģ"; VariantName = "[No Variations]" +Change component parameters: Designator = "C1"; Footprint = "C0603"; UniqueID = "\gge66964c34a4fec96d" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Change component parameters: Designator = "C2"; Footprint = "C0603"; UniqueID = "\ggeffcf16b24939ebf5" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Change component parameters: Designator = "C3"; Footprint = "C0603"; UniqueID = "\gge2a8eca0813df4c7e" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]" +Added Component: Designator=R5(6-0805_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R6(6-0805_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Pin To Net: NetName=VCC3.3 Pin=R5-2 +Added Pin To Net: NetName=VCC3.3 Pin=R6-2 +Change Net Name : Old Net Name=R1_1 New Net Name=NetR1_1 +Change Net Name : Old Net Name=R2_1 New Net Name=NetR2_1 +Change Net Name : Old Net Name=U4_14 New Net Name=NetBAT1_1 +Added Net: Name=GND +Added Pin To Net: NetName=NetPt1_2 Pin=R5-1 +Added Pin To Net: NetName=NetPt1_2 Pin=U5-J1.11 +Added Net: Name=NetPt1_2 +Added Pin To Net: NetName=NetPt2_2 Pin=R6-1 +Added Pin To Net: NetName=NetPt2_2 Pin=U5-J1.12 +Added Net: Name=NetPt2_2 +Added Class: Name=SIF Light_SCH 20220112_2022-07-06 +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-43-30.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-43-30.LOG new file mode 100644 index 0000000..38863e8 --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-43-30.LOG @@ -0,0 +1,3 @@ +Change Component Footprint: Designator=U2 Old Footprint= New Footprint=Դģ +Change Component Footprint: Designator=U3 Old Footprint= New Footprint=Դģ +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-58-09.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-58-09.LOG new file mode 100644 index 0000000..fd14aaa --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 15-58-09.LOG @@ -0,0 +1,21 @@ +Change Component Footprint: Designator=U2 Old Footprint= New Footprint=Դģ +Change Component Footprint: Designator=U3 Old Footprint= New Footprint=Դģ +Added Component: Designator=P?(1.25T-6P) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=P?-1 +Added Pin To Net: NetName=VCC3.3 Pin=P?-3 +Added Pin To Net: NetName=GND Pin=P?-4 +Added Pin To Net: NetName=VCC3.3 Pin=P?-6 +Added Pin To Net: NetName=NetP?_2 Pin=P?-2 +Added Pin To Net: NetName=NetP?_2 Pin=R6-1 +Added Pin To Net: NetName=NetP?_2 Pin=U5-J1.12 +Added Net: Name=NetP?_2 +Added Pin To Net: NetName=NetP?_5 Pin=P?-5 +Added Pin To Net: NetName=NetP?_5 Pin=R5-1 +Added Pin To Net: NetName=NetP?_5 Pin=U5-J1.11 +Added Net: Name=NetP?_5 +Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P? Header 6 +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-02-27.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-02-27.LOG new file mode 100644 index 0000000..ed4e45b --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-02-27.LOG @@ -0,0 +1,3 @@ +Removed Pin From Net: NetName=GND Pin=P?-1 +Added Pin To Net: NetName=DGND Pin=P?-1 +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-05-02.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-05-02.LOG new file mode 100644 index 0000000..e8ad404 --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-6 16-05-02.LOG @@ -0,0 +1,2 @@ +Added Pin To Net: NetName=DGND Pin=P?-4 +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-35-20.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-35-20.LOG new file mode 100644 index 0000000..14d1801 --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-35-20.LOG @@ -0,0 +1,30 @@ +Removed Pin From Net: NetName=DGND Pin=P?-1 +Removed Pin From Net: NetName=VCC3.3 Pin=P?-3 +Removed Pin From Net: NetName=DGND Pin=P?-4 +Removed Pin From Net: NetName=VCC3.3 Pin=P?-6 +Removed Member From Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=P? +Added Component: Designator=P1(1.25t-3p) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=P2(1.25t-3p) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=DGND Pin=P1-1 +Added Pin To Net: NetName=VCC3.3 Pin=P1-3 +Added Pin To Net: NetName=DGND Pin=P2-1 +Added Pin To Net: NetName=VCC3.3 Pin=P2-3 +Added Pin To Net: NetName=NetP1_2 Pin=P1-2 +Added Pin To Net: NetName=NetP1_2 Pin=R5-1 +Added Pin To Net: NetName=NetP1_2 Pin=U5-J1.11 +Added Net: Name=NetP1_2 +Added Pin To Net: NetName=NetP2_2 Pin=P2-2 +Added Pin To Net: NetName=NetP2_2 Pin=R6-1 +Added Pin To Net: NetName=NetP2_2 Pin=U5-J1.12 +Added Net: Name=NetP2_2 +Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P1 Header 3 +Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P2 Header 3 +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-37-07.LOG b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-37-07.LOG new file mode 100644 index 0000000..ef06f83 --- /dev/null +++ b/SIF LIGHT/主板/Project Logs for PCB_Project2/PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06 PCB ECO 2022-7-7 15-37-07.LOG @@ -0,0 +1,4 @@ +Change Component Footprint: Designator=P1 Old Footprint=1.25t-3p New Footprint=ds18b20 +Change Component Comment : Designator=P1 Old Comment=Header 3 New Comment=inner +Change Component Comment : Designator=P2 Old Comment=Header 3 New Comment=outside' +Added Room: Name=SIF Light_SCH 20220112_2022-07-06 diff --git a/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.drc b/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.drc new file mode 100644 index 0000000..6bdaf26 --- /dev/null +++ b/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.drc @@ -0,0 +1,210 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc +Date : 2022/7/7 +Time : 16:14:59 + +Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) + Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm + Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm + Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm + Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm +Rule Violations :4 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm] +Rule Violations :130 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm] + Violation between Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm] + Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm] + Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm] + Violation between Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm] + Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm] + Violation between Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm] + Violation between Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm] + Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm] + Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm] + Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm] + Violation between Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm] + Violation between Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm] + Violation between Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm] + Violation between Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm] + Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm] + Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm] + Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm] + Violation between Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm] +Rule Violations :28 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 162 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.html b/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.html new file mode 100644 index 0000000..d66e289 --- /dev/null +++ b/SIF LIGHT/主板/Project Outputs for PCB_Project2/Design Rule Check - PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.html @@ -0,0 +1,822 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/7/7
Time:16:14:59
Elapsed Time:00:00:01
Filename:C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc
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Warnings:0
Rule Violations:162
+

Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.254mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)4
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)130
Silk to Silk (Clearance=0.254mm) (All),(All)28
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total162

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Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm
Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm
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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]
Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]
Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]
Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]
Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]
Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]
Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]
Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]
Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]
Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]
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+ diff --git a/SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar b/SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar new file mode 100644 index 0000000..3d4de95 Binary files /dev/null and b/SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar differ diff --git a/SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc b/SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc new file mode 100644 index 0000000..abd4af4 Binary files /dev/null and b/SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc differ diff --git a/SIF LIGHT/主板/ds18b20.PcbLib b/SIF LIGHT/主板/ds18b20.PcbLib new file mode 100644 index 0000000..8442ca3 Binary files /dev/null and b/SIF LIGHT/主板/ds18b20.PcbLib differ diff --git a/SIF LIGHT/主板/电源模块.PcbLib b/SIF LIGHT/主板/电源模块.PcbLib new file mode 100644 index 0000000..c66bd70 Binary files /dev/null and b/SIF LIGHT/主板/电源模块.PcbLib differ diff --git a/SIF LIGHT/灯板/1.25t-3p.PcbLib b/SIF LIGHT/灯板/1.25t-3p.PcbLib new file mode 100644 index 0000000..ebe4ac3 Binary files /dev/null and b/SIF LIGHT/灯板/1.25t-3p.PcbLib differ diff --git a/SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib b/SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib new file mode 100644 index 0000000..cdf5c15 Binary files /dev/null and b/SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib differ diff --git a/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc b/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc new file mode 100644 index 0000000..cff6e51 Binary files /dev/null and b/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc differ diff --git a/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc.htm b/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc.htm new file mode 100644 index 0000000..4855fc1 --- /dev/null +++ b/SIF LIGHT/灯板/PCB_PCB_SIF Light _灯板 20220224_2022-03-24_2022-07-13.pcbdoc.htm @@ -0,0 +1,175 @@ + + + + + + + + + + Reporting Options +

File in Previous Format

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Date:2022/7/13
Time:13:08:06
Filename:C:\Users\hu123456\Desktop\SIF LIGHT\ư\PCB_PCB_SIF Light _ư 20220224_2022-03-24_2022-07-13.pcbdoc
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VersionWarning
6.3CAUTION - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.
Summer 09CAUTION - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.
Summer 09CAUTION - Existing testpoint rules and settings are used as fabrication testpoint information.
Release 12CAUTION - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.
Release 13CAUTION - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.
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This file was generated by an earlier version of the software

+ + diff --git a/SIF LIGHT/灯板/PCB_Project1.PrjPCB b/SIF LIGHT/灯板/PCB_Project1.PrjPCB new file mode 100644 index 0000000..89b3107 --- /dev/null +++ b/SIF LIGHT/灯板/PCB_Project1.PrjPCB @@ -0,0 +1,1124 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=1.25t-3p.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=WKJAWSLO + +[Document2] +DocumentPath=ds18b20.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=VFTAMGSC + +[Document3] +DocumentPath=SIF Light_SCH_ư 20220224_2022-07-13.schdoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=EGWLJJOU + +[Document4] +DocumentPath=PCB_PCB_SIF Light _ư 20220224_2022-03-24_2022-07-13.pcbdoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=ASWOSVND + +[Document5] +DocumentPath=pin.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=LFQKMIBY + +[Document6] +DocumentPath=DS18B20 MSOP8.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=EWKDHWWP + +[GeneratedDocument1] +DocumentPath=Project Outputs for PCB_Project1\Design Rule Check - PCB_PCB_SIF Light _ư 20220224_2022-03-24_2022-07-13.html +DItemRevisionGUID= + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + diff --git a/SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure b/SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure new file mode 100644 index 0000000..1fefdc5 --- /dev/null +++ b/SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=SIF Light_SCH_ư 20220224_2022-07-13.schdoc diff --git a/SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc b/SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc new file mode 100644 index 0000000..015ad0d Binary files /dev/null and b/SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc differ diff --git a/SIF LIGHT/灯板/ds18b20.PcbLib b/SIF LIGHT/灯板/ds18b20.PcbLib new file mode 100644 index 0000000..8442ca3 Binary files /dev/null and b/SIF LIGHT/灯板/ds18b20.PcbLib differ diff --git a/SIF LIGHT/灯板/pin.PcbLib b/SIF LIGHT/灯板/pin.PcbLib new file mode 100644 index 0000000..0dc4185 Binary files /dev/null and b/SIF LIGHT/灯板/pin.PcbLib differ diff --git a/TC300转接板/PCB2.PcbDoc b/TC300转接板/PCB2.PcbDoc new file mode 100644 index 0000000..9481a0b Binary files /dev/null and b/TC300转接板/PCB2.PcbDoc differ diff --git a/TC300转接板/PCB_Project2.PrjPCB b/TC300转接板/PCB_Project2.PrjPCB new file mode 100644 index 0000000..4970110 --- /dev/null +++ b/TC300转接板/PCB_Project2.PrjPCB @@ -0,0 +1,1110 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=USB3.0.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=QXBFSBLI + +[Document2] +DocumentPath=Sheet2.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=RNLAFQCH + +[Document3] +DocumentPath=Schlib1.SchLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=QEMFOUYW + +[Document4] +DocumentPath=PCB2.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=HCYXMQFC + +[Document5] +DocumentPath=fpc15.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=HKYBISTS + +[GeneratedDocument1] +DocumentPath=Project Outputs for PCB_Project2\Design Rule Check - PCB2.html +DItemRevisionGUID= + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=Virtual Printer +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + +[SmartPDF] +PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + diff --git a/TC300转接板/PCB_Project2.PrjPCBStructure b/TC300转接板/PCB_Project2.PrjPCBStructure new file mode 100644 index 0000000..6288434 --- /dev/null +++ b/TC300转接板/PCB_Project2.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=Sheet2.SchDoc diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-33-21.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-33-21.LOG new file mode 100644 index 0000000..da10250 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-33-21.LOG @@ -0,0 +1,44 @@ +Added Component: Designator=P1(HDR1X15) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=P2(HDR1X10) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=D+ Pin=P1-8 +Added Pin To Net: NetName=D+ Pin=P2-3 +Added Net: Name=D+ +Added Pin To Net: NetName=D- Pin=P1-9 +Added Pin To Net: NetName=D- Pin=P2-2 +Added Net: Name=D- +Added Pin To Net: NetName=GND_DRAIN Pin=P2-8 +Added Net: Name=GND_DRAIN +Added Pin To Net: NetName=GND Pin=P1-1 +Added Pin To Net: NetName=GND Pin=P1-4 +Added Pin To Net: NetName=GND Pin=P1-7 +Added Pin To Net: NetName=GND Pin=P1-10 +Added Pin To Net: NetName=GND Pin=P2-5 +Added Net: Name=GND +Added Pin To Net: NetName=ID Pin=P2-4 +Added Net: Name=ID +Added Pin To Net: NetName=MicB_SSRX+ Pin=P1-3 +Added Pin To Net: NetName=MicB_SSRX+ Pin=P2-10 +Added Net: Name=MicB_SSRX+ +Added Pin To Net: NetName=MicB_SSRX- Pin=P1-2 +Added Pin To Net: NetName=MicB_SSRX- Pin=P2-9 +Added Net: Name=MicB_SSRX- +Added Pin To Net: NetName=MicB_SSTX+ Pin=P1-5 +Added Pin To Net: NetName=MicB_SSTX+ Pin=P2-7 +Added Net: Name=MicB_SSTX+ +Added Pin To Net: NetName=MicB_SSTX- Pin=P1-6 +Added Pin To Net: NetName=MicB_SSTX- Pin=P2-6 +Added Net: Name=MicB_SSTX- +Added Pin To Net: NetName=VBUS Pin=P1-11 +Added Pin To Net: NetName=VBUS Pin=P1-12 +Added Pin To Net: NetName=VBUS Pin=P2-1 +Added Net: Name=VBUS +Added Class: Name=Sheet2 +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-34-28.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-34-28.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-34-28.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-37-54.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-37-54.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-37-54.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-38-20.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-38-20.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-38-20.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-39-11.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-39-11.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-39-11.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-41-36.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-41-36.LOG new file mode 100644 index 0000000..e69de29 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-48-38.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-48-38.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-48-38.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-49-39.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-49-39.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 13-49-39.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-01-06.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-01-06.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-01-06.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-05-31.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-05-31.LOG new file mode 100644 index 0000000..4e66e39 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-05-31.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-27-13.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-27-13.LOG new file mode 100644 index 0000000..27d4e19 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-27-13.LOG @@ -0,0 +1,3 @@ +Change Component Footprint: Designator=P2 Old Footprint=HDR1X10 New Footprint=USB3.0 +Change Component Footprint: Designator=P1 Old Footprint=HDR1X15 New Footprint=fpc15 +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-41-53.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-41-53.LOG new file mode 100644 index 0000000..a6ec59a --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 14-41-53.LOG @@ -0,0 +1,3 @@ +Removed Pin From Net: NetName=MicB_SSRX+ Pin=P2-10 +Added Pin To Net: NetName=MicB_SSRX+ Pin=P2-8 +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 15-27-56.LOG b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 15-27-56.LOG new file mode 100644 index 0000000..e357991 --- /dev/null +++ b/TC300转接板/Project Logs for PCB_Project2/PCB2 PCB ECO 2022-7-5 15-27-56.LOG @@ -0,0 +1,19 @@ +Added Component: Designator=P1(fpc15) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=P1-1 +Added Pin To Net: NetName=MicB_SSRX- Pin=P1-2 +Added Pin To Net: NetName=MicB_SSRX+ Pin=P1-3 +Added Pin To Net: NetName=GND Pin=P1-4 +Added Pin To Net: NetName=MicB_SSTX+ Pin=P1-5 +Added Pin To Net: NetName=MicB_SSTX- Pin=P1-6 +Added Pin To Net: NetName=GND Pin=P1-7 +Added Pin To Net: NetName=D+ Pin=P1-8 +Added Pin To Net: NetName=D- Pin=P1-9 +Added Pin To Net: NetName=GND Pin=P1-10 +Added Pin To Net: NetName=VBUS Pin=P1-11 +Added Pin To Net: NetName=VBUS Pin=P1-12 +Added Member To Class: ClassName=Sheet2 Member=Component P1 Header 15 +Added Room: Name=Sheet2 diff --git a/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.drc b/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.drc new file mode 100644 index 0000000..6f56161 --- /dev/null +++ b/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.drc @@ -0,0 +1,77 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\TC300תӰ\PCB2.PcbDoc +Date : 2022/7/7 +Time : 15:09:22 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) + Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-10(94.75mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm + Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-11(83.05mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm +Rule Violations :2 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(86.65mm,67.901mm) on Multi-Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(91.15mm,67.901mm) on Multi-Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-9(92.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-5(84.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Via (88.341mm,67.996mm) from Top Layer to Bottom Layer And Via (88.976mm,67.31mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.231mm] / [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (89.865mm,81.91mm) from Top Layer to Bottom Layer And Via (90.297mm,81.102mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm] +Rule Violations :12 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-1(85.139mm,78.959mm) on Top Layer And Track (82.639mm,78.996mm)(84.639mm,78.996mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-15(92.139mm,78.959mm) on Top Layer And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,78.996mm)(82.639mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.959mm)(82.639mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.997mm)(82.639mm,82.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.587mm,82.959mm)(94.587mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad P2-5(84.9mm,70.101mm) on Top Layer And Track (83.058mm,70.101mm)(84.328mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.095mm < 0.254mm) Between Pad P2-9(92.9mm,70.101mm) on Top Layer And Track (93.472mm,70.101mm)(94.742mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.095mm] +Rule Violations :9 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.17mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay Silk Text to Silk Clearance [0.17mm] + Violation between Silk To Silk Clearance Constraint: (0.197mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay Silk Text to Silk Clearance [0.197mm] +Rule Violations :2 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Matched Lengths(Tolerance=25.4mm) (All) + Violation between Matched Net Lengths: Between Net GND And Net ID Length:0mm is not within 25.4mm tolerance of Length:28.32mm (2.92mm short) +Rule Violations :1 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 26 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.html b/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.html new file mode 100644 index 0000000..093c28e --- /dev/null +++ b/TC300转接板/Project Outputs for PCB_Project2/Design Rule Check - PCB2.html @@ -0,0 +1,426 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/7/7
Time:15:09:22
Elapsed Time:00:00:01
Filename:C:\Users\hu123456\Desktop\TC300תӰ\PCB2.PcbDoc
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Warnings:0
Rule Violations:26
+

Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)2
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)12
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)9
Silk to Silk (Clearance=0.254mm) (All),(All)2
Net Antennae (Tolerance=0mm) (All)0
Matched Lengths(Tolerance=25.4mm) (All)1
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total26

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Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-10(94.75mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-11(83.05mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
Back to top

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(86.65mm,67.901mm) on Multi-Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(91.15mm,67.901mm) on Multi-Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-9(92.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-5(84.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Via (88.341mm,67.996mm) from Top Layer to Bottom Layer And Via (88.976mm,67.31mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.231mm] / [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (89.865mm,81.91mm) from Top Layer to Bottom Layer And Via (90.297mm,81.102mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]
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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-1(85.139mm,78.959mm) on Top Layer And Track (82.639mm,78.996mm)(84.639mm,78.996mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-15(92.139mm,78.959mm) on Top Layer And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,78.996mm)(82.639mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.959mm)(82.639mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.997mm)(82.639mm,82.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.587mm,82.959mm)(94.587mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad P2-5(84.9mm,70.101mm) on Top Layer And Track (83.058mm,70.101mm)(84.328mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm]
Silk To Solder Mask Clearance Constraint: (0.095mm < 0.254mm) Between Pad P2-9(92.9mm,70.101mm) on Top Layer And Track (93.472mm,70.101mm)(94.742mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.095mm]
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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.17mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay Silk Text to Silk Clearance [0.17mm]
Silk To Silk Clearance Constraint: (0.197mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay Silk Text to Silk Clearance [0.197mm]
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Matched Lengths(Tolerance=25.4mm) (All)
Matched Net Lengths: Between Net GND And Net ID Length:0mm is not within 25.4mm tolerance of Length:28.32mm (2.92mm short)
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+ diff --git a/TC300转接板/Schlib1.SchLib b/TC300转接板/Schlib1.SchLib new file mode 100644 index 0000000..6a9327c Binary files /dev/null and b/TC300转接板/Schlib1.SchLib differ diff --git a/TC300转接板/Sheet2.SchDoc b/TC300转接板/Sheet2.SchDoc new file mode 100644 index 0000000..503d3cf Binary files /dev/null and b/TC300转接板/Sheet2.SchDoc differ diff --git a/TC300转接板/TC300转接板2022.7.7.rar b/TC300转接板/TC300转接板2022.7.7.rar new file mode 100644 index 0000000..d201fc1 Binary files /dev/null and b/TC300转接板/TC300转接板2022.7.7.rar differ diff --git a/TC300转接板/USB3.0.PcbLib b/TC300转接板/USB3.0.PcbLib new file mode 100644 index 0000000..a4198f0 Binary files /dev/null and b/TC300转接板/USB3.0.PcbLib differ diff --git a/TC300转接板/fpc15.PcbLib b/TC300转接板/fpc15.PcbLib new file mode 100644 index 0000000..e27235f Binary files /dev/null and b/TC300转接板/fpc15.PcbLib differ diff --git a/optower/PCB_optoTower 改版HU20220304_2022-07-07.pcbdoc b/optower/PCB_optoTower 改版HU20220304_2022-07-07.pcbdoc new file mode 100644 index 0000000..ed19e95 Binary files /dev/null and b/optower/PCB_optoTower 改版HU20220304_2022-07-07.pcbdoc differ diff --git a/optower/PCB_optoTower优化2022.7.7.rar b/optower/PCB_optoTower优化2022.7.7.rar new file mode 100644 index 0000000..8e1b9cb Binary files /dev/null and b/optower/PCB_optoTower优化2022.7.7.rar differ diff --git a/使用时间监测模块/0603.PcbLib b/使用时间监测模块/0603.PcbLib new file mode 100644 index 0000000..90c7a89 Binary files /dev/null and b/使用时间监测模块/0603.PcbLib differ diff --git a/使用时间监测模块/117.PcbLib b/使用时间监测模块/117.PcbLib new file mode 100644 index 0000000..a67d1ec Binary files /dev/null and b/使用时间监测模块/117.PcbLib differ diff --git a/使用时间监测模块/1N4001W.PcbLib b/使用时间监测模块/1N4001W.PcbLib new file mode 100644 index 0000000..40aa84d Binary files /dev/null and b/使用时间监测模块/1N4001W.PcbLib differ diff --git a/使用时间监测模块/CNJMA2001WR-S-2P.PcbLib b/使用时间监测模块/CNJMA2001WR-S-2P.PcbLib new file mode 100644 index 0000000..2715b23 Binary files /dev/null and b/使用时间监测模块/CNJMA2001WR-S-2P.PcbLib differ diff --git a/使用时间监测模块/FC-135.PcbLib b/使用时间监测模块/FC-135.PcbLib new file mode 100644 index 0000000..9060dd5 Binary files /dev/null and b/使用时间监测模块/FC-135.PcbLib differ diff --git a/使用时间监测模块/GS2040AR-CR.PcbLib b/使用时间监测模块/GS2040AR-CR.PcbLib new file mode 100644 index 0000000..abee5a0 Binary files /dev/null and b/使用时间监测模块/GS2040AR-CR.PcbLib differ diff --git a/使用时间监测模块/MAX40200AUK+T.PcbLib b/使用时间监测模块/MAX40200AUK+T.PcbLib new file mode 100644 index 0000000..2b554cd Binary files /dev/null and b/使用时间监测模块/MAX40200AUK+T.PcbLib differ diff --git a/使用时间监测模块/PCB1.PcbDoc b/使用时间监测模块/PCB1.PcbDoc new file mode 100644 index 0000000..5f76475 Binary files /dev/null and b/使用时间监测模块/PCB1.PcbDoc differ diff --git a/使用时间监测模块/PCB_Project2.PrjPCB b/使用时间监测模块/PCB_Project2.PrjPCB new file mode 100644 index 0000000..295d76b --- /dev/null +++ b/使用时间监测模块/PCB_Project2.PrjPCB @@ -0,0 +1,1300 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=117.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=CLOVGEAG + +[Document2] +DocumentPath=MAX40200AUK+T.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=SGHXNDPL + +[Document3] +DocumentPath=XAL4020-102ME.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=FOCXOKOP + +[Document4] +DocumentPath=TLV62568A.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=TLSTNFSJ + +[Document5] +DocumentPath=SW.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=LXDCRWHM + +[Document6] +DocumentPath=CNJMA2001WR-S-2P.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=INPGMSFR + +[Document7] +DocumentPath=0603.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=BIUPNOXY + +[Document8] +DocumentPath=s8550.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=YEHQBMNG + +[Document9] +DocumentPath=FC-135.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=FQOKAWCL + +[Document10] +DocumentPath=GS2040AR-CR.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=XHCRLJYY + +[Document11] +DocumentPath=esp32-picp-d4.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=YQPQVROV + +[Document12] +DocumentPath=Sheet1.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=EOQQGAML + +[Document13] +DocumentPath=PCB1.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=IMPPCEGS + +[Document14] +DocumentPath=1N4001W.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=BVJNXFNT + +[Document15] +DocumentPath=TLV62568A.SchLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=XNYTWASM + +[GeneratedDocument1] +DocumentPath=Project Outputs for PCB_Project2\Design Rule Check - PCB1.html +DItemRevisionGUID= + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=Virtual Printer +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +Configuration1_Name1=ColumnNameFormat +Configuration1_Item1=CaptionAsName +Configuration1_Name2=Filter +Configuration1_Item2=545046300E5446696C74657257726170706572000D46696C7465722E416374697665090F46696C7465722E43726974657269610A04000000000000000000 +Configuration1_Name3=ForceUpdateSettings +Configuration1_Item3=False +Configuration1_Name4=General +Configuration1_Item4=OpenExported=False|AddToProject=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePCBData=False|IncludeVaultData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=|BatchMode=5|FormWidth=956|FormHeight=659|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=|ViewType=0 +Configuration1_Name5=GroupOrder +Configuration1_Item5=Value=True|Comment=True|Footprint=True +Configuration1_Name6=OutputConfigurationParameter1 +Configuration1_Item6=e +Configuration1_Name7=PCBDocument +Configuration1_Item7=FileName=PCB1.PcbDoc +Configuration1_Name8=PCBDocument2 +Configuration1_Item8=FileName=[PCB Document 1] +Configuration1_Name9=SortOrder +Configuration1_Item9=Designator=Up|Comment=Up|Footprint=Up +Configuration1_Name10=VisibleOrder +Configuration1_Item10=Comment=100|Description=100|Designator=100|Footprint=100|LibRef=100|Quantity=100|Value=100 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + +[SmartPDF] +PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + diff --git a/使用时间监测模块/PCB_Project2.PrjPCBStructure b/使用时间监测模块/PCB_Project2.PrjPCBStructure new file mode 100644 index 0000000..985c898 --- /dev/null +++ b/使用时间监测模块/PCB_Project2.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=Sheet1.SchDoc diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-22-32.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-22-32.LOG new file mode 100644 index 0000000..d6471fb --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-22-32.LOG @@ -0,0 +1,452 @@ +Added Component: Designator=C2(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C3(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=C4(C0805) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Chip Capacitor"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "C0805"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100F"; VariantName = "[No Variations]" +Added Component: Designator=C5(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=C6(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "3pF"; VariantName = "[No Variations]" +Added Component: Designator=C7(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "3pF"; VariantName = "[No Variations]" +Added Component: Designator=C8(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C9(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C10(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C11(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=C12(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "2.2F"; VariantName = "[No Variations]" +Added Component: Designator=C13(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C14(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "22F/10V"; VariantName = "[No Variations]" +Added Component: Designator=D?(SMC) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=P1(HDR1X2) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=P2(HDR1X3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=Q?(SOT-23B_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=Q?(SOT-23B_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=Q?(SOT-23B_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=Q?(SOT-23B_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=R3(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "69.8K"; VariantName = "[No Variations]" +Added Component: Designator=R4(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "22.1K"; VariantName = "[No Variations]" +Added Component: Designator=R5(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R6(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R7(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R8(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R9(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R10(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R11(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R12(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=R13(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R14(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R15(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R16(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R17(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R18(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R19(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R20(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=Y?(R38) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Crystal, Thru-Hole; 2 Leads; Body 3.1 x 8.2 mm (Dia.xH)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "R38"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3 Pin=C2-1 +Added Pin To Net: NetName=+3.3 Pin=C3-2 +Added Pin To Net: NetName=+3.3 Pin=C4-1 +Added Pin To Net: NetName=+3.3 Pin=C5-2 +Added Pin To Net: NetName=+3.3 Pin=C8-2 +Added Pin To Net: NetName=+3.3 Pin=D?-2 +Added Pin To Net: NetName=+3.3 Pin=Q?-3 +Added Pin To Net: NetName=+3.3 Pin=Q?-3 +Added Pin To Net: NetName=+3.3 Pin=Q?-3 +Added Pin To Net: NetName=+3.3 Pin=Q?-3 +Added Pin To Net: NetName=+3.3 Pin=R6-2 +Added Pin To Net: NetName=+3.3 Pin=R8-1 +Added Pin To Net: NetName=+3.3 Pin=R10-2 +Added Pin To Net: NetName=+3.3 Pin=R12-2 +Added Net: Name=+3.3 +Added Pin To Net: NetName=3.3V Pin=C9-2 +Added Pin To Net: NetName=3.3V Pin=C10-2 +Added Pin To Net: NetName=3.3V Pin=C11-1 +Added Net: Name=3.3V +Added Net: Name=EN +Added Pin To Net: NetName=GND1 Pin=C2-2 +Added Pin To Net: NetName=GND1 Pin=C3-1 +Added Pin To Net: NetName=GND1 Pin=C4-2 +Added Pin To Net: NetName=GND1 Pin=C5-1 +Added Pin To Net: NetName=GND1 Pin=C6-1 +Added Pin To Net: NetName=GND1 Pin=C7-1 +Added Pin To Net: NetName=GND1 Pin=C8-1 +Added Pin To Net: NetName=GND1 Pin=C9-1 +Added Pin To Net: NetName=GND1 Pin=C10-1 +Added Pin To Net: NetName=GND1 Pin=C11-2 +Added Pin To Net: NetName=GND1 Pin=C12-1 +Added Pin To Net: NetName=GND1 Pin=C14-1 +Added Pin To Net: NetName=GND1 Pin=P1-2 +Added Pin To Net: NetName=GND1 Pin=P2-3 +Added Pin To Net: NetName=GND1 Pin=R4-2 +Added Net: Name=GND1 +Added Net: Name=IO0 +Added Pin To Net: NetName=IO34 ADC Pin=C14-2 +Added Pin To Net: NetName=IO34 ADC Pin=D?-1 +Added Pin To Net: NetName=IO34 ADC Pin=R3-1 +Added Net: Name=IO34 ADC +Added Pin To Net: NetName=LED A Pin=R13-1 +Added Net: Name=LED A +Added Pin To Net: NetName=LED B Pin=R14-1 +Added Net: Name=LED B +Added Pin To Net: NetName=LED C Pin=R15-1 +Added Net: Name=LED C +Added Pin To Net: NetName=LED DP Pin=R20-1 +Added Net: Name=LED DP +Added Pin To Net: NetName=LED D Pin=R16-1 +Added Net: Name=LED D +Added Pin To Net: NetName=LED E Pin=R17-1 +Added Net: Name=LED E +Added Pin To Net: NetName=LED F Pin=R18-1 +Added Net: Name=LED F +Added Pin To Net: NetName=LED G Pin=R19-1 +Added Net: Name=LED G +Added Pin To Net: NetName=LED H1 Pin=R5-2 +Added Net: Name=LED H1 +Added Pin To Net: NetName=LED H2 Pin=R7-1 +Added Net: Name=LED H2 +Added Pin To Net: NetName=LED H3 Pin=R9-2 +Added Net: Name=LED H3 +Added Pin To Net: NetName=LED H4 Pin=R11-1 +Added Net: Name=LED H4 +Added Pin To Net: NetName=NetC6_2 Pin=C6-2 +Added Pin To Net: NetName=NetC6_2 Pin=Y?-1 +Added Net: Name=NetC6_2 +Added Pin To Net: NetName=NetC7_2 Pin=C7-2 +Added Pin To Net: NetName=NetC7_2 Pin=Y?-2 +Added Net: Name=NetC7_2 +Added Pin To Net: NetName=NetC12_2 Pin=C12-2 +Added Pin To Net: NetName=NetC12_2 Pin=P1-1 +Added Net: Name=NetC12_2 +Added Pin To Net: NetName=NetC13_1 Pin=C13-1 +Added Net: Name=NetC13_1 +Added Pin To Net: NetName=NetC13_2 Pin=C13-2 +Added Net: Name=NetC13_2 +Added Pin To Net: NetName=NetQ?_1 Pin=Q?-1 +Added Net: Name=NetQ?_1 +Added Pin To Net: NetName=NetQ?_2 Pin=Q?-2 +Added Pin To Net: NetName=NetQ?_2 Pin=R5-1 +Added Pin To Net: NetName=NetQ?_2 Pin=R6-1 +Added Net: Name=NetQ?_2 +Added Pin To Net: NetName=NetR3_2 Pin=R3-2 +Added Pin To Net: NetName=NetR3_2 Pin=R4-1 +Added Net: Name=NetR3_2 +Added Pin To Net: NetName=NetR13_2 Pin=R13-2 +Added Net: Name=NetR13_2 +Added Pin To Net: NetName=NetR14_2 Pin=R14-2 +Added Net: Name=NetR14_2 +Added Pin To Net: NetName=NetR15_2 Pin=R15-2 +Added Net: Name=NetR15_2 +Added Pin To Net: NetName=NetR16_2 Pin=R16-2 +Added Net: Name=NetR16_2 +Added Pin To Net: NetName=NetR17_2 Pin=R17-2 +Added Net: Name=NetR17_2 +Added Pin To Net: NetName=NetR18_2 Pin=R18-2 +Added Net: Name=NetR18_2 +Added Pin To Net: NetName=NetR19_2 Pin=R19-2 +Added Net: Name=NetR19_2 +Added Pin To Net: NetName=NetR20_2 Pin=R20-2 +Added Net: Name=NetR20_2 +Added Pin To Net: NetName=U0RXD Pin=P2-2 +Added Net: Name=U0RXD +Added Pin To Net: NetName=U0TXD Pin=P2-1 +Added Net: Name=U0TXD +Added Class: Name=Sheet1 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-23-40.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-23-40.LOG new file mode 100644 index 0000000..34fb5cb --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-23-40.LOG @@ -0,0 +1,29 @@ +Change Component Designator: OldDesignator=Q? NewDesignator=Q1 +Change Component Designator: OldDesignator=Q? NewDesignator=Q2 +Change Component Designator: OldDesignator=Q? NewDesignator=Q3 +Change Component Designator: OldDesignator=Q? NewDesignator=Q4 +Change Net Name : Old Net Name=NetQ?_2 New Net Name=NetQ1_2 +Added Pin To Net: NetName=NetQ1_1 Pin=Q1-1 +Added Net: Name=NetQ1_1 +Added Pin To Net: NetName=NetQ2_1 Pin=Q2-1 +Added Net: Name=NetQ2_1 +Added Pin To Net: NetName=NetQ2_2 Pin=Q2-2 +Added Pin To Net: NetName=NetQ2_2 Pin=R7-2 +Added Pin To Net: NetName=NetQ2_2 Pin=R8-2 +Added Net: Name=NetQ2_2 +Added Pin To Net: NetName=NetQ3_1 Pin=Q3-1 +Added Net: Name=NetQ3_1 +Added Pin To Net: NetName=NetQ3_2 Pin=Q3-2 +Added Pin To Net: NetName=NetQ3_2 Pin=R9-1 +Added Pin To Net: NetName=NetQ3_2 Pin=R10-1 +Added Net: Name=NetQ3_2 +Added Pin To Net: NetName=NetQ4_1 Pin=Q4-1 +Added Net: Name=NetQ4_1 +Added Pin To Net: NetName=NetQ4_2 Pin=Q4-2 +Added Pin To Net: NetName=NetQ4_2 Pin=R11-2 +Added Pin To Net: NetName=NetQ4_2 Pin=R12-1 +Added Net: Name=NetQ4_2 +Added Member To Class: ClassName=Sheet1 Member=Component Q2 PNP +Added Member To Class: ClassName=Sheet1 Member=Component Q3 PNP +Added Member To Class: ClassName=Sheet1 Member=Component Q4 PNP +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-26-47.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-26-47.LOG new file mode 100644 index 0000000..52a33f4 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-26-47.LOG @@ -0,0 +1,50 @@ +Change Component Footprint: Designator=C2 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C3 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C5 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C6 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C7 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C8 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C9 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C10 Old Footprint=RAD-0.3 New Footprint=0402 +Change Component Footprint: Designator=C11 Old Footprint=RAD-0.3 New Footprint=0402 +Added Component: Designator=U1(esp32-pico-d4) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3 Pin=U1-1 +Added Pin To Net: NetName=+3.3 Pin=U1-3 +Added Pin To Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=EN Pin=U1-9 +Added Pin To Net: NetName=IO34 ADC Pin=U1-10 +Added Pin To Net: NetName=NetC6_2 Pin=U1-12 +Added Pin To Net: NetName=NetC7_2 Pin=U1-13 +Added Pin To Net: NetName=+3.3 Pin=U1-19 +Added Pin To Net: NetName=GND1 Pin=U1-22 +Added Pin To Net: NetName=IO0 Pin=U1-23 +Added Pin To Net: NetName=LED DP Pin=U1-27 +Added Pin To Net: NetName=LED G Pin=U1-28 +Added Pin To Net: NetName=LED F Pin=U1-29 +Added Pin To Net: NetName=LED E Pin=U1-30 +Added Pin To Net: NetName=LED D Pin=U1-31 +Added Pin To Net: NetName=LED C Pin=U1-32 +Added Pin To Net: NetName=LED B Pin=U1-33 +Added Pin To Net: NetName=LED A Pin=U1-34 +Added Pin To Net: NetName=LED H4 Pin=U1-35 +Added Pin To Net: NetName=LED H3 Pin=U1-36 +Added Pin To Net: NetName=3.3V Pin=U1-37 +Added Pin To Net: NetName=LED H2 Pin=U1-38 +Added Pin To Net: NetName=LED H1 Pin=U1-39 +Added Pin To Net: NetName=U0RXD Pin=U1-40 +Added Pin To Net: NetName=U0TXD Pin=U1-41 +Added Pin To Net: NetName=3.3V Pin=U1-43 +Added Pin To Net: NetName=3.3V Pin=U1-46 +Added Pin To Net: NetName=GND1 Pin=U1-49 +Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-31-26.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-31-26.LOG new file mode 100644 index 0000000..b5dee41 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-31-26.LOG @@ -0,0 +1,16 @@ +Added Component: Designator=U3(GS2040AR-CR) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=NetR17_2 Pin=U3-1 +Added Pin To Net: NetName=NetR16_2 Pin=U3-2 +Added Pin To Net: NetName=NetR20_2 Pin=U3-3 +Added Pin To Net: NetName=NetR15_2 Pin=U3-4 +Added Pin To Net: NetName=NetR19_2 Pin=U3-5 +Added Pin To Net: NetName=NetQ1_1 Pin=U3-6 +Added Pin To Net: NetName=NetR14_2 Pin=U3-7 +Added Pin To Net: NetName=NetQ2_1 Pin=U3-8 +Added Pin To Net: NetName=NetQ3_1 Pin=U3-9 +Added Pin To Net: NetName=NetR18_2 Pin=U3-10 +Added Pin To Net: NetName=NetR13_2 Pin=U3-11 +Added Pin To Net: NetName=NetQ4_1 Pin=U3-12 +Added Member To Class: ClassName=Sheet1 Member=Component U3 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-38-48.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-38-48.LOG new file mode 100644 index 0000000..51d4d1f --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-4-29 17-38-48.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=Y? Old Footprint=R38 New Footprint=FC-135 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-31-50.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-31-50.LOG new file mode 100644 index 0000000..f5898c8 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-31-50.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=C4 Old Footprint=C0805 New Footprint=DIODE_SMC +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-50-57.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-50-57.LOG new file mode 100644 index 0000000..f0c9a76 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-5 16-50-57.LOG @@ -0,0 +1,53 @@ +Removed Pin From Net: NetName=+3.3 Pin=Q1-3 +Removed Pin From Net: NetName=+3.3 Pin=Q2-3 +Removed Pin From Net: NetName=+3.3 Pin=Q3-3 +Removed Pin From Net: NetName=+3.3 Pin=Q4-3 +Removed Pin From Net: NetName=NetQ1_1 Pin=U3-6 +Removed Pin From Net: NetName=NetQ2_1 Pin=U3-8 +Removed Pin From Net: NetName=NetQ3_1 Pin=U3-9 +Removed Pin From Net: NetName=NetQ4_1 Pin=U3-12 +Change Component Footprint: Designator=R5 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R6 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R7 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R8 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R9 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R10 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R11 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R12 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R13 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R14 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R15 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R16 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R17 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R18 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R19 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=R20 Old Footprint=AXIAL-0.3 New Footprint=0402 +Change Component Footprint: Designator=Q1 Old Footprint=SOT-23B_N New Footprint=s8550 +Change Component Footprint: Designator=Q2 Old Footprint=SOT-23B_N New Footprint=s8550 +Change Component Footprint: Designator=Q3 Old Footprint=SOT-23B_N New Footprint=s8550 +Change Component Footprint: Designator=Q4 Old Footprint=SOT-23B_N New Footprint=s8550 +Added Pin To Net: NetName=+3.3 Pin=Q1-2 +Added Pin To Net: NetName=+3.3 Pin=Q2-2 +Added Pin To Net: NetName=+3.3 Pin=Q3-2 +Added Pin To Net: NetName=+3.3 Pin=Q4-2 +Added Pin To Net: NetName=NetQ1_1 Pin=R5-1 +Added Pin To Net: NetName=NetQ1_1 Pin=R6-1 +Added Pin To Net: NetName=NetQ2_1 Pin=R7-2 +Added Pin To Net: NetName=NetQ2_1 Pin=R8-2 +Added Pin To Net: NetName=NetQ3_1 Pin=R9-1 +Added Pin To Net: NetName=NetQ3_1 Pin=R10-1 +Added Pin To Net: NetName=NetQ4_1 Pin=R11-2 +Added Pin To Net: NetName=NetQ4_1 Pin=R12-1 +Added Pin To Net: NetName=NetQ1_3 Pin=Q1-3 +Added Pin To Net: NetName=NetQ1_3 Pin=U3-6 +Added Net: Name=NetQ1_3 +Added Pin To Net: NetName=NetQ2_3 Pin=Q2-3 +Added Pin To Net: NetName=NetQ2_3 Pin=U3-8 +Added Net: Name=NetQ2_3 +Added Pin To Net: NetName=NetQ3_3 Pin=Q3-3 +Added Pin To Net: NetName=NetQ3_3 Pin=U3-9 +Added Net: Name=NetQ3_3 +Added Pin To Net: NetName=NetQ4_3 Pin=Q4-3 +Added Pin To Net: NetName=NetQ4_3 Pin=U3-12 +Added Net: Name=NetQ4_3 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 14-44-33.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 14-44-33.LOG new file mode 100644 index 0000000..b658e05 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 14-44-33.LOG @@ -0,0 +1,115 @@ +Removed Pin From Net: NetName=GND1 Pin=C12-1 +Removed Pin From Net: NetName=GND1 Pin=C14-1 +Removed Pin From Net: NetName=IO34 ADC Pin=C14-2 +Removed Pin From Net: NetName=IO34 ADC Pin=R3-1 +Removed Pin From Net: NetName=GND1 Pin=R4-2 +Removed Pin From Net: NetName=LED A Pin=R13-1 +Removed Pin From Net: NetName=LED B Pin=R14-1 +Removed Pin From Net: NetName=LED C Pin=R15-1 +Removed Pin From Net: NetName=LED D Pin=R16-1 +Removed Pin From Net: NetName=LED E Pin=R17-1 +Removed Pin From Net: NetName=LED F Pin=R18-1 +Removed Pin From Net: NetName=LED G Pin=R19-1 +Removed Pin From Net: NetName=LED DP Pin=R20-1 +Removed Member From Class: ClassName=Sheet1 Member=R3 +Removed Member From Class: ClassName=Sheet1 Member=R4 +Removed Member From Class: ClassName=Sheet1 Member=R13 +Removed Member From Class: ClassName=Sheet1 Member=R14 +Removed Member From Class: ClassName=Sheet1 Member=R15 +Removed Member From Class: ClassName=Sheet1 Member=R16 +Removed Member From Class: ClassName=Sheet1 Member=R17 +Removed Member From Class: ClassName=Sheet1 Member=R18 +Removed Member From Class: ClassName=Sheet1 Member=R19 +Removed Member From Class: ClassName=Sheet1 Member=R20 +Change Component Footprint: Designator=C12 Old Footprint=RAD-0.3 New Footprint=6-0805_N +Change Component Footprint: Designator=C13 Old Footprint=RAD-0.3 New Footprint=6-0805_N +Change Component Footprint: Designator=C14 Old Footprint=RAD-0.3 New Footprint=6-0805_N +Change Component Designator: OldDesignator=U3 NewDesignator=U5 +Change component parameters: Designator = "C12"; Footprint = "6-0805_N"; UniqueID = "\SLGBJKAR" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "0.22F"; VariantName = "[No Variations]" +Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\PWVEDBTD" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22F"; VariantName = "[No Variations]" +Added Component: Designator=C15(6-0805_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=C16(6-0805_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=U2(LM340) +Add component. Clean all parameters for all variants +Added Component: Designator=U3(AMS1117) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=IO34 ADC Pin=C16-2 +Added Pin To Net: NetName=NetC12_2 Pin=U2-1 +Added Pin To Net: NetName=IO34 ADC Pin=U3-2 +Added Pin To Net: NetName=IO34 ADC Pin=U3-4 +Added Pin To Net: NetName=+5 Pin=C13-2 +Added Pin To Net: NetName=+5 Pin=C14-2 +Added Pin To Net: NetName=+5 Pin=C15-2 +Added Pin To Net: NetName=+5 Pin=U2-3 +Added Pin To Net: NetName=+5 Pin=U3-3 +Added Net: Name=+5 +Added Pin To Net: NetName=DP Pin=U5-3 +Added Net: Name=DP +Added Pin To Net: NetName=GND Pin=C12-1 +Added Pin To Net: NetName=GND Pin=C13-1 +Added Pin To Net: NetName=GND Pin=C14-1 +Added Pin To Net: NetName=GND Pin=C15-1 +Added Pin To Net: NetName=GND Pin=C16-1 +Added Pin To Net: NetName=GND Pin=U2-2 +Added Pin To Net: NetName=GND Pin=U2-4 +Added Pin To Net: NetName=GND Pin=U3-1 +Added Net: Name=GND +Added Pin To Net: NetName=GR1 Pin=U5-6 +Added Net: Name=GR1 +Added Pin To Net: NetName=GR2 Pin=U5-8 +Added Net: Name=GR2 +Added Pin To Net: NetName=GR3 Pin=U5-9 +Added Net: Name=GR3 +Added Pin To Net: NetName=GR4 Pin=U5-12 +Added Net: Name=GR4 +Added Pin To Net: NetName=SG1 Pin=U5-11 +Added Net: Name=SG1 +Added Pin To Net: NetName=SG2 Pin=U5-7 +Added Net: Name=SG2 +Added Pin To Net: NetName=SG3 Pin=U5-4 +Added Net: Name=SG3 +Added Pin To Net: NetName=SG4 Pin=U5-2 +Added Net: Name=SG4 +Added Pin To Net: NetName=SG5 Pin=U5-1 +Added Net: Name=SG5 +Added Pin To Net: NetName=SG6 Pin=U5-10 +Added Net: Name=SG6 +Added Pin To Net: NetName=SG7 Pin=U5-5 +Added Net: Name=SG7 +Added Member To Class: ClassName=Sheet1 Member=Component C15 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C16 Cap +Added Member To Class: ClassName=Sheet1 Member=Component U2 +Added Member To Class: ClassName=Sheet1 Member=Component U5 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-32-17.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-32-17.LOG new file mode 100644 index 0000000..413b030 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-32-17.LOG @@ -0,0 +1,17 @@ +Added Component: Designator=U4(VK1650) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=GR1 Pin=U4-1 +Added Pin To Net: NetName=GND Pin=U4-4 +Added Pin To Net: NetName=GR2 Pin=U4-5 +Added Pin To Net: NetName=GR3 Pin=U4-6 +Added Pin To Net: NetName=GR4 Pin=U4-7 +Added Pin To Net: NetName=SG1 Pin=U4-8 +Added Pin To Net: NetName=SG2 Pin=U4-9 +Added Pin To Net: NetName=SG3 Pin=U4-11 +Added Pin To Net: NetName=SG4 Pin=U4-12 +Added Pin To Net: NetName=SG5 Pin=U4-13 +Added Pin To Net: NetName=SG6 Pin=U4-14 +Added Pin To Net: NetName=SG7 Pin=U4-15 +Added Pin To Net: NetName=DP Pin=U4-16 +Added Member To Class: ClassName=Sheet1 Member=Component U4 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-33-42.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-33-42.LOG new file mode 100644 index 0000000..56d0bcb --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-33-42.LOG @@ -0,0 +1,49 @@ +Removed Pin From Net: NetName=+3.3 Pin=Q1-2 +Removed Pin From Net: NetName=+3.3 Pin=Q2-2 +Removed Pin From Net: NetName=+3.3 Pin=Q3-2 +Removed Pin From Net: NetName=+3.3 Pin=Q4-2 +Removed Pin From Net: NetName=LED H1 Pin=R5-2 +Removed Pin From Net: NetName=+3.3 Pin=R6-2 +Removed Pin From Net: NetName=LED H2 Pin=R7-1 +Removed Pin From Net: NetName=+3.3 Pin=R8-1 +Removed Pin From Net: NetName=LED H3 Pin=R9-2 +Removed Pin From Net: NetName=+3.3 Pin=R10-2 +Removed Pin From Net: NetName=LED H4 Pin=R11-1 +Removed Pin From Net: NetName=+3.3 Pin=R12-2 +Removed Member From Class: ClassName=Sheet1 Member=Q1 +Removed Member From Class: ClassName=Sheet1 Member=Q2 +Removed Member From Class: ClassName=Sheet1 Member=Q3 +Removed Member From Class: ClassName=Sheet1 Member=Q4 +Removed Member From Class: ClassName=Sheet1 Member=R5 +Removed Member From Class: ClassName=Sheet1 Member=R6 +Removed Member From Class: ClassName=Sheet1 Member=R7 +Removed Member From Class: ClassName=Sheet1 Member=R8 +Removed Member From Class: ClassName=Sheet1 Member=R9 +Removed Member From Class: ClassName=Sheet1 Member=R10 +Removed Member From Class: ClassName=Sheet1 Member=R11 +Removed Member From Class: ClassName=Sheet1 Member=R12 +Added Component: Designator=C?(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]" +Added Component: Designator=C?(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=C?-1 +Added Pin To Net: NetName=GND Pin=C?-1 +Added Pin To Net: NetName=+3.3 Pin=C?-2 +Added Pin To Net: NetName=+3.3 Pin=C?-2 +Added Pin To Net: NetName=+3.3 Pin=U4-10 +Added Member To Class: ClassName=Sheet1 Member=Component C? Cap +Added Member To Class: ClassName=Sheet1 Member=Component C? Cap diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-39-22.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-39-22.LOG new file mode 100644 index 0000000..56fda06 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-39-22.LOG @@ -0,0 +1,6 @@ +Change Component Footprint: Designator=C? Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C? Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Designator: OldDesignator=C? NewDesignator=C17 +Change Component Designator: OldDesignator=C? NewDesignator=C18 +Added Member To Class: ClassName=Sheet1 Member=Component C17 Cap +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-41-37.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-41-37.LOG new file mode 100644 index 0000000..bf4c8fe --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 15-41-37.LOG @@ -0,0 +1,37 @@ +Added Component: Designator=C1(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "nameAlias"; Value = "Value(F)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "C_0603_US"; VariantName = "[No Variations]" +Added Component: Designator=R1(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Added Component: Designator=R2(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND1 Pin=C1-1 +Added Pin To Net: NetName=EN Pin=C1-2 +Added Pin To Net: NetName=EN Pin=R1-1 +Added Pin To Net: NetName=+3.3 Pin=R1-2 +Added Pin To Net: NetName=IO0 Pin=R2-1 +Added Pin To Net: NetName=+3.3 Pin=R2-2 +Added Member To Class: ClassName=Sheet1 Member=Component C1 1u +Added Member To Class: ClassName=Sheet1 Member=Component R1 10k +Added Member To Class: ClassName=Sheet1 Member=Component R2 10k +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 16-55-30.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 16-55-30.LOG new file mode 100644 index 0000000..d336544 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 16-55-30.LOG @@ -0,0 +1,7 @@ +Added Pin To Net: NetName=+3.3 Pin=C9-2 +Added Pin To Net: NetName=+3.3 Pin=C10-2 +Added Pin To Net: NetName=+3.3 Pin=C11-1 +Added Pin To Net: NetName=+3.3 Pin=U1-37 +Added Pin To Net: NetName=+3.3 Pin=U1-43 +Added Pin To Net: NetName=+3.3 Pin=U1-46 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-00-44.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-00-44.LOG new file mode 100644 index 0000000..24edf5e --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-00-44.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=P1 Old Footprint=HDR1X2 New Footprint=CNJMA2001WR-S-2P +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-10-05.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-10-05.LOG new file mode 100644 index 0000000..bed6883 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-10-05.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=D? Old Footprint=SMC New Footprint=1N4001W +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-14-50.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-14-50.LOG new file mode 100644 index 0000000..7ebdafd --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-6 17-14-50.LOG @@ -0,0 +1,41 @@ +Added Component: Designator=R?(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]" +Added Component: Designator=SW1(SW) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "SHOU HAN"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C557591"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "S"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]" +Added Component: Designator=SW2(SW) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "SHOU HAN"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C557591"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "S"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3 Pin=R?-2 +Added Pin To Net: NetName=IO0 Pin=SW1-1 +Added Pin To Net: NetName=GND1 Pin=SW1-2 +Added Pin To Net: NetName=GND Pin=SW2-2 +Added Pin To Net: NetName=SW Pin=R?-1 +Added Pin To Net: NetName=SW Pin=SW2-1 +Added Pin To Net: NetName=SW Pin=U1-24 +Added Net: Name=SW +Added Member To Class: ClassName=Sheet1 Member=Component R? Res1 +Added Member To Class: ClassName=Sheet1 Member=Component SW1 TS342A2P-WZ +Added Member To Class: ClassName=Sheet1 Member=Component SW2 TS342A2P-WZ +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 10-42-00.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 10-42-00.LOG new file mode 100644 index 0000000..f6c88bc --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 10-42-00.LOG @@ -0,0 +1,7 @@ +Added Pin To Net: NetName=CLK Pin=U1-14 +Added Pin To Net: NetName=CLK Pin=U4-2 +Added Net: Name=CLK +Added Pin To Net: NetName=DAT Pin=U1-15 +Added Pin To Net: NetName=DAT Pin=U4-3 +Added Net: Name=DAT +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 11-35-31.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 11-35-31.LOG new file mode 100644 index 0000000..a80d9ef --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-5-7 11-35-31.LOG @@ -0,0 +1,14 @@ +Added Pin To Net: NetName=GND1 Pin=C12-1 +Added Pin To Net: NetName=GND1 Pin=C13-1 +Added Pin To Net: NetName=GND1 Pin=C14-1 +Added Pin To Net: NetName=GND1 Pin=C15-1 +Added Pin To Net: NetName=GND1 Pin=C16-1 +Added Pin To Net: NetName=GND1 Pin=C17-1 +Added Pin To Net: NetName=GND1 Pin=C18-1 +Added Pin To Net: NetName=GND1 Pin=SW2-2 +Added Pin To Net: NetName=GND1 Pin=U2-2 +Added Pin To Net: NetName=GND1 Pin=U2-4 +Added Pin To Net: NetName=GND1 Pin=U3-1 +Added Pin To Net: NetName=GND1 Pin=U4-4 +Change Net Name : Old Net Name=GND1 New Net Name=GND +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-28.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-28.LOG new file mode 100644 index 0000000..312d572 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-28.LOG @@ -0,0 +1,58 @@ +Removed Pin From Net: NetName=GND Pin=C14-1 +Removed Pin From Net: NetName=+5 Pin=C14-2 +Removed Pin From Net: NetName=GND Pin=C15-1 +Removed Pin From Net: NetName=+5 Pin=C15-2 +Removed Pin From Net: NetName=GND Pin=C16-1 +Removed Pin From Net: NetName=IO34 ADC Pin=C16-2 +Removed Pin From Net: NetName=IO34 ADC Pin=D?-1 +Removed Pin From Net: NetName=+3.3 Pin=D?-2 +Removed Pin From Net: NetName=GND Pin=U3-1 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-2 +Removed Pin From Net: NetName=+5 Pin=U3-3 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-4 +Removed Member From Class: ClassName=Sheet1 Member=C14 +Removed Member From Class: ClassName=Sheet1 Member=C15 +Removed Member From Class: ClassName=Sheet1 Member=C16 +Removed Member From Class: ClassName=Sheet1 Member=U3 +Change Component Designator: OldDesignator=D? NewDesignator=D1 +Added Component: Designator=C?(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]" +Added Component: Designator=D2(1N4001W) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=R?(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=C?-1 +Added Pin To Net: NetName=IO34 ADC Pin=C?-2 +Added Pin To Net: NetName=+5 Pin=D1-1 +Added Pin To Net: NetName=+3.3 Pin=D2-2 +Added Pin To Net: NetName=+5 Pin=R?-1 +Added Pin To Net: NetName=IO34 ADC Pin=R?-2 +Added Pin To Net: NetName=NetD1_2 Pin=D1-2 +Added Pin To Net: NetName=NetD1_2 Pin=D2-1 +Added Net: Name=NetD1_2 +Added Member To Class: ClassName=Sheet1 Member=Component C? Cap +Added Member To Class: ClassName=Sheet1 Member=Component D2 Diode +Added Member To Class: ClassName=Sheet1 Member=Component R? Res1 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-51.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-51.LOG new file mode 100644 index 0000000..ace1187 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-16 16-28-51.LOG @@ -0,0 +1,33 @@ +Added Component: Designator=U1(esp32-pico-d4) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3 Pin=U1-1 +Added Pin To Net: NetName=+3.3 Pin=U1-3 +Added Pin To Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=EN Pin=U1-9 +Added Pin To Net: NetName=IO34 ADC Pin=U1-10 +Added Pin To Net: NetName=NetC6_2 Pin=U1-12 +Added Pin To Net: NetName=NetC7_2 Pin=U1-13 +Added Pin To Net: NetName=CLK Pin=U1-14 +Added Pin To Net: NetName=DAT Pin=U1-15 +Added Pin To Net: NetName=+3.3 Pin=U1-19 +Added Pin To Net: NetName=GND Pin=U1-22 +Added Pin To Net: NetName=IO0 Pin=U1-23 +Added Pin To Net: NetName=SW Pin=U1-24 +Added Pin To Net: NetName=+3.3 Pin=U1-37 +Added Pin To Net: NetName=U0RXD Pin=U1-40 +Added Pin To Net: NetName=U0TXD Pin=U1-41 +Added Pin To Net: NetName=+3.3 Pin=U1-43 +Added Pin To Net: NetName=+3.3 Pin=U1-46 +Added Pin To Net: NetName=GND Pin=U1-49 +Added Member To Class: ClassName=Sheet1 Member=Component R? Res1 +Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG new file mode 100644 index 0000000..85c0ac4 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG @@ -0,0 +1,129 @@ +Removed Pin From Net: NetName=+3.3 Pin=C2-1 +Removed Pin From Net: NetName=GND Pin=C2-2 +Removed Pin From Net: NetName=+3.3 Pin=C5-2 +Removed Pin From Net: NetName=GND Pin=C6-1 +Removed Pin From Net: NetName=GND Pin=C7-1 +Removed Pin From Net: NetName=GND Pin=C9-1 +Removed Pin From Net: NetName=+3.3 Pin=C9-2 +Removed Pin From Net: NetName=GND Pin=C10-1 +Removed Pin From Net: NetName=+3.3 Pin=C10-2 +Removed Pin From Net: NetName=+5 Pin=C15-2 +Removed Pin From Net: NetName=GND Pin=C16-1 +Removed Pin From Net: NetName=IO34 ADC Pin=C16-2 +Removed Pin From Net: NetName=+3.3 Pin=C17-2 +Removed Pin From Net: NetName=+3.3 Pin=C18-2 +Removed Pin From Net: NetName=IO34 ADC Pin=D?-1 +Removed Pin From Net: NetName=+3.3 Pin=D?-2 +Removed Pin From Net: NetName=+3.3 Pin=U1-4 +Removed Pin From Net: NetName=GND Pin=U3-1 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-2 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-4 +Removed Pin From Net: NetName=+3.3 Pin=U4-10 +Removed Member From Class: ClassName=Sheet1 Member=C2 +Removed Member From Class: ClassName=Sheet1 Member=C6 +Removed Member From Class: ClassName=Sheet1 Member=C7 +Removed Member From Class: ClassName=Sheet1 Member=C9 +Removed Member From Class: ClassName=Sheet1 Member=C10 +Removed Member From Class: ClassName=Sheet1 Member=D? +Removed Member From Class: ClassName=Sheet1 Member=Y? +Change Component Footprint: Designator=C14 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Footprint: Designator=C15 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Footprint: Designator=C16 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Comment : Designator=U3 Old Comment= New Comment=TLV62568A +Change Component Designator: OldDesignator=C17 NewDesignator=C18 +Change Component Designator: OldDesignator=C18 NewDesignator=C19 +Change Component Designator: OldDesignator=R? NewDesignator=R3 +Change Component Designator: OldDesignator=U4 NewDesignator=U5 +Change Component Designator: OldDesignator=U5 NewDesignator=U6 +Change component parameters: Designator = "C14"; Footprint = "RAD-0.3"; UniqueID = "\WMNPPNUP" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "4.7F"; VariantName = "[No Variations]" +Change component parameters: Designator = "C15"; Footprint = "RAD-0.3"; UniqueID = "\NCFGQGJL" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22F"; VariantName = "[No Variations]" +Change component parameters: Designator = "C16"; Footprint = "RAD-0.3"; UniqueID = "\NYURCQQB" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "10pF"; VariantName = "[No Variations]" +Added Component: Designator=C17(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]" +Added Component: Designator=R4(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R5(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R6(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=C17-1 +Added Pin To Net: NetName=IO34 ADC Pin=C17-2 +Added Pin To Net: NetName=GND Pin=R5-1 +Added Pin To Net: NetName=IO34 ADC Pin=R6-2 +Added Pin To Net: NetName=GND Pin=U3-2 +Change Net Name : Old Net Name=+3.3 New Net Name=+3.3-2 +Added Pin To Net: NetName=+3.3 Pin=C5-2 +Added Pin To Net: NetName=+3.3 Pin=C15-2 +Added Pin To Net: NetName=+3.3 Pin=C16-2 +Added Pin To Net: NetName=+3.3 Pin=C18-2 +Added Pin To Net: NetName=+3.3 Pin=C19-2 +Added Pin To Net: NetName=+3.3 Pin=R4-2 +Added Pin To Net: NetName=+3.3 Pin=R6-1 +Added Pin To Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=+3.3 Pin=U5-10 +Added Net: Name=+3.3 +Added Pin To Net: NetName=NetC16_1 Pin=C16-1 +Added Pin To Net: NetName=NetC16_1 Pin=R4-1 +Added Pin To Net: NetName=NetC16_1 Pin=R5-2 +Added Pin To Net: NetName=NetC16_1 Pin=U3-1 +Added Net: Name=NetC16_1 +Added Pin To Net: NetName=NetPL?_1 Pin=U3-4 +Added Net: Name=NetPL?_1 +Added Member To Class: ClassName=Sheet1 Member=Component C19 Cap +Added Member To Class: ClassName=Sheet1 Member=Component R4 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component R5 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component R6 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component U6 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG new file mode 100644 index 0000000..5c04efe --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG @@ -0,0 +1,2 @@ +Added Member To Class: ClassName=Sheet1 Member=Component C12 Cap +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG new file mode 100644 index 0000000..38615e1 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG @@ -0,0 +1,5 @@ +Removed Pin From Net: NetName=+3.3 Pin=C5-2 +Removed Pin From Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=+3.3-2 Pin=C5-2 +Added Pin To Net: NetName=+3.3-2 Pin=U1-4 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG new file mode 100644 index 0000000..f1b4ebb --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG @@ -0,0 +1,30 @@ +Added Component: Designator=U1(esp32-pico-d4) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3-2 Pin=U1-1 +Added Pin To Net: NetName=+3.3-2 Pin=U1-3 +Added Pin To Net: NetName=+3.3-2 Pin=U1-4 +Added Pin To Net: NetName=EN Pin=U1-9 +Added Pin To Net: NetName=IO34 ADC Pin=U1-10 +Added Pin To Net: NetName=CLK Pin=U1-14 +Added Pin To Net: NetName=DAT Pin=U1-15 +Added Pin To Net: NetName=+3.3-2 Pin=U1-19 +Added Pin To Net: NetName=GND Pin=U1-22 +Added Pin To Net: NetName=IO0 Pin=U1-23 +Added Pin To Net: NetName=SW Pin=U1-24 +Added Pin To Net: NetName=+3.3-2 Pin=U1-37 +Added Pin To Net: NetName=U0RXD Pin=U1-40 +Added Pin To Net: NetName=U0TXD Pin=U1-41 +Added Pin To Net: NetName=+3.3-2 Pin=U1-43 +Added Pin To Net: NetName=+3.3-2 Pin=U1-46 +Added Pin To Net: NetName=GND Pin=U1-49 +Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG new file mode 100644 index 0000000..8865168 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG @@ -0,0 +1,16 @@ +Change Component Footprint: Designator=R4 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=R5 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=R6 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=C14 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C15 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C16 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C17 Old Footprint=RAD-0.3 New Footprint=0603 +Added Component: Designator=U3(TLV62568A) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=NetC16_1 Pin=U3-1 +Added Pin To Net: NetName=GND Pin=U3-2 +Added Pin To Net: NetName=+5 Pin=U3-3 +Added Pin To Net: NetName=NetPL?_1 Pin=U3-4 +Added Pin To Net: NetName=+5 Pin=U3-5 +Added Member To Class: ClassName=Sheet1 Member=Component U3 TLV62568A +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG new file mode 100644 index 0000000..a0a263b --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG @@ -0,0 +1,6 @@ +Added Component: Designator=PL?(XAL4020-102ME) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=NetPL?_1 Pin=PL?-1 +Added Pin To Net: NetName=+3.3 Pin=PL?-2 +Added Member To Class: ClassName=Sheet1 Member=Component PL? 2.2H +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG new file mode 100644 index 0000000..3ee9131 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG @@ -0,0 +1,8 @@ +Added Component: Designator=U4(MAX40200AUK+T) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=+3.3 Pin=U4-1 +Added Pin To Net: NetName=GND Pin=U4-2 +Added Pin To Net: NetName=+3.3 Pin=U4-3 +Added Pin To Net: NetName=+3.3-2 Pin=U4-5 +Added Member To Class: ClassName=Sheet1 Member=Component U4 MAX40200AUK+T +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG new file mode 100644 index 0000000..43fe089 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG @@ -0,0 +1,10 @@ +Added Component: Designator=P2(HDR1X3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=U0TXD Pin=P2-1 +Added Pin To Net: NetName=U0RXD Pin=P2-2 +Added Pin To Net: NetName=GND Pin=P2-3 +Added Member To Class: ClassName=Sheet1 Member=Component P2 DEBUG +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG new file mode 100644 index 0000000..6a5b8db --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG @@ -0,0 +1,63 @@ +Removed Pin From Net: NetName=GND Pin=C14-1 +Removed Pin From Net: NetName=+5 Pin=C14-2 +Removed Pin From Net: NetName=GND Pin=C15-1 +Removed Pin From Net: NetName=+3.3 Pin=C15-2 +Removed Pin From Net: NetName=+3.3 Pin=C16-2 +Removed Pin From Net: NetName=+3.3 Pin=PL?-2 +Removed Pin From Net: NetName=+3.3 Pin=R4-2 +Removed Pin From Net: NetName=GND Pin=R5-1 +Removed Pin From Net: NetName=GND Pin=U3-2 +Removed Pin From Net: NetName=+5 Pin=U3-3 +Removed Pin From Net: NetName=+5 Pin=U3-5 +Removed Member From Class: ClassName=Sheet1 Member=C16 +Removed Member From Class: ClassName=Sheet1 Member=PL? +Removed Member From Class: ClassName=Sheet1 Member=R4 +Removed Member From Class: ClassName=Sheet1 Member=R5 +Removed Member From Class: ClassName=Sheet1 Member=U3 +Change Component Footprint: Designator=C14 Old Footprint=0603 New Footprint=6-0805_N +Change Component Footprint: Designator=C15 Old Footprint=0603 New Footprint=6-0805_N +Change Component Comment : Designator=C14 Old Comment=Cap New Comment=10uF +Change Component Comment : Designator=C15 Old Comment=Cap New Comment=22uF/25V +Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\QDBKEQLT" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805X106K160NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C89189"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters: Designator = "C15"; Footprint = "6-0805_N"; UniqueID = "\MJCTGQXY" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "A_Ԫ"; Value = "C45783"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "B_Ԫ"; Value = "22uF (226) 20% 25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "C_Ԫ"; Value = "Ƭ"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "D_Ԫͺ"; Value = "CL21A226MAQNNNE"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "E_װ"; Value = "0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "F_ֵ()/ֵ(uF)"; Value = "22.0000000000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "G_ѹ"; Value = "25.00"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "H_"; Value = "20%"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "I_"; Value = "2"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "J_ƷƲ"; Value = "SAMSUNG()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805F226M100NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C 0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C67101"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "/Ԫ"; Value = "0.134"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ԭ"; Value = "SZLY"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ע"; Value = "ƬԪ"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+5 Pin=C14-1 +Added Pin To Net: NetName=GND Pin=C14-2 +Added Pin To Net: NetName=+3.3 Pin=C15-1 +Added Pin To Net: NetName=GND Pin=C15-2 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG new file mode 100644 index 0000000..6cc26c8 --- /dev/null +++ b/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG @@ -0,0 +1,18 @@ +Added Component: Designator=U?(1117) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Device"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Name"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Origin Footprint"; Value = "AMS117-3.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Symbol"; Value = "AMS117"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=U?-1 +Added Pin To Net: NetName=+3.3 Pin=U?-2 +Added Pin To Net: NetName=+5 Pin=U?-3 +Added Member To Class: ClassName=Sheet1 Member=Component U? AMS117 +Added Room: Name=Sheet1 diff --git a/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc b/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc new file mode 100644 index 0000000..572e032 --- /dev/null +++ b/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc @@ -0,0 +1,270 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\ʹʱģ\PCB1.PcbDoc +Date : 2022/6/30 +Time : 13:25:17 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad C1-2(147.677mm,60.3mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(141.275mm,50.436mm) on Top Layer And Pad C11-2(141.275mm,49.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Pad R1-1(147.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Via (147.93mm,59.487mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.209mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.209mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.166mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.166mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad C18-2(140.64mm,51.991mm) on Bottom Layer And Pad C19-2(140.64mm,50.752mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.236mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.771mm,49.436mm) on Top Layer And Pad C3-2(145.771mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (151.613mm,58.649mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.156mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(144.272mm,49.436mm) on Top Layer And Pad C5-2(144.272mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(143.264mm,60.655mm) on Top Layer And Pad C8-2(144.264mm,60.655mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad P2-2(141.224mm,58.547mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.149mm < 0.254mm) Between Pad P2-3(141.224mm,61.087mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.149mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(147.694mm,61.214mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Pad R2-2(150.343mm,50.995mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.186mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad R2-2(150.343mm,50.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.222mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(176.352mm,57.904mm) on Bottom Layer And Pad R3-2(176.352mm,56.904mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad R6-2(160.325mm,51.918mm) on Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.124mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (148.107mm,51.486mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.124mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.113mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.113mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.234mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.191mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.616mm,56.972mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.191mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.185mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (157.353mm,56.007mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.185mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-2(147.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-11(147.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.749mm) on Top Layer And Pad U1-12(147.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Pad U1-13(146.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Pad U1-14(146.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Pad U1-15(145.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.173mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.173mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Pad U1-16(145.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Pad U1-17(144.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.176mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.999mm) on Top Layer And Pad U1-18(144.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.999mm) on Top Layer And Pad U1-19(143.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.999mm) on Top Layer And Pad U1-20(143.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,53.249mm) on Top Layer And Pad U1-3(147.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.999mm) on Top Layer And Pad U1-21(142.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Pad U1-22(142.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.187mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.187mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Pad U1-23(141.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.121mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.121mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Pad U1-24(141.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.186mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Pad U1-25(140.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Pad U1-26(140.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.749mm) on Top Layer And Pad U1-27(140.518mm,57.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,57.249mm) on Top Layer And Pad U1-28(140.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.749mm) on Top Layer And Pad U1-29(140.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,56.249mm) on Top Layer And Pad U1-30(140.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Pad U1-4(147.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.749mm) on Top Layer And Pad U1-31(140.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,55.249mm) on Top Layer And Pad U1-32(140.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.749mm) on Top Layer And Pad U1-33(140.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,54.249mm) on Top Layer And Pad U1-34(140.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.749mm) on Top Layer And Pad U1-35(140.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,53.249mm) on Top Layer And Pad U1-36(140.518mm,52.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Pad U1-37(141.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Pad U1-38(141.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.225mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.225mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Pad U1-39(142.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Pad U1-40(142.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.136mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.136mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Pad U1-5(147.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.999mm) on Top Layer And Pad U1-41(143.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.999mm) on Top Layer And Pad U1-42(143.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.999mm) on Top Layer And Pad U1-43(144.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.999mm) on Top Layer And Pad U1-44(144.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.999mm) on Top Layer And Pad U1-45(145.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.999mm) on Top Layer And Pad U1-46(145.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Pad U1-47(146.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.081mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.088mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.088mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.091mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.091mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.087mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.087mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.749mm) on Top Layer And Pad U1-6(147.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,55.249mm) on Top Layer And Pad U1-7(147.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.749mm) on Top Layer And Pad U1-8(147.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,56.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.143mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Via (171.45mm,52.984mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.143mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Pad U4-2(164.367mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-2(164.367mm,53.726mm) on Bottom Layer And Pad U4-3(165.317mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-3(165.317mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.195mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.195mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Via (166.827mm,52.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (148.107mm,51.486mm) from Top Layer to Bottom Layer And Via (148.742mm,50.876mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (148.742mm,50.876mm) from Top Layer to Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.162mm < 0.254mm) Between Via (156.616mm,56.972mm) from Top Layer to Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.162mm] / [Bottom Solder] Mask Sliver [0.162mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (157.353mm,56.007mm) from Top Layer to Bottom Layer And Via (158.064mm,55.423mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (158.818mm,52.9mm) from Top Layer to Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Via (166.827mm,52.248mm) from Top Layer to Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] / [Bottom Solder] Mask Sliver [0.253mm] +Rule Violations :106 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.922mm) on Bottom Overlay And Pad U5-1(143.739mm,52.654mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.749mm) on Top Overlay And Pad U1-1(147.518mm,52.749mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.699mm,53.878mm) on Bottom Overlay And Pad U4-1(163.417mm,53.726mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.164mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.164mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(166.903mm,58.714mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(166.903mm,60.514mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.228mm < 0.254mm) Between Pad C18-1(140.64mm,53.391mm) on Bottom Layer And Text "TX" (142.392mm,54.356mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.228mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Text "+" (175.336mm,51.206mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,54.764mm)(176.787mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (176.787mm,51.425mm)(180.487mm,51.425mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (176.787mm,55.703mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,49.345mm)(148.163mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,51.112mm)(148.163mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,49.345mm)(144.011mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,51.112mm)(144.011mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,58.685mm)(175.687mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,61.838mm)(175.687mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,58.685mm)(179.839mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-1(164.166mm,60.745mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-2(164.166mm,58.445mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (156.54mm,59.106mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (157.175mm,51.994mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (159.96mm,55.119mm)(159.96mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Track (147.594mm,51.923mm)(147.594mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Track (147.594mm,58.58mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Track (147.098mm,59.075mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Track (140.442mm,59.075mm)(140.938mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Track (140.442mm,58.58mm)(140.442mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Track (140.442mm,51.923mm)(140.442mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Track (140.442mm,51.923mm)(140.938mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.999mm) on Top Layer And Track (147.098mm,51.923mm)(147.594mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(173.801mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.076mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.076mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(171.501mm,60.528mm) on Bottom Layer And Track (168.1mm,59.067mm)(174.902mm,59.067mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U4-4(165.317mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U4-5(163.417mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-1(143.739mm,52.654mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-10(149.484mm,60.274mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-11(149.484mm,59.004mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-12(149.484mm,57.734mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-13(149.484mm,56.464mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-14(149.484mm,55.194mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-15(149.484mm,53.924mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-16(149.484mm,52.654mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-2(143.739mm,53.924mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-3(143.739mm,55.194mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-8(143.739mm,61.544mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-9(149.484mm,61.544mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Track (151.486mm,50.597mm)(151.486mm,53.384mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Via (151.486mm,50.597mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0.196mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (150.038mm,61.544mm)(150.52mm,61.062mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (151.13mm,59.995mm)(151.917mm,59.995mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (150.038mm,61.544mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.225mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (151.13mm,59.995mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] +Rule Violations :110 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Text "+" (175.336mm,51.206mm) on Bottom Overlay And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay Silk Text to Silk Clearance [0.195mm] + Violation between Silk To Silk Clearance Constraint: (0.07mm < 0.254mm) Between Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay And Track (142.494mm,54.737mm)(142.494mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.07mm] + Violation between Silk To Silk Clearance Constraint: (0.129mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (175.687mm,61.838mm)(179.839mm,61.838mm) on Bottom Overlay Silk Text to Silk Clearance [0.129mm] + Violation between Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm] + Violation between Silk To Silk Clearance Constraint: (0.206mm < 0.254mm) Between Text "TX" (142.392mm,54.356mm) on Bottom Overlay And Track (139.954mm,54.737mm)(142.494mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.206mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (168.605mm,51.867mm) on Bottom Overlay And Track (165.918mm,51.677mm)(165.918mm,53.479mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] +Rule Violations :6 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 222 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html b/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html new file mode 100644 index 0000000..7c3d65d --- /dev/null +++ b/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html @@ -0,0 +1,1002 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/6/30
Time:13:25:17
Elapsed Time:00:00:01
Filename:C:\Users\hu123456\Desktop\ʹʱģ\PCB1.PcbDoc
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Warnings:0
Rule Violations:222
+

Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)106
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)110
Silk to Silk (Clearance=0.254mm) (All),(All)6
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total222

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad C1-2(147.677mm,60.3mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(141.275mm,50.436mm) on Top Layer And Pad C11-2(141.275mm,49.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Pad R1-1(147.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Via (147.93mm,59.487mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm]
Minimum Solder Mask Sliver Constraint: (0.209mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.209mm]
Minimum Solder Mask Sliver Constraint: (0.166mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.166mm]
Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad C18-2(140.64mm,51.991mm) on Bottom Layer And Pad C19-2(140.64mm,50.752mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.236mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.771mm,49.436mm) on Top Layer And Pad C3-2(145.771mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (151.613mm,58.649mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.156mm]
Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(144.272mm,49.436mm) on Top Layer And Pad C5-2(144.272mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(143.264mm,60.655mm) on Top Layer And Pad C8-2(144.264mm,60.655mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad P2-2(141.224mm,58.547mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm]
Minimum Solder Mask Sliver Constraint: (0.149mm < 0.254mm) Between Pad P2-3(141.224mm,61.087mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.149mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(147.694mm,61.214mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Pad R2-2(150.343mm,50.995mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.186mm]
Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad R2-2(150.343mm,50.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.222mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(176.352mm,57.904mm) on Bottom Layer And Pad R3-2(176.352mm,56.904mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad R6-2(160.325mm,51.918mm) on Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.124mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (148.107mm,51.486mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.124mm]
Minimum Solder Mask Sliver Constraint: (0.113mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.113mm]
Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.234mm]
Minimum Solder Mask Sliver Constraint: (0.191mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.616mm,56.972mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.191mm]
Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm]
Minimum Solder Mask Sliver Constraint: (0.185mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (157.353mm,56.007mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.185mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-2(147.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-11(147.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.749mm) on Top Layer And Pad U1-12(147.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Pad U1-13(146.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Pad U1-14(146.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Pad U1-15(145.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.173mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.173mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Pad U1-16(145.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Pad U1-17(144.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.176mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.999mm) on Top Layer And Pad U1-18(144.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.999mm) on Top Layer And Pad U1-19(143.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.999mm) on Top Layer And Pad U1-20(143.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,53.249mm) on Top Layer And Pad U1-3(147.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.999mm) on Top Layer And Pad U1-21(142.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Pad U1-22(142.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.187mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.187mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Pad U1-23(141.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.121mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.121mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Pad U1-24(141.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.186mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Pad U1-25(140.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Pad U1-26(140.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.749mm) on Top Layer And Pad U1-27(140.518mm,57.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,57.249mm) on Top Layer And Pad U1-28(140.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.749mm) on Top Layer And Pad U1-29(140.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,56.249mm) on Top Layer And Pad U1-30(140.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Pad U1-4(147.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.749mm) on Top Layer And Pad U1-31(140.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,55.249mm) on Top Layer And Pad U1-32(140.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.749mm) on Top Layer And Pad U1-33(140.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,54.249mm) on Top Layer And Pad U1-34(140.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.749mm) on Top Layer And Pad U1-35(140.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,53.249mm) on Top Layer And Pad U1-36(140.518mm,52.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Pad U1-37(141.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Pad U1-38(141.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.225mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.225mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Pad U1-39(142.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Pad U1-40(142.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.136mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.136mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Pad U1-5(147.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.999mm) on Top Layer And Pad U1-41(143.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.999mm) on Top Layer And Pad U1-42(143.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.999mm) on Top Layer And Pad U1-43(144.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.999mm) on Top Layer And Pad U1-44(144.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.999mm) on Top Layer And Pad U1-45(145.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.999mm) on Top Layer And Pad U1-46(145.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Pad U1-47(146.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.081mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.088mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.088mm]
Minimum Solder Mask Sliver Constraint: (0.091mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.091mm]
Minimum Solder Mask Sliver Constraint: (0.087mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.087mm]
Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.749mm) on Top Layer And Pad U1-6(147.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,55.249mm) on Top Layer And Pad U1-7(147.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.749mm) on Top Layer And Pad U1-8(147.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,56.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.143mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Via (171.45mm,52.984mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.143mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Pad U4-2(164.367mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-2(164.367mm,53.726mm) on Bottom Layer And Pad U4-3(165.317mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-3(165.317mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.195mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.195mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Via (166.827mm,52.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (148.107mm,51.486mm) from Top Layer to Bottom Layer And Via (148.742mm,50.876mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (148.742mm,50.876mm) from Top Layer to Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm]
Minimum Solder Mask Sliver Constraint: (0.162mm < 0.254mm) Between Via (156.616mm,56.972mm) from Top Layer to Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.162mm] / [Bottom Solder] Mask Sliver [0.162mm]
Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (157.353mm,56.007mm) from Top Layer to Bottom Layer And Via (158.064mm,55.423mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm]
Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (158.818mm,52.9mm) from Top Layer to Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Via (166.827mm,52.248mm) from Top Layer to Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] / [Bottom Solder] Mask Sliver [0.253mm]
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.922mm) on Bottom Overlay And Pad U5-1(143.739mm,52.654mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.749mm) on Top Overlay And Pad U1-1(147.518mm,52.749mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.699mm,53.878mm) on Bottom Overlay And Pad U4-1(163.417mm,53.726mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.164mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.164mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(166.903mm,58.714mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(166.903mm,60.514mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.228mm < 0.254mm) Between Pad C18-1(140.64mm,53.391mm) on Bottom Layer And Text "TX" (142.392mm,54.356mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.228mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Text "+" (175.336mm,51.206mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,54.764mm)(176.787mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (176.787mm,51.425mm)(180.487mm,51.425mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm]
Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (176.787mm,55.703mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,49.345mm)(148.163mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,51.112mm)(148.163mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,49.345mm)(144.011mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,51.112mm)(144.011mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,58.685mm)(175.687mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,61.838mm)(175.687mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,58.685mm)(179.839mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-1(164.166mm,60.745mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-2(164.166mm,58.445mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (156.54mm,59.106mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (157.175mm,51.994mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (159.96mm,55.119mm)(159.96mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Track (147.594mm,51.923mm)(147.594mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Track (147.594mm,58.58mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Track (147.098mm,59.075mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Track (140.442mm,59.075mm)(140.938mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Track (140.442mm,58.58mm)(140.442mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Track (140.442mm,51.923mm)(140.442mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Track (140.442mm,51.923mm)(140.938mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.999mm) on Top Layer And Track (147.098mm,51.923mm)(147.594mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(173.801mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.076mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.076mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(171.501mm,60.528mm) on Bottom Layer And Track (168.1mm,59.067mm)(174.902mm,59.067mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U4-4(165.317mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U4-5(163.417mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-1(143.739mm,52.654mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-10(149.484mm,60.274mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-11(149.484mm,59.004mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-12(149.484mm,57.734mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-13(149.484mm,56.464mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-14(149.484mm,55.194mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-15(149.484mm,53.924mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-16(149.484mm,52.654mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-2(143.739mm,53.924mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-3(143.739mm,55.194mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-8(143.739mm,61.544mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-9(149.484mm,61.544mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Track (151.486mm,50.597mm)(151.486mm,53.384mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Via (151.486mm,50.597mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0.196mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (150.038mm,61.544mm)(150.52mm,61.062mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (151.13mm,59.995mm)(151.917mm,59.995mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (150.038mm,61.544mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.225mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (151.13mm,59.995mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Text "+" (175.336mm,51.206mm) on Bottom Overlay And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay Silk Text to Silk Clearance [0.195mm]
Silk To Silk Clearance Constraint: (0.07mm < 0.254mm) Between Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay And Track (142.494mm,54.737mm)(142.494mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.07mm]
Silk To Silk Clearance Constraint: (0.129mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (175.687mm,61.838mm)(179.839mm,61.838mm) on Bottom Overlay Silk Text to Silk Clearance [0.129mm]
Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm]
Silk To Silk Clearance Constraint: (0.206mm < 0.254mm) Between Text "TX" (142.392mm,54.356mm) on Bottom Overlay And Track (139.954mm,54.737mm)(142.494mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.206mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (168.605mm,51.867mm) on Bottom Overlay And Track (165.918mm,51.677mm)(165.918mm,53.479mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
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+ diff --git a/使用时间监测模块/Project Outputs for PCB_Project2/Status Report.Txt b/使用时间监测模块/Project Outputs for PCB_Project2/Status Report.Txt new file mode 100644 index 0000000..3c2eb06 --- /dev/null +++ b/使用时间监测模块/Project Outputs for PCB_Project2/Status Report.Txt @@ -0,0 +1,9 @@ +Output: Bill of Materials +Type : BOM +From : Variant [[No Variations]] of Project [PCB_Project2.PrjPCB] + + +Files Generated : 0 +Documents Printed : 0 + +Finished Output Generation At 15:00:08 On 2022/5/7 diff --git a/使用时间监测模块/SW.PcbLib b/使用时间监测模块/SW.PcbLib new file mode 100644 index 0000000..8fd0f1e Binary files /dev/null and b/使用时间监测模块/SW.PcbLib differ diff --git a/使用时间监测模块/Sheet1.SchDoc b/使用时间监测模块/Sheet1.SchDoc new file mode 100644 index 0000000..d03afd3 Binary files /dev/null and b/使用时间监测模块/Sheet1.SchDoc differ diff --git a/使用时间监测模块/TLV62568A.PcbLib b/使用时间监测模块/TLV62568A.PcbLib new file mode 100644 index 0000000..f880bd8 Binary files /dev/null and b/使用时间监测模块/TLV62568A.PcbLib differ diff --git a/使用时间监测模块/TLV62568A.SchLib b/使用时间监测模块/TLV62568A.SchLib new file mode 100644 index 0000000..ac8ff54 Binary files /dev/null and b/使用时间监测模块/TLV62568A.SchLib differ diff --git a/使用时间监测模块/XAL4020-102ME.PcbLib b/使用时间监测模块/XAL4020-102ME.PcbLib new file mode 100644 index 0000000..836c447 Binary files /dev/null and b/使用时间监测模块/XAL4020-102ME.PcbLib differ diff --git a/使用时间监测模块/debug.log b/使用时间监测模块/debug.log new file mode 100644 index 0000000..e69de29 diff --git a/使用时间监测模块/esp32-picp-d4.PcbLib b/使用时间监测模块/esp32-picp-d4.PcbLib new file mode 100644 index 0000000..385211a Binary files /dev/null and b/使用时间监测模块/esp32-picp-d4.PcbLib differ diff --git a/使用时间监测模块/s8550.PcbLib b/使用时间监测模块/s8550.PcbLib new file mode 100644 index 0000000..218823e Binary files /dev/null and b/使用时间监测模块/s8550.PcbLib differ diff --git a/使用时间监测模块/使用时间检测22.6.30.rar b/使用时间监测模块/使用时间检测22.6.30.rar new file mode 100644 index 0000000..6a261a8 Binary files /dev/null and b/使用时间监测模块/使用时间检测22.6.30.rar differ diff --git a/光电二极管/pcb及原理图/AD7798.SchLib b/光电二极管/pcb及原理图/AD7798.SchLib new file mode 100644 index 0000000..b199188 Binary files /dev/null and b/光电二极管/pcb及原理图/AD7798.SchLib differ diff --git a/光电二极管/pcb及原理图/AD8500.SchLib b/光电二极管/pcb及原理图/AD8500.SchLib new file mode 100644 index 0000000..510ebee Binary files /dev/null and b/光电二极管/pcb及原理图/AD8500.SchLib differ diff --git a/光电二极管/pcb及原理图/AD8502.SchLib b/光电二极管/pcb及原理图/AD8502.SchLib new file mode 100644 index 0000000..1a5fa33 Binary files /dev/null and b/光电二极管/pcb及原理图/AD8502.SchLib differ diff --git a/光电二极管/pcb及原理图/ADR3433.SchLib b/光电二极管/pcb及原理图/ADR3433.SchLib new file mode 100644 index 0000000..cadec3e Binary files /dev/null and b/光电二极管/pcb及原理图/ADR3433.SchLib differ diff --git a/光电二极管/pcb及原理图/PCB1.PcbDoc b/光电二极管/pcb及原理图/PCB1.PcbDoc new file mode 100644 index 0000000..771e33b Binary files /dev/null and b/光电二极管/pcb及原理图/PCB1.PcbDoc differ diff --git a/光电二极管/pcb及原理图/PCB_Project1.PrjPCB b/光电二极管/pcb及原理图/PCB_Project1.PrjPCB new file mode 100644 index 0000000..d9f611b --- /dev/null +++ b/光电二极管/pcb及原理图/PCB_Project1.PrjPCB @@ -0,0 +1,1052 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=Sheet1.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=SJXALIYO + +[Document2] +DocumentPath=PCB1.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=UXEQSDIX + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + diff --git a/光电二极管/pcb及原理图/Sheet1.SchDoc b/光电二极管/pcb及原理图/Sheet1.SchDoc new file mode 100644 index 0000000..14fc42a Binary files /dev/null and b/光电二极管/pcb及原理图/Sheet1.SchDoc differ diff --git a/光电二极管/资料/FD11A-SpecSheet.pdf b/光电二极管/资料/FD11A-SpecSheet.pdf new file mode 100644 index 0000000..7587ce6 Binary files /dev/null and b/光电二极管/资料/FD11A-SpecSheet.pdf differ diff --git a/光电二极管/资料/ads8883.pdf b/光电二极管/资料/ads8883.pdf new file mode 100644 index 0000000..9f0652b Binary files /dev/null and b/光电二极管/资料/ads8883.pdf differ diff --git a/光电二极管/资料/ina181.pdf b/光电二极管/资料/ina181.pdf new file mode 100644 index 0000000..53823a5 Binary files /dev/null and b/光电二极管/资料/ina181.pdf differ diff --git a/光电二极管/资料/ref34-q1.pdf b/光电二极管/资料/ref34-q1.pdf new file mode 100644 index 0000000..7038595 Binary files /dev/null and b/光电二极管/资料/ref34-q1.pdf differ diff --git a/植物探头/使用时间监测模块/117.PcbLib b/植物探头/使用时间监测模块/117.PcbLib new file mode 100644 index 0000000..a67d1ec Binary files /dev/null and b/植物探头/使用时间监测模块/117.PcbLib differ diff --git a/植物探头/使用时间监测模块/ASM1117-3.3.PcbLib b/植物探头/使用时间监测模块/ASM1117-3.3.PcbLib new file mode 100644 index 0000000..10785fb Binary files /dev/null and b/植物探头/使用时间监测模块/ASM1117-3.3.PcbLib differ diff --git a/植物探头/使用时间监测模块/Design Rule Check - PCB1.drc b/植物探头/使用时间监测模块/Design Rule Check - PCB1.drc new file mode 100644 index 0000000..a3a1dab --- /dev/null +++ b/植物探头/使用时间监测模块/Design Rule Check - PCB1.drc @@ -0,0 +1,328 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\ֲ̽ͷ\ʹʱģ\PCB1.PcbDoc +Date : 2022/6/27 +Time : 9:56:40 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.159mm < 0.254mm) Between Pad BT1-1(158.293mm,60.173mm) on Bottom Layer And Via (158.242mm,57.81mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.159mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C10-1(147.447mm,49.952mm) on Bottom Layer And Pad C10-2(147.447mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(145.466mm,50.952mm) on Bottom Layer And Pad C1-2(145.466mm,49.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.085mm < 0.254mm) Between Pad C1-1(145.466mm,50.952mm) on Bottom Layer And Via (145.339mm,51.791mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.085mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(147.184mm,61.671mm) on Bottom Layer And Pad C11-2(148.184mm,61.671mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.212mm < 0.254mm) Between Pad C11-2(148.184mm,61.671mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.212mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad C14-1(173.7mm,58.522mm) on Bottom Layer And Via (172.415mm,58.699mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(152.171mm,56.726mm) on Bottom Layer And Pad C8-2(152.171mm,57.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C9-1(150.927mm,61.943mm) on Bottom Layer And Pad C9-2(150.927mm,60.943mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(146.456mm,49.952mm) on Bottom Layer And Pad R1-2(146.456mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(144.475mm,49.952mm) on Bottom Layer And Pad R2-2(144.475mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(179.638mm,60.35mm) on Top Layer And Pad R3-2(178.638mm,60.35mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Pad U1-2(150.541mm,59.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Pad U1-48(149.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(150.541mm,55.044mm) on Bottom Layer And Pad U1-11(150.541mm,54.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(150.541mm,55.044mm) on Bottom Layer And Pad U1-9(150.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(150.541mm,54.544mm) on Bottom Layer And Pad U1-12(150.541mm,54.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Pad U1-13(149.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Pad U1-14(149.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Pad U1-15(148.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(148.791mm,53.294mm) on Bottom Layer And Pad U1-16(148.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(148.29mm,53.294mm) on Bottom Layer And Pad U1-17(147.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Pad U1-18(147.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Pad U1-19(146.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.193mm < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Via (147.193mm,52.248mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.193mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Pad U1-20(146.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.216mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Via (147.193mm,52.248mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.216mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(150.541mm,59.044mm) on Bottom Layer And Pad U1-3(150.541mm,58.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Pad U1-21(145.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Pad U1-22(145.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Pad U1-23(144.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Pad U1-24(144.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.132mm < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.132mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Pad U1-25(143.541mm,54.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Pad U1-26(143.541mm,54.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(143.541mm,54.544mm) on Bottom Layer And Pad U1-27(143.541mm,55.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(143.541mm,55.044mm) on Bottom Layer And Pad U1-28(143.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(143.541mm,55.544mm) on Bottom Layer And Pad U1-29(143.541mm,56.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(143.541mm,56.044mm) on Bottom Layer And Pad U1-30(143.541mm,56.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(150.541mm,58.544mm) on Bottom Layer And Pad U1-4(150.541mm,58.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(143.541mm,56.544mm) on Bottom Layer And Pad U1-31(143.541mm,57.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(143.541mm,57.044mm) on Bottom Layer And Pad U1-32(143.541mm,57.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(143.541mm,57.544mm) on Bottom Layer And Pad U1-33(143.541mm,58.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.142mm < 0.254mm) Between Pad U1-32(143.541mm,57.544mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.142mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(143.541mm,58.044mm) on Bottom Layer And Pad U1-34(143.541mm,58.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.132mm < 0.254mm) Between Pad U1-33(143.541mm,58.044mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.132mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(143.541mm,58.544mm) on Bottom Layer And Pad U1-35(143.541mm,59.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-34(143.541mm,58.544mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.081mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(143.541mm,59.044mm) on Bottom Layer And Pad U1-36(143.541mm,59.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-35(143.541mm,59.044mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.081mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(143.541mm,59.544mm) on Bottom Layer And Pad U1-37(144.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(144.29mm,60.294mm) on Bottom Layer And Pad U1-38(144.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(144.791mm,60.294mm) on Bottom Layer And Pad U1-39(145.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(145.29mm,60.294mm) on Bottom Layer And Pad U1-40(145.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(150.541mm,58.044mm) on Bottom Layer And Pad U1-5(150.541mm,57.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(145.791mm,60.294mm) on Bottom Layer And Pad U1-41(146.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(146.29mm,60.294mm) on Bottom Layer And Pad U1-42(146.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(146.791mm,60.294mm) on Bottom Layer And Pad U1-43(147.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(147.29mm,60.294mm) on Bottom Layer And Pad U1-44(147.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(147.791mm,60.294mm) on Bottom Layer And Pad U1-45(148.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(148.29mm,60.294mm) on Bottom Layer And Pad U1-46(148.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(148.791mm,60.294mm) on Bottom Layer And Pad U1-47(149.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.206mm < 0.254mm) Between Pad U1-46(148.791mm,60.294mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.206mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Pad U1-48(149.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.193mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.193mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.112mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.061mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.061mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(150.541mm,57.544mm) on Bottom Layer And Pad U1-6(150.541mm,57.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(150.541mm,57.044mm) on Bottom Layer And Pad U1-7(150.541mm,56.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(150.541mm,56.544mm) on Bottom Layer And Pad U1-8(150.541mm,56.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(150.541mm,56.044mm) on Bottom Layer And Pad U1-9(150.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U2-1(170.586mm,54.345mm) on Bottom Layer And Via (169.85mm,55.499mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.176mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.157mm < 0.254mm) Between Pad U3-2(170.572mm,59.007mm) on Bottom Layer And Via (172.415mm,58.699mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.157mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad U3-3(170.572mm,56.707mm) on Bottom Layer And Via (169.85mm,55.499mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.229mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U3-4(164.857mm,59.007mm) on Bottom Layer And Via (162.941mm,58.064mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Via (155.55mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.1mm < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Via (156.794mm,52.07mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.1mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.234mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Via (154.94mm,61.493mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.222mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.122mm < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Via (162.916mm,51.968mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.122mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Via (162.916mm,51.968mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.061mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Via (167.03mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U6-1(162.128mm,59.282mm) on Bottom Layer And Pad U6-2(161.178mm,59.282mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.221mm < 0.254mm) Between Pad U6-1(162.128mm,59.282mm) on Bottom Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.221mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U6-2(161.178mm,59.282mm) on Bottom Layer And Pad U6-3(160.228mm,59.282mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad U6-3(160.228mm,59.282mm) on Bottom Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U7-1(152.063mm,61.498mm) on Bottom Layer And Pad U7-2(153.013mm,61.498mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Pad U7-3(153.963mm,61.498mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Via (152.063mm,61.498mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Via (153.963mm,61.498mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.227mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Via (153.01mm,59.08mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.227mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Via (153.01mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.229mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (144.475mm,58.801mm) from Top Layer to Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.084mm < 0.254mm) Between Via (153.01mm,59.08mm) from Top Layer to Bottom Layer And Via (153.01mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.084mm] / [Bottom Solder] Mask Sliver [0.084mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Via (154.356mm,53.289mm) from Top Layer to Bottom Layer And Via (154.94mm,52.705mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.123mm] / [Bottom Solder] Mask Sliver [0.123mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.059mm < 0.254mm) Between Via (154.559mm,52.045mm) from Top Layer to Bottom Layer And Via (154.94mm,52.705mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.059mm] / [Bottom Solder] Mask Sliver [0.059mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.074mm < 0.254mm) Between Via (154.94mm,52.705mm) from Top Layer to Bottom Layer And Via (155.55mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.074mm] / [Bottom Solder] Mask Sliver [0.074mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Via (156.794mm,52.07mm) from Top Layer to Bottom Layer And Via (157.378mm,52.654mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.123mm] / [Bottom Solder] Mask Sliver [0.123mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Via (158.445mm,53.365mm) from Top Layer to Bottom Layer And Via (159.258mm,53.391mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] / [Bottom Solder] Mask Sliver [0.11mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.044mm < 0.254mm) Between Via (159.258mm,53.391mm) from Top Layer to Bottom Layer And Via (159.385mm,54.127mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.044mm] / [Bottom Solder] Mask Sliver [0.044mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (161.036mm,56.185mm) from Top Layer to Bottom Layer And Via (161.696mm,56.82mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Via (162.179mm,54.864mm) from Top Layer to Bottom Layer And Via (162.204mm,54.051mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] / [Bottom Solder] Mask Sliver [0.11mm] +Rule Violations :104 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (146.842mm,48.976mm) on Top Overlay And Pad U4-1(146.842mm,49.708mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (151.18mm,59.544mm) on Bottom Overlay And Pad U1-1(150.541mm,59.544mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.09mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad C9-1(150.927mm,61.943mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.141mm < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad C9-2(150.927mm,60.943mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.141mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad U7-1(152.063mm,61.498mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (157.292mm,53.849mm) on Bottom Overlay And Pad BT1-1(158.293mm,60.173mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (157.292mm,53.849mm) on Bottom Overlay And Pad BT1-2(156.292mm,60.173mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.846mm,59.13mm) on Bottom Overlay And Pad U6-1(162.128mm,59.282mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.246mm < 0.254mm) Between Pad BT1-1(158.293mm,60.173mm) on Bottom Layer And Text "+" (158.969mm,59.818mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.246mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C?-1(149.022mm,49.381mm) on Bottom Layer And Track (148.422mm,50.281mm)(149.622mm,50.281mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C?-2(149.022mm,51.181mm) on Bottom Layer And Track (148.422mm,50.281mm)(149.622mm,50.281mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(173.609mm,50.8mm) on Bottom Layer And Track (173.009mm,51.7mm)(174.209mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(173.609mm,52.6mm) on Bottom Layer And Track (173.009mm,51.7mm)(174.209mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Text "+" (175.082mm,52.959mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (175.168mm,51.7mm)(176.368mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.196mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.196mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-2(175.768mm,50.8mm) on Bottom Layer And Track (175.168mm,51.7mm)(176.368mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-1(173.7mm,58.522mm) on Bottom Layer And Track (174.6mm,57.922mm)(174.6mm,59.122mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C14-2(175.5mm,58.522mm) on Bottom Layer And Text "-" (176.225mm,57.125mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-2(175.5mm,58.522mm) on Bottom Layer And Track (174.6mm,57.922mm)(174.6mm,59.122mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(173.7mm,60.655mm) on Bottom Layer And Track (174.6mm,60.055mm)(174.6mm,61.255mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(175.5mm,60.655mm) on Bottom Layer And Track (174.6mm,60.055mm)(174.6mm,61.255mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C9-1(150.927mm,61.943mm) on Bottom Layer And Text "U1" (151.075mm,61.564mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.195mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Text "U1" (151.075mm,61.564mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.195mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.203mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.203mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.209mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (151.462mm,59.449mm)(151.462mm,61.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.209mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,56.72mm)(176.736mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (176.736mm,57.659mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(140.818mm,61.747mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(140.818mm,59.207mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(140.818mm,56.667mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R?-1(151.181mm,49.356mm) on Bottom Layer And Track (150.581mm,50.256mm)(151.781mm,50.256mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R?-2(151.181mm,51.156mm) on Bottom Layer And Track (150.581mm,50.256mm)(151.781mm,50.256mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(141.224mm,49.581mm) on Bottom Layer And Track (139.648mm,49.54mm)(140.341mm,49.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(141.224mm,49.581mm) on Bottom Layer And Track (142.107mm,49.54mm)(142.8mm,49.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Track (139.648mm,53.692mm)(140.341mm,53.692mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Track (142.107mm,53.692mm)(142.8mm,53.692mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (177.532mm,57.587mm)(178.225mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (179.991mm,57.587mm)(180.684mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (177.532mm,53.434mm)(178.225mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (179.991mm,53.434mm)(180.684mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.067mm < 0.254mm) Between Pad U1-11(150.541mm,54.544mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.067mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Track (150.617mm,53.218mm)(150.617mm,53.714mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.211mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-15(148.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.185mm < 0.254mm) Between Pad U1-16(148.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.185mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.008mm < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.008mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.207mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-2(150.541mm,59.044mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.026mm < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.026mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.217mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.217mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.021mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.021mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.012mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.012mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.115mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.115mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.117mm < 0.254mm) Between Pad U1-3(150.541mm,58.544mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.117mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(143.541mm,59.544mm) on Bottom Layer And Track (143.464mm,59.875mm)(143.464mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-37(144.29mm,60.294mm) on Bottom Layer And Track (143.464mm,60.37mm)(143.96mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.21mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.227mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.227mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-48(149.791mm,60.294mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(149.791mm,60.294mm) on Bottom Layer And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(170.586mm,54.345mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(170.586mm,52.045mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(170.586mm,49.745mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(164.871mm,52.045mm) on Bottom Layer And Track (166.333mm,48.643mm)(166.333mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-1(170.572mm,61.307mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-2(170.572mm,59.007mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-3(170.572mm,56.707mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-4(164.857mm,59.007mm) on Bottom Layer And Track (166.319mm,55.605mm)(166.319mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-1(146.842mm,49.708mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-10(141.097mm,57.328mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-11(141.097mm,56.058mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-12(141.097mm,54.788mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-13(141.097mm,53.518mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-14(141.097mm,52.248mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-15(141.097mm,50.978mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-16(141.097mm,49.708mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-2(146.842mm,50.978mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-3(146.842mm,52.248mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-4(146.842mm,53.518mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-5(146.842mm,54.788mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-6(146.842mm,56.058mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-7(146.842mm,57.328mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-8(146.842mm,58.598mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-9(141.097mm,58.598mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.435mm,60.764mm) on Top Overlay And Track (152.063mm,61.498mm)(153.963mm,61.498mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.435mm,60.764mm) on Top Overlay And Via (152.063mm,61.498mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(174.295mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-11(159.055mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-11(159.055mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(159.055mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(159.055mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(169.215mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(169.215mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-7(169.215mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(169.215mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-8(166.675mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-8(166.675mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-9(164.135mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-9(164.135mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U6-4(160.228mm,61.577mm) on Bottom Layer And Track (160.723mm,61.331mm)(161.634mm,61.331mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U6-5(162.128mm,61.577mm) on Bottom Layer And Track (160.723mm,61.331mm)(161.634mm,61.331mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Track (152.558mm,59.449mm)(153.468mm,59.449mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] +Rule Violations :152 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.107mm < 0.254mm) Between Arc (151.18mm,59.544mm) on Bottom Overlay And Text "C8" (152.324mm,58.928mm) on Bottom Overlay Silk Text to Silk Clearance [0.107mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Text "U1" (151.075mm,61.564mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "+" (158.969mm,59.818mm) on Bottom Overlay And Track (159.627mm,59.529mm)(159.627mm,61.331mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "BT1" (161.864mm,62.79mm) on Bottom Overlay And Text "U6" (162.887mm,62.97mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Text "C10" (147.599mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Text "R?" (151.917mm,52.821mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.159mm < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0.159mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Text "C10" (147.599mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Text "R1" (146.609mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.173mm < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.173mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Text "R1" (146.609mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.123mm < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.123mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C11" (148.369mm,62.84mm) on Bottom Overlay And Text "C9" (151.079mm,63.144mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (151.462mm,59.449mm)(151.462mm,61.252mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.031mm < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (152.558mm,59.449mm)(153.468mm,59.449mm) on Bottom Overlay Silk Text to Silk Clearance [0.031mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C9" (151.079mm,63.144mm) on Bottom Overlay And Text "U1" (151.075mm,61.564mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.057mm < 0.254mm) Between Text "R?" (151.917mm,52.821mm) on Bottom Overlay And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0.057mm] + Violation between Silk To Silk Clearance Constraint: (0.082mm < 0.254mm) Between Text "R?" (151.917mm,52.821mm) on Bottom Overlay And Track (150.617mm,53.218mm)(150.617mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.082mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.648mm,49.54mm)(139.648mm,53.692mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.648mm,53.692mm)(140.341mm,53.692mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] +Rule Violations :24 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 280 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/植物探头/使用时间监测模块/Design Rule Check - PCB1.html b/植物探头/使用时间监测模块/Design Rule Check - PCB1.html new file mode 100644 index 0000000..b225ee7 --- /dev/null +++ b/植物探头/使用时间监测模块/Design Rule Check - PCB1.html @@ -0,0 +1,1176 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/6/27
Time:9:56:40
Elapsed Time:00:00:01
Filename:C:\Users\hu123456\Desktop\ֲ̽ͷ\ʹʱģ\PCB1.PcbDoc
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Warnings:0
Rule Violations:280
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Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)104
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)152
Silk to Silk (Clearance=0.254mm) (All),(All)24
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total280

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.159mm < 0.254mm) Between Pad BT1-1(158.293mm,60.173mm) on Bottom Layer And Via (158.242mm,57.81mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.159mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C10-1(147.447mm,49.952mm) on Bottom Layer And Pad C10-2(147.447mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(145.466mm,50.952mm) on Bottom Layer And Pad C1-2(145.466mm,49.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.085mm < 0.254mm) Between Pad C1-1(145.466mm,50.952mm) on Bottom Layer And Via (145.339mm,51.791mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.085mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(147.184mm,61.671mm) on Bottom Layer And Pad C11-2(148.184mm,61.671mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.212mm < 0.254mm) Between Pad C11-2(148.184mm,61.671mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.212mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad C14-1(173.7mm,58.522mm) on Bottom Layer And Via (172.415mm,58.699mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(152.171mm,56.726mm) on Bottom Layer And Pad C8-2(152.171mm,57.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C9-1(150.927mm,61.943mm) on Bottom Layer And Pad C9-2(150.927mm,60.943mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(146.456mm,49.952mm) on Bottom Layer And Pad R1-2(146.456mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(144.475mm,49.952mm) on Bottom Layer And Pad R2-2(144.475mm,50.952mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(179.638mm,60.35mm) on Top Layer And Pad R3-2(178.638mm,60.35mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Pad U1-2(150.541mm,59.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Pad U1-48(149.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(150.541mm,55.044mm) on Bottom Layer And Pad U1-11(150.541mm,54.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(150.541mm,55.044mm) on Bottom Layer And Pad U1-9(150.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(150.541mm,54.544mm) on Bottom Layer And Pad U1-12(150.541mm,54.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Pad U1-13(149.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Pad U1-14(149.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Pad U1-15(148.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(148.791mm,53.294mm) on Bottom Layer And Pad U1-16(148.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(148.29mm,53.294mm) on Bottom Layer And Pad U1-17(147.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Pad U1-18(147.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Pad U1-19(146.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.193mm < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Via (147.193mm,52.248mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.193mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Pad U1-20(146.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.216mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Via (147.193mm,52.248mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.216mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(150.541mm,59.044mm) on Bottom Layer And Pad U1-3(150.541mm,58.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Pad U1-21(145.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Pad U1-22(145.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Pad U1-23(144.791mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Pad U1-24(144.29mm,53.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.132mm < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.132mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Pad U1-25(143.541mm,54.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Pad U1-26(143.541mm,54.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(143.541mm,54.544mm) on Bottom Layer And Pad U1-27(143.541mm,55.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(143.541mm,55.044mm) on Bottom Layer And Pad U1-28(143.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(143.541mm,55.544mm) on Bottom Layer And Pad U1-29(143.541mm,56.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(143.541mm,56.044mm) on Bottom Layer And Pad U1-30(143.541mm,56.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(150.541mm,58.544mm) on Bottom Layer And Pad U1-4(150.541mm,58.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(143.541mm,56.544mm) on Bottom Layer And Pad U1-31(143.541mm,57.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(143.541mm,57.044mm) on Bottom Layer And Pad U1-32(143.541mm,57.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(143.541mm,57.544mm) on Bottom Layer And Pad U1-33(143.541mm,58.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.142mm < 0.254mm) Between Pad U1-32(143.541mm,57.544mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.142mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(143.541mm,58.044mm) on Bottom Layer And Pad U1-34(143.541mm,58.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.132mm < 0.254mm) Between Pad U1-33(143.541mm,58.044mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.132mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(143.541mm,58.544mm) on Bottom Layer And Pad U1-35(143.541mm,59.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-34(143.541mm,58.544mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.081mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(143.541mm,59.044mm) on Bottom Layer And Pad U1-36(143.541mm,59.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-35(143.541mm,59.044mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.081mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(143.541mm,59.544mm) on Bottom Layer And Pad U1-37(144.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(144.29mm,60.294mm) on Bottom Layer And Pad U1-38(144.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(144.791mm,60.294mm) on Bottom Layer And Pad U1-39(145.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(145.29mm,60.294mm) on Bottom Layer And Pad U1-40(145.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(150.541mm,58.044mm) on Bottom Layer And Pad U1-5(150.541mm,57.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(145.791mm,60.294mm) on Bottom Layer And Pad U1-41(146.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(146.29mm,60.294mm) on Bottom Layer And Pad U1-42(146.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(146.791mm,60.294mm) on Bottom Layer And Pad U1-43(147.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(147.29mm,60.294mm) on Bottom Layer And Pad U1-44(147.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(147.791mm,60.294mm) on Bottom Layer And Pad U1-45(148.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(148.29mm,60.294mm) on Bottom Layer And Pad U1-46(148.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(148.791mm,60.294mm) on Bottom Layer And Pad U1-47(149.29mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.206mm < 0.254mm) Between Pad U1-46(148.791mm,60.294mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.206mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Pad U1-48(149.791mm,60.294mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.193mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Via (149.149mm,61.341mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.193mm]
Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.475mm,58.801mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.112mm]
Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.061mm]
Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U1-49(147.041mm,56.794mm) on Bottom Layer And Via (144.958mm,54.28mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.061mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(150.541mm,57.544mm) on Bottom Layer And Pad U1-6(150.541mm,57.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(150.541mm,57.044mm) on Bottom Layer And Pad U1-7(150.541mm,56.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(150.541mm,56.544mm) on Bottom Layer And Pad U1-8(150.541mm,56.044mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(150.541mm,56.044mm) on Bottom Layer And Pad U1-9(150.541mm,55.544mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U2-1(170.586mm,54.345mm) on Bottom Layer And Via (169.85mm,55.499mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.176mm]
Minimum Solder Mask Sliver Constraint: (0.157mm < 0.254mm) Between Pad U3-2(170.572mm,59.007mm) on Bottom Layer And Via (172.415mm,58.699mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.157mm]
Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad U3-3(170.572mm,56.707mm) on Bottom Layer And Via (169.85mm,55.499mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.229mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U3-4(164.857mm,59.007mm) on Bottom Layer And Via (162.941mm,58.064mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Via (155.55mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.1mm < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Via (156.794mm,52.07mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.1mm]
Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.234mm]
Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Via (154.94mm,61.493mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.222mm]
Minimum Solder Mask Sliver Constraint: (0.122mm < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Via (162.916mm,51.968mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.122mm]
Minimum Solder Mask Sliver Constraint: (0.061mm < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Via (162.916mm,51.968mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.061mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Via (167.03mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U6-1(162.128mm,59.282mm) on Bottom Layer And Pad U6-2(161.178mm,59.282mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.221mm < 0.254mm) Between Pad U6-1(162.128mm,59.282mm) on Bottom Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.221mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U6-2(161.178mm,59.282mm) on Bottom Layer And Pad U6-3(160.228mm,59.282mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad U6-3(160.228mm,59.282mm) on Bottom Layer And Via (161.188mm,58.826mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U7-1(152.063mm,61.498mm) on Bottom Layer And Pad U7-2(153.013mm,61.498mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Pad U7-3(153.963mm,61.498mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Via (152.063mm,61.498mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U7-2(153.013mm,61.498mm) on Bottom Layer And Via (153.963mm,61.498mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.227mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Via (153.01mm,59.08mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.227mm]
Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Via (153.01mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.229mm]
Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (144.475mm,58.801mm) from Top Layer to Bottom Layer And Via (144.526mm,57.887mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]
Minimum Solder Mask Sliver Constraint: (0.084mm < 0.254mm) Between Via (153.01mm,59.08mm) from Top Layer to Bottom Layer And Via (153.01mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.084mm] / [Bottom Solder] Mask Sliver [0.084mm]
Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Via (154.356mm,53.289mm) from Top Layer to Bottom Layer And Via (154.94mm,52.705mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.123mm] / [Bottom Solder] Mask Sliver [0.123mm]
Minimum Solder Mask Sliver Constraint: (0.059mm < 0.254mm) Between Via (154.559mm,52.045mm) from Top Layer to Bottom Layer And Via (154.94mm,52.705mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.059mm] / [Bottom Solder] Mask Sliver [0.059mm]
Minimum Solder Mask Sliver Constraint: (0.074mm < 0.254mm) Between Via (154.94mm,52.705mm) from Top Layer to Bottom Layer And Via (155.55mm,52.222mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.074mm] / [Bottom Solder] Mask Sliver [0.074mm]
Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Via (156.794mm,52.07mm) from Top Layer to Bottom Layer And Via (157.378mm,52.654mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.123mm] / [Bottom Solder] Mask Sliver [0.123mm]
Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Via (158.445mm,53.365mm) from Top Layer to Bottom Layer And Via (159.258mm,53.391mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] / [Bottom Solder] Mask Sliver [0.11mm]
Minimum Solder Mask Sliver Constraint: (0.044mm < 0.254mm) Between Via (159.258mm,53.391mm) from Top Layer to Bottom Layer And Via (159.385mm,54.127mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.044mm] / [Bottom Solder] Mask Sliver [0.044mm]
Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (161.036mm,56.185mm) from Top Layer to Bottom Layer And Via (161.696mm,56.82mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]
Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Via (162.179mm,54.864mm) from Top Layer to Bottom Layer And Via (162.204mm,54.051mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] / [Bottom Solder] Mask Sliver [0.11mm]
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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (146.842mm,48.976mm) on Top Overlay And Pad U4-1(146.842mm,49.708mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (151.18mm,59.544mm) on Bottom Overlay And Pad U1-1(150.541mm,59.544mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.09mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad C9-1(150.927mm,61.943mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.141mm < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad C9-2(150.927mm,60.943mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.141mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Pad U7-1(152.063mm,61.498mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (157.292mm,53.849mm) on Bottom Overlay And Pad BT1-1(158.293mm,60.173mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (157.292mm,53.849mm) on Bottom Overlay And Pad BT1-2(156.292mm,60.173mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.846mm,59.13mm) on Bottom Overlay And Pad U6-1(162.128mm,59.282mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.246mm < 0.254mm) Between Pad BT1-1(158.293mm,60.173mm) on Bottom Layer And Text "+" (158.969mm,59.818mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.246mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C?-1(149.022mm,49.381mm) on Bottom Layer And Track (148.422mm,50.281mm)(149.622mm,50.281mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C?-2(149.022mm,51.181mm) on Bottom Layer And Track (148.422mm,50.281mm)(149.622mm,50.281mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(173.609mm,50.8mm) on Bottom Layer And Track (173.009mm,51.7mm)(174.209mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(173.609mm,52.6mm) on Bottom Layer And Track (173.009mm,51.7mm)(174.209mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Text "+" (175.082mm,52.959mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (175.168mm,51.7mm)(176.368mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.196mm]
Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad C13-1(175.768mm,52.6mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.196mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-2(175.768mm,50.8mm) on Bottom Layer And Track (175.168mm,51.7mm)(176.368mm,51.7mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-1(173.7mm,58.522mm) on Bottom Layer And Track (174.6mm,57.922mm)(174.6mm,59.122mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C14-2(175.5mm,58.522mm) on Bottom Layer And Text "-" (176.225mm,57.125mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-2(175.5mm,58.522mm) on Bottom Layer And Track (174.6mm,57.922mm)(174.6mm,59.122mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(173.7mm,60.655mm) on Bottom Layer And Track (174.6mm,60.055mm)(174.6mm,61.255mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(175.5mm,60.655mm) on Bottom Layer And Track (174.6mm,60.055mm)(174.6mm,61.255mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C9-1(150.927mm,61.943mm) on Bottom Layer And Text "U1" (151.075mm,61.564mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.195mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Text "U1" (151.075mm,61.564mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.195mm]
Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.203mm]
Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.203mm]
Silk To Solder Mask Clearance Constraint: (0.209mm < 0.254mm) Between Pad C9-2(150.927mm,60.943mm) on Bottom Layer And Track (151.462mm,59.449mm)(151.462mm,61.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.209mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,56.72mm)(176.736mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm]
Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (176.736mm,57.659mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(140.818mm,61.747mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(140.818mm,59.207mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(140.818mm,56.667mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R?-1(151.181mm,49.356mm) on Bottom Layer And Track (150.581mm,50.256mm)(151.781mm,50.256mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R?-2(151.181mm,51.156mm) on Bottom Layer And Track (150.581mm,50.256mm)(151.781mm,50.256mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(141.224mm,49.581mm) on Bottom Layer And Track (139.648mm,49.54mm)(140.341mm,49.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(141.224mm,49.581mm) on Bottom Layer And Track (142.107mm,49.54mm)(142.8mm,49.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Track (139.648mm,53.692mm)(140.341mm,53.692mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(141.224mm,53.651mm) on Bottom Layer And Track (142.107mm,53.692mm)(142.8mm,53.692mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (177.532mm,57.587mm)(178.225mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (179.991mm,57.587mm)(180.684mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (177.532mm,53.434mm)(178.225mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (179.991mm,53.434mm)(180.684mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-1(150.541mm,59.544mm) on Bottom Layer And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.067mm < 0.254mm) Between Pad U1-11(150.541mm,54.544mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.067mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-12(150.541mm,54.044mm) on Bottom Layer And Track (150.617mm,53.218mm)(150.617mm,53.714mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.211mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(149.791mm,53.294mm) on Bottom Layer And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-14(149.29mm,53.294mm) on Bottom Layer And Text "R?" (151.917mm,52.821mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-15(148.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.185mm < 0.254mm) Between Pad U1-16(148.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.185mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.008mm < 0.254mm) Between Pad U1-17(147.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.008mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-18(147.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "C?" (149.758mm,52.846mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.207mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-19(146.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-2(150.541mm,59.044mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.026mm < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.026mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-20(146.29mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-21(145.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.217mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.217mm]
Silk To Solder Mask Clearance Constraint: (0.021mm < 0.254mm) Between Pad U1-22(145.29mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.021mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-23(144.791mm,53.294mm) on Bottom Layer And Text "R1" (146.609mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.012mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.012mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-24(144.29mm,53.294mm) on Bottom Layer And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Text "C1" (145.618mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.115mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Text "C10" (147.599mm,52.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.115mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(143.541mm,54.044mm) on Bottom Layer And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.117mm < 0.254mm) Between Pad U1-3(150.541mm,58.544mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.117mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(143.541mm,59.544mm) on Bottom Layer And Track (143.464mm,59.875mm)(143.464mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-37(144.29mm,60.294mm) on Bottom Layer And Track (143.464mm,60.37mm)(143.96mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.21mm]
Silk To Solder Mask Clearance Constraint: (0.227mm < 0.254mm) Between Pad U1-47(149.29mm,60.294mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.227mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U1-48(149.791mm,60.294mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(149.791mm,60.294mm) on Bottom Layer And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(170.586mm,54.345mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(170.586mm,52.045mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(170.586mm,49.745mm) on Bottom Layer And Track (169.125mm,48.643mm)(169.125mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(164.871mm,52.045mm) on Bottom Layer And Track (166.333mm,48.643mm)(166.333mm,55.446mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-1(170.572mm,61.307mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-2(170.572mm,59.007mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-3(170.572mm,56.707mm) on Bottom Layer And Track (169.111mm,55.605mm)(169.111mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-4(164.857mm,59.007mm) on Bottom Layer And Track (166.319mm,55.605mm)(166.319mm,62.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-1(146.842mm,49.708mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-10(141.097mm,57.328mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-11(141.097mm,56.058mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-12(141.097mm,54.788mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-13(141.097mm,53.518mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-14(141.097mm,52.248mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-15(141.097mm,50.978mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-16(141.097mm,49.708mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-2(146.842mm,50.978mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-3(146.842mm,52.248mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-4(146.842mm,53.518mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-5(146.842mm,54.788mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-6(146.842mm,56.058mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-7(146.842mm,57.328mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-8(146.842mm,58.598mm) on Top Layer And Track (145.741mm,49.077mm)(145.741mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-9(141.097mm,58.598mm) on Top Layer And Track (142.198mm,49.077mm)(142.198mm,59.229mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.435mm,60.764mm) on Top Overlay And Track (152.063mm,61.498mm)(153.963mm,61.498mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.435mm,60.764mm) on Top Overlay And Via (152.063mm,61.498mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(174.295mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.295mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(156.515mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-10(161.595mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-11(159.055mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-11(159.055mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-12(156.515mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(159.055mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(159.055mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(161.595mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(164.135mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(166.675mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(169.215mm,50.267mm) on Top Layer And Track (148.387mm,50.35mm)(177.216mm,50.35mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(169.215mm,50.267mm) on Top Layer And Track (148.387mm,51.366mm)(177.089mm,51.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-7(169.215mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(169.215mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-8(166.675mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-8(166.675mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-9(164.135mm,60.764mm) on Top Layer And Track (148.387mm,59.367mm)(177.089mm,59.367mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-9(164.135mm,60.764mm) on Top Layer And Track (148.387mm,60.383mm)(177.216mm,60.383mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U6-4(160.228mm,61.577mm) on Bottom Layer And Track (160.723mm,61.331mm)(161.634mm,61.331mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U6-5(162.128mm,61.577mm) on Bottom Layer And Track (160.723mm,61.331mm)(161.634mm,61.331mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Text "C8" (152.324mm,58.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U7-5(152.063mm,59.203mm) on Bottom Layer And Track (152.558mm,59.449mm)(153.468mm,59.449mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.107mm < 0.254mm) Between Arc (151.18mm,59.544mm) on Bottom Overlay And Text "C8" (152.324mm,58.928mm) on Bottom Overlay Silk Text to Silk Clearance [0.107mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (151.345mm,61.65mm) on Bottom Overlay And Text "U1" (151.075mm,61.564mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "+" (158.969mm,59.818mm) on Bottom Overlay And Track (159.627mm,59.529mm)(159.627mm,61.331mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "BT1" (161.864mm,62.79mm) on Bottom Overlay And Text "U6" (162.887mm,62.97mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Text "C10" (147.599mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Text "R?" (151.917mm,52.821mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.159mm < 0.254mm) Between Text "C?" (149.758mm,52.846mm) on Bottom Overlay And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0.159mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Text "C10" (147.599mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Text "R1" (146.609mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.173mm < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.173mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (145.618mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Text "R1" (146.609mm,52.162mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.123mm < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.464mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.123mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C10" (147.599mm,52.162mm) on Bottom Overlay And Track (143.464mm,53.218mm)(143.96mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C11" (148.369mm,62.84mm) on Bottom Overlay And Text "C9" (151.079mm,63.144mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (150.121mm,60.37mm)(150.617mm,60.37mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (150.617mm,59.875mm)(150.617mm,60.37mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (151.462mm,59.449mm)(151.462mm,61.252mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.031mm < 0.254mm) Between Text "C8" (152.324mm,58.928mm) on Bottom Overlay And Track (152.558mm,59.449mm)(153.468mm,59.449mm) on Bottom Overlay Silk Text to Silk Clearance [0.031mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C9" (151.079mm,63.144mm) on Bottom Overlay And Text "U1" (151.075mm,61.564mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.057mm < 0.254mm) Between Text "R?" (151.917mm,52.821mm) on Bottom Overlay And Track (150.121mm,53.218mm)(150.617mm,53.218mm) on Bottom Overlay Silk Text to Silk Clearance [0.057mm]
Silk To Silk Clearance Constraint: (0.082mm < 0.254mm) Between Text "R?" (151.917mm,52.821mm) on Bottom Overlay And Track (150.617mm,53.218mm)(150.617mm,53.714mm) on Bottom Overlay Silk Text to Silk Clearance [0.082mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.648mm,49.54mm)(139.648mm,53.692mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.648mm,53.692mm)(140.341mm,53.692mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
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+ diff --git a/植物探头/使用时间监测模块/LM340-5.PcbLib b/植物探头/使用时间监测模块/LM340-5.PcbLib new file mode 100644 index 0000000..f2c5918 Binary files /dev/null and b/植物探头/使用时间监测模块/LM340-5.PcbLib differ diff --git a/植物探头/使用时间监测模块/MAX40200AUK+T.PcbLib b/植物探头/使用时间监测模块/MAX40200AUK+T.PcbLib new file mode 100644 index 0000000..2b554cd Binary files /dev/null and b/植物探头/使用时间监测模块/MAX40200AUK+T.PcbLib differ diff --git a/植物探头/使用时间监测模块/MS920SE FL27E.PcbLib b/植物探头/使用时间监测模块/MS920SE FL27E.PcbLib new file mode 100644 index 0000000..251afc6 Binary files /dev/null and b/植物探头/使用时间监测模块/MS920SE FL27E.PcbLib differ diff --git a/植物探头/使用时间监测模块/PCB1.PcbDoc b/植物探头/使用时间监测模块/PCB1.PcbDoc index 22d58ca..5f76475 100644 Binary files a/植物探头/使用时间监测模块/PCB1.PcbDoc and b/植物探头/使用时间监测模块/PCB1.PcbDoc differ diff --git a/植物探头/使用时间监测模块/PCB_Project2.PrjPCB b/植物探头/使用时间监测模块/PCB_Project2.PrjPCB index 1f64990..295d76b 100644 --- a/植物探头/使用时间监测模块/PCB_Project2.PrjPCB +++ b/植物探头/使用时间监测模块/PCB_Project2.PrjPCB @@ -38,6 +38,74 @@ PrefsVaultGUID= PrefsRevisionGUID= [Document1] +DocumentPath=117.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=CLOVGEAG + +[Document2] +DocumentPath=MAX40200AUK+T.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=SGHXNDPL + +[Document3] +DocumentPath=XAL4020-102ME.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=FOCXOKOP + +[Document4] +DocumentPath=TLV62568A.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=TLSTNFSJ + +[Document5] DocumentPath=SW.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -54,7 +122,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=LXDCRWHM -[Document2] +[Document6] DocumentPath=CNJMA2001WR-S-2P.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -71,7 +139,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=INPGMSFR -[Document3] +[Document7] DocumentPath=0603.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -88,58 +156,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=BIUPNOXY -[Document4] -DocumentPath=..\..\air\С\VK1650.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=ELLVDYJE - -[Document5] -DocumentPath=..\..\air\С\LM340.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=LFBRLLME - -[Document6] -DocumentPath=..\..\air\С\AMS1117-3.3.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=JMSULWYB - -[Document7] +[Document8] DocumentPath=s8550.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -156,7 +173,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=YEHQBMNG -[Document8] +[Document9] DocumentPath=FC-135.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -173,7 +190,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=FQOKAWCL -[Document9] +[Document10] DocumentPath=GS2040AR-CR.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -190,7 +207,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=XHCRLJYY -[Document10] +[Document11] DocumentPath=esp32-picp-d4.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -207,7 +224,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=YQPQVROV -[Document11] +[Document12] DocumentPath=Sheet1.SchDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -224,7 +241,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=EOQQGAML -[Document12] +[Document13] DocumentPath=PCB1.PcbDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -241,23 +258,6 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=IMPPCEGS -[Document13] -DocumentPath=..\..\air\С\LMZ21701.SchLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=BVKMUSVW - [Document14] DocumentPath=1N4001W.PcbLib AnnotationEnabled=1 @@ -275,6 +275,23 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=BVJNXFNT +[Document15] +DocumentPath=TLV62568A.SchLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=XNYTWASM + [GeneratedDocument1] DocumentPath=Project Outputs for PCB_Project2\Design Rule Check - PCB1.html DItemRevisionGUID= diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-21 17-32-21.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-21 17-32-21.LOG new file mode 100644 index 0000000..fad1be9 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-21 17-32-21.LOG @@ -0,0 +1,76 @@ +Removed Pin From Net: NetName=GND Pin=C14-1 +Removed Pin From Net: NetName=+5 Pin=C14-2 +Removed Pin From Net: NetName=GND Pin=C15-1 +Removed Pin From Net: NetName=+5 Pin=C15-2 +Removed Pin From Net: NetName=GND Pin=C16-1 +Removed Pin From Net: NetName=IO34 ADC Pin=C16-2 +Removed Pin From Net: NetName=IO34 ADC Pin=D?-1 +Removed Pin From Net: NetName=+3.3 Pin=D?-2 +Removed Pin From Net: NetName=GND Pin=U3-1 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-2 +Removed Pin From Net: NetName=+5 Pin=U3-3 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-4 +Removed Member From Class: ClassName=Sheet1 Member=C16 +Removed Member From Class: ClassName=Sheet1 Member=D? +Removed Member From Class: ClassName=Sheet1 Member=U3 +Change Component Comment : Designator=C14 Old Comment=Cap New Comment=10uF +Change Component Comment : Designator=C15 Old Comment=Cap New Comment=22uF/25V +Change Component Designator: OldDesignator=R? NewDesignator=R3 +Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\KEXGXJDS" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805X106K160NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C89189"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters: Designator = "C15"; Footprint = "6-0805_N"; UniqueID = "\SNPXTYOC" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "A_Ԫ"; Value = "C45783"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "B_Ԫ"; Value = "22uF (226) 20% 25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "C_Ԫ"; Value = "Ƭ"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "D_Ԫͺ"; Value = "CL21A226MAQNNNE"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "E_װ"; Value = "0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "F_ֵ()/ֵ(uF)"; Value = "22.0000000000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "G_ѹ"; Value = "25.00"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "H_"; Value = "20%"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "I_"; Value = "2"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "J_ƷƲ"; Value = "SAMSUNG()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805F226M100NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C 0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C67101"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "/Ԫ"; Value = "0.134"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ԭ"; Value = "SZLY"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ע"; Value = "ƬԪ"; VariantName = "[No Variations]" +Added Component: Designator=R4(6-0805_N) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Device"; Value = "10k"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Name"; Value = "10k"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Origin Footprint"; Value = "R0603"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Symbol"; Value = "10k"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+5 Pin=C14-1 +Added Pin To Net: NetName=GND Pin=C14-2 +Added Pin To Net: NetName=+3.3 Pin=C15-1 +Added Pin To Net: NetName=GND Pin=C15-2 +Added Pin To Net: NetName=+5 Pin=R4-1 +Added Pin To Net: NetName=NetQ?_1 Pin=R4-2 +Added Net: Name=NetQ?_1 +Added Member To Class: ClassName=Sheet1 Member=Component R4 10k +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-14.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-14.LOG new file mode 100644 index 0000000..f95e34a --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-14.LOG @@ -0,0 +1,69 @@ +Removed Pin From Net: NetName=+3.3 Pin=C4-1 +Removed Pin From Net: NetName=GND Pin=C4-2 +Removed Pin From Net: NetName=+5 Pin=R4-1 +Removed Member From Class: ClassName=Sheet1 Member=C4 +Removed Member From Class: ClassName=Sheet1 Member=R4 +Added Component: Designator=BT1(BAT-2) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Battery; 2 Leads"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "BAT-2"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "24-Mar-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=C?(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=D1(SMC) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=D2(SMC) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Component: Designator=R?(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "10k/20K"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=BT1-2 +Added Pin To Net: NetName=GND Pin=C?-1 +Added Pin To Net: NetName=IO34 ADC Pin=C?-2 +Added Pin To Net: NetName=+3.3 Pin=D1-1 +Added Pin To Net: NetName=+3.3 Pin=R?-1 +Added Pin To Net: NetName=IO34 ADC Pin=R?-2 +Added Pin To Net: NetName=+3.3-2 Pin=D2-2 +Added Net: Name=+3.3-2 +Added Pin To Net: NetName=NetBT1_1 Pin=BT1-1 +Added Pin To Net: NetName=NetBT1_1 Pin=D1-2 +Added Pin To Net: NetName=NetBT1_1 Pin=D2-1 +Added Net: Name=NetBT1_1 +Added Member To Class: ClassName=Sheet1 Member=Component BT1 MS920SE +Added Member To Class: ClassName=Sheet1 Member=Component C? Cap +Added Member To Class: ClassName=Sheet1 Member=Component D1 Diode +Added Member To Class: ClassName=Sheet1 Member=Component D2 Diode +Added Member To Class: ClassName=Sheet1 Member=Component R? Res1 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-27.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-27.LOG new file mode 100644 index 0000000..99b37fa --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-51-27.LOG @@ -0,0 +1,32 @@ +Added Component: Designator=U1(esp32-pico-d4) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3 Pin=U1-1 +Added Pin To Net: NetName=+3.3 Pin=U1-3 +Added Pin To Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=EN Pin=U1-9 +Added Pin To Net: NetName=IO34 ADC Pin=U1-10 +Added Pin To Net: NetName=NetC6_2 Pin=U1-12 +Added Pin To Net: NetName=NetC7_2 Pin=U1-13 +Added Pin To Net: NetName=CLK Pin=U1-14 +Added Pin To Net: NetName=DAT Pin=U1-15 +Added Pin To Net: NetName=+3.3 Pin=U1-19 +Added Pin To Net: NetName=GND Pin=U1-22 +Added Pin To Net: NetName=IO0 Pin=U1-23 +Added Pin To Net: NetName=SW Pin=U1-24 +Added Pin To Net: NetName=+3.3 Pin=U1-37 +Added Pin To Net: NetName=U0RXD Pin=U1-40 +Added Pin To Net: NetName=U0TXD Pin=U1-41 +Added Pin To Net: NetName=+3.3 Pin=U1-43 +Added Pin To Net: NetName=+3.3 Pin=U1-46 +Added Pin To Net: NetName=GND Pin=U1-49 +Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-54-58.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-54-58.LOG new file mode 100644 index 0000000..dc84a97 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-54-58.LOG @@ -0,0 +1,30 @@ +Removed Pin From Net: NetName=GND Pin=C5-1 +Removed Pin From Net: NetName=+3.3 Pin=C5-2 +Removed Pin From Net: NetName=GND Pin=C6-1 +Removed Pin From Net: NetName=GND Pin=C7-1 +Removed Pin From Net: NetName=+3.3 Pin=C15-1 +Removed Pin From Net: NetName=+3.3 Pin=C17-2 +Removed Pin From Net: NetName=+3.3 Pin=C18-2 +Removed Pin From Net: NetName=+3.3 Pin=D1-1 +Removed Pin From Net: NetName=+3.3 Pin=R1-2 +Removed Pin From Net: NetName=+3.3 Pin=R2-2 +Removed Pin From Net: NetName=+3.3 Pin=R3-2 +Removed Pin From Net: NetName=+3.3 Pin=R?-1 +Removed Pin From Net: NetName=+3.3 Pin=U4-10 +Removed Member From Class: ClassName=Sheet1 Member=C5 +Removed Member From Class: ClassName=Sheet1 Member=C6 +Removed Member From Class: ClassName=Sheet1 Member=C7 +Removed Member From Class: ClassName=Sheet1 Member=Y? +Added Pin To Net: NetName=+3.3 Pin=D2-2 +Change Net Name : Old Net Name=+3.3 New Net Name=+3.3-2 +Added Pin To Net: NetName=+3.3 Pin=C15-1 +Added Pin To Net: NetName=+3.3 Pin=C17-2 +Added Pin To Net: NetName=+3.3 Pin=C18-2 +Added Pin To Net: NetName=+3.3 Pin=D1-1 +Added Pin To Net: NetName=+3.3 Pin=R1-2 +Added Pin To Net: NetName=+3.3 Pin=R2-2 +Added Pin To Net: NetName=+3.3 Pin=R3-2 +Added Pin To Net: NetName=+3.3 Pin=R?-1 +Added Pin To Net: NetName=+3.3 Pin=U4-10 +Added Net: Name=+3.3 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-55-39.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-55-39.LOG new file mode 100644 index 0000000..79a0278 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-55-39.LOG @@ -0,0 +1,97 @@ +Added Component: Designator=C1(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "nameAlias"; Value = "Value(F)"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "C_0603_US"; VariantName = "[No Variations]" +Added Component: Designator=C2(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C3(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=C8(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C9(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C10(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "0.1F"; VariantName = "[No Variations]" +Added Component: Designator=C11(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1F"; VariantName = "[No Variations]" +Added Component: Designator=R1(0402) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "nameAlias"; Value = "Value()"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=C1-1 +Added Pin To Net: NetName=EN Pin=C1-2 +Added Pin To Net: NetName=+3.3-2 Pin=C2-1 +Added Pin To Net: NetName=GND Pin=C2-2 +Added Pin To Net: NetName=GND Pin=C3-1 +Added Pin To Net: NetName=+3.3-2 Pin=C3-2 +Added Pin To Net: NetName=GND Pin=C8-1 +Added Pin To Net: NetName=+3.3-2 Pin=C8-2 +Added Pin To Net: NetName=GND Pin=C9-1 +Added Pin To Net: NetName=+3.3-2 Pin=C9-2 +Added Pin To Net: NetName=GND Pin=C10-1 +Added Pin To Net: NetName=+3.3-2 Pin=C10-2 +Added Pin To Net: NetName=+3.3-2 Pin=C11-1 +Added Pin To Net: NetName=GND Pin=C11-2 +Added Pin To Net: NetName=EN Pin=R1-1 +Added Pin To Net: NetName=+3.3 Pin=R1-2 +Added Member To Class: ClassName=Sheet1 Member=Component C1 1u +Added Member To Class: ClassName=Sheet1 Member=Component C2 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C3 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C8 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C9 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C10 Cap +Added Member To Class: ClassName=Sheet1 Member=Component C11 Cap +Added Member To Class: ClassName=Sheet1 Member=Component R1 10k +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-57-49.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-57-49.LOG new file mode 100644 index 0000000..ae5ae02 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 11-57-49.LOG @@ -0,0 +1,5 @@ +Change Component Footprint: Designator=R? Old Footprint=AXIAL-0.3 New Footprint=6-0805_N +Change Component Footprint: Designator=C? Old Footprint=RAD-0.3 New Footprint=6-0805_N +Change Component Footprint: Designator=D1 Old Footprint=SMC New Footprint=1N4001W +Change Component Footprint: Designator=D2 Old Footprint=SMC New Footprint=1N4001W +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-12.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-12.LOG new file mode 100644 index 0000000..ad56e99 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-12.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=U2 Old Footprint=LM340 New Footprint=LM340-5 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-49.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-49.LOG new file mode 100644 index 0000000..6f82d69 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-02-49.LOG @@ -0,0 +1 @@ +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-50-32.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-50-32.LOG new file mode 100644 index 0000000..79b7615 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 12-50-32.LOG @@ -0,0 +1,18 @@ +Added Component: Designator=U3(ASM1117-3.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Device"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Name"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Origin Footprint"; Value = "AMS117-3.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Symbol"; Value = "AMS117"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=U3-1 +Added Pin To Net: NetName=+3.3 Pin=U3-2 +Added Pin To Net: NetName=+5 Pin=U3-3 +Added Member To Class: ClassName=Sheet1 Member=Component U3 AMS117 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-04-30.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-04-30.LOG new file mode 100644 index 0000000..072e616 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-04-30.LOG @@ -0,0 +1,2 @@ +Change Component Footprint: Designator=BT1 Old Footprint=BAT-2 New Footprint=MS920SE FL27E +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-06-07.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-06-07.LOG new file mode 100644 index 0000000..074e267 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-06-07.LOG @@ -0,0 +1,12 @@ +Added Component: Designator=BT1(MS920SE FL27E) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Battery; 2 Leads"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "BAT-2"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "24-Mar-1999"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=NetBT1_1 Pin=BT1-1 +Added Pin To Net: NetName=GND Pin=BT1-2 +Added Member To Class: ClassName=Sheet1 Member=Component BT1 MS920SE +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-30-37.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-30-37.LOG new file mode 100644 index 0000000..e8e6b17 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-30-37.LOG @@ -0,0 +1,27 @@ +Removed Pin From Net: NetName=+3.3 Pin=D1-1 +Removed Pin From Net: NetName=NetBT1_1 Pin=D1-2 +Removed Pin From Net: NetName=NetBT1_1 Pin=D2-1 +Removed Pin From Net: NetName=+3.3-2 Pin=D2-2 +Removed Pin From Net: NetName=+3.3 Pin=R1-2 +Removed Pin From Net: NetName=+3.3 Pin=R2-2 +Removed Pin From Net: NetName=+3.3 Pin=R3-2 +Removed Member From Class: ClassName=Sheet1 Member=D1 +Removed Member From Class: ClassName=Sheet1 Member=D2 +Added Component: Designator=U6(MAX40200AUK+T) +Add component. Clean all parameters for all variants +Added Component: Designator=U7(MAX40200AUK+T) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=+3.3-2 Pin=R1-2 +Added Pin To Net: NetName=+3.3-2 Pin=R2-2 +Added Pin To Net: NetName=+3.3-2 Pin=R3-2 +Added Pin To Net: NetName=+3.3 Pin=U6-1 +Added Pin To Net: NetName=GND Pin=U6-2 +Added Pin To Net: NetName=+3.3 Pin=U6-3 +Added Pin To Net: NetName=NetBT1_1 Pin=U6-5 +Added Pin To Net: NetName=NetBT1_1 Pin=U7-1 +Added Pin To Net: NetName=GND Pin=U7-2 +Added Pin To Net: NetName=NetBT1_1 Pin=U7-3 +Added Pin To Net: NetName=+3.3-2 Pin=U7-5 +Added Member To Class: ClassName=Sheet1 Member=Component U6 MAX40200AUK+T +Added Member To Class: ClassName=Sheet1 Member=Component U7 MAX40200AUK+T +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-40-30.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-40-30.LOG new file mode 100644 index 0000000..c4c5215 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-24 13-40-30.LOG @@ -0,0 +1,7 @@ +Removed Pin From Net: NetName=+3.3-2 Pin=C2-1 +Removed Pin From Net: NetName=GND Pin=C2-2 +Removed Pin From Net: NetName=GND Pin=C3-1 +Removed Pin From Net: NetName=+3.3-2 Pin=C3-2 +Removed Member From Class: ClassName=Sheet1 Member=C2 +Removed Member From Class: ClassName=Sheet1 Member=C3 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG new file mode 100644 index 0000000..85c0ac4 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-28-33.LOG @@ -0,0 +1,129 @@ +Removed Pin From Net: NetName=+3.3 Pin=C2-1 +Removed Pin From Net: NetName=GND Pin=C2-2 +Removed Pin From Net: NetName=+3.3 Pin=C5-2 +Removed Pin From Net: NetName=GND Pin=C6-1 +Removed Pin From Net: NetName=GND Pin=C7-1 +Removed Pin From Net: NetName=GND Pin=C9-1 +Removed Pin From Net: NetName=+3.3 Pin=C9-2 +Removed Pin From Net: NetName=GND Pin=C10-1 +Removed Pin From Net: NetName=+3.3 Pin=C10-2 +Removed Pin From Net: NetName=+5 Pin=C15-2 +Removed Pin From Net: NetName=GND Pin=C16-1 +Removed Pin From Net: NetName=IO34 ADC Pin=C16-2 +Removed Pin From Net: NetName=+3.3 Pin=C17-2 +Removed Pin From Net: NetName=+3.3 Pin=C18-2 +Removed Pin From Net: NetName=IO34 ADC Pin=D?-1 +Removed Pin From Net: NetName=+3.3 Pin=D?-2 +Removed Pin From Net: NetName=+3.3 Pin=U1-4 +Removed Pin From Net: NetName=GND Pin=U3-1 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-2 +Removed Pin From Net: NetName=IO34 ADC Pin=U3-4 +Removed Pin From Net: NetName=+3.3 Pin=U4-10 +Removed Member From Class: ClassName=Sheet1 Member=C2 +Removed Member From Class: ClassName=Sheet1 Member=C6 +Removed Member From Class: ClassName=Sheet1 Member=C7 +Removed Member From Class: ClassName=Sheet1 Member=C9 +Removed Member From Class: ClassName=Sheet1 Member=C10 +Removed Member From Class: ClassName=Sheet1 Member=D? +Removed Member From Class: ClassName=Sheet1 Member=Y? +Change Component Footprint: Designator=C14 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Footprint: Designator=C15 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Footprint: Designator=C16 Old Footprint=6-0805_N New Footprint=RAD-0.3 +Change Component Comment : Designator=U3 Old Comment= New Comment=TLV62568A +Change Component Designator: OldDesignator=C17 NewDesignator=C18 +Change Component Designator: OldDesignator=C18 NewDesignator=C19 +Change Component Designator: OldDesignator=R? NewDesignator=R3 +Change Component Designator: OldDesignator=U4 NewDesignator=U5 +Change Component Designator: OldDesignator=U5 NewDesignator=U6 +Change component parameters: Designator = "C14"; Footprint = "RAD-0.3"; UniqueID = "\WMNPPNUP" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "4.7F"; VariantName = "[No Variations]" +Change component parameters: Designator = "C15"; Footprint = "RAD-0.3"; UniqueID = "\NCFGQGJL" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22F"; VariantName = "[No Variations]" +Change component parameters: Designator = "C16"; Footprint = "RAD-0.3"; UniqueID = "\NYURCQQB" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "10pF"; VariantName = "[No Variations]" +Added Component: Designator=C17(RAD-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]" +Added Component: Designator=R4(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R5(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Component: Designator=R6(AXIAL-0.3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=C17-1 +Added Pin To Net: NetName=IO34 ADC Pin=C17-2 +Added Pin To Net: NetName=GND Pin=R5-1 +Added Pin To Net: NetName=IO34 ADC Pin=R6-2 +Added Pin To Net: NetName=GND Pin=U3-2 +Change Net Name : Old Net Name=+3.3 New Net Name=+3.3-2 +Added Pin To Net: NetName=+3.3 Pin=C5-2 +Added Pin To Net: NetName=+3.3 Pin=C15-2 +Added Pin To Net: NetName=+3.3 Pin=C16-2 +Added Pin To Net: NetName=+3.3 Pin=C18-2 +Added Pin To Net: NetName=+3.3 Pin=C19-2 +Added Pin To Net: NetName=+3.3 Pin=R4-2 +Added Pin To Net: NetName=+3.3 Pin=R6-1 +Added Pin To Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=+3.3 Pin=U5-10 +Added Net: Name=+3.3 +Added Pin To Net: NetName=NetC16_1 Pin=C16-1 +Added Pin To Net: NetName=NetC16_1 Pin=R4-1 +Added Pin To Net: NetName=NetC16_1 Pin=R5-2 +Added Pin To Net: NetName=NetC16_1 Pin=U3-1 +Added Net: Name=NetC16_1 +Added Pin To Net: NetName=NetPL?_1 Pin=U3-4 +Added Net: Name=NetPL?_1 +Added Member To Class: ClassName=Sheet1 Member=Component C19 Cap +Added Member To Class: ClassName=Sheet1 Member=Component R4 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component R5 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component R6 Res1 +Added Member To Class: ClassName=Sheet1 Member=Component U6 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG new file mode 100644 index 0000000..5c04efe --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-45-07.LOG @@ -0,0 +1,2 @@ +Added Member To Class: ClassName=Sheet1 Member=Component C12 Cap +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG new file mode 100644 index 0000000..38615e1 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 16-49-57.LOG @@ -0,0 +1,5 @@ +Removed Pin From Net: NetName=+3.3 Pin=C5-2 +Removed Pin From Net: NetName=+3.3 Pin=U1-4 +Added Pin To Net: NetName=+3.3-2 Pin=C5-2 +Added Pin To Net: NetName=+3.3-2 Pin=U1-4 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG new file mode 100644 index 0000000..f1b4ebb --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-16-26.LOG @@ -0,0 +1,30 @@ +Added Component: Designator=U1(esp32-pico-d4) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+3.3-2 Pin=U1-1 +Added Pin To Net: NetName=+3.3-2 Pin=U1-3 +Added Pin To Net: NetName=+3.3-2 Pin=U1-4 +Added Pin To Net: NetName=EN Pin=U1-9 +Added Pin To Net: NetName=IO34 ADC Pin=U1-10 +Added Pin To Net: NetName=CLK Pin=U1-14 +Added Pin To Net: NetName=DAT Pin=U1-15 +Added Pin To Net: NetName=+3.3-2 Pin=U1-19 +Added Pin To Net: NetName=GND Pin=U1-22 +Added Pin To Net: NetName=IO0 Pin=U1-23 +Added Pin To Net: NetName=SW Pin=U1-24 +Added Pin To Net: NetName=+3.3-2 Pin=U1-37 +Added Pin To Net: NetName=U0RXD Pin=U1-40 +Added Pin To Net: NetName=U0TXD Pin=U1-41 +Added Pin To Net: NetName=+3.3-2 Pin=U1-43 +Added Pin To Net: NetName=+3.3-2 Pin=U1-46 +Added Pin To Net: NetName=GND Pin=U1-49 +Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG new file mode 100644 index 0000000..8865168 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-32-58.LOG @@ -0,0 +1,16 @@ +Change Component Footprint: Designator=R4 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=R5 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=R6 Old Footprint=AXIAL-0.3 New Footprint=0603 +Change Component Footprint: Designator=C14 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C15 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C16 Old Footprint=RAD-0.3 New Footprint=0603 +Change Component Footprint: Designator=C17 Old Footprint=RAD-0.3 New Footprint=0603 +Added Component: Designator=U3(TLV62568A) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=NetC16_1 Pin=U3-1 +Added Pin To Net: NetName=GND Pin=U3-2 +Added Pin To Net: NetName=+5 Pin=U3-3 +Added Pin To Net: NetName=NetPL?_1 Pin=U3-4 +Added Pin To Net: NetName=+5 Pin=U3-5 +Added Member To Class: ClassName=Sheet1 Member=Component U3 TLV62568A +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG new file mode 100644 index 0000000..a0a263b --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-45-08.LOG @@ -0,0 +1,6 @@ +Added Component: Designator=PL?(XAL4020-102ME) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=NetPL?_1 Pin=PL?-1 +Added Pin To Net: NetName=+3.3 Pin=PL?-2 +Added Member To Class: ClassName=Sheet1 Member=Component PL? 2.2H +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG new file mode 100644 index 0000000..3ee9131 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-29 17-54-15.LOG @@ -0,0 +1,8 @@ +Added Component: Designator=U4(MAX40200AUK+T) +Add component. Clean all parameters for all variants +Added Pin To Net: NetName=+3.3 Pin=U4-1 +Added Pin To Net: NetName=GND Pin=U4-2 +Added Pin To Net: NetName=+3.3 Pin=U4-3 +Added Pin To Net: NetName=+3.3-2 Pin=U4-5 +Added Member To Class: ClassName=Sheet1 Member=Component U4 MAX40200AUK+T +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG new file mode 100644 index 0000000..43fe089 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 10-40-52.LOG @@ -0,0 +1,10 @@ +Added Component: Designator=P2(HDR1X3) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]" +Added Pin To Net: NetName=U0TXD Pin=P2-1 +Added Pin To Net: NetName=U0RXD Pin=P2-2 +Added Pin To Net: NetName=GND Pin=P2-3 +Added Member To Class: ClassName=Sheet1 Member=Component P2 DEBUG +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG new file mode 100644 index 0000000..6a5b8db --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-39-57.LOG @@ -0,0 +1,63 @@ +Removed Pin From Net: NetName=GND Pin=C14-1 +Removed Pin From Net: NetName=+5 Pin=C14-2 +Removed Pin From Net: NetName=GND Pin=C15-1 +Removed Pin From Net: NetName=+3.3 Pin=C15-2 +Removed Pin From Net: NetName=+3.3 Pin=C16-2 +Removed Pin From Net: NetName=+3.3 Pin=PL?-2 +Removed Pin From Net: NetName=+3.3 Pin=R4-2 +Removed Pin From Net: NetName=GND Pin=R5-1 +Removed Pin From Net: NetName=GND Pin=U3-2 +Removed Pin From Net: NetName=+5 Pin=U3-3 +Removed Pin From Net: NetName=+5 Pin=U3-5 +Removed Member From Class: ClassName=Sheet1 Member=C16 +Removed Member From Class: ClassName=Sheet1 Member=PL? +Removed Member From Class: ClassName=Sheet1 Member=R4 +Removed Member From Class: ClassName=Sheet1 Member=R5 +Removed Member From Class: ClassName=Sheet1 Member=U3 +Change Component Footprint: Designator=C14 Old Footprint=0603 New Footprint=6-0805_N +Change Component Footprint: Designator=C15 Old Footprint=0603 New Footprint=6-0805_N +Change Component Comment : Designator=C14 Old Comment=Cap New Comment=10uF +Change Component Comment : Designator=C15 Old Comment=Cap New Comment=22uF/25V +Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\QDBKEQLT" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805X106K160NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C89189"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "10uF"; VariantName = "[No Variations]" +Change component parameters: Designator = "C15"; Footprint = "6-0805_N"; UniqueID = "\MJCTGQXY" +Change component parameters. Clean all parameters for all variants +Change component parameters (AddParameter): Name = "A_Ԫ"; Value = "C45783"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "B_Ԫ"; Value = "22uF (226) 20% 25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "C_Ԫ"; Value = "Ƭ"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "D_Ԫͺ"; Value = "CL21A226MAQNNNE"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Device"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "E_װ"; Value = "0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "F_ֵ()/ֵ(uF)"; Value = "22.0000000000"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "G_ѹ"; Value = "25.00"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "H_"; Value = "20%"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "I_"; Value = "2"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "J_ƷƲ"; Value = "SAMSUNG()"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805F226M100NT"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Name"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C 0805"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C67101"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Symbol"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "Value"; Value = "22uF/25V"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "/Ԫ"; Value = "0.134"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ԭ"; Value = "SZLY"; VariantName = "[No Variations]" +Change component parameters (AddParameter): Name = "ע"; Value = "ƬԪ"; VariantName = "[No Variations]" +Added Pin To Net: NetName=+5 Pin=C14-1 +Added Pin To Net: NetName=GND Pin=C14-2 +Added Pin To Net: NetName=+3.3 Pin=C15-1 +Added Pin To Net: NetName=GND Pin=C15-2 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG new file mode 100644 index 0000000..6cc26c8 --- /dev/null +++ b/植物探头/使用时间监测模块/Project Logs for PCB_Project2/PCB1 PCB ECO 2022-6-30 9-42-29.LOG @@ -0,0 +1,18 @@ +Added Component: Designator=U?(1117) +Add component. Clean all parameters for all variants +Add component (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Device"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Manufacturer Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Name"; Value = "AMS117"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Origin Footprint"; Value = "AMS117-3.3"; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Supplier Part"; Value = ""; VariantName = "[No Variations]" +Add component (AddParameter): Name = "Symbol"; Value = "AMS117"; VariantName = "[No Variations]" +Added Pin To Net: NetName=GND Pin=U?-1 +Added Pin To Net: NetName=+3.3 Pin=U?-2 +Added Pin To Net: NetName=+5 Pin=U?-3 +Added Member To Class: ClassName=Sheet1 Member=Component U? AMS117 +Added Room: Name=Sheet1 diff --git a/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc b/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc index d437156..572e032 100644 --- a/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc +++ b/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc @@ -1,7 +1,7 @@ Protel Design System Design Rule Check -PCB File : C:\Users\hu123456\Desktop\ֲ̽ͷ\ʹʱģ\PCB1.PcbDoc -Date : 2022/5/7 -Time : 14:08:10 +PCB File : C:\Users\hu123456\Desktop\ʹʱģ\PCB1.PcbDoc +Date : 2022/6/30 +Time : 13:25:17 Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) Rule Violations :0 @@ -28,299 +28,235 @@ Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) Rule Violations :0 Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C10-1(141.91mm,48.971mm) on Top Layer And Pad C10-2(141.91mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.062mm < 0.254mm) Between Pad C10-2(141.91mm,49.971mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.062mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Pad C1-2(140.648mm,61.747mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Pad R1-2(141.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.237mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.16mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Via (141.402mm,62.611mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.16mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Pad C11-2(143.241mm,48.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.069mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.069mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.057mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.057mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad C1-2(140.648mm,61.747mm) on Top Layer And Pad R1-1(140.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.237mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.138mm < 0.254mm) Between Pad C18-2(141.3mm,50.981mm) on Bottom Layer And Via (140.259mm,51.333mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.138mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C2-1(144.572mm,49.971mm) on Top Layer And Pad C2-2(144.572mm,48.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.041mm < 0.254mm) Between Pad C2-1(144.572mm,49.971mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.041mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.903mm,48.971mm) on Top Layer And Pad C3-2(145.903mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.248mm < 0.254mm) Between Pad C4-1(155.931mm,53.086mm) on Bottom Layer And Via (153.441mm,51.232mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.248mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.131mm < 0.254mm) Between Pad C4-2(155.931mm,60.706mm) on Bottom Layer And Via (153.441mm,61.62mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.131mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(147.234mm,48.971mm) on Top Layer And Pad C5-2(147.234mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Pad C6-2(149.174mm,61.943mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.171mm < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Via (150.012mm,60.35mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.171mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C7-1(143.891mm,61.595mm) on Top Layer And Pad C7-2(143.891mm,60.595mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(142.85mm,61.587mm) on Top Layer And Pad C8-2(142.85mm,60.587mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.144mm < 0.254mm) Between Pad C8-2(142.85mm,60.587mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.144mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C9-1(140.579mm,48.971mm) on Top Layer And Pad C9-2(140.579mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.204mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Via (153.213mm,49.047mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.204mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.138mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Via (153.441mm,51.232mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.138mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Via (175.666mm,57.125mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Via (179.73mm,53.797mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.097mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.118mm < 0.254mm) Between Pad P2-2(140.894mm,58.547mm) on Bottom Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.118mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R?-1(179.638mm,60.35mm) on Top Layer And Pad R?-2(178.638mm,60.35mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(140.648mm,60.808mm) on Top Layer And Pad R1-2(141.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(151.689mm,49.563mm) on Bottom Layer And Pad R2-2(151.689mm,50.563mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.108mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (148.305mm,51.505mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.108mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.175mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (148.615mm,48.971mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.175mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.175mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (149.631mm,48.971mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.175mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.086mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.086mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Via (177.952mm,56.236mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.229mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-2(147.518mm,52.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-48(146.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-11(147.518mm,57.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.343mm) on Top Layer And Pad U1-12(147.518mm,57.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-11(147.518mm,57.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Pad U1-13(146.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Pad U1-14(146.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.593mm) on Top Layer And Pad U1-15(145.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-14(146.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.593mm) on Top Layer And Pad U1-16(145.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-15(145.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.593mm) on Top Layer And Pad U1-17(144.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-16(145.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Pad U1-18(144.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.244mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.593mm) on Top Layer And Pad U1-19(143.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-18(144.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.593mm) on Top Layer And Pad U1-20(143.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-19(143.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,52.843mm) on Top Layer And Pad U1-3(147.518mm,53.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-2(147.518mm,52.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.593mm) on Top Layer And Pad U1-21(142.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-20(143.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Pad U1-22(142.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.244mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Pad U1-23(141.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.237mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.245mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.245mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Pad U1-24(141.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.142mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.142mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Pad U1-25(140.518mm,57.843mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.18mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.18mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Pad U1-26(140.518mm,57.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.238mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Via (140.36mm,58.674mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.238mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.343mm) on Top Layer And Pad U1-27(140.518mm,56.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-26(140.518mm,57.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,56.843mm) on Top Layer And Pad U1-28(140.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-27(140.518mm,56.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.343mm) on Top Layer And Pad U1-29(140.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-28(140.518mm,56.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,55.843mm) on Top Layer And Pad U1-30(140.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-29(140.518mm,55.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.343mm) on Top Layer And Pad U1-4(147.518mm,53.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-3(147.518mm,53.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.343mm) on Top Layer And Pad U1-31(140.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-30(140.518mm,55.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,54.843mm) on Top Layer And Pad U1-32(140.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-31(140.518mm,54.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.343mm) on Top Layer And Pad U1-33(140.518mm,53.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-32(140.518mm,54.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,53.843mm) on Top Layer And Pad U1-34(140.518mm,53.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-33(140.518mm,53.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.343mm) on Top Layer And Pad U1-35(140.518mm,52.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-34(140.518mm,53.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,52.843mm) on Top Layer And Pad U1-36(140.518mm,52.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-35(140.518mm,52.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Pad U1-37(141.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Pad U1-38(141.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.593mm) on Top Layer And Pad U1-39(142.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-38(141.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Pad U1-40(142.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.096mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.096mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-4(147.518mm,53.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,53.843mm) on Top Layer And Pad U1-5(147.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Pad U1-41(143.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.092mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.092mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.593mm) on Top Layer And Pad U1-42(143.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-41(143.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Pad U1-43(144.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.117mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.117mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Pad U1-44(144.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.13mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.13mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.593mm) on Top Layer And Pad U1-45(145.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-44(144.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.593mm) on Top Layer And Pad U1-46(145.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-45(145.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.593mm) on Top Layer And Pad U1-47(146.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-46(145.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.593mm) on Top Layer And Pad U1-48(146.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-47(146.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-48(146.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-5(147.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-6(147.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-7(147.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-8(147.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.343mm) on Top Layer And Pad U1-6(147.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,54.843mm) on Top Layer And Pad U1-7(147.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.343mm) on Top Layer And Pad U1-8(147.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,55.843mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.134mm < 0.254mm) Between Pad U2-3(168.388mm,55.093mm) on Bottom Layer And Via (169.139mm,56.896mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.134mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.059mm < 0.254mm) Between Pad U3-4(163.322mm,60.706mm) on Bottom Layer And Via (161.265mm,59.055mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.059mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.051mm < 0.254mm) Between Pad U4-11(149.484mm,59.08mm) on Bottom Layer And Via (148.107mm,59.055mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.051mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U4-4(143.739mm,56.54mm) on Bottom Layer And Via (145.161mm,57.074mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.253mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.123mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.071mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.071mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.16mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.16mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.111mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.111mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.151mm < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Via (151.105mm,52.146mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.151mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (150.012mm,60.35mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.018mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.095mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (152.832mm,61.011mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.095mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.12mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (152.857mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.12mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.031mm < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Via (161.265mm,59.055mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.031mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.221mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.221mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.17mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Via (145.644mm,59.741mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.17mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Via (140.005mm,63.424mm) from Top Layer to Bottom Layer And Via (140.538mm,62.814mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] / [Bottom Solder] Mask Sliver [0.107mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.184mm < 0.254mm) Between Via (140.538mm,62.814mm) from Top Layer to Bottom Layer And Via (141.402mm,62.611mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.184mm] / [Bottom Solder] Mask Sliver [0.184mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Via (141.707mm,59.588mm) from Top Layer to Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.141mm] / [Bottom Solder] Mask Sliver [0.141mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.086mm < 0.254mm) Between Via (144.856mm,59.69mm) from Top Layer to Bottom Layer And Via (145.644mm,59.741mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.086mm] / [Bottom Solder] Mask Sliver [0.086mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (145.644mm,59.741mm) from Top Layer to Bottom Layer And Via (146.482mm,59.715mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (151.105mm,55.905mm) from Top Layer to Bottom Layer And Via (151.943mm,55.905mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Via (151.661mm,58.417mm) from Top Layer to Bottom Layer And Via (152.578mm,58.191mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.241mm] / [Bottom Solder] Mask Sliver [0.241mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (152.578mm,53.086mm) from Top Layer to Bottom Layer And Via (152.857mm,52.273mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.159mm < 0.254mm) Between Via (152.832mm,61.011mm) from Top Layer to Bottom Layer And Via (153.441mm,61.62mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.159mm] / [Bottom Solder] Mask Sliver [0.159mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (158.699mm,52.934mm) from Top Layer to Bottom Layer And Via (159.537mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Via (161.265mm,59.055mm) from Top Layer to Bottom Layer And Via (161.849mm,58.445mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.141mm] / [Bottom Solder] Mask Sliver [0.141mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (177.343mm,48.108mm) from Top Layer to Bottom Layer And Via (177.343mm,49.035mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (177.343mm,49.035mm) from Top Layer to Bottom Layer And Via (177.343mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (178.841mm,49.035mm) from Top Layer to Bottom Layer And Via (178.841mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (180.162mm,48.108mm) from Top Layer to Bottom Layer And Via (180.162mm,49.035mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm] - Violation between Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (180.162mm,49.035mm) from Top Layer to Bottom Layer And Via (180.162mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm] -Rule Violations :173 + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad C1-2(147.677mm,60.3mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(141.275mm,50.436mm) on Top Layer And Pad C11-2(141.275mm,49.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Pad R1-1(147.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Via (147.93mm,59.487mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.209mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.209mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.166mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.166mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad C18-2(140.64mm,51.991mm) on Bottom Layer And Pad C19-2(140.64mm,50.752mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.236mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.771mm,49.436mm) on Top Layer And Pad C3-2(145.771mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (151.613mm,58.649mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.156mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(144.272mm,49.436mm) on Top Layer And Pad C5-2(144.272mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(143.264mm,60.655mm) on Top Layer And Pad C8-2(144.264mm,60.655mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad P2-2(141.224mm,58.547mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.149mm < 0.254mm) Between Pad P2-3(141.224mm,61.087mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.149mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(147.694mm,61.214mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Pad R2-2(150.343mm,50.995mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.186mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad R2-2(150.343mm,50.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.222mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(176.352mm,57.904mm) on Bottom Layer And Pad R3-2(176.352mm,56.904mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad R6-2(160.325mm,51.918mm) on Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.124mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (148.107mm,51.486mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.124mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.113mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.113mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.234mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.191mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.616mm,56.972mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.191mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.185mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (157.353mm,56.007mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.185mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-2(147.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-11(147.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.749mm) on Top Layer And Pad U1-12(147.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Pad U1-13(146.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Pad U1-14(146.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Pad U1-15(145.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.173mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.173mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Pad U1-16(145.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Pad U1-17(144.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.176mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.999mm) on Top Layer And Pad U1-18(144.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.999mm) on Top Layer And Pad U1-19(143.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.999mm) on Top Layer And Pad U1-20(143.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,53.249mm) on Top Layer And Pad U1-3(147.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.999mm) on Top Layer And Pad U1-21(142.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Pad U1-22(142.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.187mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.187mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Pad U1-23(141.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.121mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.121mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Pad U1-24(141.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.186mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Pad U1-25(140.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Pad U1-26(140.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.749mm) on Top Layer And Pad U1-27(140.518mm,57.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,57.249mm) on Top Layer And Pad U1-28(140.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.749mm) on Top Layer And Pad U1-29(140.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,56.249mm) on Top Layer And Pad U1-30(140.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Pad U1-4(147.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.749mm) on Top Layer And Pad U1-31(140.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,55.249mm) on Top Layer And Pad U1-32(140.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.749mm) on Top Layer And Pad U1-33(140.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,54.249mm) on Top Layer And Pad U1-34(140.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.749mm) on Top Layer And Pad U1-35(140.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,53.249mm) on Top Layer And Pad U1-36(140.518mm,52.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Pad U1-37(141.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.009mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Pad U1-38(141.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.225mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.225mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Pad U1-39(142.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Pad U1-40(142.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.136mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.136mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Pad U1-5(147.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.999mm) on Top Layer And Pad U1-41(143.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.999mm) on Top Layer And Pad U1-42(143.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.999mm) on Top Layer And Pad U1-43(144.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.999mm) on Top Layer And Pad U1-44(144.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.999mm) on Top Layer And Pad U1-45(145.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.999mm) on Top Layer And Pad U1-46(145.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Pad U1-47(146.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.081mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.088mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.088mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.091mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.091mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.087mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.087mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.749mm) on Top Layer And Pad U1-6(147.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,55.249mm) on Top Layer And Pad U1-7(147.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.749mm) on Top Layer And Pad U1-8(147.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,56.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.143mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Via (171.45mm,52.984mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.143mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Pad U4-2(164.367mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-2(164.367mm,53.726mm) on Bottom Layer And Pad U4-3(165.317mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-3(165.317mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.195mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.195mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Via (166.827mm,52.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (148.107mm,51.486mm) from Top Layer to Bottom Layer And Via (148.742mm,50.876mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (148.742mm,50.876mm) from Top Layer to Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.162mm < 0.254mm) Between Via (156.616mm,56.972mm) from Top Layer to Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.162mm] / [Bottom Solder] Mask Sliver [0.162mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (157.353mm,56.007mm) from Top Layer to Bottom Layer And Via (158.064mm,55.423mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (158.818mm,52.9mm) from Top Layer to Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Via (166.827mm,52.248mm) from Top Layer to Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] / [Bottom Solder] Mask Sliver [0.253mm] +Rule Violations :106 Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.998mm) on Bottom Overlay And Pad U4-1(143.739mm,52.73mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.343mm) on Top Overlay And Pad U1-1(147.518mm,52.343mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.922mm) on Bottom Overlay And Pad U5-1(143.739mm,52.654mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.749mm) on Top Overlay And Pad U1-1(147.518mm,52.749mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.699mm,53.878mm) on Bottom Overlay And Pad U4-1(163.417mm,53.726mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.164mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.164mm] Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-1(161.595mm,49.773mm) on Bottom Layer And Track (160.995mm,50.673mm)(162.195mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-2(161.595mm,51.573mm) on Bottom Layer And Track (160.995mm,50.673mm)(162.195mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(163.601mm,49.773mm) on Bottom Layer And Track (163.001mm,50.673mm)(164.201mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(163.601mm,51.573mm) on Bottom Layer And Track (163.001mm,50.673mm)(164.201mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C16-1(165.608mm,49.773mm) on Bottom Layer And Track (165.008mm,50.673mm)(166.208mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C16-2(165.608mm,51.573mm) on Bottom Layer And Track (165.008mm,50.673mm)(166.208mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.254mm) Between Pad C17-1(141.3mm,52.524mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.187mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.186mm < 0.254mm) Between Pad C17-2(141.3mm,53.924mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.186mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C7-1(143.891mm,61.595mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C7-2(143.891mm,60.595mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.22mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (154.284mm,49.142mm)(157.284mm,49.142mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.22mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (154.298mm,51.022mm)(157.298mm,51.022mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.206mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.161mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (155.042mm,50.089mm)(156.566mm,50.089mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.161mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.22mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (154.284mm,49.142mm)(157.284mm,49.142mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.22mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (154.298mm,51.022mm)(157.298mm,51.022mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.206mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.161mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (155.042mm,50.089mm)(156.566mm,50.089mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.161mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,56.72mm)(176.736mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (176.736mm,57.659mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(140.894mm,56.007mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(140.894mm,58.547mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(140.894mm,61.087mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Track (149.332mm,49.396mm)(149.332mm,48.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Track (149.332mm,51.163mm)(149.332mm,51.856mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Track (145.179mm,49.396mm)(145.179mm,48.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Track (145.179mm,51.163mm)(145.179mm,51.856mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (177.532mm,57.587mm)(178.225mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (179.991mm,57.587mm)(180.684mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (177.532mm,53.434mm)(178.225mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (179.991mm,53.434mm)(180.684mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Track (147.594mm,51.517mm)(147.594mm,52.012mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Track (147.594mm,58.173mm)(147.594mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Track (147.098mm,58.669mm)(147.594mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Track (140.442mm,58.669mm)(140.938mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Track (140.442mm,58.173mm)(140.442mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Track (140.442mm,51.517mm)(140.442mm,52.012mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Track (140.442mm,51.517mm)(140.938mm,51.517mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.593mm) on Top Layer And Track (147.098mm,51.517mm)(147.594mm,51.517mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(172.988mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(170.688mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(168.388mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(170.688mm,60.808mm) on Bottom Layer And Track (167.287mm,59.346mm)(174.089mm,59.346mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-4(163.322mm,60.706mm) on Bottom Layer And Track (159.996mm,59.307mm)(166.648mm,59.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-1(143.739mm,52.73mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-10(149.484mm,60.35mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-11(149.484mm,59.08mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-12(149.484mm,57.81mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-13(149.484mm,56.54mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-14(149.484mm,55.27mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-15(149.484mm,54mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-16(149.484mm,52.73mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-2(143.739mm,54mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-3(143.739mm,55.27mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-4(143.739mm,56.54mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-5(143.739mm,57.81mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-8(143.739mm,61.62mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-9(149.484mm,61.62mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(148.49mm,60.135mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (144.433mm,62.293mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.075mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.463mm,50.673mm)(148.463mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.075mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.075mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.075mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.49mm,60.135mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(148.49mm,60.135mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,62.293mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm] -Rule Violations :111 + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(166.903mm,58.714mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(166.903mm,60.514mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.228mm < 0.254mm) Between Pad C18-1(140.64mm,53.391mm) on Bottom Layer And Text "TX" (142.392mm,54.356mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.228mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Text "+" (175.336mm,51.206mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.249mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,54.764mm)(176.787mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (176.787mm,51.425mm)(180.487mm,51.425mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (176.787mm,55.703mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,49.345mm)(148.163mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,51.112mm)(148.163mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,49.345mm)(144.011mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,51.112mm)(144.011mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,58.685mm)(175.687mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,61.838mm)(175.687mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,58.685mm)(179.839mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-1(164.166mm,60.745mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-2(164.166mm,58.445mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (156.54mm,59.106mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (157.175mm,51.994mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (159.96mm,55.119mm)(159.96mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Track (147.594mm,51.923mm)(147.594mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Track (147.594mm,58.58mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Track (147.098mm,59.075mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Track (140.442mm,59.075mm)(140.938mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Track (140.442mm,58.58mm)(140.442mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Track (140.442mm,51.923mm)(140.442mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Track (140.442mm,51.923mm)(140.938mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.999mm) on Top Layer And Track (147.098mm,51.923mm)(147.594mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(173.801mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.076mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.076mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(171.501mm,60.528mm) on Bottom Layer And Track (168.1mm,59.067mm)(174.902mm,59.067mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U4-4(165.317mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U4-5(163.417mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-1(143.739mm,52.654mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-10(149.484mm,60.274mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-11(149.484mm,59.004mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-12(149.484mm,57.734mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-13(149.484mm,56.464mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-14(149.484mm,55.194mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-15(149.484mm,53.924mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-16(149.484mm,52.654mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-2(143.739mm,53.924mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-3(143.739mm,55.194mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-8(143.739mm,61.544mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-9(149.484mm,61.544mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Track (151.486mm,50.597mm)(151.486mm,53.384mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Via (151.486mm,50.597mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0.196mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (150.038mm,61.544mm)(150.52mm,61.062mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (151.13mm,59.995mm)(151.917mm,59.995mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (150.038mm,61.544mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.225mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (151.13mm,59.995mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm] +Rule Violations :110 Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) - Violation between Silk To Silk Clearance Constraint: (0.095mm < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.624mm,54.737mm)(139.624mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.095mm] - Violation between Silk To Silk Clearance Constraint: (0.092mm < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.624mm,54.737mm)(142.164mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.092mm] -Rule Violations :2 + Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Text "+" (175.336mm,51.206mm) on Bottom Overlay And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay Silk Text to Silk Clearance [0.195mm] + Violation between Silk To Silk Clearance Constraint: (0.07mm < 0.254mm) Between Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay And Track (142.494mm,54.737mm)(142.494mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.07mm] + Violation between Silk To Silk Clearance Constraint: (0.129mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (175.687mm,61.838mm)(179.839mm,61.838mm) on Bottom Overlay Silk Text to Silk Clearance [0.129mm] + Violation between Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm] + Violation between Silk To Silk Clearance Constraint: (0.206mm < 0.254mm) Between Text "TX" (142.392mm,54.356mm) on Bottom Overlay And Track (139.954mm,54.737mm)(142.494mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.206mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (168.605mm,51.867mm) on Bottom Overlay And Track (165.918mm,51.677mm)(165.918mm,53.479mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] +Rule Violations :6 Processing Rule : Net Antennae (Tolerance=0mm) (All) Rule Violations :0 @@ -329,6 +265,6 @@ Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Al Rule Violations :0 -Violations Detected : 286 +Violations Detected : 222 Waived Violations : 0 -Time Elapsed : 00:00:02 \ No newline at end of file +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html b/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html index 53ab6ec..7c3d65d 100644 --- a/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html +++ b/植物探头/使用时间监测模块/Project Outputs for PCB_Project2/Design Rule Check - PCB1.html @@ -219,22 +219,22 @@ Date: -2022/5/7 +2022/6/30 Time: -14:08:10 +13:25:17 Elapsed Time: -00:00:02 +00:00:01 Filename: -C:\Users\hu123456\Desktop\ֲ̽ͷ\ʹʱģ\PCB1.PcbDoc +C:\Users\hu123456\Desktop\ʹʱģ\PCB1.PcbDoc @@ -247,10 +247,10 @@ Rule Violations: -286 +222 -

Summary

 +

Summary

 @@ -265,930 +265,738 @@ - + - + - + - + - + - + - + - + - - + + - - + + - - + + - + - + - + -
Warnings CountCount
Clearance Constraint (Gap=0.2mm) (All),(All)Clearance Constraint (Gap=0.2mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All)Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) )Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No)Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)173Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)106
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)111Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)110
Silk to Silk (Clearance=0.254mm) (All),(All)2Silk to Silk (Clearance=0.254mm) (All),(All)6
Net Antennae (Tolerance=0mm) (All)Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total286222

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C10-1(141.91mm,48.971mm) on Top Layer And Pad C10-2(141.91mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad C1-2(147.677mm,60.3mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.062mm < 0.254mm) Between Pad C10-2(141.91mm,49.971mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.062mm]
Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Pad C1-2(140.648mm,61.747mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(141.275mm,50.436mm) on Top Layer And Pad C11-2(141.275mm,49.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Pad R1-2(141.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.237mm]
Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Pad R1-1(147.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
Minimum Solder Mask Sliver Constraint: (0.16mm < 0.254mm) Between Pad C1-1(141.648mm,61.747mm) on Top Layer And Via (141.402mm,62.611mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.16mm]
Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Via (147.93mm,59.487mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Pad C11-2(143.241mm,48.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.209mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.209mm]
Minimum Solder Mask Sliver Constraint: (0.069mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.069mm]
Minimum Solder Mask Sliver Constraint: (0.166mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.166mm]
Minimum Solder Mask Sliver Constraint: (0.057mm < 0.254mm) Between Pad C11-1(143.241mm,49.971mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.057mm]
Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad C18-2(140.64mm,51.991mm) on Bottom Layer And Pad C19-2(140.64mm,50.752mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.236mm]
Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad C1-2(140.648mm,61.747mm) on Top Layer And Pad R1-1(140.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.237mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.771mm,49.436mm) on Top Layer And Pad C3-2(145.771mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.138mm < 0.254mm) Between Pad C18-2(141.3mm,50.981mm) on Bottom Layer And Via (140.259mm,51.333mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.138mm]
Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (151.613mm,58.649mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.156mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C2-1(144.572mm,49.971mm) on Top Layer And Pad C2-2(144.572mm,48.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm]
Minimum Solder Mask Sliver Constraint: (0.041mm < 0.254mm) Between Pad C2-1(144.572mm,49.971mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.041mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(144.272mm,49.436mm) on Top Layer And Pad C5-2(144.272mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.903mm,48.971mm) on Top Layer And Pad C3-2(145.903mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(143.264mm,60.655mm) on Top Layer And Pad C8-2(144.264mm,60.655mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.248mm < 0.254mm) Between Pad C4-1(155.931mm,53.086mm) on Bottom Layer And Via (153.441mm,51.232mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.248mm]
Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad P2-2(141.224mm,58.547mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm]
Minimum Solder Mask Sliver Constraint: (0.131mm < 0.254mm) Between Pad C4-2(155.931mm,60.706mm) on Bottom Layer And Via (153.441mm,61.62mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.131mm]
Minimum Solder Mask Sliver Constraint: (0.149mm < 0.254mm) Between Pad P2-3(141.224mm,61.087mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.149mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(147.234mm,48.971mm) on Top Layer And Pad C5-2(147.234mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(147.694mm,61.214mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Pad C6-2(149.174mm,61.943mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Pad R2-2(150.343mm,50.995mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.171mm < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Via (150.012mm,60.35mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.171mm]
Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.186mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C7-1(143.891mm,61.595mm) on Top Layer And Pad C7-2(143.891mm,60.595mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad R2-2(150.343mm,50.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.222mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(142.85mm,61.587mm) on Top Layer And Pad C8-2(142.85mm,60.587mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(176.352mm,57.904mm) on Bottom Layer And Pad R3-2(176.352mm,56.904mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.144mm < 0.254mm) Between Pad C8-2(142.85mm,60.587mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.144mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad R6-2(160.325mm,51.918mm) on Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C9-1(140.579mm,48.971mm) on Top Layer And Pad C9-2(140.579mm,49.971mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.124mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (148.107mm,51.486mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.124mm]
Minimum Solder Mask Sliver Constraint: (0.204mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Via (153.213mm,49.047mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.204mm]
Minimum Solder Mask Sliver Constraint: (0.113mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.113mm]
Minimum Solder Mask Sliver Constraint: (0.138mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Via (153.441mm,51.232mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.138mm]
Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.234mm]
Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Via (175.666mm,57.125mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm]
Minimum Solder Mask Sliver Constraint: (0.191mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.616mm,56.972mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.191mm]
Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Via (179.73mm,53.797mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.097mm]
Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm]
Minimum Solder Mask Sliver Constraint: (0.118mm < 0.254mm) Between Pad P2-2(140.894mm,58.547mm) on Bottom Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.118mm]
Minimum Solder Mask Sliver Constraint: (0.185mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (157.353mm,56.007mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.185mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R?-1(179.638mm,60.35mm) on Top Layer And Pad R?-2(178.638mm,60.35mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-2(147.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(140.648mm,60.808mm) on Top Layer And Pad R1-2(141.648mm,60.808mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(151.689mm,49.563mm) on Bottom Layer And Pad R2-2(151.689mm,50.563mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-11(147.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.108mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (148.305mm,51.505mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.108mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.175mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (148.615mm,48.971mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.175mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.749mm) on Top Layer And Pad U1-12(147.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.175mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Via (149.631mm,48.971mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.175mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Pad U1-13(146.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.086mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.086mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Pad U1-14(146.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.229mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Via (177.952mm,56.236mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.229mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Pad U1-15(145.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-2(147.518mm,52.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.173mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.173mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-48(146.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Pad U1-16(145.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-11(147.518mm,57.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Pad U1-17(144.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.176mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,56.843mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.999mm) on Top Layer And Pad U1-18(144.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.343mm) on Top Layer And Pad U1-12(147.518mm,57.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.999mm) on Top Layer And Pad U1-19(143.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-11(147.518mm,57.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.999mm) on Top Layer And Pad U1-20(143.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Pad U1-13(146.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,53.249mm) on Top Layer And Pad U1-3(147.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.999mm) on Top Layer And Pad U1-21(142.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Pad U1-14(146.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Pad U1-22(142.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.187mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.187mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.593mm) on Top Layer And Pad U1-15(145.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Pad U1-23(141.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-14(146.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.121mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.121mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.593mm) on Top Layer And Pad U1-16(145.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Pad U1-24(141.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-15(145.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.186mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.593mm) on Top Layer And Pad U1-17(144.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Pad U1-25(140.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-16(145.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Pad U1-18(144.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Pad U1-26(140.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.749mm) on Top Layer And Pad U1-27(140.518mm,57.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad U1-17(144.768mm,58.593mm) on Top Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.244mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,57.249mm) on Top Layer And Pad U1-28(140.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.593mm) on Top Layer And Pad U1-19(143.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.749mm) on Top Layer And Pad U1-29(140.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-18(144.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,56.249mm) on Top Layer And Pad U1-30(140.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.593mm) on Top Layer And Pad U1-20(143.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Pad U1-4(147.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-19(143.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,52.843mm) on Top Layer And Pad U1-3(147.518mm,53.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.749mm) on Top Layer And Pad U1-31(140.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-2(147.518mm,52.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,55.249mm) on Top Layer And Pad U1-32(140.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.593mm) on Top Layer And Pad U1-21(142.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.749mm) on Top Layer And Pad U1-33(140.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-20(143.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,54.249mm) on Top Layer And Pad U1-34(140.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Pad U1-22(142.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.749mm) on Top Layer And Pad U1-35(140.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,53.249mm) on Top Layer And Pad U1-36(140.518mm,52.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad U1-21(142.768mm,58.593mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.244mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Pad U1-37(141.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Pad U1-23(141.768mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Pad U1-38(141.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.225mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.225mm]
Minimum Solder Mask Sliver Constraint: (0.237mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.237mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Pad U1-39(142.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.245mm < 0.254mm) Between Pad U1-22(142.268mm,58.593mm) on Top Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.245mm]
Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Pad U1-24(141.268mm,58.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Pad U1-40(142.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.136mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.136mm]
Minimum Solder Mask Sliver Constraint: (0.142mm < 0.254mm) Between Pad U1-23(141.768mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.142mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Pad U1-5(147.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Pad U1-25(140.518mm,57.843mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.999mm) on Top Layer And Pad U1-41(143.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.18mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Via (141.707mm,59.588mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.18mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.999mm) on Top Layer And Pad U1-42(143.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Pad U1-26(140.518mm,57.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.999mm) on Top Layer And Pad U1-43(144.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.999mm) on Top Layer And Pad U1-44(144.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.238mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Via (140.36mm,58.674mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.238mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.999mm) on Top Layer And Pad U1-45(145.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.343mm) on Top Layer And Pad U1-27(140.518mm,56.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.999mm) on Top Layer And Pad U1-46(145.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-26(140.518mm,57.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Pad U1-47(146.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,56.843mm) on Top Layer And Pad U1-28(140.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.081mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-27(140.518mm,56.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.343mm) on Top Layer And Pad U1-29(140.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.088mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.088mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-28(140.518mm,56.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.091mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.091mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,55.843mm) on Top Layer And Pad U1-30(140.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.087mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.087mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-29(140.518mm,55.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.343mm) on Top Layer And Pad U1-4(147.518mm,53.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-3(147.518mm,53.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.749mm) on Top Layer And Pad U1-6(147.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.343mm) on Top Layer And Pad U1-31(140.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,55.249mm) on Top Layer And Pad U1-7(147.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-30(140.518mm,55.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.749mm) on Top Layer And Pad U1-8(147.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,54.843mm) on Top Layer And Pad U1-32(140.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,56.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-31(140.518mm,54.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.143mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Via (171.45mm,52.984mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.143mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.343mm) on Top Layer And Pad U1-33(140.518mm,53.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Pad U4-2(164.367mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-32(140.518mm,54.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,53.843mm) on Top Layer And Pad U1-34(140.518mm,53.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-2(164.367mm,53.726mm) on Bottom Layer And Pad U4-3(165.317mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-33(140.518mm,53.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-3(165.317mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.343mm) on Top Layer And Pad U1-35(140.518mm,52.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.195mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.195mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-34(140.518mm,53.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Via (166.827mm,52.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,52.843mm) on Top Layer And Pad U1-36(140.518mm,52.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (148.107mm,51.486mm) from Top Layer to Bottom Layer And Via (148.742mm,50.876mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-35(140.518mm,52.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (148.742mm,50.876mm) from Top Layer to Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm]
Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Pad U1-37(141.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
Minimum Solder Mask Sliver Constraint: (0.162mm < 0.254mm) Between Via (156.616mm,56.972mm) from Top Layer to Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.162mm] / [Bottom Solder] Mask Sliver [0.162mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (157.353mm,56.007mm) from Top Layer to Bottom Layer And Via (158.064mm,55.423mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Pad U1-38(141.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (158.818mm,52.9mm) from Top Layer to Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Via (166.827mm,52.248mm) from Top Layer to Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] / [Bottom Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.593mm) on Top Layer And Pad U1-39(142.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-38(141.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Pad U1-40(142.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.096mm < 0.254mm) Between Pad U1-39(142.268mm,51.593mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.096mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-4(147.518mm,53.843mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,53.843mm) on Top Layer And Pad U1-5(147.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Pad U1-41(143.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.092mm < 0.254mm) Between Pad U1-40(142.768mm,51.593mm) on Top Layer And Via (142.57mm,50.648mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.092mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.593mm) on Top Layer And Pad U1-42(143.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-41(143.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Pad U1-43(144.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.117mm < 0.254mm) Between Pad U1-42(143.768mm,51.593mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.117mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Pad U1-44(144.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.13mm < 0.254mm) Between Pad U1-43(144.268mm,51.593mm) on Top Layer And Via (143.916mm,50.622mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.13mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.593mm) on Top Layer And Pad U1-45(145.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-44(144.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.593mm) on Top Layer And Pad U1-46(145.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-45(145.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.593mm) on Top Layer And Pad U1-47(146.268mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-46(145.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.593mm) on Top Layer And Pad U1-48(146.768mm,51.593mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-47(146.268mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-48(146.768mm,51.593mm) on Top Layer And Pad U1-49(144.018mm,55.093mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-5(147.518mm,54.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-6(147.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-7(147.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-8(147.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad U1-49(144.018mm,55.093mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.343mm) on Top Layer And Pad U1-6(147.518mm,54.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,54.843mm) on Top Layer And Pad U1-7(147.518mm,55.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.343mm) on Top Layer And Pad U1-8(147.518mm,55.843mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,55.843mm) on Top Layer And Pad U1-9(147.518mm,56.343mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
Minimum Solder Mask Sliver Constraint: (0.134mm < 0.254mm) Between Pad U2-3(168.388mm,55.093mm) on Bottom Layer And Via (169.139mm,56.896mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.134mm]
Minimum Solder Mask Sliver Constraint: (0.059mm < 0.254mm) Between Pad U3-4(163.322mm,60.706mm) on Bottom Layer And Via (161.265mm,59.055mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.059mm]
Minimum Solder Mask Sliver Constraint: (0.051mm < 0.254mm) Between Pad U4-11(149.484mm,59.08mm) on Bottom Layer And Via (148.107mm,59.055mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.051mm]
Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U4-4(143.739mm,56.54mm) on Bottom Layer And Via (145.161mm,57.074mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.253mm]
Minimum Solder Mask Sliver Constraint: (0.123mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.123mm]
Minimum Solder Mask Sliver Constraint: (0.071mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.071mm]
Minimum Solder Mask Sliver Constraint: (0.16mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.16mm]
Minimum Solder Mask Sliver Constraint: (0.111mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.111mm]
Minimum Solder Mask Sliver Constraint: (0.151mm < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Via (151.105mm,52.146mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.151mm]
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (150.012mm,60.35mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.018mm]
Minimum Solder Mask Sliver Constraint: (0.095mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (152.832mm,61.011mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.095mm]
Minimum Solder Mask Sliver Constraint: (0.12mm < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Via (152.857mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.12mm]
Minimum Solder Mask Sliver Constraint: (0.031mm < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Via (161.265mm,59.055mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.031mm]
Minimum Solder Mask Sliver Constraint: (0.221mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Via (144.856mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.221mm]
Minimum Solder Mask Sliver Constraint: (0.17mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Via (145.644mm,59.741mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.17mm]
Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Via (140.005mm,63.424mm) from Top Layer to Bottom Layer And Via (140.538mm,62.814mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm] / [Bottom Solder] Mask Sliver [0.107mm]
Minimum Solder Mask Sliver Constraint: (0.184mm < 0.254mm) Between Via (140.538mm,62.814mm) from Top Layer to Bottom Layer And Via (141.402mm,62.611mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.184mm] / [Bottom Solder] Mask Sliver [0.184mm]
Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Via (141.707mm,59.588mm) from Top Layer to Bottom Layer And Via (142.545mm,59.69mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.141mm] / [Bottom Solder] Mask Sliver [0.141mm]
Minimum Solder Mask Sliver Constraint: (0.086mm < 0.254mm) Between Via (144.856mm,59.69mm) from Top Layer to Bottom Layer And Via (145.644mm,59.741mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.086mm] / [Bottom Solder] Mask Sliver [0.086mm]
Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (145.644mm,59.741mm) from Top Layer to Bottom Layer And Via (146.482mm,59.715mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm]
Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (151.105mm,55.905mm) from Top Layer to Bottom Layer And Via (151.943mm,55.905mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm]
Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Via (151.661mm,58.417mm) from Top Layer to Bottom Layer And Via (152.578mm,58.191mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.241mm] / [Bottom Solder] Mask Sliver [0.241mm]
Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (152.578mm,53.086mm) from Top Layer to Bottom Layer And Via (152.857mm,52.273mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm]
Minimum Solder Mask Sliver Constraint: (0.159mm < 0.254mm) Between Via (152.832mm,61.011mm) from Top Layer to Bottom Layer And Via (153.441mm,61.62mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.159mm] / [Bottom Solder] Mask Sliver [0.159mm]
Minimum Solder Mask Sliver Constraint: (0.135mm < 0.254mm) Between Via (158.699mm,52.934mm) from Top Layer to Bottom Layer And Via (159.537mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.135mm] / [Bottom Solder] Mask Sliver [0.135mm]
Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Via (161.265mm,59.055mm) from Top Layer to Bottom Layer And Via (161.849mm,58.445mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.141mm] / [Bottom Solder] Mask Sliver [0.141mm]
Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (177.343mm,48.108mm) from Top Layer to Bottom Layer And Via (177.343mm,49.035mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm]
Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (177.343mm,49.035mm) from Top Layer to Bottom Layer And Via (177.343mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm]
Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (178.841mm,49.035mm) from Top Layer to Bottom Layer And Via (178.841mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm]
Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (180.162mm,48.108mm) from Top Layer to Bottom Layer And Via (180.162mm,49.035mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm]
Minimum Solder Mask Sliver Constraint: (0.224mm < 0.254mm) Between Via (180.162mm,49.035mm) from Top Layer to Bottom Layer And Via (180.162mm,49.962mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.224mm] / [Bottom Solder] Mask Sliver [0.224mm]
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- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - -
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.998mm) on Bottom Overlay And Pad U4-1(143.739mm,52.73mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.922mm) on Bottom Overlay And Pad U5-1(143.739mm,52.654mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.343mm) on Top Overlay And Pad U1-1(147.518mm,52.343mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm]
Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.749mm) on Top Overlay And Pad U1-1(147.518mm,52.749mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.699mm,53.878mm) on Bottom Overlay And Pad U4-1(163.417mm,53.726mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-1(161.595mm,49.773mm) on Bottom Layer And Track (160.995mm,50.673mm)(162.195mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.164mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.164mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-2(161.595mm,51.573mm) on Bottom Layer And Track (160.995mm,50.673mm)(162.195mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(163.601mm,49.773mm) on Bottom Layer And Track (163.001mm,50.673mm)(164.201mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(163.601mm,51.573mm) on Bottom Layer And Track (163.001mm,50.673mm)(164.201mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C16-1(165.608mm,49.773mm) on Bottom Layer And Track (165.008mm,50.673mm)(166.208mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(166.903mm,58.714mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C16-2(165.608mm,51.573mm) on Bottom Layer And Track (165.008mm,50.673mm)(166.208mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(166.903mm,60.514mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.187mm < 0.254mm) Between Pad C17-1(141.3mm,52.524mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.187mm]
Silk To Solder Mask Clearance Constraint: (0.228mm < 0.254mm) Between Pad C18-1(140.64mm,53.391mm) on Bottom Layer And Text "TX" (142.392mm,54.356mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.228mm]
Silk To Solder Mask Clearance Constraint: (0.186mm < 0.254mm) Between Pad C17-2(141.3mm,53.924mm) on Bottom Layer And Text "TX" (140.589mm,52.756mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.186mm]
Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Text "+" (175.336mm,51.206mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.249mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C6-1(149.174mm,60.943mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C7-1(143.891mm,61.595mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C7-2(143.891mm,60.595mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.22mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (154.284mm,49.142mm)(157.284mm,49.142mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.22mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,54.764mm)(176.787mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (154.298mm,51.022mm)(157.298mm,51.022mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.206mm]
Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (176.787mm,51.425mm)(180.487mm,51.425mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm]
Silk To Solder Mask Clearance Constraint: (0.161mm < 0.254mm) Between Pad D?-1(157.354mm,50.089mm) on Bottom Layer And Track (155.042mm,50.089mm)(156.566mm,50.089mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.161mm]
Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm]
Silk To Solder Mask Clearance Constraint: (0.22mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (154.284mm,49.142mm)(157.284mm,49.142mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.22mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (176.787mm,55.703mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (154.298mm,51.022mm)(157.298mm,51.022mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.206mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.161mm < 0.254mm) Between Pad D?-2(154.254mm,50.089mm) on Bottom Layer And Track (155.042mm,50.089mm)(156.566mm,50.089mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.161mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,49.345mm)(148.163mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,53.381mm)(176.736mm,54.308mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,51.112mm)(148.163mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(175.971mm,54.889mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,49.345mm)(144.011mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,55.471mm)(176.736mm,55.558mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,51.112mm)(144.011mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(175.971mm,56.139mm) on Bottom Layer And Track (176.736mm,56.72mm)(176.736mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,58.685mm)(175.687mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (176.736mm,53.381mm)(180.436mm,53.381mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,61.838mm)(175.687mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.06mm,52.047mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,58.685mm)(179.839mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (176.736mm,57.659mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.061mm,58.989mm) on Bottom Layer And Track (180.436mm,53.391mm)(180.436mm,57.659mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-1(164.166mm,60.745mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(140.894mm,56.007mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-2(164.166mm,58.445mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(140.894mm,58.547mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(140.894mm,61.087mm) on Bottom Layer And Text "DEBUG" (141.351mm,56.388mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (156.54mm,59.106mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Track (149.332mm,49.396mm)(149.332mm,48.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (157.175mm,51.994mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(149.29mm,50.279mm) on Bottom Layer And Track (149.332mm,51.163mm)(149.332mm,51.856mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (159.96mm,55.119mm)(159.96mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Track (145.179mm,49.396mm)(145.179mm,48.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Track (147.594mm,51.923mm)(147.594mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(145.22mm,50.279mm) on Bottom Layer And Track (145.179mm,51.163mm)(145.179mm,51.856mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Track (147.594mm,58.58mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (177.532mm,57.587mm)(178.225mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Track (147.098mm,59.075mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(179.108mm,57.546mm) on Top Layer And Track (179.991mm,57.587mm)(180.684mm,57.587mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (177.532mm,53.434mm)(178.225mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.108mm,53.476mm) on Top Layer And Track (179.991mm,53.434mm)(180.684mm,53.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Track (140.442mm,59.075mm)(140.938mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm]
Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.343mm) on Top Layer And Track (147.594mm,51.517mm)(147.594mm,52.012mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Track (140.442mm,58.58mm)(140.442mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,57.843mm) on Top Layer And Track (147.594mm,58.173mm)(147.594mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Track (140.442mm,51.923mm)(140.442mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.593mm) on Top Layer And Track (147.098mm,58.669mm)(147.594mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Track (140.442mm,51.923mm)(140.938mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.593mm) on Top Layer And Track (140.442mm,58.669mm)(140.938mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.999mm) on Top Layer And Track (147.098mm,51.923mm)(147.594mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,57.843mm) on Top Layer And Track (140.442mm,58.173mm)(140.442mm,58.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(173.801mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.343mm) on Top Layer And Track (140.442mm,51.517mm)(140.442mm,52.012mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.593mm) on Top Layer And Track (140.442mm,51.517mm)(140.938mm,51.517mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.076mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.076mm]
Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.593mm) on Top Layer And Track (147.098mm,51.517mm)(147.594mm,51.517mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(172.988mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(171.501mm,60.528mm) on Bottom Layer And Track (168.1mm,59.067mm)(174.902mm,59.067mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(170.688mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U4-4(165.317mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(168.388mm,55.093mm) on Bottom Layer And Track (167.287mm,56.554mm)(174.089mm,56.554mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U4-5(163.417mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(170.688mm,60.808mm) on Bottom Layer And Track (167.287mm,59.346mm)(174.089mm,59.346mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-1(143.739mm,52.654mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U3-4(163.322mm,60.706mm) on Bottom Layer And Track (159.996mm,59.307mm)(166.648mm,59.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-10(149.484mm,60.274mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-1(143.739mm,52.73mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-11(149.484mm,59.004mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-10(149.484mm,60.35mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-12(149.484mm,57.734mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-11(149.484mm,59.08mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-13(149.484mm,56.464mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-12(149.484mm,57.81mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-14(149.484mm,55.194mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-13(149.484mm,56.54mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-15(149.484mm,53.924mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-14(149.484mm,55.27mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-16(149.484mm,52.654mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-15(149.484mm,54mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-2(143.739mm,53.924mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-16(149.484mm,52.73mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-3(143.739mm,55.194mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-2(143.739mm,54mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-3(143.739mm,55.27mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-4(143.739mm,56.54mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-5(143.739mm,57.81mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-6(143.739mm,59.08mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-7(143.739mm,60.35mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U4-8(143.739mm,61.62mm) on Bottom Layer And Track (144.84mm,52.099mm)(144.84mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U4-9(149.484mm,61.62mm) on Bottom Layer And Track (148.383mm,52.099mm)(148.383mm,62.252mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-8(143.739mm,61.544mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(151.384mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-9(149.484mm,61.544mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(151.384mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Track (151.486mm,50.597mm)(151.486mm,53.384mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Via (151.486mm,50.597mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0.196mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (150.038mm,61.544mm)(150.52mm,61.062mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (151.13mm,59.995mm)(151.917mm,59.995mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (150.038mm,61.544mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.225mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (151.13mm,59.995mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U5-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(148.49mm,60.135mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (144.433mm,62.293mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.075mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.463mm,50.673mm)(148.463mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.075mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.075mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.075mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-1(147.736mm,61.214mm) on Top Layer And Track (148.49mm,60.135mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(144.433mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,60.135mm)(148.49mm,60.135mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad Y?-2(145.186mm,61.214mm) on Top Layer And Track (144.433mm,62.293mm)(148.49mm,62.293mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.095mm < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.624mm,54.737mm)(139.624mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.095mm]
Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Text "+" (175.336mm,51.206mm) on Bottom Overlay And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay Silk Text to Silk Clearance [0.195mm]
Silk To Silk Clearance Constraint: (0.092mm < 0.254mm) Between Text "TX" (140.589mm,52.756mm) on Bottom Overlay And Track (139.624mm,54.737mm)(142.164mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.092mm]
Silk To Silk Clearance Constraint: (0.07mm < 0.254mm) Between Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay And Track (142.494mm,54.737mm)(142.494mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.07mm]
Silk To Silk Clearance Constraint: (0.129mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (175.687mm,61.838mm)(179.839mm,61.838mm) on Bottom Overlay Silk Text to Silk Clearance [0.129mm]
Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm]
Silk To Silk Clearance Constraint: (0.206mm < 0.254mm) Between Text "TX" (142.392mm,54.356mm) on Bottom Overlay And Track (139.954mm,54.737mm)(142.494mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.206mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (168.605mm,51.867mm) on Bottom Overlay And Track (165.918mm,51.677mm)(165.918mm,53.479mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
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diff --git a/植物探头/使用时间监测模块/Sheet1.SchDoc b/植物探头/使用时间监测模块/Sheet1.SchDoc index b8a5776..d03afd3 100644 Binary files a/植物探头/使用时间监测模块/Sheet1.SchDoc and b/植物探头/使用时间监测模块/Sheet1.SchDoc differ diff --git a/植物探头/使用时间监测模块/TLV62568A.PcbLib b/植物探头/使用时间监测模块/TLV62568A.PcbLib new file mode 100644 index 0000000..f880bd8 Binary files /dev/null and b/植物探头/使用时间监测模块/TLV62568A.PcbLib differ diff --git a/植物探头/使用时间监测模块/TLV62568A.SchLib b/植物探头/使用时间监测模块/TLV62568A.SchLib new file mode 100644 index 0000000..ac8ff54 Binary files /dev/null and b/植物探头/使用时间监测模块/TLV62568A.SchLib differ diff --git a/植物探头/使用时间监测模块/XAL4020-102ME.PcbLib b/植物探头/使用时间监测模块/XAL4020-102ME.PcbLib new file mode 100644 index 0000000..836c447 Binary files /dev/null and b/植物探头/使用时间监测模块/XAL4020-102ME.PcbLib differ diff --git a/植物探头/使用时间监测模块/使用时间检测22.6.30.rar b/植物探头/使用时间监测模块/使用时间检测22.6.30.rar new file mode 100644 index 0000000..6a261a8 Binary files /dev/null and b/植物探头/使用时间监测模块/使用时间检测22.6.30.rar differ diff --git a/气象站/1_Sheet_1.schdoc b/气象站/1_Sheet_1.schdoc index 16da144..4e4f205 100644 Binary files a/气象站/1_Sheet_1.schdoc and b/气象站/1_Sheet_1.schdoc differ diff --git a/气象站/Copy of Copy of PCB1.PcbDoc b/气象站/Copy of Copy of PCB1.PcbDoc index cbe076f..835b6ae 100644 Binary files a/气象站/Copy of Copy of PCB1.PcbDoc and b/气象站/Copy of Copy of PCB1.PcbDoc differ diff --git a/气象站/光谱气象站22.7.14.rar b/气象站/光谱气象站22.7.14.rar new file mode 100644 index 0000000..eaf6eac Binary files /dev/null and b/气象站/光谱气象站22.7.14.rar differ diff --git a/逐日系统/LM340-5.PcbLib b/逐日系统/LM340-5.PcbLib new file mode 100644 index 0000000..e296415 Binary files /dev/null and b/逐日系统/LM340-5.PcbLib differ diff --git a/逐日系统/PCB1.PcbDoc b/逐日系统/PCB1.PcbDoc new file mode 100644 index 0000000..4cceaa0 Binary files /dev/null and b/逐日系统/PCB1.PcbDoc differ diff --git a/逐日系统/PCB_Project1.PrjPCB b/逐日系统/PCB_Project1.PrjPCB new file mode 100644 index 0000000..5eb3fe0 --- /dev/null +++ b/逐日系统/PCB_Project1.PrjPCB @@ -0,0 +1,1086 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=TDA2822MTR.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=CDQELBKB + +[Document2] +DocumentPath=Sheet1.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=AVPYJHIV + +[Document3] +DocumentPath=PCB1.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=PYVUIJLO + +[Document4] +DocumentPath=LM340-5.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=BCNKLRMC + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=ComponentCrossReference +OutputName2=Component Cross Reference Report +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=ReportHierarchy +OutputName3=Report Project Hierarchy +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +OutputType4=Script +OutputName4=Script Output +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=SimpleBOM +OutputName5=Simple BOM +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=SinglePinNetReporter +OutputName6=Report Single Pin Nets +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Text Print +OutputName3=Text Print +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Text Print +OutputName4=Text Print +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Text Print +OutputName5=Text Print +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Text Print +OutputName6=Text Print +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=Text Print +OutputName7=Text Print +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Text Print +OutputName8=Text Print +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Text Print +OutputName9=Text Print +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=Text Print +OutputName10=Text Print +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType11=Text Print +OutputName11=Text Print +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Text Print +OutputName12=Text Print +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType13=Text Print +OutputName13=Text Print +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType14=Text Print +OutputName14=Text Print +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType15=Text Print +OutputName15=Text Print +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType16=Text Print +OutputName16=Text Print +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType17=Text Print +OutputName17=Text Print +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType18=Text Print +OutputName18=Text Print +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType19=Text Print +OutputName19=Text Print +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType20=Text Print +OutputName20=Text Print +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType21=Text Print +OutputName21=Text Print +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType22=Text Print +OutputName22=Text Print +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType23=Text Print +OutputName23=Text Print +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 +PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType24=Text Print +OutputName24=Text Print +OutputDocumentPath24= +OutputVariantName24= +OutputDefault24=0 +PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType25=Text Print +OutputName25=Text Print +OutputDocumentPath25= +OutputVariantName25= +OutputDefault25=0 +PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType26=Text Print +OutputName26=Text Print +OutputDocumentPath26= +OutputVariantName26= +OutputDefault26=0 +PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType27=Text Print +OutputName27=Text Print +OutputDocumentPath27= +OutputVariantName27= +OutputDefault27=0 +PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Electrical Rules Check +OutputName5=Electrical Rules Check +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=Footprint Comparison Report +OutputName6=Footprint Comparison Report +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 +Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 +Type75=1 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=1 +Type81=1 +Type82=1 +Type83=1 +Type84=1 +Type85=1 +Type86=1 +Type87=1 +Type88=1 +Type89=1 +Type90=1 +Type91=1 +Type92=1 +Type93=1 +Type94=1 +Type95=1 +Type96=1 +Type97=1 +Type98=1 +Type99=1 +Type100=1 +Type101=1 +Type102=1 +Type103=1 +Type104=1 +Type105=1 +Type106=1 +Type107=1 +Type108=1 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=1 +Type115=1 +Type116=1 + +[Difference Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=1 +Type33=1 +Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 +Type46=1 +Type47=1 +Type48=1 +Type49=1 +Type50=1 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=1 +Type57=1 +Type58=1 +Type59=1 +Type60=1 +Type61=1 +Type62=1 +Type63=1 +Type64=1 +Type65=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=2 +Type4=1 +Type5=2 +Type6=2 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=1 +Type32=2 +Type33=2 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + diff --git a/逐日系统/PCB_Project1.PrjPCBStructure b/逐日系统/PCB_Project1.PrjPCBStructure new file mode 100644 index 0000000..985c898 --- /dev/null +++ b/逐日系统/PCB_Project1.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=Sheet1.SchDoc diff --git a/逐日系统/Sheet1.SchDoc b/逐日系统/Sheet1.SchDoc new file mode 100644 index 0000000..1423414 Binary files /dev/null and b/逐日系统/Sheet1.SchDoc differ diff --git a/逐日系统/TDA2822MTR.PcbLib b/逐日系统/TDA2822MTR.PcbLib new file mode 100644 index 0000000..564daa3 Binary files /dev/null and b/逐日系统/TDA2822MTR.PcbLib differ