diff --git a/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.drc b/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.drc new file mode 100644 index 0000000..b8ab3a9 --- /dev/null +++ b/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.drc @@ -0,0 +1,211 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\fsa1\BODY\FSA_Body_PCB ΢20211217_2022-06-23.pcbdoc +Date : 2022/6/23 +Time : 17:51:24 + +Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All) + Violation between Clearance Constraint: (0.061mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (62.155mm,54.268mm)(62.155mm,66.268mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-1(39.497mm,72.009mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-2(39.497mm,69.469mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-25(77.343mm,72.009mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-26(77.343mm,69.469mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-27(77.343mm,66.929mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-28(77.343mm,64.389mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-29(77.343mm,61.849mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-3(39.497mm,66.929mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-30(77.343mm,59.309mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-31(77.343mm,56.769mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-32(77.343mm,54.229mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-33(77.343mm,51.689mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-34(77.343mm,49.149mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-35(77.343mm,46.609mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-36(77.343mm,44.069mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-4(39.497mm,64.389mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-48(76.167mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-5(39.497mm,61.849mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-6(39.497mm,59.309mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-7(39.497mm,56.769mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-8(39.497mm,54.229mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer +Rule Violations :29 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.172mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Via (65.943mm,57.806mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.172mm] +Rule Violations :1 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-11(39.497mm,46.609mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-12(39.497mm,44.069mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-38(42.037mm,49.149mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-49(40.767mm,40.419mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.148mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad U1-2(46.72mm,47.387mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,51.04mm)(48.016mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,54.821mm)(48.016mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,51.04mm)(55.616mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,54.821mm)(55.616mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Text "IN1" (64.77mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (63.691mm,49.092mm)(65.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Text "IN2" (69.469mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (69.422mm,49.092mm)(71.691mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,49.092mm)(71.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,53.645mm)(71.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,49.092mm)(63.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,53.645mm)(63.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (70.174mm,55.984mm)(71.14mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.171mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Text "v" (65.815mm,55.105mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.171mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (65.174mm,55.984mm)(65.461mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,55.984mm)(71.193mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,60.562mm)(71.193mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,55.984mm)(64.443mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Text "G" (51.181mm,71.374mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.125mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (51.231mm,72.263mm)(53.975mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (41.25mm,72.263mm)(44.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.07mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Text "HEADER" (40.767mm,73.533mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.07mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Track (41.25mm,72.263mm)(41.25mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,72.263mm)(54mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.183mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,77.047mm)(54mm,77.507mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.183mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-37(42.037mm,51.688mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.135mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.084mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.084mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (68.76mm,40.766mm)(70.439mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (66.26mm,40.766mm)(66.368mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,40.766mm)(64.689mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,40.766mm)(70.439mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,43.929mm)(70.439mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.093mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (56.484mm,70.581mm)(56.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.093mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.173mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.029mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.189mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.189mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.073mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,48.768mm)(59.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-2(61.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-3(63.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-4(65.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.181mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.181mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.142mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.142mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-5(51.684mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.099mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Text "-" (47.76mm,47.752mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.099mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-1(45.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-2(47.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-3(50.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-4(52.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(60.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(62.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(65.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(67.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,64.713mm)(53.362mm,65.679mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "dp" (53.987mm,62.512mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.074mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.074mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Text "dm" (54.102mm,61.214mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.148mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Text "v" (54.385mm,60.566mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Text "USB" (49.53mm,67.691mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (48.265mm,65.732mm)(48.784mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (52.247mm,65.732mm)(53.362mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (48.265mm,58.982mm)(48.784mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (52.247mm,58.982mm)(53.362mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] +Rule Violations :116 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "-" (47.76mm,47.752mm) on Bottom Overlay And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(54.991mm,78.104mm) on Top Overlay Silk Text to Silk Clearance [0.003mm] + Violation between Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(72.771mm,62.484mm) on Top Overlay Silk Text to Silk Clearance [0.003mm] + Violation between Silk To Silk Clearance Constraint: (0.029mm < 0.254mm) Between Text "G" (54.102mm,64.281mm) on Top Overlay And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay Silk Text to Silk Clearance [0.029mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "G" (67.056mm,54.928mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,61.081mm)(71.193mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,44.167mm)(70.439mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "tx" (69.469mm,54.337mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.186mm < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0.186mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (53.911mm,60.833mm) on Bottom Overlay And Track (54.069mm,50.927mm)(54.069mm,70.927mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U5" (68.897mm,58.674mm) on Bottom Overlay And Track (69.055mm,48.768mm)(69.055mm,68.768mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.253mm < 0.254mm) Between Text "v" (54.385mm,60.566mm) on Top Overlay And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay Silk Text to Silk Clearance [0.253mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (65.815mm,55.105mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm] +Rule Violations :17 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 163 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.html b/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.html new file mode 100644 index 0000000..f749c73 --- /dev/null +++ b/fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.html @@ -0,0 +1,829 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/6/23
Time:17:51:24
Elapsed Time:00:00:01
Filename:C:\Users\hu123456\Desktop\fsa1\BODY\FSA_Body_PCB ΢20211217_2022-06-23.pcbdoc
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Warnings:0
Rule Violations:163
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Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.254mm) (All),(All)29
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)1
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)116
Silk to Silk (Clearance=0.254mm) (All),(All)17
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total163

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Clearance Constraint (Gap=0.254mm) (All),(All)
Clearance Constraint: (0.061mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (62.155mm,54.268mm)(62.155mm,66.268mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-1(39.497mm,72.009mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-2(39.497mm,69.469mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-25(77.343mm,72.009mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-26(77.343mm,69.469mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-27(77.343mm,66.929mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-28(77.343mm,64.389mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-29(77.343mm,61.849mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-3(39.497mm,66.929mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-30(77.343mm,59.309mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-31(77.343mm,56.769mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-32(77.343mm,54.229mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-33(77.343mm,51.689mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-34(77.343mm,49.149mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-35(77.343mm,46.609mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-36(77.343mm,44.069mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-4(39.497mm,64.389mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-48(76.167mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer
Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-5(39.497mm,61.849mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-6(39.497mm,59.309mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-7(39.497mm,56.769mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-8(39.497mm,54.229mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.172mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Via (65.943mm,57.806mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.172mm]

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-11(39.497mm,46.609mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-12(39.497mm,44.069mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-38(42.037mm,49.149mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-49(40.767mm,40.419mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.148mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad U1-2(46.72mm,47.387mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,51.04mm)(48.016mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,54.821mm)(48.016mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,51.04mm)(55.616mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,54.821mm)(55.616mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Text "IN1" (64.77mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (63.691mm,49.092mm)(65.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Text "IN2" (69.469mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (69.422mm,49.092mm)(71.691mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,49.092mm)(71.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,53.645mm)(71.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,49.092mm)(63.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,53.645mm)(63.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (70.174mm,55.984mm)(71.14mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.171mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Text "v" (65.815mm,55.105mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.171mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (65.174mm,55.984mm)(65.461mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,55.984mm)(71.193mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,60.562mm)(71.193mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,55.984mm)(64.443mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.125mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Text "G" (51.181mm,71.374mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.125mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (51.231mm,72.263mm)(53.975mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (41.25mm,72.263mm)(44.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.07mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Text "HEADER" (40.767mm,73.533mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.07mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Track (41.25mm,72.263mm)(41.25mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,72.263mm)(54mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.183mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,77.047mm)(54mm,77.507mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.183mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-37(42.037mm,51.688mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.135mm]
Silk To Solder Mask Clearance Constraint: (0.084mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.084mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (68.76mm,40.766mm)(70.439mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (66.26mm,40.766mm)(66.368mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,40.766mm)(64.689mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,40.766mm)(70.439mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,43.929mm)(70.439mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.093mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (56.484mm,70.581mm)(56.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.093mm]
Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.173mm]
Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.029mm]
Silk To Solder Mask Clearance Constraint: (0.189mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.189mm]
Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.073mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,48.768mm)(59.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-2(61.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-3(63.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-4(65.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm]
Silk To Solder Mask Clearance Constraint: (0.181mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.181mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.142mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.142mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-5(51.684mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm]
Silk To Solder Mask Clearance Constraint: (0.099mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Text "-" (47.76mm,47.752mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.099mm]
Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-1(45.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-2(47.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-3(50.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-4(52.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(60.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(62.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(65.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(67.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,64.713mm)(53.362mm,65.679mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "dp" (53.987mm,62.512mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
Silk To Solder Mask Clearance Constraint: (0.074mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.074mm]
Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Text "dm" (54.102mm,61.214mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.148mm]
Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Text "v" (54.385mm,60.566mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Text "USB" (49.53mm,67.691mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (48.265mm,65.732mm)(48.784mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (52.247mm,65.732mm)(53.362mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (48.265mm,58.982mm)(48.784mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (52.247mm,58.982mm)(53.362mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "-" (47.76mm,47.752mm) on Bottom Overlay And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(54.991mm,78.104mm) on Top Overlay Silk Text to Silk Clearance [0.003mm]
Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(72.771mm,62.484mm) on Top Overlay Silk Text to Silk Clearance [0.003mm]
Silk To Silk Clearance Constraint: (0.029mm < 0.254mm) Between Text "G" (54.102mm,64.281mm) on Top Overlay And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay Silk Text to Silk Clearance [0.029mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "G" (67.056mm,54.928mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,61.081mm)(71.193mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,44.167mm)(70.439mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "tx" (69.469mm,54.337mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.186mm < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0.186mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (53.911mm,60.833mm) on Bottom Overlay And Track (54.069mm,50.927mm)(54.069mm,70.927mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U5" (68.897mm,58.674mm) on Bottom Overlay And Track (69.055mm,48.768mm)(69.055mm,68.768mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.253mm < 0.254mm) Between Text "v" (54.385mm,60.566mm) on Top Overlay And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay Silk Text to Silk Clearance [0.253mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (65.815mm,55.105mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]

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+ diff --git a/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc new file mode 100644 index 0000000..8dad265 Binary files /dev/null and b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc differ diff --git a/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc.htm b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc.htm new file mode 100644 index 0000000..2212f28 --- /dev/null +++ b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.pcbdoc.htm @@ -0,0 +1,175 @@ + + + + + + + + + + Reporting Options +

File in Previous Format

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Date:2022/6/24
Time:9:49:32
Filename:C:\Users\hu123456\Desktop\fsa1\BODY\FSA_Body_PCB ΢20211217_2022-06-23.pcbdoc
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
VersionWarning
6.3CAUTION - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.
Summer 09CAUTION - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.
Summer 09CAUTION - Existing testpoint rules and settings are used as fabrication testpoint information.
Release 12CAUTION - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.
Release 13CAUTION - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.
+

+

This file was generated by an earlier version of the software

+ + diff --git a/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.rar b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.rar new file mode 100644 index 0000000..2b50cad Binary files /dev/null and b/fsa1/BODY/FSA_Body_PCB 微调20211217_2022-06-23.rar differ diff --git a/fsa1/BOTTOM/Pogo_Bottom_PCB 微调_2022-06-24.pcbdoc b/fsa1/BOTTOM/Pogo_Bottom_PCB 微调_2022-06-24.pcbdoc new file mode 100644 index 0000000..c1c9f38 Binary files /dev/null and b/fsa1/BOTTOM/Pogo_Bottom_PCB 微调_2022-06-24.pcbdoc differ diff --git a/fsa1/HEADER/Design Rule Check - HEADER20220623.drc b/fsa1/HEADER/Design Rule Check - HEADER20220623.drc new file mode 100644 index 0000000..9aae1c0 --- /dev/null +++ b/fsa1/HEADER/Design Rule Check - HEADER20220623.drc @@ -0,0 +1,209 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\fsa1\HEADER\HEADER20220623.pcbdoc +Date : 2022/6/24 +Time : 10:07:02 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(80.52mm,85.32mm) on Multi-Layer And Pad CN2-22(79.87mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(87.12mm,85.32mm) on Multi-Layer And Pad CN2-21(87.77mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(62.232mm,85.828mm) on Multi-Layer And Pad CN3-21(61.582mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(68.832mm,85.828mm) on Multi-Layer And Pad CN3-22(69.482mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm] +Rule Violations :4 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,50.2mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,51.4mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,46.404mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,48.084mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.255mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (66.855mm,51.4mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.258mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (67.082mm,48.084mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,48.66mm)(70.193mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,49.66mm)(70.193mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.393mm,49.91mm)(71.593mm,49.91mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,48.66mm)(71.793mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,49.66mm)(71.793mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.81mm)(70.193mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.86mm)(70.193mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.393mm,46.61mm)(71.593mm,46.61mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.81mm)(71.793mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.86mm)(71.793mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,46.404mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.064mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,46.204mm)(65.032mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,48.284mm)(65.032mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,46.204mm)(67.082mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,48.284mm)(67.082mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,48.044mm)(67.282mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.755mm,50.2mm)(63.755mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,50mm)(64.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,51.6mm)(64.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,50mm)(65.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,51.6mm)(65.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,50mm)(66.805mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,51.6mm)(66.805mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,50mm)(66.855mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,51.6mm)(66.855mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.168mm < 0.254mm) Between Pad CN1-1(68.604mm,45.135mm) on Bottom Layer And Track (68.204mm,42.86mm)(68.204mm,44.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.168mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.116mm < 0.254mm) Between Pad CN1-3(68.604mm,47.635mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.116mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-4(68.604mm,48.885mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-5(68.604mm,50.135mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Track (68.218mm,51.941mm)(68.218mm,53.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-7(65.254mm,53.235mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-8(65.254mm,43.285mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.48mm,81.28mm)(87.496mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-10(81.57mm,82.02mm) on Top Layer And Track (80.137mm,81.28mm)(81.189mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN2-11(81.57mm,85.62mm) on Top Layer And Track (80.137mm,86.36mm)(81.189mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.111mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-20(86.07mm,85.62mm) on Top Layer And Track (86.451mm,86.36mm)(87.496mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-21(87.77mm,83.82mm) on Top Layer And Track (87.496mm,81.28mm)(87.496mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.14mm < 0.254mm) Between Pad CN2-22(79.87mm,83.82mm) on Top Layer And Track (80.137mm,81.28mm)(80.137mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.14mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (61.856mm,81.788mm)(62.872mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-10(67.782mm,82.528mm) on Bottom Layer And Track (68.163mm,81.788mm)(69.215mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-11(67.782mm,86.128mm) on Bottom Layer And Track (68.163mm,86.868mm)(69.215mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN3-20(63.282mm,86.128mm) on Bottom Layer And Track (61.856mm,86.868mm)(62.901mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.136mm < 0.254mm) Between Pad CN3-21(61.582mm,84.328mm) on Bottom Layer And Track (61.856mm,81.788mm)(61.856mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.136mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-22(69.482mm,84.328mm) on Bottom Layer And Track (69.215mm,81.788mm)(69.215mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,51.124mm)(77.851mm,53.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,46.124mm)(77.851mm,46.412mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (77.851mm,53.893mm)(79.094mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (82.556mm,53.893mm)(83.425mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (77.851mm,43.643mm)(79.094mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (82.556mm,43.643mm)(83.425mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,52.828mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,54.868mm)(67.155mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (67.155mm,54.868mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(63.655mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(64.905mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,54.868mm)(64.905mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.176mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.176mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(70.078mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,53.251mm)(71.328mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,53.246mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2_5V(82.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D-(80.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D+(78.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2GND(76.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3_5v(76.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D-(78.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D+(80.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Text "GND" (81.326mm,42.927mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.253mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad U1-u4Gnd(68.88mm,40.74mm) on Multi-Layer And Text "GND" (68.245mm,43.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-1(75.184mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-10(82.804mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.232mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-14(77.724mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-15(76.454mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-16(75.184mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-2(76.454mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-3(77.724mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-4(78.994mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-5(80.264mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-6(81.534mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-7(82.804mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-8(84.074mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-9(84.074mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (71.183mm,49.186mm)(71.802mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "G" (75.692mm,49.892mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "R" (75.565mm,48.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Text "U3" (73.279mm,42.941mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (75.264mm,44.286mm)(75.883mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (71.183mm,44.286mm)(71.802mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm] +Rule Violations :134 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Text "C3" (67.437mm,49.467mm) on Top Overlay Silk Text to Silk Clearance [0.179mm] + Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Text "C2" (67.564mm,45.91mm) on Top Overlay Silk Text to Silk Clearance [0.079mm] + Violation between Silk To Silk Clearance Constraint: (0.063mm < 0.254mm) Between Text "5V" (81.199mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0.063mm] + Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay Silk Text to Silk Clearance [0.079mm] + Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay Silk Text to Silk Clearance [0.079mm] + Violation between Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Text "C3" (67.437mm,49.467mm) on Top Overlay And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay Silk Text to Silk Clearance [0.179mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "D-" (69.85mm,48.406mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN5" (83.376mm,47.625mm) on Bottom Overlay And Track (83.425mm,43.643mm)(83.425mm,53.893mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (79.675mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Text "G" (69.977mm,45.993mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.155mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Text "T" (75.441mm,47.372mm) on Bottom Overlay Silk Text to Silk Clearance [0.155mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.089mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.089mm] + Violation between Silk To Silk Clearance Constraint: (0.048mm < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay Silk Text to Silk Clearance [0.048mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "T" (75.441mm,47.372mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (85.786mm,48.819mm) on Top Overlay And Track (85.98mm,39.14mm)(85.98mm,58.04mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "V" (75.708mm,46.109mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm] +Rule Violations :23 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 161 +Waived Violations : 0 +Time Elapsed : 00:00:00 \ No newline at end of file diff --git a/fsa1/HEADER/Design Rule Check - HEADER20220623.html b/fsa1/HEADER/Design Rule Check - HEADER20220623.html new file mode 100644 index 0000000..54cc88a --- /dev/null +++ b/fsa1/HEADER/Design Rule Check - HEADER20220623.html @@ -0,0 +1,819 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/6/24
Time:10:07:02
Elapsed Time:00:00:00
Filename:C:\Users\hu123456\Desktop\fsa1\HEADER\HEADER20220623.pcbdoc
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Warnings:0
Rule Violations:161
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Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)4
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)134
Silk to Silk (Clearance=0.254mm) (All),(All)23
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total161

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(80.52mm,85.32mm) on Multi-Layer And Pad CN2-22(79.87mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm]
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(87.12mm,85.32mm) on Multi-Layer And Pad CN2-21(87.77mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm]
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(62.232mm,85.828mm) on Multi-Layer And Pad CN3-21(61.582mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm]
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(68.832mm,85.828mm) on Multi-Layer And Pad CN3-22(69.482mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm]

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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,50.2mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,51.4mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,46.404mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,48.084mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.255mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (66.855mm,51.4mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.258mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (67.082mm,48.084mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,48.66mm)(70.193mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,49.66mm)(70.193mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.393mm,49.91mm)(71.593mm,49.91mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,48.66mm)(71.793mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,49.66mm)(71.793mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.81mm)(70.193mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.86mm)(70.193mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.393mm,46.61mm)(71.593mm,46.61mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.81mm)(71.793mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.86mm)(71.793mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,46.404mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.064mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,46.204mm)(65.032mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,48.284mm)(65.032mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,46.204mm)(67.082mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,48.284mm)(67.082mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,48.044mm)(67.282mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.755mm,50.2mm)(63.755mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,50mm)(64.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,51.6mm)(64.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,50mm)(65.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,51.6mm)(65.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,50mm)(66.805mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,51.6mm)(66.805mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,50mm)(66.855mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,51.6mm)(66.855mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.168mm < 0.254mm) Between Pad CN1-1(68.604mm,45.135mm) on Bottom Layer And Track (68.204mm,42.86mm)(68.204mm,44.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.168mm]
Silk To Solder Mask Clearance Constraint: (0.116mm < 0.254mm) Between Pad CN1-3(68.604mm,47.635mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.116mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-4(68.604mm,48.885mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-5(68.604mm,50.135mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Track (68.218mm,51.941mm)(68.218mm,53.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-7(65.254mm,53.235mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm]
Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-8(65.254mm,43.285mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.48mm,81.28mm)(87.496mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-10(81.57mm,82.02mm) on Top Layer And Track (80.137mm,81.28mm)(81.189mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN2-11(81.57mm,85.62mm) on Top Layer And Track (80.137mm,86.36mm)(81.189mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.111mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-20(86.07mm,85.62mm) on Top Layer And Track (86.451mm,86.36mm)(87.496mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-21(87.77mm,83.82mm) on Top Layer And Track (87.496mm,81.28mm)(87.496mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.14mm < 0.254mm) Between Pad CN2-22(79.87mm,83.82mm) on Top Layer And Track (80.137mm,81.28mm)(80.137mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.14mm]
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (61.856mm,81.788mm)(62.872mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-10(67.782mm,82.528mm) on Bottom Layer And Track (68.163mm,81.788mm)(69.215mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-11(67.782mm,86.128mm) on Bottom Layer And Track (68.163mm,86.868mm)(69.215mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN3-20(63.282mm,86.128mm) on Bottom Layer And Track (61.856mm,86.868mm)(62.901mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm]
Silk To Solder Mask Clearance Constraint: (0.136mm < 0.254mm) Between Pad CN3-21(61.582mm,84.328mm) on Bottom Layer And Track (61.856mm,81.788mm)(61.856mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.136mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-22(69.482mm,84.328mm) on Bottom Layer And Track (69.215mm,81.788mm)(69.215mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,51.124mm)(77.851mm,53.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,46.124mm)(77.851mm,46.412mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (77.851mm,53.893mm)(79.094mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (82.556mm,53.893mm)(83.425mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (77.851mm,43.643mm)(79.094mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (82.556mm,43.643mm)(83.425mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,52.828mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,54.868mm)(67.155mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (67.155mm,54.868mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(63.655mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(64.905mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,54.868mm)(64.905mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.176mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.176mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(70.078mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,53.251mm)(71.328mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,53.246mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2_5V(82.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D-(80.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D+(78.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2GND(76.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3_5v(76.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D-(78.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D+(80.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Text "GND" (81.326mm,42.927mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.253mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad U1-u4Gnd(68.88mm,40.74mm) on Multi-Layer And Text "GND" (68.245mm,43.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-1(75.184mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-10(82.804mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.232mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-14(77.724mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-15(76.454mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-16(75.184mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-2(76.454mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-3(77.724mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-4(78.994mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-5(80.264mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-6(81.534mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-7(82.804mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-8(84.074mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-9(84.074mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (71.183mm,49.186mm)(71.802mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "G" (75.692mm,49.892mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "R" (75.565mm,48.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm]
Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Text "U3" (73.279mm,42.941mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (75.264mm,44.286mm)(75.883mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm]
Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (71.183mm,44.286mm)(71.802mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm]

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Text "C3" (67.437mm,49.467mm) on Top Overlay Silk Text to Silk Clearance [0.179mm]
Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Text "C2" (67.564mm,45.91mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
Silk To Silk Clearance Constraint: (0.063mm < 0.254mm) Between Text "5V" (81.199mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0.063mm]
Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Text "C3" (67.437mm,49.467mm) on Top Overlay And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay Silk Text to Silk Clearance [0.179mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "D-" (69.85mm,48.406mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN5" (83.376mm,47.625mm) on Bottom Overlay And Track (83.425mm,43.643mm)(83.425mm,53.893mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (79.675mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Text "G" (69.977mm,45.993mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.155mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Text "T" (75.441mm,47.372mm) on Bottom Overlay Silk Text to Silk Clearance [0.155mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.089mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.089mm]
Silk To Silk Clearance Constraint: (0.048mm < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay Silk Text to Silk Clearance [0.048mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "T" (75.441mm,47.372mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (85.786mm,48.819mm) on Top Overlay And Track (85.98mm,39.14mm)(85.98mm,58.04mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "V" (75.708mm,46.109mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm]

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+ diff --git a/fsa1/HEADER/HEADER20220623.pcbdoc b/fsa1/HEADER/HEADER20220623.pcbdoc new file mode 100644 index 0000000..1aa0884 Binary files /dev/null and b/fsa1/HEADER/HEADER20220623.pcbdoc differ diff --git a/fsa1/HEADER/HEADER20220623.pcbdoc.htm b/fsa1/HEADER/HEADER20220623.pcbdoc.htm new file mode 100644 index 0000000..e2efa28 --- /dev/null +++ b/fsa1/HEADER/HEADER20220623.pcbdoc.htm @@ -0,0 +1,175 @@ + + + + + + + + + + Reporting Options +

File in Previous Format

+ + + + + + + + + + + + + + + + + +
Date:2022/6/24
Time:10:17:35
Filename:C:\Users\hu123456\Desktop\fsa1\HEADER\HEADER20220623.pcbdoc
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
VersionWarning
6.3CAUTION - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.
Summer 09CAUTION - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.
Summer 09CAUTION - Existing testpoint rules and settings are used as fabrication testpoint information.
Release 12CAUTION - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.
Release 13CAUTION - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.
+

+

This file was generated by an earlier version of the software

+ + diff --git a/fsa1/HEADER/HEADER20220623.rar b/fsa1/HEADER/HEADER20220623.rar new file mode 100644 index 0000000..ff95af1 Binary files /dev/null and b/fsa1/HEADER/HEADER20220623.rar differ diff --git a/fsa1/POGO/POGO/Pogo_Body_PCB 微调_2022-06-24.pcbdoc b/fsa1/POGO/POGO/Pogo_Body_PCB 微调_2022-06-24.pcbdoc new file mode 100644 index 0000000..10c0c9c Binary files /dev/null and b/fsa1/POGO/POGO/Pogo_Body_PCB 微调_2022-06-24.pcbdoc differ diff --git a/fsa1/POGO/POGO副板/Pogo2_Body_PCB新_2022-06-24.pcbdoc b/fsa1/POGO/POGO副板/Pogo2_Body_PCB新_2022-06-24.pcbdoc new file mode 100644 index 0000000..555c41a Binary files /dev/null and b/fsa1/POGO/POGO副板/Pogo2_Body_PCB新_2022-06-24.pcbdoc differ diff --git a/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.drc b/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.drc new file mode 100644 index 0000000..bc1956d --- /dev/null +++ b/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.drc @@ -0,0 +1,112 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\hu123456\Desktop\fsa1\sw\FSA_SW_PCB ΢_2022-06-23.pcbdoc +Date : 2022/6/24 +Time : 10:25:55 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Pad IN-2(41.031mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.146mm] / [Bottom Solder] Mask Sliver [0.047mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Pad OUT-2(62.24mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.221mm] / [Bottom Solder] Mask Sliver [0.047mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Pad SW1-2(50.117mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Pad SW1-3(50.117mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Pad SW1-5(45.617mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Pad SW1-6(45.617mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm] +Rule Violations :8 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.133mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.221mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.083mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.083mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,41.857mm)(59.467mm,42.129mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,44.23mm)(59.467mm,44.502mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Text "R1" (52.324mm,44.069mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(52.291mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(53.891mm,41.185mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (53.891mm,41.185mm)(53.891mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.128mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.618mm,40.28mm)(50.767mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,40.28mm)(50.767mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.221mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.618mm,46.079mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,45.979mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(44.967mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(45.116mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,45.979mm)(44.967mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,46.079mm)(45.116mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm] +Rule Violations :39 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Text "LED1" (56.388mm,44.958mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(39.481mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm] + Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm] + Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(60.69mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm] + Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm] + Violation between Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (39.481mm,44.649mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm] + Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.185mm] + Violation between Silk To Silk Clearance Constraint: (0.039mm < 0.254mm) Between Text "LED1" (56.388mm,44.958mm) on Top Overlay And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay Silk Text to Silk Clearance [0.039mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (60.69mm,44.649mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.108mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.108mm] + Violation between Silk To Silk Clearance Constraint: (0.056mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.056mm] +Rule Violations :17 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 64 +Waived Violations : 0 +Time Elapsed : 00:00:00 \ No newline at end of file diff --git a/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.html b/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.html new file mode 100644 index 0000000..7ec4fd8 --- /dev/null +++ b/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.html @@ -0,0 +1,528 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2022/6/24
Time:10:25:55
Elapsed Time:00:00:00
Filename:C:\Users\hu123456\Desktop\fsa1\sw\FSA_SW_PCB ΢_2022-06-23.pcbdoc
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Warnings:0
Rule Violations:64
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Summary

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WarningsCount
Total0

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)8
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)39
Silk to Silk (Clearance=0.254mm) (All),(All)17
Net Antennae (Tolerance=0mm) (All)0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total64

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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Pad IN-2(41.031mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.146mm] / [Bottom Solder] Mask Sliver [0.047mm]
Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm]
Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Pad OUT-2(62.24mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.221mm] / [Bottom Solder] Mask Sliver [0.047mm]
Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Pad SW1-2(50.117mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Pad SW1-3(50.117mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Pad SW1-5(45.617mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Pad SW1-6(45.617mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.133mm]
Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.221mm]
Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
Silk To Solder Mask Clearance Constraint: (0.083mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.083mm]
Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,41.857mm)(59.467mm,42.129mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm]
Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,44.23mm)(59.467mm,44.502mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm]
Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Text "R1" (52.324mm,44.069mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(52.291mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(53.891mm,41.185mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (53.891mm,41.185mm)(53.891mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.128mm]
Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.618mm,40.28mm)(50.767mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,40.28mm)(50.767mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.221mm]
Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm]
Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.618mm,46.079mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm]
Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,45.979mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(44.967mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(45.116mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm]
Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,45.979mm)(44.967mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,46.079mm)(45.116mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm]
Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm]

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Text "LED1" (56.388mm,44.958mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(39.481mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(60.69mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (39.481mm,44.649mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm]
Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.185mm]
Silk To Silk Clearance Constraint: (0.039mm < 0.254mm) Between Text "LED1" (56.388mm,44.958mm) on Top Overlay And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay Silk Text to Silk Clearance [0.039mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (60.69mm,44.649mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.108mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.108mm]
Silk To Silk Clearance Constraint: (0.056mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.056mm]

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+ diff --git a/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc new file mode 100644 index 0000000..eccaa6c Binary files /dev/null and b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc differ diff --git a/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc.htm b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc.htm new file mode 100644 index 0000000..9ee39f4 --- /dev/null +++ b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.pcbdoc.htm @@ -0,0 +1,175 @@ + + + + + + + + + + Reporting Options +

File in Previous Format

+ + + + + + + + + + + + + + + + + +
Date:2022/6/24
Time:10:32:06
Filename:C:\Users\hu123456\Desktop\fsa1\sw\FSA_SW_PCB ΢_2022-06-23.pcbdoc
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
VersionWarning
6.3CAUTION - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.
Summer 09CAUTION - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.
Summer 09CAUTION - Existing testpoint rules and settings are used as fabrication testpoint information.
Release 12CAUTION - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.
Release 13CAUTION - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.
+

+

This file was generated by an earlier version of the software

+ + diff --git a/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.rar b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.rar new file mode 100644 index 0000000..eed694a Binary files /dev/null and b/fsa1/sw/FSA_SW_PCB 微调_2022-06-23.rar differ diff --git a/fsa1/sw/debug.log b/fsa1/sw/debug.log new file mode 100644 index 0000000..e69de29 diff --git a/fsa2/PCB_Project1.PrjPCB b/fsa2/PCB_Project1.PrjPCB index d549c53..a62f7fd 100644 --- a/fsa2/PCB_Project1.PrjPCB +++ b/fsa2/PCB_Project1.PrjPCB @@ -38,23 +38,6 @@ PrefsVaultGUID= PrefsRevisionGUID= [Document1] -DocumentPath=..\÷װ-3d\1.25t-5p.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=XSKGBPJH - -[Document2] DocumentPath=Copy of PCB1.PcbDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -71,58 +54,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=MVPBPOVD -[Document3] -DocumentPath=..\÷װ-3d\1.25T-4P.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=TWJRKNDI - -[Document4] -DocumentPath=..\÷װ-3d\1.25t-8p.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=WLTRFQEF - -[Document5] -DocumentPath=..\÷װ-3d\CAP-SMD_L3.5-W2.8-FD.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=WHCOAUDM - -[Document6] +[Document2] DocumentPath=680uf smd.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -139,7 +71,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=QHPCOQJT -[Document7] +[Document3] DocumentPath=sw.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -156,211 +88,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=QIQXQKEM -[Document8] -DocumentPath=..\÷װ-3d\2.0T-4P.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=HHWXBLWW - -[Document9] -DocumentPath=..\÷װ-3d\3225.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=BLUDXTHO - -[Document10] -DocumentPath=..\÷װ-3d\1.25t-6p.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=KXNYXVHS - -[Document11] -DocumentPath=..\÷װ-3d\0402L.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=JROQIUOL - -[Document12] -DocumentPath=..\÷װ-3d\XAL4020.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=RVGGRYGA - -[Document13] -DocumentPath=..\÷װ-3d\JY901.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=DPOOYBPI - -[Document14] -DocumentPath=..\÷װ-3d\0402RES.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=USEJBYTX - -[Document15] -DocumentPath=..\÷װ-3d\0402CAP.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=JROQIUOL - -[Document16] -DocumentPath=..\÷װ-3d\0603RES.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=LYTPRADG - -[Document17] -DocumentPath=..\÷װ-3d\0603CAP.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=IFUOXHBC - -[Document18] -DocumentPath=..\÷װ-3d\0805CAP.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=MMGLYDRF - -[Document19] -DocumentPath=..\÷װ-3d\0805RES.PcbLib -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId=MMGLYDRF - -[Document20] +[Document4] DocumentPath=fpc-0.5-26.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -377,7 +105,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=PPLQDWNY -[Document21] +[Document5] DocumentPath=LTC3370.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -394,7 +122,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=KBNGLGDJ -[Document22] +[Document6] DocumentPath=UA78M33CDCYR.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -411,7 +139,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=TSNEAVCG -[Document23] +[Document7] DocumentPath=2.4,5.8Gwifi.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -428,7 +156,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=BGAYWDFA -[Document24] +[Document8] DocumentPath=cam.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -445,7 +173,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=XWTGDTWJ -[Document25] +[Document9] DocumentPath=ESP32-PICO-D4.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -462,7 +190,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=SMBSILBB -[Document26] +[Document10] DocumentPath=Sheet1.SchDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -479,7 +207,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=LVEOFKCS -[Document27] +[Document11] DocumentPath=CAM.SchLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -496,7 +224,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=RUKTNCVD -[Document28] +[Document12] DocumentPath=3225-40M.SchLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -513,7 +241,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=NBTHQCWS -[Document29] +[Document13] DocumentPath=LTC3370.SchLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -649,7 +377,7 @@ OutputDefault20=0 [OutputGroup2] Name=Simulator Outputs Description= -TargetPrinter=ΪWPS PDF +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 [OutputGroup3] diff --git a/云台控制/0603.PcbLib b/云台控制/0603.PcbLib new file mode 100644 index 0000000..b9c98c8 Binary files /dev/null and b/云台控制/0603.PcbLib differ diff --git a/云台控制/1.25-6P WT.PcbLib b/云台控制/1.25-6P WT.PcbLib new file mode 100644 index 0000000..60a778b Binary files /dev/null and b/云台控制/1.25-6P WT.PcbLib differ diff --git a/云台控制/1117.PcbLib b/云台控制/1117.PcbLib new file mode 100644 index 0000000..f1792e6 Binary files /dev/null and b/云台控制/1117.PcbLib differ diff --git a/云台控制/117.PcbLib b/云台控制/117.PcbLib new file mode 100644 index 0000000..a67d1ec Binary files /dev/null and b/云台控制/117.PcbLib differ diff --git a/云台控制/ESP32-WROOM-32U.PcbLib b/云台控制/ESP32-WROOM-32U.PcbLib new file mode 100644 index 0000000..637b937 Binary files /dev/null and b/云台控制/ESP32-WROOM-32U.PcbLib differ diff --git a/云台控制/JY901.PcbLib b/云台控制/JY901.PcbLib new file mode 100644 index 0000000..fa2c806 Binary files /dev/null and b/云台控制/JY901.PcbLib differ diff --git a/云台控制/KH-TYPE-C-16P.PcbLib b/云台控制/KH-TYPE-C-16P.PcbLib new file mode 100644 index 0000000..4efa304 Binary files /dev/null and b/云台控制/KH-TYPE-C-16P.PcbLib differ diff --git a/云台控制/LED0603.PcbLib b/云台控制/LED0603.PcbLib new file mode 100644 index 0000000..0a95a2e Binary files /dev/null and b/云台控制/LED0603.PcbLib differ diff --git a/云台控制/MAX14783EESA+.PcbLib b/云台控制/MAX14783EESA+.PcbLib new file mode 100644 index 0000000..a1d99f8 Binary files /dev/null and b/云台控制/MAX14783EESA+.PcbLib differ diff --git a/云台控制/PCB1.PcbDoc b/云台控制/PCB1.PcbDoc new file mode 100644 index 0000000..aeb18bc Binary files /dev/null and b/云台控制/PCB1.PcbDoc differ diff --git a/云台控制/PCB_Project1.PrjPCB b/云台控制/PCB_Project1.PrjPCB new file mode 100644 index 0000000..fc2b9ff --- /dev/null +++ b/云台控制/PCB_Project1.PrjPCB @@ -0,0 +1,1052 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=Sheet1.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=SYVVLMGY + +[Document2] +DocumentPath=PCB1.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=BFBYFBBV + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=PCB 3D Print +OutputName2=PCB 3D Print +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=PCB 3D Video +OutputName3=PCB 3D Video +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=PCB Print +OutputName4=PCB Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=PCBDrawing +OutputName5=Draftsman +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=PCBLIB Print +OutputName6=PCBLIB Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=PDF3D +OutputName7=PDF3D +OutputDocumentPath7= +OutputVariantName7=[No Variations] +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=Report Print +OutputName8=Report Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=Schematic Print +OutputName9=Schematic Prints +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=SimView Print +OutputName10=SimView Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup4] +Name=Assembly Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 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+OutputVariantName6=[No Variations] +OutputDefault6=0 + +[OutputGroup7] +Name=Other Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Text Print +OutputName1=Text Print +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=Text Print +OutputName2=Text Print +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 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+PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Server's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 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+Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportPARASOLID +OutputName4=Export PARASOLID +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=ExportSTEP +OutputName5=Export STEP +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=ExportVRML +OutputName6=Export VRML +OutputDocumentPath6= +OutputVariantName6=[No Variations] +OutputDefault6=0 +OutputType7=Save As/Export PCB +OutputName7=Save As/Export PCB +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Save As/Export Schematic +OutputName8=Save As/Export Schematic +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Specctra Design PCB +OutputName9=Specctra Design PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=HP LaserJet Pro MFP M225-M226 PCL 6 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=1 +Type26=1 +Type27=1 +Type28=1 +Type29=1 +Type30=1 +Type31=1 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+Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=1 +Type61=2 +Type62=2 +Type63=1 +Type64=0 +Type65=2 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 +Type91=3 +Type92=3 +Type93=2 +Type94=2 +Type95=2 +Type96=2 +Type97=2 +Type98=0 +Type99=1 +Type100=2 +Type101=1 +Type102=2 +Type103=2 +Type104=1 +Type105=2 +Type106=2 +Type107=2 +Type108=2 +Type109=1 +Type110=1 +Type111=1 +Type112=1 +Type113=1 +Type114=2 +Type115=2 +Type116=2 +Type117=3 +Type118=3 +Type119=3 +MultiChannelAlternate=2 +AlternateItemFail=3 +Type122=2 + +[ERC Connection Matrix] +L1=NNNNNNNNNNNWNNNWW +L2=NNWNNNNWWWNWNWNWN +L3=NWEENEEEENEWNEEWN +L4=NNENNNWEENNWNENWN +L5=NNNNNNNNNNNNNNNNN +L6=NNENNNNEENNWNENWN +L7=NNEWNNWEENNWNENWN +L8=NWEENEENEEENNEENN +L9=NWEENEEEENEWNEEWW +L10=NWNNNNNENNEWNNEWN +L11=NNENNNNEEENWNENWN +L12=WWWWNWWNWWWNWWWNN +L13=NNNNNNNNNNNWNNNWW +L14=NWEENEEEENEWNEEWW +L15=NNENNNNEEENWNENWW +L16=WWWWNWWNWWWNWWWNW +L17=WNNNNNNNWNNNWWWWN + +[Annotate] +SortOrder=3 +SortLocation=0 +MatchParameter1=Comment +MatchStrictly1=1 +MatchParameter2=Library Reference +MatchStrictly2=1 +PhysicalNamingFormat=$Component_$RoomName +GlobalIndexSortOrder=3 +GlobalIndexSortLocation=0 + +[PrjClassGen] +CompClassManualEnabled=0 +CompClassManualRoomEnabled=0 +NetClassAutoBusEnabled=1 +NetClassAutoCompEnabled=0 +NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + diff --git a/云台控制/PCB_Project1.PrjPCBStructure b/云台控制/PCB_Project1.PrjPCBStructure new file mode 100644 index 0000000..985c898 --- /dev/null +++ b/云台控制/PCB_Project1.PrjPCBStructure @@ -0,0 +1 @@ +Record=TopLevelDocument|FileName=Sheet1.SchDoc diff --git a/云台控制/PH2.0W-1X4P.PcbLib b/云台控制/PH2.0W-1X4P.PcbLib new file mode 100644 index 0000000..8545355 Binary files /dev/null and b/云台控制/PH2.0W-1X4P.PcbLib differ diff --git a/云台控制/S8050.PcbLib b/云台控制/S8050.PcbLib new file mode 100644 index 0000000..e7dafc5 Binary files /dev/null and b/云台控制/S8050.PcbLib differ diff --git a/云台控制/S8550M-D.PcbLib b/云台控制/S8550M-D.PcbLib new file mode 100644 index 0000000..596deec Binary files /dev/null and b/云台控制/S8550M-D.PcbLib differ diff --git a/云台控制/Sheet1.SchDoc b/云台控制/Sheet1.SchDoc new file mode 100644 index 0000000..7ff5367 Binary files /dev/null and b/云台控制/Sheet1.SchDoc differ diff --git a/云台控制/ch340e.PcbLib b/云台控制/ch340e.PcbLib new file mode 100644 index 0000000..7d973b2 Binary files /dev/null and b/云台控制/ch340e.PcbLib differ diff --git a/云台控制/电源.PcbLib b/云台控制/电源.PcbLib new file mode 100644 index 0000000..bf326fc Binary files /dev/null and b/云台控制/电源.PcbLib differ diff --git a/云台控制/降压模块.PcbLib b/云台控制/降压模块.PcbLib new file mode 100644 index 0000000..17903ff Binary files /dev/null and b/云台控制/降压模块.PcbLib differ diff --git a/气象站/1_Sheet_1.schdoc b/气象站/1_Sheet_1.schdoc index 9a48e74..405a909 100644 Binary files a/气象站/1_Sheet_1.schdoc and b/气象站/1_Sheet_1.schdoc differ diff --git a/气象站/CSD22206W.PcbLib b/气象站/CSD22206W.PcbLib new file mode 100644 index 0000000..9a6b7e0 Binary files /dev/null and b/气象站/CSD22206W.PcbLib differ diff --git a/气象站/Copy of Copy of PCB1.PcbDoc b/气象站/Copy of Copy of PCB1.PcbDoc index f070f40..69ca910 100644 Binary files a/气象站/Copy of Copy of PCB1.PcbDoc and b/气象站/Copy of Copy of PCB1.PcbDoc differ diff --git a/气象站/PCB_Project1.PrjPCB b/气象站/PCB_Project1.PrjPCB index 856cc8e..12b394e 100644 --- a/气象站/PCB_Project1.PrjPCB +++ b/气象站/PCB_Project1.PrjPCB @@ -38,6 +38,23 @@ PrefsVaultGUID= PrefsRevisionGUID= [Document1] +DocumentPath=CSD22206W.PcbLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=FUCSEHYV + +[Document2] DocumentPath=Copy of Copy of PCB1.PcbDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -54,7 +71,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=HYGFXRBI -[Document2] +[Document3] DocumentPath=micro sd.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -71,7 +88,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=UHGMHASS -[Document3] +[Document4] DocumentPath=ds18b20.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -88,7 +105,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=VFTAMGSC -[Document4] +[Document5] DocumentPath=CONN-SMD_PH2.0-1X2PW.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -105,7 +122,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=STGULUBD -[Document5] +[Document6] DocumentPath=Ӳ2 5P.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -122,7 +139,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=XASVVYQA -[Document6] +[Document7] DocumentPath=4p-wb-2.0mm.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -139,7 +156,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=FQLAFAEO -[Document7] +[Document8] DocumentPath=1.25t 4p.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -156,7 +173,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=MTQUHVTX -[Document8] +[Document9] DocumentPath=DSHP02TS-S.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -173,7 +190,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=DKCHJCFS -[Document9] +[Document10] DocumentPath=ESP-WROOM-02U.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -190,7 +207,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=QTNPHFAP -[Document10] +[Document11] DocumentPath=sop16.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -207,7 +224,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=XNAPDYGJ -[Document11] +[Document12] DocumentPath=S8050.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -224,7 +241,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=YQDDNVUA -[Document12] +[Document13] DocumentPath=ESP32-WROOM-32U.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -241,7 +258,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=OUIKTIFU -[Document13] +[Document14] DocumentPath=TS342A2P-WZ.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -258,7 +275,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=LLIGTRAV -[Document14] +[Document15] DocumentPath=RS0102YH8.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -275,7 +292,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=HRLQFCER -[Document15] +[Document16] DocumentPath=HYC244-SIM07-140.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -292,7 +309,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=HWCWJRQX -[Document16] +[Document17] DocumentPath=KH-IPEX-K501-29.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -309,7 +326,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=RYEDDAIA -[Document17] +[Document18] DocumentPath=LXES15AAA1-153.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -326,7 +343,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=REOSMTPI -[Document18] +[Document19] DocumentPath=MMSZ5231BT1G.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -343,7 +360,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=NKLSCBAA -[Document19] +[Document20] DocumentPath=LED0603'.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -360,7 +377,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=CJHKJUVF -[Document20] +[Document21] DocumentPath=SIM800C32.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -377,7 +394,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=SBJIOINU -[Document21] +[Document22] DocumentPath=117.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -394,7 +411,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=CLOVGEAG -[Document22] +[Document23] DocumentPath=CONN-TH_XT30UPB-M.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -411,7 +428,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=JVEXHHVU -[Document23] +[Document24] DocumentPath=.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -428,7 +445,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=VAHRHJIJ -[Document24] +[Document25] DocumentPath=1_Sheet_1.schdoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -445,7 +462,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=FOVRKPUI -[Document25] +[Document26] DocumentPath=SMD-L6.6,W6.6.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -462,7 +479,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=UKUYKKKC -[Document26] +[Document27] DocumentPath=ESDA6V1-5W6-TP.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -479,7 +496,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=UNKXCIND -[Document27] +[Document28] DocumentPath=MAX14783EESA+.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -496,7 +513,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=ESNEKVAI -[Document28] +[Document29] DocumentPath=MICRO-USB-SMD_MICROXNJ.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -513,7 +530,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=QSKHOWQE -[Document29] +[Document30] DocumentPath=S8550M-D.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -530,7 +547,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=FFHATJQK -[Document30] +[Document31] DocumentPath=2R800TA-5_.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -547,7 +564,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=HDWRXFPG -[Document31] +[Document32] DocumentPath=head1.SchLib AnnotationEnabled=1 AnnotateStartValue=1 @@ -564,7 +581,7 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=VMSATFCT -[Document32] +[Document33] DocumentPath=ZOUS.PcbLib AnnotationEnabled=1 AnnotateStartValue=1