Altium

Design Rule Verification Report

Date: 2022/7/12
Time: 10:59:30
Elapsed Time: 00:00:01
Filename: C:\Users\hu123456\Desktop\NANO PI 4MV2 PMIC TO M2 AND USB3.0\PCB1.PcbDoc
Warnings: 0
Rule Violations: 46

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 1
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 11
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 28
Silk to Silk (Clearance=0.254mm) (All),(All) 6
Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 46

Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (2.56mm > 2.54mm) Pad Free-1(60.88mm,48.768mm) on Multi-Layer Actual Hole Size = 2.56mm
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Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad M1-1(69.88mm,86.268mm) on Top Layer And Pad M1-76(70.98mm,87.043mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad M1-75(51.38mm,86.268mm) on Top Layer And Pad M1-77(50.28mm,87.043mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad PL1-1(62.56mm,41.097mm) on Top Layer And Via (61.163mm,38.1mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.236mm]
Minimum Solder Mask Sliver Constraint: (0.144mm < 0.254mm) Between Pad PR2-1(57.683mm,35.458mm) on Top Layer And Via (58.979mm,36.205mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.144mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U1-1(62.284mm,35.255mm) on Top Layer And Pad U1-2(62.284mm,36.205mm) on Top Layer [Top Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U1-2(62.284mm,36.205mm) on Top Layer And Pad U1-3(62.284mm,37.155mm) on Top Layer [Top Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.151mm < 0.254mm) Between Pad U1-3(62.284mm,37.155mm) on Top Layer And Via (61.163mm,38.1mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.151mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U1-4(59.986mm,37.155mm) on Top Layer And Pad U1-5(59.986mm,36.205mm) on Top Layer [Top Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.189mm < 0.254mm) Between Pad U1-4(59.986mm,37.155mm) on Top Layer And Via (61.163mm,38.1mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.189mm]
Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U1-5(59.986mm,36.205mm) on Top Layer And Pad U1-6(59.986mm,35.255mm) on Top Layer [Top Solder] Mask Sliver [0.215mm]
Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad U1-5(59.986mm,36.205mm) on Top Layer And Via (58.979mm,36.205mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.018mm]
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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (62.436mm,34.537mm) on Top Overlay And Pad U1-1(62.284mm,35.255mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-2(69.63mm,93.818mm) on Top Layer And Track (70.011mm,93.599mm)(71.552mm,93.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad M1-57(55.88mm,86.268mm) on Top Layer And Track (53.761mm,86.487mm)(55.499mm,86.487mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-58(55.63mm,93.818mm) on Top Layer And Track (53.511mm,93.599mm)(55.249mm,93.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-67(53.38mm,86.268mm) on Top Layer And Track (53.761mm,86.487mm)(55.499mm,86.487mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-68(53.13mm,93.818mm) on Top Layer And Track (53.511mm,93.599mm)(55.249mm,93.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-74(51.63mm,93.818mm) on Top Layer And Track (49.708mm,93.599mm)(51.249mm,93.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad M1-76(70.98mm,87.043mm) on Top Layer And Region (0 hole(s)) Top Overlay [Top Overlay] to [Top Solder] clearance [0.225mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-76(70.98mm,87.043mm) on Top Layer And Track (71.552mm,88.649mm)(71.552mm,93.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad M1-77(50.28mm,87.043mm) on Top Layer And Track (49.708mm,88.649mm)(49.708mm,91.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad PC1-1(64.618mm,36.943mm) on Top Layer And Track (64.018mm,36.043mm)(65.218mm,36.043mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad PC1-2(64.618mm,35.143mm) on Top Layer And Track (64.018mm,36.043mm)(65.218mm,36.043mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad PC2-1(55.513mm,39.479mm) on Top Layer And Track (56.413mm,38.879mm)(56.413mm,40.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad PC2-2(57.313mm,39.479mm) on Top Layer And Track (56.413mm,38.879mm)(56.413mm,40.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad PL1-1(62.56mm,41.097mm) on Top Layer And Track (60.613mm,38.938mm)(61.567mm,38.938mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad PL1-1(62.56mm,41.097mm) on Top Layer And Track (60.613mm,43.256mm)(61.567mm,43.256mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad PL1-2(59.62mm,41.097mm) on Top Layer And Track (60.613mm,38.938mm)(61.567mm,38.938mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad PL1-2(59.62mm,41.097mm) on Top Layer And Track (60.613mm,43.256mm)(61.567mm,43.256mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad PR1-1(72.325mm,34.265mm) on Top Layer And Track (71.425mm,33.665mm)(71.425mm,34.865mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad PR1-2(70.525mm,34.265mm) on Top Layer And Track (71.425mm,33.665mm)(71.425mm,34.865mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad PR2-1(57.683mm,35.458mm) on Top Layer And Track (57.083mm,36.358mm)(58.283mm,36.358mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad PR2-2(57.683mm,37.258mm) on Top Layer And Track (57.083mm,36.358mm)(58.283mm,36.358mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad PR3-1(55.55mm,37.258mm) on Top Layer And Track (54.95mm,36.358mm)(56.15mm,36.358mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad PR3-2(55.55mm,35.458mm) on Top Layer And Track (54.95mm,36.358mm)(56.15mm,36.358mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U1-1(62.284mm,35.255mm) on Top Layer And Track (60.246mm,34.666mm)(62.024mm,34.666mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U1-3(62.284mm,37.155mm) on Top Layer And Track (60.246mm,37.744mm)(62.024mm,37.744mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U1-4(59.986mm,37.155mm) on Top Layer And Track (60.246mm,37.744mm)(62.024mm,37.744mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U1-6(59.986mm,35.255mm) on Top Layer And Track (60.246mm,34.666mm)(62.024mm,34.666mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Arc (62.436mm,34.537mm) on Top Overlay And Text "U1" (60.096mm,32.944mm) on Top Overlay Silk Text to Silk Clearance [0.14mm]
Silk To Silk Clearance Constraint: (0.222mm < 0.254mm) Between Text "2" (34.524mm,38.733mm) on Top Overlay And Track (32.746mm,40.003mm)(37.826mm,40.003mm) on Top Overlay Silk Text to Silk Clearance [0.222mm]
Silk To Silk Clearance Constraint: (0.222mm < 0.254mm) Between Text "2" (39.604mm,43.813mm) on Top Overlay And Track (37.826mm,45.083mm)(42.906mm,45.083mm) on Top Overlay Silk Text to Silk Clearance [0.222mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "23" (42.144mm,75.817mm) on Top Overlay And Track (37.826mm,75.563mm)(42.906mm,75.563mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "24" (39.604mm,75.817mm) on Top Overlay And Track (37.826mm,75.563mm)(42.906mm,75.563mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (60.096mm,32.944mm) on Top Overlay And Track (60.246mm,34.666mm)(62.024mm,34.666mm) on Top Overlay Silk Text to Silk Clearance [0mm]
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