Protel Design System Design Rule Check
PCB File : C:\Users\hu123456\Desktop\fsa1\HEADER\HEADER20220623.pcbdoc
Date     : 2022/6/24
Time     : 10:07:02

Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
   Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(80.52mm,85.32mm) on Multi-Layer And Pad CN2-22(79.87mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN2-(87.12mm,85.32mm) on Multi-Layer And Pad CN2-21(87.77mm,83.82mm) on Top Layer [Top Solder] Mask Sliver [0.018mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(62.232mm,85.828mm) on Multi-Layer And Pad CN3-21(61.582mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.018mm < 0.254mm) Between Pad CN3-(68.832mm,85.828mm) on Multi-Layer And Pad CN3-22(69.482mm,84.328mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.018mm]
Rule Violations :4

Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,50.2mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (63.955mm,51.4mm) on Top Overlay And Pad C3-1(64.505mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,46.404mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (63.982mm,48.084mm) on Top Overlay And Pad C2-1(64.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.255mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (66.855mm,51.4mm) on Top Overlay And Pad C3-2(66.305mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.258mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Arc (67.082mm,48.084mm) on Top Overlay And Pad C2-2(66.532mm,47.244mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.131mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (70.393mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,46.81mm) on Top Overlay And Pad C1-2(70.993mm,47.36mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Arc (71.593mm,49.71mm) on Top Overlay And Pad C1-1(70.993mm,49.16mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,48.66mm)(70.193mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.193mm,49.66mm)(70.193mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (70.393mm,49.91mm)(71.593mm,49.91mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,48.66mm)(71.793mm,49.66mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-1(70.993mm,49.16mm) on Top Layer And Track (71.793mm,49.66mm)(71.793mm,49.71mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.81mm)(70.193mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.193mm,46.86mm)(70.193mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (70.393mm,46.61mm)(71.593mm,46.61mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.81mm)(71.793mm,46.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C1-2(70.993mm,47.36mm) on Top Layer And Track (71.793mm,46.86mm)(71.793mm,47.86mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,46.404mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.064mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.782mm,48.044mm)(63.782mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,46.204mm)(65.032mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(64.532mm,47.244mm) on Top Layer And Track (63.982mm,48.284mm)(65.032mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,46.204mm)(67.082mm,46.204mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (66.032mm,48.284mm)(67.082mm,48.284mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad C2-2(66.532mm,47.244mm) on Top Layer And Track (67.282mm,48.044mm)(67.282mm,48.084mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.755mm,50.2mm)(63.755mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,50mm)(64.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (63.955mm,51.6mm)(64.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,50mm)(65.005mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-1(64.505mm,50.8mm) on Top Layer And Track (64.005mm,51.6mm)(65.005mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,50mm)(66.805mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (65.805mm,51.6mm)(66.805mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,50mm)(66.855mm,50mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (66.805mm,51.6mm)(66.855mm,51.6mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad C3-2(66.305mm,50.8mm) on Top Layer And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.168mm < 0.254mm) Between Pad CN1-1(68.604mm,45.135mm) on Bottom Layer And Track (68.204mm,42.86mm)(68.204mm,44.54mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.168mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.116mm < 0.254mm) Between Pad CN1-3(68.604mm,47.635mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.116mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-4(68.604mm,48.885mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-5(68.604mm,50.135mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Text "CN1" (69.302mm,48.123mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad CN1-6(68.604mm,51.385mm) on Bottom Layer And Track (68.218mm,51.941mm)(68.218mm,53.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-7(65.254mm,53.235mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad CN1-8(65.254mm,43.285mm) on Bottom Layer And Track (64.034mm,44.06mm)(64.034mm,52.46mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.148mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.451mm,81.28mm)(86.48mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN2-1(86.07mm,82.02mm) on Top Layer And Track (86.48mm,81.28mm)(87.496mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-10(81.57mm,82.02mm) on Top Layer And Track (80.137mm,81.28mm)(81.189mm,81.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN2-11(81.57mm,85.62mm) on Top Layer And Track (80.137mm,86.36mm)(81.189mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.111mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-20(86.07mm,85.62mm) on Top Layer And Track (86.451mm,86.36mm)(87.496mm,86.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-21(87.77mm,83.82mm) on Top Layer And Track (87.496mm,81.28mm)(87.496mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.14mm < 0.254mm) Between Pad CN2-22(79.87mm,83.82mm) on Top Layer And Track (80.137mm,81.28mm)(80.137mm,82.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.14mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (61.856mm,81.788mm)(62.872mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.133mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-1(63.282mm,82.528mm) on Bottom Layer And Track (62.872mm,81.788mm)(62.901mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-10(67.782mm,82.528mm) on Bottom Layer And Track (68.163mm,81.788mm)(69.215mm,81.788mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-11(67.782mm,86.128mm) on Bottom Layer And Track (68.163mm,86.868mm)(69.215mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad CN3-20(63.282mm,86.128mm) on Bottom Layer And Track (61.856mm,86.868mm)(62.901mm,86.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.136mm < 0.254mm) Between Pad CN3-21(61.582mm,84.328mm) on Bottom Layer And Track (61.856mm,81.788mm)(61.856mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.136mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-22(69.482mm,84.328mm) on Bottom Layer And Track (69.215mm,81.788mm)(69.215mm,83.197mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(77.925mm,50.643mm) on Bottom Layer And Track (77.851mm,51.124mm)(77.851mm,53.868mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(77.925mm,49.393mm) on Bottom Layer And Track (77.851mm,49.874mm)(77.851mm,50.162mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-3(77.925mm,48.143mm) on Bottom Layer And Track (77.851mm,48.624mm)(77.851mm,48.912mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,46.124mm)(77.851mm,46.412mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-4(77.925mm,46.893mm) on Bottom Layer And Track (77.851mm,47.374mm)(77.851mm,47.662mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (77.851mm,53.893mm)(79.094mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-5(80.825mm,53.193mm) on Bottom Layer And Track (82.556mm,53.893mm)(83.425mm,53.893mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (77.851mm,43.643mm)(79.094mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-6(80.825mm,44.343mm) on Bottom Layer And Track (82.556mm,43.643mm)(83.425mm,43.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,52.828mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (65.905mm,54.868mm)(67.155mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(66.405mm,53.848mm) on Top Layer And Track (67.155mm,54.868mm)(67.155mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(63.655mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,52.828mm)(64.905mm,52.828mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(64.405mm,53.848mm) on Top Layer And Track (63.655mm,54.868mm)(64.905mm,54.868mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.176mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.176mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(70.078mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R2-1(70.828mm,52.451mm) on Bottom Layer And Track (70.078mm,53.251mm)(71.328mm,53.251mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (71.929mm,53.246mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R2-2(72.428mm,52.451mm) on Bottom Layer And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2_5V(82.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D-(80.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2D+(78.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad U1-u2GND(76.18mm,56.94mm) on Multi-Layer And Track (56.48mm,58.04mm)(85.98mm,58.04mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3_5v(76.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D-(78.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-U3D+(80.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Text "GND" (81.326mm,42.927mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.253mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad U1-u3GND(82.08mm,40.24mm) on Multi-Layer And Track (56.48mm,39.14mm)(85.98mm,39.14mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad U1-u4Gnd(68.88mm,40.74mm) on Multi-Layer And Text "GND" (68.245mm,43.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-1(75.184mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-10(82.804mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-11(81.534mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-12(80.264mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Text "U2" (79.375mm,53.327mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.232mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-13(78.994mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-14(77.724mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-15(76.454mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-16(75.184mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-2(76.454mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-3(77.724mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-4(78.994mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-5(80.264mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-6(81.534mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-7(82.804mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad U2-8(84.074mm,46.812mm) on Top Layer And Track (74.679mm,47.934mm)(84.579mm,47.934mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.159mm < 0.254mm) Between Pad U2-9(84.074mm,52.756mm) on Top Layer And Track (74.679mm,51.634mm)(84.579mm,51.634mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.159mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Text "R2" (71.579mm,51.88mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (71.183mm,49.186mm)(71.802mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-1(72.263mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "G" (75.692mm,49.892mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.131mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Text "R" (75.565mm,48.622mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.129mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (72.724mm,49.186mm)(74.342mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad U3-2(74.803mm,50.236mm) on Bottom Layer And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.208mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Text "U3" (73.279mm,42.941mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-3(74.803mm,43.236mm) on Bottom Layer And Track (75.264mm,44.286mm)(75.883mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.103mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (71.183mm,44.286mm)(71.802mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.103mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.232mm < 0.254mm) Between Pad U3-4(72.263mm,43.236mm) on Bottom Layer And Track (72.724mm,44.286mm)(74.342mm,44.286mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.232mm]
Rule Violations :134

Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
   Violation between Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Arc (66.855mm,50.2mm) on Top Overlay And Text "C3" (67.437mm,49.467mm) on Top Overlay Silk Text to Silk Clearance [0.179mm]
   Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Arc (67.082mm,46.404mm) on Top Overlay And Text "C2" (67.564mm,45.91mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
   Violation between Silk To Silk Clearance Constraint: (0.063mm < 0.254mm) Between Text "5V" (81.199mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0.063mm]
   Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.404mm)(67.282mm,46.444mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
   Violation between Silk To Silk Clearance Constraint: (0.079mm < 0.254mm) Between Text "C2" (67.564mm,45.91mm) on Top Overlay And Track (67.282mm,46.444mm)(67.282mm,48.044mm) on Top Overlay Silk Text to Silk Clearance [0.079mm]
   Violation between Silk To Silk Clearance Constraint: (0.179mm < 0.254mm) Between Text "C3" (67.437mm,49.467mm) on Top Overlay And Track (67.055mm,50.2mm)(67.055mm,51.4mm) on Top Overlay Silk Text to Silk Clearance [0.179mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "D-" (69.85mm,48.406mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN1" (69.302mm,48.123mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN5" (83.376mm,47.625mm) on Bottom Overlay And Track (83.425mm,43.643mm)(83.425mm,53.893mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Text "v" (70.202mm,48.146mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (69.85mm,48.406mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D-" (79.675mm,55.5mm) on Top Overlay And Text "U2" (79.375mm,53.327mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Text "G" (69.977mm,45.993mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "D+" (69.977mm,47.136mm) on Bottom Overlay And Track (71.183mm,44.286mm)(71.183mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.155mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Text "T" (75.441mm,47.372mm) on Bottom Overlay Silk Text to Silk Clearance [0.155mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.264mm,49.186mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.089mm < 0.254mm) Between Text "R" (75.565mm,48.622mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.089mm]
   Violation between Silk To Silk Clearance Constraint: (0.048mm < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (70.078mm,51.651mm)(71.328mm,51.651mm) on Bottom Overlay Silk Text to Silk Clearance [0.048mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (71.929mm,51.646mm)(73.179mm,51.646mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (71.579mm,51.88mm) on Bottom Overlay And Track (73.179mm,51.646mm)(73.179mm,53.246mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "T" (75.441mm,47.372mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (85.786mm,48.819mm) on Top Overlay And Track (85.98mm,39.14mm)(85.98mm,58.04mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "V" (75.708mm,46.109mm) on Bottom Overlay And Track (75.883mm,44.286mm)(75.883mm,49.186mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm]
Rule Violations :23

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 161
Waived Violations : 0
Time Elapsed        : 00:00:00