210 lines
39 KiB
Plaintext
210 lines
39 KiB
Plaintext
Protel Design System Design Rule Check
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PCB File : C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc
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Date : 2022/7/7
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Time : 16:14:59
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Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
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Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
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Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm
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Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
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Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm
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Rule Violations :4
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Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
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Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||
Rule Violations :130
|
||
|
||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||
Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V<35><56><EFBFBD><EFBFBD>" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V<39><56><EFBFBD><EFBFBD>" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]
|
||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]
|
||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]
|
||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]
|
||
Rule Violations :28
|
||
|
||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||
Rule Violations :0
|
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|
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Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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Rule Violations :0
|
||
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Violations Detected : 162
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Waived Violations : 0
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Time Elapsed : 00:00:01 |