77 lines
7.0 KiB
Plaintext
77 lines
7.0 KiB
Plaintext
Protel Design System Design Rule Check
|
||
PCB File : C:\Users\hu123456\Desktop\TC300ת½Ó°å\PCB2.PcbDoc
|
||
Date : 2022/7/7
|
||
Time : 15:09:22
|
||
|
||
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Un-Routed Net Constraint ( (All) )
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
|
||
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-10(94.75mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
|
||
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-11(83.05mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
|
||
Rule Violations :2
|
||
|
||
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(86.65mm,67.901mm) on Multi-Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(91.15mm,67.901mm) on Multi-Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-9(92.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-5(84.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Via (88.341mm,67.996mm) from Top Layer to Bottom Layer And Via (88.976mm,67.31mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.231mm] / [Bottom Solder] Mask Sliver [0.231mm]
|
||
Violation between Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (89.865mm,81.91mm) from Top Layer to Bottom Layer And Via (90.297mm,81.102mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]
|
||
Rule Violations :12
|
||
|
||
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-1(85.139mm,78.959mm) on Top Layer And Track (82.639mm,78.996mm)(84.639mm,78.996mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-15(92.139mm,78.959mm) on Top Layer And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,78.996mm)(82.639mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.959mm)(82.639mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.997mm)(82.639mm,82.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.587mm,82.959mm)(94.587mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad P2-5(84.9mm,70.101mm) on Top Layer And Track (83.058mm,70.101mm)(84.328mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm]
|
||
Violation between Silk To Solder Mask Clearance Constraint: (0.095mm < 0.254mm) Between Pad P2-9(92.9mm,70.101mm) on Top Layer And Track (93.472mm,70.101mm)(94.742mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.095mm]
|
||
Rule Violations :9
|
||
|
||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||
Violation between Silk To Silk Clearance Constraint: (0.17mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay Silk Text to Silk Clearance [0.17mm]
|
||
Violation between Silk To Silk Clearance Constraint: (0.197mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay Silk Text to Silk Clearance [0.197mm]
|
||
Rule Violations :2
|
||
|
||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||
Rule Violations :0
|
||
|
||
Processing Rule : Matched Lengths(Tolerance=25.4mm) (All)
|
||
Violation between Matched Net Lengths: Between Net GND And Net ID Length:0mm is not within 25.4mm tolerance of Length:28.32mm (2.92mm short)
|
||
Rule Violations :1
|
||
|
||
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
|
||
Rule Violations :0
|
||
|
||
|
||
Violations Detected : 26
|
||
Waived Violations : 0
|
||
Time Elapsed : 00:00:01 |