ELEC/fsa1/sw/Design Rule Check - FSA_SW_PCB 微调_2022-06-23.drc

Protel Design System Design Rule Check
PCB File : C:\Users\hu123456\Desktop\fsa1\sw\FSA_SW_PCB ΢µ÷_2022-06-23.pcbdoc
Date     : 2022/6/24
Time     : 10:25:55

Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
   Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Pad IN-2(41.031mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.146mm] / [Bottom Solder] Mask Sliver [0.047mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Pad OUT-2(62.24mm,40.45mm) on Multi-Layer [Top Solder] Mask Sliver [0.221mm] / [Bottom Solder] Mask Sliver [0.047mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.244mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Region (0 hole(s)) Top Solder [Top Solder] Mask Sliver [0.244mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Pad SW1-2(50.117mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Pad SW1-3(50.117mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Pad SW1-5(45.617mm,43.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
   Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Pad SW1-6(45.617mm,45.179mm) on Multi-Layer [Top Solder] Mask Sliver [0.197mm] / [Bottom Solder] Mask Sliver [0.197mm]
Rule Violations :8

Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
   Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.133mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Pad LED1-1(56.697mm,43.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.221mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad IN-1(42.281mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad IN-2(41.031mm,40.45mm) on Multi-Layer And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad LED1-1(56.697mm,43.179mm) on Multi-Layer And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.083mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.083mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,41.857mm)(59.467mm,42.129mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.233mm < 0.254mm) Between Pad LED1-2(59.237mm,43.179mm) on Multi-Layer And Track (59.467mm,44.23mm)(59.467mm,44.502mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.233mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad OUT-1(63.49mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.135mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad OUT-2(62.24mm,40.45mm) on Multi-Layer And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.223mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Text "R1" (52.324mm,44.069mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(53.086mm,43.535mm) on Top Layer And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.118mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(52.291mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.118mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (52.291mm,41.185mm)(53.891mm,41.185mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.128mm < 0.254mm) Between Pad R1-2(53.086mm,41.936mm) on Top Layer And Track (53.891mm,41.185mm)(53.891mm,42.435mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.128mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.618mm,40.28mm)(50.767mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,40.28mm)(50.767mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-1(50.117mm,41.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,41.979mm)(50.767mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-2(50.117mm,43.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.221mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Text "IRIS 20211217" (59.944mm,44.005mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.221mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.618mm,46.079mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,43.979mm)(50.767mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.243mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.121mm < 0.254mm) Between Pad SW1-3(50.117mm,45.179mm) on Multi-Layer And Track (50.767mm,45.979mm)(50.767mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.121mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(44.967mm,40.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.174mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,40.28mm)(45.116mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.174mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad SW1-4(45.617mm,41.179mm) on Multi-Layer And Track (46.118mm,40.28mm)(49.616mm,40.28mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,41.979mm)(44.967mm,42.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-5(45.617mm,43.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,43.979mm)(44.967mm,44.38mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,45.979mm)(44.967mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.218mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.242mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (44.967mm,46.079mm)(45.116mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.242mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.207mm < 0.254mm) Between Pad SW1-6(45.617mm,45.179mm) on Multi-Layer And Track (46.118mm,46.079mm)(49.616mm,46.079mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.207mm]
Rule Violations :39

Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (57.967mm,43.179mm) on Top Overlay And Text "LED1" (56.388mm,44.958mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(39.481mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
   Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (39.243mm,39.243mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
   Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(60.69mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
   Violation between Silk To Silk Clearance Constraint: (0.047mm < 0.254mm) Between Text "G" (60.452mm,39.243mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.047mm]
   Violation between Silk To Silk Clearance Constraint: (0.042mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (39.481mm,44.649mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.042mm]
   Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "IN" (42.989mm,44.895mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.185mm]
   Violation between Silk To Silk Clearance Constraint: (0.039mm < 0.254mm) Between Text "LED1" (56.388mm,44.958mm) on Top Overlay And Track (57.367mm,44.179mm)(57.367mm,44.779mm) on Top Overlay Silk Text to Silk Clearance [0.039mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (60.69mm,44.649mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "OUT" (64.897mm,44.577mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,43.035mm)(52.286mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (52.286mm,44.285mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (52.324mm,44.069mm) on Top Overlay And Track (53.886mm,43.035mm)(53.886mm,44.285mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (39.481mm,39.688mm)(43.831mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (44.927mm,39.415mm) on Bottom Overlay And Track (43.831mm,39.688mm)(43.831mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.108mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (60.69mm,39.688mm)(65.04mm,39.688mm) on Bottom Overlay Silk Text to Silk Clearance [0.108mm]
   Violation between Silk To Silk Clearance Constraint: (0.056mm < 0.254mm) Between Text "v" (65.69mm,39.542mm) on Bottom Overlay And Track (65.04mm,39.688mm)(65.04mm,44.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.056mm]
Rule Violations :17

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 64
Waived Violations : 0
Time Elapsed        : 00:00:00