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ELEC/ROCK BORD/Project Outputs for PCB_Project2/Design Rule Check - PCB2.drc
yunyifeng 6e3f165d4f 2022.7.13
2022-07-13 09:25:30 +08:00

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Protel Design System Design Rule Check
PCB File : C:\Users\hu123456\Desktop\ROCK BORD\PCB2.PcbDoc
Date : 2022/6/29
Time : 14:05:00
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Violation between Hole Size Constraint: (2.56mm > 2.54mm) Pad Free-1(142.951mm,70.251mm) on Multi-Layer Actual Hole Size = 2.56mm
Violation between Hole Size Constraint: (2.56mm > 2.54mm) Pad U1-1(123.774mm,124.116mm) on Multi-Layer Actual Hole Size = 2.56mm
Violation between Hole Size Constraint: (2.56mm > 2.54mm) Pad U1-1(123.774mm,66.116mm) on Multi-Layer Actual Hole Size = 2.56mm
Violation between Hole Size Constraint: (2.56mm > 2.54mm) Pad U1-1(172.774mm,124.116mm) on Multi-Layer Actual Hole Size = 2.56mm
Violation between Hole Size Constraint: (2.56mm > 2.54mm) Pad U1-1(172.774mm,66.116mm) on Multi-Layer Actual Hole Size = 2.56mm
Rule Violations :5
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad CN1-1(133.701mm,115.763mm) on Top Layer And Pad CN1-76(132.601mm,114.988mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad CN1-75(152.201mm,115.763mm) on Top Layer And Pad CN1-77(153.301mm,114.988mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-1(125.679mm,97.144mm) on Top Layer And Pad CN2-2(125.679mm,98.394mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-2(125.679mm,98.394mm) on Top Layer And Pad CN2-3(125.679mm,99.644mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-3(125.679mm,99.644mm) on Top Layer And Pad CN2-4(125.679mm,100.894mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-4(125.679mm,100.894mm) on Top Layer And Pad CN2-5(125.679mm,102.144mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-5(125.679mm,102.144mm) on Top Layer And Pad CN2-6(125.679mm,103.394mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-6(125.679mm,103.394mm) on Top Layer And Pad CN2-7(125.679mm,104.644mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-7(125.679mm,104.644mm) on Top Layer And Pad CN2-8(125.679mm,105.894mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN2-8(125.679mm,105.894mm) on Top Layer And Pad CN2-9(125.679mm,107.144mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-1(152.46mm,68.428mm) on Top Layer And Pad CN4-2(153.71mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-10(163.71mm,68.428mm) on Top Layer And Pad CN4-9(162.46mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-2(153.71mm,68.428mm) on Top Layer And Pad CN4-3(154.96mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-3(154.96mm,68.428mm) on Top Layer And Pad CN4-4(156.21mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-4(156.21mm,68.428mm) on Top Layer And Pad CN4-5(157.46mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-5(157.46mm,68.428mm) on Top Layer And Pad CN4-6(158.71mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-6(158.71mm,68.428mm) on Top Layer And Pad CN4-7(159.96mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-7(159.96mm,68.428mm) on Top Layer And Pad CN4-8(161.21mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad CN4-8(161.21mm,68.428mm) on Top Layer And Pad CN4-9(162.46mm,68.428mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad LD-3(162.132mm,91.969mm) on Bottom Layer And Via (160.02mm,91.923mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (135.395mm,103.632mm) from Top Layer to Bottom Layer And Via (135.433mm,102.413mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm]
Rule Violations :21
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (0.122mm < 0.254mm) Between Arc (123.774mm,124.116mm) on Bottom Overlay And Pad U1-1(123.774mm,124.116mm) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0.122mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.122mm < 0.254mm) Between Arc (123.774mm,66.116mm) on Bottom Overlay And Pad U1-1(123.774mm,66.116mm) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0.122mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (151.038mm,85.226mm) on Top Overlay And Pad MAX1-1(151.038mm,85.979mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.122mm < 0.254mm) Between Arc (172.774mm,124.116mm) on Bottom Overlay And Pad U1-1(172.774mm,124.116mm) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0.122mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.122mm < 0.254mm) Between Arc (172.774mm,66.116mm) on Bottom Overlay And Pad U1-1(172.774mm,66.116mm) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0.122mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad CN1-2(133.951mm,108.214mm) on Top Layer And Track (132.029mm,108.432mm)(133.57mm,108.432mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-57(147.701mm,115.763mm) on Top Layer And Track (148.082mm,115.544mm)(149.82mm,115.544mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-58(147.951mm,108.214mm) on Top Layer And Track (148.332mm,108.432mm)(150.07mm,108.432mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-67(150.201mm,115.763mm) on Top Layer And Track (148.082mm,115.544mm)(149.82mm,115.544mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad CN1-68(150.451mm,108.214mm) on Top Layer And Track (148.332mm,108.432mm)(150.07mm,108.432mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-74(151.951mm,108.214mm) on Top Layer And Track (152.332mm,108.432mm)(153.873mm,108.432mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad CN1-76(132.601mm,114.988mm) on Top Layer And Region (0 hole(s)) Top Overlay [Top Overlay] to [Top Solder] clearance [0.225mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-76(132.601mm,114.988mm) on Top Layer And Track (132.029mm,108.432mm)(132.029mm,113.382mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad CN1-77(153.301mm,114.988mm) on Top Layer And Track (153.873mm,110.853mm)(153.873mm,113.382mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad CN2-1(125.679mm,97.144mm) on Top Layer And Track (125.251mm,93.905mm)(125.251mm,96.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad CN2-10(122.779mm,109.645mm) on Top Layer And Track (120.679mm,110.394mm)(121.048mm,110.394mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-10(122.779mm,109.645mm) on Top Layer And Track (124.51mm,110.394mm)(125.251mm,110.394mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.054mm < 0.254mm) Between Pad CN2-11(122.779mm,94.644mm) on Top Layer And Track (120.679mm,93.894mm)(121.098mm,93.894mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.054mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.13mm < 0.254mm) Between Pad CN2-11(122.779mm,94.644mm) on Top Layer And Track (124.536mm,93.895mm)(125.251mm,93.894mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.13mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN2-9(125.679mm,107.144mm) on Top Layer And Track (125.251mm,107.775mm)(125.251mm,110.394mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad CN3-1(131.907mm,68.425mm) on Top Layer And Track (128.882mm,68.596mm)(131.422mm,68.596mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-4(135.657mm,68.425mm) on Top Layer And Track (136.138mm,68.649mm)(138.682mm,68.649mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-5(138.682mm,65.675mm) on Top Layer And Track (138.682mm,63.135mm)(138.682mm,63.944mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN3-5(138.682mm,65.675mm) on Top Layer And Track (138.682mm,67.406mm)(138.682mm,68.649mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN3-6(128.932mm,65.535mm) on Top Layer And Track (128.882mm,63.135mm)(128.882mm,63.944mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad CN3-6(128.932mm,65.535mm) on Top Layer And Track (128.882mm,67.406mm)(128.882mm,68.596mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN4-1(152.46mm,68.428mm) on Top Layer And Track (149.435mm,68.449mm)(151.975mm,68.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN4-10(163.71mm,68.428mm) on Top Layer And Track (164.341mm,68.449mm)(166.735mm,68.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN4-11(166.26mm,65.528mm) on Top Layer And Text "3.3V SDA1SCL1 IO7 GND IO0 IO2 IO3 3.3V MOSI MISO SCLKGNDSDA0 IO21IO22 IO23 IO24 IO25 GND" (167.217mm,120.262mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN4-11(166.26mm,65.528mm) on Top Layer And Track (166.735mm,62.988mm)(166.735mm,63.796mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN4-11(166.26mm,65.528mm) on Top Layer And Track (166.735mm,67.259mm)(166.735mm,68.378mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN4-12(149.91mm,65.528mm) on Top Layer And Track (149.435mm,62.988mm)(149.435mm,63.796mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN4-12(149.91mm,65.528mm) on Top Layer And Track (149.435mm,67.259mm)(149.435mm,68.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(126.517mm,73.985mm) on Top Layer And Track (125.753mm,72.476mm)(125.753mm,73.404mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(126.517mm,73.985mm) on Top Layer And Track (125.753mm,74.566mm)(125.753mm,74.654mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(126.517mm,75.235mm) on Top Layer And Track (125.753mm,74.566mm)(125.753mm,74.654mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(126.517mm,75.235mm) on Top Layer And Track (125.753mm,75.816mm)(125.753mm,76.755mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad CN5-3(123.429mm,71.142mm) on Top Layer And Track (122.052mm,72.487mm)(122.052mm,76.755mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.018mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad CN5-3(123.429mm,71.142mm) on Top Layer And Track (122.053mm,72.476mm)(125.753mm,72.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.007mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.003mm < 0.254mm) Between Pad CN5-4(123.427mm,78.085mm) on Top Layer And Track (122.052mm,72.487mm)(122.052mm,76.755mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.003mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.003mm < 0.254mm) Between Pad CN5-4(123.427mm,78.085mm) on Top Layer And Track (122.053mm,76.755mm)(125.753mm,76.755mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.003mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-1(164.262mm,103.937mm) on Top Layer And Track (164.993mm,105.088mm)(166.739mm,105.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.119mm < 0.254mm) Between Pad CN7-2(162.262mm,103.937mm) on Top Layer And Track (159.77mm,105.094mm)(161.516mm,105.094mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.119mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.098mm < 0.254mm) Between Pad CN7-3(159.912mm,109.287mm) on Top Layer And Track (159.262mm,103.443mm)(159.262mm,107.362mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.098mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-3(159.912mm,109.287mm) on Top Layer And Track (160.882mm,111.057mm)(165.642mm,111.057mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN7-4(166.612mm,109.287mm) on Top Layer And Text "3.3V SDA1SCL1 IO7 GND IO0 IO2 IO3 3.3V MOSI MISO SCLKGNDSDA0 IO21IO22 IO23 IO24 IO25 GND" (167.217mm,120.262mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-4(166.612mm,109.287mm) on Top Layer And Track (160.882mm,111.057mm)(165.642mm,111.057mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.254mm) Between Pad CN7-4(166.612mm,109.287mm) on Top Layer And Track (167.247mm,103.437mm)(167.247mm,107.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.131mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad CN8-1(125.702mm,88.438mm) on Top Layer And Track (125.873mm,88.923mm)(125.873mm,91.463mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-4(125.702mm,84.688mm) on Top Layer And Track (125.926mm,81.663mm)(125.926mm,84.207mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-5(122.952mm,81.663mm) on Top Layer And Track (120.412mm,81.663mm)(121.221mm,81.663mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-5(122.952mm,81.663mm) on Top Layer And Track (124.683mm,81.663mm)(125.926mm,81.663mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN8-6(122.812mm,91.413mm) on Top Layer And Track (120.412mm,91.463mm)(121.221mm,91.463mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad CN8-6(122.812mm,91.413mm) on Top Layer And Track (124.683mm,91.463mm)(125.873mm,91.463mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-1(158.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-1(158.176mm,121.499mm) on Top Layer And Track (158.626mm,121.499mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-1(158.176mm,121.499mm) on Top Layer And Track (158.626mm,121.499mm)(161.293mm,121.499mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-10(153.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-11(153.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-12(152.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-13(152.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-14(151.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-15(151.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-16(150.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-17(150.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-18(149.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-19(149.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-2(157.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-20(148.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-21(148.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-22(147.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-23(147.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-24(146.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-25(146.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-26(145.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-27(145.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-28(144.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-29(144.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-3(157.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-30(143.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-31(143.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-32(142.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-33(142.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-34(141.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-35(141.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-36(140.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-37(140.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-38(139.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-39(139.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-4(156.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-40(138.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-41(138.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-42(137.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-43(137.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-44(136.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-45(136.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-46(135.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-47(135.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-48(134.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-49(134.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-5(156.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-50(133.676mm,121.499mm) on Top Layer And Track (130.559mm,121.499mm)(133.226mm,121.499mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-50(133.676mm,121.499mm) on Top Layer And Track (133.226mm,121.499mm)(133.226mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-50(133.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad FPC2-51(131.826mm,123.874mm) on Top Layer And Track (130.559mm,121.499mm)(130.559mm,126.579mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad FPC2-52(160.026mm,123.874mm) on Top Layer And Track (161.293mm,121.499mm)(161.293mm,126.579mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-6(155.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-7(155.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-8(154.676mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-9(154.176mm,121.499mm) on Top Layer And Track (133.226mm,122.388mm)(158.626mm,122.388mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.079mm < 0.254mm) Between Pad LD-1(160.942mm,99.699mm) on Bottom Layer And Track (124.742mm,101.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.079mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-1(160.942mm,99.699mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad LD-10(125.552mm,89.429mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.243mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad LD-11(125.552mm,86.889mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.243mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad LD-12(126.942mm,81.699mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.21mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad LD-12(126.942mm,81.699mm) on Bottom Layer And Track (124.742mm,79.699mm)(162.942mm,79.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.245mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-2(162.132mm,94.51mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-3(162.132mm,91.969mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-4(162.132mm,89.429mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-5(162.132mm,86.889mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.079mm < 0.254mm) Between Pad LD-6(160.942mm,81.699mm) on Bottom Layer And Track (124.742mm,79.699mm)(162.942mm,79.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.079mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad LD-6(160.942mm,81.699mm) on Bottom Layer And Track (162.942mm,79.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad LD-7(126.942mm,99.699mm) on Bottom Layer And Track (124.742mm,101.699mm)(162.942mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.245mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad LD-7(126.942mm,99.699mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.21mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad LD-8(125.552mm,94.51mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.243mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.243mm < 0.254mm) Between Pad LD-9(125.552mm,91.969mm) on Bottom Layer And Track (124.742mm,79.699mm)(124.742mm,101.699mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.243mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-1(151.038mm,85.979mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-10(145.567mm,93.599mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-11(145.567mm,92.329mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-12(145.567mm,91.059mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-13(145.567mm,89.789mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-14(145.567mm,88.519mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-15(145.567mm,87.249mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-16(145.567mm,85.979mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-2(151.038mm,87.249mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-3(151.038mm,88.519mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-4(151.038mm,89.789mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-5(151.038mm,91.059mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-6(151.038mm,92.329mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-7(151.038mm,93.599mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.254mm < 0.254mm) Between Pad MAX1-8(151.038mm,94.869mm) on Top Layer And Track (149.824mm,85.398mm)(149.824mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.254mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad MAX1-9(145.567mm,94.869mm) on Top Layer And Track (146.782mm,85.398mm)(146.782mm,95.45mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.199mm < 0.254mm) Between Pad U1-1(171.504mm,119.246mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.199mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.11mm < 0.254mm) Between Pad U1-1(172.774mm,66.116mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.11mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-11(171.504mm,106.546mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-13(171.504mm,104.006mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.205mm < 0.254mm) Between Pad U1-15(171.504mm,101.466mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.205mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad U1-17(171.504mm,98.926mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.202mm < 0.254mm) Between Pad U1-23(171.504mm,91.306mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.202mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.201mm < 0.254mm) Between Pad U1-25(171.504mm,88.766mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.201mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-27(171.504mm,86.226mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad U1-29(171.504mm,83.686mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.244mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.209mm < 0.254mm) Between Pad U1-3(171.504mm,116.706mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.209mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-33(171.504mm,78.606mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad U1-35(171.504mm,76.066mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad U1-37(171.504mm,73.526mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-39(171.504mm,70.986mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad U1-5(171.504mm,114.166mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.238mm < 0.254mm) Between Pad U1-7(171.504mm,111.626mm) on Multi-Layer And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.238mm]
Rule Violations :159
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Arc (172.774mm,66.116mm) on Bottom Overlay And Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "3.3V SDA1SCL1 IO7 GND IO0 IO2 IO3 3.3V MOSI MISO SCLKGNDSDA0 IO21IO22 IO23 IO24 IO25 GND" (167.217mm,120.262mm) on Top Overlay And Track (166.739mm,103.437mm)(167.247mm,103.437mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "3.3V SDA1SCL1 IO7 GND IO0 IO2 IO3 3.3V MOSI MISO SCLKGNDSDA0 IO21IO22 IO23 IO24 IO25 GND" (167.217mm,120.262mm) on Top Overlay And Track (167.247mm,103.437mm)(167.247mm,107.356mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "3.3V SDA1SCL1 IO7 GND IO0 IO2 IO3 3.3V MOSI MISO SCLKGNDSDA0 IO21IO22 IO23 IO24 IO25 GND" (168.679mm,120.135mm) on Bottom Overlay And Track (120.269mm,62.782mm)(176.267mm,62.782mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay And Track (120.269mm,62.782mm)(176.267mm,62.782mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay And Track (170.234mm,69.716mm)(170.234mm,120.516mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "5V 5V GND TXD RXD IO1 GND IO4 IO5 GND IO6 CE0 CE1 SCL0 GND IO26 GND IO27 IO28 IO29" (170.33mm,120.008mm) on Bottom Overlay And Track (170.234mm,69.716mm)(175.314mm,69.716mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.254mm < 0.254mm) Between Text "CN1" (154.381mm,112.7mm) on Top Overlay And Track (153.873mm,108.432mm)(153.873mm,110.124mm) on Top Overlay Silk Text to Silk Clearance [0.254mm]
Violation between Silk To Silk Clearance Constraint: (0.254mm < 0.254mm) Between Text "CN1" (154.381mm,112.7mm) on Top Overlay And Track (153.873mm,110.853mm)(153.873mm,113.382mm) on Top Overlay Silk Text to Silk Clearance [0.254mm]
Violation between Silk To Silk Clearance Constraint: (0.144mm < 0.254mm) Between Text "CN7" (161.265mm,111.455mm) on Top Overlay And Track (160.882mm,111.057mm)(165.642mm,111.057mm) on Top Overlay Silk Text to Silk Clearance [0.144mm]
Violation between Silk To Silk Clearance Constraint: (0.155mm < 0.254mm) Between Text "LD" (156.794mm,102.108mm) on Bottom Overlay And Track (124.742mm,101.699mm)(162.942mm,101.699mm) on Bottom Overlay Silk Text to Silk Clearance [0.155mm]
Rule Violations :11
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 196
Waived Violations : 0
Time Elapsed : 00:00:01
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