yunyifeng/ELEC
2
1
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Files
db6b056e981fd4f0b105351634afd013c4f967c2
ELEC/air/大版/Project Outputs for PCB_Project2/Design Rule Check - PCB2.drc
yunyifeng db6b056e98 2022,6,13
2022-06-13 17:34:24 +08:00

235 lines
46 KiB
Plaintext
Raw Blame History

Protel Design System Design Rule Check
PCB File : C:\Users\hu123456\Desktop\air\´ó°æ\PCB2.PcbDoc
Date : 2022/4/27
Time : 14:57:35
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad U1-(45.339mm,119.976mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad U1-(45.339mm,61.976mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad U1-(94.339mm,119.976mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad U1-(94.339mm,61.976mm) on Multi-Layer Actual Hole Size = 2.7mm
Rule Violations :4
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad CN1-1(56.198mm,113.741mm) on Top Layer And Pad CN1-76(55.098mm,112.966mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.15mm < 0.254mm) Between Pad CN1-68(72.948mm,106.191mm) on Top Layer And Via (72.949mm,107.569mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.15mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.207mm < 0.254mm) Between Pad CN1-70(73.448mm,106.191mm) on Top Layer And Via (72.949mm,107.569mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.207mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.147mm < 0.254mm) Between Pad CN1-75(74.698mm,113.741mm) on Top Layer And Pad CN1-77(75.798mm,112.966mm) on Top Layer [Top Solder] Mask Sliver [0.147mm]
Rule Violations :4
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (45.339mm,61.976mm) on Top Overlay And Pad CN5-3(45.933mm,65.763mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-1(56.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-10(58.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-11(58.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-12(58.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-13(59.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-14(59.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-15(59.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-16(59.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-17(60.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-18(60.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-19(60.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-2(56.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad CN1-2(56.448mm,106.191mm) on Top Layer And Track (54.526mm,106.41mm)(56.067mm,106.41mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-20(60.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-21(61.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-22(61.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-23(61.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-24(61.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-25(62.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-26(62.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-27(62.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-28(62.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-29(63.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-3(56.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-30(63.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-31(63.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-32(63.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-33(64.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-34(64.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-35(64.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-36(64.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-37(65.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-38(65.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-39(65.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-4(56.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-40(65.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-41(66.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-42(66.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-43(66.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-44(66.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-45(67.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-46(67.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-47(67.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-48(67.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-49(68.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-5(57.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-50(68.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-51(68.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-52(68.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-53(69.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-54(69.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-55(69.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-56(69.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-57(70.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-57(70.198mm,113.741mm) on Top Layer And Track (70.579mm,113.522mm)(72.317mm,113.522mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-58(70.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-58(70.448mm,106.191mm) on Top Layer And Track (70.829mm,106.41mm)(72.567mm,106.41mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-6(57.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-67(72.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-67(72.698mm,113.741mm) on Top Layer And Track (70.579mm,113.522mm)(72.317mm,113.522mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-68(72.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad CN1-68(72.948mm,106.191mm) on Top Layer And Track (70.829mm,106.41mm)(72.567mm,106.41mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-69(73.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-7(57.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-70(73.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-71(73.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-72(73.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-73(74.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-74(74.448mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-74(74.448mm,106.191mm) on Top Layer And Track (74.829mm,106.41mm)(76.37mm,106.41mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-75(74.698mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad CN1-76(55.098mm,112.966mm) on Top Layer And Region (0 hole(s)) Top Overlay [Top Overlay] to [Top Solder] clearance [0.225mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-76(55.098mm,112.966mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN1-76(55.098mm,112.966mm) on Top Layer And Track (54.526mm,106.41mm)(54.526mm,111.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-77(75.798mm,112.966mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.106mm < 0.254mm) Between Pad CN1-77(75.798mm,112.966mm) on Top Layer And Track (76.37mm,108.831mm)(76.37mm,111.36mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.106mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-8(57.948mm,106.191mm) on Top Layer And Track (54.458mm,106.16mm)(76.458mm,106.16mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN1-9(58.198mm,113.741mm) on Top Layer And Track (51.206mm,112.954mm)(80.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(49.022mm,68.605mm) on Top Layer And Track (48.257mm,67.097mm)(48.257mm,68.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-1(49.022mm,68.605mm) on Top Layer And Track (48.257mm,69.187mm)(48.257mm,69.274mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(49.022mm,69.855mm) on Top Layer And Track (48.257mm,69.187mm)(48.257mm,69.274mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN5-2(49.022mm,69.855mm) on Top Layer And Track (48.257mm,70.436mm)(48.257mm,71.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad CN5-3(45.933mm,65.763mm) on Top Layer And Track (44.557mm,67.097mm)(48.257mm,67.097mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.007mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad CN5-3(45.933mm,65.763mm) on Top Layer And Track (44.557mm,67.107mm)(44.557mm,71.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.018mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.003mm < 0.254mm) Between Pad CN5-4(45.932mm,72.705mm) on Top Layer And Track (44.557mm,67.107mm)(44.557mm,71.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.003mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.003mm < 0.254mm) Between Pad CN5-4(45.932mm,72.705mm) on Top Layer And Track (44.557mm,71.375mm)(48.257mm,71.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.003mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-1(50.537mm,92.748mm) on Top Layer And Track (49.386mm,93.479mm)(49.386mm,95.225mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN7-1(50.537mm,92.748mm) on Top Layer And Track (51.206mm,73.954mm)(51.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.119mm < 0.254mm) Between Pad CN7-2(50.537mm,90.748mm) on Top Layer And Track (49.38mm,88.256mm)(49.38mm,90.001mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.119mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN7-2(50.537mm,90.748mm) on Top Layer And Track (51.206mm,73.954mm)(51.206mm,112.954mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-3(45.187mm,88.397mm) on Top Layer And Track (43.417mm,89.368mm)(43.417mm,94.127mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.098mm < 0.254mm) Between Pad CN7-3(45.187mm,88.397mm) on Top Layer And Track (47.112mm,87.748mm)(51.031mm,87.748mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.098mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-4(45.187mm,95.098mm) on Top Layer And Track (43.417mm,89.368mm)(43.417mm,94.127mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN7-4(45.187mm,95.098mm) on Top Layer And Track (47.118mm,95.733mm)(51.037mm,95.733mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad CN8-1(48.59mm,82.586mm) on Top Layer And Track (48.761mm,83.071mm)(48.761mm,85.611mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-4(48.59mm,78.836mm) on Top Layer And Track (48.814mm,75.811mm)(48.814mm,78.355mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-5(45.84mm,75.811mm) on Top Layer And Track (43.3mm,75.811mm)(44.109mm,75.811mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad CN8-5(45.84mm,75.811mm) on Top Layer And Track (47.571mm,75.811mm)(48.814mm,75.811mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad CN8-6(45.7mm,85.561mm) on Top Layer And Track (43.3mm,85.611mm)(44.109mm,85.611mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.244mm < 0.254mm) Between Pad CN8-6(45.7mm,85.561mm) on Top Layer And Track (47.571mm,85.611mm)(48.761mm,85.611mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.244mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-1(80.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-1(80.706mm,117.513mm) on Top Layer And Track (81.156mm,117.513mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-1(80.706mm,117.513mm) on Top Layer And Track (81.156mm,117.513mm)(83.823mm,117.513mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-10(76.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-11(75.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-12(75.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-13(74.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-14(74.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-15(73.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-16(73.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-17(72.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-18(72.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-19(71.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-2(80.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-20(71.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-21(70.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-22(70.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-23(69.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-24(69.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-25(68.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-26(68.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-27(67.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-28(67.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-29(66.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-3(79.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-30(66.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-31(65.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-32(65.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-33(64.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-34(64.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-35(63.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-36(63.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-37(62.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-38(62.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-39(61.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-4(79.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-40(61.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-41(60.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-42(60.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-43(59.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-44(59.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-45(58.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-46(58.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-47(57.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-48(57.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-49(56.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-5(78.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-50(56.206mm,117.513mm) on Top Layer And Track (53.089mm,117.513mm)(55.756mm,117.513mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad FPC2-50(56.206mm,117.513mm) on Top Layer And Track (55.756mm,117.513mm)(55.756mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-50(56.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad FPC2-51(54.356mm,119.888mm) on Top Layer And Track (53.089mm,117.513mm)(53.089mm,122.593mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad FPC2-52(82.556mm,119.888mm) on Top Layer And Track (83.823mm,117.513mm)(83.823mm,122.593mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-6(78.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-7(77.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-8(77.206mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.137mm < 0.254mm) Between Pad FPC2-9(76.706mm,117.513mm) on Top Layer And Track (55.756mm,118.402mm)(81.156mm,118.402mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.137mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-1(48.235mm,107.128mm) on Top Layer And Track (48.309mm,106.359mm)(48.309mm,106.647mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-1(48.235mm,107.128mm) on Top Layer And Track (48.309mm,107.609mm)(48.309mm,110.353mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-2(48.235mm,105.878mm) on Top Layer And Track (48.309mm,105.109mm)(48.309mm,105.397mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-2(48.235mm,105.878mm) on Top Layer And Track (48.309mm,106.359mm)(48.309mm,106.647mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-3(48.235mm,104.628mm) on Top Layer And Track (48.309mm,103.859mm)(48.309mm,104.147mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-3(48.235mm,104.628mm) on Top Layer And Track (48.309mm,105.109mm)(48.309mm,105.397mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-4(48.235mm,103.378mm) on Top Layer And Track (48.309mm,102.609mm)(48.309mm,102.897mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-4(48.235mm,103.378mm) on Top Layer And Track (48.309mm,103.859mm)(48.309mm,104.147mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-5(48.235mm,102.128mm) on Top Layer And Track (48.309mm,101.359mm)(48.309mm,101.647mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-5(48.235mm,102.128mm) on Top Layer And Track (48.309mm,102.609mm)(48.309mm,102.897mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-6(48.235mm,100.878mm) on Top Layer And Track (48.309mm,101.359mm)(48.309mm,101.647mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-6(48.235mm,100.878mm) on Top Layer And Track (48.309mm,97.628mm)(48.309mm,100.397mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-7(45.335mm,98.328mm) on Top Layer And Track (47.066mm,97.628mm)(48.309mm,97.628mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.183mm < 0.254mm) Between Pad P?-8(45.335mm,109.678mm) on Top Layer And Track (43.065mm,110.378mm)(43.525mm,110.378mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.183mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P?-8(45.335mm,109.678mm) on Top Layer And Track (47.066mm,110.378mm)(48.309mm,110.378mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(45.39mm,113.055mm) on Multi-Layer And Text "P?" (43.188mm,111.599mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Rule Violations :173
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
Violation between Silk To Silk Clearance Constraint: (0.181mm < 0.254mm) Between Text "-" (47.041mm,112.852mm) on Top Overlay And Track (46.66mm,111.785mm)(46.66mm,116.865mm) on Top Overlay Silk Text to Silk Clearance [0.181mm]
Violation between Silk To Silk Clearance Constraint: (0.156mm < 0.254mm) Between Text "+" (47.015mm,115.468mm) on Top Overlay And Track (46.66mm,111.785mm)(46.66mm,116.865mm) on Top Overlay Silk Text to Silk Clearance [0.156mm]
Violation between Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "CN7" (52.68mm,93.294mm) on Top Overlay And Track (54.458mm,64.16mm)(54.458mm,106.16mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "CN8" (50.343mm,82.733mm) on Top Overlay And Track (51.206mm,73.954mm)(51.206mm,112.954mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P?" (43.188mm,111.599mm) on Top Overlay And Track (44.12mm,111.785mm)(44.12mm,116.865mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P?" (43.188mm,111.599mm) on Top Overlay And Track (44.12mm,111.785mm)(46.66mm,111.785mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Rule Violations :6
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 187
Waived Violations : 0
Time Elapsed : 00:00:02
Reference in New Issue View Git Blame Copy Permalink