22.7.14
This commit is contained in:
BIN
SIF LIGHT/主板/1.25T-6P.PcbLib
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SIF LIGHT/主板/1.25T-6P.PcbLib
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SIF LIGHT/主板/1.25t-3p.PcbLib
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SIF LIGHT/主板/1.25t-3p.PcbLib
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SIF LIGHT/主板/PCB_Project2.PrjPCB
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SIF LIGHT/主板/PCB_Project2.PrjPCB
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SIF LIGHT/主板/PCB_Project2.PrjPCBStructure
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1
SIF LIGHT/主板/PCB_Project2.PrjPCBStructure
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Record=TopLevelDocument|FileName=SIF Light_SCH 20220112_2022-07-06.schdoc
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Change Component DesignItemId : Designator=C2 Old DesignItemId= New DesignItemId=0.1uF
|
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Change Component DesignItemId : Designator=C1 Old DesignItemId= New DesignItemId=1uF
|
||||
Change Component DesignItemId : Designator=U1 Old DesignItemId= New DesignItemId=2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
Change Component DesignItemId : Designator=R1 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R2 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R3 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R4 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=C3 Old DesignItemId= New DesignItemId=10uF
|
||||
Change Component DesignItemId : Designator=U5 Old DesignItemId= New DesignItemId=ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP
|
||||
Change Component DesignItemId : Designator=BAT1 Old DesignItemId= New DesignItemId=CR1220-2ZX
|
||||
Change Component DesignItemId : Designator=U4 Old DesignItemId= New DesignItemId=DS3231S
|
||||
Change Component DesignItemId : Designator=J1 Old DesignItemId= New DesignItemId=PH2.0W-1X4P
|
||||
Change Component DesignItemId : Designator=J2 Old DesignItemId= New DesignItemId=<3D><>Դ
|
||||
Change Component DesignItemId : Designator=J3 Old DesignItemId= New DesignItemId=<3D><>Դ
|
||||
Change Component DesignItemId : Designator=U2 Old DesignItemId= New DesignItemId=<3D><>ѹģ<D1B9><C4A3>
|
||||
Change Component DesignItemId : Designator=U3 Old DesignItemId= New DesignItemId=<3D><>ѹģ<D1B9><C4A3>
|
||||
Change component parameters: Designator = "U5"; Footprint = "ARDUINO-NANO-3.0#ISP"; UniqueID = "\ggea8e2f660ede1f0ef"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "sourceId"; Value = "MHTVTfAWi"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "M"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "timeStamp"; Value = "1463648055"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "J1"; Footprint = "PH2.0W-1X4P<34><50>װ"; UniqueID = "\gge02c95373f3317acc"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "HeZo"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "43650-0615"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C239442"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "<22><><EFBFBD>ݺ<EFBFBD><EFBFBD><D7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0W-1X4P"; VariantName = "[No Variations]"
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||||
Change component parameters: Designator = "J2"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge7a2095f9640df2a7"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "J3"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge24a1f388fafc13fc"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
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||||
Change component parameters: Designator = "R1"; Footprint = "R0603"; UniqueID = "\gge07bdca5a3aea9139"
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||||
Change component parameters. Clean all parameters for all variants
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R2"; Footprint = "R0603"; UniqueID = "\gge4ef602786d337833"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R3"; Footprint = "R0603"; UniqueID = "\gge195776cbb43ef2a0"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R4"; Footprint = "R0603"; UniqueID = "\gge8d4ca9ec2c2f1680"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "BAT1"; Footprint = "BAT-SMD_CR1220-2ZX"; UniqueID = "\gge8f29627181d88637"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "Q&J"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "CR1220-2ZX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C969906"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "B"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "CR1220-2ZX"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U4"; Footprint = "SOIC-16_L10.3-W7.5-P1.27-LS10.3-BL"; UniqueID = "\ggeae4eb166f739c636"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "MAXIM(<28><><EFBFBD><EFBFBD>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "DS3231S#T&R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C2651514"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "DS3231S#T&R"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U1"; Footprint = "2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>(˫H<CBAB>Ų<EFBFBD><C5B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)"; UniqueID = "\gge950fff3d33dc0e42"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "nidewenyin"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>(˫H<CBAB>Ų<EFBFBD><C5B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) COPY"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U2"; Footprint = "<22><>ѹģ<D1B9><C4A3>"; UniqueID = "\ggee20cb5c0ba300364"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "<22><>ѹģ<D1B9><C4A3>"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U3"; Footprint = "<22><>ѹģ<D1B9><C4A3>"; UniqueID = "\ggee77114038a0ead5f"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "<22><>ѹģ<D1B9><C4A3>"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C1"; Footprint = "C0603"; UniqueID = "\gge66964c34a4fec96d"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C2"; Footprint = "C0603"; UniqueID = "\ggeffcf16b24939ebf5"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C3"; Footprint = "C0603"; UniqueID = "\gge2a8eca0813df4c7e"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R5(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R6(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=R5-2
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=R6-2
|
||||
Change Net Name : Old Net Name=R1_1 New Net Name=NetR1_1
|
||||
Change Net Name : Old Net Name=R2_1 New Net Name=NetR2_1
|
||||
Change Net Name : Old Net Name=U4_14 New Net Name=NetBAT1_1
|
||||
Added Net: Name=GND
|
||||
Added Pin To Net: NetName=NetPt1_2 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetPt1_2 Pin=U5-J1.11
|
||||
Added Net: Name=NetPt1_2
|
||||
Added Pin To Net: NetName=NetPt2_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetPt2_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetPt2_2
|
||||
Added Class: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,3 @@
|
||||
Change Component Footprint: Designator=U2 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Change Component Footprint: Designator=U3 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,21 @@
|
||||
Change Component Footprint: Designator=U2 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Change Component Footprint: Designator=U3 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Added Component: Designator=P?(1.25T-6P)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=P?-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P?-3
|
||||
Added Pin To Net: NetName=GND Pin=P?-4
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P?-6
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=P?-2
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetP?_2
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=P?-5
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=U5-J1.11
|
||||
Added Net: Name=NetP?_5
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P? Header 6
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,3 @@
|
||||
Removed Pin From Net: NetName=GND Pin=P?-1
|
||||
Added Pin To Net: NetName=DGND Pin=P?-1
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,2 @@
|
||||
Added Pin To Net: NetName=DGND Pin=P?-4
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,30 @@
|
||||
Removed Pin From Net: NetName=DGND Pin=P?-1
|
||||
Removed Pin From Net: NetName=VCC3.3 Pin=P?-3
|
||||
Removed Pin From Net: NetName=DGND Pin=P?-4
|
||||
Removed Pin From Net: NetName=VCC3.3 Pin=P?-6
|
||||
Removed Member From Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=P?
|
||||
Added Component: Designator=P1(1.25t-3p)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=P2(1.25t-3p)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=DGND Pin=P1-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P1-3
|
||||
Added Pin To Net: NetName=DGND Pin=P2-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P2-3
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=P1-2
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=U5-J1.11
|
||||
Added Net: Name=NetP1_2
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=P2-2
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetP2_2
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P1 Header 3
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P2 Header 3
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,4 @@
|
||||
Change Component Footprint: Designator=P1 Old Footprint=1.25t-3p New Footprint=ds18b20
|
||||
Change Component Comment : Designator=P1 Old Comment=Header 3 New Comment=inner
|
||||
Change Component Comment : Designator=P2 Old Comment=Header 3 New Comment=outside'
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,210 @@
|
||||
Protel Design System Design Rule Check
|
||||
PCB File : C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc
|
||||
Date : 2022/7/7
|
||||
Time : 16:14:59
|
||||
|
||||
Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Un-Routed Net Constraint ( (All) )
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Rule Violations :4
|
||||
|
||||
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Rule Violations :130
|
||||
|
||||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||||
Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V<35><56><EFBFBD><EFBFBD>" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V<39><56><EFBFBD><EFBFBD>" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]
|
||||
Rule Violations :28
|
||||
|
||||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
|
||||
Violations Detected : 162
|
||||
Waived Violations : 0
|
||||
Time Elapsed : 00:00:01
|
||||
@ -0,0 +1,822 @@
|
||||
<html>
|
||||
<head>
|
||||
<META http-equiv="Content-Type" content="text/html">
|
||||
<style type="text/css">
|
||||
h1, h2, h3, h4, h5, h6 {
|
||||
font-family : segoe ui;
|
||||
color : black;
|
||||
background-color : #EDE7D9;
|
||||
padding: 0.3em;
|
||||
}
|
||||
|
||||
h1 {
|
||||
font-size: 1.2em;
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
|
||||
td, th {
|
||||
padding: 0.5em;
|
||||
text-align : left;
|
||||
width: 10em;
|
||||
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|
||||
th {
|
||||
background-color : #EEEEEE;
|
||||
|
||||
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|
||||
th.column1, td.column1 {
|
||||
text-align: left;
|
||||
width : auto;
|
||||
}
|
||||
table {
|
||||
width : 100%;
|
||||
font-size: 0.9em;
|
||||
}
|
||||
|
||||
.DRC_summary_header {
|
||||
padding-bottom : 0.1em;
|
||||
border : 0px solid black;
|
||||
width: 100%;
|
||||
align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1,
|
||||
.DRC_summary_header_col2,
|
||||
.DRC_summary_header_col3 {
|
||||
color : black;
|
||||
font-size:100%;
|
||||
padding : 0em;
|
||||
padding-top : 0.2em;
|
||||
padding-bottom 0.2em;
|
||||
border : 0px solid black;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1 {
|
||||
font-weight: bold;
|
||||
width: 8em;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col2 {
|
||||
width: 0.1em;
|
||||
|
||||
}
|
||||
|
||||
.DRC_summary_header_col3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.header_holder {
|
||||
Width = 100%;
|
||||
border = 0px solid green;
|
||||
padding = 0;
|
||||
}
|
||||
|
||||
|
||||
.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3
|
||||
{
|
||||
left : 0;
|
||||
top : 0;
|
||||
padding: 0em;
|
||||
padding-top : 0.1em;
|
||||
border : 0px solid black;
|
||||
width : 100%;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.front_matter_column1 {
|
||||
width : 8em;
|
||||
font-weight: bold;
|
||||
}
|
||||
|
||||
.front_matter_column2 {
|
||||
width: 0.1em;
|
||||
}
|
||||
|
||||
.front_matter_column3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.total_column1, .total_column {
|
||||
font-weight : bold;
|
||||
}
|
||||
.total_column1 {
|
||||
text-align : left;
|
||||
}
|
||||
.warning, .error {
|
||||
color : red;
|
||||
font-weight : bold;
|
||||
}
|
||||
tr.onmouseout_odd {
|
||||
background-color : #white;
|
||||
}
|
||||
tr.onmouseout_even {
|
||||
background-color : #FAFAFA;
|
||||
}
|
||||
tr.onmouseover_odd, tr.onmouseover_even {
|
||||
background-color : #EEEEEE;
|
||||
}
|
||||
a:link, a:visited, .q a:link,.q a:active,.q {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.callback, a:visited.callback {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.customize, a:visited.customize {
|
||||
color: #C0C0C0;
|
||||
position: absolute;
|
||||
right: 10px;
|
||||
}
|
||||
p.contents_level1 {
|
||||
font-weight : bold;
|
||||
font-size : 110%;
|
||||
margin : 0.5em;
|
||||
}
|
||||
p.contents_level2 {
|
||||
position : relative;
|
||||
left : 20px;
|
||||
margin : 0.5em;
|
||||
}
|
||||
</style><script type="text/javascript">
|
||||
function coordToMils(coord) {
|
||||
var number = coord / 10000;
|
||||
|
||||
if (number != number.toFixed(3))
|
||||
number = number.toFixed(3);
|
||||
|
||||
return number + 'mil'
|
||||
}
|
||||
|
||||
function coordToMM(coord) {
|
||||
var number = 0.0254 * coord / 10000;
|
||||
|
||||
if (number != number.toFixed(4))
|
||||
number = number.toFixed(4);
|
||||
|
||||
return number + 'mm'
|
||||
}
|
||||
|
||||
function convertCoord(coordNode, units) {
|
||||
for (var i = 0; i < coordNode.childNodes.length; i++) {
|
||||
coordNode.removeChild(coordNode.childNodes[i]);
|
||||
}
|
||||
|
||||
var coord = coordNode.getAttribute('value');
|
||||
if (coord != null) {
|
||||
if (units == 'mm') {
|
||||
textNode = document.createTextNode(coordToMM(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
} else if (units == 'mil') {
|
||||
textNode = document.createTextNode(coordToMils(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
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|
||||
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|
||||
}
|
||||
|
||||
function convertUnits(unitNode, units) {
|
||||
for (var i = 0; i < unitNode.childNodes.length; i++) {
|
||||
unitNode.removeChild(unitNode.childNodes[i]);
|
||||
}
|
||||
|
||||
textNode = document.createTextNode(units);
|
||||
unitNode.appendChild(textNode);
|
||||
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|
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|
||||
function changeUnits(radio_input, units) {
|
||||
if (radio_input.checked) {
|
||||
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||||
var elements = document.getElementsByName('coordinate');
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if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
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convertCoord(elements[i], units);
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||||
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|
||||
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|
||||
|
||||
var elements = document.getElementsByName('units');
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||||
if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
||||
convertUnits(elements[i], units);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
</script><title>Design Rule Verification Report</title>
|
||||
</head>
|
||||
<body onload=""><img ALT="Altium" src="
|
||||
file://C:\Users\Public\Documents\Altium\AD18\Templates\AD_logo.png
|
||||
"><h1>Design Rule Verification Report</h1>
|
||||
<table class="header_holder">
|
||||
<td class="column1">
|
||||
<table class="front_matter">
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Date:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">2022/7/7</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">16:14:59</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Elapsed Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">00:00:01</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Filename:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3"><a href="file:///C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc" class="file"><acronym title="C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc">C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc</acronym></a></td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
<td class="column2">
|
||||
<table class="DRC_summary_header">
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Warnings:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3">0</td></tr>
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Rule Violations:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3" style="color : red">162</td></tr>
|
||||
</table>
|
||||
</td>
|
||||
</table><a name="IDVDXQFH4TVCI2I502KFEQSUBCSEVGAQQM2SPLNUJYJBGHYJTLUBCN"><h2>Summary</h2></a><table>
|
||||
<tr>
|
||||
<th class="column1">Warnings</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">0</td>
|
||||
</tr>
|
||||
</table><br><table>
|
||||
<tr>
|
||||
<th class="column1">Rule Violations</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID5C4YYG4SSDOVNSNPD22PMF51AGWOY5J3P2KKM4FIIV1PBHQ5J40">Clearance Constraint (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDADQFVNRZJ4PMCACHR4LVIQSG4KT3B4SGITD3RBOW4VXPXMBAKZME">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDFRNUAMVPBIY4ID45IJ130XNFUELVII2CG41MI2NX3540CBUH4DHB">Un-Routed Net Constraint ( (All) )</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDNZZ2HPHHNMKWEJ2O5FUMCJCYQILVEFHTFH4L5XOC5NXRU4PM3YPN">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID4US1TKWPHWYZBSU1XYSBWAELCCCMAYKLUVVYPROH0XQY2YWYWC2M">Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDHSI4EV51BH3NWA30WA0ITROJOV02J2XAOT53BIOF5L0IHFNDT1L">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDFETFPWDHNEM1KR5URX4KBMRQPEIDADCEYZGOHXDE3SFUX3TIH1UK">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</a></td>
|
||||
<td class="column2">4</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDCRSQPW05NXZ2OTMBTXRI3BWCJMWPAC5UMNHGC4HCPOG3ZDVAP2WL">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDCTVXQ4FCPZS2JGQB5URTW3LVCEDM0LEGHH0AQIKLJZ2F12IQ0DMO">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDTKLASX114WJ50VDNG2DLBME2OHPJMA3QPBUSBBKDTODSE4IJBHP">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</a></td>
|
||||
<td class="column2">130</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDMCJP3D02ZFQHPPYMOWNQXNMLCIUH2AH4P4UYLB0K1XM3UTEDRGD">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">28</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDN3NDKPZH1WMWGKA0PK5R4AB3FCS2ZQZ2OEA3ENNDI053AUBOUC4I">Net Antennae (Tolerance=0mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDOUR41COCMLC2MRBC3BRVXC2POC1KP0TNEHS1SUHN11WXEXMBUAG">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">162</td>
|
||||
</tr>
|
||||
</table><br><a name="IDFETFPWDHNEM1KR5URX4KBMRQPEIDADCEYZGOHXDE3SFUX3TIH1UK"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=2012.13mil|Location2.Y=2131.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=2012.13mil|Location2.Y=2131.49mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=1618.43mil|Location2.Y=1737.79mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=1618.43mil|Location2.Y=1737.79mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDTKLASX114WJ50VDNG2DLBME2OHPJMA3QPBUSBBKDTODSE4IJBHP"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.292mil|Location2.X=1675.542mil|Location1.Y=1793.066mil|Location2.Y=1806.385mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.292mil|Location2.X=1675.542mil|Location1.Y=1793.066mil|Location2.Y=1806.385mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.165mil|Location2.X=1675.415mil|Location1.Y=1882.867mil|Location2.Y=1894.117mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.165mil|Location2.X=1675.415mil|Location1.Y=1882.867mil|Location2.Y=1894.117mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.453mil|Location2.X=1715.703mil|Location1.Y=1795.145mil|Location2.Y=1808.512mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.453mil|Location2.X=1715.703mil|Location1.Y=1795.145mil|Location2.Y=1808.512mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.801mil|Location2.X=1716.051mil|Location1.Y=1882.935mil|Location2.Y=1894.185mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.801mil|Location2.X=1716.051mil|Location1.Y=1882.935mil|Location2.Y=1894.185mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2346.463mil|Location2.X=2357.713mil|Location1.Y=2294.688mil|Location2.Y=2305.938mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2346.463mil|Location2.X=2357.713mil|Location1.Y=2294.688mil|Location2.Y=2305.938mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2342.699mil|Location2.X=2353.949mil|Location1.Y=2456.47mil|Location2.Y=2467.72mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2342.699mil|Location2.X=2353.949mil|Location1.Y=2456.47mil|Location2.Y=2467.72mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2181.395mil|Location2.X=2192.645mil|Location1.Y=1655.076mil|Location2.Y=1666.326mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2181.395mil|Location2.X=2192.645mil|Location1.Y=1655.076mil|Location2.Y=1666.326mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.949mil|Location2.X=2360.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.949mil|Location2.X=2360.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.297mil|Location2.X=2360.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.297mil|Location2.X=2360.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.585mil|Location2.X=2400.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.585mil|Location2.X=2400.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.458mil|Location2.X=2400.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.458mil|Location2.X=2400.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.949mil|Location2.X=2455.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.949mil|Location2.X=2455.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.297mil|Location2.X=2455.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.297mil|Location2.X=2455.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.585mil|Location2.X=2495.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.585mil|Location2.X=2495.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.458mil|Location2.X=2495.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.458mil|Location2.X=2495.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2292.229mil|Location2.Y=2303.479mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2292.229mil|Location2.Y=2303.479mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2455.733mil|Location2.Y=2466.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2455.733mil|Location2.Y=2466.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.933mil|Location2.X=2455.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.933mil|Location2.X=2455.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2481.444mil|Location2.X=2492.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2481.444mil|Location2.X=2492.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.595mil|Location2.X=2495.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.595mil|Location2.X=2495.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.041mil|Location2.X=2455.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.041mil|Location2.X=2455.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.636mil|Location2.X=2459.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.636mil|Location2.X=2459.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.71mil|Location2.X=2495.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.71mil|Location2.X=2495.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.933mil|Location2.X=2360.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.933mil|Location2.X=2360.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2386.444mil|Location2.X=2397.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2386.444mil|Location2.X=2397.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.595mil|Location2.X=2400.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.595mil|Location2.X=2400.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.041mil|Location2.X=2360.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.041mil|Location2.X=2360.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.71mil|Location2.X=2400.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.71mil|Location2.X=2400.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.155mil|Location2.X=1675.405mil|Location1.Y=1882.636mil|Location2.Y=1893.886mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.155mil|Location2.X=1675.405mil|Location1.Y=1882.636mil|Location2.Y=1893.886mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1668.849mil|Location2.X=1680.099mil|Location1.Y=1886.193mil|Location2.Y=1897.443mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1668.849mil|Location2.X=1680.099mil|Location1.Y=1886.193mil|Location2.Y=1897.443mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.817mil|Location2.X=1716.067mil|Location1.Y=1851.182mil|Location2.Y=1862.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.817mil|Location2.X=1716.067mil|Location1.Y=1851.182mil|Location2.Y=1862.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.04mil|Location2.X=1675.29mil|Location1.Y=1827.568mil|Location2.Y=1838.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.04mil|Location2.X=1675.29mil|Location1.Y=1827.568mil|Location2.Y=1838.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1701.529mil|Location2.X=1712.779mil|Location1.Y=1792.824mil|Location2.Y=1804.074mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1701.529mil|Location2.X=1712.779mil|Location1.Y=1792.824mil|Location2.Y=1804.074mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.702mil|Location2.X=1715.952mil|Location1.Y=1796.846mil|Location2.Y=1808.096mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.702mil|Location2.X=1715.952mil|Location1.Y=1796.846mil|Location2.Y=1808.096mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=4084.153mil|Location2.Y=4095.403mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=4084.153mil|Location2.Y=4095.403mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=4032.066mil|Location2.Y=4043.316mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=4032.066mil|Location2.Y=4043.316mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=3624.591mil|Location2.Y=3635.841mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=3624.591mil|Location2.Y=3635.841mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=3676.677mil|Location2.Y=3687.927mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=3676.677mil|Location2.Y=3687.927mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3949.37mil|Location2.Y=3960.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3949.37mil|Location2.Y=3960.62mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3911.863mil|Location2.Y=3923.113mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3911.863mil|Location2.Y=3923.113mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3724.375mil|Location2.Y=3735.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3724.375mil|Location2.Y=3735.625mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=3136.92mil|Location2.Y=3148.17mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=3136.92mil|Location2.Y=3148.17mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3180.472mil|Location2.Y=3191.722mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3180.472mil|Location2.Y=3191.722mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=3058.18mil|Location2.Y=3069.43mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=3058.18mil|Location2.Y=3069.43mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3101.733mil|Location2.Y=3112.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3101.733mil|Location2.Y=3112.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3526.873mil|Location2.X=3538.123mil|Location1.Y=3322.567mil|Location2.Y=3333.817mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3526.873mil|Location2.X=3538.123mil|Location1.Y=3322.567mil|Location2.Y=3333.817mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=2641.92mil|Location2.Y=2653.17mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=2641.92mil|Location2.Y=2653.17mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2685.472mil|Location2.Y=2696.722mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2685.472mil|Location2.Y=2696.722mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=2563.18mil|Location2.Y=2574.43mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=2563.18mil|Location2.Y=2574.43mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2606.733mil|Location2.Y=2617.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2606.733mil|Location2.Y=2617.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3521.856mil|Location2.X=3533.106mil|Location1.Y=2827.805mil|Location2.Y=2839.055mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3521.856mil|Location2.X=3533.106mil|Location1.Y=2827.805mil|Location2.Y=2839.055mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2468.381mil|Location2.X=2476.047mil|Location1.Y=2494.599mil|Location2.Y=2502.266mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2468.381mil|Location2.X=2476.047mil|Location1.Y=2494.599mil|Location2.Y=2502.266mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2473.262mil|Location2.X=2480.928mil|Location1.Y=2648.029mil|Location2.Y=2655.695mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2473.262mil|Location2.X=2480.928mil|Location1.Y=2648.029mil|Location2.Y=2655.695mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2471.993mil|Location2.X=2479.659mil|Location1.Y=2707.864mil|Location2.Y=2715.53mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2471.993mil|Location2.X=2479.659mil|Location1.Y=2707.864mil|Location2.Y=2715.53mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2084.311mil|Location2.Y=2091.978mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2084.311mil|Location2.Y=2091.978mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2035.098mil|Location2.Y=2042.765mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2035.098mil|Location2.Y=2042.765mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=1985.885mil|Location2.Y=1993.552mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=1985.885mil|Location2.Y=1993.552mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3500.743mil|Location2.X=3511.993mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3500.743mil|Location2.X=3511.993mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.375mil|Location2.X=3635.625mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.375mil|Location2.X=3635.625mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.524mil|Location2.X=3639.73mil|Location1.Y=2155.356mil|Location2.Y=2166.606mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.524mil|Location2.X=3639.73mil|Location1.Y=2155.356mil|Location2.Y=2166.606mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.463mil|Location2.X=3639.791mil|Location1.Y=2155.174mil|Location2.Y=2166.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.463mil|Location2.X=3639.791mil|Location1.Y=2155.174mil|Location2.Y=2166.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2290.844mil|Location2.X=2302.094mil|Location1.Y=1661.383mil|Location2.Y=1672.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2290.844mil|Location2.X=2302.094mil|Location1.Y=1661.383mil|Location2.Y=1672.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2324.57mil|Location2.X=2338.123mil|Location1.Y=1624.29mil|Location2.Y=1635.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2324.57mil|Location2.X=2338.123mil|Location1.Y=1624.29mil|Location2.Y=1635.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2293.845mil|Location2.X=2305.095mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2293.845mil|Location2.X=2305.095mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1624.367mil|Location2.Y=1635.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1624.367mil|Location2.Y=1635.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2387.906mil|Location2.X=2399.156mil|Location1.Y=1627.367mil|Location2.Y=1638.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2387.906mil|Location2.X=2399.156mil|Location1.Y=1627.367mil|Location2.Y=1638.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.367mil|Location2.X=2280.617mil|Location1.Y=1794.906mil|Location2.Y=1806.156mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.367mil|Location2.X=2280.617mil|Location1.Y=1794.906mil|Location2.Y=1806.156mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2272.367mil|Location2.X=2283.617mil|Location1.Y=1797.906mil|Location2.Y=1809.156mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2272.367mil|Location2.X=2283.617mil|Location1.Y=1797.906mil|Location2.Y=1809.156mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1766.155mil|Location2.Y=1777.405mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1766.155mil|Location2.Y=1777.405mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.29mil|Location2.X=2280.54mil|Location1.Y=1732.297mil|Location2.Y=1745.82mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.29mil|Location2.X=2280.54mil|Location1.Y=1732.297mil|Location2.Y=1745.82mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2306.383mil|Location2.X=2317.633mil|Location1.Y=1700.844mil|Location2.Y=1712.094mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2306.383mil|Location2.X=2317.633mil|Location1.Y=1700.844mil|Location2.Y=1712.094mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1703.844mil|Location2.Y=1715.094mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1703.844mil|Location2.Y=1715.094mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1634.367mil|Location2.Y=1645.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1634.367mil|Location2.Y=1645.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1637.367mil|Location2.Y=1648.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1637.367mil|Location2.Y=1648.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1671.383mil|Location2.Y=1682.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1671.383mil|Location2.Y=1682.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1634.29mil|Location2.Y=1645.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1634.29mil|Location2.Y=1645.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1704.367mil|Location2.Y=1715.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1704.367mil|Location2.Y=1715.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1707.367mil|Location2.Y=1718.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1707.367mil|Location2.Y=1718.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.598mil|Location2.X=1621.848mil|Location1.Y=1716.868mil|Location2.Y=1728.118mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.598mil|Location2.X=1621.848mil|Location1.Y=1716.868mil|Location2.Y=1728.118mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1741.383mil|Location2.Y=1752.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1741.383mil|Location2.Y=1752.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1704.29mil|Location2.Y=1715.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1704.29mil|Location2.Y=1715.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3440.588mil|Location2.X=3454.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3440.588mil|Location2.X=3454.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3390.753mil|Location2.X=3402.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3390.753mil|Location2.X=3402.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3360.588mil|Location2.X=3374.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3360.588mil|Location2.X=3374.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3310.753mil|Location2.X=3322.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3310.753mil|Location2.X=3322.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2712.014mil|Location2.X=2723.264mil|Location1.Y=3328.775mil|Location2.Y=3340.025mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2712.014mil|Location2.X=2723.264mil|Location1.Y=3328.775mil|Location2.Y=3340.025mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3264.907mil|Location2.Y=3272.574mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3264.907mil|Location2.Y=3272.574mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3363.332mil|Location2.Y=3370.999mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3363.332mil|Location2.Y=3370.999mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3461.757mil|Location2.Y=3469.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3461.757mil|Location2.Y=3469.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3560.182mil|Location2.Y=3567.849mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3560.182mil|Location2.Y=3567.849mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2794.907mil|Location2.Y=2802.574mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2794.907mil|Location2.Y=2802.574mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2893.332mil|Location2.Y=2900.999mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2893.332mil|Location2.Y=2900.999mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2991.757mil|Location2.Y=2999.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2991.757mil|Location2.Y=2999.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3090.182mil|Location2.Y=3097.849mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3090.182mil|Location2.Y=3097.849mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1677.836mil|Location2.Y=1689.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1677.836mil|Location2.Y=1689.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1961.382mil|Location2.Y=1972.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1961.382mil|Location2.Y=1972.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1911.382mil|Location2.Y=1922.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1911.382mil|Location2.Y=1922.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1861.382mil|Location2.Y=1872.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1861.382mil|Location2.Y=1872.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1811.382mil|Location2.Y=1822.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1811.382mil|Location2.Y=1822.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1761.382mil|Location2.Y=1772.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1761.382mil|Location2.Y=1772.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1711.382mil|Location2.Y=1722.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1711.382mil|Location2.Y=1722.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1661.382mil|Location2.Y=1672.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1661.382mil|Location2.Y=1672.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1727.836mil|Location2.Y=1739.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1727.836mil|Location2.Y=1739.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1777.836mil|Location2.Y=1789.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1777.836mil|Location2.Y=1789.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1827.836mil|Location2.Y=1839.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1827.836mil|Location2.Y=1839.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1877.836mil|Location2.Y=1889.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1877.836mil|Location2.Y=1889.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1927.836mil|Location2.Y=1939.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1927.836mil|Location2.Y=1939.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1977.836mil|Location2.Y=1989.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1977.836mil|Location2.Y=1989.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=2027.836mil|Location2.Y=2039.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=2027.836mil|Location2.Y=2039.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=2011.382mil|Location2.Y=2022.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=2011.382mil|Location2.Y=2022.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3168.618mil|Location2.Y=3179.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3168.618mil|Location2.Y=3179.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3230.132mil|Location2.Y=3241.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3230.132mil|Location2.Y=3241.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDMCJP3D02ZFQHPPYMOWNQXNMLCIUH2AH4P4UYLB0K1XM3UTEDRGD"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk to Silk (Clearance=0.254mm) (All),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.629mil|Location2.X=1660.879mil|Location1.Y=1802.5mil|Location2.Y=1813.995mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.629mil|Location2.X=1660.879mil|Location1.Y=1802.5mil|Location2.Y=1813.995mil|Absolute=True">Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1798.477mil|Location2.X=1809.727mil|Location1.Y=2269.68mil|Location2.Y=2283.081mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1798.477mil|Location2.X=1809.727mil|Location1.Y=2269.68mil|Location2.Y=2283.081mil|Absolute=True">Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.635mil|Location2.X=2364.885mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.635mil|Location2.X=2364.885mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2385.131mil|Location2.X=2396.381mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2385.131mil|Location2.X=2396.381mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.76mil|Location2.X=2460.01mil|Location1.Y=1810.088mil|Location2.Y=1821.338mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.76mil|Location2.X=2460.01mil|Location1.Y=1810.088mil|Location2.Y=1821.338mil|Absolute=True">Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.499mil|Location2.X=2491.749mil|Location1.Y=1809.76mil|Location2.Y=1821.01mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.499mil|Location2.X=2491.749mil|Location1.Y=1809.76mil|Location2.Y=1821.01mil|Absolute=True">Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2344.887mil|Location2.X=2356.137mil|Location1.Y=3116.992mil|Location2.Y=3128.242mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2344.887mil|Location2.X=2356.137mil|Location1.Y=3116.992mil|Location2.Y=3128.242mil|Absolute=True">Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V<35><56><EFBFBD><EFBFBD>" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2347.299mil|Location2.X=2358.549mil|Location1.Y=3586.623mil|Location2.Y=3597.873mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2347.299mil|Location2.X=2358.549mil|Location1.Y=3586.623mil|Location2.Y=3597.873mil|Absolute=True">Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V<39><56><EFBFBD><EFBFBD>" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.25mil|Location2.X=2491.5mil|Location1.Y=1809.763mil|Location2.Y=1821.013mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.25mil|Location2.X=2491.5mil|Location1.Y=1809.763mil|Location2.Y=1821.013mil|Absolute=True">Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2334.363mil|Location2.X=2345.613mil|Location1.Y=1856.863mil|Location2.Y=1868.113mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2334.363mil|Location2.X=2345.613mil|Location1.Y=1856.863mil|Location2.Y=1868.113mil|Absolute=True">Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.398mil|Location2.X=1660.648mil|Location1.Y=1806.873mil|Location2.Y=1818.123mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.398mil|Location2.X=1660.648mil|Location1.Y=1806.873mil|Location2.Y=1818.123mil|Absolute=True">Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.514mil|Location2.X=1660.764mil|Location1.Y=1866.853mil|Location2.Y=1878.103mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.514mil|Location2.X=1660.764mil|Location1.Y=1866.853mil|Location2.Y=1878.103mil|Absolute=True">Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2109.37mil|Location2.X=2120.62mil|Location1.Y=3926.868mil|Location2.Y=3938.118mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2109.37mil|Location2.X=2120.62mil|Location1.Y=3926.868mil|Location2.Y=3938.118mil|Absolute=True">Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1702.193mil|Location2.X=1713.443mil|Location1.Y=3829.352mil|Location2.Y=3840.602mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1702.193mil|Location2.X=1713.443mil|Location1.Y=3829.352mil|Location2.Y=3840.602mil|Absolute=True">Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2442.132mil|Location2.X=2449.799mil|Location1.Y=2820.234mil|Location2.Y=2827.9mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2442.132mil|Location2.X=2449.799mil|Location1.Y=2820.234mil|Location2.Y=2827.9mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1669.872mil|Location2.Y=1681.122mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1669.872mil|Location2.Y=1681.122mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1624.375mil|Location2.Y=1635.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1624.375mil|Location2.Y=1635.625mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2284.365mil|Location2.X=2295.615mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2284.365mil|Location2.X=2295.615mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2315.383mil|Location2.X=2326.633mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2315.383mil|Location2.X=2326.633mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1603.889mil|Location2.X=1611.556mil|Location1.Y=1663.655mil|Location2.Y=1671.321mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1603.889mil|Location2.X=1611.556mil|Location1.Y=1663.655mil|Location2.Y=1671.321mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1602.097mil|Location2.X=1613.347mil|Location1.Y=1630.12mil|Location2.Y=1642.498mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1602.097mil|Location2.X=1613.347mil|Location1.Y=1630.12mil|Location2.Y=1642.498mil|Absolute=True">Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1606.389mil|Location2.X=1614.056mil|Location1.Y=1718.659mil|Location2.Y=1726.326mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1606.389mil|Location2.X=1614.056mil|Location1.Y=1718.659mil|Location2.Y=1726.326mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.099mil|Location1.Y=1698.367mil|Location2.Y=1709.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.099mil|Location1.Y=1698.367mil|Location2.Y=1709.617mil|Absolute=True">Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.834mil|Location1.Y=1744.872mil|Location2.Y=1756.122mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.834mil|Location1.Y=1744.872mil|Location2.Y=1756.122mil|Absolute=True">Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1868.285mil|Location2.X=1875.951mil|Location1.Y=2046.164mil|Location2.Y=2053.831mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1868.285mil|Location2.X=1875.951mil|Location1.Y=2046.164mil|Location2.Y=2053.831mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1871.167mil|Location2.X=1878.833mil|Location1.Y=2051.923mil|Location2.Y=2059.589mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1871.167mil|Location2.X=1878.833mil|Location1.Y=2051.923mil|Location2.Y=2059.589mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2981.044mil|Location2.X=2992.294mil|Location1.Y=1855.375mil|Location2.Y=1866.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2981.044mil|Location2.X=2992.294mil|Location1.Y=1855.375mil|Location2.Y=1866.625mil|Absolute=True">Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br></body>
|
||||
</html>
|
||||
BIN
SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar
Normal file
BIN
SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar
Normal file
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BIN
SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc
Normal file
BIN
SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc
Normal file
Binary file not shown.
BIN
SIF LIGHT/主板/ds18b20.PcbLib
Normal file
BIN
SIF LIGHT/主板/ds18b20.PcbLib
Normal file
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BIN
SIF LIGHT/主板/电源模块.PcbLib
Normal file
BIN
SIF LIGHT/主板/电源模块.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/1.25t-3p.PcbLib
Normal file
BIN
SIF LIGHT/灯板/1.25t-3p.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib
Normal file
BIN
SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib
Normal file
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Binary file not shown.
@ -0,0 +1,175 @@
|
||||
<html>
|
||||
<head>
|
||||
<META http-equiv="Content-Type" content="text/html">
|
||||
<style type="text/css">
|
||||
h1, h2, h3, h4, h5, h6 {
|
||||
font-family : 'segoe-ui',arial,sans-serif;
|
||||
font-size:15pt;
|
||||
font-weight:normal;
|
||||
line-height:40px;
|
||||
color : #000;
|
||||
background-color : #dedede;
|
||||
padding: 0.3em;
|
||||
}
|
||||
body {
|
||||
font-family : verdana;
|
||||
background: #f1f1f1;
|
||||
font-size:13px;
|
||||
}
|
||||
td, th {
|
||||
padding: 0.5em;
|
||||
text-align : left;
|
||||
width: auto;
|
||||
border:1px solid #DEDEDE;
|
||||
}
|
||||
th {
|
||||
background-color : #DEDEDE;
|
||||
|
||||
}
|
||||
th.column1, td.column1 {
|
||||
text-align: left;
|
||||
width : 18%;
|
||||
}
|
||||
table {
|
||||
width : 100%;
|
||||
border-collapse: collapse;
|
||||
font-size:13px;
|
||||
}
|
||||
.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3 {
|
||||
padding-top : 0.1em;
|
||||
padding-bottom : 0.1em;
|
||||
border : 0px solid black;
|
||||
width : auto;
|
||||
vertical-align: top
|
||||
}
|
||||
.front_matter_column1 {
|
||||
text-align : right;
|
||||
}
|
||||
.total_column1, .total_column {
|
||||
font-weight : bold;
|
||||
}
|
||||
.total_column1 {
|
||||
text-align : right;
|
||||
}
|
||||
.front_matter_column2 {
|
||||
text-align : center;
|
||||
}
|
||||
.front_matter_column3 {
|
||||
text-align : left;
|
||||
}
|
||||
.warning, .error {
|
||||
color : red;
|
||||
font-weight : bold;
|
||||
}
|
||||
tr.onmouseout_odd {
|
||||
/*background-color : #EEEEE0 */
|
||||
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|
||||
tr.onmouseout_even {
|
||||
/*background-color : #F3F3E3 */
|
||||
}
|
||||
tr.onmouseover_odd, tr.onmouseover_even {
|
||||
background-color : #FFF;
|
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|
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a:link, a:visited, .q a:link,.q a:active,.q {
|
||||
color: #21489e;
|
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|
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a:link.callback, a:visited.callback {
|
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color: #008000
|
||||
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|
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a:link.customize, a:visited.customize {
|
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|
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right: 16px; top: 30px;
|
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font-family:'segoe ui',arial,tahoma,sans-serif;
|
||||
text-decoration:underline;
|
||||
font-size:11px;
|
||||
color:#0066cc;
|
||||
}
|
||||
p.contents_level1 {
|
||||
font-weight : bold;
|
||||
font-size : 110%;
|
||||
margin : 0.5em;
|
||||
}
|
||||
p.contents_level2 {
|
||||
position : relative;
|
||||
left : 20px;
|
||||
margin : 0.5em;
|
||||
}
|
||||
|
||||
HR{
|
||||
border-collapse:collapse;
|
||||
border:none;
|
||||
border-top:1px solid #dedede;
|
||||
}
|
||||
</style>
|
||||
|
||||
<style type="text/css" media="print">
|
||||
body{
|
||||
background:#fff;
|
||||
}
|
||||
|
||||
a:link.customize{
|
||||
display:none;
|
||||
}
|
||||
|
||||
table,th,td,hr{
|
||||
border-color:#999;
|
||||
background:#fff;
|
||||
}
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
<a href="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General" class="customize"><acronym title="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General">Reporting Options</acronym></a>
|
||||
<h1>File in Previous Format</h1>
|
||||
|
||||
<table class="front_matter">
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Date</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3">2022/7/13</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Time</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3">13:08:06</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Filename</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3"><a href="file://C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc" class="file"><acronym title="C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc">C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc</acronym></a></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
<br>
|
||||
|
||||
<table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="">Version</th>
|
||||
<th style="text-align : left" colspan="1" class="">Warning</th>
|
||||
</tr>
|
||||
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">6.3</td>
|
||||
<td class="column2"><b>CAUTION</b> - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Summer 09</td>
|
||||
<td class="column2"><b>CAUTION</b> - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Summer 09</td>
|
||||
<td class="column2"><b>CAUTION</b> - Existing testpoint rules and settings are used as fabrication testpoint information.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Release 12</td>
|
||||
<td class="column2"><b>CAUTION</b> - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Release 13</td>
|
||||
<td class="column2"><b>CAUTION</b> - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<br><hr>
|
||||
<p>This file was generated by <b>an earlier</b> version of the software</p>
|
||||
</body>
|
||||
</html>
|
||||
1124
SIF LIGHT/灯板/PCB_Project1.PrjPCB
Normal file
1124
SIF LIGHT/灯板/PCB_Project1.PrjPCB
Normal file
File diff suppressed because it is too large
Load Diff
1
SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure
Normal file
1
SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure
Normal file
@ -0,0 +1 @@
|
||||
Record=TopLevelDocument|FileName=SIF Light_SCH_<48>ư<EFBFBD> 20220224_2022-07-13.schdoc
|
||||
BIN
SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc
Normal file
BIN
SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/ds18b20.PcbLib
Normal file
BIN
SIF LIGHT/灯板/ds18b20.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/pin.PcbLib
Normal file
BIN
SIF LIGHT/灯板/pin.PcbLib
Normal file
Binary file not shown.
Reference in New Issue
Block a user