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fsa1/BODY/Design Rule Check - FSA_Body_PCB 微调20211217_2022-06-23.drc Normal file
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Protel Design System Design Rule Check
PCB File : C:\Users\hu123456\Desktop\fsa1\BODY\FSA_Body_PCB ΢<><CEA2>20211217_2022-06-23.pcbdoc
Date : 2022/6/23
Time : 17:51:24
Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Violation between Clearance Constraint: (0.061mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (62.155mm,54.268mm)(62.155mm,66.268mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-1(39.497mm,72.009mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-2(39.497mm,69.469mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-25(77.343mm,72.009mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-26(77.343mm,69.469mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-27(77.343mm,66.929mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-28(77.343mm,64.389mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-29(77.343mm,61.849mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-3(39.497mm,66.929mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-30(77.343mm,59.309mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-31(77.343mm,56.769mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-32(77.343mm,54.229mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-33(77.343mm,51.689mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-34(77.343mm,49.149mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-35(77.343mm,46.609mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.249mm < 0.254mm) Between Pad J1-36(77.343mm,44.069mm) on Multi-Layer And Track (78.481mm,38.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-4(39.497mm,64.389mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-48(76.167mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.16mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.481mm,38.354mm)(78.481mm,38.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-5(39.497mm,61.849mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-6(39.497mm,59.309mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-7(39.497mm,56.769mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-8(39.497mm,54.229mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (0.127mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.481mm,38.354mm)(38.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Violation between Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (38.481mm,78.354mm)(78.481mm,78.354mm) on Keep-Out Layer
Rule Violations :29
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.172mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Via (65.943mm,57.806mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.172mm]
Rule Violations :1
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-11(39.497mm,46.609mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-12(39.497mm,44.069mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-38(42.037mm,49.149mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad J1-49(40.767mm,40.419mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.148mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Arc (42.921mm,44.831mm) on Top Overlay And Pad U1-2(46.72mm,47.387mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,51.04mm)(48.016mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-1(48.491mm,53.34mm) on Top Layer And Track (48.016mm,54.821mm)(48.016mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,51.04mm)(55.616mm,51.859mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad C1-2(55.141mm,53.34mm) on Top Layer And Track (55.616mm,54.821mm)(55.616mm,55.64mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Text "IN1" (64.77mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (63.691mm,49.092mm)(65.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-1(66.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.24mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Text "IN2" (69.469mm,47.498mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.24mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (67.422mm,49.092mm)(67.96mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-2(68.691mm,47.652mm) on Top Layer And Track (69.422mm,49.092mm)(71.691mm,49.092mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,49.092mm)(71.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-3(71.755mm,51.664mm) on Top Layer And Track (71.691mm,53.645mm)(71.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,49.092mm)(63.691mm,49.682mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad DY-4(63.627mm,51.664mm) on Top Layer And Track (63.691mm,53.645mm)(63.691mm,54.492mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-1(69.693mm,56.231mm) on Top Layer And Track (70.174mm,55.984mm)(71.14mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-2(68.443mm,56.231mm) on Top Layer And Track (68.924mm,55.984mm)(69.211mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-3(67.193mm,56.231mm) on Top Layer And Track (67.674mm,55.984mm)(67.961mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.171mm < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Text "v" (65.815mm,55.105mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.171mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (65.174mm,55.984mm)(65.461mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad GPS-4(65.943mm,56.231mm) on Top Layer And Track (66.424mm,55.984mm)(66.711mm,55.984mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,55.984mm)(71.193mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-5(72.243mm,58.831mm) on Top Layer And Track (71.193mm,60.562mm)(71.193mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,55.984mm)(64.443mm,57.1mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad GPS-6(63.393mm,58.831mm) on Top Layer And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Text "G" (51.181mm,71.374mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.125mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-1(50.75mm,72.337mm) on Top Layer And Track (51.231mm,72.263mm)(53.975mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-2(49.5mm,72.337mm) on Top Layer And Track (49.981mm,72.263mm)(50.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-3(48.25mm,72.337mm) on Top Layer And Track (48.731mm,72.263mm)(49.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-4(47mm,72.337mm) on Top Layer And Track (47.481mm,72.263mm)(47.769mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-5(45.75mm,72.337mm) on Top Layer And Track (46.231mm,72.263mm)(46.519mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (41.25mm,72.263mm)(44.019mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-6(44.5mm,72.337mm) on Top Layer And Track (44.981mm,72.263mm)(45.269mm,72.263mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.07mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Text "HEADER" (40.767mm,73.533mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.07mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-7(41.95mm,75.237mm) on Top Layer And Track (41.25mm,72.263mm)(41.25mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,72.263mm)(54mm,73.506mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.183mm < 0.254mm) Between Pad HEADER-8(53.3mm,75.237mm) on Top Layer And Track (54mm,77.047mm)(54mm,77.507mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.183mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-10(39.497mm,49.149mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-11(39.497mm,46.609mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-12(39.497mm,44.069mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-37(42.037mm,51.688mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.135mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.135mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.084mm < 0.254mm) Between Pad J1-49(40.767mm,40.419mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.084mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,38.481mm)(38.73mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.17mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad J1-9(39.497mm,51.689mm) on Multi-Layer And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-1(68.189mm,39.798mm) on Top Layer And Track (68.76mm,40.766mm)(70.439mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (66.26mm,40.766mm)(66.368mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-2(66.939mm,39.798mm) on Top Layer And Track (67.51mm,40.766mm)(67.618mm,40.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,40.766mm)(64.689mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-3(64.189mm,42.498mm) on Top Layer And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,40.766mm)(70.439mm,41.067mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad LB-4(70.939mm,42.498mm) on Top Layer And Track (70.439mm,43.929mm)(70.439mm,44.167mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.093mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (56.484mm,70.581mm)(56.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.093mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad MOTOR-(57.284mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.173mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.029mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.189mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (58.184mm,78.181mm)(66.784mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.189mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad MOTOR-(67.684mm,76.281mm) on Bottom Layer And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.073mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,48.768mm)(59.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-1(59.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-2(61.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-3(63.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad MOTOR-4(65.484mm,70.531mm) on Bottom Layer And Track (59.055mm,68.768mm)(69.055mm,68.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-1(60.47mm,47.262mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.111mm < 0.254mm) Between Pad U1-2(46.72mm,47.387mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.111mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.181mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.181mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.023mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.023mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-3(60.47mm,39.512mm) on Multi-Layer And Track (61.595mm,38.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.142mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (38.73mm,38.481mm)(59.558mm,38.481mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.142mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(45.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U1-4(46.72mm,39.512mm) on Multi-Layer And Track (45.595mm,38.387mm)(61.595mm,38.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.236mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-5(51.684mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.099mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Text "-" (47.76mm,47.752mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.099mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.055mm < 0.254mm) Between Pad U3-6(49.154mm,49.331mm) on Multi-Layer And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.055mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-1(45.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-2(47.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-3(50.319mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U4-4(52.819mm,52.177mm) on Bottom Layer And Track (44.069mm,50.927mm)(54.069mm,50.927mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-1(60.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-2(62.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-3(65.305mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(67.805mm,50.018mm) on Bottom Layer And Track (59.055mm,48.768mm)(69.055mm,48.768mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-1(53.115mm,64.232mm) on Top Layer And Track (53.362mm,64.713mm)(53.362mm,65.679mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "dp" (53.987mm,62.512mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.074mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Text "G" (54.102mm,64.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.074mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-2(53.115mm,62.982mm) on Top Layer And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.148mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Text "dm" (54.102mm,61.214mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.148mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-3(53.115mm,61.732mm) on Top Layer And Track (53.362mm,62.213mm)(53.362mm,62.501mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Text "v" (54.385mm,60.566mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.204mm < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.204mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-4(53.115mm,60.482mm) on Top Layer And Track (53.362mm,60.963mm)(53.362mm,61.251mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Text "USB" (49.53mm,67.691mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (48.265mm,65.732mm)(48.784mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-5(50.515mm,66.782mm) on Top Layer And Track (52.247mm,65.732mm)(53.362mm,65.732mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (48.265mm,58.982mm)(48.784mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad USB-6(50.515mm,57.932mm) on Top Layer And Track (52.247mm,58.982mm)(53.362mm,58.982mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
Rule Violations :116
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "-" (47.76mm,47.752mm) on Bottom Overlay And Track (45.595mm,48.387mm)(61.595mm,48.387mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(54.991mm,78.104mm) on Top Overlay Silk Text to Silk Clearance [0.003mm]
Violation between Silk To Silk Clearance Constraint: (0.003mm < 0.254mm) Between Text "dp" (53.987mm,62.512mm) on Top Overlay And Track (54.991mm,62.484mm)(72.771mm,62.484mm) on Top Overlay Silk Text to Silk Clearance [0.003mm]
Violation between Silk To Silk Clearance Constraint: (0.029mm < 0.254mm) Between Text "G" (54.102mm,64.281mm) on Top Overlay And Track (53.362mm,63.463mm)(53.362mm,63.751mm) on Top Overlay Silk Text to Silk Clearance [0.029mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "G" (67.056mm,54.928mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,60.562mm)(64.443mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "GPS" (64.389mm,60.96mm) on Top Overlay And Track (64.443mm,61.081mm)(71.193mm,61.081mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,43.929mm)(64.689mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "LB" (64.643mm,44.196mm) on Top Overlay And Track (64.689mm,44.167mm)(70.439mm,44.167mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "MOTOR" (68.389mm,72.263mm) on Bottom Overlay And Track (68.484mm,70.581mm)(68.484mm,78.181mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "tx" (69.469mm,54.337mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (38.73mm,51.181mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.186mm < 0.254mm) Between Text "U3" (57.912mm,51.054mm) on Top Overlay And Track (59.558mm,38.481mm)(59.558mm,51.181mm) on Top Overlay Silk Text to Silk Clearance [0.186mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (53.911mm,60.833mm) on Bottom Overlay And Track (54.069mm,50.927mm)(54.069mm,70.927mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U5" (68.897mm,58.674mm) on Bottom Overlay And Track (69.055mm,48.768mm)(69.055mm,68.768mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.253mm < 0.254mm) Between Text "v" (54.385mm,60.566mm) on Top Overlay And Track (53.362mm,59.713mm)(53.362mm,60.001mm) on Top Overlay Silk Text to Silk Clearance [0.253mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "v" (65.815mm,55.105mm) on Top Overlay And Track (63.691mm,54.492mm)(71.691mm,54.492mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Rule Violations :17
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 163
Waived Violations : 0
Time Elapsed : 00:00:01