22.7.14
This commit is contained in:
BIN
SIF LIGHT/主板/1.25T-6P.PcbLib
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SIF LIGHT/主板/1.25T-6P.PcbLib
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SIF LIGHT/主板/1.25t-3p.PcbLib
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SIF LIGHT/主板/1.25t-3p.PcbLib
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SIF LIGHT/主板/PCB_Project2.PrjPCB
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SIF LIGHT/主板/PCB_Project2.PrjPCB
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SIF LIGHT/主板/PCB_Project2.PrjPCBStructure
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1
SIF LIGHT/主板/PCB_Project2.PrjPCBStructure
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Record=TopLevelDocument|FileName=SIF Light_SCH 20220112_2022-07-06.schdoc
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Change Component DesignItemId : Designator=C2 Old DesignItemId= New DesignItemId=0.1uF
|
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Change Component DesignItemId : Designator=C1 Old DesignItemId= New DesignItemId=1uF
|
||||
Change Component DesignItemId : Designator=U1 Old DesignItemId= New DesignItemId=2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
Change Component DesignItemId : Designator=R1 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R2 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R3 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=R4 Old DesignItemId= New DesignItemId=4.7K
|
||||
Change Component DesignItemId : Designator=C3 Old DesignItemId= New DesignItemId=10uF
|
||||
Change Component DesignItemId : Designator=U5 Old DesignItemId= New DesignItemId=ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP
|
||||
Change Component DesignItemId : Designator=BAT1 Old DesignItemId= New DesignItemId=CR1220-2ZX
|
||||
Change Component DesignItemId : Designator=U4 Old DesignItemId= New DesignItemId=DS3231S
|
||||
Change Component DesignItemId : Designator=J1 Old DesignItemId= New DesignItemId=PH2.0W-1X4P
|
||||
Change Component DesignItemId : Designator=J2 Old DesignItemId= New DesignItemId=<3D><>Դ
|
||||
Change Component DesignItemId : Designator=J3 Old DesignItemId= New DesignItemId=<3D><>Դ
|
||||
Change Component DesignItemId : Designator=U2 Old DesignItemId= New DesignItemId=<3D><>ѹģ<D1B9><C4A3>
|
||||
Change Component DesignItemId : Designator=U3 Old DesignItemId= New DesignItemId=<3D><>ѹģ<D1B9><C4A3>
|
||||
Change component parameters: Designator = "U5"; Footprint = "ARDUINO-NANO-3.0#ISP"; UniqueID = "\ggea8e2f660ede1f0ef"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "sourceId"; Value = "MHTVTfAWi"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "M"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "ARDUINO-NANO-3.0#ISP_ARDUINO-NANO-3.0#ISP"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "timeStamp"; Value = "1463648055"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "J1"; Footprint = "PH2.0W-1X4P<34><50>װ"; UniqueID = "\gge02c95373f3317acc"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "HeZo"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "43650-0615"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C239442"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "<22><><EFBFBD>ݺ<EFBFBD><EFBFBD><D7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0W-1X4P"; VariantName = "[No Variations]"
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||||
Change component parameters: Designator = "J2"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge7a2095f9640df2a7"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "J3"; Footprint = "CONN-SMD_PH2.0-1X2PW"; UniqueID = "\gge24a1f388fafc13fc"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "BOOMELE"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C64658"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "PH2.0-2P"; VariantName = "[No Variations]"
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||||
Change component parameters: Designator = "R1"; Footprint = "R0603"; UniqueID = "\gge07bdca5a3aea9139"
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||||
Change component parameters. Clean all parameters for all variants
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R2"; Footprint = "R0603"; UniqueID = "\gge4ef602786d337833"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R3"; Footprint = "R0603"; UniqueID = "\gge195776cbb43ef2a0"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "R4"; Footprint = "R0603"; UniqueID = "\gge8d4ca9ec2c2f1680"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "BAT1"; Footprint = "BAT-SMD_CR1220-2ZX"; UniqueID = "\gge8f29627181d88637"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "Q&J"; VariantName = "[No Variations]"
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||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "CR1220-2ZX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C969906"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "B"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "CR1220-2ZX"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U4"; Footprint = "SOIC-16_L10.3-W7.5-P1.27-LS10.3-BL"; UniqueID = "\ggeae4eb166f739c636"
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||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "MAXIM(<28><><EFBFBD><EFBFBD>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "DS3231S#T&R"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C2651514"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "DS3231S#T&R"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U1"; Footprint = "2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>(˫H<CBAB>Ų<EFBFBD><C5B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)"; UniqueID = "\gge950fff3d33dc0e42"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "nidewenyin"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "2·ֱ<C2B7><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>(˫H<CBAB>Ų<EFBFBD><C5B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) COPY"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U2"; Footprint = "<22><>ѹģ<D1B9><C4A3>"; UniqueID = "\ggee20cb5c0ba300364"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "<22><>ѹģ<D1B9><C4A3>"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "U3"; Footprint = "<22><>ѹģ<D1B9><C4A3>"; UniqueID = "\ggee77114038a0ead5f"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "tianyahangjia"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "<22><>ѹģ<D1B9><C4A3>"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C1"; Footprint = "C0603"; UniqueID = "\gge66964c34a4fec96d"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C2"; Footprint = "C0603"; UniqueID = "\ggeffcf16b24939ebf5"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C3"; Footprint = "C0603"; UniqueID = "\gge2a8eca0813df4c7e"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer"; Value = "AVX"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Manufacturer Part"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "BOM_Supplier Part"; Value = "C167407"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "nameAlias"; Value = "Capacitance"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "spiceSymbolName"; Value = "0603ZD105KAT2A"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R5(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R6(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=R5-2
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=R6-2
|
||||
Change Net Name : Old Net Name=R1_1 New Net Name=NetR1_1
|
||||
Change Net Name : Old Net Name=R2_1 New Net Name=NetR2_1
|
||||
Change Net Name : Old Net Name=U4_14 New Net Name=NetBAT1_1
|
||||
Added Net: Name=GND
|
||||
Added Pin To Net: NetName=NetPt1_2 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetPt1_2 Pin=U5-J1.11
|
||||
Added Net: Name=NetPt1_2
|
||||
Added Pin To Net: NetName=NetPt2_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetPt2_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetPt2_2
|
||||
Added Class: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,3 @@
|
||||
Change Component Footprint: Designator=U2 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Change Component Footprint: Designator=U3 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,21 @@
|
||||
Change Component Footprint: Designator=U2 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Change Component Footprint: Designator=U3 Old Footprint= New Footprint=<3D><>Դģ<D4B4><C4A3>
|
||||
Added Component: Designator=P?(1.25T-6P)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=P?-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P?-3
|
||||
Added Pin To Net: NetName=GND Pin=P?-4
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P?-6
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=P?-2
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetP?_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetP?_2
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=P?-5
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetP?_5 Pin=U5-J1.11
|
||||
Added Net: Name=NetP?_5
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P? Header 6
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,3 @@
|
||||
Removed Pin From Net: NetName=GND Pin=P?-1
|
||||
Added Pin To Net: NetName=DGND Pin=P?-1
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,2 @@
|
||||
Added Pin To Net: NetName=DGND Pin=P?-4
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,30 @@
|
||||
Removed Pin From Net: NetName=DGND Pin=P?-1
|
||||
Removed Pin From Net: NetName=VCC3.3 Pin=P?-3
|
||||
Removed Pin From Net: NetName=DGND Pin=P?-4
|
||||
Removed Pin From Net: NetName=VCC3.3 Pin=P?-6
|
||||
Removed Member From Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=P?
|
||||
Added Component: Designator=P1(1.25t-3p)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=P2(1.25t-3p)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=DGND Pin=P1-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P1-3
|
||||
Added Pin To Net: NetName=DGND Pin=P2-1
|
||||
Added Pin To Net: NetName=VCC3.3 Pin=P2-3
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=P1-2
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetP1_2 Pin=U5-J1.11
|
||||
Added Net: Name=NetP1_2
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=P2-2
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetP2_2 Pin=U5-J1.12
|
||||
Added Net: Name=NetP2_2
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P1 Header 3
|
||||
Added Member To Class: ClassName=SIF Light_SCH 20220112_2022-07-06 Member=Component P2 Header 3
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,4 @@
|
||||
Change Component Footprint: Designator=P1 Old Footprint=1.25t-3p New Footprint=ds18b20
|
||||
Change Component Comment : Designator=P1 Old Comment=Header 3 New Comment=inner
|
||||
Change Component Comment : Designator=P2 Old Comment=Header 3 New Comment=outside'
|
||||
Added Room: Name=SIF Light_SCH 20220112_2022-07-06
|
||||
@ -0,0 +1,210 @@
|
||||
Protel Design System Design Rule Check
|
||||
PCB File : C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc
|
||||
Date : 2022/7/7
|
||||
Time : 16:14:59
|
||||
|
||||
Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Un-Routed Net Constraint ( (All) )
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Violation between Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm
|
||||
Rule Violations :4
|
||||
|
||||
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]
|
||||
Rule Violations :130
|
||||
|
||||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||||
Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V<35><56><EFBFBD><EFBFBD>" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V<39><56><EFBFBD><EFBFBD>" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]
|
||||
Rule Violations :28
|
||||
|
||||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
|
||||
Violations Detected : 162
|
||||
Waived Violations : 0
|
||||
Time Elapsed : 00:00:01
|
||||
@ -0,0 +1,822 @@
|
||||
<html>
|
||||
<head>
|
||||
<META http-equiv="Content-Type" content="text/html">
|
||||
<style type="text/css">
|
||||
h1, h2, h3, h4, h5, h6 {
|
||||
font-family : segoe ui;
|
||||
color : black;
|
||||
background-color : #EDE7D9;
|
||||
padding: 0.3em;
|
||||
}
|
||||
|
||||
h1 {
|
||||
font-size: 1.2em;
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
|
||||
td, th {
|
||||
padding: 0.5em;
|
||||
text-align : left;
|
||||
width: 10em;
|
||||
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|
||||
th {
|
||||
background-color : #EEEEEE;
|
||||
|
||||
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|
||||
th.column1, td.column1 {
|
||||
text-align: left;
|
||||
width : auto;
|
||||
}
|
||||
table {
|
||||
width : 100%;
|
||||
font-size: 0.9em;
|
||||
}
|
||||
|
||||
.DRC_summary_header {
|
||||
padding-bottom : 0.1em;
|
||||
border : 0px solid black;
|
||||
width: 100%;
|
||||
align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1,
|
||||
.DRC_summary_header_col2,
|
||||
.DRC_summary_header_col3 {
|
||||
color : black;
|
||||
font-size:100%;
|
||||
padding : 0em;
|
||||
padding-top : 0.2em;
|
||||
padding-bottom 0.2em;
|
||||
border : 0px solid black;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1 {
|
||||
font-weight: bold;
|
||||
width: 8em;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col2 {
|
||||
width: 0.1em;
|
||||
|
||||
}
|
||||
|
||||
.DRC_summary_header_col3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.header_holder {
|
||||
Width = 100%;
|
||||
border = 0px solid green;
|
||||
padding = 0;
|
||||
}
|
||||
|
||||
|
||||
.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3
|
||||
{
|
||||
left : 0;
|
||||
top : 0;
|
||||
padding: 0em;
|
||||
padding-top : 0.1em;
|
||||
border : 0px solid black;
|
||||
width : 100%;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.front_matter_column1 {
|
||||
width : 8em;
|
||||
font-weight: bold;
|
||||
}
|
||||
|
||||
.front_matter_column2 {
|
||||
width: 0.1em;
|
||||
}
|
||||
|
||||
.front_matter_column3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.total_column1, .total_column {
|
||||
font-weight : bold;
|
||||
}
|
||||
.total_column1 {
|
||||
text-align : left;
|
||||
}
|
||||
.warning, .error {
|
||||
color : red;
|
||||
font-weight : bold;
|
||||
}
|
||||
tr.onmouseout_odd {
|
||||
background-color : #white;
|
||||
}
|
||||
tr.onmouseout_even {
|
||||
background-color : #FAFAFA;
|
||||
}
|
||||
tr.onmouseover_odd, tr.onmouseover_even {
|
||||
background-color : #EEEEEE;
|
||||
}
|
||||
a:link, a:visited, .q a:link,.q a:active,.q {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.callback, a:visited.callback {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.customize, a:visited.customize {
|
||||
color: #C0C0C0;
|
||||
position: absolute;
|
||||
right: 10px;
|
||||
}
|
||||
p.contents_level1 {
|
||||
font-weight : bold;
|
||||
font-size : 110%;
|
||||
margin : 0.5em;
|
||||
}
|
||||
p.contents_level2 {
|
||||
position : relative;
|
||||
left : 20px;
|
||||
margin : 0.5em;
|
||||
}
|
||||
</style><script type="text/javascript">
|
||||
function coordToMils(coord) {
|
||||
var number = coord / 10000;
|
||||
|
||||
if (number != number.toFixed(3))
|
||||
number = number.toFixed(3);
|
||||
|
||||
return number + 'mil'
|
||||
}
|
||||
|
||||
function coordToMM(coord) {
|
||||
var number = 0.0254 * coord / 10000;
|
||||
|
||||
if (number != number.toFixed(4))
|
||||
number = number.toFixed(4);
|
||||
|
||||
return number + 'mm'
|
||||
}
|
||||
|
||||
function convertCoord(coordNode, units) {
|
||||
for (var i = 0; i < coordNode.childNodes.length; i++) {
|
||||
coordNode.removeChild(coordNode.childNodes[i]);
|
||||
}
|
||||
|
||||
var coord = coordNode.getAttribute('value');
|
||||
if (coord != null) {
|
||||
if (units == 'mm') {
|
||||
textNode = document.createTextNode(coordToMM(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
} else if (units == 'mil') {
|
||||
textNode = document.createTextNode(coordToMils(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
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|
||||
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|
||||
}
|
||||
|
||||
function convertUnits(unitNode, units) {
|
||||
for (var i = 0; i < unitNode.childNodes.length; i++) {
|
||||
unitNode.removeChild(unitNode.childNodes[i]);
|
||||
}
|
||||
|
||||
textNode = document.createTextNode(units);
|
||||
unitNode.appendChild(textNode);
|
||||
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|
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|
||||
function changeUnits(radio_input, units) {
|
||||
if (radio_input.checked) {
|
||||
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||||
var elements = document.getElementsByName('coordinate');
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if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
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convertCoord(elements[i], units);
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||||
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|
||||
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|
||||
|
||||
var elements = document.getElementsByName('units');
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||||
if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
||||
convertUnits(elements[i], units);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
</script><title>Design Rule Verification Report</title>
|
||||
</head>
|
||||
<body onload=""><img ALT="Altium" src="
|
||||
file://C:\Users\Public\Documents\Altium\AD18\Templates\AD_logo.png
|
||||
"><h1>Design Rule Verification Report</h1>
|
||||
<table class="header_holder">
|
||||
<td class="column1">
|
||||
<table class="front_matter">
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Date:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">2022/7/7</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">16:14:59</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Elapsed Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">00:00:01</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Filename:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3"><a href="file:///C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc" class="file"><acronym title="C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc">C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc</acronym></a></td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
<td class="column2">
|
||||
<table class="DRC_summary_header">
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Warnings:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3">0</td></tr>
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Rule Violations:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3" style="color : red">162</td></tr>
|
||||
</table>
|
||||
</td>
|
||||
</table><a name="IDVDXQFH4TVCI2I502KFEQSUBCSEVGAQQM2SPLNUJYJBGHYJTLUBCN"><h2>Summary</h2></a><table>
|
||||
<tr>
|
||||
<th class="column1">Warnings</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">0</td>
|
||||
</tr>
|
||||
</table><br><table>
|
||||
<tr>
|
||||
<th class="column1">Rule Violations</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID5C4YYG4SSDOVNSNPD22PMF51AGWOY5J3P2KKM4FIIV1PBHQ5J40">Clearance Constraint (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDADQFVNRZJ4PMCACHR4LVIQSG4KT3B4SGITD3RBOW4VXPXMBAKZME">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDFRNUAMVPBIY4ID45IJ130XNFUELVII2CG41MI2NX3540CBUH4DHB">Un-Routed Net Constraint ( (All) )</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDNZZ2HPHHNMKWEJ2O5FUMCJCYQILVEFHTFH4L5XOC5NXRU4PM3YPN">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID4US1TKWPHWYZBSU1XYSBWAELCCCMAYKLUVVYPROH0XQY2YWYWC2M">Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDHSI4EV51BH3NWA30WA0ITROJOV02J2XAOT53BIOF5L0IHFNDT1L">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDFETFPWDHNEM1KR5URX4KBMRQPEIDADCEYZGOHXDE3SFUX3TIH1UK">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</a></td>
|
||||
<td class="column2">4</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDCRSQPW05NXZ2OTMBTXRI3BWCJMWPAC5UMNHGC4HCPOG3ZDVAP2WL">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDCTVXQ4FCPZS2JGQB5URTW3LVCEDM0LEGHH0AQIKLJZ2F12IQ0DMO">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDTKLASX114WJ50VDNG2DLBME2OHPJMA3QPBUSBBKDTODSE4IJBHP">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</a></td>
|
||||
<td class="column2">130</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDMCJP3D02ZFQHPPYMOWNQXNMLCIUH2AH4P4UYLB0K1XM3UTEDRGD">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">28</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDN3NDKPZH1WMWGKA0PK5R4AB3FCS2ZQZ2OEA3ENNDI053AUBOUC4I">Net Antennae (Tolerance=0mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDOUR41COCMLC2MRBC3BRVXC2POC1KP0TNEHS1SUHN11WXEXMBUAG">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">162</td>
|
||||
</tr>
|
||||
</table><br><a name="IDFETFPWDHNEM1KR5URX4KBMRQPEIDADCEYZGOHXDE3SFUX3TIH1UK"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=2012.13mil|Location2.Y=2131.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1543.75mil|Location2.X=1663.11mil|Location1.Y=2012.13mil|Location2.Y=2131.49mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(40.727mm,52.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=3941.26mil|Location2.Y=4060.62mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,101.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=1618.43mil|Location2.Y=1737.79mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3512.25mil|Location2.X=3631.61mil|Location1.Y=1618.43mil|Location2.Y=1737.79mil|Absolute=True">Hole Size Constraint: (3mm > 2.54mm) Pad Free-(90.727mm,42.624mm) on Multi-Layer Actual Hole Size = 3mm</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDTKLASX114WJ50VDNG2DLBME2OHPJMA3QPBUSBBKDTODSE4IJBHP"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.292mil|Location2.X=1675.542mil|Location1.Y=1793.066mil|Location2.Y=1806.385mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.292mil|Location2.X=1675.542mil|Location1.Y=1793.066mil|Location2.Y=1806.385mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.165mil|Location2.X=1675.415mil|Location1.Y=1882.867mil|Location2.Y=1894.117mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.165mil|Location2.X=1675.415mil|Location1.Y=1882.867mil|Location2.Y=1894.117mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (42.532mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.453mil|Location2.X=1715.703mil|Location1.Y=1795.145mil|Location2.Y=1808.512mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.453mil|Location2.X=1715.703mil|Location1.Y=1795.145mil|Location2.Y=1808.512mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (43.326mm,45.783mm) on Top Overlay And Pad C3-2(42.926mm,46.163mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.801mil|Location2.X=1716.051mil|Location1.Y=1882.935mil|Location2.Y=1894.185mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.801mil|Location2.X=1716.051mil|Location1.Y=1882.935mil|Location2.Y=1894.185mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (43.332mm,47.959mm) on Top Overlay And Pad C3-1(42.926mm,47.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2346.463mil|Location2.X=2357.713mil|Location1.Y=2294.688mil|Location2.Y=2305.938mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2346.463mil|Location2.X=2357.713mil|Location1.Y=2294.688mil|Location2.Y=2305.938mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.048mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2342.699mil|Location2.X=2353.949mil|Location1.Y=2456.47mil|Location2.Y=2467.72mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2342.699mil|Location2.X=2353.949mil|Location1.Y=2456.47mil|Location2.Y=2467.72mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.17mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Pad BAT1-1(61.432mm,60.452mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.17mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2181.395mil|Location2.X=2192.645mil|Location1.Y=1655.076mil|Location2.Y=1666.326mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2181.395mil|Location2.X=2192.645mil|Location1.Y=1655.076mil|Location2.Y=1666.326mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (55.55mm,41.806mm) on Top Overlay And Pad U4-1(55.55mm,42.545mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.949mil|Location2.X=2360.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.949mil|Location2.X=2360.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (59.919mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.297mil|Location2.X=2360.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.297mil|Location2.X=2360.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.585mil|Location2.X=2400.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.585mil|Location2.X=2400.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (60.719mm,43.481mm) on Top Overlay And Pad C2-1(60.325mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.458mil|Location2.X=2400.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.458mil|Location2.X=2400.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Pad C2-2(60.325mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.949mil|Location2.X=2455.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.949mil|Location2.X=2455.199mil|Location1.Y=1705.815mil|Location2.Y=1717.065mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Arc (62.332mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.297mil|Location2.X=2455.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.297mil|Location2.X=2455.547mil|Location1.Y=1793.605mil|Location2.Y=1806.973mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.585mil|Location2.X=2495.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.585mil|Location2.X=2495.835mil|Location1.Y=1705.883mil|Location2.Y=1717.133mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Arc (63.132mm,43.481mm) on Top Overlay And Pad C1-1(62.738mm,43.877mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.458mil|Location2.X=2495.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.458mil|Location2.X=2495.708mil|Location1.Y=1791.545mil|Location2.Y=1804.864mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.129mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Pad C1-2(62.738mm,45.277mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.129mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2292.229mil|Location2.Y=2303.479mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2292.229mil|Location2.Y=2303.479mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,53.282mm)(61.072mm,58.152mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2455.733mil|Location2.Y=2466.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2398.784mil|Location2.X=2410.034mil|Location1.Y=2455.733mil|Location2.Y=2466.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad BAT1-1(61.432mm,60.452mm) on Top Layer And Track (61.072mm,62.712mm)(61.072mm,67.602mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.933mil|Location2.X=2455.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2443.933mil|Location2.X=2455.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.023mm,43.481mm)(62.023mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2481.444mil|Location2.X=2492.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2481.444mil|Location2.X=2492.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (62.332mm,43.172mm)(63.132mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.595mil|Location2.X=2495.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.595mil|Location2.X=2495.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C1-1(62.738mm,43.877mm) on Top Layer And Track (63.442mm,43.481mm)(63.442mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.041mil|Location2.X=2455.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2444.041mil|Location2.X=2455.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.028mm,44.857mm)(62.028mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.636mil|Location2.X=2459.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.636mil|Location2.X=2459.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.71mil|Location2.X=2495.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2484.71mil|Location2.X=2495.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C1-2(62.738mm,45.277mm) on Top Layer And Track (63.448mm,44.857mm)(63.448mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.933mil|Location2.X=2360.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2348.933mil|Location2.X=2360.183mil|Location1.Y=1737.568mil|Location2.Y=1748.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.61mm,43.481mm)(59.61mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2386.444mil|Location2.X=2397.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2386.444mil|Location2.X=2397.694mil|Location1.Y=1702.516mil|Location2.Y=1713.766mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.184mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (59.919mm,43.172mm)(60.719mm,43.172mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.184mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.595mil|Location2.X=2400.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.595mil|Location2.X=2400.845mil|Location1.Y=1706.24mil|Location2.Y=1717.49mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C2-1(60.325mm,43.877mm) on Top Layer And Track (61.029mm,43.481mm)(61.029mm,44.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.041mil|Location2.X=2360.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2349.041mil|Location2.X=2360.291mil|Location1.Y=1792.48mil|Location2.Y=1803.73mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.615mm,44.857mm)(59.615mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1795.889mil|Location2.Y=1807.139mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.163mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.163mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.71mil|Location2.X=2400.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2389.71mil|Location2.X=2400.96mil|Location1.Y=1761.182mil|Location2.Y=1772.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C2-2(60.325mm,45.277mm) on Top Layer And Track (61.035mm,44.857mm)(61.035mm,45.657mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.155mil|Location2.X=1675.405mil|Location1.Y=1882.636mil|Location2.Y=1893.886mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.155mil|Location2.X=1675.405mil|Location1.Y=1882.636mil|Location2.Y=1893.886mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.127mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1668.849mil|Location2.X=1680.099mil|Location1.Y=1886.193mil|Location2.Y=1897.443mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1668.849mil|Location2.X=1680.099mil|Location1.Y=1886.193mil|Location2.Y=1897.443mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (42.532mm,48.268mm)(43.332mm,48.268mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.817mil|Location2.X=1716.067mil|Location1.Y=1851.182mil|Location2.Y=1862.432mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.817mil|Location2.X=1716.067mil|Location1.Y=1851.182mil|Location2.Y=1862.432mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.138mm < 0.254mm) Between Pad C3-1(42.926mm,47.563mm) on Top Layer And Track (43.641mm,47.159mm)(43.641mm,47.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.138mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.04mil|Location2.X=1675.29mil|Location1.Y=1827.568mil|Location2.Y=1838.818mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1664.04mil|Location2.X=1675.29mil|Location1.Y=1827.568mil|Location2.Y=1838.818mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1701.529mil|Location2.X=1712.779mil|Location1.Y=1792.824mil|Location2.Y=1804.074mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1701.529mil|Location2.X=1712.779mil|Location1.Y=1792.824mil|Location2.Y=1804.074mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.167mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (42.526mm,45.473mm)(43.326mm,45.473mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.167mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.702mil|Location2.X=1715.952mil|Location1.Y=1796.846mil|Location2.Y=1808.096mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.702mil|Location2.X=1715.952mil|Location1.Y=1796.846mil|Location2.Y=1808.096mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.133mm < 0.254mm) Between Pad C3-2(42.926mm,46.163mm) on Top Layer And Track (43.636mm,45.783mm)(43.636mm,46.583mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.133mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=4084.153mil|Location2.Y=4095.403mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=4084.153mil|Location2.Y=4095.403mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,104.044mm)(51.212mm,104.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=4032.066mil|Location2.Y=4043.316mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=4032.066mil|Location2.Y=4043.316mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,103.244mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=3624.591mil|Location2.Y=3635.841mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1864.923mil|Location2.X=1876.173mil|Location1.Y=3624.591mil|Location2.Y=3635.841mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.073mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,92.044mm)(51.212mm,92.044mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.073mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=3676.677mil|Location2.Y=3687.927mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1711.377mil|Location2.X=1722.627mil|Location1.Y=3676.677mil|Location2.Y=3687.927mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.173mm < 0.254mm) Between Pad J1-(45.512mm,92.844mm) on Top Layer And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.173mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3949.37mil|Location2.Y=3960.62mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3949.37mil|Location2.Y=3960.62mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-1(51.262mm,101.044mm) on Top Layer And Text "V" (53.34mm,100.076mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3911.863mil|Location2.Y=3923.113mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3911.863mil|Location2.Y=3923.113mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-2(51.262mm,99.044mm) on Top Layer And Text "G" (53.34mm,98.552mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3724.375mil|Location2.Y=3735.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2086.417mil|Location2.X=2097.667mil|Location1.Y=3724.375mil|Location2.Y=3735.625mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad J1-4(51.262mm,95.044mm) on Top Layer And Text "R" (53.34mm,94.742mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=3136.92mil|Location2.Y=3148.17mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=3136.92mil|Location2.Y=3148.17mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3180.472mil|Location2.Y=3191.722mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3180.472mil|Location2.Y=3191.722mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-1(86.386mm,80.375mm) on Top Layer And Track (87.826mm,81.106mm)(87.826mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=3058.18mil|Location2.Y=3069.43mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=3058.18mil|Location2.Y=3069.43mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,77.644mm)(87.826mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3101.733mil|Location2.Y=3112.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=3101.733mil|Location2.Y=3112.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-2(86.386mm,78.375mm) on Top Layer And Track (87.826mm,79.106mm)(87.826mm,79.644mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (87.826mm,75.375mm)(88.416mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2961.895mil|Location2.Y=2973.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-3(90.398mm,75.311mm) on Top Layer And Track (92.379mm,75.375mm)(93.226mm,75.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3526.873mil|Location2.X=3538.123mil|Location1.Y=3322.567mil|Location2.Y=3333.817mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3526.873mil|Location2.X=3538.123mil|Location1.Y=3322.567mil|Location2.Y=3333.817mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.194mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Text "J2" (89.535mm,84.709mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.194mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (87.826mm,83.375mm)(88.416mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=3276.855mil|Location2.Y=3288.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J2-4(90.398mm,83.439mm) on Top Layer And Track (92.379mm,83.375mm)(93.226mm,83.375mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=2641.92mil|Location2.Y=2653.17mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.643mil|Location1.Y=2641.92mil|Location2.Y=2653.17mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2685.472mil|Location2.Y=2696.722mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2685.472mil|Location2.Y=2696.722mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-1(86.386mm,67.802mm) on Top Layer And Track (87.826mm,68.533mm)(87.826mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=2563.18mil|Location2.Y=2574.43mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3453.909mil|Location2.X=3467.642mil|Location1.Y=2563.18mil|Location2.Y=2574.43mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,65.071mm)(87.826mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.112mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2606.733mil|Location2.Y=2617.983mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3452.075mil|Location2.X=3463.325mil|Location1.Y=2606.733mil|Location2.Y=2617.983mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-2(86.386mm,65.802mm) on Top Layer And Track (87.826mm,66.533mm)(87.826mm,67.071mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (87.826mm,62.802mm)(88.416mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2466.895mil|Location2.Y=2478.145mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-3(90.398mm,62.738mm) on Top Layer And Track (92.379mm,62.802mm)(93.226mm,62.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3521.856mil|Location2.X=3533.106mil|Location1.Y=2827.805mil|Location2.Y=2839.055mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3521.856mil|Location2.X=3533.106mil|Location1.Y=2827.805mil|Location2.Y=2839.055mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.206mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Text "J3" (89.408mm,72.136mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.206mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3482.386mil|Location2.X=3493.636mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (87.826mm,70.802mm)(88.416mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.284mil|Location2.X=3635.534mil|Location1.Y=2781.855mil|Location2.Y=2793.105mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad J3-4(90.398mm,70.866mm) on Top Layer And Track (92.379mm,70.802mm)(93.226mm,70.802mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2468.381mil|Location2.X=2476.047mil|Location1.Y=2494.599mil|Location2.Y=2502.266mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2468.381mil|Location2.X=2476.047mil|Location1.Y=2494.599mil|Location2.Y=2502.266mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-1(63.627mm,64.262mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2473.262mil|Location2.X=2480.928mil|Location1.Y=2648.029mil|Location2.Y=2655.695mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2473.262mil|Location2.X=2480.928mil|Location1.Y=2648.029mil|Location2.Y=2655.695mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-2(63.627mm,66.802mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2471.993mil|Location2.X=2479.659mil|Location1.Y=2707.864mil|Location2.Y=2715.53mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2471.993mil|Location2.X=2479.659mil|Location1.Y=2707.864mil|Location2.Y=2715.53mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P1-3(63.627mm,69.342mm) on Multi-Layer And Text "SIF Light V0.4" (64.008mm,71.247mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2084.311mil|Location2.Y=2091.978mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2084.311mil|Location2.Y=2091.978mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-1(87.772mm,53.267mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2035.098mil|Location2.Y=2042.765mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=2035.098mil|Location2.Y=2042.765mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-2(87.772mm,52.017mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=1985.885mil|Location2.Y=1993.552mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3480.487mil|Location2.X=3488.153mil|Location1.Y=1985.885mil|Location2.Y=1993.552mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad P2-3(87.772mm,50.767mm) on Top Layer And Track (88.502mm,49.304mm)(88.502mm,54.734mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3500.743mil|Location2.X=3511.993mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3500.743mil|Location2.X=3511.993mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (88.502mm,49.304mm)(92.202mm,49.304mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.375mil|Location2.X=3635.625mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3624.375mil|Location2.X=3635.625mil|Location1.Y=1929.662mil|Location2.Y=1940.912mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Pad P2-4(90.662mm,47.936mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.04mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.524mil|Location2.X=3639.73mil|Location1.Y=2155.356mil|Location2.Y=2166.606mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.524mil|Location2.X=3639.73mil|Location1.Y=2155.356mil|Location2.Y=2166.606mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.019mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (88.502mm,54.764mm)(92.202mm,54.764mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.019mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.463mil|Location2.X=3639.791mil|Location1.Y=2155.174mil|Location2.Y=2166.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3626.463mil|Location2.X=3639.791mil|Location1.Y=2155.174mil|Location2.Y=2166.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad P2-5(90.66mm,56.098mm) on Top Layer And Track (92.202mm,49.304mm)(92.202mm,54.753mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2290.844mil|Location2.X=2302.094mil|Location1.Y=1661.383mil|Location2.Y=1672.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2290.844mil|Location2.X=2302.094mil|Location1.Y=1661.383mil|Location2.Y=1672.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(58.178mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2324.57mil|Location2.X=2338.123mil|Location1.Y=1624.29mil|Location2.Y=1635.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2324.57mil|Location2.X=2338.123mil|Location1.Y=1624.29mil|Location2.Y=1635.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,41.249mm)(59.137mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2293.845mil|Location2.X=2305.095mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2293.845mil|Location2.X=2305.095mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-1(58.81mm,41.91mm) on Top Layer And Track (58.178mm,42.571mm)(59.137mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1624.367mil|Location2.Y=1635.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1624.367mil|Location2.Y=1635.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,41.249mm)(60.948mm,41.249mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2384.905mil|Location2.X=2396.155mil|Location1.Y=1664.383mil|Location2.Y=1675.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2387.906mil|Location2.X=2399.156mil|Location1.Y=1627.367mil|Location2.Y=1638.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2387.906mil|Location2.X=2399.156mil|Location1.Y=1627.367mil|Location2.Y=1638.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R1-2(60.316mm,41.91mm) on Top Layer And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.367mil|Location2.X=2280.617mil|Location1.Y=1794.906mil|Location2.Y=1806.156mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.367mil|Location2.X=2280.617mil|Location1.Y=1794.906mil|Location2.Y=1806.156mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.003mm)(57.632mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2272.367mil|Location2.X=2283.617mil|Location1.Y=1797.906mil|Location2.Y=1809.156mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2272.367mil|Location2.X=2283.617mil|Location1.Y=1797.906mil|Location2.Y=1809.156mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1766.155mil|Location2.Y=1777.405mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1766.155mil|Location2.Y=1777.405mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-1(58.293mm,45.33mm) on Top Layer And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.29mil|Location2.X=2280.54mil|Location1.Y=1732.297mil|Location2.Y=1745.82mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2269.29mil|Location2.X=2280.54mil|Location1.Y=1732.297mil|Location2.Y=1745.82mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(57.632mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2306.383mil|Location2.X=2317.633mil|Location1.Y=1700.844mil|Location2.Y=1712.094mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2306.383mil|Location2.X=2317.633mil|Location1.Y=1700.844mil|Location2.Y=1712.094mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (57.632mm,43.192mm)(58.954mm,43.192mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1703.844mil|Location2.Y=1715.094mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2309.383mil|Location2.X=2320.633mil|Location1.Y=1703.844mil|Location2.Y=1715.094mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R2-2(58.293mm,43.824mm) on Top Layer And Track (58.954mm,43.192mm)(58.954mm,44.151mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1634.367mil|Location2.Y=1645.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1634.367mil|Location2.Y=1645.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,41.503mm)(43.676mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (42.717mm,42.825mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1637.367mil|Location2.Y=1648.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1637.367mil|Location2.Y=1648.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-1(43.044mm,42.164mm) on Top Layer And Track (43.676mm,41.503mm)(43.676mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1671.383mil|Location2.Y=1682.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1671.383mil|Location2.Y=1682.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1634.29mil|Location2.Y=1645.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1634.29mil|Location2.Y=1645.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1674.383mil|Location2.Y=1685.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R3-2(41.538mm,42.164mm) on Top Layer And Track (40.906mm,42.825mm)(41.865mm,42.825mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1704.367mil|Location2.Y=1715.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1704.367mil|Location2.Y=1715.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,43.281mm)(43.676mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1704.906mil|Location2.X=1716.156mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (42.717mm,44.603mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1707.367mil|Location2.Y=1718.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1707.906mil|Location2.X=1719.156mil|Location1.Y=1707.367mil|Location2.Y=1718.617mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-1(43.044mm,43.942mm) on Top Layer And Track (43.676mm,43.281mm)(43.676mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.598mil|Location2.X=1621.848mil|Location1.Y=1716.868mil|Location2.Y=1728.118mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.598mil|Location2.X=1621.848mil|Location1.Y=1716.868mil|Location2.Y=1728.118mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Text "R4" (38.989mm,43.18mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1741.383mil|Location2.Y=1752.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1610.844mil|Location2.X=1622.094mil|Location1.Y=1741.383mil|Location2.Y=1752.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1704.29mil|Location2.Y=1715.54mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1644.57mil|Location2.X=1658.123mil|Location1.Y=1704.29mil|Location2.Y=1715.54mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.165mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.165mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1613.844mil|Location2.X=1625.094mil|Location1.Y=1744.383mil|Location2.Y=1755.633mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad R4-2(41.538mm,43.942mm) on Top Layer And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3440.588mil|Location2.X=3454.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3440.588mil|Location2.X=3454.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R5-1(86.868mm,44.588mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3390.753mil|Location2.X=3402.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3390.753mil|Location2.X=3402.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R5-2(86.868mm,42.788mm) on Top Layer And Track (86.268mm,43.688mm)(87.468mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3360.588mil|Location2.X=3374.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3360.588mil|Location2.X=3374.142mil|Location1.Y=1722.148mil|Location2.Y=1733.398mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad R6-1(84.836mm,44.588mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.216mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3310.753mil|Location2.X=3322.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3310.753mil|Location2.X=3322.003mil|Location1.Y=1706.501mil|Location2.Y=1717.751mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad R6-2(84.836mm,42.788mm) on Top Layer And Track (84.236mm,43.688mm)(85.436mm,43.688mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.2mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2712.014mil|Location2.X=2723.264mil|Location1.Y=3328.775mil|Location2.Y=3340.025mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2712.014mil|Location2.X=2723.264mil|Location1.Y=3328.775mil|Location2.Y=3340.025mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.222mm < 0.254mm) Between Pad U1-10(68.773mm,85.481mm) on Multi-Layer And Text "U3" (69.215mm,84.01mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.222mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3264.907mil|Location2.Y=3272.574mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3264.907mil|Location2.Y=3272.574mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-1(43.287mm,82.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3363.332mil|Location2.Y=3370.999mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3363.332mil|Location2.Y=3370.999mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-2(43.287mm,84.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3461.757mil|Location2.Y=3469.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3461.757mil|Location2.Y=3469.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-3(43.287mm,87.276mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3560.182mil|Location2.Y=3567.849mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3560.182mil|Location2.Y=3567.849mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U2-4(43.287mm,89.776mm) on Top Layer And Track (42.037mm,81.026mm)(42.037mm,91.026mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2794.907mil|Location2.Y=2802.574mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2794.907mil|Location2.Y=2802.574mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-1(43.287mm,70.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2893.332mil|Location2.Y=2900.999mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2893.332mil|Location2.Y=2900.999mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-2(43.287mm,72.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2991.757mil|Location2.Y=2999.424mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=2991.757mil|Location2.Y=2999.424mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-3(43.287mm,75.338mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3090.182mil|Location2.Y=3097.849mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1656.167mil|Location2.X=1663.833mil|Location1.Y=3090.182mil|Location2.Y=3097.849mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U3-4(43.287mm,77.838mm) on Top Layer And Track (42.037mm,69.088mm)(42.037mm,79.088mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1677.836mil|Location2.Y=1689.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1677.836mil|Location2.Y=1689.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-1(55.55mm,42.545mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1961.382mil|Location2.Y=1972.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1961.382mil|Location2.Y=1972.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-10(46.05mm,50.165mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1911.382mil|Location2.Y=1922.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1911.382mil|Location2.Y=1922.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-11(46.05mm,48.895mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1861.382mil|Location2.Y=1872.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1861.382mil|Location2.Y=1872.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-12(46.05mm,47.625mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1811.382mil|Location2.Y=1822.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1811.382mil|Location2.Y=1822.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-13(46.05mm,46.355mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1761.382mil|Location2.Y=1772.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1761.382mil|Location2.Y=1772.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-14(46.05mm,45.085mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1711.382mil|Location2.Y=1722.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1711.382mil|Location2.Y=1722.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-15(46.05mm,43.815mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1661.382mil|Location2.Y=1672.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=1661.382mil|Location2.Y=1672.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-16(46.05mm,42.545mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1727.836mil|Location2.Y=1739.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1727.836mil|Location2.Y=1739.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-2(55.55mm,43.815mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1777.836mil|Location2.Y=1789.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1777.836mil|Location2.Y=1789.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-3(55.55mm,45.085mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1827.836mil|Location2.Y=1839.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1827.836mil|Location2.Y=1839.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-4(55.55mm,46.355mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1877.836mil|Location2.Y=1889.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1877.836mil|Location2.Y=1889.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-5(55.55mm,47.625mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1927.836mil|Location2.Y=1939.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1927.836mil|Location2.Y=1939.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-6(55.55mm,48.895mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1977.836mil|Location2.Y=1989.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=1977.836mil|Location2.Y=1989.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-7(55.55mm,50.165mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=2027.836mil|Location2.Y=2039.086mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2133.04mil|Location2.X=2144.29mil|Location1.Y=2027.836mil|Location2.Y=2039.086mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad U4-8(55.55mm,51.435mm) on Top Layer And Track (54.121mm,41.764mm)(54.121mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.249mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=2011.382mil|Location2.Y=2022.632mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1855.958mil|Location2.X=1867.208mil|Location1.Y=2011.382mil|Location2.Y=2022.632mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.236mm < 0.254mm) Between Pad U4-9(46.05mm,51.435mm) on Top Layer And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.236mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,78.232mm)(81.407mm,77.597mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3193.618mil|Location2.X=3204.868mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (80.772mm,79.502mm)(81.407mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3068.618mil|Location2.Y=3079.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,77.597mm)(83.312mm,78.232mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3255.132mil|Location2.X=3266.382mil|Location1.Y=3130.132mil|Location2.Y=3141.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J1.1(82.042mm,78.867mm) on Multi-Layer And Track (82.677mm,80.137mm)(83.312mm,79.502mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3168.618mil|Location2.Y=3179.868mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3168.618mil|Location2.Y=3179.868mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,80.772mm)(71.247mm,80.137mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3230.132mil|Location2.Y=3241.382mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2793.618mil|Location2.X=2804.868mil|Location1.Y=3230.132mil|Location2.Y=3241.382mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.23mm < 0.254mm) Between Pad U5-J4.1(71.882mm,81.407mm) on Multi-Layer And Track (70.612mm,82.042mm)(71.247mm,82.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.23mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDMCJP3D02ZFQHPPYMOWNQXNMLCIUH2AH4P4UYLB0K1XM3UTEDRGD"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk to Silk (Clearance=0.254mm) (All),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.629mil|Location2.X=1660.879mil|Location1.Y=1802.5mil|Location2.Y=1813.995mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.629mil|Location2.X=1660.879mil|Location1.Y=1802.5mil|Location2.Y=1813.995mil|Absolute=True">Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Arc (42.526mm,45.783mm) on Top Overlay And Text "C3" (41.91mm,45.847mm) on Top Overlay Silk Text to Silk Clearance [0.195mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1798.477mil|Location2.X=1809.727mil|Location1.Y=2269.68mil|Location2.Y=2283.081mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1798.477mil|Location2.X=1809.727mil|Location1.Y=2269.68mil|Location2.Y=2283.081mil|Absolute=True">Silk To Silk Clearance Constraint: (0.208mm < 0.254mm) Between Arc (52.832mm,60.452mm) on Top Overlay And Text "BAT1" (42.037mm,56.642mm) on Top Overlay Silk Text to Silk Clearance [0.208mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.635mil|Location2.X=2364.885mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.635mil|Location2.X=2364.885mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (59.925mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2385.131mil|Location2.X=2396.381mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2385.131mil|Location2.X=2396.381mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (60.725mm,45.657mm) on Top Overlay And Text "C2" (59.563mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.76mil|Location2.X=2460.01mil|Location1.Y=1810.088mil|Location2.Y=1821.338mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2448.76mil|Location2.X=2460.01mil|Location1.Y=1810.088mil|Location2.Y=1821.338mil|Absolute=True">Silk To Silk Clearance Constraint: (0.05mm < 0.254mm) Between Arc (62.338mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.05mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.499mil|Location2.X=2491.749mil|Location1.Y=1809.76mil|Location2.Y=1821.01mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.499mil|Location2.X=2491.749mil|Location1.Y=1809.76mil|Location2.Y=1821.01mil|Absolute=True">Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Arc (63.138mm,45.657mm) on Top Overlay And Text "C1" (61.976mm,46.228mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2344.887mil|Location2.X=2356.137mil|Location1.Y=3116.992mil|Location2.Y=3128.242mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2344.887mil|Location2.X=2356.137mil|Location1.Y=3116.992mil|Location2.Y=3128.242mil|Absolute=True">Silk To Silk Clearance Constraint: (0.199mm < 0.254mm) Between Text "5V<35><56><EFBFBD><EFBFBD>" (58.039mm,79.502mm) on Top Overlay And Track (42.037mm,79.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0.199mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2347.299mil|Location2.X=2358.549mil|Location1.Y=3586.623mil|Location2.Y=3597.873mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2347.299mil|Location2.X=2358.549mil|Location1.Y=3586.623mil|Location2.Y=3597.873mil|Absolute=True">Silk To Silk Clearance Constraint: (0.18mm < 0.254mm) Between Text "9V<39><56><EFBFBD><EFBFBD>" (58.166mm,91.44mm) on Top Overlay And Track (42.037mm,91.026mm)(62.037mm,91.026mm) on Top Overlay Silk Text to Silk Clearance [0.18mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.25mil|Location2.X=2491.5mil|Location1.Y=1809.763mil|Location2.Y=1821.013mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2480.25mil|Location2.X=2491.5mil|Location1.Y=1809.763mil|Location2.Y=1821.013mil|Absolute=True">Silk To Silk Clearance Constraint: (0.034mm < 0.254mm) Between Text "C1" (61.976mm,46.228mm) on Top Overlay And Track (62.338mm,45.967mm)(63.138mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.034mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2334.363mil|Location2.X=2345.613mil|Location1.Y=1856.863mil|Location2.Y=1868.113mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2334.363mil|Location2.X=2345.613mil|Location1.Y=1856.863mil|Location2.Y=1868.113mil|Absolute=True">Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Text "R2" (57.404mm,46.355mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2353.636mil|Location2.X=2364.886mil|Location1.Y=1812.737mil|Location2.Y=1823.987mil|Absolute=True">Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Text "C2" (59.563mm,46.355mm) on Top Overlay And Track (59.925mm,45.967mm)(60.725mm,45.967mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.398mil|Location2.X=1660.648mil|Location1.Y=1806.873mil|Location2.Y=1818.123mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.398mil|Location2.X=1660.648mil|Location1.Y=1806.873mil|Location2.Y=1818.123mil|Absolute=True">Silk To Silk Clearance Constraint: (0.103mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.216mm,45.783mm)(42.216mm,46.583mm) on Top Overlay Silk Text to Silk Clearance [0.103mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.514mil|Location2.X=1660.764mil|Location1.Y=1866.853mil|Location2.Y=1878.103mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1649.514mil|Location2.X=1660.764mil|Location1.Y=1866.853mil|Location2.Y=1878.103mil|Absolute=True">Silk To Silk Clearance Constraint: (0.109mm < 0.254mm) Between Text "C3" (41.91mm,45.847mm) on Top Overlay And Track (42.222mm,47.159mm)(42.222mm,47.959mm) on Top Overlay Silk Text to Silk Clearance [0.109mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2109.37mil|Location2.X=2120.62mil|Location1.Y=3926.868mil|Location2.Y=3938.118mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2109.37mil|Location2.X=2120.62mil|Location1.Y=3926.868mil|Location2.Y=3938.118mil|Absolute=True">Silk To Silk Clearance Constraint: (0.229mm < 0.254mm) Between Text "G" (53.34mm,98.552mm) on Top Overlay And Text "V" (53.34mm,100.076mm) on Top Overlay Silk Text to Silk Clearance [0.229mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1702.193mil|Location2.X=1713.443mil|Location1.Y=3829.352mil|Location2.Y=3840.602mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1702.193mil|Location2.X=1713.443mil|Location1.Y=3829.352mil|Location2.Y=3840.602mil|Absolute=True">Silk To Silk Clearance Constraint: (0.213mm < 0.254mm) Between Text "J1" (43.18mm,95.885mm) on Top Overlay And Track (43.612mm,93.744mm)(43.612mm,102.344mm) on Top Overlay Silk Text to Silk Clearance [0.213mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2442.132mil|Location2.X=2449.799mil|Location1.Y=2820.234mil|Location2.Y=2827.9mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2442.132mil|Location2.X=2449.799mil|Location1.Y=2820.234mil|Location2.Y=2827.9mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "P1" (60.695mm,71.731mm) on Top Overlay And Track (62.037mm,69.088mm)(62.037mm,79.088mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1669.872mil|Location2.Y=1681.122mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1669.872mil|Location2.Y=1681.122mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (59.989mm,42.571mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1624.375mil|Location2.Y=1635.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2401.64mil|Location2.X=2412.89mil|Location1.Y=1624.375mil|Location2.Y=1635.625mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R1" (61.341mm,41.402mm) on Top Overlay And Track (60.948mm,41.249mm)(60.948mm,42.571mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2284.365mil|Location2.X=2295.615mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2284.365mil|Location2.X=2295.615mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (57.632mm,45.962mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2315.383mil|Location2.X=2326.633mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2315.383mil|Location2.X=2326.633mil|Location1.Y=1811.64mil|Location2.Y=1822.89mil|Absolute=True">Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (57.404mm,46.355mm) on Top Overlay And Track (58.954mm,45.003mm)(58.954mm,45.962mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1603.889mil|Location2.X=1611.556mil|Location1.Y=1663.655mil|Location2.Y=1671.321mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1603.889mil|Location2.X=1611.556mil|Location1.Y=1663.655mil|Location2.Y=1671.321mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(40.906mm,42.825mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1602.097mil|Location2.X=1613.347mil|Location1.Y=1630.12mil|Location2.Y=1642.498mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1602.097mil|Location2.X=1613.347mil|Location1.Y=1630.12mil|Location2.Y=1642.498mil|Absolute=True">Silk To Silk Clearance Constraint: (0.013mm < 0.254mm) Between Text "R3" (38.862mm,41.402mm) on Top Overlay And Track (40.906mm,41.503mm)(41.865mm,41.503mm) on Top Overlay Silk Text to Silk Clearance [0.013mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1606.389mil|Location2.X=1614.056mil|Location1.Y=1718.659mil|Location2.Y=1726.326mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1606.389mil|Location2.X=1614.056mil|Location1.Y=1718.659mil|Location2.Y=1726.326mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(40.906mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.099mil|Location1.Y=1698.367mil|Location2.Y=1709.617mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.099mil|Location1.Y=1698.367mil|Location2.Y=1709.617mil|Absolute=True">Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,43.281mm)(41.865mm,43.281mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.834mil|Location1.Y=1744.872mil|Location2.Y=1756.122mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1600.849mil|Location2.X=1612.834mil|Location1.Y=1744.872mil|Location2.Y=1756.122mil|Absolute=True">Silk To Silk Clearance Constraint: (0.193mm < 0.254mm) Between Text "R4" (38.989mm,43.18mm) on Top Overlay And Track (40.906mm,44.603mm)(41.865mm,44.603mm) on Top Overlay Silk Text to Silk Clearance [0.193mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1868.285mil|Location2.X=1875.951mil|Location1.Y=2046.164mil|Location2.Y=2053.831mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1868.285mil|Location2.X=1875.951mil|Location1.Y=2046.164mil|Location2.Y=2053.831mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,41.764mm)(47.479mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1871.167mil|Location2.X=1878.833mil|Location1.Y=2051.923mil|Location2.Y=2059.589mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1871.167mil|Location2.X=1878.833mil|Location1.Y=2051.923mil|Location2.Y=2059.589mil|Absolute=True">Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (47.625mm,51.88mm) on Top Overlay And Track (47.479mm,52.216mm)(54.121mm,52.216mm) on Top Overlay Silk Text to Silk Clearance [0mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2981.044mil|Location2.X=2992.294mil|Location1.Y=1855.375mil|Location2.Y=1866.625mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\SIF LIGHT\PCB_SIF Light_PCB 20220112_2022-03-24_2022-07-06.pcbdoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=2981.044mil|Location2.X=2992.294mil|Location1.Y=1855.375mil|Location2.Y=1866.625mil|Absolute=True">Silk To Silk Clearance Constraint: (0.051mm < 0.254mm) Between Text "USB" (76.073mm,47.371mm) on Bottom Overlay And Track (71.247mm,47.117mm)(77.597mm,47.117mm) on Bottom Overlay Silk Text to Silk Clearance [0.051mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br></body>
|
||||
</html>
|
||||
BIN
SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar
Normal file
BIN
SIF LIGHT/主板/SIF LIGHT 2022.7.7.rar
Normal file
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BIN
SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc
Normal file
BIN
SIF LIGHT/主板/SIF Light_SCH 20220112_2022-07-06.schdoc
Normal file
Binary file not shown.
BIN
SIF LIGHT/主板/ds18b20.PcbLib
Normal file
BIN
SIF LIGHT/主板/ds18b20.PcbLib
Normal file
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BIN
SIF LIGHT/主板/电源模块.PcbLib
Normal file
BIN
SIF LIGHT/主板/电源模块.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/1.25t-3p.PcbLib
Normal file
BIN
SIF LIGHT/灯板/1.25t-3p.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib
Normal file
BIN
SIF LIGHT/灯板/DS18B20 MSOP8.PcbLib
Normal file
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Binary file not shown.
@ -0,0 +1,175 @@
|
||||
<html>
|
||||
<head>
|
||||
<META http-equiv="Content-Type" content="text/html">
|
||||
<style type="text/css">
|
||||
h1, h2, h3, h4, h5, h6 {
|
||||
font-family : 'segoe-ui',arial,sans-serif;
|
||||
font-size:15pt;
|
||||
font-weight:normal;
|
||||
line-height:40px;
|
||||
color : #000;
|
||||
background-color : #dedede;
|
||||
padding: 0.3em;
|
||||
}
|
||||
body {
|
||||
font-family : verdana;
|
||||
background: #f1f1f1;
|
||||
font-size:13px;
|
||||
}
|
||||
td, th {
|
||||
padding: 0.5em;
|
||||
text-align : left;
|
||||
width: auto;
|
||||
border:1px solid #DEDEDE;
|
||||
}
|
||||
th {
|
||||
background-color : #DEDEDE;
|
||||
|
||||
}
|
||||
th.column1, td.column1 {
|
||||
text-align: left;
|
||||
width : 18%;
|
||||
}
|
||||
table {
|
||||
width : 100%;
|
||||
border-collapse: collapse;
|
||||
font-size:13px;
|
||||
}
|
||||
.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3 {
|
||||
padding-top : 0.1em;
|
||||
padding-bottom : 0.1em;
|
||||
border : 0px solid black;
|
||||
width : auto;
|
||||
vertical-align: top
|
||||
}
|
||||
.front_matter_column1 {
|
||||
text-align : right;
|
||||
}
|
||||
.total_column1, .total_column {
|
||||
font-weight : bold;
|
||||
}
|
||||
.total_column1 {
|
||||
text-align : right;
|
||||
}
|
||||
.front_matter_column2 {
|
||||
text-align : center;
|
||||
}
|
||||
.front_matter_column3 {
|
||||
text-align : left;
|
||||
}
|
||||
.warning, .error {
|
||||
color : red;
|
||||
font-weight : bold;
|
||||
}
|
||||
tr.onmouseout_odd {
|
||||
/*background-color : #EEEEE0 */
|
||||
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|
||||
tr.onmouseout_even {
|
||||
/*background-color : #F3F3E3 */
|
||||
}
|
||||
tr.onmouseover_odd, tr.onmouseover_even {
|
||||
background-color : #FFF;
|
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|
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a:link, a:visited, .q a:link,.q a:active,.q {
|
||||
color: #21489e;
|
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|
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a:link.callback, a:visited.callback {
|
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color: #008000
|
||||
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|
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a:link.customize, a:visited.customize {
|
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|
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right: 16px; top: 30px;
|
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font-family:'segoe ui',arial,tahoma,sans-serif;
|
||||
text-decoration:underline;
|
||||
font-size:11px;
|
||||
color:#0066cc;
|
||||
}
|
||||
p.contents_level1 {
|
||||
font-weight : bold;
|
||||
font-size : 110%;
|
||||
margin : 0.5em;
|
||||
}
|
||||
p.contents_level2 {
|
||||
position : relative;
|
||||
left : 20px;
|
||||
margin : 0.5em;
|
||||
}
|
||||
|
||||
HR{
|
||||
border-collapse:collapse;
|
||||
border:none;
|
||||
border-top:1px solid #dedede;
|
||||
}
|
||||
</style>
|
||||
|
||||
<style type="text/css" media="print">
|
||||
body{
|
||||
background:#fff;
|
||||
}
|
||||
|
||||
a:link.customize{
|
||||
display:none;
|
||||
}
|
||||
|
||||
table,th,td,hr{
|
||||
border-color:#999;
|
||||
background:#fff;
|
||||
}
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
<a href="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General" class="customize"><acronym title="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General">Reporting Options</acronym></a>
|
||||
<h1>File in Previous Format</h1>
|
||||
|
||||
<table class="front_matter">
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Date</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3">2022/7/13</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Time</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3">13:08:06</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Filename</td>
|
||||
<td class="front_matter_column2">:</td>
|
||||
<td class="front_matter_column3"><a href="file://C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc" class="file"><acronym title="C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc">C:\Users\hu123456\Desktop\SIF LIGHT\<5C>ư<EFBFBD>\PCB_PCB_SIF Light _<>ư<EFBFBD> 20220224_2022-03-24_2022-07-13.pcbdoc</acronym></a></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
<br>
|
||||
|
||||
<table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="">Version</th>
|
||||
<th style="text-align : left" colspan="1" class="">Warning</th>
|
||||
</tr>
|
||||
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">6.3</td>
|
||||
<td class="column2"><b>CAUTION</b> - Via connections to both hatched and solid signal layer polygons are now controlled by the polygon connect style rule. Re-pouring polygons may result in physical copper differences.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Summer 09</td>
|
||||
<td class="column2"><b>CAUTION</b> - File contains old violation objects. These violations are no longer supported & will not be loaded. Please run DRC after opening this file in order to refresh the violations.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Summer 09</td>
|
||||
<td class="column2"><b>CAUTION</b> - Existing testpoint rules and settings are used as fabrication testpoint information.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Release 12</td>
|
||||
<td class="column2"><b>CAUTION</b> - Air Gap Width previously controlled by Clearance rule is now controlled by Polygon Connect Style rule's newly introduced Air Gap Width (set to default value). Suggest reviewing each Polygon Connect Style rule's Air Gap Width attribute for correctness.</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1">Release 13</td>
|
||||
<td class="column2"><b>CAUTION</b> - Silkscreen Over Component Pads Rules are converted to Silk To Solder Mask Clearance Rules. Suggest examining rule scopes for accuracy.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<br><hr>
|
||||
<p>This file was generated by <b>an earlier</b> version of the software</p>
|
||||
</body>
|
||||
</html>
|
||||
1124
SIF LIGHT/灯板/PCB_Project1.PrjPCB
Normal file
1124
SIF LIGHT/灯板/PCB_Project1.PrjPCB
Normal file
File diff suppressed because it is too large
Load Diff
1
SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure
Normal file
1
SIF LIGHT/灯板/PCB_Project1.PrjPCBStructure
Normal file
@ -0,0 +1 @@
|
||||
Record=TopLevelDocument|FileName=SIF Light_SCH_<48>ư<EFBFBD> 20220224_2022-07-13.schdoc
|
||||
BIN
SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc
Normal file
BIN
SIF LIGHT/灯板/SIF Light_SCH_灯板 20220224_2022-07-13.schdoc
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/ds18b20.PcbLib
Normal file
BIN
SIF LIGHT/灯板/ds18b20.PcbLib
Normal file
Binary file not shown.
BIN
SIF LIGHT/灯板/pin.PcbLib
Normal file
BIN
SIF LIGHT/灯板/pin.PcbLib
Normal file
Binary file not shown.
BIN
TC300转接板/PCB2.PcbDoc
Normal file
BIN
TC300转接板/PCB2.PcbDoc
Normal file
Binary file not shown.
1110
TC300转接板/PCB_Project2.PrjPCB
Normal file
1110
TC300转接板/PCB_Project2.PrjPCB
Normal file
File diff suppressed because it is too large
Load Diff
1
TC300转接板/PCB_Project2.PrjPCBStructure
Normal file
1
TC300转接板/PCB_Project2.PrjPCBStructure
Normal file
@ -0,0 +1 @@
|
||||
Record=TopLevelDocument|FileName=Sheet2.SchDoc
|
||||
@ -0,0 +1,44 @@
|
||||
Added Component: Designator=P1(HDR1X15)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=P2(HDR1X10)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=D+ Pin=P1-8
|
||||
Added Pin To Net: NetName=D+ Pin=P2-3
|
||||
Added Net: Name=D+
|
||||
Added Pin To Net: NetName=D- Pin=P1-9
|
||||
Added Pin To Net: NetName=D- Pin=P2-2
|
||||
Added Net: Name=D-
|
||||
Added Pin To Net: NetName=GND_DRAIN Pin=P2-8
|
||||
Added Net: Name=GND_DRAIN
|
||||
Added Pin To Net: NetName=GND Pin=P1-1
|
||||
Added Pin To Net: NetName=GND Pin=P1-4
|
||||
Added Pin To Net: NetName=GND Pin=P1-7
|
||||
Added Pin To Net: NetName=GND Pin=P1-10
|
||||
Added Pin To Net: NetName=GND Pin=P2-5
|
||||
Added Net: Name=GND
|
||||
Added Pin To Net: NetName=ID Pin=P2-4
|
||||
Added Net: Name=ID
|
||||
Added Pin To Net: NetName=MicB_SSRX+ Pin=P1-3
|
||||
Added Pin To Net: NetName=MicB_SSRX+ Pin=P2-10
|
||||
Added Net: Name=MicB_SSRX+
|
||||
Added Pin To Net: NetName=MicB_SSRX- Pin=P1-2
|
||||
Added Pin To Net: NetName=MicB_SSRX- Pin=P2-9
|
||||
Added Net: Name=MicB_SSRX-
|
||||
Added Pin To Net: NetName=MicB_SSTX+ Pin=P1-5
|
||||
Added Pin To Net: NetName=MicB_SSTX+ Pin=P2-7
|
||||
Added Net: Name=MicB_SSTX+
|
||||
Added Pin To Net: NetName=MicB_SSTX- Pin=P1-6
|
||||
Added Pin To Net: NetName=MicB_SSTX- Pin=P2-6
|
||||
Added Net: Name=MicB_SSTX-
|
||||
Added Pin To Net: NetName=VBUS Pin=P1-11
|
||||
Added Pin To Net: NetName=VBUS Pin=P1-12
|
||||
Added Pin To Net: NetName=VBUS Pin=P2-1
|
||||
Added Net: Name=VBUS
|
||||
Added Class: Name=Sheet2
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1 @@
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1,3 @@
|
||||
Change Component Footprint: Designator=P2 Old Footprint=HDR1X10 New Footprint=USB3.0
|
||||
Change Component Footprint: Designator=P1 Old Footprint=HDR1X15 New Footprint=fpc15
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1,3 @@
|
||||
Removed Pin From Net: NetName=MicB_SSRX+ Pin=P2-10
|
||||
Added Pin To Net: NetName=MicB_SSRX+ Pin=P2-8
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1,19 @@
|
||||
Added Component: Designator=P1(fpc15)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=P1-1
|
||||
Added Pin To Net: NetName=MicB_SSRX- Pin=P1-2
|
||||
Added Pin To Net: NetName=MicB_SSRX+ Pin=P1-3
|
||||
Added Pin To Net: NetName=GND Pin=P1-4
|
||||
Added Pin To Net: NetName=MicB_SSTX+ Pin=P1-5
|
||||
Added Pin To Net: NetName=MicB_SSTX- Pin=P1-6
|
||||
Added Pin To Net: NetName=GND Pin=P1-7
|
||||
Added Pin To Net: NetName=D+ Pin=P1-8
|
||||
Added Pin To Net: NetName=D- Pin=P1-9
|
||||
Added Pin To Net: NetName=GND Pin=P1-10
|
||||
Added Pin To Net: NetName=VBUS Pin=P1-11
|
||||
Added Pin To Net: NetName=VBUS Pin=P1-12
|
||||
Added Member To Class: ClassName=Sheet2 Member=Component P1 Header 15
|
||||
Added Room: Name=Sheet2
|
||||
@ -0,0 +1,77 @@
|
||||
Protel Design System Design Rule Check
|
||||
PCB File : C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc
|
||||
Date : 2022/7/7
|
||||
Time : 15:09:22
|
||||
|
||||
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Un-Routed Net Constraint ( (All) )
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
|
||||
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-10(94.75mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
|
||||
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-11(83.05mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm
|
||||
Rule Violations :2
|
||||
|
||||
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(86.65mm,67.901mm) on Multi-Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(91.15mm,67.901mm) on Multi-Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-9(92.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-5(84.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Via (88.341mm,67.996mm) from Top Layer to Bottom Layer And Via (88.976mm,67.31mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.231mm] / [Bottom Solder] Mask Sliver [0.231mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (89.865mm,81.91mm) from Top Layer to Bottom Layer And Via (90.297mm,81.102mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]
|
||||
Rule Violations :12
|
||||
|
||||
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-1(85.139mm,78.959mm) on Top Layer And Track (82.639mm,78.996mm)(84.639mm,78.996mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-15(92.139mm,78.959mm) on Top Layer And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,78.996mm)(82.639mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.959mm)(82.639mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.997mm)(82.639mm,82.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.587mm,82.959mm)(94.587mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad P2-5(84.9mm,70.101mm) on Top Layer And Track (83.058mm,70.101mm)(84.328mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.095mm < 0.254mm) Between Pad P2-9(92.9mm,70.101mm) on Top Layer And Track (93.472mm,70.101mm)(94.742mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.095mm]
|
||||
Rule Violations :9
|
||||
|
||||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||||
Violation between Silk To Silk Clearance Constraint: (0.17mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay Silk Text to Silk Clearance [0.17mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.197mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay Silk Text to Silk Clearance [0.197mm]
|
||||
Rule Violations :2
|
||||
|
||||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Matched Lengths(Tolerance=25.4mm) (All)
|
||||
Violation between Matched Net Lengths: Between Net GND And Net ID Length:0mm is not within 25.4mm tolerance of Length:28.32mm (2.92mm short)
|
||||
Rule Violations :1
|
||||
|
||||
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
|
||||
Violations Detected : 26
|
||||
Waived Violations : 0
|
||||
Time Elapsed : 00:00:01
|
||||
@ -0,0 +1,426 @@
|
||||
<html>
|
||||
<head>
|
||||
<META http-equiv="Content-Type" content="text/html">
|
||||
<style type="text/css">
|
||||
h1, h2, h3, h4, h5, h6 {
|
||||
font-family : segoe ui;
|
||||
color : black;
|
||||
background-color : #EDE7D9;
|
||||
padding: 0.3em;
|
||||
}
|
||||
|
||||
h1 {
|
||||
font-size: 1.2em;
|
||||
}
|
||||
|
||||
h2 {
|
||||
font-size: 1.2em;
|
||||
}
|
||||
|
||||
body {
|
||||
font-family : segoe ui;
|
||||
}
|
||||
|
||||
td, th {
|
||||
padding: 0.5em;
|
||||
text-align : left;
|
||||
width: 10em;
|
||||
}
|
||||
th {
|
||||
background-color : #EEEEEE;
|
||||
|
||||
}
|
||||
th.column1, td.column1 {
|
||||
text-align: left;
|
||||
width : auto;
|
||||
}
|
||||
table {
|
||||
width : 100%;
|
||||
font-size: 0.9em;
|
||||
}
|
||||
|
||||
.DRC_summary_header {
|
||||
padding-bottom : 0.1em;
|
||||
border : 0px solid black;
|
||||
width: 100%;
|
||||
align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1,
|
||||
.DRC_summary_header_col2,
|
||||
.DRC_summary_header_col3 {
|
||||
color : black;
|
||||
font-size:100%;
|
||||
padding : 0em;
|
||||
padding-top : 0.2em;
|
||||
padding-bottom 0.2em;
|
||||
border : 0px solid black;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col1 {
|
||||
font-weight: bold;
|
||||
width: 8em;
|
||||
}
|
||||
|
||||
.DRC_summary_header_col2 {
|
||||
width: 0.1em;
|
||||
|
||||
}
|
||||
|
||||
.DRC_summary_header_col3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.header_holder {
|
||||
Width = 100%;
|
||||
border = 0px solid green;
|
||||
padding = 0;
|
||||
}
|
||||
|
||||
|
||||
.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3
|
||||
{
|
||||
left : 0;
|
||||
top : 0;
|
||||
padding: 0em;
|
||||
padding-top : 0.1em;
|
||||
border : 0px solid black;
|
||||
width : 100%;
|
||||
vertical-align: top;
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
.front_matter_column1 {
|
||||
width : 8em;
|
||||
font-weight: bold;
|
||||
}
|
||||
|
||||
.front_matter_column2 {
|
||||
width: 0.1em;
|
||||
}
|
||||
|
||||
.front_matter_column3 {
|
||||
width : auto;
|
||||
}
|
||||
|
||||
.total_column1, .total_column {
|
||||
font-weight : bold;
|
||||
}
|
||||
.total_column1 {
|
||||
text-align : left;
|
||||
}
|
||||
.warning, .error {
|
||||
color : red;
|
||||
font-weight : bold;
|
||||
}
|
||||
tr.onmouseout_odd {
|
||||
background-color : #white;
|
||||
}
|
||||
tr.onmouseout_even {
|
||||
background-color : #FAFAFA;
|
||||
}
|
||||
tr.onmouseover_odd, tr.onmouseover_even {
|
||||
background-color : #EEEEEE;
|
||||
}
|
||||
a:link, a:visited, .q a:link,.q a:active,.q {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.callback, a:visited.callback {
|
||||
color: #21489e;
|
||||
}
|
||||
a:link.customize, a:visited.customize {
|
||||
color: #C0C0C0;
|
||||
position: absolute;
|
||||
right: 10px;
|
||||
}
|
||||
p.contents_level1 {
|
||||
font-weight : bold;
|
||||
font-size : 110%;
|
||||
margin : 0.5em;
|
||||
}
|
||||
p.contents_level2 {
|
||||
position : relative;
|
||||
left : 20px;
|
||||
margin : 0.5em;
|
||||
}
|
||||
</style><script type="text/javascript">
|
||||
function coordToMils(coord) {
|
||||
var number = coord / 10000;
|
||||
|
||||
if (number != number.toFixed(3))
|
||||
number = number.toFixed(3);
|
||||
|
||||
return number + 'mil'
|
||||
}
|
||||
|
||||
function coordToMM(coord) {
|
||||
var number = 0.0254 * coord / 10000;
|
||||
|
||||
if (number != number.toFixed(4))
|
||||
number = number.toFixed(4);
|
||||
|
||||
return number + 'mm'
|
||||
}
|
||||
|
||||
function convertCoord(coordNode, units) {
|
||||
for (var i = 0; i < coordNode.childNodes.length; i++) {
|
||||
coordNode.removeChild(coordNode.childNodes[i]);
|
||||
}
|
||||
|
||||
var coord = coordNode.getAttribute('value');
|
||||
if (coord != null) {
|
||||
if (units == 'mm') {
|
||||
textNode = document.createTextNode(coordToMM(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
} else if (units == 'mil') {
|
||||
textNode = document.createTextNode(coordToMils(coord));
|
||||
coordNode.appendChild(textNode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
function convertUnits(unitNode, units) {
|
||||
for (var i = 0; i < unitNode.childNodes.length; i++) {
|
||||
unitNode.removeChild(unitNode.childNodes[i]);
|
||||
}
|
||||
|
||||
textNode = document.createTextNode(units);
|
||||
unitNode.appendChild(textNode);
|
||||
}
|
||||
|
||||
function changeUnits(radio_input, units) {
|
||||
if (radio_input.checked) {
|
||||
|
||||
var elements = document.getElementsByName('coordinate');
|
||||
if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
||||
convertCoord(elements[i], units);
|
||||
}
|
||||
}
|
||||
|
||||
var elements = document.getElementsByName('units');
|
||||
if (elements) {
|
||||
for (var i = 0; i < elements.length; i++) {
|
||||
convertUnits(elements[i], units);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
</script><title>Design Rule Verification Report</title>
|
||||
</head>
|
||||
<body onload=""><img ALT="Altium" src="
|
||||
file://C:\Users\Public\Documents\Altium\AD18\Templates\AD_logo.png
|
||||
"><h1>Design Rule Verification Report</h1>
|
||||
<table class="header_holder">
|
||||
<td class="column1">
|
||||
<table class="front_matter">
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Date:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">2022/7/7</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">15:09:22</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Elapsed Time:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3">00:00:01</td>
|
||||
</tr>
|
||||
<tr class="front_matter">
|
||||
<td class="front_matter_column1">Filename:</td>
|
||||
<td class="front_matter_column2"></td>
|
||||
<td class="front_matter_column3"><a href="file:///C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc" class="file"><acronym title="C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc">C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc</acronym></a></td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
<td class="column2">
|
||||
<table class="DRC_summary_header">
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Warnings:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3">0</td></tr>
|
||||
<tr>
|
||||
<td class="DRC_summary_header_col1">Rule Violations:</td>
|
||||
<td class="DRC_summary_header_col2"></td>
|
||||
<td class="DRC_summary_header_col3" style="color : red">26</td></tr>
|
||||
</table>
|
||||
</td>
|
||||
</table><a name="IDKAKOKIJR5AU0CHZXXY1HYC1DWGCPFWHHVTMTCXMSF4SYG3FM4KEM"><h2>Summary</h2></a><table>
|
||||
<tr>
|
||||
<th class="column1">Warnings</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">0</td>
|
||||
</tr>
|
||||
</table><br><table>
|
||||
<tr>
|
||||
<th class="column1">Rule Violations</th>
|
||||
<th class="column2">Count</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDZRD2XEIRQSMNIUBCU4GXT4DPYM24KGLVRP0LIZLVY0O30FLWUDM">Clearance Constraint (Gap=0.2mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDHF5JWXB4TJL3MQMLJFCQDHSXRJ5LPUTUL0S241PKTTAADBQ4TN4D">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDWBLTTNAZCPJ4KJGIMN1LW2UDLKYWVWPUQ13CMJFLUHJNGEZEPMTG">Un-Routed Net Constraint ( (All) )</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID1XY03G2U51I3J3NJLC0WZEXMZMJEVCJP1KK2PMOOSKF4Z3YPPI3N">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDRFBVGSZGBEENNPKZH01KI35MUGW4JSUUYAKKBSIGW4LFP3YUIMCP">Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#ID0PVK51UVAMUDNUQP2YSVJLUJ5L3LBXKXNMLVD1KSCJOUO4RW5KID">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDWNJSFRBGDT4VIRNMJVHGXFUYMXBNMEOW0MPAXGU3CYKWUARBMIN">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</a></td>
|
||||
<td class="column2">2</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDF4NS2GYJR5XFPESUTL2OOS3NWGNKUXENLGXQMMGARISGRTJUCEQP">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#ID2MVDPBHLD3ASMMIXNKN5Q5W2NF5FCNZ5FICNOCIZ13QZME2WZEFD">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">12</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDA1L0OPA0OZ3TBY4IR0JXSOVLBPSFEHOOWXWXRJDKNJYDUKNTB1KL">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</a></td>
|
||||
<td class="column2">9</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDXEAA2BZHBKWUMR1YDHG1DBOGQCMDIYFWVQNUE4XPQF1H3EIQFSC">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
|
||||
<td class="column2">2</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDZ0DB1BY1IQ2INNUMFYYSSHEJ4GGN5NM04VEYEAEEBKQ3B50PGNTM">Net Antennae (Tolerance=0mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="#IDMOUOOUULVCEHKWFN5EMNTCPJGLK5CFMJPD4X55DQQTRQRNJ4RNG">Matched Lengths(Tolerance=25.4mm) (All)</a></td>
|
||||
<td class="column2">1</td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="#IDCFKVGH1NLQZRENI2IEFA0TYKVHKIZFS3P343REPHIROE2NVQE20I">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
|
||||
<td class="column2">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
|
||||
<td style="font-weight : bold" class="column2">26</td>
|
||||
</tr>
|
||||
</table><br><a name="IDWNJSFRBGDT4VIRNMJVHGXFUYMXBNMEOW0MPAXGU3CYKWUARBMIN"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3676.53mil|Location2.X=3784.08mil|Location1.Y=2619.495mil|Location2.Y=2727.045mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3676.53mil|Location2.X=3784.08mil|Location1.Y=2619.495mil|Location2.Y=2727.045mil|Absolute=True">Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-10(94.75mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3215.901mil|Location2.X=3323.451mil|Location1.Y=2619.495mil|Location2.Y=2727.045mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3215.901mil|Location2.X=3323.451mil|Location1.Y=2619.495mil|Location2.Y=2727.045mil|Absolute=True">Hole Size Constraint: (2.7mm > 2.54mm) Pad P2-11(83.05mm,67.901mm) on Multi-Layer Actual Slot Hole Width = 2.7mm</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="ID2MVDPBHLD3ASMMIXNKN5Q5W2NF5FCNZ5FICNOCIZ13QZME2WZEFD"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3405.795mil|Location2.X=3417.045mil|Location1.Y=2700.122mil|Location2.Y=2711.372mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3405.795mil|Location2.X=3417.045mil|Location1.Y=2700.122mil|Location2.Y=2711.372mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(86.65mm,67.901mm) on Multi-Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3582.955mil|Location2.X=3594.205mil|Location1.Y=2700.122mil|Location2.Y=2711.372mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3582.955mil|Location2.X=3594.205mil|Location1.Y=2700.122mil|Location2.Y=2711.372mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad P2-(91.15mm,67.901mm) on Multi-Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3592.79mil|Location2.X=3604.04mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3592.79mil|Location2.X=3604.04mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3632.16mil|Location2.X=3643.41mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3632.16mil|Location2.X=3643.41mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-1(91.9mm,70.101mm) on Top Layer And Pad P2-9(92.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3514.05mil|Location2.X=3525.3mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3514.05mil|Location2.X=3525.3mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3553.42mil|Location2.X=3564.67mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3553.42mil|Location2.X=3564.67mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-2(89.9mm,70.101mm) on Top Layer And Pad P2-8(90.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3435.31mil|Location2.X=3446.56mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3435.31mil|Location2.X=3446.56mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3474.68mil|Location2.X=3485.93mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3474.68mil|Location2.X=3485.93mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-3(87.9mm,70.101mm) on Top Layer And Pad P2-7(88.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3356.57mil|Location2.X=3367.82mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3356.57mil|Location2.X=3367.82mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-5(84.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3395.94mil|Location2.X=3407.19mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3395.94mil|Location2.X=3407.19mil|Location1.Y=2704.984mil|Location2.Y=2716.234mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad P2-4(85.9mm,70.101mm) on Top Layer And Pad P2-6(86.9mm,70.101mm) on Top Layer [Top Solder] Mask Sliver [0.097mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3484.875mil|Location2.X=3496.125mil|Location1.Y=2657.875mil|Location2.Y=2669.125mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3484.875mil|Location2.X=3496.125mil|Location1.Y=2657.875mil|Location2.Y=2669.125mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Via (88.341mm,67.996mm) from Top Layer to Bottom Layer And Via (88.976mm,67.31mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.231mm] / [Bottom Solder] Mask Sliver [0.231mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3540.875mil|Location2.X=3553.656mil|Location1.Y=3203.285mil|Location2.Y=3214.535mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3540.875mil|Location2.X=3553.656mil|Location1.Y=3203.285mil|Location2.Y=3214.535mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.213mm < 0.254mm) Between Via (89.865mm,81.91mm) from Top Layer to Bottom Layer And Via (90.297mm,81.102mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.213mm] / [Bottom Solder] Mask Sliver [0.213mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDA1L0OPA0OZ3TBY4IR0JXSOVLBPSFEHOOWXWXRJDKNJYDUKNTB1KL"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3336.003mil|Location2.X=3347.253mil|Location1.Y=3104.473mil|Location2.Y=3115.723mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3336.003mil|Location2.X=3347.253mil|Location1.Y=3104.473mil|Location2.Y=3115.723mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-1(85.139mm,78.959mm) on Top Layer And Track (82.639mm,78.996mm)(84.639mm,78.996mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3632.191mil|Location2.X=3643.441mil|Location1.Y=3103.036mil|Location2.Y=3114.286mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3632.191mil|Location2.X=3643.441mil|Location1.Y=3103.036mil|Location2.Y=3114.286mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad P1-15(92.139mm,78.959mm) on Top Layer And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.872mil|Location2.X=3259.122mil|Location1.Y=3153.112mil|Location2.Y=3164.362mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.872mil|Location2.X=3259.122mil|Location1.Y=3153.112mil|Location2.Y=3164.362mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,78.996mm)(82.639mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.104mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.887mil|Location2.X=3259.137mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.887mil|Location2.X=3259.137mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.959mm)(82.639mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.887mil|Location2.X=3259.137mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3247.887mil|Location2.X=3259.137mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-16(83.439mm,81.534mm) on Top Layer And Track (82.639mm,82.997mm)(82.639mm,82.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3718.287mil|Location2.X=3729.537mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3718.287mil|Location2.X=3729.537mil|Location1.Y=3254.542mil|Location2.Y=3265.792mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.048mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.587mm,82.959mm)(94.587mm,84.958mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.048mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3725.873mil|Location2.X=3737.206mil|Location1.Y=3152.5mil|Location2.Y=3163.75mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3725.873mil|Location2.X=3737.206mil|Location1.Y=3152.5mil|Location2.Y=3163.75mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad P1-17(93.839mm,81.534mm) on Top Layer And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3321.248mil|Location2.X=3332.498mil|Location1.Y=2754.244mil|Location2.Y=2765.494mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3321.248mil|Location2.X=3332.498mil|Location1.Y=2754.244mil|Location2.Y=2765.494mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.094mm < 0.254mm) Between Pad P2-5(84.9mm,70.101mm) on Top Layer And Track (83.058mm,70.101mm)(84.328mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.094mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3667.495mil|Location2.X=3678.745mil|Location1.Y=2754.259mil|Location2.Y=2765.509mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3667.495mil|Location2.X=3678.745mil|Location1.Y=2754.259mil|Location2.Y=2765.509mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.095mm < 0.254mm) Between Pad P2-9(92.9mm,70.101mm) on Top Layer And Track (93.472mm,70.101mm)(94.742mm,70.101mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.095mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDXEAA2BZHBKWUMR1YDHG1DBOGQCMDIYFWVQNUE4XPQF1H3EIQFSC"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Silk to Silk (Clearance=0.254mm) (All),(All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3656.375mil|Location2.X=3667.625mil|Location1.Y=3094.696mil|Location2.Y=3105.946mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3656.375mil|Location2.X=3667.625mil|Location1.Y=3094.696mil|Location2.Y=3105.946mil|Absolute=True">Silk To Silk Clearance Constraint: (0.17mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (92.639mm,78.96mm)(94.638mm,78.96mm) on Top Overlay Silk Text to Silk Clearance [0.17mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3723.319mil|Location2.X=3736.746mil|Location1.Y=3094.696mil|Location2.Y=3105.946mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3723.319mil|Location2.X=3736.746mil|Location1.Y=3094.696mil|Location2.Y=3105.946mil|Absolute=True">Silk To Silk Clearance Constraint: (0.197mm < 0.254mm) Between Text "P1" (93.015mm,77.013mm) on Top Overlay And Track (94.638mm,78.96mm)(94.638mm,80.053mm) on Top Overlay Silk Text to Silk Clearance [0.197mm]</acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDMOUOOUULVCEHKWFN5EMNTCPJGLK5CFMJPD4X55DQQTRQRNJ4RNG"><table>
|
||||
<tr>
|
||||
<th style="text-align : left" colspan="1" class="rule">Matched Lengths(Tolerance=25.4mm) (All)</th>
|
||||
</tr>
|
||||
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
|
||||
<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300%E8%BD%AC%E6%8E%A5%E6%9D%BF\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3324.731mil|Location2.X=3608mil|Location1.Y=2710.609mil|Location2.Y=3265mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\hu123456\Desktop\TC300ת<30>Ӱ<EFBFBD>\PCB2.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=3324.731mil|Location2.X=3608mil|Location1.Y=2710.609mil|Location2.Y=3265mil|Absolute=True">Matched Net Lengths: Between Net GND And Net ID Length:0mm is not within 25.4mm tolerance of Length:28.32mm (2.92mm short) </acronym></a><br></td>
|
||||
</tr>
|
||||
</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br></body>
|
||||
</html>
|
||||
BIN
TC300转接板/Schlib1.SchLib
Normal file
BIN
TC300转接板/Schlib1.SchLib
Normal file
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BIN
TC300转接板/Sheet2.SchDoc
Normal file
BIN
TC300转接板/Sheet2.SchDoc
Normal file
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BIN
TC300转接板/TC300转接板2022.7.7.rar
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BIN
TC300转接板/TC300转接板2022.7.7.rar
Normal file
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BIN
TC300转接板/USB3.0.PcbLib
Normal file
BIN
TC300转接板/USB3.0.PcbLib
Normal file
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BIN
TC300转接板/fpc15.PcbLib
Normal file
BIN
TC300转接板/fpc15.PcbLib
Normal file
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BIN
optower/PCB_optoTower 改版HU20220304_2022-07-07.pcbdoc
Normal file
BIN
optower/PCB_optoTower 改版HU20220304_2022-07-07.pcbdoc
Normal file
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BIN
optower/PCB_optoTower优化2022.7.7.rar
Normal file
BIN
optower/PCB_optoTower优化2022.7.7.rar
Normal file
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BIN
使用时间监测模块/0603.PcbLib
Normal file
BIN
使用时间监测模块/0603.PcbLib
Normal file
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BIN
使用时间监测模块/117.PcbLib
Normal file
BIN
使用时间监测模块/117.PcbLib
Normal file
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BIN
使用时间监测模块/1N4001W.PcbLib
Normal file
BIN
使用时间监测模块/1N4001W.PcbLib
Normal file
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BIN
使用时间监测模块/CNJMA2001WR-S-2P.PcbLib
Normal file
BIN
使用时间监测模块/CNJMA2001WR-S-2P.PcbLib
Normal file
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BIN
使用时间监测模块/FC-135.PcbLib
Normal file
BIN
使用时间监测模块/FC-135.PcbLib
Normal file
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BIN
使用时间监测模块/GS2040AR-CR.PcbLib
Normal file
BIN
使用时间监测模块/GS2040AR-CR.PcbLib
Normal file
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BIN
使用时间监测模块/MAX40200AUK+T.PcbLib
Normal file
BIN
使用时间监测模块/MAX40200AUK+T.PcbLib
Normal file
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BIN
使用时间监测模块/PCB1.PcbDoc
Normal file
BIN
使用时间监测模块/PCB1.PcbDoc
Normal file
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1300
使用时间监测模块/PCB_Project2.PrjPCB
Normal file
1300
使用时间监测模块/PCB_Project2.PrjPCB
Normal file
File diff suppressed because it is too large
Load Diff
1
使用时间监测模块/PCB_Project2.PrjPCBStructure
Normal file
1
使用时间监测模块/PCB_Project2.PrjPCBStructure
Normal file
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|
||||
Record=TopLevelDocument|FileName=Sheet1.SchDoc
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||||
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||||
Added Component: Designator=C2(RAD-0.3)
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||||
Add component. Clean all parameters for all variants
|
||||
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|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
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|
||||
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|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "0.1<EFBFBD><EFBFBD>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C3(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1<><31>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C4(C0805)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Chip Capacitor"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "C0805"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "100<30><30>F"; VariantName = "[No Variations]"
|
||||
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||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
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|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
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|
||||
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||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "3pF"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C7(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "3pF"; VariantName = "[No Variations]"
|
||||
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|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
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|
||||
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|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
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|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
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|
||||
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||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
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|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
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|
||||
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||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1<><31>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C12(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "2.2<EFBFBD><EFBFBD>F"; VariantName = "[No Variations]"
|
||||
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|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "0.1<EFBFBD><EFBFBD>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C14(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "22<32><32>F/10V"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=D?(SMC)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=P1(HDR1X2)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=P2(HDR1X3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=Q?(SOT-23B_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=Q?(SOT-23B_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=Q?(SOT-23B_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=Q?(SOT-23B_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "29-May-2009"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "IPC-7351 Footprint Added."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "3-Pin SOT-23 Package 0.95 mm Pitch, 2.4 mm Lead Span"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SOT-23B"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Aug-1999"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R3(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "69.8K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R4(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "22.1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R5(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R6(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R7(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R8(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R9(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R10(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R11(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R12(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R13(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R14(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R15(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R16(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R17(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R18(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R19(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R20(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=Y?(R38)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Crystal, Thru-Hole; 2 Leads; Body 3.1 x 8.2 mm (Dia.xH)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "R38"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+3.3 Pin=C2-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=C3-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C4-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=C5-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C8-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=D?-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q?-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q?-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q?-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q?-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=R6-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=R8-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=R10-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=R12-2
|
||||
Added Net: Name=+3.3
|
||||
Added Pin To Net: NetName=3.3V Pin=C9-2
|
||||
Added Pin To Net: NetName=3.3V Pin=C10-2
|
||||
Added Pin To Net: NetName=3.3V Pin=C11-1
|
||||
Added Net: Name=3.3V
|
||||
Added Net: Name=EN
|
||||
Added Pin To Net: NetName=GND1 Pin=C2-2
|
||||
Added Pin To Net: NetName=GND1 Pin=C3-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C4-2
|
||||
Added Pin To Net: NetName=GND1 Pin=C5-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C6-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C7-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C8-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C9-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C10-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C11-2
|
||||
Added Pin To Net: NetName=GND1 Pin=C12-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C14-1
|
||||
Added Pin To Net: NetName=GND1 Pin=P1-2
|
||||
Added Pin To Net: NetName=GND1 Pin=P2-3
|
||||
Added Pin To Net: NetName=GND1 Pin=R4-2
|
||||
Added Net: Name=GND1
|
||||
Added Net: Name=IO0
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=C14-2
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=D?-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=R3-1
|
||||
Added Net: Name=IO34 ADC
|
||||
Added Pin To Net: NetName=LED A Pin=R13-1
|
||||
Added Net: Name=LED A
|
||||
Added Pin To Net: NetName=LED B Pin=R14-1
|
||||
Added Net: Name=LED B
|
||||
Added Pin To Net: NetName=LED C Pin=R15-1
|
||||
Added Net: Name=LED C
|
||||
Added Pin To Net: NetName=LED DP Pin=R20-1
|
||||
Added Net: Name=LED DP
|
||||
Added Pin To Net: NetName=LED D Pin=R16-1
|
||||
Added Net: Name=LED D
|
||||
Added Pin To Net: NetName=LED E Pin=R17-1
|
||||
Added Net: Name=LED E
|
||||
Added Pin To Net: NetName=LED F Pin=R18-1
|
||||
Added Net: Name=LED F
|
||||
Added Pin To Net: NetName=LED G Pin=R19-1
|
||||
Added Net: Name=LED G
|
||||
Added Pin To Net: NetName=LED H1 Pin=R5-2
|
||||
Added Net: Name=LED H1
|
||||
Added Pin To Net: NetName=LED H2 Pin=R7-1
|
||||
Added Net: Name=LED H2
|
||||
Added Pin To Net: NetName=LED H3 Pin=R9-2
|
||||
Added Net: Name=LED H3
|
||||
Added Pin To Net: NetName=LED H4 Pin=R11-1
|
||||
Added Net: Name=LED H4
|
||||
Added Pin To Net: NetName=NetC6_2 Pin=C6-2
|
||||
Added Pin To Net: NetName=NetC6_2 Pin=Y?-1
|
||||
Added Net: Name=NetC6_2
|
||||
Added Pin To Net: NetName=NetC7_2 Pin=C7-2
|
||||
Added Pin To Net: NetName=NetC7_2 Pin=Y?-2
|
||||
Added Net: Name=NetC7_2
|
||||
Added Pin To Net: NetName=NetC12_2 Pin=C12-2
|
||||
Added Pin To Net: NetName=NetC12_2 Pin=P1-1
|
||||
Added Net: Name=NetC12_2
|
||||
Added Pin To Net: NetName=NetC13_1 Pin=C13-1
|
||||
Added Net: Name=NetC13_1
|
||||
Added Pin To Net: NetName=NetC13_2 Pin=C13-2
|
||||
Added Net: Name=NetC13_2
|
||||
Added Pin To Net: NetName=NetQ?_1 Pin=Q?-1
|
||||
Added Net: Name=NetQ?_1
|
||||
Added Pin To Net: NetName=NetQ?_2 Pin=Q?-2
|
||||
Added Pin To Net: NetName=NetQ?_2 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetQ?_2 Pin=R6-1
|
||||
Added Net: Name=NetQ?_2
|
||||
Added Pin To Net: NetName=NetR3_2 Pin=R3-2
|
||||
Added Pin To Net: NetName=NetR3_2 Pin=R4-1
|
||||
Added Net: Name=NetR3_2
|
||||
Added Pin To Net: NetName=NetR13_2 Pin=R13-2
|
||||
Added Net: Name=NetR13_2
|
||||
Added Pin To Net: NetName=NetR14_2 Pin=R14-2
|
||||
Added Net: Name=NetR14_2
|
||||
Added Pin To Net: NetName=NetR15_2 Pin=R15-2
|
||||
Added Net: Name=NetR15_2
|
||||
Added Pin To Net: NetName=NetR16_2 Pin=R16-2
|
||||
Added Net: Name=NetR16_2
|
||||
Added Pin To Net: NetName=NetR17_2 Pin=R17-2
|
||||
Added Net: Name=NetR17_2
|
||||
Added Pin To Net: NetName=NetR18_2 Pin=R18-2
|
||||
Added Net: Name=NetR18_2
|
||||
Added Pin To Net: NetName=NetR19_2 Pin=R19-2
|
||||
Added Net: Name=NetR19_2
|
||||
Added Pin To Net: NetName=NetR20_2 Pin=R20-2
|
||||
Added Net: Name=NetR20_2
|
||||
Added Pin To Net: NetName=U0RXD Pin=P2-2
|
||||
Added Net: Name=U0RXD
|
||||
Added Pin To Net: NetName=U0TXD Pin=P2-1
|
||||
Added Net: Name=U0TXD
|
||||
Added Class: Name=Sheet1
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,29 @@
|
||||
Change Component Designator: OldDesignator=Q? NewDesignator=Q1
|
||||
Change Component Designator: OldDesignator=Q? NewDesignator=Q2
|
||||
Change Component Designator: OldDesignator=Q? NewDesignator=Q3
|
||||
Change Component Designator: OldDesignator=Q? NewDesignator=Q4
|
||||
Change Net Name : Old Net Name=NetQ?_2 New Net Name=NetQ1_2
|
||||
Added Pin To Net: NetName=NetQ1_1 Pin=Q1-1
|
||||
Added Net: Name=NetQ1_1
|
||||
Added Pin To Net: NetName=NetQ2_1 Pin=Q2-1
|
||||
Added Net: Name=NetQ2_1
|
||||
Added Pin To Net: NetName=NetQ2_2 Pin=Q2-2
|
||||
Added Pin To Net: NetName=NetQ2_2 Pin=R7-2
|
||||
Added Pin To Net: NetName=NetQ2_2 Pin=R8-2
|
||||
Added Net: Name=NetQ2_2
|
||||
Added Pin To Net: NetName=NetQ3_1 Pin=Q3-1
|
||||
Added Net: Name=NetQ3_1
|
||||
Added Pin To Net: NetName=NetQ3_2 Pin=Q3-2
|
||||
Added Pin To Net: NetName=NetQ3_2 Pin=R9-1
|
||||
Added Pin To Net: NetName=NetQ3_2 Pin=R10-1
|
||||
Added Net: Name=NetQ3_2
|
||||
Added Pin To Net: NetName=NetQ4_1 Pin=Q4-1
|
||||
Added Net: Name=NetQ4_1
|
||||
Added Pin To Net: NetName=NetQ4_2 Pin=Q4-2
|
||||
Added Pin To Net: NetName=NetQ4_2 Pin=R11-2
|
||||
Added Pin To Net: NetName=NetQ4_2 Pin=R12-1
|
||||
Added Net: Name=NetQ4_2
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component Q2 PNP
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component Q3 PNP
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component Q4 PNP
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,50 @@
|
||||
Change Component Footprint: Designator=C2 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C3 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C5 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C6 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C7 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C8 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C9 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C10 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=C11 Old Footprint=RAD-0.3 New Footprint=0402
|
||||
Added Component: Designator=U1(esp32-pico-d4)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-4
|
||||
Added Pin To Net: NetName=EN Pin=U1-9
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=U1-10
|
||||
Added Pin To Net: NetName=NetC6_2 Pin=U1-12
|
||||
Added Pin To Net: NetName=NetC7_2 Pin=U1-13
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-19
|
||||
Added Pin To Net: NetName=GND1 Pin=U1-22
|
||||
Added Pin To Net: NetName=IO0 Pin=U1-23
|
||||
Added Pin To Net: NetName=LED DP Pin=U1-27
|
||||
Added Pin To Net: NetName=LED G Pin=U1-28
|
||||
Added Pin To Net: NetName=LED F Pin=U1-29
|
||||
Added Pin To Net: NetName=LED E Pin=U1-30
|
||||
Added Pin To Net: NetName=LED D Pin=U1-31
|
||||
Added Pin To Net: NetName=LED C Pin=U1-32
|
||||
Added Pin To Net: NetName=LED B Pin=U1-33
|
||||
Added Pin To Net: NetName=LED A Pin=U1-34
|
||||
Added Pin To Net: NetName=LED H4 Pin=U1-35
|
||||
Added Pin To Net: NetName=LED H3 Pin=U1-36
|
||||
Added Pin To Net: NetName=3.3V Pin=U1-37
|
||||
Added Pin To Net: NetName=LED H2 Pin=U1-38
|
||||
Added Pin To Net: NetName=LED H1 Pin=U1-39
|
||||
Added Pin To Net: NetName=U0RXD Pin=U1-40
|
||||
Added Pin To Net: NetName=U0TXD Pin=U1-41
|
||||
Added Pin To Net: NetName=3.3V Pin=U1-43
|
||||
Added Pin To Net: NetName=3.3V Pin=U1-46
|
||||
Added Pin To Net: NetName=GND1 Pin=U1-49
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,16 @@
|
||||
Added Component: Designator=U3(GS2040AR-CR)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=NetR17_2 Pin=U3-1
|
||||
Added Pin To Net: NetName=NetR16_2 Pin=U3-2
|
||||
Added Pin To Net: NetName=NetR20_2 Pin=U3-3
|
||||
Added Pin To Net: NetName=NetR15_2 Pin=U3-4
|
||||
Added Pin To Net: NetName=NetR19_2 Pin=U3-5
|
||||
Added Pin To Net: NetName=NetQ1_1 Pin=U3-6
|
||||
Added Pin To Net: NetName=NetR14_2 Pin=U3-7
|
||||
Added Pin To Net: NetName=NetQ2_1 Pin=U3-8
|
||||
Added Pin To Net: NetName=NetQ3_1 Pin=U3-9
|
||||
Added Pin To Net: NetName=NetR18_2 Pin=U3-10
|
||||
Added Pin To Net: NetName=NetR13_2 Pin=U3-11
|
||||
Added Pin To Net: NetName=NetQ4_1 Pin=U3-12
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U3
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,2 @@
|
||||
Change Component Footprint: Designator=Y? Old Footprint=R38 New Footprint=FC-135
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,2 @@
|
||||
Change Component Footprint: Designator=C4 Old Footprint=C0805 New Footprint=DIODE_SMC
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,53 @@
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q1-3
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q2-3
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q3-3
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q4-3
|
||||
Removed Pin From Net: NetName=NetQ1_1 Pin=U3-6
|
||||
Removed Pin From Net: NetName=NetQ2_1 Pin=U3-8
|
||||
Removed Pin From Net: NetName=NetQ3_1 Pin=U3-9
|
||||
Removed Pin From Net: NetName=NetQ4_1 Pin=U3-12
|
||||
Change Component Footprint: Designator=R5 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R6 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R7 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R8 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R9 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R10 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R11 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R12 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R13 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R14 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R15 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R16 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R17 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R18 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R19 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=R20 Old Footprint=AXIAL-0.3 New Footprint=0402
|
||||
Change Component Footprint: Designator=Q1 Old Footprint=SOT-23B_N New Footprint=s8550
|
||||
Change Component Footprint: Designator=Q2 Old Footprint=SOT-23B_N New Footprint=s8550
|
||||
Change Component Footprint: Designator=Q3 Old Footprint=SOT-23B_N New Footprint=s8550
|
||||
Change Component Footprint: Designator=Q4 Old Footprint=SOT-23B_N New Footprint=s8550
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q1-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q2-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q3-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=Q4-2
|
||||
Added Pin To Net: NetName=NetQ1_1 Pin=R5-1
|
||||
Added Pin To Net: NetName=NetQ1_1 Pin=R6-1
|
||||
Added Pin To Net: NetName=NetQ2_1 Pin=R7-2
|
||||
Added Pin To Net: NetName=NetQ2_1 Pin=R8-2
|
||||
Added Pin To Net: NetName=NetQ3_1 Pin=R9-1
|
||||
Added Pin To Net: NetName=NetQ3_1 Pin=R10-1
|
||||
Added Pin To Net: NetName=NetQ4_1 Pin=R11-2
|
||||
Added Pin To Net: NetName=NetQ4_1 Pin=R12-1
|
||||
Added Pin To Net: NetName=NetQ1_3 Pin=Q1-3
|
||||
Added Pin To Net: NetName=NetQ1_3 Pin=U3-6
|
||||
Added Net: Name=NetQ1_3
|
||||
Added Pin To Net: NetName=NetQ2_3 Pin=Q2-3
|
||||
Added Pin To Net: NetName=NetQ2_3 Pin=U3-8
|
||||
Added Net: Name=NetQ2_3
|
||||
Added Pin To Net: NetName=NetQ3_3 Pin=Q3-3
|
||||
Added Pin To Net: NetName=NetQ3_3 Pin=U3-9
|
||||
Added Net: Name=NetQ3_3
|
||||
Added Pin To Net: NetName=NetQ4_3 Pin=Q4-3
|
||||
Added Pin To Net: NetName=NetQ4_3 Pin=U3-12
|
||||
Added Net: Name=NetQ4_3
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,115 @@
|
||||
Removed Pin From Net: NetName=GND1 Pin=C12-1
|
||||
Removed Pin From Net: NetName=GND1 Pin=C14-1
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=C14-2
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=R3-1
|
||||
Removed Pin From Net: NetName=GND1 Pin=R4-2
|
||||
Removed Pin From Net: NetName=LED A Pin=R13-1
|
||||
Removed Pin From Net: NetName=LED B Pin=R14-1
|
||||
Removed Pin From Net: NetName=LED C Pin=R15-1
|
||||
Removed Pin From Net: NetName=LED D Pin=R16-1
|
||||
Removed Pin From Net: NetName=LED E Pin=R17-1
|
||||
Removed Pin From Net: NetName=LED F Pin=R18-1
|
||||
Removed Pin From Net: NetName=LED G Pin=R19-1
|
||||
Removed Pin From Net: NetName=LED DP Pin=R20-1
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R3
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R4
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R13
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R14
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R15
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R16
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R17
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R18
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R19
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R20
|
||||
Change Component Footprint: Designator=C12 Old Footprint=RAD-0.3 New Footprint=6-0805_N
|
||||
Change Component Footprint: Designator=C13 Old Footprint=RAD-0.3 New Footprint=6-0805_N
|
||||
Change Component Footprint: Designator=C14 Old Footprint=RAD-0.3 New Footprint=6-0805_N
|
||||
Change Component Designator: OldDesignator=U3 NewDesignator=U5
|
||||
Change component parameters: Designator = "C12"; Footprint = "6-0805_N"; UniqueID = "\SLGBJKAR"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "0.22<EFBFBD><EFBFBD>F"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\PWVEDBTD"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "22<32><32>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C15(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1<><31>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C16(6-0805_N)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1<><31>F"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=U2(LM340)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Component: Designator=U3(AMS1117)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=C16-2
|
||||
Added Pin To Net: NetName=NetC12_2 Pin=U2-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=U3-2
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=U3-4
|
||||
Added Pin To Net: NetName=+5 Pin=C13-2
|
||||
Added Pin To Net: NetName=+5 Pin=C14-2
|
||||
Added Pin To Net: NetName=+5 Pin=C15-2
|
||||
Added Pin To Net: NetName=+5 Pin=U2-3
|
||||
Added Pin To Net: NetName=+5 Pin=U3-3
|
||||
Added Net: Name=+5
|
||||
Added Pin To Net: NetName=DP Pin=U5-3
|
||||
Added Net: Name=DP
|
||||
Added Pin To Net: NetName=GND Pin=C12-1
|
||||
Added Pin To Net: NetName=GND Pin=C13-1
|
||||
Added Pin To Net: NetName=GND Pin=C14-1
|
||||
Added Pin To Net: NetName=GND Pin=C15-1
|
||||
Added Pin To Net: NetName=GND Pin=C16-1
|
||||
Added Pin To Net: NetName=GND Pin=U2-2
|
||||
Added Pin To Net: NetName=GND Pin=U2-4
|
||||
Added Pin To Net: NetName=GND Pin=U3-1
|
||||
Added Net: Name=GND
|
||||
Added Pin To Net: NetName=GR1 Pin=U5-6
|
||||
Added Net: Name=GR1
|
||||
Added Pin To Net: NetName=GR2 Pin=U5-8
|
||||
Added Net: Name=GR2
|
||||
Added Pin To Net: NetName=GR3 Pin=U5-9
|
||||
Added Net: Name=GR3
|
||||
Added Pin To Net: NetName=GR4 Pin=U5-12
|
||||
Added Net: Name=GR4
|
||||
Added Pin To Net: NetName=SG1 Pin=U5-11
|
||||
Added Net: Name=SG1
|
||||
Added Pin To Net: NetName=SG2 Pin=U5-7
|
||||
Added Net: Name=SG2
|
||||
Added Pin To Net: NetName=SG3 Pin=U5-4
|
||||
Added Net: Name=SG3
|
||||
Added Pin To Net: NetName=SG4 Pin=U5-2
|
||||
Added Net: Name=SG4
|
||||
Added Pin To Net: NetName=SG5 Pin=U5-1
|
||||
Added Net: Name=SG5
|
||||
Added Pin To Net: NetName=SG6 Pin=U5-10
|
||||
Added Net: Name=SG6
|
||||
Added Pin To Net: NetName=SG7 Pin=U5-5
|
||||
Added Net: Name=SG7
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C15 Cap
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C16 Cap
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U2
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U5
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,17 @@
|
||||
Added Component: Designator=U4(VK1650)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=GR1 Pin=U4-1
|
||||
Added Pin To Net: NetName=GND Pin=U4-4
|
||||
Added Pin To Net: NetName=GR2 Pin=U4-5
|
||||
Added Pin To Net: NetName=GR3 Pin=U4-6
|
||||
Added Pin To Net: NetName=GR4 Pin=U4-7
|
||||
Added Pin To Net: NetName=SG1 Pin=U4-8
|
||||
Added Pin To Net: NetName=SG2 Pin=U4-9
|
||||
Added Pin To Net: NetName=SG3 Pin=U4-11
|
||||
Added Pin To Net: NetName=SG4 Pin=U4-12
|
||||
Added Pin To Net: NetName=SG5 Pin=U4-13
|
||||
Added Pin To Net: NetName=SG6 Pin=U4-14
|
||||
Added Pin To Net: NetName=SG7 Pin=U4-15
|
||||
Added Pin To Net: NetName=DP Pin=U4-16
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U4
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,49 @@
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q1-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q2-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q3-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=Q4-2
|
||||
Removed Pin From Net: NetName=LED H1 Pin=R5-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=R6-2
|
||||
Removed Pin From Net: NetName=LED H2 Pin=R7-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=R8-1
|
||||
Removed Pin From Net: NetName=LED H3 Pin=R9-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=R10-2
|
||||
Removed Pin From Net: NetName=LED H4 Pin=R11-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=R12-2
|
||||
Removed Member From Class: ClassName=Sheet1 Member=Q1
|
||||
Removed Member From Class: ClassName=Sheet1 Member=Q2
|
||||
Removed Member From Class: ClassName=Sheet1 Member=Q3
|
||||
Removed Member From Class: ClassName=Sheet1 Member=Q4
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R5
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R6
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R7
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R8
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R9
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R10
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R11
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R12
|
||||
Added Component: Designator=C?(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C?(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=C?-1
|
||||
Added Pin To Net: NetName=GND Pin=C?-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=C?-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C?-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=U4-10
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C? Cap
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C? Cap
|
||||
@ -0,0 +1,6 @@
|
||||
Change Component Footprint: Designator=C? Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=C? Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Change Component Designator: OldDesignator=C? NewDesignator=C17
|
||||
Change Component Designator: OldDesignator=C? NewDesignator=C18
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C17 Cap
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,37 @@
|
||||
Added Component: Designator=C1(0402)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "nameAlias"; Value = "Value(F)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "C"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "C_0603_US"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R1(0402)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R2(0402)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCEDA_Lib"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "nameAlias"; Value = "Value(<28><>)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "R"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "R_0603_US"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND1 Pin=C1-1
|
||||
Added Pin To Net: NetName=EN Pin=C1-2
|
||||
Added Pin To Net: NetName=EN Pin=R1-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=R1-2
|
||||
Added Pin To Net: NetName=IO0 Pin=R2-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=R2-2
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C1 1u
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R1 10k
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R2 10k
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,7 @@
|
||||
Added Pin To Net: NetName=+3.3 Pin=C9-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C10-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C11-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-37
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-43
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-46
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,2 @@
|
||||
Change Component Footprint: Designator=P1 Old Footprint=HDR1X2 New Footprint=CNJMA2001WR-S-2P
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,2 @@
|
||||
Change Component Footprint: Designator=D? Old Footprint=SMC New Footprint=1N4001W
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,41 @@
|
||||
Added Component: Designator=R?(0402)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "10K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=SW1(SW)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "SHOU HAN"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C557591"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "S"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=SW2(SW)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "SHOU HAN"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C557591"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "S"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "TS342A2P-WZ"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+3.3 Pin=R?-2
|
||||
Added Pin To Net: NetName=IO0 Pin=SW1-1
|
||||
Added Pin To Net: NetName=GND1 Pin=SW1-2
|
||||
Added Pin To Net: NetName=GND Pin=SW2-2
|
||||
Added Pin To Net: NetName=SW Pin=R?-1
|
||||
Added Pin To Net: NetName=SW Pin=SW2-1
|
||||
Added Pin To Net: NetName=SW Pin=U1-24
|
||||
Added Net: Name=SW
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R? Res1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component SW1 TS342A2P-WZ
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component SW2 TS342A2P-WZ
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,7 @@
|
||||
Added Pin To Net: NetName=CLK Pin=U1-14
|
||||
Added Pin To Net: NetName=CLK Pin=U4-2
|
||||
Added Net: Name=CLK
|
||||
Added Pin To Net: NetName=DAT Pin=U1-15
|
||||
Added Pin To Net: NetName=DAT Pin=U4-3
|
||||
Added Net: Name=DAT
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,14 @@
|
||||
Added Pin To Net: NetName=GND1 Pin=C12-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C13-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C14-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C15-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C16-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C17-1
|
||||
Added Pin To Net: NetName=GND1 Pin=C18-1
|
||||
Added Pin To Net: NetName=GND1 Pin=SW2-2
|
||||
Added Pin To Net: NetName=GND1 Pin=U2-2
|
||||
Added Pin To Net: NetName=GND1 Pin=U2-4
|
||||
Added Pin To Net: NetName=GND1 Pin=U3-1
|
||||
Added Pin To Net: NetName=GND1 Pin=U4-4
|
||||
Change Net Name : Old Net Name=GND1 New Net Name=GND
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,58 @@
|
||||
Removed Pin From Net: NetName=GND Pin=C14-1
|
||||
Removed Pin From Net: NetName=+5 Pin=C14-2
|
||||
Removed Pin From Net: NetName=GND Pin=C15-1
|
||||
Removed Pin From Net: NetName=+5 Pin=C15-2
|
||||
Removed Pin From Net: NetName=GND Pin=C16-1
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=C16-2
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=D?-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=D?-2
|
||||
Removed Pin From Net: NetName=GND Pin=U3-1
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=U3-2
|
||||
Removed Pin From Net: NetName=+5 Pin=U3-3
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=U3-4
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C14
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C15
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C16
|
||||
Removed Member From Class: ClassName=Sheet1 Member=U3
|
||||
Change Component Designator: OldDesignator=D? NewDesignator=D1
|
||||
Added Component: Designator=C?(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=D2(1N4001W)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "Code_JEDEC"; Value = "DO-214-AB"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "DO-214-AB/SMC; 2 C-Bend Leads; Body 7.9 x 5.9 mm, inc. leads (LxW)"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "SMC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageVersion"; Value = "Sep-1996"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R?(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=C?-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=C?-2
|
||||
Added Pin To Net: NetName=+5 Pin=D1-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=D2-2
|
||||
Added Pin To Net: NetName=+5 Pin=R?-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=R?-2
|
||||
Added Pin To Net: NetName=NetD1_2 Pin=D1-2
|
||||
Added Pin To Net: NetName=NetD1_2 Pin=D2-1
|
||||
Added Net: Name=NetD1_2
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C? Cap
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component D2 Diode
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R? Res1
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,33 @@
|
||||
Added Component: Designator=U1(esp32-pico-d4)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-3
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-4
|
||||
Added Pin To Net: NetName=EN Pin=U1-9
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=U1-10
|
||||
Added Pin To Net: NetName=NetC6_2 Pin=U1-12
|
||||
Added Pin To Net: NetName=NetC7_2 Pin=U1-13
|
||||
Added Pin To Net: NetName=CLK Pin=U1-14
|
||||
Added Pin To Net: NetName=DAT Pin=U1-15
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-19
|
||||
Added Pin To Net: NetName=GND Pin=U1-22
|
||||
Added Pin To Net: NetName=IO0 Pin=U1-23
|
||||
Added Pin To Net: NetName=SW Pin=U1-24
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-37
|
||||
Added Pin To Net: NetName=U0RXD Pin=U1-40
|
||||
Added Pin To Net: NetName=U0TXD Pin=U1-41
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-43
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-46
|
||||
Added Pin To Net: NetName=GND Pin=U1-49
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R? Res1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,129 @@
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C2-1
|
||||
Removed Pin From Net: NetName=GND Pin=C2-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C5-2
|
||||
Removed Pin From Net: NetName=GND Pin=C6-1
|
||||
Removed Pin From Net: NetName=GND Pin=C7-1
|
||||
Removed Pin From Net: NetName=GND Pin=C9-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C9-2
|
||||
Removed Pin From Net: NetName=GND Pin=C10-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C10-2
|
||||
Removed Pin From Net: NetName=+5 Pin=C15-2
|
||||
Removed Pin From Net: NetName=GND Pin=C16-1
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=C16-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C17-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C18-2
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=D?-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=D?-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=U1-4
|
||||
Removed Pin From Net: NetName=GND Pin=U3-1
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=U3-2
|
||||
Removed Pin From Net: NetName=IO34 ADC Pin=U3-4
|
||||
Removed Pin From Net: NetName=+3.3 Pin=U4-10
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C2
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C6
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C7
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C9
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C10
|
||||
Removed Member From Class: ClassName=Sheet1 Member=D?
|
||||
Removed Member From Class: ClassName=Sheet1 Member=Y?
|
||||
Change Component Footprint: Designator=C14 Old Footprint=6-0805_N New Footprint=RAD-0.3
|
||||
Change Component Footprint: Designator=C15 Old Footprint=6-0805_N New Footprint=RAD-0.3
|
||||
Change Component Footprint: Designator=C16 Old Footprint=6-0805_N New Footprint=RAD-0.3
|
||||
Change Component Comment : Designator=U3 Old Comment= New Comment=TLV62568A
|
||||
Change Component Designator: OldDesignator=C17 NewDesignator=C18
|
||||
Change Component Designator: OldDesignator=C18 NewDesignator=C19
|
||||
Change Component Designator: OldDesignator=R? NewDesignator=R3
|
||||
Change Component Designator: OldDesignator=U4 NewDesignator=U5
|
||||
Change Component Designator: OldDesignator=U5 NewDesignator=U6
|
||||
Change component parameters: Designator = "C14"; Footprint = "RAD-0.3"; UniqueID = "\WMNPPNUP"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "4.7<EFBFBD><EFBFBD>F"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C15"; Footprint = "RAD-0.3"; UniqueID = "\NCFGQGJL"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "22<32><32>F"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C16"; Footprint = "RAD-0.3"; UniqueID = "\NYURCQQB"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "10pF"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=C17(RAD-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Radial Cap, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "RAD-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "100pF"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R4(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R5(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Component: Designator=R6(AXIAL-0.3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageDescription"; Value = "Axial Device, Thru-Hole; 2 Leads; 0.3 in Pin Spacing"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "PackageReference"; Value = "AXIAL-0.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Published"; Value = "8-Jun-2000"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Value"; Value = "1K"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=C17-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=C17-2
|
||||
Added Pin To Net: NetName=GND Pin=R5-1
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=R6-2
|
||||
Added Pin To Net: NetName=GND Pin=U3-2
|
||||
Change Net Name : Old Net Name=+3.3 New Net Name=+3.3-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C5-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C15-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C16-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C18-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C19-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=R4-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=R6-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=U1-4
|
||||
Added Pin To Net: NetName=+3.3 Pin=U5-10
|
||||
Added Net: Name=+3.3
|
||||
Added Pin To Net: NetName=NetC16_1 Pin=C16-1
|
||||
Added Pin To Net: NetName=NetC16_1 Pin=R4-1
|
||||
Added Pin To Net: NetName=NetC16_1 Pin=R5-2
|
||||
Added Pin To Net: NetName=NetC16_1 Pin=U3-1
|
||||
Added Net: Name=NetC16_1
|
||||
Added Pin To Net: NetName=NetPL?_1 Pin=U3-4
|
||||
Added Net: Name=NetPL?_1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C19 Cap
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R4 Res1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R5 Res1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component R6 Res1
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U6
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,2 @@
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component C12 Cap
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,5 @@
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C5-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=U1-4
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=C5-2
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-4
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,30 @@
|
||||
Added Component: Designator=U1(esp32-pico-d4)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "BOM_JLCPCB Part Class"; Value = "Extended Part"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer"; Value = "Espressif Systems"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Manufacturer Part"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "BOM_Supplier Part"; Value = "C193707"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Contributor"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Frequency"; Value = "-"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spicePre"; Value = "U"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "spiceSymbolName"; Value = "ESP32-PICO-D4"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-1
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-3
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-4
|
||||
Added Pin To Net: NetName=EN Pin=U1-9
|
||||
Added Pin To Net: NetName=IO34 ADC Pin=U1-10
|
||||
Added Pin To Net: NetName=CLK Pin=U1-14
|
||||
Added Pin To Net: NetName=DAT Pin=U1-15
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-19
|
||||
Added Pin To Net: NetName=GND Pin=U1-22
|
||||
Added Pin To Net: NetName=IO0 Pin=U1-23
|
||||
Added Pin To Net: NetName=SW Pin=U1-24
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-37
|
||||
Added Pin To Net: NetName=U0RXD Pin=U1-40
|
||||
Added Pin To Net: NetName=U0TXD Pin=U1-41
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-43
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U1-46
|
||||
Added Pin To Net: NetName=GND Pin=U1-49
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U1 ESP32-PICO-D4
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,16 @@
|
||||
Change Component Footprint: Designator=R4 Old Footprint=AXIAL-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=R5 Old Footprint=AXIAL-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=R6 Old Footprint=AXIAL-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=C14 Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=C15 Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=C16 Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Change Component Footprint: Designator=C17 Old Footprint=RAD-0.3 New Footprint=0603
|
||||
Added Component: Designator=U3(TLV62568A)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=NetC16_1 Pin=U3-1
|
||||
Added Pin To Net: NetName=GND Pin=U3-2
|
||||
Added Pin To Net: NetName=+5 Pin=U3-3
|
||||
Added Pin To Net: NetName=NetPL?_1 Pin=U3-4
|
||||
Added Pin To Net: NetName=+5 Pin=U3-5
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U3 TLV62568A
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,6 @@
|
||||
Added Component: Designator=PL?(XAL4020-102ME)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=NetPL?_1 Pin=PL?-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=PL?-2
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component PL? 2.2<EFBFBD><EFBFBD>H
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,8 @@
|
||||
Added Component: Designator=U4(MAX40200AUK+T)
|
||||
Add component. Clean all parameters for all variants
|
||||
Added Pin To Net: NetName=+3.3 Pin=U4-1
|
||||
Added Pin To Net: NetName=GND Pin=U4-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=U4-3
|
||||
Added Pin To Net: NetName=+3.3-2 Pin=U4-5
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U4 MAX40200AUK+T
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,10 @@
|
||||
Added Component: Designator=P2(HDR1X3)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=U0TXD Pin=P2-1
|
||||
Added Pin To Net: NetName=U0RXD Pin=P2-2
|
||||
Added Pin To Net: NetName=GND Pin=P2-3
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component P2 DEBUG
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,63 @@
|
||||
Removed Pin From Net: NetName=GND Pin=C14-1
|
||||
Removed Pin From Net: NetName=+5 Pin=C14-2
|
||||
Removed Pin From Net: NetName=GND Pin=C15-1
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C15-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=C16-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=PL?-2
|
||||
Removed Pin From Net: NetName=+3.3 Pin=R4-2
|
||||
Removed Pin From Net: NetName=GND Pin=R5-1
|
||||
Removed Pin From Net: NetName=GND Pin=U3-2
|
||||
Removed Pin From Net: NetName=+5 Pin=U3-3
|
||||
Removed Pin From Net: NetName=+5 Pin=U3-5
|
||||
Removed Member From Class: ClassName=Sheet1 Member=C16
|
||||
Removed Member From Class: ClassName=Sheet1 Member=PL?
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R4
|
||||
Removed Member From Class: ClassName=Sheet1 Member=R5
|
||||
Removed Member From Class: ClassName=Sheet1 Member=U3
|
||||
Change Component Footprint: Designator=C14 Old Footprint=0603 New Footprint=6-0805_N
|
||||
Change Component Footprint: Designator=C15 Old Footprint=0603 New Footprint=6-0805_N
|
||||
Change Component Comment : Designator=C14 Old Comment=Cap New Comment=10uF
|
||||
Change Component Comment : Designator=C15 Old Comment=Cap New Comment=22uF/25V
|
||||
Change component parameters: Designator = "C14"; Footprint = "6-0805_N"; UniqueID = "\QDBKEQLT"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Device"; Value = "10uF"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805X106K160NT"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Name"; Value = "10uF"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C0805"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C89189"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Symbol"; Value = "10uF"; VariantName = "[No Variations]"
|
||||
Change component parameters: Designator = "C15"; Footprint = "6-0805_N"; UniqueID = "\MJCTGQXY"
|
||||
Change component parameters. Clean all parameters for all variants
|
||||
Change component parameters (AddParameter): Name = "A_Ԫ<5F><D4AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; Value = "C45783"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "B_Ԫ<5F><D4AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; Value = "22uF (226) <20><>20% 25V"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "C_Ԫ<5F><D4AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; Value = "<22><>Ƭ<EFBFBD><C6AC><EFBFBD><EFBFBD>"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "D_Ԫ<5F><D4AA><EFBFBD>ͺ<EFBFBD>"; Value = "CL21A226MAQNNNE"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Device"; Value = "22uF/25V"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "E_<45><5F>װ<EFBFBD><D7B0><EFBFBD><EFBFBD>"; Value = "0805"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "F_<46><5F>ֵ(<28><>)/<2F><>ֵ(uF)"; Value = "22.0000000000"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "G_<47><5F>ѹ"; Value = "25.00"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "H_<48><5F><EFBFBD><EFBFBD>"; Value = "<22><>20%"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "I_<49><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; Value = "2"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "J_Ʒ<5F>Ʋ<EFBFBD><C6B2><EFBFBD>"; Value = "SAMSUNG(<28><><EFBFBD><EFBFBD>)"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Manufacturer"; Value = "FH"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Manufacturer Part"; Value = "0805F226M100NT"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Name"; Value = "22uF/25V"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Origin Footprint"; Value = "C 0805"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Supplier"; Value = "LCSC"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Supplier Part"; Value = "C67101"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Symbol"; Value = "22uF/25V"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "Value"; Value = "22uF/25V"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "<22><><EFBFBD><EFBFBD>/Ԫ<><D4AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"; Value = "0.134"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "ԭ<><D4AD>"; Value = "SZLY"; VariantName = "[No Variations]"
|
||||
Change component parameters (AddParameter): Name = "<22><>ע"; Value = "<22><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƬԪ<C6AC><D4AA><EFBFBD><EFBFBD>"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=+5 Pin=C14-1
|
||||
Added Pin To Net: NetName=GND Pin=C14-2
|
||||
Added Pin To Net: NetName=+3.3 Pin=C15-1
|
||||
Added Pin To Net: NetName=GND Pin=C15-2
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,18 @@
|
||||
Added Component: Designator=U?(1117)
|
||||
Add component. Clean all parameters for all variants
|
||||
Add component (AddParameter): Name = "Add into BOM"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Convert to PCB"; Value = "yes"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Device"; Value = "AMS117"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "link"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Manufacturer"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Manufacturer Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Name"; Value = "AMS117"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Origin Footprint"; Value = "AMS117-3.3"; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Supplier"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Supplier Part"; Value = ""; VariantName = "[No Variations]"
|
||||
Add component (AddParameter): Name = "Symbol"; Value = "AMS117"; VariantName = "[No Variations]"
|
||||
Added Pin To Net: NetName=GND Pin=U?-1
|
||||
Added Pin To Net: NetName=+3.3 Pin=U?-2
|
||||
Added Pin To Net: NetName=+5 Pin=U?-3
|
||||
Added Member To Class: ClassName=Sheet1 Member=Component U? AMS117
|
||||
Added Room: Name=Sheet1
|
||||
@ -0,0 +1,270 @@
|
||||
Protel Design System Design Rule Check
|
||||
PCB File : C:\Users\hu123456\Desktop\ʹ<><CAB9>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>\PCB1.PcbDoc
|
||||
Date : 2022/6/30
|
||||
Time : 13:25:17
|
||||
|
||||
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Un-Routed Net Constraint ( (All) )
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad C1-2(147.677mm,60.3mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-1(146.677mm,60.3mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C11-1(141.275mm,50.436mm) on Top Layer And Pad C11-2(141.275mm,49.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.211mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Pad R1-1(147.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.211mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.11mm < 0.254mm) Between Pad C1-2(147.677mm,60.3mm) on Top Layer And Via (147.93mm,59.487mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.11mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.209mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.209mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.166mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.166mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.236mm < 0.254mm) Between Pad C18-2(140.64mm,51.991mm) on Bottom Layer And Pad C19-2(140.64mm,50.752mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.236mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C3-1(145.771mm,49.436mm) on Top Layer And Pad C3-2(145.771mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (151.613mm,58.649mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.156mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.182mm < 0.254mm) Between Pad C4-2(154.127mm,59.106mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.182mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C5-1(144.272mm,49.436mm) on Top Layer And Pad C5-2(144.272mm,50.436mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad C8-1(143.264mm,60.655mm) on Top Layer And Pad C8-2(144.264mm,60.655mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.241mm < 0.254mm) Between Pad P2-2(141.224mm,58.547mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.241mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.149mm < 0.254mm) Between Pad P2-3(141.224mm,61.087mm) on Bottom Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.149mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R1-1(147.694mm,61.214mm) on Top Layer And Pad R1-2(146.694mm,61.214mm) on Top Layer [Top Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Pad R2-2(150.343mm,50.995mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad R2-1(150.343mm,49.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.186mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.222mm < 0.254mm) Between Pad R2-2(150.343mm,50.995mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.222mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.197mm < 0.254mm) Between Pad R3-1(176.352mm,57.904mm) on Bottom Layer And Pad R3-2(176.352mm,56.904mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.197mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad R6-2(160.325mm,51.918mm) on Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.01mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.124mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (148.107mm,51.486mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.124mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.113mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.113mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.234mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Via (165.786mm,55.042mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.234mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.191mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.616mm,56.972mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.191mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.141mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.141mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.185mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Via (157.353mm,56.007mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.185mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-2(147.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-11(147.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-10(147.518mm,57.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-11(147.518mm,57.749mm) on Top Layer And Pad U1-12(147.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Pad U1-13(146.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.01mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Pad U1-14(146.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Pad U1-15(145.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.173mm < 0.254mm) Between Pad U1-14(146.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.173mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Pad U1-16(145.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-15(145.768mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Pad U1-17(144.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.176mm < 0.254mm) Between Pad U1-16(145.268mm,58.999mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.176mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-17(144.768mm,58.999mm) on Top Layer And Pad U1-18(144.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-18(144.268mm,58.999mm) on Top Layer And Pad U1-19(143.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-19(143.768mm,58.999mm) on Top Layer And Pad U1-20(143.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-2(147.518mm,53.249mm) on Top Layer And Pad U1-3(147.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-20(143.268mm,58.999mm) on Top Layer And Pad U1-21(142.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Pad U1-22(142.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.187mm < 0.254mm) Between Pad U1-21(142.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.187mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Pad U1-23(141.768mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.121mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.121mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Pad U1-24(141.268mm,58.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.186mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.186mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Pad U1-25(140.518mm,58.249mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Via (140.64mm,59.868mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Pad U1-26(140.518mm,57.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-26(140.518mm,57.749mm) on Top Layer And Pad U1-27(140.518mm,57.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-27(140.518mm,57.249mm) on Top Layer And Pad U1-28(140.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-28(140.518mm,56.749mm) on Top Layer And Pad U1-29(140.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-29(140.518mm,56.249mm) on Top Layer And Pad U1-30(140.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Pad U1-4(147.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-3(147.518mm,53.749mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-30(140.518mm,55.749mm) on Top Layer And Pad U1-31(140.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-31(140.518mm,55.249mm) on Top Layer And Pad U1-32(140.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-32(140.518mm,54.749mm) on Top Layer And Pad U1-33(140.518mm,54.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-33(140.518mm,54.249mm) on Top Layer And Pad U1-34(140.518mm,53.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-34(140.518mm,53.749mm) on Top Layer And Pad U1-35(140.518mm,53.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-35(140.518mm,53.249mm) on Top Layer And Pad U1-36(140.518mm,52.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Pad U1-37(141.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.009mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Pad U1-38(141.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.225mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.225mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Pad U1-39(142.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.107mm < 0.254mm) Between Pad U1-38(141.768mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.107mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Pad U1-40(142.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.136mm < 0.254mm) Between Pad U1-39(142.268mm,51.999mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.136mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Pad U1-5(147.518mm,54.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.082mm < 0.254mm) Between Pad U1-4(147.518mm,54.249mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.082mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-40(142.768mm,51.999mm) on Top Layer And Pad U1-41(143.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-41(143.268mm,51.999mm) on Top Layer And Pad U1-42(143.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-42(143.768mm,51.999mm) on Top Layer And Pad U1-43(144.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-43(144.268mm,51.999mm) on Top Layer And Pad U1-44(144.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-44(144.768mm,51.999mm) on Top Layer And Pad U1-45(145.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-45(145.268mm,51.999mm) on Top Layer And Pad U1-46(145.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Pad U1-47(146.268mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.081mm < 0.254mm) Between Pad U1-46(145.768mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.081mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Pad U1-48(146.768mm,51.999mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.088mm < 0.254mm) Between Pad U1-47(146.268mm,51.999mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.088mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.091mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (141.859mm,52.959mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.091mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.087mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.771mm,58.039mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.087mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (145.948mm,52.934mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.112mm < 0.254mm) Between Pad U1-49(144.018mm,55.499mm) on Top Layer And Via (146.583mm,54mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.112mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-5(147.518mm,54.749mm) on Top Layer And Pad U1-6(147.518mm,55.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-6(147.518mm,55.249mm) on Top Layer And Pad U1-7(147.518mm,55.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-7(147.518mm,55.749mm) on Top Layer And Pad U1-8(147.518mm,56.249mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.017mm < 0.254mm) Between Pad U1-8(147.518mm,56.249mm) on Top Layer And Pad U1-9(147.518mm,56.749mm) on Top Layer [Top Solder] Mask Sliver [0.017mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.143mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Via (171.45mm,52.984mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.143mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Pad U4-2(164.367mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-1(163.417mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.215mm < 0.254mm) Between Pad U4-2(164.367mm,53.726mm) on Bottom Layer And Pad U4-3(165.317mm,53.726mm) on Bottom Layer [Bottom Solder] Mask Sliver [0.215mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.231mm < 0.254mm) Between Pad U4-3(165.317mm,53.726mm) on Bottom Layer And Via (164.367mm,53.726mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.231mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.195mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Via (142.268mm,59.973mm) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [0.195mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Via (166.827mm,52.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (148.107mm,51.486mm) from Top Layer to Bottom Layer And Via (148.742mm,50.876mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.156mm < 0.254mm) Between Via (148.742mm,50.876mm) from Top Layer to Bottom Layer And Via (149.454mm,50.394mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.156mm] / [Bottom Solder] Mask Sliver [0.156mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.162mm < 0.254mm) Between Via (156.616mm,56.972mm) from Top Layer to Bottom Layer And Via (156.667mm,57.836mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.162mm] / [Bottom Solder] Mask Sliver [0.162mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.217mm < 0.254mm) Between Via (157.353mm,56.007mm) from Top Layer to Bottom Layer And Via (158.064mm,55.423mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.217mm] / [Bottom Solder] Mask Sliver [0.217mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.177mm < 0.254mm) Between Via (158.818mm,52.9mm) from Top Layer to Bottom Layer And Via (159.461mm,52.299mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.177mm] / [Bottom Solder] Mask Sliver [0.177mm]
|
||||
Violation between Minimum Solder Mask Sliver Constraint: (0.253mm < 0.254mm) Between Via (166.827mm,52.248mm) from Top Layer to Bottom Layer And Via (167.005mm,53.188mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.253mm] / [Bottom Solder] Mask Sliver [0.253mm]
|
||||
Rule Violations :106
|
||||
|
||||
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (143.739mm,51.922mm) on Bottom Overlay And Pad U5-1(143.739mm,52.654mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.09mm < 0.254mm) Between Arc (148.158mm,52.749mm) on Top Overlay And Pad U1-1(147.518mm,52.749mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.09mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Arc (162.699mm,53.878mm) on Bottom Overlay And Pad U4-1(163.417mm,53.726mm) on Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C12-1(172.237mm,49.773mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C12-2(172.237mm,51.573mm) on Bottom Layer And Track (171.637mm,50.673mm)(172.837mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C13-1(169.596mm,49.773mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.164mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.164mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C13-2(169.596mm,51.573mm) on Bottom Layer And Track (168.996mm,50.673mm)(170.196mm,50.673mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C14-1(166.903mm,56.207mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C14-2(166.903mm,54.407mm) on Bottom Layer And Track (166.303mm,55.307mm)(167.503mm,55.307mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.2mm < 0.254mm) Between Pad C15-1(166.903mm,58.714mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.2mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Pad C15-2(166.903mm,60.514mm) on Bottom Layer And Track (166.303mm,59.614mm)(167.503mm,59.614mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.216mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.228mm < 0.254mm) Between Pad C18-1(140.64mm,53.391mm) on Bottom Layer And Text "TX" (142.392mm,54.356mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.228mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.249mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Text "+" (175.336mm,51.206mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.249mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-1(176.022mm,52.934mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.169mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,53.515mm)(176.787mm,53.602mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.169mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.104mm < 0.254mm) Between Pad P1-2(176.022mm,54.183mm) on Bottom Layer And Track (176.787mm,54.764mm)(176.787mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.104mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (176.787mm,51.425mm)(180.487mm,51.425mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.007mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.018mm < 0.254mm) Between Pad P1-3(179.111mm,50.091mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.018mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (176.787mm,55.703mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.112mm < 0.254mm) Between Pad P1-4(179.112mm,57.033mm) on Bottom Layer And Track (180.487mm,51.436mm)(180.487mm,55.703mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.112mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,49.345mm)(148.163mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-1(148.122mm,50.229mm) on Bottom Layer And Track (148.163mm,51.112mm)(148.163mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,49.345mm)(144.011mm,48.652mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW1-2(144.052mm,50.229mm) on Bottom Layer And Track (144.011mm,51.112mm)(144.011mm,51.805mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,58.685mm)(175.687mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-1(175.728mm,60.261mm) on Bottom Layer And Track (175.687mm,61.838mm)(175.687mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,58.685mm)(179.839mm,59.378mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.127mm < 0.254mm) Between Pad SW2-2(179.798mm,60.261mm) on Bottom Layer And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.127mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-1(164.166mm,60.745mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-2(164.166mm,58.445mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-3(164.166mm,56.145mm) on Bottom Layer And Track (162.702mm,55.119mm)(162.702mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (156.54mm,59.106mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.022mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (157.175mm,51.994mm)(157.175mm,59.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.022mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U?-4(158.496mm,58.445mm) on Bottom Layer And Track (159.96mm,55.119mm)(159.96mm,61.772mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.211mm < 0.254mm) Between Pad U1-1(147.518mm,52.749mm) on Top Layer And Track (147.594mm,51.923mm)(147.594mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.211mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-12(147.518mm,58.249mm) on Top Layer And Track (147.594mm,58.58mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-13(146.768mm,58.999mm) on Top Layer And Track (147.098mm,59.075mm)(147.594mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-22(142.268mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.215mm < 0.254mm) Between Pad U1-23(141.768mm,58.999mm) on Top Layer And Text "U1" (140.132mm,59.741mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.215mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.21mm < 0.254mm) Between Pad U1-24(141.268mm,58.999mm) on Top Layer And Track (140.442mm,59.075mm)(140.938mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.21mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-25(140.518mm,58.249mm) on Top Layer And Track (140.442mm,58.58mm)(140.442mm,59.075mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-36(140.518mm,52.749mm) on Top Layer And Track (140.442mm,51.923mm)(140.442mm,52.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-37(141.268mm,51.999mm) on Top Layer And Track (140.442mm,51.923mm)(140.938mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.114mm < 0.254mm) Between Pad U1-48(146.768mm,51.999mm) on Top Layer And Track (147.098mm,51.923mm)(147.594mm,51.923mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.114mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-1(173.801mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-2(171.501mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.076mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Text "U4" (168.605mm,51.867mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.076mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-3(169.201mm,54.813mm) on Bottom Layer And Track (168.1mm,56.274mm)(174.902mm,56.274mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U2-4(171.501mm,60.528mm) on Bottom Layer And Track (168.1mm,59.067mm)(174.902mm,59.067mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.253mm < 0.254mm) Between Pad U4-4(165.317mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.253mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad U4-5(163.417mm,51.431mm) on Bottom Layer And Track (163.911mm,51.677mm)(164.822mm,51.677mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.152mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-1(143.739mm,52.654mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-10(149.484mm,60.274mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-11(149.484mm,59.004mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-12(149.484mm,57.734mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-13(149.484mm,56.464mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-14(149.484mm,55.194mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-15(149.484mm,53.924mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-16(149.484mm,52.654mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-2(143.739mm,53.924mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-3(143.739mm,55.194mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-4(143.739mm,56.464mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-5(143.739mm,57.734mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-6(143.739mm,59.004mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-7(143.739mm,60.274mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.234mm < 0.254mm) Between Pad U5-8(143.739mm,61.544mm) on Bottom Layer And Track (144.84mm,52.023mm)(144.84mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.234mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad U5-9(149.484mm,61.544mm) on Bottom Layer And Track (148.383mm,52.023mm)(148.383mm,62.175mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.247mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Track (151.486mm,50.597mm)(151.486mm,53.384mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,50.292mm) on Top Overlay And Via (151.486mm,50.597mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.196mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0.196mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Region (0 hole(s)) Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (150.038mm,61.544mm)(150.52mm,61.062mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.124mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Track (151.13mm,59.995mm)(151.917mm,59.995mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (150.038mm,61.544mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.225mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(151.384mm,60.789mm) on Top Overlay And Via (151.13mm,59.995mm) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-(174.244mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-(174.244mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-1(169.164mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-10(164.084mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-11(166.624mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-12(169.164mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-2(166.624mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-3(164.084mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-4(161.544mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-5(159.004mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.463mm,60.706mm)(177.292mm,60.706mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-6(156.464mm,60.789mm) on Top Layer And Track (148.59mm,59.69mm)(177.292mm,59.69mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-7(156.464mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-8(159.004mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.463mm,50.673mm)(177.292mm,50.673mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
|
||||
Violation between Silk To Solder Mask Clearance Constraint: (0.02mm < 0.254mm) Between Pad U6-9(161.544mm,50.292mm) on Top Layer And Track (148.59mm,51.689mm)(177.292mm,51.689mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.02mm]
|
||||
Rule Violations :110
|
||||
|
||||
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
|
||||
Violation between Silk To Silk Clearance Constraint: (0.195mm < 0.254mm) Between Text "+" (175.336mm,51.206mm) on Bottom Overlay And Track (176.787mm,51.425mm)(176.787mm,52.352mm) on Bottom Overlay Silk Text to Silk Clearance [0.195mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.07mm < 0.254mm) Between Text "DEBUG" (143.739mm,60.579mm) on Bottom Overlay And Track (142.494mm,54.737mm)(142.494mm,62.357mm) on Bottom Overlay Silk Text to Silk Clearance [0.07mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.129mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (175.687mm,61.838mm)(179.839mm,61.838mm) on Bottom Overlay Silk Text to Silk Clearance [0.129mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.14mm < 0.254mm) Between Text "RESET" (180.645mm,62.103mm) on Bottom Overlay And Track (179.839mm,61.838mm)(179.839mm,61.145mm) on Bottom Overlay Silk Text to Silk Clearance [0.14mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (0.206mm < 0.254mm) Between Text "TX" (142.392mm,54.356mm) on Bottom Overlay And Track (139.954mm,54.737mm)(142.494mm,54.737mm) on Bottom Overlay Silk Text to Silk Clearance [0.206mm]
|
||||
Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U4" (168.605mm,51.867mm) on Bottom Overlay And Track (165.918mm,51.677mm)(165.918mm,53.479mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
|
||||
Rule Violations :6
|
||||
|
||||
Processing Rule : Net Antennae (Tolerance=0mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
|
||||
Rule Violations :0
|
||||
|
||||
|
||||
Violations Detected : 222
|
||||
Waived Violations : 0
|
||||
Time Elapsed : 00:00:01
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
Output: Bill of Materials
|
||||
Type : BOM
|
||||
From : Variant [[No Variations]] of Project [PCB_Project2.PrjPCB]
|
||||
|
||||
|
||||
Files Generated : 0
|
||||
Documents Printed : 0
|
||||
|
||||
Finished Output Generation At 15:00:08 On 2022/5/7
|
||||
BIN
使用时间监测模块/SW.PcbLib
Normal file
BIN
使用时间监测模块/SW.PcbLib
Normal file
Binary file not shown.
BIN
使用时间监测模块/Sheet1.SchDoc
Normal file
BIN
使用时间监测模块/Sheet1.SchDoc
Normal file
Binary file not shown.
BIN
使用时间监测模块/TLV62568A.PcbLib
Normal file
BIN
使用时间监测模块/TLV62568A.PcbLib
Normal file
Binary file not shown.
BIN
使用时间监测模块/TLV62568A.SchLib
Normal file
BIN
使用时间监测模块/TLV62568A.SchLib
Normal file
Binary file not shown.
BIN
使用时间监测模块/XAL4020-102ME.PcbLib
Normal file
BIN
使用时间监测模块/XAL4020-102ME.PcbLib
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user